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KVM: SVM: Sync cr0 and cr3 to kvm state before nested handling
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
6bc31bdc
AP		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
49#define SVM_FEATURE_SVML (1 << 2)
50#define SVM_FEATURE_NRIP (1 << 3)
51#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 52
410e4d57
JR		 53#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56
24e09cbf
JR		 57#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58
6c8166a7
AK		 59static const u32 host_save_user_msrs[] = {
60#ifdef CONFIG_X86_64
61 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
62 MSR_FS_BASE,
63#endif
64 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
65};
66
67#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
68
69struct kvm_vcpu;
70
e6aa9abd
JR		 71struct nested_state {
72 struct vmcb *hsave;
73 u64 hsave_msr;
4a810181 74 u64 vm_cr_msr;
e6aa9abd
JR		 75 u64 vmcb;
76
77 /* These are the merged vectors */
78 u32 *msrpm;
79
80 /* gpa pointers to the real vectors */
81 u64 vmcb_msrpm;
ce2ac085 82 u64 vmcb_iopm;
aad42c64 83
cd3ff653
JR		 84 /* A VMEXIT is required but not yet emulated */
85 bool exit_required;
86
aad42c64
JR		 87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read;
89 u16 intercept_cr_write;
90 u16 intercept_dr_read;
91 u16 intercept_dr_write;
92 u32 intercept_exceptions;
93 u64 intercept;
94
e6aa9abd
JR		 95};
96
323c3d80
JR		 97#define MSRPM_OFFSETS 16
98static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
99
6c8166a7
AK		 100struct vcpu_svm {
101 struct kvm_vcpu vcpu;
102 struct vmcb *vmcb;
103 unsigned long vmcb_pa;
104 struct svm_cpu_data *svm_data;
105 uint64_t asid_generation;
106 uint64_t sysenter_esp;
107 uint64_t sysenter_eip;
108
109 u64 next_rip;
110
111 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
112 u64 host_gs_base;
6c8166a7
AK		 113
114 u32 *msrpm;
6c8166a7 115
e6aa9abd 116 struct nested_state nested;
6be7d306
JK		 117
118 bool nmi_singlestep;
66b7138f
JK		 119
120 unsigned int3_injected;
121 unsigned long int3_rip;
6c8166a7
AK		 122};
123
455716fa
JR		 124#define MSR_INVALID 0xffffffffU
125
ac72a9b7
JR		 126static struct svm_direct_access_msrs {
127 u32 index; /* Index of the MSR */
128 bool always; /* True if intercept is always on */
129} direct_access_msrs[] = {
130 { .index = MSR_K6_STAR, .always = true },
131 { .index = MSR_IA32_SYSENTER_CS, .always = true },
132#ifdef CONFIG_X86_64
133 { .index = MSR_GS_BASE, .always = true },
134 { .index = MSR_FS_BASE, .always = true },
135 { .index = MSR_KERNEL_GS_BASE, .always = true },
136 { .index = MSR_LSTAR, .always = true },
137 { .index = MSR_CSTAR, .always = true },
138 { .index = MSR_SYSCALL_MASK, .always = true },
139#endif
140 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
141 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
142 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
143 { .index = MSR_IA32_LASTINTTOIP, .always = false },
144 { .index = MSR_INVALID, .always = false },
145};
146
709ddebf
JR		 147/* enable NPT for AMD64 and X86 with PAE */
148#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149static bool npt_enabled = true;
150#else
e0231715 151static bool npt_enabled;
709ddebf 152#endif
6c7dac72
JR		 153static int npt = 1;
154
155module_param(npt, int, S_IRUGO);
e3da3acd 156
4b6e4dca 157static int nested = 1;
236de055
AG		 158module_param(nested, int, S_IRUGO);
159
44874f84 160static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 161static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 162
410e4d57 163static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 164static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 165static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 166static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
167 bool has_error_code, u32 error_code);
168
a2fa3e9f
GH		 169static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
170{
fb3f0f51 171 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 172}
173
3d6368ef
AG		 174static inline bool is_nested(struct vcpu_svm *svm)
175{
e6aa9abd 176 return svm->nested.vmcb;
3d6368ef
AG		 177}
178
2af9194d
JR		 179static inline void enable_gif(struct vcpu_svm *svm)
180{
181 svm->vcpu.arch.hflags |= HF_GIF_MASK;
182}
183
184static inline void disable_gif(struct vcpu_svm *svm)
185{
186 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
187}
188
189static inline bool gif_set(struct vcpu_svm *svm)
190{
191 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
192}
193
4866d5e3 194static unsigned long iopm_base;
6aa8b732
AK		 195
196struct kvm_ldttss_desc {
197 u16 limit0;
198 u16 base0;
e0231715
JR		 199 unsigned base1:8, type:5, dpl:2, p:1;
200 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 201 u32 base3;
202 u32 zero1;
203} __attribute__((packed));
204
205struct svm_cpu_data {
206 int cpu;
207
5008fdf5
AK		 208 u64 asid_generation;
209 u32 max_asid;
210 u32 next_asid;
6aa8b732
AK		 211 struct kvm_ldttss_desc *tss_desc;
212
213 struct page *save_area;
214};
215
216static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 217static uint32_t svm_features;
6aa8b732
AK		 218
219struct svm_init_data {
220 int cpu;
221 int r;
222};
223
224static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
225
9d8f549d 226#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 227#define MSRS_RANGE_SIZE 2048
228#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
229
455716fa
JR		 230static u32 svm_msrpm_offset(u32 msr)
231{
232 u32 offset;
233 int i;
234
235 for (i = 0; i < NUM_MSR_MAPS; i++) {
236 if (msr < msrpm_ranges[i] ||
237 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
238 continue;
239
240 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
241 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
242
243 /* Now we have the u8 offset - but need the u32 offset */
244 return offset / 4;
245 }
246
247 /* MSR not in any range */
248 return MSR_INVALID;
249}
250
6aa8b732
AK		 251#define MAX_INST_SIZE 15
252
80b7706e
JR		 253static inline u32 svm_has(u32 feat)
254{
255 return svm_features & feat;
256}
257
6aa8b732
AK		 258static inline void clgi(void)
259{
4ecac3fd 260 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 261}
262
263static inline void stgi(void)
264{
4ecac3fd 265 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 266}
267
268static inline void invlpga(unsigned long addr, u32 asid)
269{
e0231715 270 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 271}
272
6aa8b732
AK		 273static inline void force_new_asid(struct kvm_vcpu *vcpu)
274{
a2fa3e9f 275 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 276}
277
278static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
279{
280 force_new_asid(vcpu);
281}
282
283static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
284{
709ddebf 285 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 286 efer &= ~EFER_LME;
6aa8b732 287
9962d032 288 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 289 vcpu->arch.efer = efer;
6aa8b732
AK		 290}
291
6aa8b732
AK		 292static int is_external_interrupt(u32 info)
293{
294 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
295 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
296}
297
2809f5d2
GC		 298static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
299{
300 struct vcpu_svm *svm = to_svm(vcpu);
301 u32 ret = 0;
302
303 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 304 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 305 return ret & mask;
306}
307
308static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
309{
310 struct vcpu_svm *svm = to_svm(vcpu);
311
312 if (mask == 0)
313 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
314 else
315 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
316
317}
318
6aa8b732
AK		 319static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
320{
a2fa3e9f
GH		 321 struct vcpu_svm *svm = to_svm(vcpu);
322
6bc31bdc
AP		 323 if (svm->vmcb->control.next_rip != 0)
324 svm->next_rip = svm->vmcb->control.next_rip;
325
a2fa3e9f 326 if (!svm->next_rip) {
851ba692 327 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 328 EMULATE_DONE)
329 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 330 return;
331 }
5fdbf976
MT		 332 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
333 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
334 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 335
5fdbf976 336 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 337 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 338}
339
116a4752
JK		 340static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
341 bool has_error_code, u32 error_code)
342{
343 struct vcpu_svm *svm = to_svm(vcpu);
344
e0231715
JR		 345 /*
346 * If we are within a nested VM we'd better #VMEXIT and let the guest
347 * handle the exception
348 */
116a4752
JK		 349 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
350 return;
351
66b7138f
JK		 352 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
353 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
354
355 /*
356 * For guest debugging where we have to reinject #BP if some
357 * INT3 is guest-owned:
358 * Emulate nRIP by moving RIP forward. Will fail if injection
359 * raises a fault that is not intercepted. Still better than
360 * failing in all cases.
361 */
362 skip_emulated_instruction(&svm->vcpu);
363 rip = kvm_rip_read(&svm->vcpu);
364 svm->int3_rip = rip + svm->vmcb->save.cs.base;
365 svm->int3_injected = rip - old_rip;
366 }
367
116a4752
JK		 368 svm->vmcb->control.event_inj = nr
369 | SVM_EVTINJ_VALID
370 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
371 | SVM_EVTINJ_TYPE_EXEPT;
372 svm->vmcb->control.event_inj_err = error_code;
373}
374
6aa8b732
AK		 375static int has_svm(void)
376{
63d1142f 377 const char *msg;
6aa8b732 378
63d1142f 379 if (!cpu_has_svm(&msg)) {
ff81ff10 380 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 381 return 0;
382 }
383
6aa8b732
AK		 384 return 1;
385}
386
387static void svm_hardware_disable(void *garbage)
388{
2c8dceeb 389 cpu_svm_disable();
6aa8b732
AK		 390}
391
10474ae8 392static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 393{
394
0fe1e009 395 struct svm_cpu_data *sd;
6aa8b732 396 uint64_t efer;
89a27f4d 397 struct desc_ptr gdt_descr;
6aa8b732
AK		 398 struct desc_struct *gdt;
399 int me = raw_smp_processor_id();
400
10474ae8
AG		 401 rdmsrl(MSR_EFER, efer);
402 if (efer & EFER_SVME)
403 return -EBUSY;
404
6aa8b732 405 if (!has_svm()) {
e6732a5a
ZA		 406 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
407 me);
10474ae8 408 return -EINVAL;
6aa8b732 409 }
0fe1e009 410 sd = per_cpu(svm_data, me);
6aa8b732 411
0fe1e009 412 if (!sd) {
e6732a5a 413 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 414 me);
10474ae8 415 return -EINVAL;
6aa8b732
AK		 416 }
417
0fe1e009
TH		 418 sd->asid_generation = 1;
419 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
420 sd->next_asid = sd->max_asid + 1;
6aa8b732 421
d6ab1ed4 422 native_store_gdt(&gdt_descr);
89a27f4d 423 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 424 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 425
9962d032 426 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 427
d0316554 428 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 429
430 return 0;
6aa8b732
AK		 431}
432
0da1db75
JR		 433static void svm_cpu_uninit(int cpu)
434{
0fe1e009 435 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 436
0fe1e009 437 if (!sd)
0da1db75
JR		 438 return;
439
440 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 441 __free_page(sd->save_area);
442 kfree(sd);
0da1db75
JR		 443}
444
6aa8b732
AK		 445static int svm_cpu_init(int cpu)
446{
0fe1e009 447 struct svm_cpu_data *sd;
6aa8b732
AK		 448 int r;
449
0fe1e009
TH		 450 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
451 if (!sd)
6aa8b732 452 return -ENOMEM;
0fe1e009
TH		 453 sd->cpu = cpu;
454 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 455 r = -ENOMEM;
0fe1e009 456 if (!sd->save_area)
6aa8b732
AK		 457 goto err_1;
458
0fe1e009 459 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 460
461 return 0;
462
463err_1:
0fe1e009 464 kfree(sd);
6aa8b732
AK		 465 return r;
466
467}
468
ac72a9b7
JR		 469static bool valid_msr_intercept(u32 index)
470{
471 int i;
472
473 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
474 if (direct_access_msrs[i].index == index)
475 return true;
476
477 return false;
478}
479
bfc733a7
RR		 480static void set_msr_interception(u32 *msrpm, unsigned msr,
481 int read, int write)
6aa8b732 482{
455716fa
JR		 483 u8 bit_read, bit_write;
484 unsigned long tmp;
485 u32 offset;
6aa8b732 486
ac72a9b7
JR		 487 /*
488 * If this warning triggers extend the direct_access_msrs list at the
489 * beginning of the file
490 */
491 WARN_ON(!valid_msr_intercept(msr));
492
455716fa
JR		 493 offset = svm_msrpm_offset(msr);
494 bit_read = 2 * (msr & 0x0f);
495 bit_write = 2 * (msr & 0x0f) + 1;
496 tmp = msrpm[offset];
497
498 BUG_ON(offset == MSR_INVALID);
499
500 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
501 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
502
503 msrpm[offset] = tmp;
6aa8b732
AK		 504}
505
f65c229c
JR		 506static void svm_vcpu_init_msrpm(u32 *msrpm)
507{
ac72a9b7
JR		 508 int i;
509
f65c229c
JR		 510 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
511
ac72a9b7
JR		 512 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
513 if (!direct_access_msrs[i].always)
514 continue;
515
516 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
517 }
f65c229c
JR		 518}
519
323c3d80
JR		 520static void add_msr_offset(u32 offset)
521{
522 int i;
523
524 for (i = 0; i < MSRPM_OFFSETS; ++i) {
525
526 /* Offset already in list? */
527 if (msrpm_offsets[i] == offset)
528 return;
529
530 /* Slot used by another offset? */
531 if (msrpm_offsets[i] != MSR_INVALID)
532 continue;
533
534 /* Add offset to list */
535 msrpm_offsets[i] = offset;
536
537 return;
538 }
539
540 /*
541 * If this BUG triggers the msrpm_offsets table has an overflow. Just
542 * increase MSRPM_OFFSETS in this case.
543 */
544 BUG();
545}
546
547static void init_msrpm_offsets(void)
548{
549 int i;
550
551 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
552
553 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
554 u32 offset;
555
556 offset = svm_msrpm_offset(direct_access_msrs[i].index);
557 BUG_ON(offset == MSR_INVALID);
558
559 add_msr_offset(offset);
560 }
561}
562
24e09cbf
JR		 563static void svm_enable_lbrv(struct vcpu_svm *svm)
564{
565 u32 *msrpm = svm->msrpm;
566
567 svm->vmcb->control.lbr_ctl = 1;
568 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
569 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
570 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
571 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
572}
573
574static void svm_disable_lbrv(struct vcpu_svm *svm)
575{
576 u32 *msrpm = svm->msrpm;
577
578 svm->vmcb->control.lbr_ctl = 0;
579 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
580 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
581 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
582 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
583}
584
6aa8b732
AK		 585static __init int svm_hardware_setup(void)
586{
587 int cpu;
588 struct page *iopm_pages;
f65c229c 589 void *iopm_va;
6aa8b732
AK		 590 int r;
591
6aa8b732
AK		 592 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
593
594 if (!iopm_pages)
595 return -ENOMEM;
c8681339
AL		 596
597 iopm_va = page_address(iopm_pages);
598 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 599 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
600
323c3d80
JR		 601 init_msrpm_offsets();
602
50a37eb4
JR		 603 if (boot_cpu_has(X86_FEATURE_NX))
604 kvm_enable_efer_bits(EFER_NX);
605
1b2fd70c
AG		 606 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
607 kvm_enable_efer_bits(EFER_FFXSR);
608
236de055
AG		 609 if (nested) {
610 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
611 kvm_enable_efer_bits(EFER_SVME);
612 }
613
3230bb47 614 for_each_possible_cpu(cpu) {
6aa8b732
AK		 615 r = svm_cpu_init(cpu);
616 if (r)
f65c229c 617 goto err;
6aa8b732 618 }
33bd6a0b
JR		 619
620 svm_features = cpuid_edx(SVM_CPUID_FUNC);
621
e3da3acd
JR		 622 if (!svm_has(SVM_FEATURE_NPT))
623 npt_enabled = false;
624
6c7dac72
JR		 625 if (npt_enabled && !npt) {
626 printk(KERN_INFO "kvm: Nested Paging disabled\n");
627 npt_enabled = false;
628 }
629
18552672 630 if (npt_enabled) {
e3da3acd 631 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 632 kvm_enable_tdp();
5f4cb662
JR		 633 } else
634 kvm_disable_tdp();
e3da3acd 635
6aa8b732
AK		 636 return 0;
637
f65c229c 638err:
6aa8b732
AK		 639 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
640 iopm_base = 0;
641 return r;
642}
643
644static __exit void svm_hardware_unsetup(void)
645{
0da1db75
JR		 646 int cpu;
647
3230bb47 648 for_each_possible_cpu(cpu)
0da1db75
JR		 649 svm_cpu_uninit(cpu);
650
6aa8b732 651 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 652 iopm_base = 0;
6aa8b732
AK		 653}
654
655static void init_seg(struct vmcb_seg *seg)
656{
657 seg->selector = 0;
658 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 659 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 660 seg->limit = 0xffff;
661 seg->base = 0;
662}
663
664static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
665{
666 seg->selector = 0;
667 seg->attrib = SVM_SELECTOR_P_MASK | type;
668 seg->limit = 0xffff;
669 seg->base = 0;
670}
671
e6101a96 672static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 673{
e6101a96
JR		 674 struct vmcb_control_area *control = &svm->vmcb->control;
675 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 676
bff78274
AK		 677 svm->vcpu.fpu_active = 1;
678
e0231715 679 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 680 INTERCEPT_CR3_MASK |
649d6864 681 INTERCEPT_CR4_MASK;
6aa8b732 682
e0231715 683 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 684 INTERCEPT_CR3_MASK |
80a8119c
AK		 685 INTERCEPT_CR4_MASK |
686 INTERCEPT_CR8_MASK;
6aa8b732 687
e0231715 688 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 689 INTERCEPT_DR1_MASK |
690 INTERCEPT_DR2_MASK |
727f5a23
JK		 691 INTERCEPT_DR3_MASK |
692 INTERCEPT_DR4_MASK |
693 INTERCEPT_DR5_MASK |
694 INTERCEPT_DR6_MASK |
695 INTERCEPT_DR7_MASK;
6aa8b732 696
e0231715 697 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 698 INTERCEPT_DR1_MASK |
699 INTERCEPT_DR2_MASK |
700 INTERCEPT_DR3_MASK |
727f5a23 701 INTERCEPT_DR4_MASK |
6aa8b732 702 INTERCEPT_DR5_MASK |
727f5a23 703 INTERCEPT_DR6_MASK |
6aa8b732
AK		 704 INTERCEPT_DR7_MASK;
705
7aa81cc0 706 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 707 (1 << UD_VECTOR) |
708 (1 << MC_VECTOR);
6aa8b732
AK		 709
710
e0231715 711 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 712 (1ULL << INTERCEPT_NMI) |
0152527b 713 (1ULL << INTERCEPT_SMI) |
d225157b 714 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 715 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 716 (1ULL << INTERCEPT_INVD) |
6aa8b732 717 (1ULL << INTERCEPT_HLT) |
a7052897 718 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 719 (1ULL << INTERCEPT_INVLPGA) |
720 (1ULL << INTERCEPT_IOIO_PROT) |
721 (1ULL << INTERCEPT_MSR_PROT) |
722 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 723 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 724 (1ULL << INTERCEPT_VMRUN) |
725 (1ULL << INTERCEPT_VMMCALL) |
726 (1ULL << INTERCEPT_VMLOAD) |
727 (1ULL << INTERCEPT_VMSAVE) |
728 (1ULL << INTERCEPT_STGI) |
729 (1ULL << INTERCEPT_CLGI) |
916ce236 730 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 731 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 732 (1ULL << INTERCEPT_MONITOR) |
733 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 734
735 control->iopm_base_pa = iopm_base;
f65c229c 736 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 737 control->tsc_offset = 0;
6aa8b732
AK		 738 control->int_ctl = V_INTR_MASKING_MASK;
739
740 init_seg(&save->es);
741 init_seg(&save->ss);
742 init_seg(&save->ds);
743 init_seg(&save->fs);
744 init_seg(&save->gs);
745
746 save->cs.selector = 0xf000;
747 /* Executable/Readable Code Segment */
748 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
749 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
750 save->cs.limit = 0xffff;
d92899a0
AK		 751 /*
752 * cs.base should really be 0xffff0000, but vmx can't handle that, so
753 * be consistent with it.
754 *
755 * Replace when we have real mode working for vmx.
756 */
757 save->cs.base = 0xf0000;
6aa8b732
AK		 758
759 save->gdtr.limit = 0xffff;
760 save->idtr.limit = 0xffff;
761
762 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
763 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
764
9962d032 765 save->efer = EFER_SVME;
d77c26fc 766 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 767 save->dr7 = 0x400;
768 save->rflags = 2;
769 save->rip = 0x0000fff0;
5fdbf976 770 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 771
e0231715
JR		 772 /*
773 * This is the guest-visible cr0 value.
18fa000a 774 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 775 */
18fa000a
EH		 776 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
777 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
778
66aee91a 779 save->cr4 = X86_CR4_PAE;
6aa8b732 780 /* rdx = ?? */
709ddebf
JR		 781
782 if (npt_enabled) {
783 /* Setup VMCB for Nested Paging */
784 control->nested_ctl = 1;
a7052897
MT		 785 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
786 (1ULL << INTERCEPT_INVLPG));
709ddebf 787 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 788 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
789 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 790 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 791 save->cr3 = 0;
792 save->cr4 = 0;
793 }
a79d2f18 794 force_new_asid(&svm->vcpu);
1371d904 795
e6aa9abd 796 svm->nested.vmcb = 0;
2af9194d
JR		 797 svm->vcpu.arch.hflags = 0;
798
565d0998
ML		 799 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
800 control->pause_filter_count = 3000;
801 control->intercept |= (1ULL << INTERCEPT_PAUSE);
802 }
803
2af9194d 804 enable_gif(svm);
6aa8b732
AK		 805}
806
e00c8cf2 807static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 808{
809 struct vcpu_svm *svm = to_svm(vcpu);
810
e6101a96 811 init_vmcb(svm);
70433389 812
c5af89b6 813 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 814 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 815 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
816 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 817 }
5fdbf976
MT		 818 vcpu->arch.regs_avail = ~0;
819 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 820
821 return 0;
04d2cc77
AK		 822}
823
fb3f0f51 824static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 825{
a2fa3e9f 826 struct vcpu_svm *svm;
6aa8b732 827 struct page *page;
f65c229c 828 struct page *msrpm_pages;
b286d5d8 829 struct page *hsave_page;
3d6368ef 830 struct page *nested_msrpm_pages;
fb3f0f51 831 int err;
6aa8b732 832
c16f862d 833 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 834 if (!svm) {
835 err = -ENOMEM;
836 goto out;
837 }
838
839 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
840 if (err)
841 goto free_svm;
842
b7af4043 843 err = -ENOMEM;
6aa8b732 844 page = alloc_page(GFP_KERNEL);
b7af4043 845 if (!page)
fb3f0f51 846 goto uninit;
6aa8b732 847
f65c229c
JR		 848 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
849 if (!msrpm_pages)
b7af4043 850 goto free_page1;
3d6368ef
AG		 851
852 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
853 if (!nested_msrpm_pages)
b7af4043 854 goto free_page2;
f65c229c 855
b286d5d8
AG		 856 hsave_page = alloc_page(GFP_KERNEL);
857 if (!hsave_page)
b7af4043
TY		 858 goto free_page3;
859
e6aa9abd 860 svm->nested.hsave = page_address(hsave_page);
b286d5d8 861
b7af4043
TY		 862 svm->msrpm = page_address(msrpm_pages);
863 svm_vcpu_init_msrpm(svm->msrpm);
864
e6aa9abd 865 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 866 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 867
a2fa3e9f
GH		 868 svm->vmcb = page_address(page);
869 clear_page(svm->vmcb);
870 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
871 svm->asid_generation = 0;
e6101a96 872 init_vmcb(svm);
a2fa3e9f 873
fb3f0f51 874 fx_init(&svm->vcpu);
ad312c7c 875 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 876 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 877 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 878
fb3f0f51 879 return &svm->vcpu;
36241b8c 880
b7af4043
TY		 881free_page3:
882 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
883free_page2:
884 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
885free_page1:
886 __free_page(page);
fb3f0f51
RR		 887uninit:
888 kvm_vcpu_uninit(&svm->vcpu);
889free_svm:
a4770347 890 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 891out:
892 return ERR_PTR(err);
6aa8b732
AK		 893}
894
895static void svm_free_vcpu(struct kvm_vcpu *vcpu)
896{
a2fa3e9f
GH		 897 struct vcpu_svm *svm = to_svm(vcpu);
898
fb3f0f51 899 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 900 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 901 __free_page(virt_to_page(svm->nested.hsave));
902 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 903 kvm_vcpu_uninit(vcpu);
a4770347 904 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 905}
906
15ad7146 907static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 908{
a2fa3e9f 909 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 910 int i;
0cc5064d 911
0cc5064d 912 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 913 u64 delta;
0cc5064d 914
953899b6
JR		 915 if (check_tsc_unstable()) {
916 /*
917 * Make sure that the guest sees a monotonically
918 * increasing TSC.
919 */
920 delta = vcpu->arch.host_tsc - native_read_tsc();
921 svm->vmcb->control.tsc_offset += delta;
922 if (is_nested(svm))
923 svm->nested.hsave->control.tsc_offset += delta;
924 }
0cc5064d 925 vcpu->cpu = cpu;
2f599714 926 kvm_migrate_timers(vcpu);
4b656b12 927 svm->asid_generation = 0;
0cc5064d 928 }
94dfbdb3
AL		 929
930 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 931 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 932}
933
934static void svm_vcpu_put(struct kvm_vcpu *vcpu)
935{
a2fa3e9f 936 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 937 int i;
938
e1beb1d3 939 ++vcpu->stat.host_state_reload;
94dfbdb3 940 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 941 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 942
e935d48e 943 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 944}
945
6aa8b732
AK		 946static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
947{
a2fa3e9f 948 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 949}
950
951static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
952{
a2fa3e9f 953 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 954}
955
6de4f3ad
AK		 956static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
957{
958 switch (reg) {
959 case VCPU_EXREG_PDPTR:
960 BUG_ON(!npt_enabled);
961 load_pdptrs(vcpu, vcpu->arch.cr3);
962 break;
963 default:
964 BUG();
965 }
966}
967
f0b85051
AG		 968static void svm_set_vintr(struct vcpu_svm *svm)
969{
970 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
971}
972
973static void svm_clear_vintr(struct vcpu_svm *svm)
974{
975 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
976}
977
6aa8b732
AK		 978static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
979{
a2fa3e9f 980 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 981
982 switch (seg) {
983 case VCPU_SREG_CS: return &save->cs;
984 case VCPU_SREG_DS: return &save->ds;
985 case VCPU_SREG_ES: return &save->es;
986 case VCPU_SREG_FS: return &save->fs;
987 case VCPU_SREG_GS: return &save->gs;
988 case VCPU_SREG_SS: return &save->ss;
989 case VCPU_SREG_TR: return &save->tr;
990 case VCPU_SREG_LDTR: return &save->ldtr;
991 }
992 BUG();
8b6d44c7 993 return NULL;
6aa8b732
AK		 994}
995
996static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
997{
998 struct vmcb_seg *s = svm_seg(vcpu, seg);
999
1000 return s->base;
1001}
1002
1003static void svm_get_segment(struct kvm_vcpu *vcpu,
1004 struct kvm_segment *var, int seg)
1005{
1006 struct vmcb_seg *s = svm_seg(vcpu, seg);
1007
1008 var->base = s->base;
1009 var->limit = s->limit;
1010 var->selector = s->selector;
1011 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1012 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1013 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1014 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1015 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1016 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1017 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1018 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1019
e0231715
JR		 1020 /*
1021 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1022 * for cross vendor migration purposes by "not present"
1023 */
1024 var->unusable = !var->present || (var->type == 0);
1025
1fbdc7a5
AP		 1026 switch (seg) {
1027 case VCPU_SREG_CS:
1028 /*
1029 * SVM always stores 0 for the 'G' bit in the CS selector in
1030 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1031 * Intel's VMENTRY has a check on the 'G' bit.
1032 */
25022acc 1033 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1034 break;
1035 case VCPU_SREG_TR:
1036 /*
1037 * Work around a bug where the busy flag in the tr selector
1038 * isn't exposed
1039 */
c0d09828 1040 var->type |= 0x2;
1fbdc7a5
AP		 1041 break;
1042 case VCPU_SREG_DS:
1043 case VCPU_SREG_ES:
1044 case VCPU_SREG_FS:
1045 case VCPU_SREG_GS:
1046 /*
1047 * The accessed bit must always be set in the segment
1048 * descriptor cache, although it can be cleared in the
1049 * descriptor, the cached bit always remains at 1. Since
1050 * Intel has a check on this, set it here to support
1051 * cross-vendor migration.
1052 */
1053 if (!var->unusable)
1054 var->type |= 0x1;
1055 break;
b586eb02 1056 case VCPU_SREG_SS:
e0231715
JR		 1057 /*
1058 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1059 * descriptor is left as 1, although the whole segment has
1060 * been made unusable. Clear it here to pass an Intel VMX
1061 * entry check when cross vendor migrating.
1062 */
1063 if (var->unusable)
1064 var->db = 0;
1065 break;
1fbdc7a5 1066 }
6aa8b732
AK		 1067}
1068
2e4d2653
IE		 1069static int svm_get_cpl(struct kvm_vcpu *vcpu)
1070{
1071 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1072
1073 return save->cpl;
1074}
1075
89a27f4d 1076static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1077{
a2fa3e9f
GH		 1078 struct vcpu_svm *svm = to_svm(vcpu);
1079
89a27f4d
GN		 1080 dt->size = svm->vmcb->save.idtr.limit;
1081 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1082}
1083
89a27f4d 1084static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1085{
a2fa3e9f
GH		 1086 struct vcpu_svm *svm = to_svm(vcpu);
1087
89a27f4d
GN		 1088 svm->vmcb->save.idtr.limit = dt->size;
1089 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1090}
1091
89a27f4d 1092static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1093{
a2fa3e9f
GH		 1094 struct vcpu_svm *svm = to_svm(vcpu);
1095
89a27f4d
GN		 1096 dt->size = svm->vmcb->save.gdtr.limit;
1097 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1098}
1099
89a27f4d 1100static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1101{
a2fa3e9f
GH		 1102 struct vcpu_svm *svm = to_svm(vcpu);
1103
89a27f4d
GN		 1104 svm->vmcb->save.gdtr.limit = dt->size;
1105 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1106}
1107
e8467fda
AK		 1108static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1109{
1110}
1111
25c4c276 1112static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1113{
1114}
1115
d225157b
AK		 1116static void update_cr0_intercept(struct vcpu_svm *svm)
1117{
66a562f7 1118 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1119 ulong gcr0 = svm->vcpu.arch.cr0;
1120 u64 *hcr0 = &svm->vmcb->save.cr0;
1121
1122 if (!svm->vcpu.fpu_active)
1123 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1124 else
1125 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1126 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1127
1128
1129 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1130 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1131 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1132 if (is_nested(svm)) {
1133 struct vmcb *hsave = svm->nested.hsave;
1134
1135 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1136 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1137 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1138 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1139 }
d225157b
AK		 1140 } else {
1141 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1142 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1143 if (is_nested(svm)) {
1144 struct vmcb *hsave = svm->nested.hsave;
1145
1146 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1147 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1148 }
d225157b
AK		 1149 }
1150}
1151
6aa8b732
AK		 1152static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1153{
a2fa3e9f
GH		 1154 struct vcpu_svm *svm = to_svm(vcpu);
1155
7f5d8b56
JR		 1156 if (is_nested(svm)) {
1157 /*
1158 * We are here because we run in nested mode, the host kvm
1159 * intercepts cr0 writes but the l1 hypervisor does not.
1160 * But the L1 hypervisor may intercept selective cr0 writes.
1161 * This needs to be checked here.
1162 */
1163 unsigned long old, new;
1164
1165 /* Remove bits that would trigger a real cr0 write intercept */
1166 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1167 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1168
1169 if (old == new) {
1170 /* cr0 write with ts and mp unchanged */
1171 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1172 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1173 return;
1174 }
1175 }
1176
05b3e0c2 1177#ifdef CONFIG_X86_64
f6801dff 1178 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1179 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1180 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1181 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1182 }
1183
d77c26fc 1184 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1185 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1186 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1187 }
1188 }
1189#endif
ad312c7c 1190 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1191
1192 if (!npt_enabled)
1193 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1194
1195 if (!vcpu->fpu_active)
334df50a 1196 cr0 |= X86_CR0_TS;
709ddebf
JR		 1197 /*
1198 * re-enable caching here because the QEMU bios
1199 * does not do it - this results in some delay at
1200 * reboot
1201 */
1202 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1203 svm->vmcb->save.cr0 = cr0;
d225157b 1204 update_cr0_intercept(svm);
6aa8b732
AK		 1205}
1206
1207static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1208{
6394b649 1209 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1210 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1211
1212 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1213 force_new_asid(vcpu);
6394b649 1214
ec077263
JR		 1215 vcpu->arch.cr4 = cr4;
1216 if (!npt_enabled)
1217 cr4 |= X86_CR4_PAE;
6394b649 1218 cr4 |= host_cr4_mce;
ec077263 1219 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1220}
1221
1222static void svm_set_segment(struct kvm_vcpu *vcpu,
1223 struct kvm_segment *var, int seg)
1224{
a2fa3e9f 1225 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1226 struct vmcb_seg *s = svm_seg(vcpu, seg);
1227
1228 s->base = var->base;
1229 s->limit = var->limit;
1230 s->selector = var->selector;
1231 if (var->unusable)
1232 s->attrib = 0;
1233 else {
1234 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1235 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1236 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1237 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1238 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1239 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1240 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1241 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1242 }
1243 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1244 svm->vmcb->save.cpl
1245 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1246 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1247
1248}
1249
44c11430 1250static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1251{
d0bfb940
JK		 1252 struct vcpu_svm *svm = to_svm(vcpu);
1253
d0bfb940
JK		 1254 svm->vmcb->control.intercept_exceptions &=
1255 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1256
6be7d306 1257 if (svm->nmi_singlestep)
44c11430
GN		 1258 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1259
d0bfb940
JK		 1260 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1261 if (vcpu->guest_debug &
1262 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1263 svm->vmcb->control.intercept_exceptions |=
1264 1 << DB_VECTOR;
1265 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1266 svm->vmcb->control.intercept_exceptions |=
1267 1 << BP_VECTOR;
1268 } else
1269 vcpu->guest_debug = 0;
44c11430
GN		 1270}
1271
355be0b9 1272static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1273{
44c11430
GN		 1274 struct vcpu_svm *svm = to_svm(vcpu);
1275
ae675ef0
JK		 1276 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1277 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1278 else
1279 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1280
355be0b9 1281 update_db_intercept(vcpu);
6aa8b732
AK		 1282}
1283
1284static void load_host_msrs(struct kvm_vcpu *vcpu)
1285{
94dfbdb3 1286#ifdef CONFIG_X86_64
a2fa3e9f 1287 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1288#endif
6aa8b732
AK		 1289}
1290
1291static void save_host_msrs(struct kvm_vcpu *vcpu)
1292{
94dfbdb3 1293#ifdef CONFIG_X86_64
a2fa3e9f 1294 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1295#endif
6aa8b732
AK		 1296}
1297
0fe1e009 1298static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1299{
0fe1e009
TH		 1300 if (sd->next_asid > sd->max_asid) {
1301 ++sd->asid_generation;
1302 sd->next_asid = 1;
a2fa3e9f 1303 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1304 }
1305
0fe1e009
TH		 1306 svm->asid_generation = sd->asid_generation;
1307 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1308}
1309
020df079 1310static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1311{
42dbaa5a 1312 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1313
020df079 1314 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1315}
1316
851ba692 1317static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1318{
6aa8b732
AK		 1319 u64 fault_address;
1320 u32 error_code;
6aa8b732 1321
a2fa3e9f
GH		 1322 fault_address = svm->vmcb->control.exit_info_2;
1323 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1324
229456fc 1325 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1326 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1327 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1328 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1329}
1330
851ba692 1331static int db_interception(struct vcpu_svm *svm)
d0bfb940 1332{
851ba692
AK		 1333 struct kvm_run *kvm_run = svm->vcpu.run;
1334
d0bfb940 1335 if (!(svm->vcpu.guest_debug &
44c11430 1336 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1337 !svm->nmi_singlestep) {
d0bfb940
JK		 1338 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1339 return 1;
1340 }
44c11430 1341
6be7d306
JK		 1342 if (svm->nmi_singlestep) {
1343 svm->nmi_singlestep = false;
44c11430
GN		 1344 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1345 svm->vmcb->save.rflags &=
1346 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1347 update_db_intercept(&svm->vcpu);
1348 }
1349
1350 if (svm->vcpu.guest_debug &
e0231715 1351 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1352 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1353 kvm_run->debug.arch.pc =
1354 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1355 kvm_run->debug.arch.exception = DB_VECTOR;
1356 return 0;
1357 }
1358
1359 return 1;
d0bfb940
JK		 1360}
1361
851ba692 1362static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1363{
851ba692
AK		 1364 struct kvm_run *kvm_run = svm->vcpu.run;
1365
d0bfb940
JK		 1366 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1367 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1368 kvm_run->debug.arch.exception = BP_VECTOR;
1369 return 0;
1370}
1371
851ba692 1372static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1373{
1374 int er;
1375
851ba692 1376 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1377 if (er != EMULATE_DONE)
7ee5d940 1378 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1379 return 1;
1380}
1381
6b52d186 1382static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1383{
6b52d186 1384 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1385 u32 excp;
1386
1387 if (is_nested(svm)) {
1388 u32 h_excp, n_excp;
1389
1390 h_excp = svm->nested.hsave->control.intercept_exceptions;
1391 n_excp = svm->nested.intercept_exceptions;
1392 h_excp &= ~(1 << NM_VECTOR);
1393 excp = h_excp | n_excp;
1394 } else {
1395 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1396 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1397 }
1398
1399 svm->vmcb->control.intercept_exceptions = excp;
1400
e756fc62 1401 svm->vcpu.fpu_active = 1;
d225157b 1402 update_cr0_intercept(svm);
6b52d186 1403}
a2fa3e9f 1404
6b52d186
AK		 1405static int nm_interception(struct vcpu_svm *svm)
1406{
1407 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1408 return 1;
7807fa6c
AL		 1409}
1410
851ba692 1411static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1412{
1413 /*
1414 * On an #MC intercept the MCE handler is not called automatically in
1415 * the host. So do it by hand here.
1416 */
1417 asm volatile (
1418 "int $0x12\n");
1419 /* not sure if we ever come back to this point */
1420
1421 return 1;
1422}
1423
851ba692 1424static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1425{
851ba692
AK		 1426 struct kvm_run *kvm_run = svm->vcpu.run;
1427
46fe4ddd
JR		 1428 /*
1429 * VMCB is undefined after a SHUTDOWN intercept
1430 * so reinitialize it.
1431 */
a2fa3e9f 1432 clear_page(svm->vmcb);
e6101a96 1433 init_vmcb(svm);
46fe4ddd
JR		 1434
1435 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1436 return 0;
1437}
1438
851ba692 1439static int io_interception(struct vcpu_svm *svm)
6aa8b732 1440{
cf8f70bf 1441 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1442 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1443 int size, in, string;
039576c0 1444 unsigned port;
6aa8b732 1445
e756fc62 1446 ++svm->vcpu.stat.io_exits;
e70669ab 1447 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1448 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf
GN		 1449 if (string || in)
1450 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1451
039576c0
AK		 1452 port = io_info >> 16;
1453 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1454 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1455 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1456
1457 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1458}
1459
851ba692 1460static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1461{
1462 return 1;
1463}
1464
851ba692 1465static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1466{
1467 ++svm->vcpu.stat.irq_exits;
1468 return 1;
1469}
1470
851ba692 1471static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1472{
1473 return 1;
1474}
1475
851ba692 1476static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1477{
5fdbf976 1478 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1479 skip_emulated_instruction(&svm->vcpu);
1480 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1481}
1482
851ba692 1483static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1484{
5fdbf976 1485 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1486 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1487 kvm_emulate_hypercall(&svm->vcpu);
1488 return 1;
02e235bc
AK		 1489}
1490
c0725420
AG		 1491static int nested_svm_check_permissions(struct vcpu_svm *svm)
1492{
f6801dff 1493 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1494 || !is_paging(&svm->vcpu)) {
1495 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1496 return 1;
1497 }
1498
1499 if (svm->vmcb->save.cpl) {
1500 kvm_inject_gp(&svm->vcpu, 0);
1501 return 1;
1502 }
1503
1504 return 0;
1505}
1506
cf74a78b
AG		 1507static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1508 bool has_error_code, u32 error_code)
1509{
b8e88bc8
JR		 1510 int vmexit;
1511
0295ad7d
JR		 1512 if (!is_nested(svm))
1513 return 0;
cf74a78b 1514
0295ad7d
JR		 1515 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1516 svm->vmcb->control.exit_code_hi = 0;
1517 svm->vmcb->control.exit_info_1 = error_code;
1518 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1519
b8e88bc8
JR		 1520 vmexit = nested_svm_intercept(svm);
1521 if (vmexit == NESTED_EXIT_DONE)
1522 svm->nested.exit_required = true;
1523
1524 return vmexit;
cf74a78b
AG		 1525}
1526
8fe54654
JR		 1527/* This function returns true if it is save to enable the irq window */
1528static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1529{
26666957 1530 if (!is_nested(svm))
8fe54654 1531 return true;
cf74a78b 1532
26666957 1533 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1534 return true;
cf74a78b 1535
26666957 1536 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1537 return false;
cf74a78b 1538
197717d5
JR		 1539 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1540 svm->vmcb->control.exit_info_1 = 0;
1541 svm->vmcb->control.exit_info_2 = 0;
26666957 1542
cd3ff653
JR		 1543 if (svm->nested.intercept & 1ULL) {
1544 /*
1545 * The #vmexit can't be emulated here directly because this
1546 * code path runs with irqs and preemtion disabled. A
1547 * #vmexit emulation might sleep. Only signal request for
1548 * the #vmexit here.
1549 */
1550 svm->nested.exit_required = true;
236649de 1551 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1552 return false;
cf74a78b
AG		 1553 }
1554
8fe54654 1555 return true;
cf74a78b
AG		 1556}
1557
887f500c
JR		 1558/* This function returns true if it is save to enable the nmi window */
1559static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1560{
1561 if (!is_nested(svm))
1562 return true;
1563
1564 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1565 return true;
1566
1567 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1568 svm->nested.exit_required = true;
1569
1570 return false;
1571}
1572
7597f129 1573static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1574{
1575 struct page *page;
1576
6c3bd3d7
JR		 1577 might_sleep();
1578
34f80cfa 1579 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1580 if (is_error_page(page))
1581 goto error;
1582
7597f129
JR		 1583 *_page = page;
1584
1585 return kmap(page);
34f80cfa
JR		 1586
1587error:
1588 kvm_release_page_clean(page);
1589 kvm_inject_gp(&svm->vcpu, 0);
1590
1591 return NULL;
1592}
1593
7597f129 1594static void nested_svm_unmap(struct page *page)
34f80cfa 1595{
7597f129 1596 kunmap(page);
34f80cfa
JR		 1597 kvm_release_page_dirty(page);
1598}
1599
ce2ac085
JR		 1600static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1601{
1602 unsigned port;
1603 u8 val, bit;
1604 u64 gpa;
1605
1606 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1607 return NESTED_EXIT_HOST;
1608
1609 port = svm->vmcb->control.exit_info_1 >> 16;
1610 gpa = svm->nested.vmcb_iopm + (port / 8);
1611 bit = port % 8;
1612 val = 0;
1613
1614 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1615 val &= (1 << bit);
1616
1617 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1618}
1619
d2477826 1620static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1621{
0d6b3537
JR		 1622 u32 offset, msr, value;
1623 int write, mask;
4c2161ae 1624
3d62d9aa 1625 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1626 return NESTED_EXIT_HOST;
3d62d9aa 1627
0d6b3537
JR		 1628 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1629 offset = svm_msrpm_offset(msr);
1630 write = svm->vmcb->control.exit_info_1 & 1;
1631 mask = 1 << ((2 * (msr & 0xf)) + write);
4c2161ae 1632
0d6b3537
JR		 1633 if (offset == MSR_INVALID)
1634 return NESTED_EXIT_DONE;
3d62d9aa 1635
0d6b3537
JR		 1636 /* Offset is in 32 bit units but need in 8 bit units */
1637 offset *= 4;
1638
1639 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1640 return NESTED_EXIT_DONE;
1641
1642 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1643}
1644
410e4d57 1645static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1646{
cf74a78b 1647 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1648
410e4d57
JR		 1649 switch (exit_code) {
1650 case SVM_EXIT_INTR:
1651 case SVM_EXIT_NMI:
1652 return NESTED_EXIT_HOST;
410e4d57 1653 case SVM_EXIT_NPF:
e0231715 1654 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1655 if (npt_enabled)
1656 return NESTED_EXIT_HOST;
1657 break;
410e4d57 1658 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1659 /* When we're shadowing, trap PFs */
410e4d57
JR		 1660 if (!npt_enabled)
1661 return NESTED_EXIT_HOST;
1662 break;
66a562f7
JR		 1663 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1664 nm_interception(svm);
1665 break;
410e4d57
JR		 1666 default:
1667 break;
cf74a78b
AG		 1668 }
1669
410e4d57
JR		 1670 return NESTED_EXIT_CONTINUE;
1671}
1672
1673/*
1674 * If this function returns true, this #vmexit was already handled
1675 */
b8e88bc8 1676static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1677{
1678 u32 exit_code = svm->vmcb->control.exit_code;
1679 int vmexit = NESTED_EXIT_HOST;
1680
cf74a78b 1681 switch (exit_code) {
9c4e40b9 1682 case SVM_EXIT_MSR:
3d62d9aa 1683 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1684 break;
ce2ac085
JR		 1685 case SVM_EXIT_IOIO:
1686 vmexit = nested_svm_intercept_ioio(svm);
1687 break;
cf74a78b
AG		 1688 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1689 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1690 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1691 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1692 break;
1693 }
1694 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1695 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1696 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1697 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1698 break;
1699 }
1700 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1701 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1702 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1703 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1704 break;
1705 }
1706 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1707 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1708 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1709 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1710 break;
1711 }
1712 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1713 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1714 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1715 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1716 break;
1717 }
1718 default: {
1719 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1720 if (svm->nested.intercept & exit_bits)
410e4d57 1721 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1722 }
1723 }
1724
b8e88bc8
JR		 1725 return vmexit;
1726}
1727
1728static int nested_svm_exit_handled(struct vcpu_svm *svm)
1729{
1730 int vmexit;
1731
1732 vmexit = nested_svm_intercept(svm);
1733
1734 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1735 nested_svm_vmexit(svm);
9c4e40b9
JR		 1736
1737 return vmexit;
cf74a78b
AG		 1738}
1739
0460a979
JR		 1740static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1741{
1742 struct vmcb_control_area *dst = &dst_vmcb->control;
1743 struct vmcb_control_area *from = &from_vmcb->control;
1744
1745 dst->intercept_cr_read = from->intercept_cr_read;
1746 dst->intercept_cr_write = from->intercept_cr_write;
1747 dst->intercept_dr_read = from->intercept_dr_read;
1748 dst->intercept_dr_write = from->intercept_dr_write;
1749 dst->intercept_exceptions = from->intercept_exceptions;
1750 dst->intercept = from->intercept;
1751 dst->iopm_base_pa = from->iopm_base_pa;
1752 dst->msrpm_base_pa = from->msrpm_base_pa;
1753 dst->tsc_offset = from->tsc_offset;
1754 dst->asid = from->asid;
1755 dst->tlb_ctl = from->tlb_ctl;
1756 dst->int_ctl = from->int_ctl;
1757 dst->int_vector = from->int_vector;
1758 dst->int_state = from->int_state;
1759 dst->exit_code = from->exit_code;
1760 dst->exit_code_hi = from->exit_code_hi;
1761 dst->exit_info_1 = from->exit_info_1;
1762 dst->exit_info_2 = from->exit_info_2;
1763 dst->exit_int_info = from->exit_int_info;
1764 dst->exit_int_info_err = from->exit_int_info_err;
1765 dst->nested_ctl = from->nested_ctl;
1766 dst->event_inj = from->event_inj;
1767 dst->event_inj_err = from->event_inj_err;
1768 dst->nested_cr3 = from->nested_cr3;
1769 dst->lbr_ctl = from->lbr_ctl;
1770}
1771
34f80cfa 1772static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1773{
34f80cfa 1774 struct vmcb *nested_vmcb;
e6aa9abd 1775 struct vmcb *hsave = svm->nested.hsave;
33740e40 1776 struct vmcb *vmcb = svm->vmcb;
7597f129 1777 struct page *page;
cf74a78b 1778
17897f36
JR		 1779 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1780 vmcb->control.exit_info_1,
1781 vmcb->control.exit_info_2,
1782 vmcb->control.exit_int_info,
1783 vmcb->control.exit_int_info_err);
1784
7597f129 1785 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1786 if (!nested_vmcb)
1787 return 1;
1788
06fc7772
JR		 1789 /* Exit nested SVM mode */
1790 svm->nested.vmcb = 0;
1791
cf74a78b 1792 /* Give the current vmcb to the guest */
33740e40
JR		 1793 disable_gif(svm);
1794
1795 nested_vmcb->save.es = vmcb->save.es;
1796 nested_vmcb->save.cs = vmcb->save.cs;
1797 nested_vmcb->save.ss = vmcb->save.ss;
1798 nested_vmcb->save.ds = vmcb->save.ds;
1799 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1800 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1801 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1802 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1803 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1804 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1805 nested_vmcb->save.rflags = vmcb->save.rflags;
1806 nested_vmcb->save.rip = vmcb->save.rip;
1807 nested_vmcb->save.rsp = vmcb->save.rsp;
1808 nested_vmcb->save.rax = vmcb->save.rax;
1809 nested_vmcb->save.dr7 = vmcb->save.dr7;
1810 nested_vmcb->save.dr6 = vmcb->save.dr6;
1811 nested_vmcb->save.cpl = vmcb->save.cpl;
1812
1813 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1814 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1815 nested_vmcb->control.int_state = vmcb->control.int_state;
1816 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1817 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1818 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1819 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1820 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1821 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1822
1823 /*
1824 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1825 * to make sure that we do not lose injected events. So check event_inj
1826 * here and copy it to exit_int_info if it is valid.
1827 * Exit_int_info and event_inj can't be both valid because the case
1828 * below only happens on a VMRUN instruction intercept which has
1829 * no valid exit_int_info set.
1830 */
1831 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1832 struct vmcb_control_area *nc = &nested_vmcb->control;
1833
1834 nc->exit_int_info = vmcb->control.event_inj;
1835 nc->exit_int_info_err = vmcb->control.event_inj_err;
1836 }
1837
33740e40
JR		 1838 nested_vmcb->control.tlb_ctl = 0;
1839 nested_vmcb->control.event_inj = 0;
1840 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1841
1842 /* We always set V_INTR_MASKING and remember the old value in hflags */
1843 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1844 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1845
cf74a78b 1846 /* Restore the original control entries */
0460a979 1847 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1848
219b65dc
AG		 1849 kvm_clear_exception_queue(&svm->vcpu);
1850 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1851
1852 /* Restore selected save entries */
1853 svm->vmcb->save.es = hsave->save.es;
1854 svm->vmcb->save.cs = hsave->save.cs;
1855 svm->vmcb->save.ss = hsave->save.ss;
1856 svm->vmcb->save.ds = hsave->save.ds;
1857 svm->vmcb->save.gdtr = hsave->save.gdtr;
1858 svm->vmcb->save.idtr = hsave->save.idtr;
1859 svm->vmcb->save.rflags = hsave->save.rflags;
1860 svm_set_efer(&svm->vcpu, hsave->save.efer);
1861 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1862 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1863 if (npt_enabled) {
1864 svm->vmcb->save.cr3 = hsave->save.cr3;
1865 svm->vcpu.arch.cr3 = hsave->save.cr3;
1866 } else {
1867 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1868 }
1869 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1870 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1871 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1872 svm->vmcb->save.dr7 = 0;
1873 svm->vmcb->save.cpl = 0;
1874 svm->vmcb->control.exit_int_info = 0;
1875
7597f129 1876 nested_svm_unmap(page);
cf74a78b
AG		 1877
1878 kvm_mmu_reset_context(&svm->vcpu);
1879 kvm_mmu_load(&svm->vcpu);
1880
1881 return 0;
1882}
3d6368ef 1883
9738b2c9 1884static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1885{
323c3d80
JR		 1886 /*
1887 * This function merges the msr permission bitmaps of kvm and the
1888 * nested vmcb. It is omptimized in that it only merges the parts where
1889 * the kvm msr permission bitmap may contain zero bits
1890 */
3d6368ef 1891 int i;
9738b2c9 1892
323c3d80
JR		 1893 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1894 return true;
9738b2c9 1895
323c3d80
JR		 1896 for (i = 0; i < MSRPM_OFFSETS; i++) {
1897 u32 value, p;
1898 u64 offset;
9738b2c9 1899
323c3d80
JR		 1900 if (msrpm_offsets[i] == 0xffffffff)
1901 break;
3d6368ef 1902
0d6b3537
JR		 1903 p = msrpm_offsets[i];
1904 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 1905
1906 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1907 return false;
1908
1909 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1910 }
1911
1912 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 1913
1914 return true;
3d6368ef
AG		 1915}
1916
9738b2c9 1917static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1918{
9738b2c9 1919 struct vmcb *nested_vmcb;
e6aa9abd 1920 struct vmcb *hsave = svm->nested.hsave;
defbba56 1921 struct vmcb *vmcb = svm->vmcb;
7597f129 1922 struct page *page;
06fc7772
JR		 1923 u64 vmcb_gpa;
1924
1925 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1926
7597f129 1927 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1928 if (!nested_vmcb)
1929 return false;
1930
ecf1405d 1931 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 1932 nested_vmcb->save.rip,
1933 nested_vmcb->control.int_ctl,
1934 nested_vmcb->control.event_inj,
1935 nested_vmcb->control.nested_ctl);
1936
2e554e8d
JR		 1937 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1938 nested_vmcb->control.intercept_cr_write,
1939 nested_vmcb->control.intercept_exceptions,
1940 nested_vmcb->control.intercept);
1941
3d6368ef 1942 /* Clear internal status */
219b65dc
AG		 1943 kvm_clear_exception_queue(&svm->vcpu);
1944 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 1945
e0231715
JR		 1946 /*
1947 * Save the old vmcb, so we don't need to pick what we save, but can
1948 * restore everything when a VMEXIT occurs
1949 */
defbba56
JR		 1950 hsave->save.es = vmcb->save.es;
1951 hsave->save.cs = vmcb->save.cs;
1952 hsave->save.ss = vmcb->save.ss;
1953 hsave->save.ds = vmcb->save.ds;
1954 hsave->save.gdtr = vmcb->save.gdtr;
1955 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1956 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1957 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1958 hsave->save.cr4 = svm->vcpu.arch.cr4;
1959 hsave->save.rflags = vmcb->save.rflags;
1960 hsave->save.rip = svm->next_rip;
1961 hsave->save.rsp = vmcb->save.rsp;
1962 hsave->save.rax = vmcb->save.rax;
1963 if (npt_enabled)
1964 hsave->save.cr3 = vmcb->save.cr3;
1965 else
1966 hsave->save.cr3 = svm->vcpu.arch.cr3;
1967
0460a979 1968 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1969
1970 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1971 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1972 else
1973 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1974
1975 /* Load the nested guest state */
1976 svm->vmcb->save.es = nested_vmcb->save.es;
1977 svm->vmcb->save.cs = nested_vmcb->save.cs;
1978 svm->vmcb->save.ss = nested_vmcb->save.ss;
1979 svm->vmcb->save.ds = nested_vmcb->save.ds;
1980 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1981 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1982 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1983 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1984 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1985 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1986 if (npt_enabled) {
1987 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1988 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 1989 } else
3d6368ef 1990 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 1991
1992 /* Guest paging mode is active - reset mmu */
1993 kvm_mmu_reset_context(&svm->vcpu);
1994
defbba56 1995 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1996 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1997 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1998 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 1999
3d6368ef
AG		 2000 /* In case we don't even reach vcpu_run, the fields are not updated */
2001 svm->vmcb->save.rax = nested_vmcb->save.rax;
2002 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2003 svm->vmcb->save.rip = nested_vmcb->save.rip;
2004 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2005 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2006 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2007
f7138538 2008 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2009 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2010
aad42c64
JR		 2011 /* cache intercepts */
2012 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2013 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2014 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2015 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2016 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2017 svm->nested.intercept = nested_vmcb->control.intercept;
2018
3d6368ef 2019 force_new_asid(&svm->vcpu);
3d6368ef 2020 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2021 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2022 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2023 else
2024 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2025
88ab24ad
JR		 2026 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2027 /* We only want the cr8 intercept bits of the guest */
2028 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2029 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2030 }
2031
e0231715
JR		 2032 /*
2033 * We don't want a nested guest to be more powerful than the guest, so
2034 * all intercepts are ORed
2035 */
88ab24ad
JR		 2036 svm->vmcb->control.intercept_cr_read |=
2037 nested_vmcb->control.intercept_cr_read;
2038 svm->vmcb->control.intercept_cr_write |=
2039 nested_vmcb->control.intercept_cr_write;
2040 svm->vmcb->control.intercept_dr_read |=
2041 nested_vmcb->control.intercept_dr_read;
2042 svm->vmcb->control.intercept_dr_write |=
2043 nested_vmcb->control.intercept_dr_write;
2044 svm->vmcb->control.intercept_exceptions |=
2045 nested_vmcb->control.intercept_exceptions;
2046
2047 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2048
2049 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2050 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2051 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2052 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2053 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2054 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2055
7597f129 2056 nested_svm_unmap(page);
9738b2c9 2057
06fc7772
JR		 2058 /* nested_vmcb is our indicator if nested SVM is activated */
2059 svm->nested.vmcb = vmcb_gpa;
2060
2af9194d 2061 enable_gif(svm);
3d6368ef 2062
9738b2c9 2063 return true;
3d6368ef
AG		 2064}
2065
9966bf68 2066static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2067{
2068 to_vmcb->save.fs = from_vmcb->save.fs;
2069 to_vmcb->save.gs = from_vmcb->save.gs;
2070 to_vmcb->save.tr = from_vmcb->save.tr;
2071 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2072 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2073 to_vmcb->save.star = from_vmcb->save.star;
2074 to_vmcb->save.lstar = from_vmcb->save.lstar;
2075 to_vmcb->save.cstar = from_vmcb->save.cstar;
2076 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2077 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2078 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2079 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2080}
2081
851ba692 2082static int vmload_interception(struct vcpu_svm *svm)
5542675b 2083{
9966bf68 2084 struct vmcb *nested_vmcb;
7597f129 2085 struct page *page;
9966bf68 2086
5542675b
AG		 2087 if (nested_svm_check_permissions(svm))
2088 return 1;
2089
2090 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2091 skip_emulated_instruction(&svm->vcpu);
2092
7597f129 2093 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2094 if (!nested_vmcb)
2095 return 1;
2096
2097 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2098 nested_svm_unmap(page);
5542675b
AG		 2099
2100 return 1;
2101}
2102
851ba692 2103static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2104{
9966bf68 2105 struct vmcb *nested_vmcb;
7597f129 2106 struct page *page;
9966bf68 2107
5542675b
AG		 2108 if (nested_svm_check_permissions(svm))
2109 return 1;
2110
2111 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2112 skip_emulated_instruction(&svm->vcpu);
2113
7597f129 2114 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2115 if (!nested_vmcb)
2116 return 1;
2117
2118 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2119 nested_svm_unmap(page);
5542675b
AG		 2120
2121 return 1;
2122}
2123
851ba692 2124static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2125{
3d6368ef
AG		 2126 if (nested_svm_check_permissions(svm))
2127 return 1;
2128
2129 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2130 skip_emulated_instruction(&svm->vcpu);
2131
9738b2c9 2132 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2133 return 1;
2134
9738b2c9 2135 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2136 goto failed;
2137
2138 return 1;
2139
2140failed:
2141
2142 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2143 svm->vmcb->control.exit_code_hi = 0;
2144 svm->vmcb->control.exit_info_1 = 0;
2145 svm->vmcb->control.exit_info_2 = 0;
2146
2147 nested_svm_vmexit(svm);
3d6368ef
AG		 2148
2149 return 1;
2150}
2151
851ba692 2152static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2153{
2154 if (nested_svm_check_permissions(svm))
2155 return 1;
2156
2157 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2158 skip_emulated_instruction(&svm->vcpu);
2159
2af9194d 2160 enable_gif(svm);
1371d904
AG		 2161
2162 return 1;
2163}
2164
851ba692 2165static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2166{
2167 if (nested_svm_check_permissions(svm))
2168 return 1;
2169
2170 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2171 skip_emulated_instruction(&svm->vcpu);
2172
2af9194d 2173 disable_gif(svm);
1371d904
AG		 2174
2175 /* After a CLGI no interrupts should come */
2176 svm_clear_vintr(svm);
2177 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2178
2179 return 1;
2180}
2181
851ba692 2182static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2183{
2184 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2185
ec1ff790
JR		 2186 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2187 vcpu->arch.regs[VCPU_REGS_RAX]);
2188
ff092385
AG		 2189 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2190 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2191
2192 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2193 skip_emulated_instruction(&svm->vcpu);
2194 return 1;
2195}
2196
532a46b9
JR		 2197static int skinit_interception(struct vcpu_svm *svm)
2198{
2199 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2200
2201 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2202 return 1;
2203}
2204
851ba692 2205static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2206{
7ee5d940 2207 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2208 return 1;
2209}
2210
851ba692 2211static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2212{
37817f29 2213 u16 tss_selector;
64a7ec06
GN		 2214 int reason;
2215 int int_type = svm->vmcb->control.exit_int_info &
2216 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2217 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2218 uint32_t type =
2219 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2220 uint32_t idt_v =
2221 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2222 bool has_error_code = false;
2223 u32 error_code = 0;
37817f29
IE		 2224
2225 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2226
37817f29
IE		 2227 if (svm->vmcb->control.exit_info_2 &
2228 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2229 reason = TASK_SWITCH_IRET;
2230 else if (svm->vmcb->control.exit_info_2 &
2231 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2232 reason = TASK_SWITCH_JMP;
fe8e7f83 2233 else if (idt_v)
64a7ec06
GN		 2234 reason = TASK_SWITCH_GATE;
2235 else
2236 reason = TASK_SWITCH_CALL;
2237
fe8e7f83
GN		 2238 if (reason == TASK_SWITCH_GATE) {
2239 switch (type) {
2240 case SVM_EXITINTINFO_TYPE_NMI:
2241 svm->vcpu.arch.nmi_injected = false;
2242 break;
2243 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2244 if (svm->vmcb->control.exit_info_2 &
2245 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2246 has_error_code = true;
2247 error_code =
2248 (u32)svm->vmcb->control.exit_info_2;
2249 }
fe8e7f83
GN		 2250 kvm_clear_exception_queue(&svm->vcpu);
2251 break;
2252 case SVM_EXITINTINFO_TYPE_INTR:
2253 kvm_clear_interrupt_queue(&svm->vcpu);
2254 break;
2255 default:
2256 break;
2257 }
2258 }
64a7ec06 2259
8317c298
GN		 2260 if (reason != TASK_SWITCH_GATE ||
2261 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2262 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2263 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2264 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2265
acb54517
GN		 2266 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2267 has_error_code, error_code) == EMULATE_FAIL) {
2268 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2269 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2270 svm->vcpu.run->internal.ndata = 0;
2271 return 0;
2272 }
2273 return 1;
6aa8b732
AK		 2274}
2275
851ba692 2276static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2277{
5fdbf976 2278 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2279 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2280 return 1;
6aa8b732
AK		 2281}
2282
851ba692 2283static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2284{
2285 ++svm->vcpu.stat.nmi_window_exits;
2286 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2287 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2288 return 1;
2289}
2290
851ba692 2291static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2292{
851ba692 2293 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2294 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2295 return 1;
2296}
2297
851ba692 2298static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2299{
851ba692 2300 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2301 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2302 return 1;
2303}
2304
851ba692 2305static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2306{
851ba692
AK		 2307 struct kvm_run *kvm_run = svm->vcpu.run;
2308
0a5fff19
GN		 2309 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2310 /* instruction emulation calls kvm_set_cr8() */
851ba692 2311 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2312 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2313 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2314 return 1;
95ba8273 2315 }
0a5fff19
GN		 2316 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2317 return 1;
1d075434
JR		 2318 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2319 return 0;
2320}
2321
6aa8b732
AK		 2322static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2323{
a2fa3e9f
GH		 2324 struct vcpu_svm *svm = to_svm(vcpu);
2325
6aa8b732 2326 switch (ecx) {
af24a4e4 2327 case MSR_IA32_TSC: {
20824f30 2328 u64 tsc_offset;
6aa8b732 2329
20824f30
JR		 2330 if (is_nested(svm))
2331 tsc_offset = svm->nested.hsave->control.tsc_offset;
2332 else
2333 tsc_offset = svm->vmcb->control.tsc_offset;
2334
2335 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2336 break;
2337 }
0e859cac 2338 case MSR_K6_STAR:
a2fa3e9f 2339 *data = svm->vmcb->save.star;
6aa8b732 2340 break;
0e859cac 2341#ifdef CONFIG_X86_64
6aa8b732 2342 case MSR_LSTAR:
a2fa3e9f 2343 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2344 break;
2345 case MSR_CSTAR:
a2fa3e9f 2346 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2347 break;
2348 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2349 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2350 break;
2351 case MSR_SYSCALL_MASK:
a2fa3e9f 2352 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2353 break;
2354#endif
2355 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2356 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2357 break;
2358 case MSR_IA32_SYSENTER_EIP:
017cb99e 2359 *data = svm->sysenter_eip;
6aa8b732
AK		 2360 break;
2361 case MSR_IA32_SYSENTER_ESP:
017cb99e 2362 *data = svm->sysenter_esp;
6aa8b732 2363 break;
e0231715
JR		 2364 /*
2365 * Nobody will change the following 5 values in the VMCB so we can
2366 * safely return them on rdmsr. They will always be 0 until LBRV is
2367 * implemented.
2368 */
a2938c80
JR		 2369 case MSR_IA32_DEBUGCTLMSR:
2370 *data = svm->vmcb->save.dbgctl;
2371 break;
2372 case MSR_IA32_LASTBRANCHFROMIP:
2373 *data = svm->vmcb->save.br_from;
2374 break;
2375 case MSR_IA32_LASTBRANCHTOIP:
2376 *data = svm->vmcb->save.br_to;
2377 break;
2378 case MSR_IA32_LASTINTFROMIP:
2379 *data = svm->vmcb->save.last_excp_from;
2380 break;
2381 case MSR_IA32_LASTINTTOIP:
2382 *data = svm->vmcb->save.last_excp_to;
2383 break;
b286d5d8 2384 case MSR_VM_HSAVE_PA:
e6aa9abd 2385 *data = svm->nested.hsave_msr;
b286d5d8 2386 break;
eb6f302e 2387 case MSR_VM_CR:
4a810181 2388 *data = svm->nested.vm_cr_msr;
eb6f302e 2389 break;
c8a73f18
AG		 2390 case MSR_IA32_UCODE_REV:
2391 *data = 0x01000065;
2392 break;
6aa8b732 2393 default:
3bab1f5d 2394 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2395 }
2396 return 0;
2397}
2398
851ba692 2399static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2400{
ad312c7c 2401 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2402 u64 data;
2403
59200273
AK		 2404 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2405 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2406 kvm_inject_gp(&svm->vcpu, 0);
59200273 2407 } else {
229456fc 2408 trace_kvm_msr_read(ecx, data);
af9ca2d7 2409
5fdbf976 2410 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2411 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2412 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2413 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2414 }
2415 return 1;
2416}
2417
4a810181
JR		 2418static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2419{
2420 struct vcpu_svm *svm = to_svm(vcpu);
2421 int svm_dis, chg_mask;
2422
2423 if (data & ~SVM_VM_CR_VALID_MASK)
2424 return 1;
2425
2426 chg_mask = SVM_VM_CR_VALID_MASK;
2427
2428 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2429 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2430
2431 svm->nested.vm_cr_msr &= ~chg_mask;
2432 svm->nested.vm_cr_msr |= (data & chg_mask);
2433
2434 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2435
2436 /* check for svm_disable while efer.svme is set */
2437 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2438 return 1;
2439
2440 return 0;
2441}
2442
6aa8b732
AK		 2443static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2444{
a2fa3e9f
GH		 2445 struct vcpu_svm *svm = to_svm(vcpu);
2446
6aa8b732 2447 switch (ecx) {
af24a4e4 2448 case MSR_IA32_TSC: {
20824f30
JR		 2449 u64 tsc_offset = data - native_read_tsc();
2450 u64 g_tsc_offset = 0;
2451
2452 if (is_nested(svm)) {
2453 g_tsc_offset = svm->vmcb->control.tsc_offset -
2454 svm->nested.hsave->control.tsc_offset;
2455 svm->nested.hsave->control.tsc_offset = tsc_offset;
2456 }
2457
2458 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2459
6aa8b732
AK		 2460 break;
2461 }
0e859cac 2462 case MSR_K6_STAR:
a2fa3e9f 2463 svm->vmcb->save.star = data;
6aa8b732 2464 break;
49b14f24 2465#ifdef CONFIG_X86_64
6aa8b732 2466 case MSR_LSTAR:
a2fa3e9f 2467 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2468 break;
2469 case MSR_CSTAR:
a2fa3e9f 2470 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2471 break;
2472 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2473 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2474 break;
2475 case MSR_SYSCALL_MASK:
a2fa3e9f 2476 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2477 break;
2478#endif
2479 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2480 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2481 break;
2482 case MSR_IA32_SYSENTER_EIP:
017cb99e 2483 svm->sysenter_eip = data;
a2fa3e9f 2484 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2485 break;
2486 case MSR_IA32_SYSENTER_ESP:
017cb99e 2487 svm->sysenter_esp = data;
a2fa3e9f 2488 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2489 break;
a2938c80 2490 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2491 if (!svm_has(SVM_FEATURE_LBRV)) {
2492 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2493 __func__, data);
24e09cbf
JR		 2494 break;
2495 }
2496 if (data & DEBUGCTL_RESERVED_BITS)
2497 return 1;
2498
2499 svm->vmcb->save.dbgctl = data;
2500 if (data & (1ULL<<0))
2501 svm_enable_lbrv(svm);
2502 else
2503 svm_disable_lbrv(svm);
a2938c80 2504 break;
b286d5d8 2505 case MSR_VM_HSAVE_PA:
e6aa9abd 2506 svm->nested.hsave_msr = data;
62b9abaa 2507 break;
3c5d0a44 2508 case MSR_VM_CR:
4a810181 2509 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2510 case MSR_VM_IGNNE:
3c5d0a44
AG		 2511 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2512 break;
6aa8b732 2513 default:
3bab1f5d 2514 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2515 }
2516 return 0;
2517}
2518
851ba692 2519static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2520{
ad312c7c 2521 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2522 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2523 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2524
af9ca2d7 2525
5fdbf976 2526 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2527 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2528 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2529 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2530 } else {
2531 trace_kvm_msr_write(ecx, data);
e756fc62 2532 skip_emulated_instruction(&svm->vcpu);
59200273 2533 }
6aa8b732
AK		 2534 return 1;
2535}
2536
851ba692 2537static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2538{
e756fc62 2539 if (svm->vmcb->control.exit_info_1)
851ba692 2540 return wrmsr_interception(svm);
6aa8b732 2541 else
851ba692 2542 return rdmsr_interception(svm);
6aa8b732
AK		 2543}
2544
851ba692 2545static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2546{
851ba692
AK		 2547 struct kvm_run *kvm_run = svm->vcpu.run;
2548
f0b85051 2549 svm_clear_vintr(svm);
85f455f7 2550 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2551 /*
2552 * If the user space waits to inject interrupts, exit as soon as
2553 * possible
2554 */
8061823a
GN		 2555 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2556 kvm_run->request_interrupt_window &&
2557 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2558 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2559 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2560 return 0;
2561 }
2562
2563 return 1;
2564}
2565
565d0998
ML		 2566static int pause_interception(struct vcpu_svm *svm)
2567{
2568 kvm_vcpu_on_spin(&(svm->vcpu));
2569 return 1;
2570}
2571
851ba692 2572static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2573 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2574 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2575 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2576 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2577 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2578 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2579 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2580 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2581 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2582 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2583 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2584 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2585 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2586 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2587 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2588 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2589 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2590 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2591 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2592 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2593 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2594 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2595 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2596 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2597 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2598 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2599 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2600 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2601 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2602 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2603 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2604 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2605 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2606 [SVM_EXIT_SMI] = nop_on_interception,
2607 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2608 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2609 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2610 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2611 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2612 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2613 [SVM_EXIT_HLT] = halt_interception,
a7052897 2614 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2615 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2616 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2617 [SVM_EXIT_MSR] = msr_interception,
2618 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2619 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2620 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2621 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2622 [SVM_EXIT_VMLOAD] = vmload_interception,
2623 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2624 [SVM_EXIT_STGI] = stgi_interception,
2625 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2626 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2627 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2628 [SVM_EXIT_MONITOR] = invalid_op_interception,
2629 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2630 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2631};
2632
851ba692 2633static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2634{
04d2cc77 2635 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2636 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2637 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2638
5bfd8b54 2639 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2640
2be4fc7a
JR		 2641 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2642 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2643 if (npt_enabled)
2644 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2645
cd3ff653
JR		 2646 if (unlikely(svm->nested.exit_required)) {
2647 nested_svm_vmexit(svm);
2648 svm->nested.exit_required = false;
2649
2650 return 1;
2651 }
2652
cf74a78b 2653 if (is_nested(svm)) {
410e4d57
JR		 2654 int vmexit;
2655
d8cabddf
JR		 2656 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2657 svm->vmcb->control.exit_info_1,
2658 svm->vmcb->control.exit_info_2,
2659 svm->vmcb->control.exit_int_info,
2660 svm->vmcb->control.exit_int_info_err);
2661
410e4d57
JR		 2662 vmexit = nested_svm_exit_special(svm);
2663
2664 if (vmexit == NESTED_EXIT_CONTINUE)
2665 vmexit = nested_svm_exit_handled(svm);
2666
2667 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2668 return 1;
cf74a78b
AG		 2669 }
2670
a5c3832d
JR		 2671 svm_complete_interrupts(svm);
2672
04d2cc77
AK		 2673 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2674 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2675 kvm_run->fail_entry.hardware_entry_failure_reason
2676 = svm->vmcb->control.exit_code;
2677 return 0;
2678 }
2679
a2fa3e9f 2680 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2681 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2682 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2683 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2684 "exit_code 0x%x\n",
b8688d51 2685 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2686 exit_code);
2687
9d8f549d 2688 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2689 || !svm_exit_handlers[exit_code]) {
6aa8b732 2690 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2691 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2692 return 0;
2693 }
2694
851ba692 2695 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2696}
2697
2698static void reload_tss(struct kvm_vcpu *vcpu)
2699{
2700 int cpu = raw_smp_processor_id();
2701
0fe1e009
TH		 2702 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2703 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2704 load_TR_desc();
2705}
2706
e756fc62 2707static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2708{
2709 int cpu = raw_smp_processor_id();
2710
0fe1e009 2711 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2712
a2fa3e9f 2713 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2714 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2715 if (svm->asid_generation != sd->asid_generation)
2716 new_asid(svm, sd);
6aa8b732
AK		 2717}
2718
95ba8273
GN		 2719static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2720{
2721 struct vcpu_svm *svm = to_svm(vcpu);
2722
2723 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2724 vcpu->arch.hflags |= HF_NMI_MASK;
2725 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2726 ++vcpu->stat.nmi_injections;
2727}
6aa8b732 2728
85f455f7 2729static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2730{
2731 struct vmcb_control_area *control;
2732
229456fc 2733 trace_kvm_inj_virq(irq);
af9ca2d7 2734
fa89a817 2735 ++svm->vcpu.stat.irq_injections;
e756fc62 2736 control = &svm->vmcb->control;
85f455f7 2737 control->int_vector = irq;
6aa8b732
AK		 2738 control->int_ctl &= ~V_INTR_PRIO_MASK;
2739 control->int_ctl |= V_IRQ_MASK |
2740 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2741}
2742
66fd3f7f 2743static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2744{
2745 struct vcpu_svm *svm = to_svm(vcpu);
2746
2af9194d 2747 BUG_ON(!(gif_set(svm)));
cf74a78b 2748
219b65dc
AG		 2749 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2750 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2751}
2752
95ba8273 2753static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2754{
2755 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2756
88ab24ad
JR		 2757 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2758 return;
2759
95ba8273 2760 if (irr == -1)
aaacfc9a
JR		 2761 return;
2762
95ba8273
GN		 2763 if (tpr >= irr)
2764 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2765}
aaacfc9a 2766
95ba8273
GN		 2767static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2768{
2769 struct vcpu_svm *svm = to_svm(vcpu);
2770 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2771 int ret;
2772 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2773 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2774 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2775
2776 return ret;
aaacfc9a
JR		 2777}
2778
3cfc3092
JK		 2779static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2780{
2781 struct vcpu_svm *svm = to_svm(vcpu);
2782
2783 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2784}
2785
2786static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2787{
2788 struct vcpu_svm *svm = to_svm(vcpu);
2789
2790 if (masked) {
2791 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2792 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2793 } else {
2794 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2795 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2796 }
2797}
2798
78646121
GN		 2799static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2800{
2801 struct vcpu_svm *svm = to_svm(vcpu);
2802 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2803 int ret;
2804
2805 if (!gif_set(svm) ||
2806 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2807 return 0;
2808
2809 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2810
2811 if (is_nested(svm))
2812 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2813
2814 return ret;
78646121
GN		 2815}
2816
9222be18 2817static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2818{
219b65dc 2819 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2820
e0231715
JR		 2821 /*
2822 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2823 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2824 * get that intercept, this function will be called again though and
2825 * we'll get the vintr intercept.
2826 */
8fe54654 2827 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2828 svm_set_vintr(svm);
2829 svm_inject_irq(svm, 0x0);
2830 }
85f455f7
ED		 2831}
2832
95ba8273 2833static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2834{
04d2cc77 2835 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2836
44c11430
GN		 2837 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2838 == HF_NMI_MASK)
2839 return; /* IRET will cause a vm exit */
2840
e0231715
JR		 2841 /*
2842 * Something prevents NMI from been injected. Single step over possible
2843 * problem (IRET or exception injection or interrupt shadow)
2844 */
924584cc
JR		 2845 svm->nmi_singlestep = true;
2846 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2847 update_db_intercept(vcpu);
c1150d8c
DL		 2848}
2849
cbc94022
IE		 2850static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2851{
2852 return 0;
2853}
2854
d9e368d6
AK		 2855static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2856{
2857 force_new_asid(vcpu);
2858}
2859
04d2cc77
AK		 2860static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2861{
2862}
2863
d7bf8221
JR		 2864static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2865{
2866 struct vcpu_svm *svm = to_svm(vcpu);
2867
88ab24ad
JR		 2868 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2869 return;
2870
d7bf8221
JR		 2871 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2872 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2873 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2874 }
2875}
2876
649d6864
JR		 2877static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2878{
2879 struct vcpu_svm *svm = to_svm(vcpu);
2880 u64 cr8;
2881
88ab24ad
JR		 2882 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2883 return;
2884
649d6864
JR		 2885 cr8 = kvm_get_cr8(vcpu);
2886 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2887 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2888}
2889
9222be18
GN		 2890static void svm_complete_interrupts(struct vcpu_svm *svm)
2891{
2892 u8 vector;
2893 int type;
2894 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 2895 unsigned int3_injected = svm->int3_injected;
2896
2897 svm->int3_injected = 0;
9222be18 2898
44c11430
GN		 2899 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2900 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2901
9222be18
GN		 2902 svm->vcpu.arch.nmi_injected = false;
2903 kvm_clear_exception_queue(&svm->vcpu);
2904 kvm_clear_interrupt_queue(&svm->vcpu);
2905
2906 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2907 return;
2908
2909 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2910 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2911
2912 switch (type) {
2913 case SVM_EXITINTINFO_TYPE_NMI:
2914 svm->vcpu.arch.nmi_injected = true;
2915 break;
2916 case SVM_EXITINTINFO_TYPE_EXEPT:
219b65dc
AG		 2917 if (is_nested(svm))
2918 break;
66b7138f
JK		 2919 /*
2920 * In case of software exceptions, do not reinject the vector,
2921 * but re-execute the instruction instead. Rewind RIP first
2922 * if we emulated INT3 before.
2923 */
2924 if (kvm_exception_is_soft(vector)) {
2925 if (vector == BP_VECTOR && int3_injected &&
2926 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2927 kvm_rip_write(&svm->vcpu,
2928 kvm_rip_read(&svm->vcpu) -
2929 int3_injected);
9222be18 2930 break;
66b7138f 2931 }
9222be18
GN		 2932 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2933 u32 err = svm->vmcb->control.exit_int_info_err;
2934 kvm_queue_exception_e(&svm->vcpu, vector, err);
2935
2936 } else
2937 kvm_queue_exception(&svm->vcpu, vector);
2938 break;
2939 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2940 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2941 break;
2942 default:
2943 break;
2944 }
2945}
2946
80e31d4f
AK		 2947#ifdef CONFIG_X86_64
2948#define R "r"
2949#else
2950#define R "e"
2951#endif
2952
851ba692 2953static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2954{
a2fa3e9f 2955 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2956 u16 fs_selector;
2957 u16 gs_selector;
2958 u16 ldt_selector;
d9e368d6 2959
2041a06a
JR		 2960 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2961 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2962 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2963
cd3ff653
JR		 2964 /*
2965 * A vmexit emulation is required before the vcpu can be executed
2966 * again.
2967 */
2968 if (unlikely(svm->nested.exit_required))
2969 return;
2970
e756fc62 2971 pre_svm_run(svm);
6aa8b732 2972
649d6864
JR		 2973 sync_lapic_to_cr8(vcpu);
2974
6aa8b732 2975 save_host_msrs(vcpu);
d6e88aec
AK		 2976 fs_selector = kvm_read_fs();
2977 gs_selector = kvm_read_gs();
2978 ldt_selector = kvm_read_ldt();
cda0ffdd 2979 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2980 /* required for live migration with NPT */
2981 if (npt_enabled)
2982 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2983
04d2cc77
AK		 2984 clgi();
2985
2986 local_irq_enable();
36241b8c 2987
6aa8b732 2988 asm volatile (
80e31d4f
AK		 2989 "push %%"R"bp; \n\t"
2990 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2991 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2992 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2993 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2994 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2995 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2996#ifdef CONFIG_X86_64
fb3f0f51
RR		 2997 "mov %c[r8](%[svm]), %%r8 \n\t"
2998 "mov %c[r9](%[svm]), %%r9 \n\t"
2999 "mov %c[r10](%[svm]), %%r10 \n\t"
3000 "mov %c[r11](%[svm]), %%r11 \n\t"
3001 "mov %c[r12](%[svm]), %%r12 \n\t"
3002 "mov %c[r13](%[svm]), %%r13 \n\t"
3003 "mov %c[r14](%[svm]), %%r14 \n\t"
3004 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3005#endif
3006
6aa8b732 3007 /* Enter guest mode */
80e31d4f
AK		 3008 "push %%"R"ax \n\t"
3009 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3010 __ex(SVM_VMLOAD) "\n\t"
3011 __ex(SVM_VMRUN) "\n\t"
3012 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3013 "pop %%"R"ax \n\t"
6aa8b732
AK		 3014
3015 /* Save guest registers, load host registers */
80e31d4f
AK		 3016 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3017 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3018 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3019 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3020 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3021 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3022#ifdef CONFIG_X86_64
fb3f0f51
RR		 3023 "mov %%r8, %c[r8](%[svm]) \n\t"
3024 "mov %%r9, %c[r9](%[svm]) \n\t"
3025 "mov %%r10, %c[r10](%[svm]) \n\t"
3026 "mov %%r11, %c[r11](%[svm]) \n\t"
3027 "mov %%r12, %c[r12](%[svm]) \n\t"
3028 "mov %%r13, %c[r13](%[svm]) \n\t"
3029 "mov %%r14, %c[r14](%[svm]) \n\t"
3030 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3031#endif
80e31d4f 3032 "pop %%"R"bp"
6aa8b732 3033 :
fb3f0f51 3034 : [svm]"a"(svm),
6aa8b732 3035 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3036 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3037 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3038 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3039 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3040 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3041 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3042#ifdef CONFIG_X86_64
ad312c7c
ZX		 3043 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3044 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3045 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3046 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3047 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3048 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3049 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3050 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3051#endif
54a08c04 3052 : "cc", "memory"
80e31d4f 3053 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3054#ifdef CONFIG_X86_64
54a08c04
LV		 3055 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3056#endif
3057 );
6aa8b732 3058
ad312c7c 3059 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3060 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3061 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3062 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3063
d6e88aec
AK		 3064 kvm_load_fs(fs_selector);
3065 kvm_load_gs(gs_selector);
3066 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3067 load_host_msrs(vcpu);
3068
3069 reload_tss(vcpu);
3070
56ba47dd
AK		 3071 local_irq_disable();
3072
3073 stgi();
3074
d7bf8221
JR		 3075 sync_cr8_to_lapic(vcpu);
3076
a2fa3e9f 3077 svm->next_rip = 0;
9222be18 3078
6de4f3ad
AK		 3079 if (npt_enabled) {
3080 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3081 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3082 }
6aa8b732
AK		 3083}
3084
80e31d4f
AK		 3085#undef R
3086
6aa8b732
AK		 3087static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3088{
a2fa3e9f
GH		 3089 struct vcpu_svm *svm = to_svm(vcpu);
3090
709ddebf
JR		 3091 if (npt_enabled) {
3092 svm->vmcb->control.nested_cr3 = root;
3093 force_new_asid(vcpu);
3094 return;
3095 }
3096
a2fa3e9f 3097 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3098 force_new_asid(vcpu);
3099}
3100
6aa8b732
AK		 3101static int is_disabled(void)
3102{
6031a61c
JR		 3103 u64 vm_cr;
3104
3105 rdmsrl(MSR_VM_CR, vm_cr);
3106 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3107 return 1;
3108
6aa8b732
AK		 3109 return 0;
3110}
3111
102d8325
IM		 3112static void
3113svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3114{
3115 /*
3116 * Patch in the VMMCALL instruction:
3117 */
3118 hypercall[0] = 0x0f;
3119 hypercall[1] = 0x01;
3120 hypercall[2] = 0xd9;
102d8325
IM		 3121}
3122
002c7f7c
YS		 3123static void svm_check_processor_compat(void *rtn)
3124{
3125 *(int *)rtn = 0;
3126}
3127
774ead3a
AK		 3128static bool svm_cpu_has_accelerated_tpr(void)
3129{
3130 return false;
3131}
3132
67253af5
SY		 3133static int get_npt_level(void)
3134{
3135#ifdef CONFIG_X86_64
3136 return PT64_ROOT_LEVEL;
3137#else
3138 return PT32E_ROOT_LEVEL;
3139#endif
3140}
3141
4b12f0de 3142static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3143{
3144 return 0;
3145}
3146
0e851880
SY		 3147static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3148{
3149}
3150
229456fc 3151static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3152 { SVM_EXIT_READ_CR0, "read_cr0" },
3153 { SVM_EXIT_READ_CR3, "read_cr3" },
3154 { SVM_EXIT_READ_CR4, "read_cr4" },
3155 { SVM_EXIT_READ_CR8, "read_cr8" },
3156 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3157 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3158 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3159 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3160 { SVM_EXIT_READ_DR0, "read_dr0" },
3161 { SVM_EXIT_READ_DR1, "read_dr1" },
3162 { SVM_EXIT_READ_DR2, "read_dr2" },
3163 { SVM_EXIT_READ_DR3, "read_dr3" },
3164 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3165 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3166 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3167 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3168 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3169 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3170 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3171 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3172 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3173 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3174 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3175 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3176 { SVM_EXIT_INTR, "interrupt" },
3177 { SVM_EXIT_NMI, "nmi" },
3178 { SVM_EXIT_SMI, "smi" },
3179 { SVM_EXIT_INIT, "init" },
3180 { SVM_EXIT_VINTR, "vintr" },
3181 { SVM_EXIT_CPUID, "cpuid" },
3182 { SVM_EXIT_INVD, "invd" },
3183 { SVM_EXIT_HLT, "hlt" },
3184 { SVM_EXIT_INVLPG, "invlpg" },
3185 { SVM_EXIT_INVLPGA, "invlpga" },
3186 { SVM_EXIT_IOIO, "io" },
3187 { SVM_EXIT_MSR, "msr" },
3188 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3189 { SVM_EXIT_SHUTDOWN, "shutdown" },
3190 { SVM_EXIT_VMRUN, "vmrun" },
3191 { SVM_EXIT_VMMCALL, "hypercall" },
3192 { SVM_EXIT_VMLOAD, "vmload" },
3193 { SVM_EXIT_VMSAVE, "vmsave" },
3194 { SVM_EXIT_STGI, "stgi" },
3195 { SVM_EXIT_CLGI, "clgi" },
3196 { SVM_EXIT_SKINIT, "skinit" },
3197 { SVM_EXIT_WBINVD, "wbinvd" },
3198 { SVM_EXIT_MONITOR, "monitor" },
3199 { SVM_EXIT_MWAIT, "mwait" },
3200 { SVM_EXIT_NPF, "npf" },
3201 { -1, NULL }
3202};
3203
17cc3935 3204static int svm_get_lpage_level(void)
344f414f 3205{
17cc3935 3206 return PT_PDPE_LEVEL;
344f414f
JR		 3207}
3208
4e47c7a6
SY		 3209static bool svm_rdtscp_supported(void)
3210{
3211 return false;
3212}
3213
02daab21
AK		 3214static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3215{
3216 struct vcpu_svm *svm = to_svm(vcpu);
3217
02daab21 3218 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3219 if (is_nested(svm))
3220 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3221 update_cr0_intercept(svm);
02daab21
AK		 3222}
3223
cbdd1bea 3224static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3225 .cpu_has_kvm_support = has_svm,
3226 .disabled_by_bios = is_disabled,
3227 .hardware_setup = svm_hardware_setup,
3228 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3229 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3230 .hardware_enable = svm_hardware_enable,
3231 .hardware_disable = svm_hardware_disable,
774ead3a 3232 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3233
3234 .vcpu_create = svm_create_vcpu,
3235 .vcpu_free = svm_free_vcpu,
04d2cc77 3236 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3237
04d2cc77 3238 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3239 .vcpu_load = svm_vcpu_load,
3240 .vcpu_put = svm_vcpu_put,
3241
3242 .set_guest_debug = svm_guest_debug,
3243 .get_msr = svm_get_msr,
3244 .set_msr = svm_set_msr,
3245 .get_segment_base = svm_get_segment_base,
3246 .get_segment = svm_get_segment,
3247 .set_segment = svm_set_segment,
2e4d2653 3248 .get_cpl = svm_get_cpl,
1747fb71 3249 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3250 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3251 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3252 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3253 .set_cr3 = svm_set_cr3,
3254 .set_cr4 = svm_set_cr4,
3255 .set_efer = svm_set_efer,
3256 .get_idt = svm_get_idt,
3257 .set_idt = svm_set_idt,
3258 .get_gdt = svm_get_gdt,
3259 .set_gdt = svm_set_gdt,
020df079 3260 .set_dr7 = svm_set_dr7,
6de4f3ad 3261 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3262 .get_rflags = svm_get_rflags,
3263 .set_rflags = svm_set_rflags,
6b52d186 3264 .fpu_activate = svm_fpu_activate,
02daab21 3265 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3266
6aa8b732 3267 .tlb_flush = svm_flush_tlb,
6aa8b732 3268
6aa8b732 3269 .run = svm_vcpu_run,
04d2cc77 3270 .handle_exit = handle_exit,
6aa8b732 3271 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3272 .set_interrupt_shadow = svm_set_interrupt_shadow,
3273 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3274 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3275 .set_irq = svm_set_irq,
95ba8273 3276 .set_nmi = svm_inject_nmi,
298101da 3277 .queue_exception = svm_queue_exception,
78646121 3278 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3279 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3280 .get_nmi_mask = svm_get_nmi_mask,
3281 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3282 .enable_nmi_window = enable_nmi_window,
3283 .enable_irq_window = enable_irq_window,
3284 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3285
3286 .set_tss_addr = svm_set_tss_addr,
67253af5 3287 .get_tdp_level = get_npt_level,
4b12f0de 3288 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3289
3290 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3291 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3292
3293 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3294
3295 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3296};
3297
3298static int __init svm_init(void)
3299{
cb498ea2 3300 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3301 THIS_MODULE);
6aa8b732
AK		 3302}
3303
3304static void __exit svm_exit(void)
3305{
cb498ea2 3306 kvm_exit();
6aa8b732
AK		 3307}
3308
3309module_init(svm_init)
3310module_exit(svm_exit)
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