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KVM: Move cr0/cr4/efer related helpers to x86.h
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
565d0998 49#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 50
410e4d57
JR		 51#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
24e09cbf
JR		 55#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
6c8166a7
AK		 57static const u32 host_save_user_msrs[] = {
58#ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61#endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63};
64
65#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67struct kvm_vcpu;
68
e6aa9abd
JR		 69struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
aad42c64 79
cd3ff653
JR		 80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
aad42c64
JR		 83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
e6aa9abd
JR		 91};
92
6c8166a7
AK		 93struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
6c8166a7
AK		 106
107 u32 *msrpm;
6c8166a7 108
e6aa9abd 109 struct nested_state nested;
6be7d306
JK		 110
111 bool nmi_singlestep;
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116static bool npt_enabled = true;
117#else
e3da3acd 118static bool npt_enabled = false;
709ddebf 119#endif
6c7dac72
JR		 120static int npt = 1;
121
122module_param(npt, int, S_IRUGO);
e3da3acd 123
4b6e4dca 124static int nested = 1;
236de055
AG		 125module_param(nested, int, S_IRUGO);
126
44874f84 127static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 128static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 129
410e4d57 130static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 131static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 132static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
a2fa3e9f
GH		 135static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136{
fb3f0f51 137 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 138}
139
3d6368ef
AG		 140static inline bool is_nested(struct vcpu_svm *svm)
141{
e6aa9abd 142 return svm->nested.vmcb;
3d6368ef
AG		 143}
144
2af9194d
JR		 145static inline void enable_gif(struct vcpu_svm *svm)
146{
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148}
149
150static inline void disable_gif(struct vcpu_svm *svm)
151{
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153}
154
155static inline bool gif_set(struct vcpu_svm *svm)
156{
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158}
159
4866d5e3 160static unsigned long iopm_base;
6aa8b732
AK		 161
162struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169} __attribute__((packed));
170
171struct svm_cpu_data {
172 int cpu;
173
5008fdf5
AK		 174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
6aa8b732
AK		 177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180};
181
182static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 183static uint32_t svm_features;
6aa8b732
AK		 184
185struct svm_init_data {
186 int cpu;
187 int r;
188};
189
190static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
9d8f549d 192#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 193#define MSRS_RANGE_SIZE 2048
194#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196#define MAX_INST_SIZE 15
197
80b7706e
JR		 198static inline u32 svm_has(u32 feat)
199{
200 return svm_features & feat;
201}
202
6aa8b732
AK		 203static inline void clgi(void)
204{
4ecac3fd 205 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 206}
207
208static inline void stgi(void)
209{
4ecac3fd 210 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 211}
212
213static inline void invlpga(unsigned long addr, u32 asid)
214{
4ecac3fd 215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 216}
217
6aa8b732
AK		 218static inline void force_new_asid(struct kvm_vcpu *vcpu)
219{
a2fa3e9f 220 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 221}
222
223static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224{
225 force_new_asid(vcpu);
226}
227
228static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229{
709ddebf 230 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 231 efer &= ~EFER_LME;
6aa8b732 232
9962d032 233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 234 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 235}
236
298101da
AK		 237static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239{
240 struct vcpu_svm *svm = to_svm(vcpu);
241
cf74a78b
AG		 242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
298101da
AK		 247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252}
253
6aa8b732
AK		 254static int is_external_interrupt(u32 info)
255{
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258}
259
2809f5d2
GC		 260static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261{
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268}
269
270static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271{
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279}
280
6aa8b732
AK		 281static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282{
a2fa3e9f
GH		 283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
851ba692 286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 289 return;
290 }
5fdbf976
MT		 291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 294
5fdbf976 295 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 296 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 297}
298
299static int has_svm(void)
300{
63d1142f 301 const char *msg;
6aa8b732 302
63d1142f 303 if (!cpu_has_svm(&msg)) {
ff81ff10 304 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 305 return 0;
306 }
307
6aa8b732
AK		 308 return 1;
309}
310
311static void svm_hardware_disable(void *garbage)
312{
2c8dceeb 313 cpu_svm_disable();
6aa8b732
AK		 314}
315
10474ae8 316static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 317{
318
0fe1e009 319 struct svm_cpu_data *sd;
6aa8b732 320 uint64_t efer;
b792c344 321 struct descriptor_table gdt_descr;
6aa8b732
AK		 322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
10474ae8
AG		 325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
6aa8b732 329 if (!has_svm()) {
e6732a5a
ZA		 330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
10474ae8 332 return -EINVAL;
6aa8b732 333 }
0fe1e009 334 sd = per_cpu(svm_data, me);
6aa8b732 335
0fe1e009 336 if (!sd) {
e6732a5a 337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 338 me);
10474ae8 339 return -EINVAL;
6aa8b732
AK		 340 }
341
0fe1e009
TH		 342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
6aa8b732 345
b792c344
AM		 346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
0fe1e009 348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 349
9962d032 350 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 351
d0316554 352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 353
354 return 0;
6aa8b732
AK		 355}
356
0da1db75
JR		 357static void svm_cpu_uninit(int cpu)
358{
0fe1e009 359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 360
0fe1e009 361 if (!sd)
0da1db75
JR		 362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 365 __free_page(sd->save_area);
366 kfree(sd);
0da1db75
JR		 367}
368
6aa8b732
AK		 369static int svm_cpu_init(int cpu)
370{
0fe1e009 371 struct svm_cpu_data *sd;
6aa8b732
AK		 372 int r;
373
0fe1e009
TH		 374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
6aa8b732 376 return -ENOMEM;
0fe1e009
TH		 377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 379 r = -ENOMEM;
0fe1e009 380 if (!sd->save_area)
6aa8b732
AK		 381 goto err_1;
382
0fe1e009 383 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 384
385 return 0;
386
387err_1:
0fe1e009 388 kfree(sd);
6aa8b732
AK		 389 return r;
390
391}
392
bfc733a7
RR		 393static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
6aa8b732
AK		 395{
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
bfc733a7 409 return;
6aa8b732
AK		 410 }
411 }
bfc733a7 412 BUG();
6aa8b732
AK		 413}
414
f65c229c
JR		 415static void svm_vcpu_init_msrpm(u32 *msrpm)
416{
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419#ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426#endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 429}
430
24e09cbf
JR		 431static void svm_enable_lbrv(struct vcpu_svm *svm)
432{
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440}
441
442static void svm_disable_lbrv(struct vcpu_svm *svm)
443{
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451}
452
6aa8b732
AK		 453static __init int svm_hardware_setup(void)
454{
455 int cpu;
456 struct page *iopm_pages;
f65c229c 457 void *iopm_va;
6aa8b732
AK		 458 int r;
459
6aa8b732
AK		 460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
c8681339
AL		 464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
50a37eb4
JR		 469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
1b2fd70c
AG		 472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
236de055
AG		 475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
3230bb47 480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 481 r = svm_cpu_init(cpu);
482 if (r)
f65c229c 483 goto err;
6aa8b732 484 }
33bd6a0b
JR		 485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
e3da3acd
JR		 488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
6c7dac72
JR		 491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
18552672 496 if (npt_enabled) {
e3da3acd 497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 498 kvm_enable_tdp();
5f4cb662
JR		 499 } else
500 kvm_disable_tdp();
e3da3acd 501
6aa8b732
AK		 502 return 0;
503
f65c229c 504err:
6aa8b732
AK		 505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508}
509
510static __exit void svm_hardware_unsetup(void)
511{
0da1db75
JR		 512 int cpu;
513
3230bb47 514 for_each_possible_cpu(cpu)
0da1db75
JR		 515 svm_cpu_uninit(cpu);
516
6aa8b732 517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 518 iopm_base = 0;
6aa8b732
AK		 519}
520
521static void init_seg(struct vmcb_seg *seg)
522{
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528}
529
530static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531{
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
e6101a96 538static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 539{
e6101a96
JR		 540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 542
bff78274
AK		 543 svm->vcpu.fpu_active = 1;
544
6aa8b732
AK		 545 control->intercept_cr_read = INTERCEPT_CR0_MASK |
546 INTERCEPT_CR3_MASK |
649d6864 547 INTERCEPT_CR4_MASK;
6aa8b732
AK		 548
549 control->intercept_cr_write = INTERCEPT_CR0_MASK |
550 INTERCEPT_CR3_MASK |
80a8119c
AK		 551 INTERCEPT_CR4_MASK |
552 INTERCEPT_CR8_MASK;
6aa8b732
AK		 553
554 control->intercept_dr_read = INTERCEPT_DR0_MASK |
555 INTERCEPT_DR1_MASK |
556 INTERCEPT_DR2_MASK |
727f5a23
JK		 557 INTERCEPT_DR3_MASK |
558 INTERCEPT_DR4_MASK |
559 INTERCEPT_DR5_MASK |
560 INTERCEPT_DR6_MASK |
561 INTERCEPT_DR7_MASK;
6aa8b732
AK		 562
563 control->intercept_dr_write = INTERCEPT_DR0_MASK |
564 INTERCEPT_DR1_MASK |
565 INTERCEPT_DR2_MASK |
566 INTERCEPT_DR3_MASK |
727f5a23 567 INTERCEPT_DR4_MASK |
6aa8b732 568 INTERCEPT_DR5_MASK |
727f5a23 569 INTERCEPT_DR6_MASK |
6aa8b732
AK		 570 INTERCEPT_DR7_MASK;
571
7aa81cc0 572 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 573 (1 << UD_VECTOR) |
574 (1 << MC_VECTOR);
6aa8b732
AK		 575
576
577 control->intercept = (1ULL << INTERCEPT_INTR) |
578 (1ULL << INTERCEPT_NMI) |
0152527b 579 (1ULL << INTERCEPT_SMI) |
d225157b 580 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 581 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 582 (1ULL << INTERCEPT_INVD) |
6aa8b732 583 (1ULL << INTERCEPT_HLT) |
a7052897 584 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 585 (1ULL << INTERCEPT_INVLPGA) |
586 (1ULL << INTERCEPT_IOIO_PROT) |
587 (1ULL << INTERCEPT_MSR_PROT) |
588 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 589 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 590 (1ULL << INTERCEPT_VMRUN) |
591 (1ULL << INTERCEPT_VMMCALL) |
592 (1ULL << INTERCEPT_VMLOAD) |
593 (1ULL << INTERCEPT_VMSAVE) |
594 (1ULL << INTERCEPT_STGI) |
595 (1ULL << INTERCEPT_CLGI) |
916ce236 596 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 597 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 598 (1ULL << INTERCEPT_MONITOR) |
599 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 600
601 control->iopm_base_pa = iopm_base;
f65c229c 602 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 603 control->tsc_offset = 0;
6aa8b732
AK		 604 control->int_ctl = V_INTR_MASKING_MASK;
605
606 init_seg(&save->es);
607 init_seg(&save->ss);
608 init_seg(&save->ds);
609 init_seg(&save->fs);
610 init_seg(&save->gs);
611
612 save->cs.selector = 0xf000;
613 /* Executable/Readable Code Segment */
614 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
615 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
616 save->cs.limit = 0xffff;
d92899a0
AK		 617 /*
618 * cs.base should really be 0xffff0000, but vmx can't handle that, so
619 * be consistent with it.
620 *
621 * Replace when we have real mode working for vmx.
622 */
623 save->cs.base = 0xf0000;
6aa8b732
AK		 624
625 save->gdtr.limit = 0xffff;
626 save->idtr.limit = 0xffff;
627
628 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
629 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
630
9962d032 631 save->efer = EFER_SVME;
d77c26fc 632 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 633 save->dr7 = 0x400;
634 save->rflags = 2;
635 save->rip = 0x0000fff0;
5fdbf976 636 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 637
18fa000a
EH		 638 /* This is the guest-visible cr0 value.
639 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 640 */
18fa000a
EH		 641 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
642 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
643
66aee91a 644 save->cr4 = X86_CR4_PAE;
6aa8b732 645 /* rdx = ?? */
709ddebf
JR		 646
647 if (npt_enabled) {
648 /* Setup VMCB for Nested Paging */
649 control->nested_ctl = 1;
a7052897
MT		 650 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
651 (1ULL << INTERCEPT_INVLPG));
709ddebf 652 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 653 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
654 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 655 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 656 save->cr3 = 0;
657 save->cr4 = 0;
658 }
a79d2f18 659 force_new_asid(&svm->vcpu);
1371d904 660
e6aa9abd 661 svm->nested.vmcb = 0;
2af9194d
JR		 662 svm->vcpu.arch.hflags = 0;
663
565d0998
ML		 664 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
665 control->pause_filter_count = 3000;
666 control->intercept |= (1ULL << INTERCEPT_PAUSE);
667 }
668
2af9194d 669 enable_gif(svm);
6aa8b732
AK		 670}
671
e00c8cf2 672static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 673{
674 struct vcpu_svm *svm = to_svm(vcpu);
675
e6101a96 676 init_vmcb(svm);
70433389 677
c5af89b6 678 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 679 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 680 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
681 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 682 }
5fdbf976
MT		 683 vcpu->arch.regs_avail = ~0;
684 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 685
686 return 0;
04d2cc77
AK		 687}
688
fb3f0f51 689static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 690{
a2fa3e9f 691 struct vcpu_svm *svm;
6aa8b732 692 struct page *page;
f65c229c 693 struct page *msrpm_pages;
b286d5d8 694 struct page *hsave_page;
3d6368ef 695 struct page *nested_msrpm_pages;
fb3f0f51 696 int err;
6aa8b732 697
c16f862d 698 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 699 if (!svm) {
700 err = -ENOMEM;
701 goto out;
702 }
703
704 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
705 if (err)
706 goto free_svm;
707
6aa8b732 708 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 709 if (!page) {
710 err = -ENOMEM;
711 goto uninit;
712 }
6aa8b732 713
f65c229c
JR		 714 err = -ENOMEM;
715 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
716 if (!msrpm_pages)
717 goto uninit;
3d6368ef
AG		 718
719 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
720 if (!nested_msrpm_pages)
721 goto uninit;
722
f65c229c
JR		 723 svm->msrpm = page_address(msrpm_pages);
724 svm_vcpu_init_msrpm(svm->msrpm);
725
b286d5d8
AG		 726 hsave_page = alloc_page(GFP_KERNEL);
727 if (!hsave_page)
728 goto uninit;
e6aa9abd 729 svm->nested.hsave = page_address(hsave_page);
b286d5d8 730
e6aa9abd 731 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 732
a2fa3e9f
GH		 733 svm->vmcb = page_address(page);
734 clear_page(svm->vmcb);
735 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
736 svm->asid_generation = 0;
e6101a96 737 init_vmcb(svm);
a2fa3e9f 738
fb3f0f51 739 fx_init(&svm->vcpu);
ad312c7c 740 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 741 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 742 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 743
fb3f0f51 744 return &svm->vcpu;
36241b8c 745
fb3f0f51
RR		 746uninit:
747 kvm_vcpu_uninit(&svm->vcpu);
748free_svm:
a4770347 749 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 750out:
751 return ERR_PTR(err);
6aa8b732
AK		 752}
753
754static void svm_free_vcpu(struct kvm_vcpu *vcpu)
755{
a2fa3e9f
GH		 756 struct vcpu_svm *svm = to_svm(vcpu);
757
fb3f0f51 758 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 759 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 760 __free_page(virt_to_page(svm->nested.hsave));
761 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 762 kvm_vcpu_uninit(vcpu);
a4770347 763 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 764}
765
15ad7146 766static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 767{
a2fa3e9f 768 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 769 int i;
0cc5064d 770
0cc5064d 771 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 772 u64 delta;
0cc5064d 773
953899b6
JR		 774 if (check_tsc_unstable()) {
775 /*
776 * Make sure that the guest sees a monotonically
777 * increasing TSC.
778 */
779 delta = vcpu->arch.host_tsc - native_read_tsc();
780 svm->vmcb->control.tsc_offset += delta;
781 if (is_nested(svm))
782 svm->nested.hsave->control.tsc_offset += delta;
783 }
0cc5064d 784 vcpu->cpu = cpu;
2f599714 785 kvm_migrate_timers(vcpu);
4b656b12 786 svm->asid_generation = 0;
0cc5064d 787 }
94dfbdb3
AL		 788
789 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 790 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 791}
792
793static void svm_vcpu_put(struct kvm_vcpu *vcpu)
794{
a2fa3e9f 795 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 796 int i;
797
e1beb1d3 798 ++vcpu->stat.host_state_reload;
94dfbdb3 799 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 800 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 801
e935d48e 802 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 803}
804
6aa8b732
AK		 805static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
806{
a2fa3e9f 807 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 808}
809
810static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
811{
a2fa3e9f 812 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 813}
814
6de4f3ad
AK		 815static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
816{
817 switch (reg) {
818 case VCPU_EXREG_PDPTR:
819 BUG_ON(!npt_enabled);
820 load_pdptrs(vcpu, vcpu->arch.cr3);
821 break;
822 default:
823 BUG();
824 }
825}
826
f0b85051
AG		 827static void svm_set_vintr(struct vcpu_svm *svm)
828{
829 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
830}
831
832static void svm_clear_vintr(struct vcpu_svm *svm)
833{
834 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
835}
836
6aa8b732
AK		 837static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
838{
a2fa3e9f 839 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 840
841 switch (seg) {
842 case VCPU_SREG_CS: return &save->cs;
843 case VCPU_SREG_DS: return &save->ds;
844 case VCPU_SREG_ES: return &save->es;
845 case VCPU_SREG_FS: return &save->fs;
846 case VCPU_SREG_GS: return &save->gs;
847 case VCPU_SREG_SS: return &save->ss;
848 case VCPU_SREG_TR: return &save->tr;
849 case VCPU_SREG_LDTR: return &save->ldtr;
850 }
851 BUG();
8b6d44c7 852 return NULL;
6aa8b732
AK		 853}
854
855static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
856{
857 struct vmcb_seg *s = svm_seg(vcpu, seg);
858
859 return s->base;
860}
861
862static void svm_get_segment(struct kvm_vcpu *vcpu,
863 struct kvm_segment *var, int seg)
864{
865 struct vmcb_seg *s = svm_seg(vcpu, seg);
866
867 var->base = s->base;
868 var->limit = s->limit;
869 var->selector = s->selector;
870 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
871 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
872 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
873 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
874 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
875 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
876 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
877 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 878
19bca6ab
AP		 879 /* AMD's VMCB does not have an explicit unusable field, so emulate it
880 * for cross vendor migration purposes by "not present"
881 */
882 var->unusable = !var->present || (var->type == 0);
883
1fbdc7a5
AP		 884 switch (seg) {
885 case VCPU_SREG_CS:
886 /*
887 * SVM always stores 0 for the 'G' bit in the CS selector in
888 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
889 * Intel's VMENTRY has a check on the 'G' bit.
890 */
25022acc 891 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 892 break;
893 case VCPU_SREG_TR:
894 /*
895 * Work around a bug where the busy flag in the tr selector
896 * isn't exposed
897 */
c0d09828 898 var->type |= 0x2;
1fbdc7a5
AP		 899 break;
900 case VCPU_SREG_DS:
901 case VCPU_SREG_ES:
902 case VCPU_SREG_FS:
903 case VCPU_SREG_GS:
904 /*
905 * The accessed bit must always be set in the segment
906 * descriptor cache, although it can be cleared in the
907 * descriptor, the cached bit always remains at 1. Since
908 * Intel has a check on this, set it here to support
909 * cross-vendor migration.
910 */
911 if (!var->unusable)
912 var->type |= 0x1;
913 break;
b586eb02
AP		 914 case VCPU_SREG_SS:
915 /* On AMD CPUs sometimes the DB bit in the segment
916 * descriptor is left as 1, although the whole segment has
917 * been made unusable. Clear it here to pass an Intel VMX
918 * entry check when cross vendor migrating.
919 */
920 if (var->unusable)
921 var->db = 0;
922 break;
1fbdc7a5 923 }
6aa8b732
AK		 924}
925
2e4d2653
IE		 926static int svm_get_cpl(struct kvm_vcpu *vcpu)
927{
928 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
929
930 return save->cpl;
931}
932
6aa8b732
AK		 933static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
934{
a2fa3e9f
GH		 935 struct vcpu_svm *svm = to_svm(vcpu);
936
937 dt->limit = svm->vmcb->save.idtr.limit;
938 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 939}
940
941static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
942{
a2fa3e9f
GH		 943 struct vcpu_svm *svm = to_svm(vcpu);
944
945 svm->vmcb->save.idtr.limit = dt->limit;
946 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 947}
948
949static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
950{
a2fa3e9f
GH		 951 struct vcpu_svm *svm = to_svm(vcpu);
952
953 dt->limit = svm->vmcb->save.gdtr.limit;
954 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 955}
956
957static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
958{
a2fa3e9f
GH		 959 struct vcpu_svm *svm = to_svm(vcpu);
960
961 svm->vmcb->save.gdtr.limit = dt->limit;
962 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 963}
964
e8467fda
AK		 965static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
966{
967}
968
25c4c276 969static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 970{
971}
972
d225157b
AK		 973static void update_cr0_intercept(struct vcpu_svm *svm)
974{
975 ulong gcr0 = svm->vcpu.arch.cr0;
976 u64 *hcr0 = &svm->vmcb->save.cr0;
977
978 if (!svm->vcpu.fpu_active)
979 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
980 else
981 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
982 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
983
984
985 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
986 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
987 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
988 } else {
989 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
990 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
991 }
992}
993
6aa8b732
AK		 994static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
995{
a2fa3e9f
GH		 996 struct vcpu_svm *svm = to_svm(vcpu);
997
05b3e0c2 998#ifdef CONFIG_X86_64
ad312c7c 999 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1000 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 1001 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 1002 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1003 }
1004
d77c26fc 1005 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 1006 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 1007 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1008 }
1009 }
1010#endif
ad312c7c 1011 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1012
1013 if (!npt_enabled)
1014 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1015
1016 if (!vcpu->fpu_active)
334df50a 1017 cr0 |= X86_CR0_TS;
709ddebf
JR		 1018 /*
1019 * re-enable caching here because the QEMU bios
1020 * does not do it - this results in some delay at
1021 * reboot
1022 */
1023 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1024 svm->vmcb->save.cr0 = cr0;
d225157b 1025 update_cr0_intercept(svm);
6aa8b732
AK		 1026}
1027
1028static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1029{
6394b649 1030 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1031 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1032
1033 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1034 force_new_asid(vcpu);
6394b649 1035
ec077263
JR		 1036 vcpu->arch.cr4 = cr4;
1037 if (!npt_enabled)
1038 cr4 |= X86_CR4_PAE;
6394b649 1039 cr4 |= host_cr4_mce;
ec077263 1040 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1041}
1042
1043static void svm_set_segment(struct kvm_vcpu *vcpu,
1044 struct kvm_segment *var, int seg)
1045{
a2fa3e9f 1046 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1047 struct vmcb_seg *s = svm_seg(vcpu, seg);
1048
1049 s->base = var->base;
1050 s->limit = var->limit;
1051 s->selector = var->selector;
1052 if (var->unusable)
1053 s->attrib = 0;
1054 else {
1055 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1056 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1057 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1058 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1059 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1060 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1061 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1062 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1063 }
1064 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1065 svm->vmcb->save.cpl
1066 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1067 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1068
1069}
1070
44c11430 1071static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1072{
d0bfb940
JK		 1073 struct vcpu_svm *svm = to_svm(vcpu);
1074
d0bfb940
JK		 1075 svm->vmcb->control.intercept_exceptions &=
1076 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1077
6be7d306 1078 if (svm->nmi_singlestep)
44c11430
GN		 1079 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1080
d0bfb940
JK		 1081 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1082 if (vcpu->guest_debug &
1083 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1084 svm->vmcb->control.intercept_exceptions |=
1085 1 << DB_VECTOR;
1086 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1087 svm->vmcb->control.intercept_exceptions |=
1088 1 << BP_VECTOR;
1089 } else
1090 vcpu->guest_debug = 0;
44c11430
GN		 1091}
1092
355be0b9 1093static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1094{
44c11430
GN		 1095 struct vcpu_svm *svm = to_svm(vcpu);
1096
ae675ef0
JK		 1097 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1098 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1099 else
1100 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1101
355be0b9 1102 update_db_intercept(vcpu);
6aa8b732
AK		 1103}
1104
1105static void load_host_msrs(struct kvm_vcpu *vcpu)
1106{
94dfbdb3 1107#ifdef CONFIG_X86_64
a2fa3e9f 1108 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1109#endif
6aa8b732
AK		 1110}
1111
1112static void save_host_msrs(struct kvm_vcpu *vcpu)
1113{
94dfbdb3 1114#ifdef CONFIG_X86_64
a2fa3e9f 1115 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1116#endif
6aa8b732
AK		 1117}
1118
0fe1e009 1119static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1120{
0fe1e009
TH		 1121 if (sd->next_asid > sd->max_asid) {
1122 ++sd->asid_generation;
1123 sd->next_asid = 1;
a2fa3e9f 1124 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1125 }
1126
0fe1e009
TH		 1127 svm->asid_generation = sd->asid_generation;
1128 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1129}
1130
c76de350 1131static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1132{
42dbaa5a 1133 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1134
1135 switch (dr) {
1136 case 0 ... 3:
c76de350 1137 *dest = vcpu->arch.db[dr];
42dbaa5a 1138 break;
c76de350
JK		 1139 case 4:
1140 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1141 return EMULATE_FAIL; /* will re-inject UD */
1142 /* fall through */
42dbaa5a
JK		 1143 case 6:
1144 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1145 *dest = vcpu->arch.dr6;
42dbaa5a 1146 else
c76de350 1147 *dest = svm->vmcb->save.dr6;
42dbaa5a 1148 break;
c76de350
JK		 1149 case 5:
1150 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1151 return EMULATE_FAIL; /* will re-inject UD */
1152 /* fall through */
42dbaa5a
JK		 1153 case 7:
1154 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1155 *dest = vcpu->arch.dr7;
42dbaa5a 1156 else
c76de350 1157 *dest = svm->vmcb->save.dr7;
42dbaa5a 1158 break;
42dbaa5a
JK		 1159 }
1160
c76de350 1161 return EMULATE_DONE;
6aa8b732
AK		 1162}
1163
c76de350 1164static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1165{
a2fa3e9f
GH		 1166 struct vcpu_svm *svm = to_svm(vcpu);
1167
6aa8b732
AK		 1168 switch (dr) {
1169 case 0 ... 3:
42dbaa5a
JK		 1170 vcpu->arch.db[dr] = value;
1171 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1172 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1173 break;
1174 case 4:
1175 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1176 return EMULATE_FAIL; /* will re-inject UD */
1177 /* fall through */
42dbaa5a 1178 case 6:
42dbaa5a 1179 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1180 break;
1181 case 5:
1182 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1183 return EMULATE_FAIL; /* will re-inject UD */
1184 /* fall through */
42dbaa5a 1185 case 7:
42dbaa5a
JK		 1186 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1187 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1188 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1189 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1190 }
c76de350 1191 break;
6aa8b732 1192 }
c76de350
JK		 1193
1194 return EMULATE_DONE;
6aa8b732
AK		 1195}
1196
851ba692 1197static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1198{
6aa8b732
AK		 1199 u64 fault_address;
1200 u32 error_code;
6aa8b732 1201
a2fa3e9f
GH		 1202 fault_address = svm->vmcb->control.exit_info_2;
1203 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1204
229456fc 1205 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1206 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1207 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1208 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1209}
1210
851ba692 1211static int db_interception(struct vcpu_svm *svm)
d0bfb940 1212{
851ba692
AK		 1213 struct kvm_run *kvm_run = svm->vcpu.run;
1214
d0bfb940 1215 if (!(svm->vcpu.guest_debug &
44c11430 1216 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1217 !svm->nmi_singlestep) {
d0bfb940
JK		 1218 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1219 return 1;
1220 }
44c11430 1221
6be7d306
JK		 1222 if (svm->nmi_singlestep) {
1223 svm->nmi_singlestep = false;
44c11430
GN		 1224 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1225 svm->vmcb->save.rflags &=
1226 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1227 update_db_intercept(&svm->vcpu);
1228 }
1229
1230 if (svm->vcpu.guest_debug &
1231 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1232 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1233 kvm_run->debug.arch.pc =
1234 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1235 kvm_run->debug.arch.exception = DB_VECTOR;
1236 return 0;
1237 }
1238
1239 return 1;
d0bfb940
JK		 1240}
1241
851ba692 1242static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1243{
851ba692
AK		 1244 struct kvm_run *kvm_run = svm->vcpu.run;
1245
d0bfb940
JK		 1246 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1247 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1248 kvm_run->debug.arch.exception = BP_VECTOR;
1249 return 0;
1250}
1251
851ba692 1252static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1253{
1254 int er;
1255
851ba692 1256 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1257 if (er != EMULATE_DONE)
7ee5d940 1258 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1259 return 1;
1260}
1261
6b52d186 1262static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1263{
6b52d186 1264 struct vcpu_svm *svm = to_svm(vcpu);
a2fa3e9f 1265 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
e756fc62 1266 svm->vcpu.fpu_active = 1;
d225157b 1267 update_cr0_intercept(svm);
6b52d186 1268}
a2fa3e9f 1269
6b52d186
AK		 1270static int nm_interception(struct vcpu_svm *svm)
1271{
1272 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1273 return 1;
7807fa6c
AL		 1274}
1275
851ba692 1276static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1277{
1278 /*
1279 * On an #MC intercept the MCE handler is not called automatically in
1280 * the host. So do it by hand here.
1281 */
1282 asm volatile (
1283 "int $0x12\n");
1284 /* not sure if we ever come back to this point */
1285
1286 return 1;
1287}
1288
851ba692 1289static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1290{
851ba692
AK		 1291 struct kvm_run *kvm_run = svm->vcpu.run;
1292
46fe4ddd
JR		 1293 /*
1294 * VMCB is undefined after a SHUTDOWN intercept
1295 * so reinitialize it.
1296 */
a2fa3e9f 1297 clear_page(svm->vmcb);
e6101a96 1298 init_vmcb(svm);
46fe4ddd
JR		 1299
1300 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1301 return 0;
1302}
1303
851ba692 1304static int io_interception(struct vcpu_svm *svm)
6aa8b732 1305{
d77c26fc 1306 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1307 int size, in, string;
039576c0 1308 unsigned port;
6aa8b732 1309
e756fc62 1310 ++svm->vcpu.stat.io_exits;
6aa8b732 1311
a2fa3e9f 1312 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1313
e70669ab
LV		 1314 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1315
1316 if (string) {
3427318f 1317 if (emulate_instruction(&svm->vcpu,
851ba692 1318 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1319 return 0;
1320 return 1;
1321 }
1322
039576c0
AK		 1323 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1324 port = io_info >> 16;
1325 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1326
e93f36bc 1327 skip_emulated_instruction(&svm->vcpu);
851ba692 1328 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1329}
1330
851ba692 1331static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1332{
1333 return 1;
1334}
1335
851ba692 1336static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1337{
1338 ++svm->vcpu.stat.irq_exits;
1339 return 1;
1340}
1341
851ba692 1342static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1343{
1344 return 1;
1345}
1346
851ba692 1347static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1348{
5fdbf976 1349 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1350 skip_emulated_instruction(&svm->vcpu);
1351 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1352}
1353
851ba692 1354static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1355{
5fdbf976 1356 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1357 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1358 kvm_emulate_hypercall(&svm->vcpu);
1359 return 1;
02e235bc
AK		 1360}
1361
c0725420
AG		 1362static int nested_svm_check_permissions(struct vcpu_svm *svm)
1363{
1364 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1365 || !is_paging(&svm->vcpu)) {
1366 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1367 return 1;
1368 }
1369
1370 if (svm->vmcb->save.cpl) {
1371 kvm_inject_gp(&svm->vcpu, 0);
1372 return 1;
1373 }
1374
1375 return 0;
1376}
1377
cf74a78b
AG		 1378static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1379 bool has_error_code, u32 error_code)
1380{
0295ad7d
JR		 1381 if (!is_nested(svm))
1382 return 0;
cf74a78b 1383
0295ad7d
JR		 1384 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1385 svm->vmcb->control.exit_code_hi = 0;
1386 svm->vmcb->control.exit_info_1 = error_code;
1387 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1388
410e4d57 1389 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1390}
1391
1392static inline int nested_svm_intr(struct vcpu_svm *svm)
1393{
26666957
JR		 1394 if (!is_nested(svm))
1395 return 0;
cf74a78b 1396
26666957
JR		 1397 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1398 return 0;
cf74a78b 1399
26666957
JR		 1400 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1401 return 0;
cf74a78b 1402
26666957
JR		 1403 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1404
cd3ff653
JR		 1405 if (svm->nested.intercept & 1ULL) {
1406 /*
1407 * The #vmexit can't be emulated here directly because this
1408 * code path runs with irqs and preemtion disabled. A
1409 * #vmexit emulation might sleep. Only signal request for
1410 * the #vmexit here.
1411 */
1412 svm->nested.exit_required = true;
236649de 1413 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1414 return 1;
cf74a78b
AG		 1415 }
1416
1417 return 0;
1418}
1419
34f80cfa
JR		 1420static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1421{
1422 struct page *page;
1423
34f80cfa 1424 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1425 if (is_error_page(page))
1426 goto error;
1427
1428 return kmap_atomic(page, idx);
1429
1430error:
1431 kvm_release_page_clean(page);
1432 kvm_inject_gp(&svm->vcpu, 0);
1433
1434 return NULL;
1435}
1436
1437static void nested_svm_unmap(void *addr, enum km_type idx)
1438{
1439 struct page *page;
1440
1441 if (!addr)
1442 return;
1443
1444 page = kmap_atomic_to_page(addr);
1445
1446 kunmap_atomic(addr, idx);
1447 kvm_release_page_dirty(page);
1448}
1449
3d62d9aa 1450static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1451{
4c2161ae 1452 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1453 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1454 bool ret = false;
1455 u32 t0, t1;
1456 u8 *msrpm;
4c2161ae 1457
3d62d9aa
JR		 1458 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1459 return false;
1460
1461 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1462
1463 if (!msrpm)
1464 goto out;
4c2161ae
JR		 1465
1466 switch (msr) {
1467 case 0 ... 0x1fff:
1468 t0 = (msr * 2) % 8;
1469 t1 = msr / 8;
1470 break;
1471 case 0xc0000000 ... 0xc0001fff:
1472 t0 = (8192 + msr - 0xc0000000) * 2;
1473 t1 = (t0 / 8);
1474 t0 %= 8;
1475 break;
1476 case 0xc0010000 ... 0xc0011fff:
1477 t0 = (16384 + msr - 0xc0010000) * 2;
1478 t1 = (t0 / 8);
1479 t0 %= 8;
1480 break;
1481 default:
3d62d9aa
JR		 1482 ret = true;
1483 goto out;
4c2161ae 1484 }
4c2161ae 1485
3d62d9aa
JR		 1486 ret = msrpm[t1] & ((1 << param) << t0);
1487
1488out:
1489 nested_svm_unmap(msrpm, KM_USER0);
1490
1491 return ret;
4c2161ae
JR		 1492}
1493
410e4d57 1494static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1495{
cf74a78b 1496 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1497
410e4d57
JR		 1498 switch (exit_code) {
1499 case SVM_EXIT_INTR:
1500 case SVM_EXIT_NMI:
1501 return NESTED_EXIT_HOST;
cf74a78b 1502 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1503 case SVM_EXIT_NPF:
1504 if (npt_enabled)
1505 return NESTED_EXIT_HOST;
1506 break;
1507 /* When we're shadowing, trap PFs */
1508 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1509 if (!npt_enabled)
1510 return NESTED_EXIT_HOST;
1511 break;
1512 default:
1513 break;
cf74a78b
AG		 1514 }
1515
410e4d57
JR		 1516 return NESTED_EXIT_CONTINUE;
1517}
1518
1519/*
1520 * If this function returns true, this #vmexit was already handled
1521 */
1522static int nested_svm_exit_handled(struct vcpu_svm *svm)
1523{
1524 u32 exit_code = svm->vmcb->control.exit_code;
1525 int vmexit = NESTED_EXIT_HOST;
1526
cf74a78b 1527 switch (exit_code) {
9c4e40b9 1528 case SVM_EXIT_MSR:
3d62d9aa 1529 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1530 break;
cf74a78b
AG		 1531 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1532 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1533 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1534 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1535 break;
1536 }
1537 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1538 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1539 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1540 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1541 break;
1542 }
1543 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1544 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1545 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1546 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1547 break;
1548 }
1549 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1550 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1551 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1552 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1553 break;
1554 }
1555 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1556 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1557 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1558 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1559 break;
1560 }
1561 default: {
1562 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1563 if (svm->nested.intercept & exit_bits)
410e4d57 1564 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1565 }
1566 }
1567
410e4d57 1568 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1569 nested_svm_vmexit(svm);
1570 }
1571
1572 return vmexit;
cf74a78b
AG		 1573}
1574
0460a979
JR		 1575static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1576{
1577 struct vmcb_control_area *dst = &dst_vmcb->control;
1578 struct vmcb_control_area *from = &from_vmcb->control;
1579
1580 dst->intercept_cr_read = from->intercept_cr_read;
1581 dst->intercept_cr_write = from->intercept_cr_write;
1582 dst->intercept_dr_read = from->intercept_dr_read;
1583 dst->intercept_dr_write = from->intercept_dr_write;
1584 dst->intercept_exceptions = from->intercept_exceptions;
1585 dst->intercept = from->intercept;
1586 dst->iopm_base_pa = from->iopm_base_pa;
1587 dst->msrpm_base_pa = from->msrpm_base_pa;
1588 dst->tsc_offset = from->tsc_offset;
1589 dst->asid = from->asid;
1590 dst->tlb_ctl = from->tlb_ctl;
1591 dst->int_ctl = from->int_ctl;
1592 dst->int_vector = from->int_vector;
1593 dst->int_state = from->int_state;
1594 dst->exit_code = from->exit_code;
1595 dst->exit_code_hi = from->exit_code_hi;
1596 dst->exit_info_1 = from->exit_info_1;
1597 dst->exit_info_2 = from->exit_info_2;
1598 dst->exit_int_info = from->exit_int_info;
1599 dst->exit_int_info_err = from->exit_int_info_err;
1600 dst->nested_ctl = from->nested_ctl;
1601 dst->event_inj = from->event_inj;
1602 dst->event_inj_err = from->event_inj_err;
1603 dst->nested_cr3 = from->nested_cr3;
1604 dst->lbr_ctl = from->lbr_ctl;
1605}
1606
34f80cfa 1607static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1608{
34f80cfa 1609 struct vmcb *nested_vmcb;
e6aa9abd 1610 struct vmcb *hsave = svm->nested.hsave;
33740e40 1611 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1612
17897f36
JR		 1613 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1614 vmcb->control.exit_info_1,
1615 vmcb->control.exit_info_2,
1616 vmcb->control.exit_int_info,
1617 vmcb->control.exit_int_info_err);
1618
34f80cfa
JR		 1619 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1620 if (!nested_vmcb)
1621 return 1;
1622
cf74a78b 1623 /* Give the current vmcb to the guest */
33740e40
JR		 1624 disable_gif(svm);
1625
1626 nested_vmcb->save.es = vmcb->save.es;
1627 nested_vmcb->save.cs = vmcb->save.cs;
1628 nested_vmcb->save.ss = vmcb->save.ss;
1629 nested_vmcb->save.ds = vmcb->save.ds;
1630 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1631 nested_vmcb->save.idtr = vmcb->save.idtr;
1632 if (npt_enabled)
1633 nested_vmcb->save.cr3 = vmcb->save.cr3;
1634 nested_vmcb->save.cr2 = vmcb->save.cr2;
1635 nested_vmcb->save.rflags = vmcb->save.rflags;
1636 nested_vmcb->save.rip = vmcb->save.rip;
1637 nested_vmcb->save.rsp = vmcb->save.rsp;
1638 nested_vmcb->save.rax = vmcb->save.rax;
1639 nested_vmcb->save.dr7 = vmcb->save.dr7;
1640 nested_vmcb->save.dr6 = vmcb->save.dr6;
1641 nested_vmcb->save.cpl = vmcb->save.cpl;
1642
1643 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1644 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1645 nested_vmcb->control.int_state = vmcb->control.int_state;
1646 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1647 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1648 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1649 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1650 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1651 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1652
1653 /*
1654 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1655 * to make sure that we do not lose injected events. So check event_inj
1656 * here and copy it to exit_int_info if it is valid.
1657 * Exit_int_info and event_inj can't be both valid because the case
1658 * below only happens on a VMRUN instruction intercept which has
1659 * no valid exit_int_info set.
1660 */
1661 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1662 struct vmcb_control_area *nc = &nested_vmcb->control;
1663
1664 nc->exit_int_info = vmcb->control.event_inj;
1665 nc->exit_int_info_err = vmcb->control.event_inj_err;
1666 }
1667
33740e40
JR		 1668 nested_vmcb->control.tlb_ctl = 0;
1669 nested_vmcb->control.event_inj = 0;
1670 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1671
1672 /* We always set V_INTR_MASKING and remember the old value in hflags */
1673 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1674 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1675
cf74a78b 1676 /* Restore the original control entries */
0460a979 1677 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1678
219b65dc
AG		 1679 kvm_clear_exception_queue(&svm->vcpu);
1680 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1681
1682 /* Restore selected save entries */
1683 svm->vmcb->save.es = hsave->save.es;
1684 svm->vmcb->save.cs = hsave->save.cs;
1685 svm->vmcb->save.ss = hsave->save.ss;
1686 svm->vmcb->save.ds = hsave->save.ds;
1687 svm->vmcb->save.gdtr = hsave->save.gdtr;
1688 svm->vmcb->save.idtr = hsave->save.idtr;
1689 svm->vmcb->save.rflags = hsave->save.rflags;
1690 svm_set_efer(&svm->vcpu, hsave->save.efer);
1691 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1692 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1693 if (npt_enabled) {
1694 svm->vmcb->save.cr3 = hsave->save.cr3;
1695 svm->vcpu.arch.cr3 = hsave->save.cr3;
1696 } else {
1697 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1698 }
1699 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1700 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1701 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1702 svm->vmcb->save.dr7 = 0;
1703 svm->vmcb->save.cpl = 0;
1704 svm->vmcb->control.exit_int_info = 0;
1705
cf74a78b 1706 /* Exit nested SVM mode */
e6aa9abd 1707 svm->nested.vmcb = 0;
cf74a78b 1708
34f80cfa 1709 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1710
1711 kvm_mmu_reset_context(&svm->vcpu);
1712 kvm_mmu_load(&svm->vcpu);
1713
1714 return 0;
1715}
3d6368ef 1716
9738b2c9 1717static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1718{
9738b2c9 1719 u32 *nested_msrpm;
3d6368ef 1720 int i;
9738b2c9
JR		 1721
1722 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1723 if (!nested_msrpm)
1724 return false;
1725
3d6368ef 1726 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1727 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1728
e6aa9abd 1729 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1730
9738b2c9
JR		 1731 nested_svm_unmap(nested_msrpm, KM_USER0);
1732
1733 return true;
3d6368ef
AG		 1734}
1735
9738b2c9 1736static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1737{
9738b2c9 1738 struct vmcb *nested_vmcb;
e6aa9abd 1739 struct vmcb *hsave = svm->nested.hsave;
defbba56 1740 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1741
9738b2c9
JR		 1742 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1743 if (!nested_vmcb)
1744 return false;
1745
3d6368ef 1746 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1747 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1748
0ac406de
JR		 1749 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1750 nested_vmcb->save.rip,
1751 nested_vmcb->control.int_ctl,
1752 nested_vmcb->control.event_inj,
1753 nested_vmcb->control.nested_ctl);
1754
3d6368ef 1755 /* Clear internal status */
219b65dc
AG		 1756 kvm_clear_exception_queue(&svm->vcpu);
1757 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1758
1759 /* Save the old vmcb, so we don't need to pick what we save, but
1760 can restore everything when a VMEXIT occurs */
defbba56
JR		 1761 hsave->save.es = vmcb->save.es;
1762 hsave->save.cs = vmcb->save.cs;
1763 hsave->save.ss = vmcb->save.ss;
1764 hsave->save.ds = vmcb->save.ds;
1765 hsave->save.gdtr = vmcb->save.gdtr;
1766 hsave->save.idtr = vmcb->save.idtr;
1767 hsave->save.efer = svm->vcpu.arch.shadow_efer;
4d4ec087 1768 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1769 hsave->save.cr4 = svm->vcpu.arch.cr4;
1770 hsave->save.rflags = vmcb->save.rflags;
1771 hsave->save.rip = svm->next_rip;
1772 hsave->save.rsp = vmcb->save.rsp;
1773 hsave->save.rax = vmcb->save.rax;
1774 if (npt_enabled)
1775 hsave->save.cr3 = vmcb->save.cr3;
1776 else
1777 hsave->save.cr3 = svm->vcpu.arch.cr3;
1778
0460a979 1779 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1780
1781 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1782 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1783 else
1784 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1785
1786 /* Load the nested guest state */
1787 svm->vmcb->save.es = nested_vmcb->save.es;
1788 svm->vmcb->save.cs = nested_vmcb->save.cs;
1789 svm->vmcb->save.ss = nested_vmcb->save.ss;
1790 svm->vmcb->save.ds = nested_vmcb->save.ds;
1791 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1792 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1793 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1794 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1795 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1796 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1797 if (npt_enabled) {
1798 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1799 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1800 } else {
1801 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1802 kvm_mmu_reset_context(&svm->vcpu);
1803 }
defbba56 1804 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1805 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1806 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1807 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1808 /* In case we don't even reach vcpu_run, the fields are not updated */
1809 svm->vmcb->save.rax = nested_vmcb->save.rax;
1810 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1811 svm->vmcb->save.rip = nested_vmcb->save.rip;
1812 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1813 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1814 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1815
1816 /* We don't want a nested guest to be more powerful than the guest,
1817 so all intercepts are ORed */
1818 svm->vmcb->control.intercept_cr_read |=
1819 nested_vmcb->control.intercept_cr_read;
1820 svm->vmcb->control.intercept_cr_write |=
1821 nested_vmcb->control.intercept_cr_write;
1822 svm->vmcb->control.intercept_dr_read |=
1823 nested_vmcb->control.intercept_dr_read;
1824 svm->vmcb->control.intercept_dr_write |=
1825 nested_vmcb->control.intercept_dr_write;
1826 svm->vmcb->control.intercept_exceptions |=
1827 nested_vmcb->control.intercept_exceptions;
1828
1829 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1830
e6aa9abd 1831 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1832
aad42c64
JR		 1833 /* cache intercepts */
1834 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1835 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1836 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1837 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1838 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1839 svm->nested.intercept = nested_vmcb->control.intercept;
1840
3d6368ef 1841 force_new_asid(&svm->vcpu);
3d6368ef 1842 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1843 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1844 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1845 else
1846 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1847
3d6368ef
AG		 1848 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1849 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1850 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1851 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1852 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1853
9738b2c9
JR		 1854 nested_svm_unmap(nested_vmcb, KM_USER0);
1855
2af9194d 1856 enable_gif(svm);
3d6368ef 1857
9738b2c9 1858 return true;
3d6368ef
AG		 1859}
1860
9966bf68 1861static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1862{
1863 to_vmcb->save.fs = from_vmcb->save.fs;
1864 to_vmcb->save.gs = from_vmcb->save.gs;
1865 to_vmcb->save.tr = from_vmcb->save.tr;
1866 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1867 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1868 to_vmcb->save.star = from_vmcb->save.star;
1869 to_vmcb->save.lstar = from_vmcb->save.lstar;
1870 to_vmcb->save.cstar = from_vmcb->save.cstar;
1871 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1872 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1873 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1874 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1875}
1876
851ba692 1877static int vmload_interception(struct vcpu_svm *svm)
5542675b 1878{
9966bf68
JR		 1879 struct vmcb *nested_vmcb;
1880
5542675b
AG		 1881 if (nested_svm_check_permissions(svm))
1882 return 1;
1883
1884 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1885 skip_emulated_instruction(&svm->vcpu);
1886
9966bf68
JR		 1887 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1888 if (!nested_vmcb)
1889 return 1;
1890
1891 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1892 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1893
1894 return 1;
1895}
1896
851ba692 1897static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1898{
9966bf68
JR		 1899 struct vmcb *nested_vmcb;
1900
5542675b
AG		 1901 if (nested_svm_check_permissions(svm))
1902 return 1;
1903
1904 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1905 skip_emulated_instruction(&svm->vcpu);
1906
9966bf68
JR		 1907 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1908 if (!nested_vmcb)
1909 return 1;
1910
1911 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1912 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1913
1914 return 1;
1915}
1916
851ba692 1917static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1918{
3d6368ef
AG		 1919 if (nested_svm_check_permissions(svm))
1920 return 1;
1921
1922 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1923 skip_emulated_instruction(&svm->vcpu);
1924
9738b2c9 1925 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1926 return 1;
1927
9738b2c9 1928 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1929 goto failed;
1930
1931 return 1;
1932
1933failed:
1934
1935 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1936 svm->vmcb->control.exit_code_hi = 0;
1937 svm->vmcb->control.exit_info_1 = 0;
1938 svm->vmcb->control.exit_info_2 = 0;
1939
1940 nested_svm_vmexit(svm);
3d6368ef
AG		 1941
1942 return 1;
1943}
1944
851ba692 1945static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1946{
1947 if (nested_svm_check_permissions(svm))
1948 return 1;
1949
1950 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1951 skip_emulated_instruction(&svm->vcpu);
1952
2af9194d 1953 enable_gif(svm);
1371d904
AG		 1954
1955 return 1;
1956}
1957
851ba692 1958static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1959{
1960 if (nested_svm_check_permissions(svm))
1961 return 1;
1962
1963 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1964 skip_emulated_instruction(&svm->vcpu);
1965
2af9194d 1966 disable_gif(svm);
1371d904
AG		 1967
1968 /* After a CLGI no interrupts should come */
1969 svm_clear_vintr(svm);
1970 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1971
1972 return 1;
1973}
1974
851ba692 1975static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1976{
1977 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1978
ec1ff790
JR		 1979 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1980 vcpu->arch.regs[VCPU_REGS_RAX]);
1981
ff092385
AG		 1982 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1983 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1984
1985 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1986 skip_emulated_instruction(&svm->vcpu);
1987 return 1;
1988}
1989
532a46b9
JR		 1990static int skinit_interception(struct vcpu_svm *svm)
1991{
1992 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1993
1994 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1995 return 1;
1996}
1997
851ba692 1998static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1999{
7ee5d940 2000 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2001 return 1;
2002}
2003
851ba692 2004static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2005{
37817f29 2006 u16 tss_selector;
64a7ec06
GN		 2007 int reason;
2008 int int_type = svm->vmcb->control.exit_int_info &
2009 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2010 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2011 uint32_t type =
2012 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2013 uint32_t idt_v =
2014 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2015
2016 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2017
37817f29
IE		 2018 if (svm->vmcb->control.exit_info_2 &
2019 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2020 reason = TASK_SWITCH_IRET;
2021 else if (svm->vmcb->control.exit_info_2 &
2022 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2023 reason = TASK_SWITCH_JMP;
fe8e7f83 2024 else if (idt_v)
64a7ec06
GN		 2025 reason = TASK_SWITCH_GATE;
2026 else
2027 reason = TASK_SWITCH_CALL;
2028
fe8e7f83
GN		 2029 if (reason == TASK_SWITCH_GATE) {
2030 switch (type) {
2031 case SVM_EXITINTINFO_TYPE_NMI:
2032 svm->vcpu.arch.nmi_injected = false;
2033 break;
2034 case SVM_EXITINTINFO_TYPE_EXEPT:
2035 kvm_clear_exception_queue(&svm->vcpu);
2036 break;
2037 case SVM_EXITINTINFO_TYPE_INTR:
2038 kvm_clear_interrupt_queue(&svm->vcpu);
2039 break;
2040 default:
2041 break;
2042 }
2043 }
64a7ec06 2044
8317c298
GN		 2045 if (reason != TASK_SWITCH_GATE ||
2046 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2047 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2048 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2049 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2050
2051 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2052}
2053
851ba692 2054static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2055{
5fdbf976 2056 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2057 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2058 return 1;
6aa8b732
AK		 2059}
2060
851ba692 2061static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2062{
2063 ++svm->vcpu.stat.nmi_window_exits;
2064 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2065 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2066 return 1;
2067}
2068
851ba692 2069static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2070{
851ba692 2071 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2072 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2073 return 1;
2074}
2075
851ba692 2076static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2077{
851ba692 2078 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2079 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2080 return 1;
2081}
2082
851ba692 2083static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2084{
851ba692
AK		 2085 struct kvm_run *kvm_run = svm->vcpu.run;
2086
0a5fff19
GN		 2087 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2088 /* instruction emulation calls kvm_set_cr8() */
851ba692 2089 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2090 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2091 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2092 return 1;
95ba8273 2093 }
0a5fff19
GN		 2094 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2095 return 1;
1d075434
JR		 2096 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2097 return 0;
2098}
2099
6aa8b732
AK		 2100static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2101{
a2fa3e9f
GH		 2102 struct vcpu_svm *svm = to_svm(vcpu);
2103
6aa8b732 2104 switch (ecx) {
af24a4e4 2105 case MSR_IA32_TSC: {
20824f30 2106 u64 tsc_offset;
6aa8b732 2107
20824f30
JR		 2108 if (is_nested(svm))
2109 tsc_offset = svm->nested.hsave->control.tsc_offset;
2110 else
2111 tsc_offset = svm->vmcb->control.tsc_offset;
2112
2113 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2114 break;
2115 }
0e859cac 2116 case MSR_K6_STAR:
a2fa3e9f 2117 *data = svm->vmcb->save.star;
6aa8b732 2118 break;
0e859cac 2119#ifdef CONFIG_X86_64
6aa8b732 2120 case MSR_LSTAR:
a2fa3e9f 2121 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2122 break;
2123 case MSR_CSTAR:
a2fa3e9f 2124 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2125 break;
2126 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2127 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2128 break;
2129 case MSR_SYSCALL_MASK:
a2fa3e9f 2130 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2131 break;
2132#endif
2133 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2134 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2135 break;
2136 case MSR_IA32_SYSENTER_EIP:
017cb99e 2137 *data = svm->sysenter_eip;
6aa8b732
AK		 2138 break;
2139 case MSR_IA32_SYSENTER_ESP:
017cb99e 2140 *data = svm->sysenter_esp;
6aa8b732 2141 break;
a2938c80
JR		 2142 /* Nobody will change the following 5 values in the VMCB so
2143 we can safely return them on rdmsr. They will always be 0
2144 until LBRV is implemented. */
2145 case MSR_IA32_DEBUGCTLMSR:
2146 *data = svm->vmcb->save.dbgctl;
2147 break;
2148 case MSR_IA32_LASTBRANCHFROMIP:
2149 *data = svm->vmcb->save.br_from;
2150 break;
2151 case MSR_IA32_LASTBRANCHTOIP:
2152 *data = svm->vmcb->save.br_to;
2153 break;
2154 case MSR_IA32_LASTINTFROMIP:
2155 *data = svm->vmcb->save.last_excp_from;
2156 break;
2157 case MSR_IA32_LASTINTTOIP:
2158 *data = svm->vmcb->save.last_excp_to;
2159 break;
b286d5d8 2160 case MSR_VM_HSAVE_PA:
e6aa9abd 2161 *data = svm->nested.hsave_msr;
b286d5d8 2162 break;
eb6f302e
JR		 2163 case MSR_VM_CR:
2164 *data = 0;
2165 break;
c8a73f18
AG		 2166 case MSR_IA32_UCODE_REV:
2167 *data = 0x01000065;
2168 break;
6aa8b732 2169 default:
3bab1f5d 2170 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2171 }
2172 return 0;
2173}
2174
851ba692 2175static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2176{
ad312c7c 2177 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2178 u64 data;
2179
e756fc62 2180 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2181 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2182 else {
229456fc 2183 trace_kvm_msr_read(ecx, data);
af9ca2d7 2184
5fdbf976 2185 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2186 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2187 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2188 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2189 }
2190 return 1;
2191}
2192
2193static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2194{
a2fa3e9f
GH		 2195 struct vcpu_svm *svm = to_svm(vcpu);
2196
6aa8b732 2197 switch (ecx) {
af24a4e4 2198 case MSR_IA32_TSC: {
20824f30
JR		 2199 u64 tsc_offset = data - native_read_tsc();
2200 u64 g_tsc_offset = 0;
2201
2202 if (is_nested(svm)) {
2203 g_tsc_offset = svm->vmcb->control.tsc_offset -
2204 svm->nested.hsave->control.tsc_offset;
2205 svm->nested.hsave->control.tsc_offset = tsc_offset;
2206 }
2207
2208 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2209
6aa8b732
AK		 2210 break;
2211 }
0e859cac 2212 case MSR_K6_STAR:
a2fa3e9f 2213 svm->vmcb->save.star = data;
6aa8b732 2214 break;
49b14f24 2215#ifdef CONFIG_X86_64
6aa8b732 2216 case MSR_LSTAR:
a2fa3e9f 2217 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2218 break;
2219 case MSR_CSTAR:
a2fa3e9f 2220 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2221 break;
2222 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2223 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2224 break;
2225 case MSR_SYSCALL_MASK:
a2fa3e9f 2226 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2227 break;
2228#endif
2229 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2230 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2231 break;
2232 case MSR_IA32_SYSENTER_EIP:
017cb99e 2233 svm->sysenter_eip = data;
a2fa3e9f 2234 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2235 break;
2236 case MSR_IA32_SYSENTER_ESP:
017cb99e 2237 svm->sysenter_esp = data;
a2fa3e9f 2238 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2239 break;
a2938c80 2240 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2241 if (!svm_has(SVM_FEATURE_LBRV)) {
2242 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2243 __func__, data);
24e09cbf
JR		 2244 break;
2245 }
2246 if (data & DEBUGCTL_RESERVED_BITS)
2247 return 1;
2248
2249 svm->vmcb->save.dbgctl = data;
2250 if (data & (1ULL<<0))
2251 svm_enable_lbrv(svm);
2252 else
2253 svm_disable_lbrv(svm);
a2938c80 2254 break;
b286d5d8 2255 case MSR_VM_HSAVE_PA:
e6aa9abd 2256 svm->nested.hsave_msr = data;
62b9abaa 2257 break;
3c5d0a44
AG		 2258 case MSR_VM_CR:
2259 case MSR_VM_IGNNE:
3c5d0a44
AG		 2260 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2261 break;
6aa8b732 2262 default:
3bab1f5d 2263 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2264 }
2265 return 0;
2266}
2267
851ba692 2268static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2269{
ad312c7c 2270 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2271 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2272 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2273
229456fc 2274 trace_kvm_msr_write(ecx, data);
af9ca2d7 2275
5fdbf976 2276 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2277 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2278 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2279 else
e756fc62 2280 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2281 return 1;
2282}
2283
851ba692 2284static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2285{
e756fc62 2286 if (svm->vmcb->control.exit_info_1)
851ba692 2287 return wrmsr_interception(svm);
6aa8b732 2288 else
851ba692 2289 return rdmsr_interception(svm);
6aa8b732
AK		 2290}
2291
851ba692 2292static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2293{
851ba692
AK		 2294 struct kvm_run *kvm_run = svm->vcpu.run;
2295
f0b85051 2296 svm_clear_vintr(svm);
85f455f7 2297 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2298 /*
2299 * If the user space waits to inject interrupts, exit as soon as
2300 * possible
2301 */
8061823a
GN		 2302 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2303 kvm_run->request_interrupt_window &&
2304 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2305 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2306 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2307 return 0;
2308 }
2309
2310 return 1;
2311}
2312
565d0998
ML		 2313static int pause_interception(struct vcpu_svm *svm)
2314{
2315 kvm_vcpu_on_spin(&(svm->vcpu));
2316 return 1;
2317}
2318
851ba692 2319static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2320 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2321 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2322 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2323 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2324 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2325 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2326 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2327 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2328 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2329 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2330 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2331 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2332 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2333 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2334 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2335 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2336 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2337 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2338 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2339 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2340 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2341 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2342 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2343 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2344 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2345 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2346 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2347 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2348 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2349 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2350 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2351 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2352 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2353 [SVM_EXIT_SMI] = nop_on_interception,
2354 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2355 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2356 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2357 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2358 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2359 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2360 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2361 [SVM_EXIT_HLT] = halt_interception,
a7052897 2362 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2363 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2364 [SVM_EXIT_IOIO] = io_interception,
2365 [SVM_EXIT_MSR] = msr_interception,
2366 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2367 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2368 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2369 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2370 [SVM_EXIT_VMLOAD] = vmload_interception,
2371 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2372 [SVM_EXIT_STGI] = stgi_interception,
2373 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2374 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2375 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2376 [SVM_EXIT_MONITOR] = invalid_op_interception,
2377 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2378 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2379};
2380
851ba692 2381static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2382{
04d2cc77 2383 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2384 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2385 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2386
229456fc 2387 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2388
cd3ff653
JR		 2389 if (unlikely(svm->nested.exit_required)) {
2390 nested_svm_vmexit(svm);
2391 svm->nested.exit_required = false;
2392
2393 return 1;
2394 }
2395
cf74a78b 2396 if (is_nested(svm)) {
410e4d57
JR		 2397 int vmexit;
2398
d8cabddf
JR		 2399 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2400 svm->vmcb->control.exit_info_1,
2401 svm->vmcb->control.exit_info_2,
2402 svm->vmcb->control.exit_int_info,
2403 svm->vmcb->control.exit_int_info_err);
2404
410e4d57
JR		 2405 vmexit = nested_svm_exit_special(svm);
2406
2407 if (vmexit == NESTED_EXIT_CONTINUE)
2408 vmexit = nested_svm_exit_handled(svm);
2409
2410 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2411 return 1;
cf74a78b
AG		 2412 }
2413
a5c3832d
JR		 2414 svm_complete_interrupts(svm);
2415
888f9f3e 2416 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2417 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2418 if (npt_enabled)
709ddebf 2419 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2420
2421 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2422 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2423 kvm_run->fail_entry.hardware_entry_failure_reason
2424 = svm->vmcb->control.exit_code;
2425 return 0;
2426 }
2427
a2fa3e9f 2428 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2429 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2430 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2431 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2432 "exit_code 0x%x\n",
b8688d51 2433 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2434 exit_code);
2435
9d8f549d 2436 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2437 || !svm_exit_handlers[exit_code]) {
6aa8b732 2438 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2439 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2440 return 0;
2441 }
2442
851ba692 2443 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2444}
2445
2446static void reload_tss(struct kvm_vcpu *vcpu)
2447{
2448 int cpu = raw_smp_processor_id();
2449
0fe1e009
TH		 2450 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2451 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2452 load_TR_desc();
2453}
2454
e756fc62 2455static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2456{
2457 int cpu = raw_smp_processor_id();
2458
0fe1e009 2459 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2460
a2fa3e9f 2461 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2462 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2463 if (svm->asid_generation != sd->asid_generation)
2464 new_asid(svm, sd);
6aa8b732
AK		 2465}
2466
95ba8273
GN		 2467static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2468{
2469 struct vcpu_svm *svm = to_svm(vcpu);
2470
2471 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2472 vcpu->arch.hflags |= HF_NMI_MASK;
2473 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2474 ++vcpu->stat.nmi_injections;
2475}
6aa8b732 2476
85f455f7 2477static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2478{
2479 struct vmcb_control_area *control;
2480
229456fc 2481 trace_kvm_inj_virq(irq);
af9ca2d7 2482
fa89a817 2483 ++svm->vcpu.stat.irq_injections;
e756fc62 2484 control = &svm->vmcb->control;
85f455f7 2485 control->int_vector = irq;
6aa8b732
AK		 2486 control->int_ctl &= ~V_INTR_PRIO_MASK;
2487 control->int_ctl |= V_IRQ_MASK |
2488 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2489}
2490
66fd3f7f 2491static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2492{
2493 struct vcpu_svm *svm = to_svm(vcpu);
2494
2af9194d 2495 BUG_ON(!(gif_set(svm)));
cf74a78b 2496
219b65dc
AG		 2497 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2498 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2499}
2500
95ba8273 2501static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2502{
2503 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2504
95ba8273 2505 if (irr == -1)
aaacfc9a
JR		 2506 return;
2507
95ba8273
GN		 2508 if (tpr >= irr)
2509 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2510}
aaacfc9a 2511
95ba8273
GN		 2512static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2513{
2514 struct vcpu_svm *svm = to_svm(vcpu);
2515 struct vmcb *vmcb = svm->vmcb;
2516 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2517 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2518}
2519
3cfc3092
JK		 2520static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2521{
2522 struct vcpu_svm *svm = to_svm(vcpu);
2523
2524 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2525}
2526
2527static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2528{
2529 struct vcpu_svm *svm = to_svm(vcpu);
2530
2531 if (masked) {
2532 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2533 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2534 } else {
2535 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2536 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2537 }
2538}
2539
78646121
GN		 2540static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2541{
2542 struct vcpu_svm *svm = to_svm(vcpu);
2543 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2544 int ret;
2545
2546 if (!gif_set(svm) ||
2547 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2548 return 0;
2549
2550 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2551
2552 if (is_nested(svm))
2553 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2554
2555 return ret;
78646121
GN		 2556}
2557
9222be18 2558static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2559{
219b65dc 2560 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2561
2562 nested_svm_intr(svm);
2563
2564 /* In case GIF=0 we can't rely on the CPU to tell us when
2565 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2566 * The next time we get that intercept, this function will be
2567 * called again though and we'll get the vintr intercept. */
2af9194d 2568 if (gif_set(svm)) {
219b65dc
AG		 2569 svm_set_vintr(svm);
2570 svm_inject_irq(svm, 0x0);
2571 }
85f455f7
ED		 2572}
2573
95ba8273 2574static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2575{
04d2cc77 2576 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2577
44c11430
GN		 2578 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2579 == HF_NMI_MASK)
2580 return; /* IRET will cause a vm exit */
2581
2582 /* Something prevents NMI from been injected. Single step over
2583 possible problem (IRET or exception injection or interrupt
2584 shadow) */
6be7d306 2585 svm->nmi_singlestep = true;
44c11430
GN		 2586 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2587 update_db_intercept(vcpu);
c1150d8c
DL		 2588}
2589
cbc94022
IE		 2590static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2591{
2592 return 0;
2593}
2594
d9e368d6
AK		 2595static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2596{
2597 force_new_asid(vcpu);
2598}
2599
04d2cc77
AK		 2600static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2601{
2602}
2603
d7bf8221
JR		 2604static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2605{
2606 struct vcpu_svm *svm = to_svm(vcpu);
2607
2608 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2609 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2610 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2611 }
2612}
2613
649d6864
JR		 2614static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2615{
2616 struct vcpu_svm *svm = to_svm(vcpu);
2617 u64 cr8;
2618
649d6864
JR		 2619 cr8 = kvm_get_cr8(vcpu);
2620 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2621 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2622}
2623
9222be18
GN		 2624static void svm_complete_interrupts(struct vcpu_svm *svm)
2625{
2626 u8 vector;
2627 int type;
2628 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2629
44c11430
GN		 2630 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2631 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2632
9222be18
GN		 2633 svm->vcpu.arch.nmi_injected = false;
2634 kvm_clear_exception_queue(&svm->vcpu);
2635 kvm_clear_interrupt_queue(&svm->vcpu);
2636
2637 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2638 return;
2639
2640 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2641 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2642
2643 switch (type) {
2644 case SVM_EXITINTINFO_TYPE_NMI:
2645 svm->vcpu.arch.nmi_injected = true;
2646 break;
2647 case SVM_EXITINTINFO_TYPE_EXEPT:
2648 /* In case of software exception do not reinject an exception
2649 vector, but re-execute and instruction instead */
219b65dc
AG		 2650 if (is_nested(svm))
2651 break;
66fd3f7f 2652 if (kvm_exception_is_soft(vector))
9222be18
GN		 2653 break;
2654 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2655 u32 err = svm->vmcb->control.exit_int_info_err;
2656 kvm_queue_exception_e(&svm->vcpu, vector, err);
2657
2658 } else
2659 kvm_queue_exception(&svm->vcpu, vector);
2660 break;
2661 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2662 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2663 break;
2664 default:
2665 break;
2666 }
2667}
2668
80e31d4f
AK		 2669#ifdef CONFIG_X86_64
2670#define R "r"
2671#else
2672#define R "e"
2673#endif
2674
851ba692 2675static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2676{
a2fa3e9f 2677 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2678 u16 fs_selector;
2679 u16 gs_selector;
2680 u16 ldt_selector;
d9e368d6 2681
cd3ff653
JR		 2682 /*
2683 * A vmexit emulation is required before the vcpu can be executed
2684 * again.
2685 */
2686 if (unlikely(svm->nested.exit_required))
2687 return;
2688
5fdbf976
MT		 2689 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2690 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2691 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2692
e756fc62 2693 pre_svm_run(svm);
6aa8b732 2694
649d6864
JR		 2695 sync_lapic_to_cr8(vcpu);
2696
6aa8b732 2697 save_host_msrs(vcpu);
d6e88aec
AK		 2698 fs_selector = kvm_read_fs();
2699 gs_selector = kvm_read_gs();
2700 ldt_selector = kvm_read_ldt();
cda0ffdd 2701 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2702 /* required for live migration with NPT */
2703 if (npt_enabled)
2704 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2705
04d2cc77
AK		 2706 clgi();
2707
2708 local_irq_enable();
36241b8c 2709
6aa8b732 2710 asm volatile (
80e31d4f
AK		 2711 "push %%"R"bp; \n\t"
2712 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2713 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2714 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2715 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2716 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2717 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2718#ifdef CONFIG_X86_64
fb3f0f51
RR		 2719 "mov %c[r8](%[svm]), %%r8 \n\t"
2720 "mov %c[r9](%[svm]), %%r9 \n\t"
2721 "mov %c[r10](%[svm]), %%r10 \n\t"
2722 "mov %c[r11](%[svm]), %%r11 \n\t"
2723 "mov %c[r12](%[svm]), %%r12 \n\t"
2724 "mov %c[r13](%[svm]), %%r13 \n\t"
2725 "mov %c[r14](%[svm]), %%r14 \n\t"
2726 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2727#endif
2728
6aa8b732 2729 /* Enter guest mode */
80e31d4f
AK		 2730 "push %%"R"ax \n\t"
2731 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2732 __ex(SVM_VMLOAD) "\n\t"
2733 __ex(SVM_VMRUN) "\n\t"
2734 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2735 "pop %%"R"ax \n\t"
6aa8b732
AK		 2736
2737 /* Save guest registers, load host registers */
80e31d4f
AK		 2738 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2739 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2740 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2741 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2742 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2743 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2744#ifdef CONFIG_X86_64
fb3f0f51
RR		 2745 "mov %%r8, %c[r8](%[svm]) \n\t"
2746 "mov %%r9, %c[r9](%[svm]) \n\t"
2747 "mov %%r10, %c[r10](%[svm]) \n\t"
2748 "mov %%r11, %c[r11](%[svm]) \n\t"
2749 "mov %%r12, %c[r12](%[svm]) \n\t"
2750 "mov %%r13, %c[r13](%[svm]) \n\t"
2751 "mov %%r14, %c[r14](%[svm]) \n\t"
2752 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2753#endif
80e31d4f 2754 "pop %%"R"bp"
6aa8b732 2755 :
fb3f0f51 2756 : [svm]"a"(svm),
6aa8b732 2757 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2758 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2759 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2760 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2761 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2762 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2763 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2764#ifdef CONFIG_X86_64
ad312c7c
ZX		 2765 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2766 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2767 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2768 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2769 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2770 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2771 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2772 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2773#endif
54a08c04 2774 : "cc", "memory"
80e31d4f 2775 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2776#ifdef CONFIG_X86_64
54a08c04
LV		 2777 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2778#endif
2779 );
6aa8b732 2780
ad312c7c 2781 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2782 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2783 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2784 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2785
d6e88aec
AK		 2786 kvm_load_fs(fs_selector);
2787 kvm_load_gs(gs_selector);
2788 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2789 load_host_msrs(vcpu);
2790
2791 reload_tss(vcpu);
2792
56ba47dd
AK		 2793 local_irq_disable();
2794
2795 stgi();
2796
d7bf8221
JR		 2797 sync_cr8_to_lapic(vcpu);
2798
a2fa3e9f 2799 svm->next_rip = 0;
9222be18 2800
6de4f3ad
AK		 2801 if (npt_enabled) {
2802 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2803 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2804 }
6aa8b732
AK		 2805}
2806
80e31d4f
AK		 2807#undef R
2808
6aa8b732
AK		 2809static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2810{
a2fa3e9f
GH		 2811 struct vcpu_svm *svm = to_svm(vcpu);
2812
709ddebf
JR		 2813 if (npt_enabled) {
2814 svm->vmcb->control.nested_cr3 = root;
2815 force_new_asid(vcpu);
2816 return;
2817 }
2818
a2fa3e9f 2819 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2820 force_new_asid(vcpu);
2821}
2822
6aa8b732
AK		 2823static int is_disabled(void)
2824{
6031a61c
JR		 2825 u64 vm_cr;
2826
2827 rdmsrl(MSR_VM_CR, vm_cr);
2828 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2829 return 1;
2830
6aa8b732
AK		 2831 return 0;
2832}
2833
102d8325
IM		 2834static void
2835svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2836{
2837 /*
2838 * Patch in the VMMCALL instruction:
2839 */
2840 hypercall[0] = 0x0f;
2841 hypercall[1] = 0x01;
2842 hypercall[2] = 0xd9;
102d8325
IM		 2843}
2844
002c7f7c
YS		 2845static void svm_check_processor_compat(void *rtn)
2846{
2847 *(int *)rtn = 0;
2848}
2849
774ead3a
AK		 2850static bool svm_cpu_has_accelerated_tpr(void)
2851{
2852 return false;
2853}
2854
67253af5
SY		 2855static int get_npt_level(void)
2856{
2857#ifdef CONFIG_X86_64
2858 return PT64_ROOT_LEVEL;
2859#else
2860 return PT32E_ROOT_LEVEL;
2861#endif
2862}
2863
4b12f0de 2864static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2865{
2866 return 0;
2867}
2868
0e851880
SY		 2869static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2870{
2871}
2872
229456fc
MT		 2873static const struct trace_print_flags svm_exit_reasons_str[] = {
2874 { SVM_EXIT_READ_CR0, "read_cr0" },
2875 { SVM_EXIT_READ_CR3, "read_cr3" },
2876 { SVM_EXIT_READ_CR4, "read_cr4" },
2877 { SVM_EXIT_READ_CR8, "read_cr8" },
2878 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2879 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2880 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2881 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2882 { SVM_EXIT_READ_DR0, "read_dr0" },
2883 { SVM_EXIT_READ_DR1, "read_dr1" },
2884 { SVM_EXIT_READ_DR2, "read_dr2" },
2885 { SVM_EXIT_READ_DR3, "read_dr3" },
2886 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2887 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2888 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2889 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2890 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2891 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2892 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2893 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2894 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2895 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2896 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2897 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2898 { SVM_EXIT_INTR, "interrupt" },
2899 { SVM_EXIT_NMI, "nmi" },
2900 { SVM_EXIT_SMI, "smi" },
2901 { SVM_EXIT_INIT, "init" },
2902 { SVM_EXIT_VINTR, "vintr" },
2903 { SVM_EXIT_CPUID, "cpuid" },
2904 { SVM_EXIT_INVD, "invd" },
2905 { SVM_EXIT_HLT, "hlt" },
2906 { SVM_EXIT_INVLPG, "invlpg" },
2907 { SVM_EXIT_INVLPGA, "invlpga" },
2908 { SVM_EXIT_IOIO, "io" },
2909 { SVM_EXIT_MSR, "msr" },
2910 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2911 { SVM_EXIT_SHUTDOWN, "shutdown" },
2912 { SVM_EXIT_VMRUN, "vmrun" },
2913 { SVM_EXIT_VMMCALL, "hypercall" },
2914 { SVM_EXIT_VMLOAD, "vmload" },
2915 { SVM_EXIT_VMSAVE, "vmsave" },
2916 { SVM_EXIT_STGI, "stgi" },
2917 { SVM_EXIT_CLGI, "clgi" },
2918 { SVM_EXIT_SKINIT, "skinit" },
2919 { SVM_EXIT_WBINVD, "wbinvd" },
2920 { SVM_EXIT_MONITOR, "monitor" },
2921 { SVM_EXIT_MWAIT, "mwait" },
2922 { SVM_EXIT_NPF, "npf" },
2923 { -1, NULL }
2924};
2925
17cc3935 2926static int svm_get_lpage_level(void)
344f414f 2927{
17cc3935 2928 return PT_PDPE_LEVEL;
344f414f
JR		 2929}
2930
4e47c7a6
SY		 2931static bool svm_rdtscp_supported(void)
2932{
2933 return false;
2934}
2935
02daab21
AK		 2936static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
2937{
2938 struct vcpu_svm *svm = to_svm(vcpu);
2939
d225157b 2940 update_cr0_intercept(svm);
02daab21 2941 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
02daab21
AK		 2942}
2943
cbdd1bea 2944static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2945 .cpu_has_kvm_support = has_svm,
2946 .disabled_by_bios = is_disabled,
2947 .hardware_setup = svm_hardware_setup,
2948 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2949 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2950 .hardware_enable = svm_hardware_enable,
2951 .hardware_disable = svm_hardware_disable,
774ead3a 2952 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2953
2954 .vcpu_create = svm_create_vcpu,
2955 .vcpu_free = svm_free_vcpu,
04d2cc77 2956 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2957
04d2cc77 2958 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2959 .vcpu_load = svm_vcpu_load,
2960 .vcpu_put = svm_vcpu_put,
2961
2962 .set_guest_debug = svm_guest_debug,
2963 .get_msr = svm_get_msr,
2964 .set_msr = svm_set_msr,
2965 .get_segment_base = svm_get_segment_base,
2966 .get_segment = svm_get_segment,
2967 .set_segment = svm_set_segment,
2e4d2653 2968 .get_cpl = svm_get_cpl,
1747fb71 2969 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 2970 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 2971 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2972 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2973 .set_cr3 = svm_set_cr3,
2974 .set_cr4 = svm_set_cr4,
2975 .set_efer = svm_set_efer,
2976 .get_idt = svm_get_idt,
2977 .set_idt = svm_set_idt,
2978 .get_gdt = svm_get_gdt,
2979 .set_gdt = svm_set_gdt,
2980 .get_dr = svm_get_dr,
2981 .set_dr = svm_set_dr,
6de4f3ad 2982 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2983 .get_rflags = svm_get_rflags,
2984 .set_rflags = svm_set_rflags,
6b52d186 2985 .fpu_activate = svm_fpu_activate,
02daab21 2986 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 2987
6aa8b732 2988 .tlb_flush = svm_flush_tlb,
6aa8b732 2989
6aa8b732 2990 .run = svm_vcpu_run,
04d2cc77 2991 .handle_exit = handle_exit,
6aa8b732 2992 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2993 .set_interrupt_shadow = svm_set_interrupt_shadow,
2994 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2995 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2996 .set_irq = svm_set_irq,
95ba8273 2997 .set_nmi = svm_inject_nmi,
298101da 2998 .queue_exception = svm_queue_exception,
78646121 2999 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3000 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3001 .get_nmi_mask = svm_get_nmi_mask,
3002 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3003 .enable_nmi_window = enable_nmi_window,
3004 .enable_irq_window = enable_irq_window,
3005 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3006
3007 .set_tss_addr = svm_set_tss_addr,
67253af5 3008 .get_tdp_level = get_npt_level,
4b12f0de 3009 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3010
3011 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3012 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3013
3014 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3015
3016 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3017};
3018
3019static int __init svm_init(void)
3020{
cb498ea2 3021 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3022 THIS_MODULE);
6aa8b732
AK		 3023}
3024
3025static void __exit svm_exit(void)
3026{
cb498ea2 3027 kvm_exit();
6aa8b732
AK		 3028}
3029
3030module_init(svm_init)
3031module_exit(svm_exit)
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