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KVM: SVM: Add tracepoint for #vmexit because intr pending
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
80b7706e 49
410e4d57
JR		 50#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
51#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
52#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
53
24e09cbf
JR		 54#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
55
c0725420
AG		 56/* Turn on to get debugging output*/
57/* #define NESTED_DEBUG */
58
59#ifdef NESTED_DEBUG
60#define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
61#else
62#define nsvm_printk(fmt, args...) do {} while(0)
63#endif
64
6c8166a7
AK		 65static const u32 host_save_user_msrs[] = {
66#ifdef CONFIG_X86_64
67 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
68 MSR_FS_BASE,
69#endif
70 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
71};
72
73#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
74
75struct kvm_vcpu;
76
e6aa9abd
JR		 77struct nested_state {
78 struct vmcb *hsave;
79 u64 hsave_msr;
80 u64 vmcb;
81
82 /* These are the merged vectors */
83 u32 *msrpm;
84
85 /* gpa pointers to the real vectors */
86 u64 vmcb_msrpm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
aad42c64
JR		 91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
e6aa9abd
JR		 99};
100
6c8166a7
AK		 101struct vcpu_svm {
102 struct kvm_vcpu vcpu;
103 struct vmcb *vmcb;
104 unsigned long vmcb_pa;
105 struct svm_cpu_data *svm_data;
106 uint64_t asid_generation;
107 uint64_t sysenter_esp;
108 uint64_t sysenter_eip;
109
110 u64 next_rip;
111
112 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
113 u64 host_gs_base;
6c8166a7
AK		 114
115 u32 *msrpm;
6c8166a7 116
e6aa9abd 117 struct nested_state nested;
6c8166a7
AK		 118};
119
709ddebf
JR		 120/* enable NPT for AMD64 and X86 with PAE */
121#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
122static bool npt_enabled = true;
123#else
e3da3acd 124static bool npt_enabled = false;
709ddebf 125#endif
6c7dac72
JR		 126static int npt = 1;
127
128module_param(npt, int, S_IRUGO);
e3da3acd 129
4b6e4dca 130static int nested = 1;
236de055
AG		 131module_param(nested, int, S_IRUGO);
132
44874f84 133static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 134static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 135
410e4d57 136static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 137static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 138static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
139 bool has_error_code, u32 error_code);
140
a2fa3e9f
GH		 141static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
142{
fb3f0f51 143 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 144}
145
3d6368ef
AG		 146static inline bool is_nested(struct vcpu_svm *svm)
147{
e6aa9abd 148 return svm->nested.vmcb;
3d6368ef
AG		 149}
150
2af9194d
JR		 151static inline void enable_gif(struct vcpu_svm *svm)
152{
153 svm->vcpu.arch.hflags |= HF_GIF_MASK;
154}
155
156static inline void disable_gif(struct vcpu_svm *svm)
157{
158 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
159}
160
161static inline bool gif_set(struct vcpu_svm *svm)
162{
163 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
164}
165
4866d5e3 166static unsigned long iopm_base;
6aa8b732
AK		 167
168struct kvm_ldttss_desc {
169 u16 limit0;
170 u16 base0;
171 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
172 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
173 u32 base3;
174 u32 zero1;
175} __attribute__((packed));
176
177struct svm_cpu_data {
178 int cpu;
179
5008fdf5
AK		 180 u64 asid_generation;
181 u32 max_asid;
182 u32 next_asid;
6aa8b732
AK		 183 struct kvm_ldttss_desc *tss_desc;
184
185 struct page *save_area;
186};
187
188static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 189static uint32_t svm_features;
6aa8b732
AK		 190
191struct svm_init_data {
192 int cpu;
193 int r;
194};
195
196static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
197
9d8f549d 198#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 199#define MSRS_RANGE_SIZE 2048
200#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
201
202#define MAX_INST_SIZE 15
203
80b7706e
JR		 204static inline u32 svm_has(u32 feat)
205{
206 return svm_features & feat;
207}
208
6aa8b732
AK		 209static inline void clgi(void)
210{
4ecac3fd 211 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 212}
213
214static inline void stgi(void)
215{
4ecac3fd 216 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 217}
218
219static inline void invlpga(unsigned long addr, u32 asid)
220{
4ecac3fd 221 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 222}
223
6aa8b732
AK		 224static inline void force_new_asid(struct kvm_vcpu *vcpu)
225{
a2fa3e9f 226 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 227}
228
229static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
230{
231 force_new_asid(vcpu);
232}
233
234static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
235{
709ddebf 236 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 237 efer &= ~EFER_LME;
6aa8b732 238
9962d032 239 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 240 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 241}
242
298101da
AK		 243static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
244 bool has_error_code, u32 error_code)
245{
246 struct vcpu_svm *svm = to_svm(vcpu);
247
cf74a78b
AG		 248 /* If we are within a nested VM we'd better #VMEXIT and let the
249 guest handle the exception */
250 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
251 return;
252
298101da
AK		 253 svm->vmcb->control.event_inj = nr
254 | SVM_EVTINJ_VALID
255 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
256 | SVM_EVTINJ_TYPE_EXEPT;
257 svm->vmcb->control.event_inj_err = error_code;
258}
259
6aa8b732
AK		 260static int is_external_interrupt(u32 info)
261{
262 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
263 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
264}
265
2809f5d2
GC		 266static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
267{
268 struct vcpu_svm *svm = to_svm(vcpu);
269 u32 ret = 0;
270
271 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
272 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
273 return ret & mask;
274}
275
276static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
277{
278 struct vcpu_svm *svm = to_svm(vcpu);
279
280 if (mask == 0)
281 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
282 else
283 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
284
285}
286
6aa8b732
AK		 287static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
288{
a2fa3e9f
GH		 289 struct vcpu_svm *svm = to_svm(vcpu);
290
291 if (!svm->next_rip) {
851ba692 292 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 293 EMULATE_DONE)
294 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 295 return;
296 }
5fdbf976
MT		 297 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
298 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
299 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 300
5fdbf976 301 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 302 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 303}
304
305static int has_svm(void)
306{
63d1142f 307 const char *msg;
6aa8b732 308
63d1142f 309 if (!cpu_has_svm(&msg)) {
ff81ff10 310 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 311 return 0;
312 }
313
6aa8b732
AK		 314 return 1;
315}
316
317static void svm_hardware_disable(void *garbage)
318{
2c8dceeb 319 cpu_svm_disable();
6aa8b732
AK		 320}
321
10474ae8 322static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 323{
324
325 struct svm_cpu_data *svm_data;
326 uint64_t efer;
b792c344 327 struct descriptor_table gdt_descr;
6aa8b732
AK		 328 struct desc_struct *gdt;
329 int me = raw_smp_processor_id();
330
10474ae8
AG		 331 rdmsrl(MSR_EFER, efer);
332 if (efer & EFER_SVME)
333 return -EBUSY;
334
6aa8b732 335 if (!has_svm()) {
e6732a5a
ZA		 336 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
337 me);
10474ae8 338 return -EINVAL;
6aa8b732
AK		 339 }
340 svm_data = per_cpu(svm_data, me);
341
342 if (!svm_data) {
e6732a5a 343 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 344 me);
10474ae8 345 return -EINVAL;
6aa8b732
AK		 346 }
347
348 svm_data->asid_generation = 1;
349 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
350 svm_data->next_asid = svm_data->max_asid + 1;
351
b792c344
AM		 352 kvm_get_gdt(&gdt_descr);
353 gdt = (struct desc_struct *)gdt_descr.base;
6aa8b732
AK		 354 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
355
9962d032 356 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732
AK		 357
358 wrmsrl(MSR_VM_HSAVE_PA,
359 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
10474ae8
AG		 360
361 return 0;
6aa8b732
AK		 362}
363
0da1db75
JR		 364static void svm_cpu_uninit(int cpu)
365{
366 struct svm_cpu_data *svm_data
367 = per_cpu(svm_data, raw_smp_processor_id());
368
369 if (!svm_data)
370 return;
371
372 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
373 __free_page(svm_data->save_area);
374 kfree(svm_data);
375}
376
6aa8b732
AK		 377static int svm_cpu_init(int cpu)
378{
379 struct svm_cpu_data *svm_data;
380 int r;
381
382 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
383 if (!svm_data)
384 return -ENOMEM;
385 svm_data->cpu = cpu;
386 svm_data->save_area = alloc_page(GFP_KERNEL);
387 r = -ENOMEM;
388 if (!svm_data->save_area)
389 goto err_1;
390
391 per_cpu(svm_data, cpu) = svm_data;
392
393 return 0;
394
395err_1:
396 kfree(svm_data);
397 return r;
398
399}
400
bfc733a7
RR		 401static void set_msr_interception(u32 *msrpm, unsigned msr,
402 int read, int write)
6aa8b732
AK		 403{
404 int i;
405
406 for (i = 0; i < NUM_MSR_MAPS; i++) {
407 if (msr >= msrpm_ranges[i] &&
408 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
409 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
410 msrpm_ranges[i]) * 2;
411
412 u32 *base = msrpm + (msr_offset / 32);
413 u32 msr_shift = msr_offset % 32;
414 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
415 *base = (*base & ~(0x3 << msr_shift)) |
416 (mask << msr_shift);
bfc733a7 417 return;
6aa8b732
AK		 418 }
419 }
bfc733a7 420 BUG();
6aa8b732
AK		 421}
422
f65c229c
JR		 423static void svm_vcpu_init_msrpm(u32 *msrpm)
424{
425 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
426
427#ifdef CONFIG_X86_64
428 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
429 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
430 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
431 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
432 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
433 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
434#endif
435 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
436 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 437}
438
24e09cbf
JR		 439static void svm_enable_lbrv(struct vcpu_svm *svm)
440{
441 u32 *msrpm = svm->msrpm;
442
443 svm->vmcb->control.lbr_ctl = 1;
444 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
445 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
446 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
447 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
448}
449
450static void svm_disable_lbrv(struct vcpu_svm *svm)
451{
452 u32 *msrpm = svm->msrpm;
453
454 svm->vmcb->control.lbr_ctl = 0;
455 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
456 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
457 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
458 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
459}
460
6aa8b732
AK		 461static __init int svm_hardware_setup(void)
462{
463 int cpu;
464 struct page *iopm_pages;
f65c229c 465 void *iopm_va;
6aa8b732
AK		 466 int r;
467
6aa8b732
AK		 468 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
469
470 if (!iopm_pages)
471 return -ENOMEM;
c8681339
AL		 472
473 iopm_va = page_address(iopm_pages);
474 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 475 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
476
50a37eb4
JR		 477 if (boot_cpu_has(X86_FEATURE_NX))
478 kvm_enable_efer_bits(EFER_NX);
479
1b2fd70c
AG		 480 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
481 kvm_enable_efer_bits(EFER_FFXSR);
482
236de055
AG		 483 if (nested) {
484 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
485 kvm_enable_efer_bits(EFER_SVME);
486 }
487
3230bb47 488 for_each_possible_cpu(cpu) {
6aa8b732
AK		 489 r = svm_cpu_init(cpu);
490 if (r)
f65c229c 491 goto err;
6aa8b732 492 }
33bd6a0b
JR		 493
494 svm_features = cpuid_edx(SVM_CPUID_FUNC);
495
e3da3acd
JR		 496 if (!svm_has(SVM_FEATURE_NPT))
497 npt_enabled = false;
498
6c7dac72
JR		 499 if (npt_enabled && !npt) {
500 printk(KERN_INFO "kvm: Nested Paging disabled\n");
501 npt_enabled = false;
502 }
503
18552672 504 if (npt_enabled) {
e3da3acd 505 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 506 kvm_enable_tdp();
5f4cb662
JR		 507 } else
508 kvm_disable_tdp();
e3da3acd 509
6aa8b732
AK		 510 return 0;
511
f65c229c 512err:
6aa8b732
AK		 513 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
514 iopm_base = 0;
515 return r;
516}
517
518static __exit void svm_hardware_unsetup(void)
519{
0da1db75
JR		 520 int cpu;
521
3230bb47 522 for_each_possible_cpu(cpu)
0da1db75
JR		 523 svm_cpu_uninit(cpu);
524
6aa8b732 525 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 526 iopm_base = 0;
6aa8b732
AK		 527}
528
529static void init_seg(struct vmcb_seg *seg)
530{
531 seg->selector = 0;
532 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
533 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
538static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
539{
540 seg->selector = 0;
541 seg->attrib = SVM_SELECTOR_P_MASK | type;
542 seg->limit = 0xffff;
543 seg->base = 0;
544}
545
e6101a96 546static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 547{
e6101a96
JR		 548 struct vmcb_control_area *control = &svm->vmcb->control;
549 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 550
551 control->intercept_cr_read = INTERCEPT_CR0_MASK |
552 INTERCEPT_CR3_MASK |
649d6864 553 INTERCEPT_CR4_MASK;
6aa8b732
AK		 554
555 control->intercept_cr_write = INTERCEPT_CR0_MASK |
556 INTERCEPT_CR3_MASK |
80a8119c
AK		 557 INTERCEPT_CR4_MASK |
558 INTERCEPT_CR8_MASK;
6aa8b732
AK		 559
560 control->intercept_dr_read = INTERCEPT_DR0_MASK |
561 INTERCEPT_DR1_MASK |
562 INTERCEPT_DR2_MASK |
563 INTERCEPT_DR3_MASK;
564
565 control->intercept_dr_write = INTERCEPT_DR0_MASK |
566 INTERCEPT_DR1_MASK |
567 INTERCEPT_DR2_MASK |
568 INTERCEPT_DR3_MASK |
569 INTERCEPT_DR5_MASK |
570 INTERCEPT_DR7_MASK;
571
7aa81cc0 572 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 573 (1 << UD_VECTOR) |
574 (1 << MC_VECTOR);
6aa8b732
AK		 575
576
577 control->intercept = (1ULL << INTERCEPT_INTR) |
578 (1ULL << INTERCEPT_NMI) |
0152527b 579 (1ULL << INTERCEPT_SMI) |
6aa8b732 580 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 581 (1ULL << INTERCEPT_INVD) |
6aa8b732 582 (1ULL << INTERCEPT_HLT) |
a7052897 583 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 584 (1ULL << INTERCEPT_INVLPGA) |
585 (1ULL << INTERCEPT_IOIO_PROT) |
586 (1ULL << INTERCEPT_MSR_PROT) |
587 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 588 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 589 (1ULL << INTERCEPT_VMRUN) |
590 (1ULL << INTERCEPT_VMMCALL) |
591 (1ULL << INTERCEPT_VMLOAD) |
592 (1ULL << INTERCEPT_VMSAVE) |
593 (1ULL << INTERCEPT_STGI) |
594 (1ULL << INTERCEPT_CLGI) |
916ce236 595 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 596 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 597 (1ULL << INTERCEPT_MONITOR) |
598 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 599
600 control->iopm_base_pa = iopm_base;
f65c229c 601 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 602 control->tsc_offset = 0;
6aa8b732
AK		 603 control->int_ctl = V_INTR_MASKING_MASK;
604
605 init_seg(&save->es);
606 init_seg(&save->ss);
607 init_seg(&save->ds);
608 init_seg(&save->fs);
609 init_seg(&save->gs);
610
611 save->cs.selector = 0xf000;
612 /* Executable/Readable Code Segment */
613 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
614 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
615 save->cs.limit = 0xffff;
d92899a0
AK		 616 /*
617 * cs.base should really be 0xffff0000, but vmx can't handle that, so
618 * be consistent with it.
619 *
620 * Replace when we have real mode working for vmx.
621 */
622 save->cs.base = 0xf0000;
6aa8b732
AK		 623
624 save->gdtr.limit = 0xffff;
625 save->idtr.limit = 0xffff;
626
627 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
628 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
629
9962d032 630 save->efer = EFER_SVME;
d77c26fc 631 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 632 save->dr7 = 0x400;
633 save->rflags = 2;
634 save->rip = 0x0000fff0;
5fdbf976 635 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732
AK		 636
637 /*
638 * cr0 val on cpu init should be 0x60000010, we enable cpu
639 * cache by default. the orderly way is to enable cache in bios.
640 */
707d92fa 641 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
66aee91a 642 save->cr4 = X86_CR4_PAE;
6aa8b732 643 /* rdx = ?? */
709ddebf
JR		 644
645 if (npt_enabled) {
646 /* Setup VMCB for Nested Paging */
647 control->nested_ctl = 1;
a7052897
MT		 648 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
649 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 650 control->intercept_exceptions &= ~(1 << PF_VECTOR);
651 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
652 INTERCEPT_CR3_MASK);
653 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
654 INTERCEPT_CR3_MASK);
655 save->g_pat = 0x0007040600070406ULL;
656 /* enable caching because the QEMU Bios doesn't enable it */
657 save->cr0 = X86_CR0_ET;
658 save->cr3 = 0;
659 save->cr4 = 0;
660 }
a79d2f18 661 force_new_asid(&svm->vcpu);
1371d904 662
e6aa9abd 663 svm->nested.vmcb = 0;
2af9194d
JR		 664 svm->vcpu.arch.hflags = 0;
665
666 enable_gif(svm);
6aa8b732
AK		 667}
668
e00c8cf2 669static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 670{
671 struct vcpu_svm *svm = to_svm(vcpu);
672
e6101a96 673 init_vmcb(svm);
70433389 674
c5af89b6 675 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 676 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 677 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
678 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 679 }
5fdbf976
MT		 680 vcpu->arch.regs_avail = ~0;
681 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 682
683 return 0;
04d2cc77
AK		 684}
685
fb3f0f51 686static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 687{
a2fa3e9f 688 struct vcpu_svm *svm;
6aa8b732 689 struct page *page;
f65c229c 690 struct page *msrpm_pages;
b286d5d8 691 struct page *hsave_page;
3d6368ef 692 struct page *nested_msrpm_pages;
fb3f0f51 693 int err;
6aa8b732 694
c16f862d 695 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 696 if (!svm) {
697 err = -ENOMEM;
698 goto out;
699 }
700
701 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
702 if (err)
703 goto free_svm;
704
6aa8b732 705 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 706 if (!page) {
707 err = -ENOMEM;
708 goto uninit;
709 }
6aa8b732 710
f65c229c
JR		 711 err = -ENOMEM;
712 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!msrpm_pages)
714 goto uninit;
3d6368ef
AG		 715
716 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
717 if (!nested_msrpm_pages)
718 goto uninit;
719
f65c229c
JR		 720 svm->msrpm = page_address(msrpm_pages);
721 svm_vcpu_init_msrpm(svm->msrpm);
722
b286d5d8
AG		 723 hsave_page = alloc_page(GFP_KERNEL);
724 if (!hsave_page)
725 goto uninit;
e6aa9abd 726 svm->nested.hsave = page_address(hsave_page);
b286d5d8 727
e6aa9abd 728 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 729
a2fa3e9f
GH		 730 svm->vmcb = page_address(page);
731 clear_page(svm->vmcb);
732 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
733 svm->asid_generation = 0;
e6101a96 734 init_vmcb(svm);
a2fa3e9f 735
fb3f0f51
RR		 736 fx_init(&svm->vcpu);
737 svm->vcpu.fpu_active = 1;
ad312c7c 738 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 739 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 740 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 741
fb3f0f51 742 return &svm->vcpu;
36241b8c 743
fb3f0f51
RR		 744uninit:
745 kvm_vcpu_uninit(&svm->vcpu);
746free_svm:
a4770347 747 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 748out:
749 return ERR_PTR(err);
6aa8b732
AK		 750}
751
752static void svm_free_vcpu(struct kvm_vcpu *vcpu)
753{
a2fa3e9f
GH		 754 struct vcpu_svm *svm = to_svm(vcpu);
755
fb3f0f51 756 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 757 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 758 __free_page(virt_to_page(svm->nested.hsave));
759 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 760 kvm_vcpu_uninit(vcpu);
a4770347 761 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 762}
763
15ad7146 764static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 765{
a2fa3e9f 766 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 767 int i;
0cc5064d 768
0cc5064d 769 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 770 u64 delta;
0cc5064d
AK		 771
772 /*
773 * Make sure that the guest sees a monotonically
774 * increasing TSC.
775 */
e935d48e 776 delta = vcpu->arch.host_tsc - native_read_tsc();
a2fa3e9f 777 svm->vmcb->control.tsc_offset += delta;
77b1ab17
JR		 778 if (is_nested(svm))
779 svm->nested.hsave->control.tsc_offset += delta;
0cc5064d 780 vcpu->cpu = cpu;
2f599714 781 kvm_migrate_timers(vcpu);
4b656b12 782 svm->asid_generation = 0;
0cc5064d 783 }
94dfbdb3
AL		 784
785 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 786 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 787}
788
789static void svm_vcpu_put(struct kvm_vcpu *vcpu)
790{
a2fa3e9f 791 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 792 int i;
793
e1beb1d3 794 ++vcpu->stat.host_state_reload;
94dfbdb3 795 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 796 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 797
e935d48e 798 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 799}
800
6aa8b732
AK		 801static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
802{
a2fa3e9f 803 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 804}
805
806static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
807{
a2fa3e9f 808 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 809}
810
6de4f3ad
AK		 811static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
812{
813 switch (reg) {
814 case VCPU_EXREG_PDPTR:
815 BUG_ON(!npt_enabled);
816 load_pdptrs(vcpu, vcpu->arch.cr3);
817 break;
818 default:
819 BUG();
820 }
821}
822
f0b85051
AG		 823static void svm_set_vintr(struct vcpu_svm *svm)
824{
825 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
826}
827
828static void svm_clear_vintr(struct vcpu_svm *svm)
829{
830 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
831}
832
6aa8b732
AK		 833static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
834{
a2fa3e9f 835 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 836
837 switch (seg) {
838 case VCPU_SREG_CS: return &save->cs;
839 case VCPU_SREG_DS: return &save->ds;
840 case VCPU_SREG_ES: return &save->es;
841 case VCPU_SREG_FS: return &save->fs;
842 case VCPU_SREG_GS: return &save->gs;
843 case VCPU_SREG_SS: return &save->ss;
844 case VCPU_SREG_TR: return &save->tr;
845 case VCPU_SREG_LDTR: return &save->ldtr;
846 }
847 BUG();
8b6d44c7 848 return NULL;
6aa8b732
AK		 849}
850
851static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
852{
853 struct vmcb_seg *s = svm_seg(vcpu, seg);
854
855 return s->base;
856}
857
858static void svm_get_segment(struct kvm_vcpu *vcpu,
859 struct kvm_segment *var, int seg)
860{
861 struct vmcb_seg *s = svm_seg(vcpu, seg);
862
863 var->base = s->base;
864 var->limit = s->limit;
865 var->selector = s->selector;
866 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
867 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
868 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
869 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
870 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
871 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
872 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
873 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 874
19bca6ab
AP		 875 /* AMD's VMCB does not have an explicit unusable field, so emulate it
876 * for cross vendor migration purposes by "not present"
877 */
878 var->unusable = !var->present || (var->type == 0);
879
1fbdc7a5
AP		 880 switch (seg) {
881 case VCPU_SREG_CS:
882 /*
883 * SVM always stores 0 for the 'G' bit in the CS selector in
884 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
885 * Intel's VMENTRY has a check on the 'G' bit.
886 */
25022acc 887 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 888 break;
889 case VCPU_SREG_TR:
890 /*
891 * Work around a bug where the busy flag in the tr selector
892 * isn't exposed
893 */
c0d09828 894 var->type |= 0x2;
1fbdc7a5
AP		 895 break;
896 case VCPU_SREG_DS:
897 case VCPU_SREG_ES:
898 case VCPU_SREG_FS:
899 case VCPU_SREG_GS:
900 /*
901 * The accessed bit must always be set in the segment
902 * descriptor cache, although it can be cleared in the
903 * descriptor, the cached bit always remains at 1. Since
904 * Intel has a check on this, set it here to support
905 * cross-vendor migration.
906 */
907 if (!var->unusable)
908 var->type |= 0x1;
909 break;
b586eb02
AP		 910 case VCPU_SREG_SS:
911 /* On AMD CPUs sometimes the DB bit in the segment
912 * descriptor is left as 1, although the whole segment has
913 * been made unusable. Clear it here to pass an Intel VMX
914 * entry check when cross vendor migrating.
915 */
916 if (var->unusable)
917 var->db = 0;
918 break;
1fbdc7a5 919 }
6aa8b732
AK		 920}
921
2e4d2653
IE		 922static int svm_get_cpl(struct kvm_vcpu *vcpu)
923{
924 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
925
926 return save->cpl;
927}
928
6aa8b732
AK		 929static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
930{
a2fa3e9f
GH		 931 struct vcpu_svm *svm = to_svm(vcpu);
932
933 dt->limit = svm->vmcb->save.idtr.limit;
934 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 935}
936
937static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
938{
a2fa3e9f
GH		 939 struct vcpu_svm *svm = to_svm(vcpu);
940
941 svm->vmcb->save.idtr.limit = dt->limit;
942 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 943}
944
945static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
946{
a2fa3e9f
GH		 947 struct vcpu_svm *svm = to_svm(vcpu);
948
949 dt->limit = svm->vmcb->save.gdtr.limit;
950 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 951}
952
953static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
954{
a2fa3e9f
GH		 955 struct vcpu_svm *svm = to_svm(vcpu);
956
957 svm->vmcb->save.gdtr.limit = dt->limit;
958 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 959}
960
25c4c276 961static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 962{
963}
964
6aa8b732
AK		 965static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
966{
a2fa3e9f
GH		 967 struct vcpu_svm *svm = to_svm(vcpu);
968
05b3e0c2 969#ifdef CONFIG_X86_64
ad312c7c 970 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 971 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 972 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 973 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 974 }
975
d77c26fc 976 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 977 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 978 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 979 }
980 }
981#endif
709ddebf
JR		 982 if (npt_enabled)
983 goto set;
984
ad312c7c 985 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 986 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 987 vcpu->fpu_active = 1;
988 }
989
ad312c7c 990 vcpu->arch.cr0 = cr0;
707d92fa 991 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 992 if (!vcpu->fpu_active) {
993 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 994 cr0 |= X86_CR0_TS;
6b390b63 995 }
709ddebf
JR		 996set:
997 /*
998 * re-enable caching here because the QEMU bios
999 * does not do it - this results in some delay at
1000 * reboot
1001 */
1002 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1003 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 1004}
1005
1006static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1007{
6394b649 1008 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1009 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1010
1011 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1012 force_new_asid(vcpu);
6394b649 1013
ec077263
JR		 1014 vcpu->arch.cr4 = cr4;
1015 if (!npt_enabled)
1016 cr4 |= X86_CR4_PAE;
6394b649 1017 cr4 |= host_cr4_mce;
ec077263 1018 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1019}
1020
1021static void svm_set_segment(struct kvm_vcpu *vcpu,
1022 struct kvm_segment *var, int seg)
1023{
a2fa3e9f 1024 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1025 struct vmcb_seg *s = svm_seg(vcpu, seg);
1026
1027 s->base = var->base;
1028 s->limit = var->limit;
1029 s->selector = var->selector;
1030 if (var->unusable)
1031 s->attrib = 0;
1032 else {
1033 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1034 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1035 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1036 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1037 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1038 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1039 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1040 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1041 }
1042 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1043 svm->vmcb->save.cpl
1044 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1045 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1046
1047}
1048
44c11430 1049static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1050{
d0bfb940
JK		 1051 struct vcpu_svm *svm = to_svm(vcpu);
1052
d0bfb940
JK		 1053 svm->vmcb->control.intercept_exceptions &=
1054 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430
GN		 1055
1056 if (vcpu->arch.singlestep)
1057 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1058
d0bfb940
JK		 1059 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1060 if (vcpu->guest_debug &
1061 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1062 svm->vmcb->control.intercept_exceptions |=
1063 1 << DB_VECTOR;
1064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1065 svm->vmcb->control.intercept_exceptions |=
1066 1 << BP_VECTOR;
1067 } else
1068 vcpu->guest_debug = 0;
44c11430
GN		 1069}
1070
355be0b9 1071static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1072{
44c11430
GN		 1073 struct vcpu_svm *svm = to_svm(vcpu);
1074
ae675ef0
JK		 1075 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1076 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1077 else
1078 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1079
355be0b9 1080 update_db_intercept(vcpu);
6aa8b732
AK		 1081}
1082
1083static void load_host_msrs(struct kvm_vcpu *vcpu)
1084{
94dfbdb3 1085#ifdef CONFIG_X86_64
a2fa3e9f 1086 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1087#endif
6aa8b732
AK		 1088}
1089
1090static void save_host_msrs(struct kvm_vcpu *vcpu)
1091{
94dfbdb3 1092#ifdef CONFIG_X86_64
a2fa3e9f 1093 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1094#endif
6aa8b732
AK		 1095}
1096
e756fc62 1097static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
6aa8b732
AK		 1098{
1099 if (svm_data->next_asid > svm_data->max_asid) {
1100 ++svm_data->asid_generation;
1101 svm_data->next_asid = 1;
a2fa3e9f 1102 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1103 }
1104
a2fa3e9f
GH		 1105 svm->asid_generation = svm_data->asid_generation;
1106 svm->vmcb->control.asid = svm_data->next_asid++;
6aa8b732
AK		 1107}
1108
6aa8b732
AK		 1109static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1110{
42dbaa5a
JK		 1111 struct vcpu_svm *svm = to_svm(vcpu);
1112 unsigned long val;
1113
1114 switch (dr) {
1115 case 0 ... 3:
1116 val = vcpu->arch.db[dr];
1117 break;
1118 case 6:
1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 val = vcpu->arch.dr6;
1121 else
1122 val = svm->vmcb->save.dr6;
1123 break;
1124 case 7:
1125 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1126 val = vcpu->arch.dr7;
1127 else
1128 val = svm->vmcb->save.dr7;
1129 break;
1130 default:
1131 val = 0;
1132 }
1133
af9ca2d7 1134 return val;
6aa8b732
AK		 1135}
1136
1137static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1138 int *exception)
1139{
a2fa3e9f
GH		 1140 struct vcpu_svm *svm = to_svm(vcpu);
1141
42dbaa5a 1142 *exception = 0;
6aa8b732
AK		 1143
1144 switch (dr) {
1145 case 0 ... 3:
42dbaa5a
JK		 1146 vcpu->arch.db[dr] = value;
1147 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1148 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1149 return;
1150 case 4 ... 5:
42dbaa5a 1151 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1152 *exception = UD_VECTOR;
42dbaa5a
JK		 1153 return;
1154 case 6:
1155 if (value & 0xffffffff00000000ULL) {
1156 *exception = GP_VECTOR;
6aa8b732
AK		 1157 return;
1158 }
42dbaa5a
JK		 1159 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1160 return;
1161 case 7:
1162 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1163 *exception = GP_VECTOR;
1164 return;
1165 }
42dbaa5a
JK		 1166 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1167 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1168 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1169 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1170 }
6aa8b732 1171 return;
6aa8b732 1172 default:
42dbaa5a 1173 /* FIXME: Possible case? */
6aa8b732 1174 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1175 __func__, dr);
6aa8b732
AK		 1176 *exception = UD_VECTOR;
1177 return;
1178 }
1179}
1180
851ba692 1181static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1182{
6aa8b732
AK		 1183 u64 fault_address;
1184 u32 error_code;
6aa8b732 1185
a2fa3e9f
GH		 1186 fault_address = svm->vmcb->control.exit_info_2;
1187 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1188
229456fc 1189 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1190 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1191 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1192 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1193}
1194
851ba692 1195static int db_interception(struct vcpu_svm *svm)
d0bfb940 1196{
851ba692
AK		 1197 struct kvm_run *kvm_run = svm->vcpu.run;
1198
d0bfb940 1199 if (!(svm->vcpu.guest_debug &
44c11430
GN		 1200 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1201 !svm->vcpu.arch.singlestep) {
d0bfb940
JK		 1202 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1203 return 1;
1204 }
44c11430
GN		 1205
1206 if (svm->vcpu.arch.singlestep) {
1207 svm->vcpu.arch.singlestep = false;
1208 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1209 svm->vmcb->save.rflags &=
1210 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1211 update_db_intercept(&svm->vcpu);
1212 }
1213
1214 if (svm->vcpu.guest_debug &
1215 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1216 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1217 kvm_run->debug.arch.pc =
1218 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1219 kvm_run->debug.arch.exception = DB_VECTOR;
1220 return 0;
1221 }
1222
1223 return 1;
d0bfb940
JK		 1224}
1225
851ba692 1226static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1227{
851ba692
AK		 1228 struct kvm_run *kvm_run = svm->vcpu.run;
1229
d0bfb940
JK		 1230 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1231 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1232 kvm_run->debug.arch.exception = BP_VECTOR;
1233 return 0;
1234}
1235
851ba692 1236static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1237{
1238 int er;
1239
851ba692 1240 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1241 if (er != EMULATE_DONE)
7ee5d940 1242 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1243 return 1;
1244}
1245
851ba692 1246static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1247{
a2fa3e9f 1248 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1249 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1250 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1251 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1252
1253 return 1;
7807fa6c
AL		 1254}
1255
851ba692 1256static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1257{
1258 /*
1259 * On an #MC intercept the MCE handler is not called automatically in
1260 * the host. So do it by hand here.
1261 */
1262 asm volatile (
1263 "int $0x12\n");
1264 /* not sure if we ever come back to this point */
1265
1266 return 1;
1267}
1268
851ba692 1269static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1270{
851ba692
AK		 1271 struct kvm_run *kvm_run = svm->vcpu.run;
1272
46fe4ddd
JR		 1273 /*
1274 * VMCB is undefined after a SHUTDOWN intercept
1275 * so reinitialize it.
1276 */
a2fa3e9f 1277 clear_page(svm->vmcb);
e6101a96 1278 init_vmcb(svm);
46fe4ddd
JR		 1279
1280 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1281 return 0;
1282}
1283
851ba692 1284static int io_interception(struct vcpu_svm *svm)
6aa8b732 1285{
d77c26fc 1286 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1287 int size, in, string;
039576c0 1288 unsigned port;
6aa8b732 1289
e756fc62 1290 ++svm->vcpu.stat.io_exits;
6aa8b732 1291
a2fa3e9f 1292 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1293
e70669ab
LV		 1294 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1295
1296 if (string) {
3427318f 1297 if (emulate_instruction(&svm->vcpu,
851ba692 1298 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1299 return 0;
1300 return 1;
1301 }
1302
039576c0
AK		 1303 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1304 port = io_info >> 16;
1305 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1306
e93f36bc 1307 skip_emulated_instruction(&svm->vcpu);
851ba692 1308 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1309}
1310
851ba692 1311static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1312{
1313 return 1;
1314}
1315
851ba692 1316static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1317{
1318 ++svm->vcpu.stat.irq_exits;
1319 return 1;
1320}
1321
851ba692 1322static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1323{
1324 return 1;
1325}
1326
851ba692 1327static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1328{
5fdbf976 1329 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1330 skip_emulated_instruction(&svm->vcpu);
1331 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1332}
1333
851ba692 1334static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1335{
5fdbf976 1336 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1337 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1338 kvm_emulate_hypercall(&svm->vcpu);
1339 return 1;
02e235bc
AK		 1340}
1341
c0725420
AG		 1342static int nested_svm_check_permissions(struct vcpu_svm *svm)
1343{
1344 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1345 || !is_paging(&svm->vcpu)) {
1346 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1347 return 1;
1348 }
1349
1350 if (svm->vmcb->save.cpl) {
1351 kvm_inject_gp(&svm->vcpu, 0);
1352 return 1;
1353 }
1354
1355 return 0;
1356}
1357
cf74a78b
AG		 1358static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1359 bool has_error_code, u32 error_code)
1360{
0295ad7d
JR		 1361 if (!is_nested(svm))
1362 return 0;
cf74a78b 1363
0295ad7d
JR		 1364 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1365 svm->vmcb->control.exit_code_hi = 0;
1366 svm->vmcb->control.exit_info_1 = error_code;
1367 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1368
410e4d57 1369 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1370}
1371
1372static inline int nested_svm_intr(struct vcpu_svm *svm)
1373{
26666957
JR		 1374 if (!is_nested(svm))
1375 return 0;
cf74a78b 1376
26666957
JR		 1377 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1378 return 0;
cf74a78b 1379
26666957
JR		 1380 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1381 return 0;
cf74a78b 1382
26666957
JR		 1383 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1384
cd3ff653
JR		 1385 if (svm->nested.intercept & 1ULL) {
1386 /*
1387 * The #vmexit can't be emulated here directly because this
1388 * code path runs with irqs and preemtion disabled. A
1389 * #vmexit emulation might sleep. Only signal request for
1390 * the #vmexit here.
1391 */
1392 svm->nested.exit_required = true;
236649de 1393 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1394 return 1;
cf74a78b
AG		 1395 }
1396
1397 return 0;
1398}
1399
34f80cfa
JR		 1400static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1401{
1402 struct page *page;
1403
34f80cfa 1404 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1405 if (is_error_page(page))
1406 goto error;
1407
1408 return kmap_atomic(page, idx);
1409
1410error:
1411 kvm_release_page_clean(page);
1412 kvm_inject_gp(&svm->vcpu, 0);
1413
1414 return NULL;
1415}
1416
1417static void nested_svm_unmap(void *addr, enum km_type idx)
1418{
1419 struct page *page;
1420
1421 if (!addr)
1422 return;
1423
1424 page = kmap_atomic_to_page(addr);
1425
1426 kunmap_atomic(addr, idx);
1427 kvm_release_page_dirty(page);
1428}
1429
3d62d9aa 1430static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1431{
4c2161ae 1432 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1433 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1434 bool ret = false;
1435 u32 t0, t1;
1436 u8 *msrpm;
4c2161ae 1437
3d62d9aa
JR		 1438 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1439 return false;
1440
1441 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1442
1443 if (!msrpm)
1444 goto out;
4c2161ae
JR		 1445
1446 switch (msr) {
1447 case 0 ... 0x1fff:
1448 t0 = (msr * 2) % 8;
1449 t1 = msr / 8;
1450 break;
1451 case 0xc0000000 ... 0xc0001fff:
1452 t0 = (8192 + msr - 0xc0000000) * 2;
1453 t1 = (t0 / 8);
1454 t0 %= 8;
1455 break;
1456 case 0xc0010000 ... 0xc0011fff:
1457 t0 = (16384 + msr - 0xc0010000) * 2;
1458 t1 = (t0 / 8);
1459 t0 %= 8;
1460 break;
1461 default:
3d62d9aa
JR		 1462 ret = true;
1463 goto out;
4c2161ae 1464 }
4c2161ae 1465
3d62d9aa
JR		 1466 ret = msrpm[t1] & ((1 << param) << t0);
1467
1468out:
1469 nested_svm_unmap(msrpm, KM_USER0);
1470
1471 return ret;
4c2161ae
JR		 1472}
1473
410e4d57 1474static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1475{
cf74a78b 1476 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1477
410e4d57
JR		 1478 switch (exit_code) {
1479 case SVM_EXIT_INTR:
1480 case SVM_EXIT_NMI:
1481 return NESTED_EXIT_HOST;
cf74a78b 1482 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1483 case SVM_EXIT_NPF:
1484 if (npt_enabled)
1485 return NESTED_EXIT_HOST;
1486 break;
1487 /* When we're shadowing, trap PFs */
1488 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1489 if (!npt_enabled)
1490 return NESTED_EXIT_HOST;
1491 break;
1492 default:
1493 break;
cf74a78b
AG		 1494 }
1495
410e4d57
JR		 1496 return NESTED_EXIT_CONTINUE;
1497}
1498
1499/*
1500 * If this function returns true, this #vmexit was already handled
1501 */
1502static int nested_svm_exit_handled(struct vcpu_svm *svm)
1503{
1504 u32 exit_code = svm->vmcb->control.exit_code;
1505 int vmexit = NESTED_EXIT_HOST;
1506
cf74a78b 1507 switch (exit_code) {
9c4e40b9 1508 case SVM_EXIT_MSR:
3d62d9aa 1509 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1510 break;
cf74a78b
AG		 1511 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1512 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1513 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1514 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1515 break;
1516 }
1517 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1518 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1519 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1520 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1521 break;
1522 }
1523 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1524 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1525 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1526 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1527 break;
1528 }
1529 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1530 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1531 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1532 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1533 break;
1534 }
1535 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1536 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1537 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1538 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1539 break;
1540 }
1541 default: {
1542 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1543 nsvm_printk("exit code: 0x%x\n", exit_code);
aad42c64 1544 if (svm->nested.intercept & exit_bits)
410e4d57 1545 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1546 }
1547 }
1548
410e4d57 1549 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1550 nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
1551 nested_svm_vmexit(svm);
1552 }
1553
1554 return vmexit;
cf74a78b
AG		 1555}
1556
0460a979
JR		 1557static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1558{
1559 struct vmcb_control_area *dst = &dst_vmcb->control;
1560 struct vmcb_control_area *from = &from_vmcb->control;
1561
1562 dst->intercept_cr_read = from->intercept_cr_read;
1563 dst->intercept_cr_write = from->intercept_cr_write;
1564 dst->intercept_dr_read = from->intercept_dr_read;
1565 dst->intercept_dr_write = from->intercept_dr_write;
1566 dst->intercept_exceptions = from->intercept_exceptions;
1567 dst->intercept = from->intercept;
1568 dst->iopm_base_pa = from->iopm_base_pa;
1569 dst->msrpm_base_pa = from->msrpm_base_pa;
1570 dst->tsc_offset = from->tsc_offset;
1571 dst->asid = from->asid;
1572 dst->tlb_ctl = from->tlb_ctl;
1573 dst->int_ctl = from->int_ctl;
1574 dst->int_vector = from->int_vector;
1575 dst->int_state = from->int_state;
1576 dst->exit_code = from->exit_code;
1577 dst->exit_code_hi = from->exit_code_hi;
1578 dst->exit_info_1 = from->exit_info_1;
1579 dst->exit_info_2 = from->exit_info_2;
1580 dst->exit_int_info = from->exit_int_info;
1581 dst->exit_int_info_err = from->exit_int_info_err;
1582 dst->nested_ctl = from->nested_ctl;
1583 dst->event_inj = from->event_inj;
1584 dst->event_inj_err = from->event_inj_err;
1585 dst->nested_cr3 = from->nested_cr3;
1586 dst->lbr_ctl = from->lbr_ctl;
1587}
1588
34f80cfa 1589static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1590{
34f80cfa 1591 struct vmcb *nested_vmcb;
e6aa9abd 1592 struct vmcb *hsave = svm->nested.hsave;
33740e40 1593 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1594
17897f36
JR		 1595 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1596 vmcb->control.exit_info_1,
1597 vmcb->control.exit_info_2,
1598 vmcb->control.exit_int_info,
1599 vmcb->control.exit_int_info_err);
1600
34f80cfa
JR		 1601 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1602 if (!nested_vmcb)
1603 return 1;
1604
cf74a78b 1605 /* Give the current vmcb to the guest */
33740e40
JR		 1606 disable_gif(svm);
1607
1608 nested_vmcb->save.es = vmcb->save.es;
1609 nested_vmcb->save.cs = vmcb->save.cs;
1610 nested_vmcb->save.ss = vmcb->save.ss;
1611 nested_vmcb->save.ds = vmcb->save.ds;
1612 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1613 nested_vmcb->save.idtr = vmcb->save.idtr;
1614 if (npt_enabled)
1615 nested_vmcb->save.cr3 = vmcb->save.cr3;
1616 nested_vmcb->save.cr2 = vmcb->save.cr2;
1617 nested_vmcb->save.rflags = vmcb->save.rflags;
1618 nested_vmcb->save.rip = vmcb->save.rip;
1619 nested_vmcb->save.rsp = vmcb->save.rsp;
1620 nested_vmcb->save.rax = vmcb->save.rax;
1621 nested_vmcb->save.dr7 = vmcb->save.dr7;
1622 nested_vmcb->save.dr6 = vmcb->save.dr6;
1623 nested_vmcb->save.cpl = vmcb->save.cpl;
1624
1625 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1626 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1627 nested_vmcb->control.int_state = vmcb->control.int_state;
1628 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1629 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1630 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1631 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1632 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1633 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1634
1635 /*
1636 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1637 * to make sure that we do not lose injected events. So check event_inj
1638 * here and copy it to exit_int_info if it is valid.
1639 * Exit_int_info and event_inj can't be both valid because the case
1640 * below only happens on a VMRUN instruction intercept which has
1641 * no valid exit_int_info set.
1642 */
1643 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1644 struct vmcb_control_area *nc = &nested_vmcb->control;
1645
1646 nc->exit_int_info = vmcb->control.event_inj;
1647 nc->exit_int_info_err = vmcb->control.event_inj_err;
1648 }
1649
33740e40
JR		 1650 nested_vmcb->control.tlb_ctl = 0;
1651 nested_vmcb->control.event_inj = 0;
1652 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1653
1654 /* We always set V_INTR_MASKING and remember the old value in hflags */
1655 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1656 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1657
cf74a78b 1658 /* Restore the original control entries */
0460a979 1659 copy_vmcb_control_area(vmcb, hsave);
cf74a78b
AG		 1660
1661 /* Kill any pending exceptions */
1662 if (svm->vcpu.arch.exception.pending == true)
1663 nsvm_printk("WARNING: Pending Exception\n");
33740e40 1664
219b65dc
AG		 1665 kvm_clear_exception_queue(&svm->vcpu);
1666 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1667
1668 /* Restore selected save entries */
1669 svm->vmcb->save.es = hsave->save.es;
1670 svm->vmcb->save.cs = hsave->save.cs;
1671 svm->vmcb->save.ss = hsave->save.ss;
1672 svm->vmcb->save.ds = hsave->save.ds;
1673 svm->vmcb->save.gdtr = hsave->save.gdtr;
1674 svm->vmcb->save.idtr = hsave->save.idtr;
1675 svm->vmcb->save.rflags = hsave->save.rflags;
1676 svm_set_efer(&svm->vcpu, hsave->save.efer);
1677 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1678 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1679 if (npt_enabled) {
1680 svm->vmcb->save.cr3 = hsave->save.cr3;
1681 svm->vcpu.arch.cr3 = hsave->save.cr3;
1682 } else {
1683 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1684 }
1685 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1686 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1687 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1688 svm->vmcb->save.dr7 = 0;
1689 svm->vmcb->save.cpl = 0;
1690 svm->vmcb->control.exit_int_info = 0;
1691
cf74a78b 1692 /* Exit nested SVM mode */
e6aa9abd 1693 svm->nested.vmcb = 0;
cf74a78b 1694
34f80cfa 1695 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1696
1697 kvm_mmu_reset_context(&svm->vcpu);
1698 kvm_mmu_load(&svm->vcpu);
1699
1700 return 0;
1701}
3d6368ef 1702
9738b2c9 1703static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1704{
9738b2c9 1705 u32 *nested_msrpm;
3d6368ef 1706 int i;
9738b2c9
JR		 1707
1708 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1709 if (!nested_msrpm)
1710 return false;
1711
3d6368ef 1712 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1713 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1714
e6aa9abd 1715 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1716
9738b2c9
JR		 1717 nested_svm_unmap(nested_msrpm, KM_USER0);
1718
1719 return true;
3d6368ef
AG		 1720}
1721
9738b2c9 1722static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1723{
9738b2c9 1724 struct vmcb *nested_vmcb;
e6aa9abd 1725 struct vmcb *hsave = svm->nested.hsave;
defbba56 1726 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1727
9738b2c9
JR		 1728 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1729 if (!nested_vmcb)
1730 return false;
1731
3d6368ef 1732 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1733 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1734
0ac406de
JR		 1735 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1736 nested_vmcb->save.rip,
1737 nested_vmcb->control.int_ctl,
1738 nested_vmcb->control.event_inj,
1739 nested_vmcb->control.nested_ctl);
1740
3d6368ef 1741 /* Clear internal status */
219b65dc
AG		 1742 kvm_clear_exception_queue(&svm->vcpu);
1743 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1744
1745 /* Save the old vmcb, so we don't need to pick what we save, but
1746 can restore everything when a VMEXIT occurs */
defbba56
JR		 1747 hsave->save.es = vmcb->save.es;
1748 hsave->save.cs = vmcb->save.cs;
1749 hsave->save.ss = vmcb->save.ss;
1750 hsave->save.ds = vmcb->save.ds;
1751 hsave->save.gdtr = vmcb->save.gdtr;
1752 hsave->save.idtr = vmcb->save.idtr;
1753 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1754 hsave->save.cr0 = svm->vcpu.arch.cr0;
1755 hsave->save.cr4 = svm->vcpu.arch.cr4;
1756 hsave->save.rflags = vmcb->save.rflags;
1757 hsave->save.rip = svm->next_rip;
1758 hsave->save.rsp = vmcb->save.rsp;
1759 hsave->save.rax = vmcb->save.rax;
1760 if (npt_enabled)
1761 hsave->save.cr3 = vmcb->save.cr3;
1762 else
1763 hsave->save.cr3 = svm->vcpu.arch.cr3;
1764
0460a979 1765 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1766
1767 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1768 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1769 else
1770 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1771
1772 /* Load the nested guest state */
1773 svm->vmcb->save.es = nested_vmcb->save.es;
1774 svm->vmcb->save.cs = nested_vmcb->save.cs;
1775 svm->vmcb->save.ss = nested_vmcb->save.ss;
1776 svm->vmcb->save.ds = nested_vmcb->save.ds;
1777 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1778 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1779 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1780 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1781 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1782 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1783 if (npt_enabled) {
1784 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1785 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1786 } else {
1787 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1788 kvm_mmu_reset_context(&svm->vcpu);
1789 }
defbba56 1790 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1791 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1792 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1793 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1794 /* In case we don't even reach vcpu_run, the fields are not updated */
1795 svm->vmcb->save.rax = nested_vmcb->save.rax;
1796 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1797 svm->vmcb->save.rip = nested_vmcb->save.rip;
1798 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1799 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1800 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1801
1802 /* We don't want a nested guest to be more powerful than the guest,
1803 so all intercepts are ORed */
1804 svm->vmcb->control.intercept_cr_read |=
1805 nested_vmcb->control.intercept_cr_read;
1806 svm->vmcb->control.intercept_cr_write |=
1807 nested_vmcb->control.intercept_cr_write;
1808 svm->vmcb->control.intercept_dr_read |=
1809 nested_vmcb->control.intercept_dr_read;
1810 svm->vmcb->control.intercept_dr_write |=
1811 nested_vmcb->control.intercept_dr_write;
1812 svm->vmcb->control.intercept_exceptions |=
1813 nested_vmcb->control.intercept_exceptions;
1814
1815 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1816
e6aa9abd 1817 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1818
aad42c64
JR		 1819 /* cache intercepts */
1820 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1821 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1822 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1823 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1824 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1825 svm->nested.intercept = nested_vmcb->control.intercept;
1826
3d6368ef 1827 force_new_asid(&svm->vcpu);
3d6368ef
AG		 1828 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1829 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1830 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1831 nested_vmcb->control.int_ctl);
1832 }
1833 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1834 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1835 else
1836 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1837
1838 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1839 nested_vmcb->control.exit_int_info,
1840 nested_vmcb->control.int_state);
1841
1842 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1843 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1844 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1845 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1846 nsvm_printk("Injecting Event: 0x%x\n",
1847 nested_vmcb->control.event_inj);
1848 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1849 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1850
9738b2c9
JR		 1851 nested_svm_unmap(nested_vmcb, KM_USER0);
1852
2af9194d 1853 enable_gif(svm);
3d6368ef 1854
9738b2c9 1855 return true;
3d6368ef
AG		 1856}
1857
9966bf68 1858static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1859{
1860 to_vmcb->save.fs = from_vmcb->save.fs;
1861 to_vmcb->save.gs = from_vmcb->save.gs;
1862 to_vmcb->save.tr = from_vmcb->save.tr;
1863 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1864 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1865 to_vmcb->save.star = from_vmcb->save.star;
1866 to_vmcb->save.lstar = from_vmcb->save.lstar;
1867 to_vmcb->save.cstar = from_vmcb->save.cstar;
1868 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1869 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1870 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1871 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1872}
1873
851ba692 1874static int vmload_interception(struct vcpu_svm *svm)
5542675b 1875{
9966bf68
JR		 1876 struct vmcb *nested_vmcb;
1877
5542675b
AG		 1878 if (nested_svm_check_permissions(svm))
1879 return 1;
1880
1881 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1882 skip_emulated_instruction(&svm->vcpu);
1883
9966bf68
JR		 1884 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1885 if (!nested_vmcb)
1886 return 1;
1887
1888 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1889 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1890
1891 return 1;
1892}
1893
851ba692 1894static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1895{
9966bf68
JR		 1896 struct vmcb *nested_vmcb;
1897
5542675b
AG		 1898 if (nested_svm_check_permissions(svm))
1899 return 1;
1900
1901 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1902 skip_emulated_instruction(&svm->vcpu);
1903
9966bf68
JR		 1904 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1905 if (!nested_vmcb)
1906 return 1;
1907
1908 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1909 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1910
1911 return 1;
1912}
1913
851ba692 1914static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef
AG		 1915{
1916 nsvm_printk("VMrun\n");
1f8da478 1917
3d6368ef
AG		 1918 if (nested_svm_check_permissions(svm))
1919 return 1;
1920
1921 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1922 skip_emulated_instruction(&svm->vcpu);
1923
9738b2c9 1924 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1925 return 1;
1926
9738b2c9 1927 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1928 goto failed;
1929
1930 return 1;
1931
1932failed:
1933
1934 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1935 svm->vmcb->control.exit_code_hi = 0;
1936 svm->vmcb->control.exit_info_1 = 0;
1937 svm->vmcb->control.exit_info_2 = 0;
1938
1939 nested_svm_vmexit(svm);
3d6368ef
AG		 1940
1941 return 1;
1942}
1943
851ba692 1944static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1945{
1946 if (nested_svm_check_permissions(svm))
1947 return 1;
1948
1949 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1950 skip_emulated_instruction(&svm->vcpu);
1951
2af9194d 1952 enable_gif(svm);
1371d904
AG		 1953
1954 return 1;
1955}
1956
851ba692 1957static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1958{
1959 if (nested_svm_check_permissions(svm))
1960 return 1;
1961
1962 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1963 skip_emulated_instruction(&svm->vcpu);
1964
2af9194d 1965 disable_gif(svm);
1371d904
AG		 1966
1967 /* After a CLGI no interrupts should come */
1968 svm_clear_vintr(svm);
1969 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1970
1971 return 1;
1972}
1973
851ba692 1974static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1975{
1976 struct kvm_vcpu *vcpu = &svm->vcpu;
1977 nsvm_printk("INVLPGA\n");
1978
1979 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1980 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1981
1982 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1983 skip_emulated_instruction(&svm->vcpu);
1984 return 1;
1985}
1986
851ba692 1987static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1988{
7ee5d940 1989 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1990 return 1;
1991}
1992
851ba692 1993static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 1994{
37817f29 1995 u16 tss_selector;
64a7ec06
GN		 1996 int reason;
1997 int int_type = svm->vmcb->control.exit_int_info &
1998 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1999 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2000 uint32_t type =
2001 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2002 uint32_t idt_v =
2003 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2004
2005 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2006
37817f29
IE		 2007 if (svm->vmcb->control.exit_info_2 &
2008 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2009 reason = TASK_SWITCH_IRET;
2010 else if (svm->vmcb->control.exit_info_2 &
2011 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2012 reason = TASK_SWITCH_JMP;
fe8e7f83 2013 else if (idt_v)
64a7ec06
GN		 2014 reason = TASK_SWITCH_GATE;
2015 else
2016 reason = TASK_SWITCH_CALL;
2017
fe8e7f83
GN		 2018 if (reason == TASK_SWITCH_GATE) {
2019 switch (type) {
2020 case SVM_EXITINTINFO_TYPE_NMI:
2021 svm->vcpu.arch.nmi_injected = false;
2022 break;
2023 case SVM_EXITINTINFO_TYPE_EXEPT:
2024 kvm_clear_exception_queue(&svm->vcpu);
2025 break;
2026 case SVM_EXITINTINFO_TYPE_INTR:
2027 kvm_clear_interrupt_queue(&svm->vcpu);
2028 break;
2029 default:
2030 break;
2031 }
2032 }
64a7ec06 2033
8317c298
GN		 2034 if (reason != TASK_SWITCH_GATE ||
2035 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2036 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2037 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2038 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2039
2040 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2041}
2042
851ba692 2043static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2044{
5fdbf976 2045 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2046 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2047 return 1;
6aa8b732
AK		 2048}
2049
851ba692 2050static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2051{
2052 ++svm->vcpu.stat.nmi_window_exits;
2053 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2054 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2055 return 1;
2056}
2057
851ba692 2058static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2059{
851ba692 2060 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2061 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2062 return 1;
2063}
2064
851ba692 2065static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2066{
851ba692 2067 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2068 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2069 return 1;
2070}
2071
851ba692 2072static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2073{
851ba692
AK		 2074 struct kvm_run *kvm_run = svm->vcpu.run;
2075
0a5fff19
GN		 2076 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2077 /* instruction emulation calls kvm_set_cr8() */
851ba692 2078 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2079 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2080 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2081 return 1;
95ba8273 2082 }
0a5fff19
GN		 2083 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2084 return 1;
1d075434
JR		 2085 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2086 return 0;
2087}
2088
6aa8b732
AK		 2089static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2090{
a2fa3e9f
GH		 2091 struct vcpu_svm *svm = to_svm(vcpu);
2092
6aa8b732 2093 switch (ecx) {
af24a4e4 2094 case MSR_IA32_TSC: {
20824f30 2095 u64 tsc_offset;
6aa8b732 2096
20824f30
JR		 2097 if (is_nested(svm))
2098 tsc_offset = svm->nested.hsave->control.tsc_offset;
2099 else
2100 tsc_offset = svm->vmcb->control.tsc_offset;
2101
2102 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2103 break;
2104 }
0e859cac 2105 case MSR_K6_STAR:
a2fa3e9f 2106 *data = svm->vmcb->save.star;
6aa8b732 2107 break;
0e859cac 2108#ifdef CONFIG_X86_64
6aa8b732 2109 case MSR_LSTAR:
a2fa3e9f 2110 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2111 break;
2112 case MSR_CSTAR:
a2fa3e9f 2113 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2114 break;
2115 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2116 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2117 break;
2118 case MSR_SYSCALL_MASK:
a2fa3e9f 2119 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2120 break;
2121#endif
2122 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2123 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2124 break;
2125 case MSR_IA32_SYSENTER_EIP:
017cb99e 2126 *data = svm->sysenter_eip;
6aa8b732
AK		 2127 break;
2128 case MSR_IA32_SYSENTER_ESP:
017cb99e 2129 *data = svm->sysenter_esp;
6aa8b732 2130 break;
a2938c80
JR		 2131 /* Nobody will change the following 5 values in the VMCB so
2132 we can safely return them on rdmsr. They will always be 0
2133 until LBRV is implemented. */
2134 case MSR_IA32_DEBUGCTLMSR:
2135 *data = svm->vmcb->save.dbgctl;
2136 break;
2137 case MSR_IA32_LASTBRANCHFROMIP:
2138 *data = svm->vmcb->save.br_from;
2139 break;
2140 case MSR_IA32_LASTBRANCHTOIP:
2141 *data = svm->vmcb->save.br_to;
2142 break;
2143 case MSR_IA32_LASTINTFROMIP:
2144 *data = svm->vmcb->save.last_excp_from;
2145 break;
2146 case MSR_IA32_LASTINTTOIP:
2147 *data = svm->vmcb->save.last_excp_to;
2148 break;
b286d5d8 2149 case MSR_VM_HSAVE_PA:
e6aa9abd 2150 *data = svm->nested.hsave_msr;
b286d5d8 2151 break;
eb6f302e
JR		 2152 case MSR_VM_CR:
2153 *data = 0;
2154 break;
c8a73f18
AG		 2155 case MSR_IA32_UCODE_REV:
2156 *data = 0x01000065;
2157 break;
6aa8b732 2158 default:
3bab1f5d 2159 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2160 }
2161 return 0;
2162}
2163
851ba692 2164static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2165{
ad312c7c 2166 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2167 u64 data;
2168
e756fc62 2169 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2170 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2171 else {
229456fc 2172 trace_kvm_msr_read(ecx, data);
af9ca2d7 2173
5fdbf976 2174 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2175 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2176 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2177 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2178 }
2179 return 1;
2180}
2181
2182static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2183{
a2fa3e9f
GH		 2184 struct vcpu_svm *svm = to_svm(vcpu);
2185
6aa8b732 2186 switch (ecx) {
af24a4e4 2187 case MSR_IA32_TSC: {
20824f30
JR		 2188 u64 tsc_offset = data - native_read_tsc();
2189 u64 g_tsc_offset = 0;
2190
2191 if (is_nested(svm)) {
2192 g_tsc_offset = svm->vmcb->control.tsc_offset -
2193 svm->nested.hsave->control.tsc_offset;
2194 svm->nested.hsave->control.tsc_offset = tsc_offset;
2195 }
2196
2197 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2198
6aa8b732
AK		 2199 break;
2200 }
0e859cac 2201 case MSR_K6_STAR:
a2fa3e9f 2202 svm->vmcb->save.star = data;
6aa8b732 2203 break;
49b14f24 2204#ifdef CONFIG_X86_64
6aa8b732 2205 case MSR_LSTAR:
a2fa3e9f 2206 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2207 break;
2208 case MSR_CSTAR:
a2fa3e9f 2209 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2210 break;
2211 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2212 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2213 break;
2214 case MSR_SYSCALL_MASK:
a2fa3e9f 2215 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2216 break;
2217#endif
2218 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2219 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2220 break;
2221 case MSR_IA32_SYSENTER_EIP:
017cb99e 2222 svm->sysenter_eip = data;
a2fa3e9f 2223 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2224 break;
2225 case MSR_IA32_SYSENTER_ESP:
017cb99e 2226 svm->sysenter_esp = data;
a2fa3e9f 2227 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2228 break;
a2938c80 2229 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2230 if (!svm_has(SVM_FEATURE_LBRV)) {
2231 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2232 __func__, data);
24e09cbf
JR		 2233 break;
2234 }
2235 if (data & DEBUGCTL_RESERVED_BITS)
2236 return 1;
2237
2238 svm->vmcb->save.dbgctl = data;
2239 if (data & (1ULL<<0))
2240 svm_enable_lbrv(svm);
2241 else
2242 svm_disable_lbrv(svm);
a2938c80 2243 break;
b286d5d8 2244 case MSR_VM_HSAVE_PA:
e6aa9abd 2245 svm->nested.hsave_msr = data;
62b9abaa 2246 break;
3c5d0a44
AG		 2247 case MSR_VM_CR:
2248 case MSR_VM_IGNNE:
3c5d0a44
AG		 2249 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2250 break;
6aa8b732 2251 default:
3bab1f5d 2252 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2253 }
2254 return 0;
2255}
2256
851ba692 2257static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2258{
ad312c7c 2259 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2260 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2261 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2262
229456fc 2263 trace_kvm_msr_write(ecx, data);
af9ca2d7 2264
5fdbf976 2265 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2266 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2267 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2268 else
e756fc62 2269 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2270 return 1;
2271}
2272
851ba692 2273static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2274{
e756fc62 2275 if (svm->vmcb->control.exit_info_1)
851ba692 2276 return wrmsr_interception(svm);
6aa8b732 2277 else
851ba692 2278 return rdmsr_interception(svm);
6aa8b732
AK		 2279}
2280
851ba692 2281static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2282{
851ba692
AK		 2283 struct kvm_run *kvm_run = svm->vcpu.run;
2284
f0b85051 2285 svm_clear_vintr(svm);
85f455f7 2286 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2287 /*
2288 * If the user space waits to inject interrupts, exit as soon as
2289 * possible
2290 */
8061823a
GN		 2291 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2292 kvm_run->request_interrupt_window &&
2293 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2294 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2295 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2296 return 0;
2297 }
2298
2299 return 1;
2300}
2301
851ba692 2302static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2303 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2304 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2305 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2306 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2307 /* for now: */
2308 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2309 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2310 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2311 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2312 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2313 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2314 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2315 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2316 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2317 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2318 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2319 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2320 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2321 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2322 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2323 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2324 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2325 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2326 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2327 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2328 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2329 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2330 [SVM_EXIT_SMI] = nop_on_interception,
2331 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2332 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2333 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2334 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2335 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2336 [SVM_EXIT_INVD] = emulate_on_interception,
6aa8b732 2337 [SVM_EXIT_HLT] = halt_interception,
a7052897 2338 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2339 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2340 [SVM_EXIT_IOIO] = io_interception,
2341 [SVM_EXIT_MSR] = msr_interception,
2342 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2343 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2344 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2345 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2346 [SVM_EXIT_VMLOAD] = vmload_interception,
2347 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2348 [SVM_EXIT_STGI] = stgi_interception,
2349 [SVM_EXIT_CLGI] = clgi_interception,
6aa8b732 2350 [SVM_EXIT_SKINIT] = invalid_op_interception,
cf5a94d1 2351 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2352 [SVM_EXIT_MONITOR] = invalid_op_interception,
2353 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2354 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2355};
2356
851ba692 2357static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2358{
04d2cc77 2359 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2360 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2361 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2362
229456fc 2363 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2364
cd3ff653
JR		 2365 if (unlikely(svm->nested.exit_required)) {
2366 nested_svm_vmexit(svm);
2367 svm->nested.exit_required = false;
2368
2369 return 1;
2370 }
2371
cf74a78b 2372 if (is_nested(svm)) {
410e4d57
JR		 2373 int vmexit;
2374
d8cabddf
JR		 2375 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2376 svm->vmcb->control.exit_info_1,
2377 svm->vmcb->control.exit_info_2,
2378 svm->vmcb->control.exit_int_info,
2379 svm->vmcb->control.exit_int_info_err);
2380
cf74a78b
AG		 2381 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2382 exit_code, svm->vmcb->control.exit_info_1,
2383 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
410e4d57
JR		 2384
2385 vmexit = nested_svm_exit_special(svm);
2386
2387 if (vmexit == NESTED_EXIT_CONTINUE)
2388 vmexit = nested_svm_exit_handled(svm);
2389
2390 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2391 return 1;
cf74a78b
AG		 2392 }
2393
a5c3832d
JR		 2394 svm_complete_interrupts(svm);
2395
709ddebf
JR		 2396 if (npt_enabled) {
2397 int mmu_reload = 0;
2398 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2399 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2400 mmu_reload = 1;
2401 }
2402 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2403 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2404 if (mmu_reload) {
2405 kvm_mmu_reset_context(vcpu);
2406 kvm_mmu_load(vcpu);
2407 }
2408 }
2409
04d2cc77
AK		 2410
2411 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2412 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2413 kvm_run->fail_entry.hardware_entry_failure_reason
2414 = svm->vmcb->control.exit_code;
2415 return 0;
2416 }
2417
a2fa3e9f 2418 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2419 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2420 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2421 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2422 "exit_code 0x%x\n",
b8688d51 2423 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2424 exit_code);
2425
9d8f549d 2426 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2427 || !svm_exit_handlers[exit_code]) {
6aa8b732 2428 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2429 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2430 return 0;
2431 }
2432
851ba692 2433 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2434}
2435
2436static void reload_tss(struct kvm_vcpu *vcpu)
2437{
2438 int cpu = raw_smp_processor_id();
2439
2440 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
d77c26fc 2441 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2442 load_TR_desc();
2443}
2444
e756fc62 2445static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2446{
2447 int cpu = raw_smp_processor_id();
2448
2449 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2450
a2fa3e9f 2451 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12
MT		 2452 /* FIXME: handle wraparound of asid_generation */
2453 if (svm->asid_generation != svm_data->asid_generation)
e756fc62 2454 new_asid(svm, svm_data);
6aa8b732
AK		 2455}
2456
95ba8273
GN		 2457static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2458{
2459 struct vcpu_svm *svm = to_svm(vcpu);
2460
2461 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2462 vcpu->arch.hflags |= HF_NMI_MASK;
2463 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2464 ++vcpu->stat.nmi_injections;
2465}
6aa8b732 2466
85f455f7 2467static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2468{
2469 struct vmcb_control_area *control;
2470
229456fc 2471 trace_kvm_inj_virq(irq);
af9ca2d7 2472
fa89a817 2473 ++svm->vcpu.stat.irq_injections;
e756fc62 2474 control = &svm->vmcb->control;
85f455f7 2475 control->int_vector = irq;
6aa8b732
AK		 2476 control->int_ctl &= ~V_INTR_PRIO_MASK;
2477 control->int_ctl |= V_IRQ_MASK |
2478 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2479}
2480
66fd3f7f 2481static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2482{
2483 struct vcpu_svm *svm = to_svm(vcpu);
2484
2af9194d 2485 BUG_ON(!(gif_set(svm)));
cf74a78b 2486
219b65dc
AG		 2487 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2488 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2489}
2490
95ba8273 2491static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2492{
2493 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2494
95ba8273 2495 if (irr == -1)
aaacfc9a
JR		 2496 return;
2497
95ba8273
GN		 2498 if (tpr >= irr)
2499 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2500}
aaacfc9a 2501
95ba8273
GN		 2502static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2503{
2504 struct vcpu_svm *svm = to_svm(vcpu);
2505 struct vmcb *vmcb = svm->vmcb;
2506 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2507 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2508}
2509
78646121
GN		 2510static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2511{
2512 struct vcpu_svm *svm = to_svm(vcpu);
2513 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2514 int ret;
2515
2516 if (!gif_set(svm) ||
2517 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2518 return 0;
2519
2520 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2521
2522 if (is_nested(svm))
2523 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2524
2525 return ret;
78646121
GN		 2526}
2527
9222be18 2528static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2529{
219b65dc
AG		 2530 struct vcpu_svm *svm = to_svm(vcpu);
2531 nsvm_printk("Trying to open IRQ window\n");
2532
2533 nested_svm_intr(svm);
2534
2535 /* In case GIF=0 we can't rely on the CPU to tell us when
2536 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2537 * The next time we get that intercept, this function will be
2538 * called again though and we'll get the vintr intercept. */
2af9194d 2539 if (gif_set(svm)) {
219b65dc
AG		 2540 svm_set_vintr(svm);
2541 svm_inject_irq(svm, 0x0);
2542 }
85f455f7
ED		 2543}
2544
95ba8273 2545static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2546{
04d2cc77 2547 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2548
44c11430
GN		 2549 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2550 == HF_NMI_MASK)
2551 return; /* IRET will cause a vm exit */
2552
2553 /* Something prevents NMI from been injected. Single step over
2554 possible problem (IRET or exception injection or interrupt
2555 shadow) */
2556 vcpu->arch.singlestep = true;
2557 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2558 update_db_intercept(vcpu);
c1150d8c
DL		 2559}
2560
cbc94022
IE		 2561static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2562{
2563 return 0;
2564}
2565
d9e368d6
AK		 2566static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2567{
2568 force_new_asid(vcpu);
2569}
2570
04d2cc77
AK		 2571static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2572{
2573}
2574
d7bf8221
JR		 2575static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2576{
2577 struct vcpu_svm *svm = to_svm(vcpu);
2578
2579 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2580 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2581 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2582 }
2583}
2584
649d6864
JR		 2585static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2586{
2587 struct vcpu_svm *svm = to_svm(vcpu);
2588 u64 cr8;
2589
649d6864
JR		 2590 cr8 = kvm_get_cr8(vcpu);
2591 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2592 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2593}
2594
9222be18
GN		 2595static void svm_complete_interrupts(struct vcpu_svm *svm)
2596{
2597 u8 vector;
2598 int type;
2599 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2600
44c11430
GN		 2601 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2602 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2603
9222be18
GN		 2604 svm->vcpu.arch.nmi_injected = false;
2605 kvm_clear_exception_queue(&svm->vcpu);
2606 kvm_clear_interrupt_queue(&svm->vcpu);
2607
2608 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2609 return;
2610
2611 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2612 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2613
2614 switch (type) {
2615 case SVM_EXITINTINFO_TYPE_NMI:
2616 svm->vcpu.arch.nmi_injected = true;
2617 break;
2618 case SVM_EXITINTINFO_TYPE_EXEPT:
2619 /* In case of software exception do not reinject an exception
2620 vector, but re-execute and instruction instead */
219b65dc
AG		 2621 if (is_nested(svm))
2622 break;
66fd3f7f 2623 if (kvm_exception_is_soft(vector))
9222be18
GN		 2624 break;
2625 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2626 u32 err = svm->vmcb->control.exit_int_info_err;
2627 kvm_queue_exception_e(&svm->vcpu, vector, err);
2628
2629 } else
2630 kvm_queue_exception(&svm->vcpu, vector);
2631 break;
2632 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2633 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2634 break;
2635 default:
2636 break;
2637 }
2638}
2639
80e31d4f
AK		 2640#ifdef CONFIG_X86_64
2641#define R "r"
2642#else
2643#define R "e"
2644#endif
2645
851ba692 2646static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2647{
a2fa3e9f 2648 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2649 u16 fs_selector;
2650 u16 gs_selector;
2651 u16 ldt_selector;
d9e368d6 2652
cd3ff653
JR		 2653 /*
2654 * A vmexit emulation is required before the vcpu can be executed
2655 * again.
2656 */
2657 if (unlikely(svm->nested.exit_required))
2658 return;
2659
5fdbf976
MT		 2660 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2661 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2662 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2663
e756fc62 2664 pre_svm_run(svm);
6aa8b732 2665
649d6864
JR		 2666 sync_lapic_to_cr8(vcpu);
2667
6aa8b732 2668 save_host_msrs(vcpu);
d6e88aec
AK		 2669 fs_selector = kvm_read_fs();
2670 gs_selector = kvm_read_gs();
2671 ldt_selector = kvm_read_ldt();
cda0ffdd 2672 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2673 /* required for live migration with NPT */
2674 if (npt_enabled)
2675 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2676
04d2cc77
AK		 2677 clgi();
2678
2679 local_irq_enable();
36241b8c 2680
6aa8b732 2681 asm volatile (
80e31d4f
AK		 2682 "push %%"R"bp; \n\t"
2683 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2684 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2685 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2686 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2687 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2688 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2689#ifdef CONFIG_X86_64
fb3f0f51
RR		 2690 "mov %c[r8](%[svm]), %%r8 \n\t"
2691 "mov %c[r9](%[svm]), %%r9 \n\t"
2692 "mov %c[r10](%[svm]), %%r10 \n\t"
2693 "mov %c[r11](%[svm]), %%r11 \n\t"
2694 "mov %c[r12](%[svm]), %%r12 \n\t"
2695 "mov %c[r13](%[svm]), %%r13 \n\t"
2696 "mov %c[r14](%[svm]), %%r14 \n\t"
2697 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2698#endif
2699
6aa8b732 2700 /* Enter guest mode */
80e31d4f
AK		 2701 "push %%"R"ax \n\t"
2702 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2703 __ex(SVM_VMLOAD) "\n\t"
2704 __ex(SVM_VMRUN) "\n\t"
2705 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2706 "pop %%"R"ax \n\t"
6aa8b732
AK		 2707
2708 /* Save guest registers, load host registers */
80e31d4f
AK		 2709 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2710 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2711 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2712 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2713 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2714 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2715#ifdef CONFIG_X86_64
fb3f0f51
RR		 2716 "mov %%r8, %c[r8](%[svm]) \n\t"
2717 "mov %%r9, %c[r9](%[svm]) \n\t"
2718 "mov %%r10, %c[r10](%[svm]) \n\t"
2719 "mov %%r11, %c[r11](%[svm]) \n\t"
2720 "mov %%r12, %c[r12](%[svm]) \n\t"
2721 "mov %%r13, %c[r13](%[svm]) \n\t"
2722 "mov %%r14, %c[r14](%[svm]) \n\t"
2723 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2724#endif
80e31d4f 2725 "pop %%"R"bp"
6aa8b732 2726 :
fb3f0f51 2727 : [svm]"a"(svm),
6aa8b732 2728 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2729 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2730 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2731 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2732 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2733 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2734 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2735#ifdef CONFIG_X86_64
ad312c7c
ZX		 2736 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2737 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2738 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2739 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2740 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2741 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2742 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2743 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2744#endif
54a08c04 2745 : "cc", "memory"
80e31d4f 2746 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2747#ifdef CONFIG_X86_64
54a08c04
LV		 2748 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2749#endif
2750 );
6aa8b732 2751
ad312c7c 2752 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2753 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2754 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2755 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2756
d6e88aec
AK		 2757 kvm_load_fs(fs_selector);
2758 kvm_load_gs(gs_selector);
2759 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2760 load_host_msrs(vcpu);
2761
2762 reload_tss(vcpu);
2763
56ba47dd
AK		 2764 local_irq_disable();
2765
2766 stgi();
2767
d7bf8221
JR		 2768 sync_cr8_to_lapic(vcpu);
2769
a2fa3e9f 2770 svm->next_rip = 0;
9222be18 2771
6de4f3ad
AK		 2772 if (npt_enabled) {
2773 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2774 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2775 }
6aa8b732
AK		 2776}
2777
80e31d4f
AK		 2778#undef R
2779
6aa8b732
AK		 2780static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2781{
a2fa3e9f
GH		 2782 struct vcpu_svm *svm = to_svm(vcpu);
2783
709ddebf
JR		 2784 if (npt_enabled) {
2785 svm->vmcb->control.nested_cr3 = root;
2786 force_new_asid(vcpu);
2787 return;
2788 }
2789
a2fa3e9f 2790 svm->vmcb->save.cr3 = root;
6aa8b732 2791 force_new_asid(vcpu);
7807fa6c
AL		 2792
2793 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2794 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2795 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2796 vcpu->fpu_active = 0;
2797 }
6aa8b732
AK		 2798}
2799
6aa8b732
AK		 2800static int is_disabled(void)
2801{
6031a61c
JR		 2802 u64 vm_cr;
2803
2804 rdmsrl(MSR_VM_CR, vm_cr);
2805 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2806 return 1;
2807
6aa8b732
AK		 2808 return 0;
2809}
2810
102d8325
IM		 2811static void
2812svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2813{
2814 /*
2815 * Patch in the VMMCALL instruction:
2816 */
2817 hypercall[0] = 0x0f;
2818 hypercall[1] = 0x01;
2819 hypercall[2] = 0xd9;
102d8325
IM		 2820}
2821
002c7f7c
YS		 2822static void svm_check_processor_compat(void *rtn)
2823{
2824 *(int *)rtn = 0;
2825}
2826
774ead3a
AK		 2827static bool svm_cpu_has_accelerated_tpr(void)
2828{
2829 return false;
2830}
2831
67253af5
SY		 2832static int get_npt_level(void)
2833{
2834#ifdef CONFIG_X86_64
2835 return PT64_ROOT_LEVEL;
2836#else
2837 return PT32E_ROOT_LEVEL;
2838#endif
2839}
2840
4b12f0de 2841static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2842{
2843 return 0;
2844}
2845
229456fc
MT		 2846static const struct trace_print_flags svm_exit_reasons_str[] = {
2847 { SVM_EXIT_READ_CR0, "read_cr0" },
2848 { SVM_EXIT_READ_CR3, "read_cr3" },
2849 { SVM_EXIT_READ_CR4, "read_cr4" },
2850 { SVM_EXIT_READ_CR8, "read_cr8" },
2851 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2852 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2853 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2854 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2855 { SVM_EXIT_READ_DR0, "read_dr0" },
2856 { SVM_EXIT_READ_DR1, "read_dr1" },
2857 { SVM_EXIT_READ_DR2, "read_dr2" },
2858 { SVM_EXIT_READ_DR3, "read_dr3" },
2859 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2860 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2861 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2862 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2863 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2864 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2865 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2866 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2867 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2868 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2869 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2870 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2871 { SVM_EXIT_INTR, "interrupt" },
2872 { SVM_EXIT_NMI, "nmi" },
2873 { SVM_EXIT_SMI, "smi" },
2874 { SVM_EXIT_INIT, "init" },
2875 { SVM_EXIT_VINTR, "vintr" },
2876 { SVM_EXIT_CPUID, "cpuid" },
2877 { SVM_EXIT_INVD, "invd" },
2878 { SVM_EXIT_HLT, "hlt" },
2879 { SVM_EXIT_INVLPG, "invlpg" },
2880 { SVM_EXIT_INVLPGA, "invlpga" },
2881 { SVM_EXIT_IOIO, "io" },
2882 { SVM_EXIT_MSR, "msr" },
2883 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2884 { SVM_EXIT_SHUTDOWN, "shutdown" },
2885 { SVM_EXIT_VMRUN, "vmrun" },
2886 { SVM_EXIT_VMMCALL, "hypercall" },
2887 { SVM_EXIT_VMLOAD, "vmload" },
2888 { SVM_EXIT_VMSAVE, "vmsave" },
2889 { SVM_EXIT_STGI, "stgi" },
2890 { SVM_EXIT_CLGI, "clgi" },
2891 { SVM_EXIT_SKINIT, "skinit" },
2892 { SVM_EXIT_WBINVD, "wbinvd" },
2893 { SVM_EXIT_MONITOR, "monitor" },
2894 { SVM_EXIT_MWAIT, "mwait" },
2895 { SVM_EXIT_NPF, "npf" },
2896 { -1, NULL }
2897};
2898
344f414f
JR		 2899static bool svm_gb_page_enable(void)
2900{
2901 return true;
2902}
2903
cbdd1bea 2904static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2905 .cpu_has_kvm_support = has_svm,
2906 .disabled_by_bios = is_disabled,
2907 .hardware_setup = svm_hardware_setup,
2908 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2909 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2910 .hardware_enable = svm_hardware_enable,
2911 .hardware_disable = svm_hardware_disable,
774ead3a 2912 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2913
2914 .vcpu_create = svm_create_vcpu,
2915 .vcpu_free = svm_free_vcpu,
04d2cc77 2916 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2917
04d2cc77 2918 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2919 .vcpu_load = svm_vcpu_load,
2920 .vcpu_put = svm_vcpu_put,
2921
2922 .set_guest_debug = svm_guest_debug,
2923 .get_msr = svm_get_msr,
2924 .set_msr = svm_set_msr,
2925 .get_segment_base = svm_get_segment_base,
2926 .get_segment = svm_get_segment,
2927 .set_segment = svm_set_segment,
2e4d2653 2928 .get_cpl = svm_get_cpl,
1747fb71 2929 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2930 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2931 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2932 .set_cr3 = svm_set_cr3,
2933 .set_cr4 = svm_set_cr4,
2934 .set_efer = svm_set_efer,
2935 .get_idt = svm_get_idt,
2936 .set_idt = svm_set_idt,
2937 .get_gdt = svm_get_gdt,
2938 .set_gdt = svm_set_gdt,
2939 .get_dr = svm_get_dr,
2940 .set_dr = svm_set_dr,
6de4f3ad 2941 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2942 .get_rflags = svm_get_rflags,
2943 .set_rflags = svm_set_rflags,
2944
6aa8b732 2945 .tlb_flush = svm_flush_tlb,
6aa8b732 2946
6aa8b732 2947 .run = svm_vcpu_run,
04d2cc77 2948 .handle_exit = handle_exit,
6aa8b732 2949 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2950 .set_interrupt_shadow = svm_set_interrupt_shadow,
2951 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2952 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2953 .set_irq = svm_set_irq,
95ba8273 2954 .set_nmi = svm_inject_nmi,
298101da 2955 .queue_exception = svm_queue_exception,
78646121 2956 .interrupt_allowed = svm_interrupt_allowed,
95ba8273
GN		 2957 .nmi_allowed = svm_nmi_allowed,
2958 .enable_nmi_window = enable_nmi_window,
2959 .enable_irq_window = enable_irq_window,
2960 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2961
2962 .set_tss_addr = svm_set_tss_addr,
67253af5 2963 .get_tdp_level = get_npt_level,
4b12f0de 2964 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2965
2966 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2967 .gb_page_enable = svm_gb_page_enable,
6aa8b732
AK		 2968};
2969
2970static int __init svm_init(void)
2971{
cb498ea2 2972 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2973 THIS_MODULE);
6aa8b732
AK		 2974}
2975
2976static void __exit svm_exit(void)
2977{
cb498ea2 2978 kvm_exit();
6aa8b732
AK		 2979}
2980
2981module_init(svm_init)
2982module_exit(svm_exit)
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