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KVM: x86: Moving PT_*_LEVEL to mmu.h
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
6aa8b732 29
e495606d 30#include <asm/desc.h>
6aa8b732 31
63d1142f 32#include <asm/virtext.h>
229456fc 33#include "trace.h"
63d1142f 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
40#define IOPM_ALLOC_ORDER 2
41#define MSRPM_ALLOC_ORDER 1
42
6aa8b732
AK		 43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
80b7706e
JR		 46#define SVM_FEATURE_NPT (1 << 0)
47#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 48#define SVM_FEATURE_SVML (1 << 2)
565d0998 49#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 50
410e4d57
JR		 51#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
24e09cbf
JR		 55#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
6c8166a7
AK		 57static const u32 host_save_user_msrs[] = {
58#ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61#endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63};
64
65#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67struct kvm_vcpu;
68
e6aa9abd
JR		 69struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
aad42c64 79
cd3ff653
JR		 80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
aad42c64
JR		 83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
e6aa9abd
JR		 91};
92
6c8166a7
AK		 93struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
6c8166a7
AK		 106
107 u32 *msrpm;
6c8166a7 108
e6aa9abd 109 struct nested_state nested;
6be7d306
JK		 110
111 bool nmi_singlestep;
6c8166a7
AK		 112};
113
709ddebf
JR		 114/* enable NPT for AMD64 and X86 with PAE */
115#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116static bool npt_enabled = true;
117#else
e3da3acd 118static bool npt_enabled = false;
709ddebf 119#endif
6c7dac72
JR		 120static int npt = 1;
121
122module_param(npt, int, S_IRUGO);
e3da3acd 123
4b6e4dca 124static int nested = 1;
236de055
AG		 125module_param(nested, int, S_IRUGO);
126
44874f84 127static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 128static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 129
410e4d57 130static int nested_svm_exit_handled(struct vcpu_svm *svm);
cf74a78b 131static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 132static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
a2fa3e9f
GH		 135static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136{
fb3f0f51 137 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 138}
139
3d6368ef
AG		 140static inline bool is_nested(struct vcpu_svm *svm)
141{
e6aa9abd 142 return svm->nested.vmcb;
3d6368ef
AG		 143}
144
2af9194d
JR		 145static inline void enable_gif(struct vcpu_svm *svm)
146{
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148}
149
150static inline void disable_gif(struct vcpu_svm *svm)
151{
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153}
154
155static inline bool gif_set(struct vcpu_svm *svm)
156{
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158}
159
4866d5e3 160static unsigned long iopm_base;
6aa8b732
AK		 161
162struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169} __attribute__((packed));
170
171struct svm_cpu_data {
172 int cpu;
173
5008fdf5
AK		 174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
6aa8b732
AK		 177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180};
181
182static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 183static uint32_t svm_features;
6aa8b732
AK		 184
185struct svm_init_data {
186 int cpu;
187 int r;
188};
189
190static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
9d8f549d 192#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 193#define MSRS_RANGE_SIZE 2048
194#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196#define MAX_INST_SIZE 15
197
80b7706e
JR		 198static inline u32 svm_has(u32 feat)
199{
200 return svm_features & feat;
201}
202
6aa8b732
AK		 203static inline void clgi(void)
204{
4ecac3fd 205 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 206}
207
208static inline void stgi(void)
209{
4ecac3fd 210 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 211}
212
213static inline void invlpga(unsigned long addr, u32 asid)
214{
4ecac3fd 215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 216}
217
6aa8b732
AK		 218static inline void force_new_asid(struct kvm_vcpu *vcpu)
219{
a2fa3e9f 220 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 221}
222
223static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224{
225 force_new_asid(vcpu);
226}
227
228static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229{
709ddebf 230 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 231 efer &= ~EFER_LME;
6aa8b732 232
9962d032 233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
ad312c7c 234 vcpu->arch.shadow_efer = efer;
6aa8b732
AK		 235}
236
298101da
AK		 237static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239{
240 struct vcpu_svm *svm = to_svm(vcpu);
241
cf74a78b
AG		 242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
298101da
AK		 247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252}
253
6aa8b732
AK		 254static int is_external_interrupt(u32 info)
255{
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258}
259
2809f5d2
GC		 260static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261{
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268}
269
270static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271{
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279}
280
6aa8b732
AK		 281static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282{
a2fa3e9f
GH		 283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
851ba692 286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 289 return;
290 }
5fdbf976
MT		 291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 294
5fdbf976 295 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 296 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 297}
298
299static int has_svm(void)
300{
63d1142f 301 const char *msg;
6aa8b732 302
63d1142f 303 if (!cpu_has_svm(&msg)) {
ff81ff10 304 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 305 return 0;
306 }
307
6aa8b732
AK		 308 return 1;
309}
310
311static void svm_hardware_disable(void *garbage)
312{
2c8dceeb 313 cpu_svm_disable();
6aa8b732
AK		 314}
315
10474ae8 316static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 317{
318
0fe1e009 319 struct svm_cpu_data *sd;
6aa8b732 320 uint64_t efer;
b792c344 321 struct descriptor_table gdt_descr;
6aa8b732
AK		 322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
10474ae8
AG		 325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
6aa8b732 329 if (!has_svm()) {
e6732a5a
ZA		 330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
10474ae8 332 return -EINVAL;
6aa8b732 333 }
0fe1e009 334 sd = per_cpu(svm_data, me);
6aa8b732 335
0fe1e009 336 if (!sd) {
e6732a5a 337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 338 me);
10474ae8 339 return -EINVAL;
6aa8b732
AK		 340 }
341
0fe1e009
TH		 342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
6aa8b732 345
b792c344
AM		 346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
0fe1e009 348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 349
9962d032 350 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 351
d0316554 352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 353
354 return 0;
6aa8b732
AK		 355}
356
0da1db75
JR		 357static void svm_cpu_uninit(int cpu)
358{
0fe1e009 359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 360
0fe1e009 361 if (!sd)
0da1db75
JR		 362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 365 __free_page(sd->save_area);
366 kfree(sd);
0da1db75
JR		 367}
368
6aa8b732
AK		 369static int svm_cpu_init(int cpu)
370{
0fe1e009 371 struct svm_cpu_data *sd;
6aa8b732
AK		 372 int r;
373
0fe1e009
TH		 374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
6aa8b732 376 return -ENOMEM;
0fe1e009
TH		 377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 379 r = -ENOMEM;
0fe1e009 380 if (!sd->save_area)
6aa8b732
AK		 381 goto err_1;
382
0fe1e009 383 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 384
385 return 0;
386
387err_1:
0fe1e009 388 kfree(sd);
6aa8b732
AK		 389 return r;
390
391}
392
bfc733a7
RR		 393static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
6aa8b732
AK		 395{
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
bfc733a7 409 return;
6aa8b732
AK		 410 }
411 }
bfc733a7 412 BUG();
6aa8b732
AK		 413}
414
f65c229c
JR		 415static void svm_vcpu_init_msrpm(u32 *msrpm)
416{
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419#ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426#endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 429}
430
24e09cbf
JR		 431static void svm_enable_lbrv(struct vcpu_svm *svm)
432{
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440}
441
442static void svm_disable_lbrv(struct vcpu_svm *svm)
443{
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451}
452
6aa8b732
AK		 453static __init int svm_hardware_setup(void)
454{
455 int cpu;
456 struct page *iopm_pages;
f65c229c 457 void *iopm_va;
6aa8b732
AK		 458 int r;
459
6aa8b732
AK		 460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
c8681339
AL		 464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
50a37eb4
JR		 469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
1b2fd70c
AG		 472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
236de055
AG		 475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
3230bb47 480 for_each_possible_cpu(cpu) {
6aa8b732
AK		 481 r = svm_cpu_init(cpu);
482 if (r)
f65c229c 483 goto err;
6aa8b732 484 }
33bd6a0b
JR		 485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
e3da3acd
JR		 488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
6c7dac72
JR		 491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
18552672 496 if (npt_enabled) {
e3da3acd 497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 498 kvm_enable_tdp();
5f4cb662
JR		 499 } else
500 kvm_disable_tdp();
e3da3acd 501
6aa8b732
AK		 502 return 0;
503
f65c229c 504err:
6aa8b732
AK		 505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508}
509
510static __exit void svm_hardware_unsetup(void)
511{
0da1db75
JR		 512 int cpu;
513
3230bb47 514 for_each_possible_cpu(cpu)
0da1db75
JR		 515 svm_cpu_uninit(cpu);
516
6aa8b732 517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 518 iopm_base = 0;
6aa8b732
AK		 519}
520
521static void init_seg(struct vmcb_seg *seg)
522{
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528}
529
530static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531{
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536}
537
e6101a96 538static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 539{
e6101a96
JR		 540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732
AK		 542
543 control->intercept_cr_read = INTERCEPT_CR0_MASK |
544 INTERCEPT_CR3_MASK |
649d6864 545 INTERCEPT_CR4_MASK;
6aa8b732
AK		 546
547 control->intercept_cr_write = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
80a8119c
AK		 549 INTERCEPT_CR4_MASK |
550 INTERCEPT_CR8_MASK;
6aa8b732
AK		 551
552 control->intercept_dr_read = INTERCEPT_DR0_MASK |
553 INTERCEPT_DR1_MASK |
554 INTERCEPT_DR2_MASK |
555 INTERCEPT_DR3_MASK;
556
557 control->intercept_dr_write = INTERCEPT_DR0_MASK |
558 INTERCEPT_DR1_MASK |
559 INTERCEPT_DR2_MASK |
560 INTERCEPT_DR3_MASK |
561 INTERCEPT_DR5_MASK |
562 INTERCEPT_DR7_MASK;
563
7aa81cc0 564 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 565 (1 << UD_VECTOR) |
566 (1 << MC_VECTOR);
6aa8b732
AK		 567
568
569 control->intercept = (1ULL << INTERCEPT_INTR) |
570 (1ULL << INTERCEPT_NMI) |
0152527b 571 (1ULL << INTERCEPT_SMI) |
6aa8b732 572 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 573 (1ULL << INTERCEPT_INVD) |
6aa8b732 574 (1ULL << INTERCEPT_HLT) |
a7052897 575 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 576 (1ULL << INTERCEPT_INVLPGA) |
577 (1ULL << INTERCEPT_IOIO_PROT) |
578 (1ULL << INTERCEPT_MSR_PROT) |
579 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 580 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 581 (1ULL << INTERCEPT_VMRUN) |
582 (1ULL << INTERCEPT_VMMCALL) |
583 (1ULL << INTERCEPT_VMLOAD) |
584 (1ULL << INTERCEPT_VMSAVE) |
585 (1ULL << INTERCEPT_STGI) |
586 (1ULL << INTERCEPT_CLGI) |
916ce236 587 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 588 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 589 (1ULL << INTERCEPT_MONITOR) |
590 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 591
592 control->iopm_base_pa = iopm_base;
f65c229c 593 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 594 control->tsc_offset = 0;
6aa8b732
AK		 595 control->int_ctl = V_INTR_MASKING_MASK;
596
597 init_seg(&save->es);
598 init_seg(&save->ss);
599 init_seg(&save->ds);
600 init_seg(&save->fs);
601 init_seg(&save->gs);
602
603 save->cs.selector = 0xf000;
604 /* Executable/Readable Code Segment */
605 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
606 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
607 save->cs.limit = 0xffff;
d92899a0
AK		 608 /*
609 * cs.base should really be 0xffff0000, but vmx can't handle that, so
610 * be consistent with it.
611 *
612 * Replace when we have real mode working for vmx.
613 */
614 save->cs.base = 0xf0000;
6aa8b732
AK		 615
616 save->gdtr.limit = 0xffff;
617 save->idtr.limit = 0xffff;
618
619 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
620 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
621
9962d032 622 save->efer = EFER_SVME;
d77c26fc 623 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 624 save->dr7 = 0x400;
625 save->rflags = 2;
626 save->rip = 0x0000fff0;
5fdbf976 627 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 628
18fa000a
EH		 629 /* This is the guest-visible cr0 value.
630 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 631 */
18fa000a
EH		 632 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
633 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
634
66aee91a 635 save->cr4 = X86_CR4_PAE;
6aa8b732 636 /* rdx = ?? */
709ddebf
JR		 637
638 if (npt_enabled) {
639 /* Setup VMCB for Nested Paging */
640 control->nested_ctl = 1;
a7052897
MT		 641 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
642 (1ULL << INTERCEPT_INVLPG));
709ddebf
JR		 643 control->intercept_exceptions &= ~(1 << PF_VECTOR);
644 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
647 INTERCEPT_CR3_MASK);
648 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
a79d2f18 652 force_new_asid(&svm->vcpu);
1371d904 653
e6aa9abd 654 svm->nested.vmcb = 0;
2af9194d
JR		 655 svm->vcpu.arch.hflags = 0;
656
565d0998
ML		 657 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
658 control->pause_filter_count = 3000;
659 control->intercept |= (1ULL << INTERCEPT_PAUSE);
660 }
661
2af9194d 662 enable_gif(svm);
6aa8b732
AK		 663}
664
e00c8cf2 665static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 666{
667 struct vcpu_svm *svm = to_svm(vcpu);
668
e6101a96 669 init_vmcb(svm);
70433389 670
c5af89b6 671 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 672 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 673 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
674 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 675 }
5fdbf976
MT		 676 vcpu->arch.regs_avail = ~0;
677 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 678
679 return 0;
04d2cc77
AK		 680}
681
fb3f0f51 682static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 683{
a2fa3e9f 684 struct vcpu_svm *svm;
6aa8b732 685 struct page *page;
f65c229c 686 struct page *msrpm_pages;
b286d5d8 687 struct page *hsave_page;
3d6368ef 688 struct page *nested_msrpm_pages;
fb3f0f51 689 int err;
6aa8b732 690
c16f862d 691 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 692 if (!svm) {
693 err = -ENOMEM;
694 goto out;
695 }
696
697 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
698 if (err)
699 goto free_svm;
700
6aa8b732 701 page = alloc_page(GFP_KERNEL);
fb3f0f51
RR		 702 if (!page) {
703 err = -ENOMEM;
704 goto uninit;
705 }
6aa8b732 706
f65c229c
JR		 707 err = -ENOMEM;
708 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
709 if (!msrpm_pages)
710 goto uninit;
3d6368ef
AG		 711
712 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!nested_msrpm_pages)
714 goto uninit;
715
f65c229c
JR		 716 svm->msrpm = page_address(msrpm_pages);
717 svm_vcpu_init_msrpm(svm->msrpm);
718
b286d5d8
AG		 719 hsave_page = alloc_page(GFP_KERNEL);
720 if (!hsave_page)
721 goto uninit;
e6aa9abd 722 svm->nested.hsave = page_address(hsave_page);
b286d5d8 723
e6aa9abd 724 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 725
a2fa3e9f
GH		 726 svm->vmcb = page_address(page);
727 clear_page(svm->vmcb);
728 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
729 svm->asid_generation = 0;
e6101a96 730 init_vmcb(svm);
a2fa3e9f 731
fb3f0f51
RR		 732 fx_init(&svm->vcpu);
733 svm->vcpu.fpu_active = 1;
ad312c7c 734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 735 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 737
fb3f0f51 738 return &svm->vcpu;
36241b8c 739
fb3f0f51
RR		 740uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742free_svm:
a4770347 743 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 744out:
745 return ERR_PTR(err);
6aa8b732
AK		 746}
747
748static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749{
a2fa3e9f
GH		 750 struct vcpu_svm *svm = to_svm(vcpu);
751
fb3f0f51 752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 756 kvm_vcpu_uninit(vcpu);
a4770347 757 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 758}
759
15ad7146 760static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 761{
a2fa3e9f 762 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 763 int i;
0cc5064d 764
0cc5064d 765 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 766 u64 delta;
0cc5064d 767
953899b6
JR		 768 if (check_tsc_unstable()) {
769 /*
770 * Make sure that the guest sees a monotonically
771 * increasing TSC.
772 */
773 delta = vcpu->arch.host_tsc - native_read_tsc();
774 svm->vmcb->control.tsc_offset += delta;
775 if (is_nested(svm))
776 svm->nested.hsave->control.tsc_offset += delta;
777 }
0cc5064d 778 vcpu->cpu = cpu;
2f599714 779 kvm_migrate_timers(vcpu);
4b656b12 780 svm->asid_generation = 0;
0cc5064d 781 }
94dfbdb3
AL		 782
783 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 784 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 785}
786
787static void svm_vcpu_put(struct kvm_vcpu *vcpu)
788{
a2fa3e9f 789 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 790 int i;
791
e1beb1d3 792 ++vcpu->stat.host_state_reload;
94dfbdb3 793 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 794 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 795
e935d48e 796 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 797}
798
6aa8b732
AK		 799static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
800{
a2fa3e9f 801 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 802}
803
804static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
805{
a2fa3e9f 806 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 807}
808
6de4f3ad
AK		 809static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
810{
811 switch (reg) {
812 case VCPU_EXREG_PDPTR:
813 BUG_ON(!npt_enabled);
814 load_pdptrs(vcpu, vcpu->arch.cr3);
815 break;
816 default:
817 BUG();
818 }
819}
820
f0b85051
AG		 821static void svm_set_vintr(struct vcpu_svm *svm)
822{
823 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
824}
825
826static void svm_clear_vintr(struct vcpu_svm *svm)
827{
828 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
829}
830
6aa8b732
AK		 831static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
832{
a2fa3e9f 833 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 834
835 switch (seg) {
836 case VCPU_SREG_CS: return &save->cs;
837 case VCPU_SREG_DS: return &save->ds;
838 case VCPU_SREG_ES: return &save->es;
839 case VCPU_SREG_FS: return &save->fs;
840 case VCPU_SREG_GS: return &save->gs;
841 case VCPU_SREG_SS: return &save->ss;
842 case VCPU_SREG_TR: return &save->tr;
843 case VCPU_SREG_LDTR: return &save->ldtr;
844 }
845 BUG();
8b6d44c7 846 return NULL;
6aa8b732
AK		 847}
848
849static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
850{
851 struct vmcb_seg *s = svm_seg(vcpu, seg);
852
853 return s->base;
854}
855
856static void svm_get_segment(struct kvm_vcpu *vcpu,
857 struct kvm_segment *var, int seg)
858{
859 struct vmcb_seg *s = svm_seg(vcpu, seg);
860
861 var->base = s->base;
862 var->limit = s->limit;
863 var->selector = s->selector;
864 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
865 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
866 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
867 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
868 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
869 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
870 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
871 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 872
19bca6ab
AP		 873 /* AMD's VMCB does not have an explicit unusable field, so emulate it
874 * for cross vendor migration purposes by "not present"
875 */
876 var->unusable = !var->present || (var->type == 0);
877
1fbdc7a5
AP		 878 switch (seg) {
879 case VCPU_SREG_CS:
880 /*
881 * SVM always stores 0 for the 'G' bit in the CS selector in
882 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
883 * Intel's VMENTRY has a check on the 'G' bit.
884 */
25022acc 885 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 886 break;
887 case VCPU_SREG_TR:
888 /*
889 * Work around a bug where the busy flag in the tr selector
890 * isn't exposed
891 */
c0d09828 892 var->type |= 0x2;
1fbdc7a5
AP		 893 break;
894 case VCPU_SREG_DS:
895 case VCPU_SREG_ES:
896 case VCPU_SREG_FS:
897 case VCPU_SREG_GS:
898 /*
899 * The accessed bit must always be set in the segment
900 * descriptor cache, although it can be cleared in the
901 * descriptor, the cached bit always remains at 1. Since
902 * Intel has a check on this, set it here to support
903 * cross-vendor migration.
904 */
905 if (!var->unusable)
906 var->type |= 0x1;
907 break;
b586eb02
AP		 908 case VCPU_SREG_SS:
909 /* On AMD CPUs sometimes the DB bit in the segment
910 * descriptor is left as 1, although the whole segment has
911 * been made unusable. Clear it here to pass an Intel VMX
912 * entry check when cross vendor migrating.
913 */
914 if (var->unusable)
915 var->db = 0;
916 break;
1fbdc7a5 917 }
6aa8b732
AK		 918}
919
2e4d2653
IE		 920static int svm_get_cpl(struct kvm_vcpu *vcpu)
921{
922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
923
924 return save->cpl;
925}
926
6aa8b732
AK		 927static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928{
a2fa3e9f
GH		 929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 dt->limit = svm->vmcb->save.idtr.limit;
932 dt->base = svm->vmcb->save.idtr.base;
6aa8b732
AK		 933}
934
935static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
936{
a2fa3e9f
GH		 937 struct vcpu_svm *svm = to_svm(vcpu);
938
939 svm->vmcb->save.idtr.limit = dt->limit;
940 svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 941}
942
943static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
944{
a2fa3e9f
GH		 945 struct vcpu_svm *svm = to_svm(vcpu);
946
947 dt->limit = svm->vmcb->save.gdtr.limit;
948 dt->base = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 949}
950
951static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
952{
a2fa3e9f
GH		 953 struct vcpu_svm *svm = to_svm(vcpu);
954
955 svm->vmcb->save.gdtr.limit = dt->limit;
956 svm->vmcb->save.gdtr.base = dt->base ;
6aa8b732
AK		 957}
958
25c4c276 959static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 960{
961}
962
6aa8b732
AK		 963static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
964{
a2fa3e9f
GH		 965 struct vcpu_svm *svm = to_svm(vcpu);
966
05b3e0c2 967#ifdef CONFIG_X86_64
ad312c7c 968 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 969 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
ad312c7c 970 vcpu->arch.shadow_efer |= EFER_LMA;
2b5203ee 971 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 972 }
973
d77c26fc 974 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
ad312c7c 975 vcpu->arch.shadow_efer &= ~EFER_LMA;
2b5203ee 976 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 977 }
978 }
979#endif
709ddebf
JR		 980 if (npt_enabled)
981 goto set;
982
ad312c7c 983 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
a2fa3e9f 984 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
7807fa6c
AL		 985 vcpu->fpu_active = 1;
986 }
987
ad312c7c 988 vcpu->arch.cr0 = cr0;
707d92fa 989 cr0 |= X86_CR0_PG | X86_CR0_WP;
6b390b63
JR		 990 if (!vcpu->fpu_active) {
991 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
334df50a 992 cr0 |= X86_CR0_TS;
6b390b63 993 }
709ddebf
JR		 994set:
995 /*
996 * re-enable caching here because the QEMU bios
997 * does not do it - this results in some delay at
998 * reboot
999 */
1000 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1001 svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 1002}
1003
1004static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1005{
6394b649 1006 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1007 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1008
1009 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1010 force_new_asid(vcpu);
6394b649 1011
ec077263
JR		 1012 vcpu->arch.cr4 = cr4;
1013 if (!npt_enabled)
1014 cr4 |= X86_CR4_PAE;
6394b649 1015 cr4 |= host_cr4_mce;
ec077263 1016 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1017}
1018
1019static void svm_set_segment(struct kvm_vcpu *vcpu,
1020 struct kvm_segment *var, int seg)
1021{
a2fa3e9f 1022 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1023 struct vmcb_seg *s = svm_seg(vcpu, seg);
1024
1025 s->base = var->base;
1026 s->limit = var->limit;
1027 s->selector = var->selector;
1028 if (var->unusable)
1029 s->attrib = 0;
1030 else {
1031 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1032 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1033 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1034 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1035 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1036 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1037 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1038 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1039 }
1040 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1041 svm->vmcb->save.cpl
1042 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1043 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1044
1045}
1046
44c11430 1047static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1048{
d0bfb940
JK		 1049 struct vcpu_svm *svm = to_svm(vcpu);
1050
d0bfb940
JK		 1051 svm->vmcb->control.intercept_exceptions &=
1052 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1053
6be7d306 1054 if (svm->nmi_singlestep)
44c11430
GN		 1055 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1056
d0bfb940
JK		 1057 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1058 if (vcpu->guest_debug &
1059 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1060 svm->vmcb->control.intercept_exceptions |=
1061 1 << DB_VECTOR;
1062 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1063 svm->vmcb->control.intercept_exceptions |=
1064 1 << BP_VECTOR;
1065 } else
1066 vcpu->guest_debug = 0;
44c11430
GN		 1067}
1068
355be0b9 1069static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1070{
44c11430
GN		 1071 struct vcpu_svm *svm = to_svm(vcpu);
1072
ae675ef0
JK		 1073 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1074 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1075 else
1076 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1077
355be0b9 1078 update_db_intercept(vcpu);
6aa8b732
AK		 1079}
1080
1081static void load_host_msrs(struct kvm_vcpu *vcpu)
1082{
94dfbdb3 1083#ifdef CONFIG_X86_64
a2fa3e9f 1084 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1085#endif
6aa8b732
AK		 1086}
1087
1088static void save_host_msrs(struct kvm_vcpu *vcpu)
1089{
94dfbdb3 1090#ifdef CONFIG_X86_64
a2fa3e9f 1091 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1092#endif
6aa8b732
AK		 1093}
1094
0fe1e009 1095static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1096{
0fe1e009
TH		 1097 if (sd->next_asid > sd->max_asid) {
1098 ++sd->asid_generation;
1099 sd->next_asid = 1;
a2fa3e9f 1100 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1101 }
1102
0fe1e009
TH		 1103 svm->asid_generation = sd->asid_generation;
1104 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1105}
1106
6aa8b732
AK		 1107static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1108{
42dbaa5a
JK		 1109 struct vcpu_svm *svm = to_svm(vcpu);
1110 unsigned long val;
1111
1112 switch (dr) {
1113 case 0 ... 3:
1114 val = vcpu->arch.db[dr];
1115 break;
1116 case 6:
1117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1118 val = vcpu->arch.dr6;
1119 else
1120 val = svm->vmcb->save.dr6;
1121 break;
1122 case 7:
1123 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1124 val = vcpu->arch.dr7;
1125 else
1126 val = svm->vmcb->save.dr7;
1127 break;
1128 default:
1129 val = 0;
1130 }
1131
af9ca2d7 1132 return val;
6aa8b732
AK		 1133}
1134
1135static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1136 int *exception)
1137{
a2fa3e9f
GH		 1138 struct vcpu_svm *svm = to_svm(vcpu);
1139
42dbaa5a 1140 *exception = 0;
6aa8b732
AK		 1141
1142 switch (dr) {
1143 case 0 ... 3:
42dbaa5a
JK		 1144 vcpu->arch.db[dr] = value;
1145 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1146 vcpu->arch.eff_db[dr] = value;
6aa8b732
AK		 1147 return;
1148 case 4 ... 5:
42dbaa5a 1149 if (vcpu->arch.cr4 & X86_CR4_DE)
6aa8b732 1150 *exception = UD_VECTOR;
42dbaa5a
JK		 1151 return;
1152 case 6:
1153 if (value & 0xffffffff00000000ULL) {
1154 *exception = GP_VECTOR;
6aa8b732
AK		 1155 return;
1156 }
42dbaa5a
JK		 1157 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1158 return;
1159 case 7:
1160 if (value & 0xffffffff00000000ULL) {
6aa8b732
AK		 1161 *exception = GP_VECTOR;
1162 return;
1163 }
42dbaa5a
JK		 1164 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1165 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1166 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1167 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1168 }
6aa8b732 1169 return;
6aa8b732 1170 default:
42dbaa5a 1171 /* FIXME: Possible case? */
6aa8b732 1172 printk(KERN_DEBUG "%s: unexpected dr %u\n",
b8688d51 1173 __func__, dr);
6aa8b732
AK		 1174 *exception = UD_VECTOR;
1175 return;
1176 }
1177}
1178
851ba692 1179static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1180{
6aa8b732
AK		 1181 u64 fault_address;
1182 u32 error_code;
6aa8b732 1183
a2fa3e9f
GH		 1184 fault_address = svm->vmcb->control.exit_info_2;
1185 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1186
229456fc 1187 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1188 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1189 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1190 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1191}
1192
851ba692 1193static int db_interception(struct vcpu_svm *svm)
d0bfb940 1194{
851ba692
AK		 1195 struct kvm_run *kvm_run = svm->vcpu.run;
1196
d0bfb940 1197 if (!(svm->vcpu.guest_debug &
44c11430 1198 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1199 !svm->nmi_singlestep) {
d0bfb940
JK		 1200 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1201 return 1;
1202 }
44c11430 1203
6be7d306
JK		 1204 if (svm->nmi_singlestep) {
1205 svm->nmi_singlestep = false;
44c11430
GN		 1206 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1207 svm->vmcb->save.rflags &=
1208 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1209 update_db_intercept(&svm->vcpu);
1210 }
1211
1212 if (svm->vcpu.guest_debug &
1213 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1214 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1215 kvm_run->debug.arch.pc =
1216 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1217 kvm_run->debug.arch.exception = DB_VECTOR;
1218 return 0;
1219 }
1220
1221 return 1;
d0bfb940
JK		 1222}
1223
851ba692 1224static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1225{
851ba692
AK		 1226 struct kvm_run *kvm_run = svm->vcpu.run;
1227
d0bfb940
JK		 1228 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1229 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1230 kvm_run->debug.arch.exception = BP_VECTOR;
1231 return 0;
1232}
1233
851ba692 1234static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1235{
1236 int er;
1237
851ba692 1238 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1239 if (er != EMULATE_DONE)
7ee5d940 1240 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1241 return 1;
1242}
1243
851ba692 1244static int nm_interception(struct vcpu_svm *svm)
7807fa6c 1245{
a2fa3e9f 1246 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
ad312c7c 1247 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
a2fa3e9f 1248 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
e756fc62 1249 svm->vcpu.fpu_active = 1;
a2fa3e9f
GH		 1250
1251 return 1;
7807fa6c
AL		 1252}
1253
851ba692 1254static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1255{
1256 /*
1257 * On an #MC intercept the MCE handler is not called automatically in
1258 * the host. So do it by hand here.
1259 */
1260 asm volatile (
1261 "int $0x12\n");
1262 /* not sure if we ever come back to this point */
1263
1264 return 1;
1265}
1266
851ba692 1267static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1268{
851ba692
AK		 1269 struct kvm_run *kvm_run = svm->vcpu.run;
1270
46fe4ddd
JR		 1271 /*
1272 * VMCB is undefined after a SHUTDOWN intercept
1273 * so reinitialize it.
1274 */
a2fa3e9f 1275 clear_page(svm->vmcb);
e6101a96 1276 init_vmcb(svm);
46fe4ddd
JR		 1277
1278 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1279 return 0;
1280}
1281
851ba692 1282static int io_interception(struct vcpu_svm *svm)
6aa8b732 1283{
d77c26fc 1284 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1285 int size, in, string;
039576c0 1286 unsigned port;
6aa8b732 1287
e756fc62 1288 ++svm->vcpu.stat.io_exits;
6aa8b732 1289
a2fa3e9f 1290 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1291
e70669ab
LV		 1292 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1293
1294 if (string) {
3427318f 1295 if (emulate_instruction(&svm->vcpu,
851ba692 1296 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1297 return 0;
1298 return 1;
1299 }
1300
039576c0
AK		 1301 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1302 port = io_info >> 16;
1303 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1304
e93f36bc 1305 skip_emulated_instruction(&svm->vcpu);
851ba692 1306 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1307}
1308
851ba692 1309static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1310{
1311 return 1;
1312}
1313
851ba692 1314static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1315{
1316 ++svm->vcpu.stat.irq_exits;
1317 return 1;
1318}
1319
851ba692 1320static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1321{
1322 return 1;
1323}
1324
851ba692 1325static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1326{
5fdbf976 1327 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1328 skip_emulated_instruction(&svm->vcpu);
1329 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1330}
1331
851ba692 1332static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1333{
5fdbf976 1334 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1335 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1336 kvm_emulate_hypercall(&svm->vcpu);
1337 return 1;
02e235bc
AK		 1338}
1339
c0725420
AG		 1340static int nested_svm_check_permissions(struct vcpu_svm *svm)
1341{
1342 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1343 || !is_paging(&svm->vcpu)) {
1344 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1345 return 1;
1346 }
1347
1348 if (svm->vmcb->save.cpl) {
1349 kvm_inject_gp(&svm->vcpu, 0);
1350 return 1;
1351 }
1352
1353 return 0;
1354}
1355
cf74a78b
AG		 1356static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1357 bool has_error_code, u32 error_code)
1358{
0295ad7d
JR		 1359 if (!is_nested(svm))
1360 return 0;
cf74a78b 1361
0295ad7d
JR		 1362 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1363 svm->vmcb->control.exit_code_hi = 0;
1364 svm->vmcb->control.exit_info_1 = error_code;
1365 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1366
410e4d57 1367 return nested_svm_exit_handled(svm);
cf74a78b
AG		 1368}
1369
1370static inline int nested_svm_intr(struct vcpu_svm *svm)
1371{
26666957
JR		 1372 if (!is_nested(svm))
1373 return 0;
cf74a78b 1374
26666957
JR		 1375 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1376 return 0;
cf74a78b 1377
26666957
JR		 1378 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1379 return 0;
cf74a78b 1380
26666957
JR		 1381 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1382
cd3ff653
JR		 1383 if (svm->nested.intercept & 1ULL) {
1384 /*
1385 * The #vmexit can't be emulated here directly because this
1386 * code path runs with irqs and preemtion disabled. A
1387 * #vmexit emulation might sleep. Only signal request for
1388 * the #vmexit here.
1389 */
1390 svm->nested.exit_required = true;
236649de 1391 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
26666957 1392 return 1;
cf74a78b
AG		 1393 }
1394
1395 return 0;
1396}
1397
34f80cfa
JR		 1398static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1399{
1400 struct page *page;
1401
34f80cfa 1402 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1403 if (is_error_page(page))
1404 goto error;
1405
1406 return kmap_atomic(page, idx);
1407
1408error:
1409 kvm_release_page_clean(page);
1410 kvm_inject_gp(&svm->vcpu, 0);
1411
1412 return NULL;
1413}
1414
1415static void nested_svm_unmap(void *addr, enum km_type idx)
1416{
1417 struct page *page;
1418
1419 if (!addr)
1420 return;
1421
1422 page = kmap_atomic_to_page(addr);
1423
1424 kunmap_atomic(addr, idx);
1425 kvm_release_page_dirty(page);
1426}
1427
3d62d9aa 1428static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1429{
4c2161ae 1430 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1431 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1432 bool ret = false;
1433 u32 t0, t1;
1434 u8 *msrpm;
4c2161ae 1435
3d62d9aa
JR		 1436 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1437 return false;
1438
1439 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1440
1441 if (!msrpm)
1442 goto out;
4c2161ae
JR		 1443
1444 switch (msr) {
1445 case 0 ... 0x1fff:
1446 t0 = (msr * 2) % 8;
1447 t1 = msr / 8;
1448 break;
1449 case 0xc0000000 ... 0xc0001fff:
1450 t0 = (8192 + msr - 0xc0000000) * 2;
1451 t1 = (t0 / 8);
1452 t0 %= 8;
1453 break;
1454 case 0xc0010000 ... 0xc0011fff:
1455 t0 = (16384 + msr - 0xc0010000) * 2;
1456 t1 = (t0 / 8);
1457 t0 %= 8;
1458 break;
1459 default:
3d62d9aa
JR		 1460 ret = true;
1461 goto out;
4c2161ae 1462 }
4c2161ae 1463
3d62d9aa
JR		 1464 ret = msrpm[t1] & ((1 << param) << t0);
1465
1466out:
1467 nested_svm_unmap(msrpm, KM_USER0);
1468
1469 return ret;
4c2161ae
JR		 1470}
1471
410e4d57 1472static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1473{
cf74a78b 1474 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1475
410e4d57
JR		 1476 switch (exit_code) {
1477 case SVM_EXIT_INTR:
1478 case SVM_EXIT_NMI:
1479 return NESTED_EXIT_HOST;
cf74a78b 1480 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1481 case SVM_EXIT_NPF:
1482 if (npt_enabled)
1483 return NESTED_EXIT_HOST;
1484 break;
1485 /* When we're shadowing, trap PFs */
1486 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1487 if (!npt_enabled)
1488 return NESTED_EXIT_HOST;
1489 break;
1490 default:
1491 break;
cf74a78b
AG		 1492 }
1493
410e4d57
JR		 1494 return NESTED_EXIT_CONTINUE;
1495}
1496
1497/*
1498 * If this function returns true, this #vmexit was already handled
1499 */
1500static int nested_svm_exit_handled(struct vcpu_svm *svm)
1501{
1502 u32 exit_code = svm->vmcb->control.exit_code;
1503 int vmexit = NESTED_EXIT_HOST;
1504
cf74a78b 1505 switch (exit_code) {
9c4e40b9 1506 case SVM_EXIT_MSR:
3d62d9aa 1507 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1508 break;
cf74a78b
AG		 1509 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1510 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1511 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1512 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1513 break;
1514 }
1515 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1516 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1517 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1518 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1519 break;
1520 }
1521 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1522 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1523 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1524 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1525 break;
1526 }
1527 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1528 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1529 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1530 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1531 break;
1532 }
1533 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1534 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1535 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1536 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1537 break;
1538 }
1539 default: {
1540 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1541 if (svm->nested.intercept & exit_bits)
410e4d57 1542 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1543 }
1544 }
1545
410e4d57 1546 if (vmexit == NESTED_EXIT_DONE) {
9c4e40b9
JR		 1547 nested_svm_vmexit(svm);
1548 }
1549
1550 return vmexit;
cf74a78b
AG		 1551}
1552
0460a979
JR		 1553static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1554{
1555 struct vmcb_control_area *dst = &dst_vmcb->control;
1556 struct vmcb_control_area *from = &from_vmcb->control;
1557
1558 dst->intercept_cr_read = from->intercept_cr_read;
1559 dst->intercept_cr_write = from->intercept_cr_write;
1560 dst->intercept_dr_read = from->intercept_dr_read;
1561 dst->intercept_dr_write = from->intercept_dr_write;
1562 dst->intercept_exceptions = from->intercept_exceptions;
1563 dst->intercept = from->intercept;
1564 dst->iopm_base_pa = from->iopm_base_pa;
1565 dst->msrpm_base_pa = from->msrpm_base_pa;
1566 dst->tsc_offset = from->tsc_offset;
1567 dst->asid = from->asid;
1568 dst->tlb_ctl = from->tlb_ctl;
1569 dst->int_ctl = from->int_ctl;
1570 dst->int_vector = from->int_vector;
1571 dst->int_state = from->int_state;
1572 dst->exit_code = from->exit_code;
1573 dst->exit_code_hi = from->exit_code_hi;
1574 dst->exit_info_1 = from->exit_info_1;
1575 dst->exit_info_2 = from->exit_info_2;
1576 dst->exit_int_info = from->exit_int_info;
1577 dst->exit_int_info_err = from->exit_int_info_err;
1578 dst->nested_ctl = from->nested_ctl;
1579 dst->event_inj = from->event_inj;
1580 dst->event_inj_err = from->event_inj_err;
1581 dst->nested_cr3 = from->nested_cr3;
1582 dst->lbr_ctl = from->lbr_ctl;
1583}
1584
34f80cfa 1585static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1586{
34f80cfa 1587 struct vmcb *nested_vmcb;
e6aa9abd 1588 struct vmcb *hsave = svm->nested.hsave;
33740e40 1589 struct vmcb *vmcb = svm->vmcb;
cf74a78b 1590
17897f36
JR		 1591 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1592 vmcb->control.exit_info_1,
1593 vmcb->control.exit_info_2,
1594 vmcb->control.exit_int_info,
1595 vmcb->control.exit_int_info_err);
1596
34f80cfa
JR		 1597 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1598 if (!nested_vmcb)
1599 return 1;
1600
cf74a78b 1601 /* Give the current vmcb to the guest */
33740e40
JR		 1602 disable_gif(svm);
1603
1604 nested_vmcb->save.es = vmcb->save.es;
1605 nested_vmcb->save.cs = vmcb->save.cs;
1606 nested_vmcb->save.ss = vmcb->save.ss;
1607 nested_vmcb->save.ds = vmcb->save.ds;
1608 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1609 nested_vmcb->save.idtr = vmcb->save.idtr;
1610 if (npt_enabled)
1611 nested_vmcb->save.cr3 = vmcb->save.cr3;
1612 nested_vmcb->save.cr2 = vmcb->save.cr2;
1613 nested_vmcb->save.rflags = vmcb->save.rflags;
1614 nested_vmcb->save.rip = vmcb->save.rip;
1615 nested_vmcb->save.rsp = vmcb->save.rsp;
1616 nested_vmcb->save.rax = vmcb->save.rax;
1617 nested_vmcb->save.dr7 = vmcb->save.dr7;
1618 nested_vmcb->save.dr6 = vmcb->save.dr6;
1619 nested_vmcb->save.cpl = vmcb->save.cpl;
1620
1621 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1622 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1623 nested_vmcb->control.int_state = vmcb->control.int_state;
1624 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1625 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1626 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1627 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1628 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1629 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1630
1631 /*
1632 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1633 * to make sure that we do not lose injected events. So check event_inj
1634 * here and copy it to exit_int_info if it is valid.
1635 * Exit_int_info and event_inj can't be both valid because the case
1636 * below only happens on a VMRUN instruction intercept which has
1637 * no valid exit_int_info set.
1638 */
1639 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1640 struct vmcb_control_area *nc = &nested_vmcb->control;
1641
1642 nc->exit_int_info = vmcb->control.event_inj;
1643 nc->exit_int_info_err = vmcb->control.event_inj_err;
1644 }
1645
33740e40
JR		 1646 nested_vmcb->control.tlb_ctl = 0;
1647 nested_vmcb->control.event_inj = 0;
1648 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1649
1650 /* We always set V_INTR_MASKING and remember the old value in hflags */
1651 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1652 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1653
cf74a78b 1654 /* Restore the original control entries */
0460a979 1655 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1656
219b65dc
AG		 1657 kvm_clear_exception_queue(&svm->vcpu);
1658 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1659
1660 /* Restore selected save entries */
1661 svm->vmcb->save.es = hsave->save.es;
1662 svm->vmcb->save.cs = hsave->save.cs;
1663 svm->vmcb->save.ss = hsave->save.ss;
1664 svm->vmcb->save.ds = hsave->save.ds;
1665 svm->vmcb->save.gdtr = hsave->save.gdtr;
1666 svm->vmcb->save.idtr = hsave->save.idtr;
1667 svm->vmcb->save.rflags = hsave->save.rflags;
1668 svm_set_efer(&svm->vcpu, hsave->save.efer);
1669 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1670 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1671 if (npt_enabled) {
1672 svm->vmcb->save.cr3 = hsave->save.cr3;
1673 svm->vcpu.arch.cr3 = hsave->save.cr3;
1674 } else {
1675 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1676 }
1677 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1678 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1679 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1680 svm->vmcb->save.dr7 = 0;
1681 svm->vmcb->save.cpl = 0;
1682 svm->vmcb->control.exit_int_info = 0;
1683
cf74a78b 1684 /* Exit nested SVM mode */
e6aa9abd 1685 svm->nested.vmcb = 0;
cf74a78b 1686
34f80cfa 1687 nested_svm_unmap(nested_vmcb, KM_USER0);
cf74a78b
AG		 1688
1689 kvm_mmu_reset_context(&svm->vcpu);
1690 kvm_mmu_load(&svm->vcpu);
1691
1692 return 0;
1693}
3d6368ef 1694
9738b2c9 1695static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1696{
9738b2c9 1697 u32 *nested_msrpm;
3d6368ef 1698 int i;
9738b2c9
JR		 1699
1700 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1701 if (!nested_msrpm)
1702 return false;
1703
3d6368ef 1704 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1705 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1706
e6aa9abd 1707 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1708
9738b2c9
JR		 1709 nested_svm_unmap(nested_msrpm, KM_USER0);
1710
1711 return true;
3d6368ef
AG		 1712}
1713
9738b2c9 1714static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1715{
9738b2c9 1716 struct vmcb *nested_vmcb;
e6aa9abd 1717 struct vmcb *hsave = svm->nested.hsave;
defbba56 1718 struct vmcb *vmcb = svm->vmcb;
3d6368ef 1719
9738b2c9
JR		 1720 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1721 if (!nested_vmcb)
1722 return false;
1723
3d6368ef 1724 /* nested_vmcb is our indicator if nested SVM is activated */
e6aa9abd 1725 svm->nested.vmcb = svm->vmcb->save.rax;
3d6368ef 1726
0ac406de
JR		 1727 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1728 nested_vmcb->save.rip,
1729 nested_vmcb->control.int_ctl,
1730 nested_vmcb->control.event_inj,
1731 nested_vmcb->control.nested_ctl);
1732
3d6368ef 1733 /* Clear internal status */
219b65dc
AG		 1734 kvm_clear_exception_queue(&svm->vcpu);
1735 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1736
1737 /* Save the old vmcb, so we don't need to pick what we save, but
1738 can restore everything when a VMEXIT occurs */
defbba56
JR		 1739 hsave->save.es = vmcb->save.es;
1740 hsave->save.cs = vmcb->save.cs;
1741 hsave->save.ss = vmcb->save.ss;
1742 hsave->save.ds = vmcb->save.ds;
1743 hsave->save.gdtr = vmcb->save.gdtr;
1744 hsave->save.idtr = vmcb->save.idtr;
1745 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1746 hsave->save.cr0 = svm->vcpu.arch.cr0;
1747 hsave->save.cr4 = svm->vcpu.arch.cr4;
1748 hsave->save.rflags = vmcb->save.rflags;
1749 hsave->save.rip = svm->next_rip;
1750 hsave->save.rsp = vmcb->save.rsp;
1751 hsave->save.rax = vmcb->save.rax;
1752 if (npt_enabled)
1753 hsave->save.cr3 = vmcb->save.cr3;
1754 else
1755 hsave->save.cr3 = svm->vcpu.arch.cr3;
1756
0460a979 1757 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1758
1759 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1760 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1761 else
1762 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1763
1764 /* Load the nested guest state */
1765 svm->vmcb->save.es = nested_vmcb->save.es;
1766 svm->vmcb->save.cs = nested_vmcb->save.cs;
1767 svm->vmcb->save.ss = nested_vmcb->save.ss;
1768 svm->vmcb->save.ds = nested_vmcb->save.ds;
1769 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1770 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1771 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1772 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1773 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1774 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1775 if (npt_enabled) {
1776 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1777 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1778 } else {
1779 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1780 kvm_mmu_reset_context(&svm->vcpu);
1781 }
defbba56 1782 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1783 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1784 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1785 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1786 /* In case we don't even reach vcpu_run, the fields are not updated */
1787 svm->vmcb->save.rax = nested_vmcb->save.rax;
1788 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1789 svm->vmcb->save.rip = nested_vmcb->save.rip;
1790 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1791 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1792 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1793
1794 /* We don't want a nested guest to be more powerful than the guest,
1795 so all intercepts are ORed */
1796 svm->vmcb->control.intercept_cr_read |=
1797 nested_vmcb->control.intercept_cr_read;
1798 svm->vmcb->control.intercept_cr_write |=
1799 nested_vmcb->control.intercept_cr_write;
1800 svm->vmcb->control.intercept_dr_read |=
1801 nested_vmcb->control.intercept_dr_read;
1802 svm->vmcb->control.intercept_dr_write |=
1803 nested_vmcb->control.intercept_dr_write;
1804 svm->vmcb->control.intercept_exceptions |=
1805 nested_vmcb->control.intercept_exceptions;
1806
1807 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1808
e6aa9abd 1809 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1810
aad42c64
JR		 1811 /* cache intercepts */
1812 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1813 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1814 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1815 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1816 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1817 svm->nested.intercept = nested_vmcb->control.intercept;
1818
3d6368ef 1819 force_new_asid(&svm->vcpu);
3d6368ef 1820 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1821 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1822 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1823 else
1824 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1825
3d6368ef
AG		 1826 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1827 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1828 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1829 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1830 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1831
9738b2c9
JR		 1832 nested_svm_unmap(nested_vmcb, KM_USER0);
1833
2af9194d 1834 enable_gif(svm);
3d6368ef 1835
9738b2c9 1836 return true;
3d6368ef
AG		 1837}
1838
9966bf68 1839static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1840{
1841 to_vmcb->save.fs = from_vmcb->save.fs;
1842 to_vmcb->save.gs = from_vmcb->save.gs;
1843 to_vmcb->save.tr = from_vmcb->save.tr;
1844 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1845 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1846 to_vmcb->save.star = from_vmcb->save.star;
1847 to_vmcb->save.lstar = from_vmcb->save.lstar;
1848 to_vmcb->save.cstar = from_vmcb->save.cstar;
1849 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1850 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1851 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1852 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1853}
1854
851ba692 1855static int vmload_interception(struct vcpu_svm *svm)
5542675b 1856{
9966bf68
JR		 1857 struct vmcb *nested_vmcb;
1858
5542675b
AG		 1859 if (nested_svm_check_permissions(svm))
1860 return 1;
1861
1862 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1863 skip_emulated_instruction(&svm->vcpu);
1864
9966bf68
JR		 1865 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1866 if (!nested_vmcb)
1867 return 1;
1868
1869 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1870 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1871
1872 return 1;
1873}
1874
851ba692 1875static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1876{
9966bf68
JR		 1877 struct vmcb *nested_vmcb;
1878
5542675b
AG		 1879 if (nested_svm_check_permissions(svm))
1880 return 1;
1881
1882 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1883 skip_emulated_instruction(&svm->vcpu);
1884
9966bf68
JR		 1885 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1886 if (!nested_vmcb)
1887 return 1;
1888
1889 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1890 nested_svm_unmap(nested_vmcb, KM_USER0);
5542675b
AG		 1891
1892 return 1;
1893}
1894
851ba692 1895static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1896{
3d6368ef
AG		 1897 if (nested_svm_check_permissions(svm))
1898 return 1;
1899
1900 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1901 skip_emulated_instruction(&svm->vcpu);
1902
9738b2c9 1903 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1904 return 1;
1905
9738b2c9 1906 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1907 goto failed;
1908
1909 return 1;
1910
1911failed:
1912
1913 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1914 svm->vmcb->control.exit_code_hi = 0;
1915 svm->vmcb->control.exit_info_1 = 0;
1916 svm->vmcb->control.exit_info_2 = 0;
1917
1918 nested_svm_vmexit(svm);
3d6368ef
AG		 1919
1920 return 1;
1921}
1922
851ba692 1923static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1924{
1925 if (nested_svm_check_permissions(svm))
1926 return 1;
1927
1928 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1929 skip_emulated_instruction(&svm->vcpu);
1930
2af9194d 1931 enable_gif(svm);
1371d904
AG		 1932
1933 return 1;
1934}
1935
851ba692 1936static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 1937{
1938 if (nested_svm_check_permissions(svm))
1939 return 1;
1940
1941 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1942 skip_emulated_instruction(&svm->vcpu);
1943
2af9194d 1944 disable_gif(svm);
1371d904
AG		 1945
1946 /* After a CLGI no interrupts should come */
1947 svm_clear_vintr(svm);
1948 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1949
1950 return 1;
1951}
1952
851ba692 1953static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 1954{
1955 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 1956
ec1ff790
JR		 1957 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1958 vcpu->arch.regs[VCPU_REGS_RAX]);
1959
ff092385
AG		 1960 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1961 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1962
1963 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1964 skip_emulated_instruction(&svm->vcpu);
1965 return 1;
1966}
1967
532a46b9
JR		 1968static int skinit_interception(struct vcpu_svm *svm)
1969{
1970 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1971
1972 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1973 return 1;
1974}
1975
851ba692 1976static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 1977{
7ee5d940 1978 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 1979 return 1;
1980}
1981
851ba692 1982static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 1983{
37817f29 1984 u16 tss_selector;
64a7ec06
GN		 1985 int reason;
1986 int int_type = svm->vmcb->control.exit_int_info &
1987 SVM_EXITINTINFO_TYPE_MASK;
8317c298 1988 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 1989 uint32_t type =
1990 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1991 uint32_t idt_v =
1992 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 1993
1994 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 1995
37817f29
IE		 1996 if (svm->vmcb->control.exit_info_2 &
1997 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 1998 reason = TASK_SWITCH_IRET;
1999 else if (svm->vmcb->control.exit_info_2 &
2000 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2001 reason = TASK_SWITCH_JMP;
fe8e7f83 2002 else if (idt_v)
64a7ec06
GN		 2003 reason = TASK_SWITCH_GATE;
2004 else
2005 reason = TASK_SWITCH_CALL;
2006
fe8e7f83
GN		 2007 if (reason == TASK_SWITCH_GATE) {
2008 switch (type) {
2009 case SVM_EXITINTINFO_TYPE_NMI:
2010 svm->vcpu.arch.nmi_injected = false;
2011 break;
2012 case SVM_EXITINTINFO_TYPE_EXEPT:
2013 kvm_clear_exception_queue(&svm->vcpu);
2014 break;
2015 case SVM_EXITINTINFO_TYPE_INTR:
2016 kvm_clear_interrupt_queue(&svm->vcpu);
2017 break;
2018 default:
2019 break;
2020 }
2021 }
64a7ec06 2022
8317c298
GN		 2023 if (reason != TASK_SWITCH_GATE ||
2024 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2025 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2026 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2027 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2028
2029 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2030}
2031
851ba692 2032static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2033{
5fdbf976 2034 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2035 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2036 return 1;
6aa8b732
AK		 2037}
2038
851ba692 2039static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2040{
2041 ++svm->vcpu.stat.nmi_window_exits;
2042 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2043 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2044 return 1;
2045}
2046
851ba692 2047static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2048{
851ba692 2049 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2050 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2051 return 1;
2052}
2053
851ba692 2054static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2055{
851ba692 2056 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2057 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2058 return 1;
2059}
2060
851ba692 2061static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2062{
851ba692
AK		 2063 struct kvm_run *kvm_run = svm->vcpu.run;
2064
0a5fff19
GN		 2065 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2066 /* instruction emulation calls kvm_set_cr8() */
851ba692 2067 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2068 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2069 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2070 return 1;
95ba8273 2071 }
0a5fff19
GN		 2072 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2073 return 1;
1d075434
JR		 2074 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2075 return 0;
2076}
2077
6aa8b732
AK		 2078static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2079{
a2fa3e9f
GH		 2080 struct vcpu_svm *svm = to_svm(vcpu);
2081
6aa8b732 2082 switch (ecx) {
af24a4e4 2083 case MSR_IA32_TSC: {
20824f30 2084 u64 tsc_offset;
6aa8b732 2085
20824f30
JR		 2086 if (is_nested(svm))
2087 tsc_offset = svm->nested.hsave->control.tsc_offset;
2088 else
2089 tsc_offset = svm->vmcb->control.tsc_offset;
2090
2091 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2092 break;
2093 }
0e859cac 2094 case MSR_K6_STAR:
a2fa3e9f 2095 *data = svm->vmcb->save.star;
6aa8b732 2096 break;
0e859cac 2097#ifdef CONFIG_X86_64
6aa8b732 2098 case MSR_LSTAR:
a2fa3e9f 2099 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2100 break;
2101 case MSR_CSTAR:
a2fa3e9f 2102 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2103 break;
2104 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2105 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2106 break;
2107 case MSR_SYSCALL_MASK:
a2fa3e9f 2108 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2109 break;
2110#endif
2111 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2112 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2113 break;
2114 case MSR_IA32_SYSENTER_EIP:
017cb99e 2115 *data = svm->sysenter_eip;
6aa8b732
AK		 2116 break;
2117 case MSR_IA32_SYSENTER_ESP:
017cb99e 2118 *data = svm->sysenter_esp;
6aa8b732 2119 break;
a2938c80
JR		 2120 /* Nobody will change the following 5 values in the VMCB so
2121 we can safely return them on rdmsr. They will always be 0
2122 until LBRV is implemented. */
2123 case MSR_IA32_DEBUGCTLMSR:
2124 *data = svm->vmcb->save.dbgctl;
2125 break;
2126 case MSR_IA32_LASTBRANCHFROMIP:
2127 *data = svm->vmcb->save.br_from;
2128 break;
2129 case MSR_IA32_LASTBRANCHTOIP:
2130 *data = svm->vmcb->save.br_to;
2131 break;
2132 case MSR_IA32_LASTINTFROMIP:
2133 *data = svm->vmcb->save.last_excp_from;
2134 break;
2135 case MSR_IA32_LASTINTTOIP:
2136 *data = svm->vmcb->save.last_excp_to;
2137 break;
b286d5d8 2138 case MSR_VM_HSAVE_PA:
e6aa9abd 2139 *data = svm->nested.hsave_msr;
b286d5d8 2140 break;
eb6f302e
JR		 2141 case MSR_VM_CR:
2142 *data = 0;
2143 break;
c8a73f18
AG		 2144 case MSR_IA32_UCODE_REV:
2145 *data = 0x01000065;
2146 break;
6aa8b732 2147 default:
3bab1f5d 2148 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2149 }
2150 return 0;
2151}
2152
851ba692 2153static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2154{
ad312c7c 2155 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2156 u64 data;
2157
e756fc62 2158 if (svm_get_msr(&svm->vcpu, ecx, &data))
c1a5d4f9 2159 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2160 else {
229456fc 2161 trace_kvm_msr_read(ecx, data);
af9ca2d7 2162
5fdbf976 2163 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2164 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2165 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2166 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2167 }
2168 return 1;
2169}
2170
2171static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2172{
a2fa3e9f
GH		 2173 struct vcpu_svm *svm = to_svm(vcpu);
2174
6aa8b732 2175 switch (ecx) {
af24a4e4 2176 case MSR_IA32_TSC: {
20824f30
JR		 2177 u64 tsc_offset = data - native_read_tsc();
2178 u64 g_tsc_offset = 0;
2179
2180 if (is_nested(svm)) {
2181 g_tsc_offset = svm->vmcb->control.tsc_offset -
2182 svm->nested.hsave->control.tsc_offset;
2183 svm->nested.hsave->control.tsc_offset = tsc_offset;
2184 }
2185
2186 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2187
6aa8b732
AK		 2188 break;
2189 }
0e859cac 2190 case MSR_K6_STAR:
a2fa3e9f 2191 svm->vmcb->save.star = data;
6aa8b732 2192 break;
49b14f24 2193#ifdef CONFIG_X86_64
6aa8b732 2194 case MSR_LSTAR:
a2fa3e9f 2195 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2196 break;
2197 case MSR_CSTAR:
a2fa3e9f 2198 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2199 break;
2200 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2201 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2202 break;
2203 case MSR_SYSCALL_MASK:
a2fa3e9f 2204 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2205 break;
2206#endif
2207 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2208 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2209 break;
2210 case MSR_IA32_SYSENTER_EIP:
017cb99e 2211 svm->sysenter_eip = data;
a2fa3e9f 2212 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2213 break;
2214 case MSR_IA32_SYSENTER_ESP:
017cb99e 2215 svm->sysenter_esp = data;
a2fa3e9f 2216 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2217 break;
a2938c80 2218 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2219 if (!svm_has(SVM_FEATURE_LBRV)) {
2220 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2221 __func__, data);
24e09cbf
JR		 2222 break;
2223 }
2224 if (data & DEBUGCTL_RESERVED_BITS)
2225 return 1;
2226
2227 svm->vmcb->save.dbgctl = data;
2228 if (data & (1ULL<<0))
2229 svm_enable_lbrv(svm);
2230 else
2231 svm_disable_lbrv(svm);
a2938c80 2232 break;
b286d5d8 2233 case MSR_VM_HSAVE_PA:
e6aa9abd 2234 svm->nested.hsave_msr = data;
62b9abaa 2235 break;
3c5d0a44
AG		 2236 case MSR_VM_CR:
2237 case MSR_VM_IGNNE:
3c5d0a44
AG		 2238 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2239 break;
6aa8b732 2240 default:
3bab1f5d 2241 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2242 }
2243 return 0;
2244}
2245
851ba692 2246static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2247{
ad312c7c 2248 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2249 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2250 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2251
229456fc 2252 trace_kvm_msr_write(ecx, data);
af9ca2d7 2253
5fdbf976 2254 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2255 if (svm_set_msr(&svm->vcpu, ecx, data))
c1a5d4f9 2256 kvm_inject_gp(&svm->vcpu, 0);
6aa8b732 2257 else
e756fc62 2258 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2259 return 1;
2260}
2261
851ba692 2262static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2263{
e756fc62 2264 if (svm->vmcb->control.exit_info_1)
851ba692 2265 return wrmsr_interception(svm);
6aa8b732 2266 else
851ba692 2267 return rdmsr_interception(svm);
6aa8b732
AK		 2268}
2269
851ba692 2270static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2271{
851ba692
AK		 2272 struct kvm_run *kvm_run = svm->vcpu.run;
2273
f0b85051 2274 svm_clear_vintr(svm);
85f455f7 2275 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2276 /*
2277 * If the user space waits to inject interrupts, exit as soon as
2278 * possible
2279 */
8061823a
GN		 2280 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2281 kvm_run->request_interrupt_window &&
2282 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2283 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2284 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2285 return 0;
2286 }
2287
2288 return 1;
2289}
2290
565d0998
ML		 2291static int pause_interception(struct vcpu_svm *svm)
2292{
2293 kvm_vcpu_on_spin(&(svm->vcpu));
2294 return 1;
2295}
2296
851ba692 2297static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2298 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2299 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2300 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2301 [SVM_EXIT_READ_CR8] = emulate_on_interception,
6aa8b732
AK		 2302 /* for now: */
2303 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2304 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2305 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2306 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2307 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2308 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2309 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2310 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2311 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2312 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2313 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2314 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2315 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2316 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2317 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2318 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2319 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2320 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2321 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2322 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2323 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2324 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2325 [SVM_EXIT_SMI] = nop_on_interception,
2326 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2327 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2328 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2329 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2330 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2331 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2332 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2333 [SVM_EXIT_HLT] = halt_interception,
a7052897 2334 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2335 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2336 [SVM_EXIT_IOIO] = io_interception,
2337 [SVM_EXIT_MSR] = msr_interception,
2338 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2339 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2340 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2341 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2342 [SVM_EXIT_VMLOAD] = vmload_interception,
2343 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2344 [SVM_EXIT_STGI] = stgi_interception,
2345 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2346 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2347 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2348 [SVM_EXIT_MONITOR] = invalid_op_interception,
2349 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2350 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2351};
2352
851ba692 2353static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2354{
04d2cc77 2355 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2356 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2357 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2358
229456fc 2359 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2360
cd3ff653
JR		 2361 if (unlikely(svm->nested.exit_required)) {
2362 nested_svm_vmexit(svm);
2363 svm->nested.exit_required = false;
2364
2365 return 1;
2366 }
2367
cf74a78b 2368 if (is_nested(svm)) {
410e4d57
JR		 2369 int vmexit;
2370
d8cabddf
JR		 2371 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2372 svm->vmcb->control.exit_info_1,
2373 svm->vmcb->control.exit_info_2,
2374 svm->vmcb->control.exit_int_info,
2375 svm->vmcb->control.exit_int_info_err);
2376
410e4d57
JR		 2377 vmexit = nested_svm_exit_special(svm);
2378
2379 if (vmexit == NESTED_EXIT_CONTINUE)
2380 vmexit = nested_svm_exit_handled(svm);
2381
2382 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2383 return 1;
cf74a78b
AG		 2384 }
2385
a5c3832d
JR		 2386 svm_complete_interrupts(svm);
2387
709ddebf
JR		 2388 if (npt_enabled) {
2389 int mmu_reload = 0;
2390 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2391 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2392 mmu_reload = 1;
2393 }
2394 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2395 vcpu->arch.cr3 = svm->vmcb->save.cr3;
709ddebf
JR		 2396 if (mmu_reload) {
2397 kvm_mmu_reset_context(vcpu);
2398 kvm_mmu_load(vcpu);
2399 }
2400 }
2401
04d2cc77
AK		 2402
2403 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2404 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2405 kvm_run->fail_entry.hardware_entry_failure_reason
2406 = svm->vmcb->control.exit_code;
2407 return 0;
2408 }
2409
a2fa3e9f 2410 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2411 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2412 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2413 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2414 "exit_code 0x%x\n",
b8688d51 2415 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2416 exit_code);
2417
9d8f549d 2418 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2419 || !svm_exit_handlers[exit_code]) {
6aa8b732 2420 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2421 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2422 return 0;
2423 }
2424
851ba692 2425 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2426}
2427
2428static void reload_tss(struct kvm_vcpu *vcpu)
2429{
2430 int cpu = raw_smp_processor_id();
2431
0fe1e009
TH		 2432 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2433 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2434 load_TR_desc();
2435}
2436
e756fc62 2437static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2438{
2439 int cpu = raw_smp_processor_id();
2440
0fe1e009 2441 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2442
a2fa3e9f 2443 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2444 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2445 if (svm->asid_generation != sd->asid_generation)
2446 new_asid(svm, sd);
6aa8b732
AK		 2447}
2448
95ba8273
GN		 2449static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2450{
2451 struct vcpu_svm *svm = to_svm(vcpu);
2452
2453 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2454 vcpu->arch.hflags |= HF_NMI_MASK;
2455 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2456 ++vcpu->stat.nmi_injections;
2457}
6aa8b732 2458
85f455f7 2459static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2460{
2461 struct vmcb_control_area *control;
2462
229456fc 2463 trace_kvm_inj_virq(irq);
af9ca2d7 2464
fa89a817 2465 ++svm->vcpu.stat.irq_injections;
e756fc62 2466 control = &svm->vmcb->control;
85f455f7 2467 control->int_vector = irq;
6aa8b732
AK		 2468 control->int_ctl &= ~V_INTR_PRIO_MASK;
2469 control->int_ctl |= V_IRQ_MASK |
2470 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2471}
2472
66fd3f7f 2473static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2474{
2475 struct vcpu_svm *svm = to_svm(vcpu);
2476
2af9194d 2477 BUG_ON(!(gif_set(svm)));
cf74a78b 2478
219b65dc
AG		 2479 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2480 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2481}
2482
95ba8273 2483static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2484{
2485 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2486
95ba8273 2487 if (irr == -1)
aaacfc9a
JR		 2488 return;
2489
95ba8273
GN		 2490 if (tpr >= irr)
2491 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2492}
aaacfc9a 2493
95ba8273
GN		 2494static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2495{
2496 struct vcpu_svm *svm = to_svm(vcpu);
2497 struct vmcb *vmcb = svm->vmcb;
2498 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2499 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2500}
2501
3cfc3092
JK		 2502static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2503{
2504 struct vcpu_svm *svm = to_svm(vcpu);
2505
2506 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2507}
2508
2509static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2510{
2511 struct vcpu_svm *svm = to_svm(vcpu);
2512
2513 if (masked) {
2514 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2515 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2516 } else {
2517 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2518 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2519 }
2520}
2521
78646121
GN		 2522static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2523{
2524 struct vcpu_svm *svm = to_svm(vcpu);
2525 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2526 int ret;
2527
2528 if (!gif_set(svm) ||
2529 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2530 return 0;
2531
2532 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2533
2534 if (is_nested(svm))
2535 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2536
2537 return ret;
78646121
GN		 2538}
2539
9222be18 2540static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2541{
219b65dc 2542 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc
AG		 2543
2544 nested_svm_intr(svm);
2545
2546 /* In case GIF=0 we can't rely on the CPU to tell us when
2547 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2548 * The next time we get that intercept, this function will be
2549 * called again though and we'll get the vintr intercept. */
2af9194d 2550 if (gif_set(svm)) {
219b65dc
AG		 2551 svm_set_vintr(svm);
2552 svm_inject_irq(svm, 0x0);
2553 }
85f455f7
ED		 2554}
2555
95ba8273 2556static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2557{
04d2cc77 2558 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2559
44c11430
GN		 2560 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2561 == HF_NMI_MASK)
2562 return; /* IRET will cause a vm exit */
2563
2564 /* Something prevents NMI from been injected. Single step over
2565 possible problem (IRET or exception injection or interrupt
2566 shadow) */
6be7d306 2567 svm->nmi_singlestep = true;
44c11430
GN		 2568 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2569 update_db_intercept(vcpu);
c1150d8c
DL		 2570}
2571
cbc94022
IE		 2572static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2573{
2574 return 0;
2575}
2576
d9e368d6
AK		 2577static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2578{
2579 force_new_asid(vcpu);
2580}
2581
04d2cc77
AK		 2582static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2583{
2584}
2585
d7bf8221
JR		 2586static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2587{
2588 struct vcpu_svm *svm = to_svm(vcpu);
2589
2590 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2591 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2592 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2593 }
2594}
2595
649d6864
JR		 2596static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2597{
2598 struct vcpu_svm *svm = to_svm(vcpu);
2599 u64 cr8;
2600
649d6864
JR		 2601 cr8 = kvm_get_cr8(vcpu);
2602 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2603 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2604}
2605
9222be18
GN		 2606static void svm_complete_interrupts(struct vcpu_svm *svm)
2607{
2608 u8 vector;
2609 int type;
2610 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2611
44c11430
GN		 2612 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2613 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2614
9222be18
GN		 2615 svm->vcpu.arch.nmi_injected = false;
2616 kvm_clear_exception_queue(&svm->vcpu);
2617 kvm_clear_interrupt_queue(&svm->vcpu);
2618
2619 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2620 return;
2621
2622 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2623 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2624
2625 switch (type) {
2626 case SVM_EXITINTINFO_TYPE_NMI:
2627 svm->vcpu.arch.nmi_injected = true;
2628 break;
2629 case SVM_EXITINTINFO_TYPE_EXEPT:
2630 /* In case of software exception do not reinject an exception
2631 vector, but re-execute and instruction instead */
219b65dc
AG		 2632 if (is_nested(svm))
2633 break;
66fd3f7f 2634 if (kvm_exception_is_soft(vector))
9222be18
GN		 2635 break;
2636 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2637 u32 err = svm->vmcb->control.exit_int_info_err;
2638 kvm_queue_exception_e(&svm->vcpu, vector, err);
2639
2640 } else
2641 kvm_queue_exception(&svm->vcpu, vector);
2642 break;
2643 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2644 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2645 break;
2646 default:
2647 break;
2648 }
2649}
2650
80e31d4f
AK		 2651#ifdef CONFIG_X86_64
2652#define R "r"
2653#else
2654#define R "e"
2655#endif
2656
851ba692 2657static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2658{
a2fa3e9f 2659 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2660 u16 fs_selector;
2661 u16 gs_selector;
2662 u16 ldt_selector;
d9e368d6 2663
cd3ff653
JR		 2664 /*
2665 * A vmexit emulation is required before the vcpu can be executed
2666 * again.
2667 */
2668 if (unlikely(svm->nested.exit_required))
2669 return;
2670
5fdbf976
MT		 2671 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2672 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2673 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2674
e756fc62 2675 pre_svm_run(svm);
6aa8b732 2676
649d6864
JR		 2677 sync_lapic_to_cr8(vcpu);
2678
6aa8b732 2679 save_host_msrs(vcpu);
d6e88aec
AK		 2680 fs_selector = kvm_read_fs();
2681 gs_selector = kvm_read_gs();
2682 ldt_selector = kvm_read_ldt();
cda0ffdd 2683 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2684 /* required for live migration with NPT */
2685 if (npt_enabled)
2686 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2687
04d2cc77
AK		 2688 clgi();
2689
2690 local_irq_enable();
36241b8c 2691
6aa8b732 2692 asm volatile (
80e31d4f
AK		 2693 "push %%"R"bp; \n\t"
2694 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2695 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2696 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2697 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2698 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2699 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2700#ifdef CONFIG_X86_64
fb3f0f51
RR		 2701 "mov %c[r8](%[svm]), %%r8 \n\t"
2702 "mov %c[r9](%[svm]), %%r9 \n\t"
2703 "mov %c[r10](%[svm]), %%r10 \n\t"
2704 "mov %c[r11](%[svm]), %%r11 \n\t"
2705 "mov %c[r12](%[svm]), %%r12 \n\t"
2706 "mov %c[r13](%[svm]), %%r13 \n\t"
2707 "mov %c[r14](%[svm]), %%r14 \n\t"
2708 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2709#endif
2710
6aa8b732 2711 /* Enter guest mode */
80e31d4f
AK		 2712 "push %%"R"ax \n\t"
2713 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2714 __ex(SVM_VMLOAD) "\n\t"
2715 __ex(SVM_VMRUN) "\n\t"
2716 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2717 "pop %%"R"ax \n\t"
6aa8b732
AK		 2718
2719 /* Save guest registers, load host registers */
80e31d4f
AK		 2720 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2721 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2722 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2723 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2724 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2725 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2726#ifdef CONFIG_X86_64
fb3f0f51
RR		 2727 "mov %%r8, %c[r8](%[svm]) \n\t"
2728 "mov %%r9, %c[r9](%[svm]) \n\t"
2729 "mov %%r10, %c[r10](%[svm]) \n\t"
2730 "mov %%r11, %c[r11](%[svm]) \n\t"
2731 "mov %%r12, %c[r12](%[svm]) \n\t"
2732 "mov %%r13, %c[r13](%[svm]) \n\t"
2733 "mov %%r14, %c[r14](%[svm]) \n\t"
2734 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2735#endif
80e31d4f 2736 "pop %%"R"bp"
6aa8b732 2737 :
fb3f0f51 2738 : [svm]"a"(svm),
6aa8b732 2739 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2740 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2741 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2742 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2743 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2744 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2745 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2746#ifdef CONFIG_X86_64
ad312c7c
ZX		 2747 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2748 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2749 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2750 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2751 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2752 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2753 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2754 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2755#endif
54a08c04 2756 : "cc", "memory"
80e31d4f 2757 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2758#ifdef CONFIG_X86_64
54a08c04
LV		 2759 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2760#endif
2761 );
6aa8b732 2762
ad312c7c 2763 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2764 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2765 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2766 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2767
d6e88aec
AK		 2768 kvm_load_fs(fs_selector);
2769 kvm_load_gs(gs_selector);
2770 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2771 load_host_msrs(vcpu);
2772
2773 reload_tss(vcpu);
2774
56ba47dd
AK		 2775 local_irq_disable();
2776
2777 stgi();
2778
d7bf8221
JR		 2779 sync_cr8_to_lapic(vcpu);
2780
a2fa3e9f 2781 svm->next_rip = 0;
9222be18 2782
6de4f3ad
AK		 2783 if (npt_enabled) {
2784 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2785 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2786 }
6aa8b732
AK		 2787}
2788
80e31d4f
AK		 2789#undef R
2790
6aa8b732
AK		 2791static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2792{
a2fa3e9f
GH		 2793 struct vcpu_svm *svm = to_svm(vcpu);
2794
709ddebf
JR		 2795 if (npt_enabled) {
2796 svm->vmcb->control.nested_cr3 = root;
2797 force_new_asid(vcpu);
2798 return;
2799 }
2800
a2fa3e9f 2801 svm->vmcb->save.cr3 = root;
6aa8b732 2802 force_new_asid(vcpu);
7807fa6c
AL		 2803
2804 if (vcpu->fpu_active) {
a2fa3e9f
GH		 2805 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2806 svm->vmcb->save.cr0 |= X86_CR0_TS;
7807fa6c
AL		 2807 vcpu->fpu_active = 0;
2808 }
6aa8b732
AK		 2809}
2810
6aa8b732
AK		 2811static int is_disabled(void)
2812{
6031a61c
JR		 2813 u64 vm_cr;
2814
2815 rdmsrl(MSR_VM_CR, vm_cr);
2816 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2817 return 1;
2818
6aa8b732
AK		 2819 return 0;
2820}
2821
102d8325
IM		 2822static void
2823svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2824{
2825 /*
2826 * Patch in the VMMCALL instruction:
2827 */
2828 hypercall[0] = 0x0f;
2829 hypercall[1] = 0x01;
2830 hypercall[2] = 0xd9;
102d8325
IM		 2831}
2832
002c7f7c
YS		 2833static void svm_check_processor_compat(void *rtn)
2834{
2835 *(int *)rtn = 0;
2836}
2837
774ead3a
AK		 2838static bool svm_cpu_has_accelerated_tpr(void)
2839{
2840 return false;
2841}
2842
67253af5
SY		 2843static int get_npt_level(void)
2844{
2845#ifdef CONFIG_X86_64
2846 return PT64_ROOT_LEVEL;
2847#else
2848 return PT32E_ROOT_LEVEL;
2849#endif
2850}
2851
4b12f0de 2852static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2853{
2854 return 0;
2855}
2856
0e851880
SY		 2857static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2858{
2859}
2860
229456fc
MT		 2861static const struct trace_print_flags svm_exit_reasons_str[] = {
2862 { SVM_EXIT_READ_CR0, "read_cr0" },
2863 { SVM_EXIT_READ_CR3, "read_cr3" },
2864 { SVM_EXIT_READ_CR4, "read_cr4" },
2865 { SVM_EXIT_READ_CR8, "read_cr8" },
2866 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2867 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2868 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2869 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2870 { SVM_EXIT_READ_DR0, "read_dr0" },
2871 { SVM_EXIT_READ_DR1, "read_dr1" },
2872 { SVM_EXIT_READ_DR2, "read_dr2" },
2873 { SVM_EXIT_READ_DR3, "read_dr3" },
2874 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2875 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2876 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2877 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2878 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2879 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2880 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2881 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2882 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2883 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2884 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2885 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2886 { SVM_EXIT_INTR, "interrupt" },
2887 { SVM_EXIT_NMI, "nmi" },
2888 { SVM_EXIT_SMI, "smi" },
2889 { SVM_EXIT_INIT, "init" },
2890 { SVM_EXIT_VINTR, "vintr" },
2891 { SVM_EXIT_CPUID, "cpuid" },
2892 { SVM_EXIT_INVD, "invd" },
2893 { SVM_EXIT_HLT, "hlt" },
2894 { SVM_EXIT_INVLPG, "invlpg" },
2895 { SVM_EXIT_INVLPGA, "invlpga" },
2896 { SVM_EXIT_IOIO, "io" },
2897 { SVM_EXIT_MSR, "msr" },
2898 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2899 { SVM_EXIT_SHUTDOWN, "shutdown" },
2900 { SVM_EXIT_VMRUN, "vmrun" },
2901 { SVM_EXIT_VMMCALL, "hypercall" },
2902 { SVM_EXIT_VMLOAD, "vmload" },
2903 { SVM_EXIT_VMSAVE, "vmsave" },
2904 { SVM_EXIT_STGI, "stgi" },
2905 { SVM_EXIT_CLGI, "clgi" },
2906 { SVM_EXIT_SKINIT, "skinit" },
2907 { SVM_EXIT_WBINVD, "wbinvd" },
2908 { SVM_EXIT_MONITOR, "monitor" },
2909 { SVM_EXIT_MWAIT, "mwait" },
2910 { SVM_EXIT_NPF, "npf" },
2911 { -1, NULL }
2912};
2913
344f414f
JR		 2914static bool svm_gb_page_enable(void)
2915{
2916 return true;
2917}
2918
4e47c7a6
SY		 2919static bool svm_rdtscp_supported(void)
2920{
2921 return false;
2922}
2923
cbdd1bea 2924static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 2925 .cpu_has_kvm_support = has_svm,
2926 .disabled_by_bios = is_disabled,
2927 .hardware_setup = svm_hardware_setup,
2928 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 2929 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 2930 .hardware_enable = svm_hardware_enable,
2931 .hardware_disable = svm_hardware_disable,
774ead3a 2932 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 2933
2934 .vcpu_create = svm_create_vcpu,
2935 .vcpu_free = svm_free_vcpu,
04d2cc77 2936 .vcpu_reset = svm_vcpu_reset,
6aa8b732 2937
04d2cc77 2938 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 2939 .vcpu_load = svm_vcpu_load,
2940 .vcpu_put = svm_vcpu_put,
2941
2942 .set_guest_debug = svm_guest_debug,
2943 .get_msr = svm_get_msr,
2944 .set_msr = svm_set_msr,
2945 .get_segment_base = svm_get_segment_base,
2946 .get_segment = svm_get_segment,
2947 .set_segment = svm_set_segment,
2e4d2653 2948 .get_cpl = svm_get_cpl,
1747fb71 2949 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
25c4c276 2950 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 2951 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 2952 .set_cr3 = svm_set_cr3,
2953 .set_cr4 = svm_set_cr4,
2954 .set_efer = svm_set_efer,
2955 .get_idt = svm_get_idt,
2956 .set_idt = svm_set_idt,
2957 .get_gdt = svm_get_gdt,
2958 .set_gdt = svm_set_gdt,
2959 .get_dr = svm_get_dr,
2960 .set_dr = svm_set_dr,
6de4f3ad 2961 .cache_reg = svm_cache_reg,
6aa8b732
AK		 2962 .get_rflags = svm_get_rflags,
2963 .set_rflags = svm_set_rflags,
2964
6aa8b732 2965 .tlb_flush = svm_flush_tlb,
6aa8b732 2966
6aa8b732 2967 .run = svm_vcpu_run,
04d2cc77 2968 .handle_exit = handle_exit,
6aa8b732 2969 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 2970 .set_interrupt_shadow = svm_set_interrupt_shadow,
2971 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 2972 .patch_hypercall = svm_patch_hypercall,
2a8067f1 2973 .set_irq = svm_set_irq,
95ba8273 2974 .set_nmi = svm_inject_nmi,
298101da 2975 .queue_exception = svm_queue_exception,
78646121 2976 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 2977 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 2978 .get_nmi_mask = svm_get_nmi_mask,
2979 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 2980 .enable_nmi_window = enable_nmi_window,
2981 .enable_irq_window = enable_irq_window,
2982 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 2983
2984 .set_tss_addr = svm_set_tss_addr,
67253af5 2985 .get_tdp_level = get_npt_level,
4b12f0de 2986 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 2987
2988 .exit_reasons_str = svm_exit_reasons_str,
344f414f 2989 .gb_page_enable = svm_gb_page_enable,
0e851880
SY		 2990
2991 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 2992
2993 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 2994};
2995
2996static int __init svm_init(void)
2997{
cb498ea2 2998 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 2999 THIS_MODULE);
6aa8b732
AK		 3000}
3001
3002static void __exit svm_exit(void)
3003{
cb498ea2 3004 kvm_exit();
6aa8b732
AK		 3005}
3006
3007module_init(svm_init)
3008module_exit(svm_exit)
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