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KVM: x86: Add kvm_is_linear_rip
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
edf88417
AK		 16#include <linux/kvm_host.h>
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
5fdbf976 20#include "kvm_cache_regs.h"
fe4c7b19 21#include "x86.h"
e495606d 22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/vmalloc.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
6aa8b732 30
e495606d 31#include <asm/desc.h>
6aa8b732 32
63d1142f 33#include <asm/virtext.h>
229456fc 34#include "trace.h"
63d1142f 35
4ecac3fd
AK		 36#define __ex(x) __kvm_handle_fault_on_reboot(x)
37
6aa8b732
AK		 38MODULE_AUTHOR("Qumranet");
39MODULE_LICENSE("GPL");
40
41#define IOPM_ALLOC_ORDER 2
42#define MSRPM_ALLOC_ORDER 1
43
6aa8b732
AK		 44#define SEG_TYPE_LDT 2
45#define SEG_TYPE_BUSY_TSS16 3
46
80b7706e
JR		 47#define SVM_FEATURE_NPT (1 << 0)
48#define SVM_FEATURE_LBRV (1 << 1)
94c935a1 49#define SVM_FEATURE_SVML (1 << 2)
565d0998 50#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 51
410e4d57
JR		 52#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
53#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
54#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
55
24e09cbf
JR		 56#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
57
6c8166a7
AK		 58static const u32 host_save_user_msrs[] = {
59#ifdef CONFIG_X86_64
60 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
61 MSR_FS_BASE,
62#endif
63 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
64};
65
66#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
67
68struct kvm_vcpu;
69
e6aa9abd
JR		 70struct nested_state {
71 struct vmcb *hsave;
72 u64 hsave_msr;
73 u64 vmcb;
74
75 /* These are the merged vectors */
76 u32 *msrpm;
77
78 /* gpa pointers to the real vectors */
79 u64 vmcb_msrpm;
aad42c64 80
cd3ff653
JR		 81 /* A VMEXIT is required but not yet emulated */
82 bool exit_required;
83
aad42c64
JR		 84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read;
86 u16 intercept_cr_write;
87 u16 intercept_dr_read;
88 u16 intercept_dr_write;
89 u32 intercept_exceptions;
90 u64 intercept;
91
e6aa9abd
JR		 92};
93
6c8166a7
AK		 94struct vcpu_svm {
95 struct kvm_vcpu vcpu;
96 struct vmcb *vmcb;
97 unsigned long vmcb_pa;
98 struct svm_cpu_data *svm_data;
99 uint64_t asid_generation;
100 uint64_t sysenter_esp;
101 uint64_t sysenter_eip;
102
103 u64 next_rip;
104
105 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
106 u64 host_gs_base;
6c8166a7
AK		 107
108 u32 *msrpm;
6c8166a7 109
e6aa9abd 110 struct nested_state nested;
6be7d306
JK		 111
112 bool nmi_singlestep;
6c8166a7
AK		 113};
114
709ddebf
JR		 115/* enable NPT for AMD64 and X86 with PAE */
116#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
117static bool npt_enabled = true;
118#else
e3da3acd 119static bool npt_enabled = false;
709ddebf 120#endif
6c7dac72
JR		 121static int npt = 1;
122
123module_param(npt, int, S_IRUGO);
e3da3acd 124
4b6e4dca 125static int nested = 1;
236de055
AG		 126module_param(nested, int, S_IRUGO);
127
44874f84 128static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 129static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 130
410e4d57 131static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 132static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 133static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 134static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
135 bool has_error_code, u32 error_code);
136
a2fa3e9f
GH		 137static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
138{
fb3f0f51 139 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 140}
141
3d6368ef
AG		 142static inline bool is_nested(struct vcpu_svm *svm)
143{
e6aa9abd 144 return svm->nested.vmcb;
3d6368ef
AG		 145}
146
2af9194d
JR		 147static inline void enable_gif(struct vcpu_svm *svm)
148{
149 svm->vcpu.arch.hflags |= HF_GIF_MASK;
150}
151
152static inline void disable_gif(struct vcpu_svm *svm)
153{
154 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
155}
156
157static inline bool gif_set(struct vcpu_svm *svm)
158{
159 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
160}
161
4866d5e3 162static unsigned long iopm_base;
6aa8b732
AK		 163
164struct kvm_ldttss_desc {
165 u16 limit0;
166 u16 base0;
167 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
168 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
169 u32 base3;
170 u32 zero1;
171} __attribute__((packed));
172
173struct svm_cpu_data {
174 int cpu;
175
5008fdf5
AK		 176 u64 asid_generation;
177 u32 max_asid;
178 u32 next_asid;
6aa8b732
AK		 179 struct kvm_ldttss_desc *tss_desc;
180
181 struct page *save_area;
182};
183
184static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 185static uint32_t svm_features;
6aa8b732
AK		 186
187struct svm_init_data {
188 int cpu;
189 int r;
190};
191
192static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
193
9d8f549d 194#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 195#define MSRS_RANGE_SIZE 2048
196#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
197
198#define MAX_INST_SIZE 15
199
80b7706e
JR		 200static inline u32 svm_has(u32 feat)
201{
202 return svm_features & feat;
203}
204
6aa8b732
AK		 205static inline void clgi(void)
206{
4ecac3fd 207 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 208}
209
210static inline void stgi(void)
211{
4ecac3fd 212 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 213}
214
215static inline void invlpga(unsigned long addr, u32 asid)
216{
4ecac3fd 217 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
6aa8b732
AK		 218}
219
6aa8b732
AK		 220static inline void force_new_asid(struct kvm_vcpu *vcpu)
221{
a2fa3e9f 222 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 223}
224
225static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
226{
227 force_new_asid(vcpu);
228}
229
230static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
231{
709ddebf 232 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 233 efer &= ~EFER_LME;
6aa8b732 234
9962d032 235 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
f6801dff 236 vcpu->arch.efer = efer;
6aa8b732
AK		 237}
238
6aa8b732
AK		 239static int is_external_interrupt(u32 info)
240{
241 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
242 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
243}
244
2809f5d2
GC		 245static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
246{
247 struct vcpu_svm *svm = to_svm(vcpu);
248 u32 ret = 0;
249
250 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 251 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 252 return ret & mask;
253}
254
255static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
256{
257 struct vcpu_svm *svm = to_svm(vcpu);
258
259 if (mask == 0)
260 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
261 else
262 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
263
264}
265
6aa8b732
AK		 266static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
267{
a2fa3e9f
GH		 268 struct vcpu_svm *svm = to_svm(vcpu);
269
270 if (!svm->next_rip) {
851ba692 271 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 272 EMULATE_DONE)
273 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 274 return;
275 }
5fdbf976
MT		 276 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
277 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
278 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 279
5fdbf976 280 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 281 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 282}
283
116a4752
JK		 284static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
285 bool has_error_code, u32 error_code)
286{
287 struct vcpu_svm *svm = to_svm(vcpu);
288
289 /* If we are within a nested VM we'd better #VMEXIT and let the
290 guest handle the exception */
291 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
292 return;
293
294 svm->vmcb->control.event_inj = nr
295 | SVM_EVTINJ_VALID
296 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
297 | SVM_EVTINJ_TYPE_EXEPT;
298 svm->vmcb->control.event_inj_err = error_code;
299}
300
6aa8b732
AK		 301static int has_svm(void)
302{
63d1142f 303 const char *msg;
6aa8b732 304
63d1142f 305 if (!cpu_has_svm(&msg)) {
ff81ff10 306 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 307 return 0;
308 }
309
6aa8b732
AK		 310 return 1;
311}
312
313static void svm_hardware_disable(void *garbage)
314{
2c8dceeb 315 cpu_svm_disable();
6aa8b732
AK		 316}
317
10474ae8 318static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 319{
320
0fe1e009 321 struct svm_cpu_data *sd;
6aa8b732 322 uint64_t efer;
89a27f4d 323 struct desc_ptr gdt_descr;
6aa8b732
AK		 324 struct desc_struct *gdt;
325 int me = raw_smp_processor_id();
326
10474ae8
AG		 327 rdmsrl(MSR_EFER, efer);
328 if (efer & EFER_SVME)
329 return -EBUSY;
330
6aa8b732 331 if (!has_svm()) {
e6732a5a
ZA		 332 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
333 me);
10474ae8 334 return -EINVAL;
6aa8b732 335 }
0fe1e009 336 sd = per_cpu(svm_data, me);
6aa8b732 337
0fe1e009 338 if (!sd) {
e6732a5a 339 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 340 me);
10474ae8 341 return -EINVAL;
6aa8b732
AK		 342 }
343
0fe1e009
TH		 344 sd->asid_generation = 1;
345 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
346 sd->next_asid = sd->max_asid + 1;
6aa8b732 347
b792c344 348 kvm_get_gdt(&gdt_descr);
89a27f4d 349 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 350 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 351
9962d032 352 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 353
d0316554 354 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8
AG		 355
356 return 0;
6aa8b732
AK		 357}
358
0da1db75
JR		 359static void svm_cpu_uninit(int cpu)
360{
0fe1e009 361 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 362
0fe1e009 363 if (!sd)
0da1db75
JR		 364 return;
365
366 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 367 __free_page(sd->save_area);
368 kfree(sd);
0da1db75
JR		 369}
370
6aa8b732
AK		 371static int svm_cpu_init(int cpu)
372{
0fe1e009 373 struct svm_cpu_data *sd;
6aa8b732
AK		 374 int r;
375
0fe1e009
TH		 376 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
377 if (!sd)
6aa8b732 378 return -ENOMEM;
0fe1e009
TH		 379 sd->cpu = cpu;
380 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 381 r = -ENOMEM;
0fe1e009 382 if (!sd->save_area)
6aa8b732
AK		 383 goto err_1;
384
0fe1e009 385 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 386
387 return 0;
388
389err_1:
0fe1e009 390 kfree(sd);
6aa8b732
AK		 391 return r;
392
393}
394
bfc733a7
RR		 395static void set_msr_interception(u32 *msrpm, unsigned msr,
396 int read, int write)
6aa8b732
AK		 397{
398 int i;
399
400 for (i = 0; i < NUM_MSR_MAPS; i++) {
401 if (msr >= msrpm_ranges[i] &&
402 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
403 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
404 msrpm_ranges[i]) * 2;
405
406 u32 *base = msrpm + (msr_offset / 32);
407 u32 msr_shift = msr_offset % 32;
408 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
409 *base = (*base & ~(0x3 << msr_shift)) |
410 (mask << msr_shift);
bfc733a7 411 return;
6aa8b732
AK		 412 }
413 }
bfc733a7 414 BUG();
6aa8b732
AK		 415}
416
f65c229c
JR		 417static void svm_vcpu_init_msrpm(u32 *msrpm)
418{
419 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
420
421#ifdef CONFIG_X86_64
422 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
424 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
425 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
426 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
427 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
428#endif
429 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
430 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
f65c229c
JR		 431}
432
24e09cbf
JR		 433static void svm_enable_lbrv(struct vcpu_svm *svm)
434{
435 u32 *msrpm = svm->msrpm;
436
437 svm->vmcb->control.lbr_ctl = 1;
438 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
440 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
441 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
442}
443
444static void svm_disable_lbrv(struct vcpu_svm *svm)
445{
446 u32 *msrpm = svm->msrpm;
447
448 svm->vmcb->control.lbr_ctl = 0;
449 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
451 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
452 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
453}
454
6aa8b732
AK		 455static __init int svm_hardware_setup(void)
456{
457 int cpu;
458 struct page *iopm_pages;
f65c229c 459 void *iopm_va;
6aa8b732
AK		 460 int r;
461
6aa8b732
AK		 462 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
463
464 if (!iopm_pages)
465 return -ENOMEM;
c8681339
AL		 466
467 iopm_va = page_address(iopm_pages);
468 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 469 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
470
50a37eb4
JR		 471 if (boot_cpu_has(X86_FEATURE_NX))
472 kvm_enable_efer_bits(EFER_NX);
473
1b2fd70c
AG		 474 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
475 kvm_enable_efer_bits(EFER_FFXSR);
476
236de055
AG		 477 if (nested) {
478 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
479 kvm_enable_efer_bits(EFER_SVME);
480 }
481
3230bb47 482 for_each_possible_cpu(cpu) {
6aa8b732
AK		 483 r = svm_cpu_init(cpu);
484 if (r)
f65c229c 485 goto err;
6aa8b732 486 }
33bd6a0b
JR		 487
488 svm_features = cpuid_edx(SVM_CPUID_FUNC);
489
e3da3acd
JR		 490 if (!svm_has(SVM_FEATURE_NPT))
491 npt_enabled = false;
492
6c7dac72
JR		 493 if (npt_enabled && !npt) {
494 printk(KERN_INFO "kvm: Nested Paging disabled\n");
495 npt_enabled = false;
496 }
497
18552672 498 if (npt_enabled) {
e3da3acd 499 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 500 kvm_enable_tdp();
5f4cb662
JR		 501 } else
502 kvm_disable_tdp();
e3da3acd 503
6aa8b732
AK		 504 return 0;
505
f65c229c 506err:
6aa8b732
AK		 507 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
508 iopm_base = 0;
509 return r;
510}
511
512static __exit void svm_hardware_unsetup(void)
513{
0da1db75
JR		 514 int cpu;
515
3230bb47 516 for_each_possible_cpu(cpu)
0da1db75
JR		 517 svm_cpu_uninit(cpu);
518
6aa8b732 519 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 520 iopm_base = 0;
6aa8b732
AK		 521}
522
523static void init_seg(struct vmcb_seg *seg)
524{
525 seg->selector = 0;
526 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
527 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
528 seg->limit = 0xffff;
529 seg->base = 0;
530}
531
532static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
533{
534 seg->selector = 0;
535 seg->attrib = SVM_SELECTOR_P_MASK | type;
536 seg->limit = 0xffff;
537 seg->base = 0;
538}
539
e6101a96 540static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 541{
e6101a96
JR		 542 struct vmcb_control_area *control = &svm->vmcb->control;
543 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 544
bff78274
AK		 545 svm->vcpu.fpu_active = 1;
546
6aa8b732
AK		 547 control->intercept_cr_read = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
649d6864 549 INTERCEPT_CR4_MASK;
6aa8b732
AK		 550
551 control->intercept_cr_write = INTERCEPT_CR0_MASK |
552 INTERCEPT_CR3_MASK |
80a8119c
AK		 553 INTERCEPT_CR4_MASK |
554 INTERCEPT_CR8_MASK;
6aa8b732
AK		 555
556 control->intercept_dr_read = INTERCEPT_DR0_MASK |
557 INTERCEPT_DR1_MASK |
558 INTERCEPT_DR2_MASK |
727f5a23
JK		 559 INTERCEPT_DR3_MASK |
560 INTERCEPT_DR4_MASK |
561 INTERCEPT_DR5_MASK |
562 INTERCEPT_DR6_MASK |
563 INTERCEPT_DR7_MASK;
6aa8b732
AK		 564
565 control->intercept_dr_write = INTERCEPT_DR0_MASK |
566 INTERCEPT_DR1_MASK |
567 INTERCEPT_DR2_MASK |
568 INTERCEPT_DR3_MASK |
727f5a23 569 INTERCEPT_DR4_MASK |
6aa8b732 570 INTERCEPT_DR5_MASK |
727f5a23 571 INTERCEPT_DR6_MASK |
6aa8b732
AK		 572 INTERCEPT_DR7_MASK;
573
7aa81cc0 574 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 575 (1 << UD_VECTOR) |
576 (1 << MC_VECTOR);
6aa8b732
AK		 577
578
579 control->intercept = (1ULL << INTERCEPT_INTR) |
580 (1ULL << INTERCEPT_NMI) |
0152527b 581 (1ULL << INTERCEPT_SMI) |
d225157b 582 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 583 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 584 (1ULL << INTERCEPT_INVD) |
6aa8b732 585 (1ULL << INTERCEPT_HLT) |
a7052897 586 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 587 (1ULL << INTERCEPT_INVLPGA) |
588 (1ULL << INTERCEPT_IOIO_PROT) |
589 (1ULL << INTERCEPT_MSR_PROT) |
590 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 591 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 592 (1ULL << INTERCEPT_VMRUN) |
593 (1ULL << INTERCEPT_VMMCALL) |
594 (1ULL << INTERCEPT_VMLOAD) |
595 (1ULL << INTERCEPT_VMSAVE) |
596 (1ULL << INTERCEPT_STGI) |
597 (1ULL << INTERCEPT_CLGI) |
916ce236 598 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 599 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 600 (1ULL << INTERCEPT_MONITOR) |
601 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 602
603 control->iopm_base_pa = iopm_base;
f65c229c 604 control->msrpm_base_pa = __pa(svm->msrpm);
0cc5064d 605 control->tsc_offset = 0;
6aa8b732
AK		 606 control->int_ctl = V_INTR_MASKING_MASK;
607
608 init_seg(&save->es);
609 init_seg(&save->ss);
610 init_seg(&save->ds);
611 init_seg(&save->fs);
612 init_seg(&save->gs);
613
614 save->cs.selector = 0xf000;
615 /* Executable/Readable Code Segment */
616 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
617 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
618 save->cs.limit = 0xffff;
d92899a0
AK		 619 /*
620 * cs.base should really be 0xffff0000, but vmx can't handle that, so
621 * be consistent with it.
622 *
623 * Replace when we have real mode working for vmx.
624 */
625 save->cs.base = 0xf0000;
6aa8b732
AK		 626
627 save->gdtr.limit = 0xffff;
628 save->idtr.limit = 0xffff;
629
630 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
631 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
632
9962d032 633 save->efer = EFER_SVME;
d77c26fc 634 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 635 save->dr7 = 0x400;
636 save->rflags = 2;
637 save->rip = 0x0000fff0;
5fdbf976 638 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 639
18fa000a
EH		 640 /* This is the guest-visible cr0 value.
641 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 642 */
18fa000a
EH		 643 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
644 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
645
66aee91a 646 save->cr4 = X86_CR4_PAE;
6aa8b732 647 /* rdx = ?? */
709ddebf
JR		 648
649 if (npt_enabled) {
650 /* Setup VMCB for Nested Paging */
651 control->nested_ctl = 1;
a7052897
MT		 652 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
653 (1ULL << INTERCEPT_INVLPG));
709ddebf 654 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 655 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
656 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 657 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 658 save->cr3 = 0;
659 save->cr4 = 0;
660 }
a79d2f18 661 force_new_asid(&svm->vcpu);
1371d904 662
e6aa9abd 663 svm->nested.vmcb = 0;
2af9194d
JR		 664 svm->vcpu.arch.hflags = 0;
665
565d0998
ML		 666 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
667 control->pause_filter_count = 3000;
668 control->intercept |= (1ULL << INTERCEPT_PAUSE);
669 }
670
2af9194d 671 enable_gif(svm);
6aa8b732
AK		 672}
673
e00c8cf2 674static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 675{
676 struct vcpu_svm *svm = to_svm(vcpu);
677
e6101a96 678 init_vmcb(svm);
70433389 679
c5af89b6 680 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 681 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 682 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
683 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 684 }
5fdbf976
MT		 685 vcpu->arch.regs_avail = ~0;
686 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 687
688 return 0;
04d2cc77
AK		 689}
690
fb3f0f51 691static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 692{
a2fa3e9f 693 struct vcpu_svm *svm;
6aa8b732 694 struct page *page;
f65c229c 695 struct page *msrpm_pages;
b286d5d8 696 struct page *hsave_page;
3d6368ef 697 struct page *nested_msrpm_pages;
fb3f0f51 698 int err;
6aa8b732 699
c16f862d 700 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 701 if (!svm) {
702 err = -ENOMEM;
703 goto out;
704 }
705
706 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
707 if (err)
708 goto free_svm;
709
b7af4043 710 err = -ENOMEM;
6aa8b732 711 page = alloc_page(GFP_KERNEL);
b7af4043 712 if (!page)
fb3f0f51 713 goto uninit;
6aa8b732 714
f65c229c
JR		 715 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
716 if (!msrpm_pages)
b7af4043 717 goto free_page1;
3d6368ef
AG		 718
719 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
720 if (!nested_msrpm_pages)
b7af4043 721 goto free_page2;
f65c229c 722
b286d5d8
AG		 723 hsave_page = alloc_page(GFP_KERNEL);
724 if (!hsave_page)
b7af4043
TY		 725 goto free_page3;
726
e6aa9abd 727 svm->nested.hsave = page_address(hsave_page);
b286d5d8 728
b7af4043
TY		 729 svm->msrpm = page_address(msrpm_pages);
730 svm_vcpu_init_msrpm(svm->msrpm);
731
e6aa9abd 732 svm->nested.msrpm = page_address(nested_msrpm_pages);
3d6368ef 733
a2fa3e9f
GH		 734 svm->vmcb = page_address(page);
735 clear_page(svm->vmcb);
736 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
737 svm->asid_generation = 0;
e6101a96 738 init_vmcb(svm);
a2fa3e9f 739
fb3f0f51 740 fx_init(&svm->vcpu);
ad312c7c 741 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 742 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 743 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 744
fb3f0f51 745 return &svm->vcpu;
36241b8c 746
b7af4043
TY		 747free_page3:
748 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
749free_page2:
750 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
751free_page1:
752 __free_page(page);
fb3f0f51
RR		 753uninit:
754 kvm_vcpu_uninit(&svm->vcpu);
755free_svm:
a4770347 756 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 757out:
758 return ERR_PTR(err);
6aa8b732
AK		 759}
760
761static void svm_free_vcpu(struct kvm_vcpu *vcpu)
762{
a2fa3e9f
GH		 763 struct vcpu_svm *svm = to_svm(vcpu);
764
fb3f0f51 765 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 766 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 767 __free_page(virt_to_page(svm->nested.hsave));
768 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 769 kvm_vcpu_uninit(vcpu);
a4770347 770 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 771}
772
15ad7146 773static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 774{
a2fa3e9f 775 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 776 int i;
0cc5064d 777
0cc5064d 778 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 779 u64 delta;
0cc5064d 780
953899b6
JR		 781 if (check_tsc_unstable()) {
782 /*
783 * Make sure that the guest sees a monotonically
784 * increasing TSC.
785 */
786 delta = vcpu->arch.host_tsc - native_read_tsc();
787 svm->vmcb->control.tsc_offset += delta;
788 if (is_nested(svm))
789 svm->nested.hsave->control.tsc_offset += delta;
790 }
0cc5064d 791 vcpu->cpu = cpu;
2f599714 792 kvm_migrate_timers(vcpu);
4b656b12 793 svm->asid_generation = 0;
0cc5064d 794 }
94dfbdb3
AL		 795
796 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 797 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 798}
799
800static void svm_vcpu_put(struct kvm_vcpu *vcpu)
801{
a2fa3e9f 802 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 803 int i;
804
e1beb1d3 805 ++vcpu->stat.host_state_reload;
94dfbdb3 806 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 807 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 808
e935d48e 809 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 810}
811
6aa8b732
AK		 812static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
813{
a2fa3e9f 814 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 815}
816
817static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
818{
a2fa3e9f 819 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 820}
821
6de4f3ad
AK		 822static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
823{
824 switch (reg) {
825 case VCPU_EXREG_PDPTR:
826 BUG_ON(!npt_enabled);
827 load_pdptrs(vcpu, vcpu->arch.cr3);
828 break;
829 default:
830 BUG();
831 }
832}
833
f0b85051
AG		 834static void svm_set_vintr(struct vcpu_svm *svm)
835{
836 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
837}
838
839static void svm_clear_vintr(struct vcpu_svm *svm)
840{
841 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
842}
843
6aa8b732
AK		 844static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
845{
a2fa3e9f 846 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 847
848 switch (seg) {
849 case VCPU_SREG_CS: return &save->cs;
850 case VCPU_SREG_DS: return &save->ds;
851 case VCPU_SREG_ES: return &save->es;
852 case VCPU_SREG_FS: return &save->fs;
853 case VCPU_SREG_GS: return &save->gs;
854 case VCPU_SREG_SS: return &save->ss;
855 case VCPU_SREG_TR: return &save->tr;
856 case VCPU_SREG_LDTR: return &save->ldtr;
857 }
858 BUG();
8b6d44c7 859 return NULL;
6aa8b732
AK		 860}
861
862static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
863{
864 struct vmcb_seg *s = svm_seg(vcpu, seg);
865
866 return s->base;
867}
868
869static void svm_get_segment(struct kvm_vcpu *vcpu,
870 struct kvm_segment *var, int seg)
871{
872 struct vmcb_seg *s = svm_seg(vcpu, seg);
873
874 var->base = s->base;
875 var->limit = s->limit;
876 var->selector = s->selector;
877 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
878 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
879 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
880 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
881 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
882 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
883 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
884 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 885
19bca6ab
AP		 886 /* AMD's VMCB does not have an explicit unusable field, so emulate it
887 * for cross vendor migration purposes by "not present"
888 */
889 var->unusable = !var->present || (var->type == 0);
890
1fbdc7a5
AP		 891 switch (seg) {
892 case VCPU_SREG_CS:
893 /*
894 * SVM always stores 0 for the 'G' bit in the CS selector in
895 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
896 * Intel's VMENTRY has a check on the 'G' bit.
897 */
25022acc 898 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 899 break;
900 case VCPU_SREG_TR:
901 /*
902 * Work around a bug where the busy flag in the tr selector
903 * isn't exposed
904 */
c0d09828 905 var->type |= 0x2;
1fbdc7a5
AP		 906 break;
907 case VCPU_SREG_DS:
908 case VCPU_SREG_ES:
909 case VCPU_SREG_FS:
910 case VCPU_SREG_GS:
911 /*
912 * The accessed bit must always be set in the segment
913 * descriptor cache, although it can be cleared in the
914 * descriptor, the cached bit always remains at 1. Since
915 * Intel has a check on this, set it here to support
916 * cross-vendor migration.
917 */
918 if (!var->unusable)
919 var->type |= 0x1;
920 break;
b586eb02
AP		 921 case VCPU_SREG_SS:
922 /* On AMD CPUs sometimes the DB bit in the segment
923 * descriptor is left as 1, although the whole segment has
924 * been made unusable. Clear it here to pass an Intel VMX
925 * entry check when cross vendor migrating.
926 */
927 if (var->unusable)
928 var->db = 0;
929 break;
1fbdc7a5 930 }
6aa8b732
AK		 931}
932
2e4d2653
IE		 933static int svm_get_cpl(struct kvm_vcpu *vcpu)
934{
935 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
936
937 return save->cpl;
938}
939
89a27f4d 940static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 941{
a2fa3e9f
GH		 942 struct vcpu_svm *svm = to_svm(vcpu);
943
89a27f4d
GN		 944 dt->size = svm->vmcb->save.idtr.limit;
945 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 946}
947
89a27f4d 948static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 949{
a2fa3e9f
GH		 950 struct vcpu_svm *svm = to_svm(vcpu);
951
89a27f4d
GN		 952 svm->vmcb->save.idtr.limit = dt->size;
953 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 954}
955
89a27f4d 956static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 957{
a2fa3e9f
GH		 958 struct vcpu_svm *svm = to_svm(vcpu);
959
89a27f4d
GN		 960 dt->size = svm->vmcb->save.gdtr.limit;
961 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 962}
963
89a27f4d 964static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 965{
a2fa3e9f
GH		 966 struct vcpu_svm *svm = to_svm(vcpu);
967
89a27f4d
GN		 968 svm->vmcb->save.gdtr.limit = dt->size;
969 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 970}
971
e8467fda
AK		 972static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
973{
974}
975
25c4c276 976static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 977{
978}
979
d225157b
AK		 980static void update_cr0_intercept(struct vcpu_svm *svm)
981{
66a562f7 982 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 983 ulong gcr0 = svm->vcpu.arch.cr0;
984 u64 *hcr0 = &svm->vmcb->save.cr0;
985
986 if (!svm->vcpu.fpu_active)
987 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
988 else
989 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
990 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
991
992
993 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 994 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
995 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
996 if (is_nested(svm)) {
997 struct vmcb *hsave = svm->nested.hsave;
998
999 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1000 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1001 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1002 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1003 }
d225157b
AK		 1004 } else {
1005 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1006 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1007 if (is_nested(svm)) {
1008 struct vmcb *hsave = svm->nested.hsave;
1009
1010 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1011 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1012 }
d225157b
AK		 1013 }
1014}
1015
6aa8b732
AK		 1016static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1017{
a2fa3e9f
GH		 1018 struct vcpu_svm *svm = to_svm(vcpu);
1019
05b3e0c2 1020#ifdef CONFIG_X86_64
f6801dff 1021 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1022 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1023 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1024 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1025 }
1026
d77c26fc 1027 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1028 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1029 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1030 }
1031 }
1032#endif
ad312c7c 1033 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1034
1035 if (!npt_enabled)
1036 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1037
1038 if (!vcpu->fpu_active)
334df50a 1039 cr0 |= X86_CR0_TS;
709ddebf
JR		 1040 /*
1041 * re-enable caching here because the QEMU bios
1042 * does not do it - this results in some delay at
1043 * reboot
1044 */
1045 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1046 svm->vmcb->save.cr0 = cr0;
d225157b 1047 update_cr0_intercept(svm);
6aa8b732
AK		 1048}
1049
1050static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1051{
6394b649 1052 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1053 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1054
1055 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1056 force_new_asid(vcpu);
6394b649 1057
ec077263
JR		 1058 vcpu->arch.cr4 = cr4;
1059 if (!npt_enabled)
1060 cr4 |= X86_CR4_PAE;
6394b649 1061 cr4 |= host_cr4_mce;
ec077263 1062 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1063}
1064
1065static void svm_set_segment(struct kvm_vcpu *vcpu,
1066 struct kvm_segment *var, int seg)
1067{
a2fa3e9f 1068 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1069 struct vmcb_seg *s = svm_seg(vcpu, seg);
1070
1071 s->base = var->base;
1072 s->limit = var->limit;
1073 s->selector = var->selector;
1074 if (var->unusable)
1075 s->attrib = 0;
1076 else {
1077 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1078 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1079 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1080 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1081 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1082 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1083 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1084 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1085 }
1086 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1087 svm->vmcb->save.cpl
1088 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1089 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1090
1091}
1092
44c11430 1093static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1094{
d0bfb940
JK		 1095 struct vcpu_svm *svm = to_svm(vcpu);
1096
d0bfb940
JK		 1097 svm->vmcb->control.intercept_exceptions &=
1098 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1099
6be7d306 1100 if (svm->nmi_singlestep)
44c11430
GN		 1101 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1102
d0bfb940
JK		 1103 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1104 if (vcpu->guest_debug &
1105 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1106 svm->vmcb->control.intercept_exceptions |=
1107 1 << DB_VECTOR;
1108 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1109 svm->vmcb->control.intercept_exceptions |=
1110 1 << BP_VECTOR;
1111 } else
1112 vcpu->guest_debug = 0;
44c11430
GN		 1113}
1114
355be0b9 1115static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1116{
44c11430
GN		 1117 struct vcpu_svm *svm = to_svm(vcpu);
1118
ae675ef0
JK		 1119 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1120 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1121 else
1122 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1123
355be0b9 1124 update_db_intercept(vcpu);
6aa8b732
AK		 1125}
1126
1127static void load_host_msrs(struct kvm_vcpu *vcpu)
1128{
94dfbdb3 1129#ifdef CONFIG_X86_64
a2fa3e9f 1130 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1131#endif
6aa8b732
AK		 1132}
1133
1134static void save_host_msrs(struct kvm_vcpu *vcpu)
1135{
94dfbdb3 1136#ifdef CONFIG_X86_64
a2fa3e9f 1137 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1138#endif
6aa8b732
AK		 1139}
1140
0fe1e009 1141static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1142{
0fe1e009
TH		 1143 if (sd->next_asid > sd->max_asid) {
1144 ++sd->asid_generation;
1145 sd->next_asid = 1;
a2fa3e9f 1146 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1147 }
1148
0fe1e009
TH		 1149 svm->asid_generation = sd->asid_generation;
1150 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1151}
1152
c76de350 1153static int svm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *dest)
6aa8b732 1154{
42dbaa5a 1155 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a
JK		 1156
1157 switch (dr) {
1158 case 0 ... 3:
c76de350 1159 *dest = vcpu->arch.db[dr];
42dbaa5a 1160 break;
c76de350
JK		 1161 case 4:
1162 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1163 return EMULATE_FAIL; /* will re-inject UD */
1164 /* fall through */
42dbaa5a
JK		 1165 case 6:
1166 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1167 *dest = vcpu->arch.dr6;
42dbaa5a 1168 else
c76de350 1169 *dest = svm->vmcb->save.dr6;
42dbaa5a 1170 break;
c76de350
JK		 1171 case 5:
1172 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1173 return EMULATE_FAIL; /* will re-inject UD */
1174 /* fall through */
42dbaa5a
JK		 1175 case 7:
1176 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
c76de350 1177 *dest = vcpu->arch.dr7;
42dbaa5a 1178 else
c76de350 1179 *dest = svm->vmcb->save.dr7;
42dbaa5a 1180 break;
42dbaa5a
JK		 1181 }
1182
c76de350 1183 return EMULATE_DONE;
6aa8b732
AK		 1184}
1185
c76de350 1186static int svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value)
6aa8b732 1187{
a2fa3e9f
GH		 1188 struct vcpu_svm *svm = to_svm(vcpu);
1189
6aa8b732
AK		 1190 switch (dr) {
1191 case 0 ... 3:
42dbaa5a
JK		 1192 vcpu->arch.db[dr] = value;
1193 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1194 vcpu->arch.eff_db[dr] = value;
c76de350
JK		 1195 break;
1196 case 4:
1197 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1198 return EMULATE_FAIL; /* will re-inject UD */
1199 /* fall through */
42dbaa5a 1200 case 6:
42dbaa5a 1201 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
c76de350
JK		 1202 break;
1203 case 5:
1204 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
1205 return EMULATE_FAIL; /* will re-inject UD */
1206 /* fall through */
42dbaa5a 1207 case 7:
42dbaa5a
JK		 1208 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1209 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1210 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1211 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1212 }
c76de350 1213 break;
6aa8b732 1214 }
c76de350
JK		 1215
1216 return EMULATE_DONE;
6aa8b732
AK		 1217}
1218
851ba692 1219static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1220{
6aa8b732
AK		 1221 u64 fault_address;
1222 u32 error_code;
6aa8b732 1223
a2fa3e9f
GH		 1224 fault_address = svm->vmcb->control.exit_info_2;
1225 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1226
229456fc 1227 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1228 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1229 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1230 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1231}
1232
851ba692 1233static int db_interception(struct vcpu_svm *svm)
d0bfb940 1234{
851ba692
AK		 1235 struct kvm_run *kvm_run = svm->vcpu.run;
1236
d0bfb940 1237 if (!(svm->vcpu.guest_debug &
44c11430 1238 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1239 !svm->nmi_singlestep) {
d0bfb940
JK		 1240 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1241 return 1;
1242 }
44c11430 1243
6be7d306
JK		 1244 if (svm->nmi_singlestep) {
1245 svm->nmi_singlestep = false;
44c11430
GN		 1246 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1247 svm->vmcb->save.rflags &=
1248 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1249 update_db_intercept(&svm->vcpu);
1250 }
1251
1252 if (svm->vcpu.guest_debug &
1253 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1254 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1255 kvm_run->debug.arch.pc =
1256 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1257 kvm_run->debug.arch.exception = DB_VECTOR;
1258 return 0;
1259 }
1260
1261 return 1;
d0bfb940
JK		 1262}
1263
851ba692 1264static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1265{
851ba692
AK		 1266 struct kvm_run *kvm_run = svm->vcpu.run;
1267
d0bfb940
JK		 1268 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1269 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1270 kvm_run->debug.arch.exception = BP_VECTOR;
1271 return 0;
1272}
1273
851ba692 1274static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1275{
1276 int er;
1277
851ba692 1278 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1279 if (er != EMULATE_DONE)
7ee5d940 1280 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1281 return 1;
1282}
1283
6b52d186 1284static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1285{
6b52d186 1286 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1287 u32 excp;
1288
1289 if (is_nested(svm)) {
1290 u32 h_excp, n_excp;
1291
1292 h_excp = svm->nested.hsave->control.intercept_exceptions;
1293 n_excp = svm->nested.intercept_exceptions;
1294 h_excp &= ~(1 << NM_VECTOR);
1295 excp = h_excp | n_excp;
1296 } else {
1297 excp = svm->vmcb->control.intercept_exceptions;
1298 excp &= ~(1 << NM_VECTOR);
1299 }
1300
1301 svm->vmcb->control.intercept_exceptions = excp;
1302
e756fc62 1303 svm->vcpu.fpu_active = 1;
d225157b 1304 update_cr0_intercept(svm);
6b52d186 1305}
a2fa3e9f 1306
6b52d186
AK		 1307static int nm_interception(struct vcpu_svm *svm)
1308{
1309 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1310 return 1;
7807fa6c
AL		 1311}
1312
851ba692 1313static int mc_interception(struct vcpu_svm *svm)
53371b50
JR		 1314{
1315 /*
1316 * On an #MC intercept the MCE handler is not called automatically in
1317 * the host. So do it by hand here.
1318 */
1319 asm volatile (
1320 "int $0x12\n");
1321 /* not sure if we ever come back to this point */
1322
1323 return 1;
1324}
1325
851ba692 1326static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1327{
851ba692
AK		 1328 struct kvm_run *kvm_run = svm->vcpu.run;
1329
46fe4ddd
JR		 1330 /*
1331 * VMCB is undefined after a SHUTDOWN intercept
1332 * so reinitialize it.
1333 */
a2fa3e9f 1334 clear_page(svm->vmcb);
e6101a96 1335 init_vmcb(svm);
46fe4ddd
JR		 1336
1337 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1338 return 0;
1339}
1340
851ba692 1341static int io_interception(struct vcpu_svm *svm)
6aa8b732 1342{
d77c26fc 1343 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1344 int size, in, string;
039576c0 1345 unsigned port;
6aa8b732 1346
e756fc62 1347 ++svm->vcpu.stat.io_exits;
6aa8b732 1348
a2fa3e9f 1349 svm->next_rip = svm->vmcb->control.exit_info_2;
6aa8b732 1350
e70669ab
LV		 1351 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1352
1353 if (string) {
3427318f 1354 if (emulate_instruction(&svm->vcpu,
851ba692 1355 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1356 return 0;
1357 return 1;
1358 }
1359
039576c0
AK		 1360 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1361 port = io_info >> 16;
1362 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
6aa8b732 1363
e93f36bc 1364 skip_emulated_instruction(&svm->vcpu);
851ba692 1365 return kvm_emulate_pio(&svm->vcpu, in, size, port);
6aa8b732
AK		 1366}
1367
851ba692 1368static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1369{
1370 return 1;
1371}
1372
851ba692 1373static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1374{
1375 ++svm->vcpu.stat.irq_exits;
1376 return 1;
1377}
1378
851ba692 1379static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1380{
1381 return 1;
1382}
1383
851ba692 1384static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1385{
5fdbf976 1386 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1387 skip_emulated_instruction(&svm->vcpu);
1388 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1389}
1390
851ba692 1391static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1392{
5fdbf976 1393 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1394 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1395 kvm_emulate_hypercall(&svm->vcpu);
1396 return 1;
02e235bc
AK		 1397}
1398
c0725420
AG		 1399static int nested_svm_check_permissions(struct vcpu_svm *svm)
1400{
f6801dff 1401 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1402 || !is_paging(&svm->vcpu)) {
1403 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1404 return 1;
1405 }
1406
1407 if (svm->vmcb->save.cpl) {
1408 kvm_inject_gp(&svm->vcpu, 0);
1409 return 1;
1410 }
1411
1412 return 0;
1413}
1414
cf74a78b
AG		 1415static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1416 bool has_error_code, u32 error_code)
1417{
b8e88bc8
JR		 1418 int vmexit;
1419
0295ad7d
JR		 1420 if (!is_nested(svm))
1421 return 0;
cf74a78b 1422
0295ad7d
JR		 1423 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1424 svm->vmcb->control.exit_code_hi = 0;
1425 svm->vmcb->control.exit_info_1 = error_code;
1426 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1427
b8e88bc8
JR		 1428 vmexit = nested_svm_intercept(svm);
1429 if (vmexit == NESTED_EXIT_DONE)
1430 svm->nested.exit_required = true;
1431
1432 return vmexit;
cf74a78b
AG		 1433}
1434
8fe54654
JR		 1435/* This function returns true if it is save to enable the irq window */
1436static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1437{
26666957 1438 if (!is_nested(svm))
8fe54654 1439 return true;
cf74a78b 1440
26666957 1441 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1442 return true;
cf74a78b 1443
26666957 1444 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1445 return false;
cf74a78b 1446
26666957
JR		 1447 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1448
cd3ff653
JR		 1449 if (svm->nested.intercept & 1ULL) {
1450 /*
1451 * The #vmexit can't be emulated here directly because this
1452 * code path runs with irqs and preemtion disabled. A
1453 * #vmexit emulation might sleep. Only signal request for
1454 * the #vmexit here.
1455 */
1456 svm->nested.exit_required = true;
236649de 1457 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1458 return false;
cf74a78b
AG		 1459 }
1460
8fe54654 1461 return true;
cf74a78b
AG		 1462}
1463
7597f129 1464static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1465{
1466 struct page *page;
1467
6c3bd3d7
JR		 1468 might_sleep();
1469
34f80cfa 1470 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1471 if (is_error_page(page))
1472 goto error;
1473
7597f129
JR		 1474 *_page = page;
1475
1476 return kmap(page);
34f80cfa
JR		 1477
1478error:
1479 kvm_release_page_clean(page);
1480 kvm_inject_gp(&svm->vcpu, 0);
1481
1482 return NULL;
1483}
1484
7597f129 1485static void nested_svm_unmap(struct page *page)
34f80cfa 1486{
7597f129 1487 kunmap(page);
34f80cfa
JR		 1488 kvm_release_page_dirty(page);
1489}
1490
3d62d9aa 1491static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1492{
4c2161ae 1493 u32 param = svm->vmcb->control.exit_info_1 & 1;
3d62d9aa
JR		 1494 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1495 bool ret = false;
1496 u32 t0, t1;
4c7da8cb 1497 u8 val;
4c2161ae 1498
3d62d9aa
JR		 1499 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1500 return false;
1501
4c2161ae
JR		 1502 switch (msr) {
1503 case 0 ... 0x1fff:
1504 t0 = (msr * 2) % 8;
1505 t1 = msr / 8;
1506 break;
1507 case 0xc0000000 ... 0xc0001fff:
1508 t0 = (8192 + msr - 0xc0000000) * 2;
1509 t1 = (t0 / 8);
1510 t0 %= 8;
1511 break;
1512 case 0xc0010000 ... 0xc0011fff:
1513 t0 = (16384 + msr - 0xc0010000) * 2;
1514 t1 = (t0 / 8);
1515 t0 %= 8;
1516 break;
1517 default:
3d62d9aa
JR		 1518 ret = true;
1519 goto out;
4c2161ae 1520 }
4c2161ae 1521
4c7da8cb
JR		 1522 if (!kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + t1, &val, 1))
1523 ret = val & ((1 << param) << t0);
3d62d9aa
JR		 1524
1525out:
3d62d9aa 1526 return ret;
4c2161ae
JR		 1527}
1528
410e4d57 1529static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1530{
cf74a78b 1531 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1532
410e4d57
JR		 1533 switch (exit_code) {
1534 case SVM_EXIT_INTR:
1535 case SVM_EXIT_NMI:
1536 return NESTED_EXIT_HOST;
cf74a78b 1537 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1538 case SVM_EXIT_NPF:
1539 if (npt_enabled)
1540 return NESTED_EXIT_HOST;
1541 break;
1542 /* When we're shadowing, trap PFs */
1543 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1544 if (!npt_enabled)
1545 return NESTED_EXIT_HOST;
1546 break;
66a562f7
JR		 1547 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1548 nm_interception(svm);
1549 break;
410e4d57
JR		 1550 default:
1551 break;
cf74a78b
AG		 1552 }
1553
410e4d57
JR		 1554 return NESTED_EXIT_CONTINUE;
1555}
1556
1557/*
1558 * If this function returns true, this #vmexit was already handled
1559 */
b8e88bc8 1560static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1561{
1562 u32 exit_code = svm->vmcb->control.exit_code;
1563 int vmexit = NESTED_EXIT_HOST;
1564
cf74a78b 1565 switch (exit_code) {
9c4e40b9 1566 case SVM_EXIT_MSR:
3d62d9aa 1567 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1568 break;
cf74a78b
AG		 1569 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1570 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1571 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1572 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1573 break;
1574 }
1575 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1576 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1577 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1578 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1579 break;
1580 }
1581 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1582 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1583 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1584 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1585 break;
1586 }
1587 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1588 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1589 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1590 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1591 break;
1592 }
1593 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1594 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1595 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1596 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1597 break;
1598 }
1599 default: {
1600 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1601 if (svm->nested.intercept & exit_bits)
410e4d57 1602 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1603 }
1604 }
1605
b8e88bc8
JR		 1606 return vmexit;
1607}
1608
1609static int nested_svm_exit_handled(struct vcpu_svm *svm)
1610{
1611 int vmexit;
1612
1613 vmexit = nested_svm_intercept(svm);
1614
1615 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1616 nested_svm_vmexit(svm);
9c4e40b9
JR		 1617
1618 return vmexit;
cf74a78b
AG		 1619}
1620
0460a979
JR		 1621static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1622{
1623 struct vmcb_control_area *dst = &dst_vmcb->control;
1624 struct vmcb_control_area *from = &from_vmcb->control;
1625
1626 dst->intercept_cr_read = from->intercept_cr_read;
1627 dst->intercept_cr_write = from->intercept_cr_write;
1628 dst->intercept_dr_read = from->intercept_dr_read;
1629 dst->intercept_dr_write = from->intercept_dr_write;
1630 dst->intercept_exceptions = from->intercept_exceptions;
1631 dst->intercept = from->intercept;
1632 dst->iopm_base_pa = from->iopm_base_pa;
1633 dst->msrpm_base_pa = from->msrpm_base_pa;
1634 dst->tsc_offset = from->tsc_offset;
1635 dst->asid = from->asid;
1636 dst->tlb_ctl = from->tlb_ctl;
1637 dst->int_ctl = from->int_ctl;
1638 dst->int_vector = from->int_vector;
1639 dst->int_state = from->int_state;
1640 dst->exit_code = from->exit_code;
1641 dst->exit_code_hi = from->exit_code_hi;
1642 dst->exit_info_1 = from->exit_info_1;
1643 dst->exit_info_2 = from->exit_info_2;
1644 dst->exit_int_info = from->exit_int_info;
1645 dst->exit_int_info_err = from->exit_int_info_err;
1646 dst->nested_ctl = from->nested_ctl;
1647 dst->event_inj = from->event_inj;
1648 dst->event_inj_err = from->event_inj_err;
1649 dst->nested_cr3 = from->nested_cr3;
1650 dst->lbr_ctl = from->lbr_ctl;
1651}
1652
34f80cfa 1653static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1654{
34f80cfa 1655 struct vmcb *nested_vmcb;
e6aa9abd 1656 struct vmcb *hsave = svm->nested.hsave;
33740e40 1657 struct vmcb *vmcb = svm->vmcb;
7597f129 1658 struct page *page;
cf74a78b 1659
17897f36
JR		 1660 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1661 vmcb->control.exit_info_1,
1662 vmcb->control.exit_info_2,
1663 vmcb->control.exit_int_info,
1664 vmcb->control.exit_int_info_err);
1665
7597f129 1666 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1667 if (!nested_vmcb)
1668 return 1;
1669
06fc7772
JR		 1670 /* Exit nested SVM mode */
1671 svm->nested.vmcb = 0;
1672
cf74a78b 1673 /* Give the current vmcb to the guest */
33740e40
JR		 1674 disable_gif(svm);
1675
1676 nested_vmcb->save.es = vmcb->save.es;
1677 nested_vmcb->save.cs = vmcb->save.cs;
1678 nested_vmcb->save.ss = vmcb->save.ss;
1679 nested_vmcb->save.ds = vmcb->save.ds;
1680 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1681 nested_vmcb->save.idtr = vmcb->save.idtr;
cdbbdc12 1682 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
33740e40
JR		 1683 if (npt_enabled)
1684 nested_vmcb->save.cr3 = vmcb->save.cr3;
cdbbdc12
JR		 1685 else
1686 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1687 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1688 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1689 nested_vmcb->save.rflags = vmcb->save.rflags;
1690 nested_vmcb->save.rip = vmcb->save.rip;
1691 nested_vmcb->save.rsp = vmcb->save.rsp;
1692 nested_vmcb->save.rax = vmcb->save.rax;
1693 nested_vmcb->save.dr7 = vmcb->save.dr7;
1694 nested_vmcb->save.dr6 = vmcb->save.dr6;
1695 nested_vmcb->save.cpl = vmcb->save.cpl;
1696
1697 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1698 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1699 nested_vmcb->control.int_state = vmcb->control.int_state;
1700 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1701 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1702 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1703 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1704 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1705 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
8d23c466
AG		 1706
1707 /*
1708 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1709 * to make sure that we do not lose injected events. So check event_inj
1710 * here and copy it to exit_int_info if it is valid.
1711 * Exit_int_info and event_inj can't be both valid because the case
1712 * below only happens on a VMRUN instruction intercept which has
1713 * no valid exit_int_info set.
1714 */
1715 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1716 struct vmcb_control_area *nc = &nested_vmcb->control;
1717
1718 nc->exit_int_info = vmcb->control.event_inj;
1719 nc->exit_int_info_err = vmcb->control.event_inj_err;
1720 }
1721
33740e40
JR		 1722 nested_vmcb->control.tlb_ctl = 0;
1723 nested_vmcb->control.event_inj = 0;
1724 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1725
1726 /* We always set V_INTR_MASKING and remember the old value in hflags */
1727 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1728 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1729
cf74a78b 1730 /* Restore the original control entries */
0460a979 1731 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1732
219b65dc
AG		 1733 kvm_clear_exception_queue(&svm->vcpu);
1734 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1735
1736 /* Restore selected save entries */
1737 svm->vmcb->save.es = hsave->save.es;
1738 svm->vmcb->save.cs = hsave->save.cs;
1739 svm->vmcb->save.ss = hsave->save.ss;
1740 svm->vmcb->save.ds = hsave->save.ds;
1741 svm->vmcb->save.gdtr = hsave->save.gdtr;
1742 svm->vmcb->save.idtr = hsave->save.idtr;
1743 svm->vmcb->save.rflags = hsave->save.rflags;
1744 svm_set_efer(&svm->vcpu, hsave->save.efer);
1745 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1746 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1747 if (npt_enabled) {
1748 svm->vmcb->save.cr3 = hsave->save.cr3;
1749 svm->vcpu.arch.cr3 = hsave->save.cr3;
1750 } else {
1751 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1752 }
1753 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1754 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1755 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1756 svm->vmcb->save.dr7 = 0;
1757 svm->vmcb->save.cpl = 0;
1758 svm->vmcb->control.exit_int_info = 0;
1759
7597f129 1760 nested_svm_unmap(page);
cf74a78b
AG		 1761
1762 kvm_mmu_reset_context(&svm->vcpu);
1763 kvm_mmu_load(&svm->vcpu);
1764
1765 return 0;
1766}
3d6368ef 1767
9738b2c9 1768static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1769{
9738b2c9 1770 u32 *nested_msrpm;
7597f129 1771 struct page *page;
3d6368ef 1772 int i;
9738b2c9 1773
7597f129 1774 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, &page);
9738b2c9
JR		 1775 if (!nested_msrpm)
1776 return false;
1777
3d6368ef 1778 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
e6aa9abd 1779 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
9738b2c9 1780
e6aa9abd 1781 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
3d6368ef 1782
7597f129 1783 nested_svm_unmap(page);
9738b2c9
JR		 1784
1785 return true;
3d6368ef
AG		 1786}
1787
9738b2c9 1788static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 1789{
9738b2c9 1790 struct vmcb *nested_vmcb;
e6aa9abd 1791 struct vmcb *hsave = svm->nested.hsave;
defbba56 1792 struct vmcb *vmcb = svm->vmcb;
7597f129 1793 struct page *page;
06fc7772
JR		 1794 u64 vmcb_gpa;
1795
1796 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 1797
7597f129 1798 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 1799 if (!nested_vmcb)
1800 return false;
1801
0ac406de
JR		 1802 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1803 nested_vmcb->save.rip,
1804 nested_vmcb->control.int_ctl,
1805 nested_vmcb->control.event_inj,
1806 nested_vmcb->control.nested_ctl);
1807
3d6368ef 1808 /* Clear internal status */
219b65dc
AG		 1809 kvm_clear_exception_queue(&svm->vcpu);
1810 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef
AG		 1811
1812 /* Save the old vmcb, so we don't need to pick what we save, but
1813 can restore everything when a VMEXIT occurs */
defbba56
JR		 1814 hsave->save.es = vmcb->save.es;
1815 hsave->save.cs = vmcb->save.cs;
1816 hsave->save.ss = vmcb->save.ss;
1817 hsave->save.ds = vmcb->save.ds;
1818 hsave->save.gdtr = vmcb->save.gdtr;
1819 hsave->save.idtr = vmcb->save.idtr;
f6801dff 1820 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 1821 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 1822 hsave->save.cr4 = svm->vcpu.arch.cr4;
1823 hsave->save.rflags = vmcb->save.rflags;
1824 hsave->save.rip = svm->next_rip;
1825 hsave->save.rsp = vmcb->save.rsp;
1826 hsave->save.rax = vmcb->save.rax;
1827 if (npt_enabled)
1828 hsave->save.cr3 = vmcb->save.cr3;
1829 else
1830 hsave->save.cr3 = svm->vcpu.arch.cr3;
1831
0460a979 1832 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 1833
1834 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1835 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1836 else
1837 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1838
1839 /* Load the nested guest state */
1840 svm->vmcb->save.es = nested_vmcb->save.es;
1841 svm->vmcb->save.cs = nested_vmcb->save.cs;
1842 svm->vmcb->save.ss = nested_vmcb->save.ss;
1843 svm->vmcb->save.ds = nested_vmcb->save.ds;
1844 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1845 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1846 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1847 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1848 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1849 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1850 if (npt_enabled) {
1851 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1852 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1853 } else {
1854 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1855 kvm_mmu_reset_context(&svm->vcpu);
1856 }
defbba56 1857 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 1858 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1859 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1860 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1861 /* In case we don't even reach vcpu_run, the fields are not updated */
1862 svm->vmcb->save.rax = nested_vmcb->save.rax;
1863 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1864 svm->vmcb->save.rip = nested_vmcb->save.rip;
1865 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1866 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1867 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1868
e6aa9abd 1869 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
3d6368ef 1870
aad42c64
JR		 1871 /* cache intercepts */
1872 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1873 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1874 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1875 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1876 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1877 svm->nested.intercept = nested_vmcb->control.intercept;
1878
3d6368ef 1879 force_new_asid(&svm->vcpu);
3d6368ef 1880 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 1881 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1882 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1883 else
1884 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1885
88ab24ad
JR		 1886 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
1887 /* We only want the cr8 intercept bits of the guest */
1888 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
1889 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1890 }
1891
1892 /* We don't want a nested guest to be more powerful than the guest,
1893 so all intercepts are ORed */
1894 svm->vmcb->control.intercept_cr_read |=
1895 nested_vmcb->control.intercept_cr_read;
1896 svm->vmcb->control.intercept_cr_write |=
1897 nested_vmcb->control.intercept_cr_write;
1898 svm->vmcb->control.intercept_dr_read |=
1899 nested_vmcb->control.intercept_dr_read;
1900 svm->vmcb->control.intercept_dr_write |=
1901 nested_vmcb->control.intercept_dr_write;
1902 svm->vmcb->control.intercept_exceptions |=
1903 nested_vmcb->control.intercept_exceptions;
1904
1905 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1906
1907 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 1908 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1909 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1910 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 1911 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1912 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1913
7597f129 1914 nested_svm_unmap(page);
9738b2c9 1915
06fc7772
JR		 1916 /* nested_vmcb is our indicator if nested SVM is activated */
1917 svm->nested.vmcb = vmcb_gpa;
1918
2af9194d 1919 enable_gif(svm);
3d6368ef 1920
9738b2c9 1921 return true;
3d6368ef
AG		 1922}
1923
9966bf68 1924static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 1925{
1926 to_vmcb->save.fs = from_vmcb->save.fs;
1927 to_vmcb->save.gs = from_vmcb->save.gs;
1928 to_vmcb->save.tr = from_vmcb->save.tr;
1929 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1930 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1931 to_vmcb->save.star = from_vmcb->save.star;
1932 to_vmcb->save.lstar = from_vmcb->save.lstar;
1933 to_vmcb->save.cstar = from_vmcb->save.cstar;
1934 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1935 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1936 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1937 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 1938}
1939
851ba692 1940static int vmload_interception(struct vcpu_svm *svm)
5542675b 1941{
9966bf68 1942 struct vmcb *nested_vmcb;
7597f129 1943 struct page *page;
9966bf68 1944
5542675b
AG		 1945 if (nested_svm_check_permissions(svm))
1946 return 1;
1947
1948 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1949 skip_emulated_instruction(&svm->vcpu);
1950
7597f129 1951 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1952 if (!nested_vmcb)
1953 return 1;
1954
1955 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 1956 nested_svm_unmap(page);
5542675b
AG		 1957
1958 return 1;
1959}
1960
851ba692 1961static int vmsave_interception(struct vcpu_svm *svm)
5542675b 1962{
9966bf68 1963 struct vmcb *nested_vmcb;
7597f129 1964 struct page *page;
9966bf68 1965
5542675b
AG		 1966 if (nested_svm_check_permissions(svm))
1967 return 1;
1968
1969 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1970 skip_emulated_instruction(&svm->vcpu);
1971
7597f129 1972 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 1973 if (!nested_vmcb)
1974 return 1;
1975
1976 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 1977 nested_svm_unmap(page);
5542675b
AG		 1978
1979 return 1;
1980}
1981
851ba692 1982static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 1983{
3d6368ef
AG		 1984 if (nested_svm_check_permissions(svm))
1985 return 1;
1986
1987 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1988 skip_emulated_instruction(&svm->vcpu);
1989
9738b2c9 1990 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 1991 return 1;
1992
9738b2c9 1993 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 1994 goto failed;
1995
1996 return 1;
1997
1998failed:
1999
2000 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2001 svm->vmcb->control.exit_code_hi = 0;
2002 svm->vmcb->control.exit_info_1 = 0;
2003 svm->vmcb->control.exit_info_2 = 0;
2004
2005 nested_svm_vmexit(svm);
3d6368ef
AG		 2006
2007 return 1;
2008}
2009
851ba692 2010static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2011{
2012 if (nested_svm_check_permissions(svm))
2013 return 1;
2014
2015 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2016 skip_emulated_instruction(&svm->vcpu);
2017
2af9194d 2018 enable_gif(svm);
1371d904
AG		 2019
2020 return 1;
2021}
2022
851ba692 2023static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2024{
2025 if (nested_svm_check_permissions(svm))
2026 return 1;
2027
2028 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2029 skip_emulated_instruction(&svm->vcpu);
2030
2af9194d 2031 disable_gif(svm);
1371d904
AG		 2032
2033 /* After a CLGI no interrupts should come */
2034 svm_clear_vintr(svm);
2035 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2036
2037 return 1;
2038}
2039
851ba692 2040static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2041{
2042 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2043
ec1ff790
JR		 2044 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2045 vcpu->arch.regs[VCPU_REGS_RAX]);
2046
ff092385
AG		 2047 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2048 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2049
2050 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2051 skip_emulated_instruction(&svm->vcpu);
2052 return 1;
2053}
2054
532a46b9
JR		 2055static int skinit_interception(struct vcpu_svm *svm)
2056{
2057 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2058
2059 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2060 return 1;
2061}
2062
851ba692 2063static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2064{
7ee5d940 2065 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2066 return 1;
2067}
2068
851ba692 2069static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2070{
37817f29 2071 u16 tss_selector;
64a7ec06
GN		 2072 int reason;
2073 int int_type = svm->vmcb->control.exit_int_info &
2074 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2075 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2076 uint32_t type =
2077 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2078 uint32_t idt_v =
2079 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
37817f29
IE		 2080
2081 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2082
37817f29
IE		 2083 if (svm->vmcb->control.exit_info_2 &
2084 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2085 reason = TASK_SWITCH_IRET;
2086 else if (svm->vmcb->control.exit_info_2 &
2087 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2088 reason = TASK_SWITCH_JMP;
fe8e7f83 2089 else if (idt_v)
64a7ec06
GN		 2090 reason = TASK_SWITCH_GATE;
2091 else
2092 reason = TASK_SWITCH_CALL;
2093
fe8e7f83
GN		 2094 if (reason == TASK_SWITCH_GATE) {
2095 switch (type) {
2096 case SVM_EXITINTINFO_TYPE_NMI:
2097 svm->vcpu.arch.nmi_injected = false;
2098 break;
2099 case SVM_EXITINTINFO_TYPE_EXEPT:
2100 kvm_clear_exception_queue(&svm->vcpu);
2101 break;
2102 case SVM_EXITINTINFO_TYPE_INTR:
2103 kvm_clear_interrupt_queue(&svm->vcpu);
2104 break;
2105 default:
2106 break;
2107 }
2108 }
64a7ec06 2109
8317c298
GN		 2110 if (reason != TASK_SWITCH_GATE ||
2111 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2112 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2113 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2114 skip_emulated_instruction(&svm->vcpu);
64a7ec06
GN		 2115
2116 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
6aa8b732
AK		 2117}
2118
851ba692 2119static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2120{
5fdbf976 2121 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2122 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2123 return 1;
6aa8b732
AK		 2124}
2125
851ba692 2126static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2127{
2128 ++svm->vcpu.stat.nmi_window_exits;
2129 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
44c11430 2130 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2131 return 1;
2132}
2133
851ba692 2134static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2135{
851ba692 2136 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
a7052897
MT		 2137 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2138 return 1;
2139}
2140
851ba692 2141static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2142{
851ba692 2143 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
b8688d51 2144 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
6aa8b732
AK		 2145 return 1;
2146}
2147
851ba692 2148static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2149{
851ba692
AK		 2150 struct kvm_run *kvm_run = svm->vcpu.run;
2151
0a5fff19
GN		 2152 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2153 /* instruction emulation calls kvm_set_cr8() */
851ba692 2154 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2155 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2156 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2157 return 1;
95ba8273 2158 }
0a5fff19
GN		 2159 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2160 return 1;
1d075434
JR		 2161 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2162 return 0;
2163}
2164
6aa8b732
AK		 2165static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2166{
a2fa3e9f
GH		 2167 struct vcpu_svm *svm = to_svm(vcpu);
2168
6aa8b732 2169 switch (ecx) {
af24a4e4 2170 case MSR_IA32_TSC: {
20824f30 2171 u64 tsc_offset;
6aa8b732 2172
20824f30
JR		 2173 if (is_nested(svm))
2174 tsc_offset = svm->nested.hsave->control.tsc_offset;
2175 else
2176 tsc_offset = svm->vmcb->control.tsc_offset;
2177
2178 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2179 break;
2180 }
0e859cac 2181 case MSR_K6_STAR:
a2fa3e9f 2182 *data = svm->vmcb->save.star;
6aa8b732 2183 break;
0e859cac 2184#ifdef CONFIG_X86_64
6aa8b732 2185 case MSR_LSTAR:
a2fa3e9f 2186 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2187 break;
2188 case MSR_CSTAR:
a2fa3e9f 2189 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2190 break;
2191 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2192 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2193 break;
2194 case MSR_SYSCALL_MASK:
a2fa3e9f 2195 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2196 break;
2197#endif
2198 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2199 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2200 break;
2201 case MSR_IA32_SYSENTER_EIP:
017cb99e 2202 *data = svm->sysenter_eip;
6aa8b732
AK		 2203 break;
2204 case MSR_IA32_SYSENTER_ESP:
017cb99e 2205 *data = svm->sysenter_esp;
6aa8b732 2206 break;
a2938c80
JR		 2207 /* Nobody will change the following 5 values in the VMCB so
2208 we can safely return them on rdmsr. They will always be 0
2209 until LBRV is implemented. */
2210 case MSR_IA32_DEBUGCTLMSR:
2211 *data = svm->vmcb->save.dbgctl;
2212 break;
2213 case MSR_IA32_LASTBRANCHFROMIP:
2214 *data = svm->vmcb->save.br_from;
2215 break;
2216 case MSR_IA32_LASTBRANCHTOIP:
2217 *data = svm->vmcb->save.br_to;
2218 break;
2219 case MSR_IA32_LASTINTFROMIP:
2220 *data = svm->vmcb->save.last_excp_from;
2221 break;
2222 case MSR_IA32_LASTINTTOIP:
2223 *data = svm->vmcb->save.last_excp_to;
2224 break;
b286d5d8 2225 case MSR_VM_HSAVE_PA:
e6aa9abd 2226 *data = svm->nested.hsave_msr;
b286d5d8 2227 break;
eb6f302e
JR		 2228 case MSR_VM_CR:
2229 *data = 0;
2230 break;
c8a73f18
AG		 2231 case MSR_IA32_UCODE_REV:
2232 *data = 0x01000065;
2233 break;
6aa8b732 2234 default:
3bab1f5d 2235 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2236 }
2237 return 0;
2238}
2239
851ba692 2240static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2241{
ad312c7c 2242 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2243 u64 data;
2244
59200273
AK		 2245 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2246 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2247 kvm_inject_gp(&svm->vcpu, 0);
59200273 2248 } else {
229456fc 2249 trace_kvm_msr_read(ecx, data);
af9ca2d7 2250
5fdbf976 2251 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2252 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2253 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2254 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2255 }
2256 return 1;
2257}
2258
2259static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2260{
a2fa3e9f
GH		 2261 struct vcpu_svm *svm = to_svm(vcpu);
2262
6aa8b732 2263 switch (ecx) {
af24a4e4 2264 case MSR_IA32_TSC: {
20824f30
JR		 2265 u64 tsc_offset = data - native_read_tsc();
2266 u64 g_tsc_offset = 0;
2267
2268 if (is_nested(svm)) {
2269 g_tsc_offset = svm->vmcb->control.tsc_offset -
2270 svm->nested.hsave->control.tsc_offset;
2271 svm->nested.hsave->control.tsc_offset = tsc_offset;
2272 }
2273
2274 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2275
6aa8b732
AK		 2276 break;
2277 }
0e859cac 2278 case MSR_K6_STAR:
a2fa3e9f 2279 svm->vmcb->save.star = data;
6aa8b732 2280 break;
49b14f24 2281#ifdef CONFIG_X86_64
6aa8b732 2282 case MSR_LSTAR:
a2fa3e9f 2283 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2284 break;
2285 case MSR_CSTAR:
a2fa3e9f 2286 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2287 break;
2288 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2289 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2290 break;
2291 case MSR_SYSCALL_MASK:
a2fa3e9f 2292 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2293 break;
2294#endif
2295 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2296 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2297 break;
2298 case MSR_IA32_SYSENTER_EIP:
017cb99e 2299 svm->sysenter_eip = data;
a2fa3e9f 2300 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2301 break;
2302 case MSR_IA32_SYSENTER_ESP:
017cb99e 2303 svm->sysenter_esp = data;
a2fa3e9f 2304 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2305 break;
a2938c80 2306 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2307 if (!svm_has(SVM_FEATURE_LBRV)) {
2308 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2309 __func__, data);
24e09cbf
JR		 2310 break;
2311 }
2312 if (data & DEBUGCTL_RESERVED_BITS)
2313 return 1;
2314
2315 svm->vmcb->save.dbgctl = data;
2316 if (data & (1ULL<<0))
2317 svm_enable_lbrv(svm);
2318 else
2319 svm_disable_lbrv(svm);
a2938c80 2320 break;
b286d5d8 2321 case MSR_VM_HSAVE_PA:
e6aa9abd 2322 svm->nested.hsave_msr = data;
62b9abaa 2323 break;
3c5d0a44
AG		 2324 case MSR_VM_CR:
2325 case MSR_VM_IGNNE:
3c5d0a44
AG		 2326 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2327 break;
6aa8b732 2328 default:
3bab1f5d 2329 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2330 }
2331 return 0;
2332}
2333
851ba692 2334static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2335{
ad312c7c 2336 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2337 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2338 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2339
af9ca2d7 2340
5fdbf976 2341 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2342 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2343 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2344 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2345 } else {
2346 trace_kvm_msr_write(ecx, data);
e756fc62 2347 skip_emulated_instruction(&svm->vcpu);
59200273 2348 }
6aa8b732
AK		 2349 return 1;
2350}
2351
851ba692 2352static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2353{
e756fc62 2354 if (svm->vmcb->control.exit_info_1)
851ba692 2355 return wrmsr_interception(svm);
6aa8b732 2356 else
851ba692 2357 return rdmsr_interception(svm);
6aa8b732
AK		 2358}
2359
851ba692 2360static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2361{
851ba692
AK		 2362 struct kvm_run *kvm_run = svm->vcpu.run;
2363
f0b85051 2364 svm_clear_vintr(svm);
85f455f7 2365 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2366 /*
2367 * If the user space waits to inject interrupts, exit as soon as
2368 * possible
2369 */
8061823a
GN		 2370 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2371 kvm_run->request_interrupt_window &&
2372 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2373 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2374 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2375 return 0;
2376 }
2377
2378 return 1;
2379}
2380
565d0998
ML		 2381static int pause_interception(struct vcpu_svm *svm)
2382{
2383 kvm_vcpu_on_spin(&(svm->vcpu));
2384 return 1;
2385}
2386
851ba692 2387static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
6aa8b732
AK		 2388 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2389 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2390 [SVM_EXIT_READ_CR4] = emulate_on_interception,
80a8119c 2391 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2392 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
6aa8b732
AK		 2393 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2394 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2395 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1d075434 2396 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
6aa8b732
AK		 2397 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2398 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2399 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2400 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2401 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2402 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2403 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2404 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2405 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2406 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2407 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2408 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2409 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2410 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2411 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2412 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2413 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2414 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2415 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
6aa8b732 2416 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 2417 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
53371b50 2418 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
a0698055 2419 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2420 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2421 [SVM_EXIT_SMI] = nop_on_interception,
2422 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2423 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 2424 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2425 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2426 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2427 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2428 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2429 [SVM_EXIT_HLT] = halt_interception,
a7052897 2430 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2431 [SVM_EXIT_INVLPGA] = invlpga_interception,
6aa8b732
AK		 2432 [SVM_EXIT_IOIO] = io_interception,
2433 [SVM_EXIT_MSR] = msr_interception,
2434 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2435 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2436 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2437 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2438 [SVM_EXIT_VMLOAD] = vmload_interception,
2439 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2440 [SVM_EXIT_STGI] = stgi_interception,
2441 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2442 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2443 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2444 [SVM_EXIT_MONITOR] = invalid_op_interception,
2445 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2446 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2447};
2448
851ba692 2449static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2450{
04d2cc77 2451 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2452 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2453 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2454
229456fc 2455 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
af9ca2d7 2456
cd3ff653
JR		 2457 if (unlikely(svm->nested.exit_required)) {
2458 nested_svm_vmexit(svm);
2459 svm->nested.exit_required = false;
2460
2461 return 1;
2462 }
2463
cf74a78b 2464 if (is_nested(svm)) {
410e4d57
JR		 2465 int vmexit;
2466
d8cabddf
JR		 2467 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2468 svm->vmcb->control.exit_info_1,
2469 svm->vmcb->control.exit_info_2,
2470 svm->vmcb->control.exit_int_info,
2471 svm->vmcb->control.exit_int_info_err);
2472
410e4d57
JR		 2473 vmexit = nested_svm_exit_special(svm);
2474
2475 if (vmexit == NESTED_EXIT_CONTINUE)
2476 vmexit = nested_svm_exit_handled(svm);
2477
2478 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2479 return 1;
cf74a78b
AG		 2480 }
2481
a5c3832d
JR		 2482 svm_complete_interrupts(svm);
2483
888f9f3e 2484 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
709ddebf 2485 vcpu->arch.cr0 = svm->vmcb->save.cr0;
888f9f3e 2486 if (npt_enabled)
709ddebf 2487 vcpu->arch.cr3 = svm->vmcb->save.cr3;
04d2cc77
AK		 2488
2489 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2490 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2491 kvm_run->fail_entry.hardware_entry_failure_reason
2492 = svm->vmcb->control.exit_code;
2493 return 0;
2494 }
2495
a2fa3e9f 2496 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2497 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2498 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2499 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2500 "exit_code 0x%x\n",
b8688d51 2501 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2502 exit_code);
2503
9d8f549d 2504 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2505 || !svm_exit_handlers[exit_code]) {
6aa8b732 2506 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2507 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2508 return 0;
2509 }
2510
851ba692 2511 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2512}
2513
2514static void reload_tss(struct kvm_vcpu *vcpu)
2515{
2516 int cpu = raw_smp_processor_id();
2517
0fe1e009
TH		 2518 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2519 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2520 load_TR_desc();
2521}
2522
e756fc62 2523static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2524{
2525 int cpu = raw_smp_processor_id();
2526
0fe1e009 2527 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2528
a2fa3e9f 2529 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2530 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2531 if (svm->asid_generation != sd->asid_generation)
2532 new_asid(svm, sd);
6aa8b732
AK		 2533}
2534
95ba8273
GN		 2535static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2536{
2537 struct vcpu_svm *svm = to_svm(vcpu);
2538
2539 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2540 vcpu->arch.hflags |= HF_NMI_MASK;
2541 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2542 ++vcpu->stat.nmi_injections;
2543}
6aa8b732 2544
85f455f7 2545static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2546{
2547 struct vmcb_control_area *control;
2548
229456fc 2549 trace_kvm_inj_virq(irq);
af9ca2d7 2550
fa89a817 2551 ++svm->vcpu.stat.irq_injections;
e756fc62 2552 control = &svm->vmcb->control;
85f455f7 2553 control->int_vector = irq;
6aa8b732
AK		 2554 control->int_ctl &= ~V_INTR_PRIO_MASK;
2555 control->int_ctl |= V_IRQ_MASK |
2556 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2557}
2558
66fd3f7f 2559static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2560{
2561 struct vcpu_svm *svm = to_svm(vcpu);
2562
2af9194d 2563 BUG_ON(!(gif_set(svm)));
cf74a78b 2564
219b65dc
AG		 2565 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2566 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2567}
2568
95ba8273 2569static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2570{
2571 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2572
88ab24ad
JR		 2573 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2574 return;
2575
95ba8273 2576 if (irr == -1)
aaacfc9a
JR		 2577 return;
2578
95ba8273
GN		 2579 if (tpr >= irr)
2580 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2581}
aaacfc9a 2582
95ba8273
GN		 2583static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2584{
2585 struct vcpu_svm *svm = to_svm(vcpu);
2586 struct vmcb *vmcb = svm->vmcb;
2587 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2588 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
aaacfc9a
JR		 2589}
2590
3cfc3092
JK		 2591static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2592{
2593 struct vcpu_svm *svm = to_svm(vcpu);
2594
2595 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2596}
2597
2598static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2599{
2600 struct vcpu_svm *svm = to_svm(vcpu);
2601
2602 if (masked) {
2603 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2604 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2605 } else {
2606 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2607 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2608 }
2609}
2610
78646121
GN		 2611static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2612{
2613 struct vcpu_svm *svm = to_svm(vcpu);
2614 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 2615 int ret;
2616
2617 if (!gif_set(svm) ||
2618 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2619 return 0;
2620
2621 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2622
2623 if (is_nested(svm))
2624 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2625
2626 return ret;
78646121
GN		 2627}
2628
9222be18 2629static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 2630{
219b65dc 2631 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 2632
219b65dc
AG		 2633 /* In case GIF=0 we can't rely on the CPU to tell us when
2634 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2635 * The next time we get that intercept, this function will be
2636 * called again though and we'll get the vintr intercept. */
8fe54654 2637 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 2638 svm_set_vintr(svm);
2639 svm_inject_irq(svm, 0x0);
2640 }
85f455f7
ED		 2641}
2642
95ba8273 2643static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 2644{
04d2cc77 2645 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 2646
44c11430
GN		 2647 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2648 == HF_NMI_MASK)
2649 return; /* IRET will cause a vm exit */
2650
2651 /* Something prevents NMI from been injected. Single step over
2652 possible problem (IRET or exception injection or interrupt
2653 shadow) */
6be7d306 2654 svm->nmi_singlestep = true;
44c11430
GN		 2655 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2656 update_db_intercept(vcpu);
c1150d8c
DL		 2657}
2658
cbc94022
IE		 2659static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2660{
2661 return 0;
2662}
2663
d9e368d6
AK		 2664static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2665{
2666 force_new_asid(vcpu);
2667}
2668
04d2cc77
AK		 2669static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2670{
2671}
2672
d7bf8221
JR		 2673static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2674{
2675 struct vcpu_svm *svm = to_svm(vcpu);
2676
88ab24ad
JR		 2677 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2678 return;
2679
d7bf8221
JR		 2680 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2681 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 2682 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 2683 }
2684}
2685
649d6864
JR		 2686static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2687{
2688 struct vcpu_svm *svm = to_svm(vcpu);
2689 u64 cr8;
2690
88ab24ad
JR		 2691 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2692 return;
2693
649d6864
JR		 2694 cr8 = kvm_get_cr8(vcpu);
2695 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2696 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2697}
2698
9222be18
GN		 2699static void svm_complete_interrupts(struct vcpu_svm *svm)
2700{
2701 u8 vector;
2702 int type;
2703 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2704
44c11430
GN		 2705 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2706 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2707
9222be18
GN		 2708 svm->vcpu.arch.nmi_injected = false;
2709 kvm_clear_exception_queue(&svm->vcpu);
2710 kvm_clear_interrupt_queue(&svm->vcpu);
2711
2712 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2713 return;
2714
2715 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2716 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2717
2718 switch (type) {
2719 case SVM_EXITINTINFO_TYPE_NMI:
2720 svm->vcpu.arch.nmi_injected = true;
2721 break;
2722 case SVM_EXITINTINFO_TYPE_EXEPT:
2723 /* In case of software exception do not reinject an exception
2724 vector, but re-execute and instruction instead */
219b65dc
AG		 2725 if (is_nested(svm))
2726 break;
66fd3f7f 2727 if (kvm_exception_is_soft(vector))
9222be18
GN		 2728 break;
2729 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2730 u32 err = svm->vmcb->control.exit_int_info_err;
2731 kvm_queue_exception_e(&svm->vcpu, vector, err);
2732
2733 } else
2734 kvm_queue_exception(&svm->vcpu, vector);
2735 break;
2736 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 2737 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 2738 break;
2739 default:
2740 break;
2741 }
2742}
2743
80e31d4f
AK		 2744#ifdef CONFIG_X86_64
2745#define R "r"
2746#else
2747#define R "e"
2748#endif
2749
851ba692 2750static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 2751{
a2fa3e9f 2752 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 2753 u16 fs_selector;
2754 u16 gs_selector;
2755 u16 ldt_selector;
d9e368d6 2756
cd3ff653
JR		 2757 /*
2758 * A vmexit emulation is required before the vcpu can be executed
2759 * again.
2760 */
2761 if (unlikely(svm->nested.exit_required))
2762 return;
2763
5fdbf976
MT		 2764 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2765 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2766 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2767
e756fc62 2768 pre_svm_run(svm);
6aa8b732 2769
649d6864
JR		 2770 sync_lapic_to_cr8(vcpu);
2771
6aa8b732 2772 save_host_msrs(vcpu);
d6e88aec
AK		 2773 fs_selector = kvm_read_fs();
2774 gs_selector = kvm_read_gs();
2775 ldt_selector = kvm_read_ldt();
cda0ffdd 2776 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 2777 /* required for live migration with NPT */
2778 if (npt_enabled)
2779 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 2780
04d2cc77
AK		 2781 clgi();
2782
2783 local_irq_enable();
36241b8c 2784
6aa8b732 2785 asm volatile (
80e31d4f
AK		 2786 "push %%"R"bp; \n\t"
2787 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2788 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2789 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2790 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2791 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2792 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 2793#ifdef CONFIG_X86_64
fb3f0f51
RR		 2794 "mov %c[r8](%[svm]), %%r8 \n\t"
2795 "mov %c[r9](%[svm]), %%r9 \n\t"
2796 "mov %c[r10](%[svm]), %%r10 \n\t"
2797 "mov %c[r11](%[svm]), %%r11 \n\t"
2798 "mov %c[r12](%[svm]), %%r12 \n\t"
2799 "mov %c[r13](%[svm]), %%r13 \n\t"
2800 "mov %c[r14](%[svm]), %%r14 \n\t"
2801 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 2802#endif
2803
6aa8b732 2804 /* Enter guest mode */
80e31d4f
AK		 2805 "push %%"R"ax \n\t"
2806 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 2807 __ex(SVM_VMLOAD) "\n\t"
2808 __ex(SVM_VMRUN) "\n\t"
2809 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 2810 "pop %%"R"ax \n\t"
6aa8b732
AK		 2811
2812 /* Save guest registers, load host registers */
80e31d4f
AK		 2813 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2814 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2815 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2816 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2817 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2818 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 2819#ifdef CONFIG_X86_64
fb3f0f51
RR		 2820 "mov %%r8, %c[r8](%[svm]) \n\t"
2821 "mov %%r9, %c[r9](%[svm]) \n\t"
2822 "mov %%r10, %c[r10](%[svm]) \n\t"
2823 "mov %%r11, %c[r11](%[svm]) \n\t"
2824 "mov %%r12, %c[r12](%[svm]) \n\t"
2825 "mov %%r13, %c[r13](%[svm]) \n\t"
2826 "mov %%r14, %c[r14](%[svm]) \n\t"
2827 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 2828#endif
80e31d4f 2829 "pop %%"R"bp"
6aa8b732 2830 :
fb3f0f51 2831 : [svm]"a"(svm),
6aa8b732 2832 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 2833 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2834 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2835 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2836 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2837 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2838 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 2839#ifdef CONFIG_X86_64
ad312c7c
ZX		 2840 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2841 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2842 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2843 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2844 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2845 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2846 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2847 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 2848#endif
54a08c04 2849 : "cc", "memory"
80e31d4f 2850 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 2851#ifdef CONFIG_X86_64
54a08c04
LV		 2852 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2853#endif
2854 );
6aa8b732 2855
ad312c7c 2856 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 2857 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2858 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2859 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 2860
d6e88aec
AK		 2861 kvm_load_fs(fs_selector);
2862 kvm_load_gs(gs_selector);
2863 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 2864 load_host_msrs(vcpu);
2865
2866 reload_tss(vcpu);
2867
56ba47dd
AK		 2868 local_irq_disable();
2869
2870 stgi();
2871
d7bf8221
JR		 2872 sync_cr8_to_lapic(vcpu);
2873
a2fa3e9f 2874 svm->next_rip = 0;
9222be18 2875
6de4f3ad
AK		 2876 if (npt_enabled) {
2877 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2878 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2879 }
6aa8b732
AK		 2880}
2881
80e31d4f
AK		 2882#undef R
2883
6aa8b732
AK		 2884static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2885{
a2fa3e9f
GH		 2886 struct vcpu_svm *svm = to_svm(vcpu);
2887
709ddebf
JR		 2888 if (npt_enabled) {
2889 svm->vmcb->control.nested_cr3 = root;
2890 force_new_asid(vcpu);
2891 return;
2892 }
2893
a2fa3e9f 2894 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 2895 force_new_asid(vcpu);
2896}
2897
6aa8b732
AK		 2898static int is_disabled(void)
2899{
6031a61c
JR		 2900 u64 vm_cr;
2901
2902 rdmsrl(MSR_VM_CR, vm_cr);
2903 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2904 return 1;
2905
6aa8b732
AK		 2906 return 0;
2907}
2908
102d8325
IM		 2909static void
2910svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2911{
2912 /*
2913 * Patch in the VMMCALL instruction:
2914 */
2915 hypercall[0] = 0x0f;
2916 hypercall[1] = 0x01;
2917 hypercall[2] = 0xd9;
102d8325
IM		 2918}
2919
002c7f7c
YS		 2920static void svm_check_processor_compat(void *rtn)
2921{
2922 *(int *)rtn = 0;
2923}
2924
774ead3a
AK		 2925static bool svm_cpu_has_accelerated_tpr(void)
2926{
2927 return false;
2928}
2929
67253af5
SY		 2930static int get_npt_level(void)
2931{
2932#ifdef CONFIG_X86_64
2933 return PT64_ROOT_LEVEL;
2934#else
2935 return PT32E_ROOT_LEVEL;
2936#endif
2937}
2938
4b12f0de 2939static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 2940{
2941 return 0;
2942}
2943
0e851880
SY		 2944static void svm_cpuid_update(struct kvm_vcpu *vcpu)
2945{
2946}
2947
229456fc
MT		 2948static const struct trace_print_flags svm_exit_reasons_str[] = {
2949 { SVM_EXIT_READ_CR0, "read_cr0" },
2950 { SVM_EXIT_READ_CR3, "read_cr3" },
2951 { SVM_EXIT_READ_CR4, "read_cr4" },
2952 { SVM_EXIT_READ_CR8, "read_cr8" },
2953 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2954 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2955 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2956 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2957 { SVM_EXIT_READ_DR0, "read_dr0" },
2958 { SVM_EXIT_READ_DR1, "read_dr1" },
2959 { SVM_EXIT_READ_DR2, "read_dr2" },
2960 { SVM_EXIT_READ_DR3, "read_dr3" },
2961 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2962 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2963 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2964 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2965 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2966 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2967 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2968 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2969 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2970 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2971 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2972 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2973 { SVM_EXIT_INTR, "interrupt" },
2974 { SVM_EXIT_NMI, "nmi" },
2975 { SVM_EXIT_SMI, "smi" },
2976 { SVM_EXIT_INIT, "init" },
2977 { SVM_EXIT_VINTR, "vintr" },
2978 { SVM_EXIT_CPUID, "cpuid" },
2979 { SVM_EXIT_INVD, "invd" },
2980 { SVM_EXIT_HLT, "hlt" },
2981 { SVM_EXIT_INVLPG, "invlpg" },
2982 { SVM_EXIT_INVLPGA, "invlpga" },
2983 { SVM_EXIT_IOIO, "io" },
2984 { SVM_EXIT_MSR, "msr" },
2985 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2986 { SVM_EXIT_SHUTDOWN, "shutdown" },
2987 { SVM_EXIT_VMRUN, "vmrun" },
2988 { SVM_EXIT_VMMCALL, "hypercall" },
2989 { SVM_EXIT_VMLOAD, "vmload" },
2990 { SVM_EXIT_VMSAVE, "vmsave" },
2991 { SVM_EXIT_STGI, "stgi" },
2992 { SVM_EXIT_CLGI, "clgi" },
2993 { SVM_EXIT_SKINIT, "skinit" },
2994 { SVM_EXIT_WBINVD, "wbinvd" },
2995 { SVM_EXIT_MONITOR, "monitor" },
2996 { SVM_EXIT_MWAIT, "mwait" },
2997 { SVM_EXIT_NPF, "npf" },
2998 { -1, NULL }
2999};
3000
17cc3935 3001static int svm_get_lpage_level(void)
344f414f 3002{
17cc3935 3003 return PT_PDPE_LEVEL;
344f414f
JR		 3004}
3005
4e47c7a6
SY		 3006static bool svm_rdtscp_supported(void)
3007{
3008 return false;
3009}
3010
02daab21
AK		 3011static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3012{
3013 struct vcpu_svm *svm = to_svm(vcpu);
3014
02daab21 3015 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3016 if (is_nested(svm))
3017 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3018 update_cr0_intercept(svm);
02daab21
AK		 3019}
3020
cbdd1bea 3021static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3022 .cpu_has_kvm_support = has_svm,
3023 .disabled_by_bios = is_disabled,
3024 .hardware_setup = svm_hardware_setup,
3025 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3026 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3027 .hardware_enable = svm_hardware_enable,
3028 .hardware_disable = svm_hardware_disable,
774ead3a 3029 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3030
3031 .vcpu_create = svm_create_vcpu,
3032 .vcpu_free = svm_free_vcpu,
04d2cc77 3033 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3034
04d2cc77 3035 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3036 .vcpu_load = svm_vcpu_load,
3037 .vcpu_put = svm_vcpu_put,
3038
3039 .set_guest_debug = svm_guest_debug,
3040 .get_msr = svm_get_msr,
3041 .set_msr = svm_set_msr,
3042 .get_segment_base = svm_get_segment_base,
3043 .get_segment = svm_get_segment,
3044 .set_segment = svm_set_segment,
2e4d2653 3045 .get_cpl = svm_get_cpl,
1747fb71 3046 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3047 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3048 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3049 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3050 .set_cr3 = svm_set_cr3,
3051 .set_cr4 = svm_set_cr4,
3052 .set_efer = svm_set_efer,
3053 .get_idt = svm_get_idt,
3054 .set_idt = svm_set_idt,
3055 .get_gdt = svm_get_gdt,
3056 .set_gdt = svm_set_gdt,
3057 .get_dr = svm_get_dr,
3058 .set_dr = svm_set_dr,
6de4f3ad 3059 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3060 .get_rflags = svm_get_rflags,
3061 .set_rflags = svm_set_rflags,
6b52d186 3062 .fpu_activate = svm_fpu_activate,
02daab21 3063 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3064
6aa8b732 3065 .tlb_flush = svm_flush_tlb,
6aa8b732 3066
6aa8b732 3067 .run = svm_vcpu_run,
04d2cc77 3068 .handle_exit = handle_exit,
6aa8b732 3069 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3070 .set_interrupt_shadow = svm_set_interrupt_shadow,
3071 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3072 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3073 .set_irq = svm_set_irq,
95ba8273 3074 .set_nmi = svm_inject_nmi,
298101da 3075 .queue_exception = svm_queue_exception,
78646121 3076 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3077 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3078 .get_nmi_mask = svm_get_nmi_mask,
3079 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3080 .enable_nmi_window = enable_nmi_window,
3081 .enable_irq_window = enable_irq_window,
3082 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3083
3084 .set_tss_addr = svm_set_tss_addr,
67253af5 3085 .get_tdp_level = get_npt_level,
4b12f0de 3086 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3087
3088 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3089 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3090
3091 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3092
3093 .rdtscp_supported = svm_rdtscp_supported,
6aa8b732
AK		 3094};
3095
3096static int __init svm_init(void)
3097{
cb498ea2 3098 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
c16f862d 3099 THIS_MODULE);
6aa8b732
AK		 3100}
3101
3102static void __exit svm_exit(void)
3103{
cb498ea2 3104 kvm_exit();
6aa8b732
AK		 3105}
3106
3107module_init(svm_init)
3108module_exit(svm_exit)
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