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KVM: x86: Drop vm_init_tsc
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
221d059d 7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
edf88417
AK		 17#include <linux/kvm_host.h>
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
5fdbf976 21#include "kvm_cache_regs.h"
fe4c7b19 22#include "x86.h"
e495606d 23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/vmalloc.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
6aa8b732 31
67ec6607 32#include <asm/tlbflush.h>
e495606d 33#include <asm/desc.h>
6aa8b732 34
63d1142f 35#include <asm/virtext.h>
229456fc 36#include "trace.h"
63d1142f 37
4ecac3fd
AK		 38#define __ex(x) __kvm_handle_fault_on_reboot(x)
39
6aa8b732
AK		 40MODULE_AUTHOR("Qumranet");
41MODULE_LICENSE("GPL");
42
43#define IOPM_ALLOC_ORDER 2
44#define MSRPM_ALLOC_ORDER 1
45
6aa8b732
AK		 46#define SEG_TYPE_LDT 2
47#define SEG_TYPE_BUSY_TSS16 3
48
6bc31bdc
AP		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_FEATURE_SVML (1 << 2)
52#define SVM_FEATURE_NRIP (1 << 3)
53#define SVM_FEATURE_PAUSE_FILTER (1 << 10)
80b7706e 54
410e4d57
JR		 55#define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56#define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57#define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
24e09cbf
JR		 59#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
67ec6607
JR		 61static bool erratum_383_found __read_mostly;
62
6c8166a7
AK		 63static const u32 host_save_user_msrs[] = {
64#ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67#endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69};
70
71#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73struct kvm_vcpu;
74
e6aa9abd
JR		 75struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
4a810181 78 u64 vm_cr_msr;
e6aa9abd
JR		 79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
ce2ac085 86 u64 vmcb_iopm;
aad42c64 87
cd3ff653
JR		 88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
aad42c64
JR		 91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read;
93 u16 intercept_cr_write;
94 u16 intercept_dr_read;
95 u16 intercept_dr_write;
96 u32 intercept_exceptions;
97 u64 intercept;
98
e6aa9abd
JR		 99};
100
323c3d80
JR		 101#define MSRPM_OFFSETS 16
102static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
103
6c8166a7
AK		 104struct vcpu_svm {
105 struct kvm_vcpu vcpu;
106 struct vmcb *vmcb;
107 unsigned long vmcb_pa;
108 struct svm_cpu_data *svm_data;
109 uint64_t asid_generation;
110 uint64_t sysenter_esp;
111 uint64_t sysenter_eip;
112
113 u64 next_rip;
114
115 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
116 u64 host_gs_base;
6c8166a7
AK		 117
118 u32 *msrpm;
6c8166a7 119
e6aa9abd 120 struct nested_state nested;
6be7d306
JK		 121
122 bool nmi_singlestep;
66b7138f
JK		 123
124 unsigned int3_injected;
125 unsigned long int3_rip;
6c8166a7
AK		 126};
127
455716fa
JR		 128#define MSR_INVALID 0xffffffffU
129
ac72a9b7
JR		 130static struct svm_direct_access_msrs {
131 u32 index; /* Index of the MSR */
132 bool always; /* True if intercept is always on */
133} direct_access_msrs[] = {
8c06585d 134 { .index = MSR_STAR, .always = true },
ac72a9b7
JR		 135 { .index = MSR_IA32_SYSENTER_CS, .always = true },
136#ifdef CONFIG_X86_64
137 { .index = MSR_GS_BASE, .always = true },
138 { .index = MSR_FS_BASE, .always = true },
139 { .index = MSR_KERNEL_GS_BASE, .always = true },
140 { .index = MSR_LSTAR, .always = true },
141 { .index = MSR_CSTAR, .always = true },
142 { .index = MSR_SYSCALL_MASK, .always = true },
143#endif
144 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
145 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
146 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
147 { .index = MSR_IA32_LASTINTTOIP, .always = false },
148 { .index = MSR_INVALID, .always = false },
6c8166a7
AK		 149};
150
709ddebf
JR		 151/* enable NPT for AMD64 and X86 with PAE */
152#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
153static bool npt_enabled = true;
154#else
e0231715 155static bool npt_enabled;
709ddebf 156#endif
6c7dac72
JR		 157static int npt = 1;
158
159module_param(npt, int, S_IRUGO);
e3da3acd 160
4b6e4dca 161static int nested = 1;
236de055
AG		 162module_param(nested, int, S_IRUGO);
163
44874f84 164static void svm_flush_tlb(struct kvm_vcpu *vcpu);
a5c3832d 165static void svm_complete_interrupts(struct vcpu_svm *svm);
04d2cc77 166
410e4d57 167static int nested_svm_exit_handled(struct vcpu_svm *svm);
b8e88bc8 168static int nested_svm_intercept(struct vcpu_svm *svm);
cf74a78b 169static int nested_svm_vmexit(struct vcpu_svm *svm);
cf74a78b
AG		 170static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
171 bool has_error_code, u32 error_code);
172
a2fa3e9f
GH		 173static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
174{
fb3f0f51 175 return container_of(vcpu, struct vcpu_svm, vcpu);
a2fa3e9f
GH		 176}
177
3d6368ef
AG		 178static inline bool is_nested(struct vcpu_svm *svm)
179{
e6aa9abd 180 return svm->nested.vmcb;
3d6368ef
AG		 181}
182
2af9194d
JR		 183static inline void enable_gif(struct vcpu_svm *svm)
184{
185 svm->vcpu.arch.hflags |= HF_GIF_MASK;
186}
187
188static inline void disable_gif(struct vcpu_svm *svm)
189{
190 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
191}
192
193static inline bool gif_set(struct vcpu_svm *svm)
194{
195 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
196}
197
4866d5e3 198static unsigned long iopm_base;
6aa8b732
AK		 199
200struct kvm_ldttss_desc {
201 u16 limit0;
202 u16 base0;
e0231715
JR		 203 unsigned base1:8, type:5, dpl:2, p:1;
204 unsigned limit1:4, zero0:3, g:1, base2:8;
6aa8b732
AK		 205 u32 base3;
206 u32 zero1;
207} __attribute__((packed));
208
209struct svm_cpu_data {
210 int cpu;
211
5008fdf5
AK		 212 u64 asid_generation;
213 u32 max_asid;
214 u32 next_asid;
6aa8b732
AK		 215 struct kvm_ldttss_desc *tss_desc;
216
217 struct page *save_area;
218};
219
220static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 221static uint32_t svm_features;
6aa8b732
AK		 222
223struct svm_init_data {
224 int cpu;
225 int r;
226};
227
228static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
229
9d8f549d 230#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 231#define MSRS_RANGE_SIZE 2048
232#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
233
455716fa
JR		 234static u32 svm_msrpm_offset(u32 msr)
235{
236 u32 offset;
237 int i;
238
239 for (i = 0; i < NUM_MSR_MAPS; i++) {
240 if (msr < msrpm_ranges[i] ||
241 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
242 continue;
243
244 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
245 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
246
247 /* Now we have the u8 offset - but need the u32 offset */
248 return offset / 4;
249 }
250
251 /* MSR not in any range */
252 return MSR_INVALID;
253}
254
6aa8b732
AK		 255#define MAX_INST_SIZE 15
256
80b7706e
JR		 257static inline u32 svm_has(u32 feat)
258{
259 return svm_features & feat;
260}
261
6aa8b732
AK		 262static inline void clgi(void)
263{
4ecac3fd 264 asm volatile (__ex(SVM_CLGI));
6aa8b732
AK		 265}
266
267static inline void stgi(void)
268{
4ecac3fd 269 asm volatile (__ex(SVM_STGI));
6aa8b732
AK		 270}
271
272static inline void invlpga(unsigned long addr, u32 asid)
273{
e0231715 274 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
6aa8b732
AK		 275}
276
6aa8b732
AK		 277static inline void force_new_asid(struct kvm_vcpu *vcpu)
278{
a2fa3e9f 279 to_svm(vcpu)->asid_generation--;
6aa8b732
AK		 280}
281
282static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
283{
284 force_new_asid(vcpu);
285}
286
287static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
288{
6dc696d4 289 vcpu->arch.efer = efer;
709ddebf 290 if (!npt_enabled && !(efer & EFER_LMA))
2b5203ee 291 efer &= ~EFER_LME;
6aa8b732 292
9962d032 293 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
6aa8b732
AK		 294}
295
6aa8b732
AK		 296static int is_external_interrupt(u32 info)
297{
298 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
299 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
300}
301
2809f5d2
GC		 302static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
303{
304 struct vcpu_svm *svm = to_svm(vcpu);
305 u32 ret = 0;
306
307 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
48005f64 308 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 309 return ret & mask;
310}
311
312static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
313{
314 struct vcpu_svm *svm = to_svm(vcpu);
315
316 if (mask == 0)
317 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
318 else
319 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
320
321}
322
6aa8b732
AK		 323static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
324{
a2fa3e9f
GH		 325 struct vcpu_svm *svm = to_svm(vcpu);
326
6bc31bdc
AP		 327 if (svm->vmcb->control.next_rip != 0)
328 svm->next_rip = svm->vmcb->control.next_rip;
329
a2fa3e9f 330 if (!svm->next_rip) {
851ba692 331 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
f629cf84
GN		 332 EMULATE_DONE)
333 printk(KERN_DEBUG "%s: NOP\n", __func__);
6aa8b732
AK		 334 return;
335 }
5fdbf976
MT		 336 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
337 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
338 __func__, kvm_rip_read(vcpu), svm->next_rip);
6aa8b732 339
5fdbf976 340 kvm_rip_write(vcpu, svm->next_rip);
2809f5d2 341 svm_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 342}
343
116a4752 344static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 345 bool has_error_code, u32 error_code,
346 bool reinject)
116a4752
JK		 347{
348 struct vcpu_svm *svm = to_svm(vcpu);
349
e0231715
JR		 350 /*
351 * If we are within a nested VM we'd better #VMEXIT and let the guest
352 * handle the exception
353 */
ce7ddec4
JR		 354 if (!reinject &&
355 nested_svm_check_exception(svm, nr, has_error_code, error_code))
116a4752
JK		 356 return;
357
66b7138f
JK		 358 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
359 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
360
361 /*
362 * For guest debugging where we have to reinject #BP if some
363 * INT3 is guest-owned:
364 * Emulate nRIP by moving RIP forward. Will fail if injection
365 * raises a fault that is not intercepted. Still better than
366 * failing in all cases.
367 */
368 skip_emulated_instruction(&svm->vcpu);
369 rip = kvm_rip_read(&svm->vcpu);
370 svm->int3_rip = rip + svm->vmcb->save.cs.base;
371 svm->int3_injected = rip - old_rip;
372 }
373
116a4752
JK		 374 svm->vmcb->control.event_inj = nr
375 | SVM_EVTINJ_VALID
376 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
377 | SVM_EVTINJ_TYPE_EXEPT;
378 svm->vmcb->control.event_inj_err = error_code;
379}
380
67ec6607
JR		 381static void svm_init_erratum_383(void)
382{
383 u32 low, high;
384 int err;
385 u64 val;
386
1be85a6d 387 if (!cpu_has_amd_erratum(amd_erratum_383))
67ec6607
JR		 388 return;
389
390 /* Use _safe variants to not break nested virtualization */
391 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
392 if (err)
393 return;
394
395 val |= (1ULL << 47);
396
397 low = lower_32_bits(val);
398 high = upper_32_bits(val);
399
400 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
401
402 erratum_383_found = true;
403}
404
6aa8b732
AK		 405static int has_svm(void)
406{
63d1142f 407 const char *msg;
6aa8b732 408
63d1142f 409 if (!cpu_has_svm(&msg)) {
ff81ff10 410 printk(KERN_INFO "has_svm: %s\n", msg);
6aa8b732
AK		 411 return 0;
412 }
413
6aa8b732
AK		 414 return 1;
415}
416
417static void svm_hardware_disable(void *garbage)
418{
2c8dceeb 419 cpu_svm_disable();
6aa8b732
AK		 420}
421
10474ae8 422static int svm_hardware_enable(void *garbage)
6aa8b732
AK		 423{
424
0fe1e009 425 struct svm_cpu_data *sd;
6aa8b732 426 uint64_t efer;
89a27f4d 427 struct desc_ptr gdt_descr;
6aa8b732
AK		 428 struct desc_struct *gdt;
429 int me = raw_smp_processor_id();
430
10474ae8
AG		 431 rdmsrl(MSR_EFER, efer);
432 if (efer & EFER_SVME)
433 return -EBUSY;
434
6aa8b732 435 if (!has_svm()) {
e6732a5a
ZA		 436 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
437 me);
10474ae8 438 return -EINVAL;
6aa8b732 439 }
0fe1e009 440 sd = per_cpu(svm_data, me);
6aa8b732 441
0fe1e009 442 if (!sd) {
e6732a5a 443 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
6aa8b732 444 me);
10474ae8 445 return -EINVAL;
6aa8b732
AK		 446 }
447
0fe1e009
TH		 448 sd->asid_generation = 1;
449 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
450 sd->next_asid = sd->max_asid + 1;
6aa8b732 451
d6ab1ed4 452 native_store_gdt(&gdt_descr);
89a27f4d 453 gdt = (struct desc_struct *)gdt_descr.address;
0fe1e009 454 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
6aa8b732 455
9962d032 456 wrmsrl(MSR_EFER, efer | EFER_SVME);
6aa8b732 457
d0316554 458 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
10474ae8 459
67ec6607
JR		 460 svm_init_erratum_383();
461
10474ae8 462 return 0;
6aa8b732
AK		 463}
464
0da1db75
JR		 465static void svm_cpu_uninit(int cpu)
466{
0fe1e009 467 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
0da1db75 468
0fe1e009 469 if (!sd)
0da1db75
JR		 470 return;
471
472 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
0fe1e009
TH		 473 __free_page(sd->save_area);
474 kfree(sd);
0da1db75
JR		 475}
476
6aa8b732
AK		 477static int svm_cpu_init(int cpu)
478{
0fe1e009 479 struct svm_cpu_data *sd;
6aa8b732
AK		 480 int r;
481
0fe1e009
TH		 482 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
483 if (!sd)
6aa8b732 484 return -ENOMEM;
0fe1e009
TH		 485 sd->cpu = cpu;
486 sd->save_area = alloc_page(GFP_KERNEL);
6aa8b732 487 r = -ENOMEM;
0fe1e009 488 if (!sd->save_area)
6aa8b732
AK		 489 goto err_1;
490
0fe1e009 491 per_cpu(svm_data, cpu) = sd;
6aa8b732
AK		 492
493 return 0;
494
495err_1:
0fe1e009 496 kfree(sd);
6aa8b732
AK		 497 return r;
498
499}
500
ac72a9b7
JR		 501static bool valid_msr_intercept(u32 index)
502{
503 int i;
504
505 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
506 if (direct_access_msrs[i].index == index)
507 return true;
508
509 return false;
510}
511
bfc733a7
RR		 512static void set_msr_interception(u32 *msrpm, unsigned msr,
513 int read, int write)
6aa8b732 514{
455716fa
JR		 515 u8 bit_read, bit_write;
516 unsigned long tmp;
517 u32 offset;
6aa8b732 518
ac72a9b7
JR		 519 /*
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
522 */
523 WARN_ON(!valid_msr_intercept(msr));
524
455716fa
JR		 525 offset = svm_msrpm_offset(msr);
526 bit_read = 2 * (msr & 0x0f);
527 bit_write = 2 * (msr & 0x0f) + 1;
528 tmp = msrpm[offset];
529
530 BUG_ON(offset == MSR_INVALID);
531
532 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
533 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
534
535 msrpm[offset] = tmp;
6aa8b732
AK		 536}
537
f65c229c 538static void svm_vcpu_init_msrpm(u32 *msrpm)
6aa8b732
AK		 539{
540 int i;
541
f65c229c
JR		 542 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
543
ac72a9b7
JR		 544 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
545 if (!direct_access_msrs[i].always)
546 continue;
547
548 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
549 }
f65c229c
JR		 550}
551
323c3d80
JR		 552static void add_msr_offset(u32 offset)
553{
554 int i;
555
556 for (i = 0; i < MSRPM_OFFSETS; ++i) {
557
558 /* Offset already in list? */
559 if (msrpm_offsets[i] == offset)
bfc733a7 560 return;
323c3d80
JR		 561
562 /* Slot used by another offset? */
563 if (msrpm_offsets[i] != MSR_INVALID)
564 continue;
565
566 /* Add offset to list */
567 msrpm_offsets[i] = offset;
568
569 return;
6aa8b732 570 }
323c3d80
JR		 571
572 /*
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
575 */
bfc733a7 576 BUG();
6aa8b732
AK		 577}
578
323c3d80 579static void init_msrpm_offsets(void)
f65c229c 580{
323c3d80 581 int i;
f65c229c 582
323c3d80
JR		 583 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
584
585 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
586 u32 offset;
587
588 offset = svm_msrpm_offset(direct_access_msrs[i].index);
589 BUG_ON(offset == MSR_INVALID);
590
591 add_msr_offset(offset);
592 }
f65c229c
JR		 593}
594
24e09cbf
JR		 595static void svm_enable_lbrv(struct vcpu_svm *svm)
596{
597 u32 *msrpm = svm->msrpm;
598
599 svm->vmcb->control.lbr_ctl = 1;
600 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
601 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
602 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
603 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
604}
605
606static void svm_disable_lbrv(struct vcpu_svm *svm)
607{
608 u32 *msrpm = svm->msrpm;
609
610 svm->vmcb->control.lbr_ctl = 0;
611 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
612 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
613 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
614 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
615}
616
6aa8b732
AK		 617static __init int svm_hardware_setup(void)
618{
619 int cpu;
620 struct page *iopm_pages;
f65c229c 621 void *iopm_va;
6aa8b732
AK		 622 int r;
623
6aa8b732
AK		 624 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
625
626 if (!iopm_pages)
627 return -ENOMEM;
c8681339
AL		 628
629 iopm_va = page_address(iopm_pages);
630 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
6aa8b732
AK		 631 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
632
323c3d80
JR		 633 init_msrpm_offsets();
634
50a37eb4
JR		 635 if (boot_cpu_has(X86_FEATURE_NX))
636 kvm_enable_efer_bits(EFER_NX);
637
1b2fd70c
AG		 638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
639 kvm_enable_efer_bits(EFER_FFXSR);
640
236de055
AG		 641 if (nested) {
642 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
eec4b140 643 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
236de055
AG		 644 }
645
3230bb47 646 for_each_possible_cpu(cpu) {
6aa8b732
AK		 647 r = svm_cpu_init(cpu);
648 if (r)
f65c229c 649 goto err;
6aa8b732 650 }
33bd6a0b
JR		 651
652 svm_features = cpuid_edx(SVM_CPUID_FUNC);
653
e3da3acd
JR		 654 if (!svm_has(SVM_FEATURE_NPT))
655 npt_enabled = false;
656
6c7dac72
JR		 657 if (npt_enabled && !npt) {
658 printk(KERN_INFO "kvm: Nested Paging disabled\n");
659 npt_enabled = false;
660 }
661
18552672 662 if (npt_enabled) {
e3da3acd 663 printk(KERN_INFO "kvm: Nested Paging enabled\n");
18552672 664 kvm_enable_tdp();
5f4cb662
JR		 665 } else
666 kvm_disable_tdp();
e3da3acd 667
6aa8b732
AK		 668 return 0;
669
f65c229c 670err:
6aa8b732
AK		 671 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
672 iopm_base = 0;
673 return r;
674}
675
676static __exit void svm_hardware_unsetup(void)
677{
0da1db75
JR		 678 int cpu;
679
3230bb47 680 for_each_possible_cpu(cpu)
0da1db75
JR		 681 svm_cpu_uninit(cpu);
682
6aa8b732 683 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
f65c229c 684 iopm_base = 0;
6aa8b732
AK		 685}
686
687static void init_seg(struct vmcb_seg *seg)
688{
689 seg->selector = 0;
690 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
e0231715 691 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
6aa8b732
AK		 692 seg->limit = 0xffff;
693 seg->base = 0;
694}
695
696static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
697{
698 seg->selector = 0;
699 seg->attrib = SVM_SELECTOR_P_MASK | type;
700 seg->limit = 0xffff;
701 seg->base = 0;
702}
703
e6101a96 704static void init_vmcb(struct vcpu_svm *svm)
6aa8b732 705{
e6101a96
JR		 706 struct vmcb_control_area *control = &svm->vmcb->control;
707 struct vmcb_save_area *save = &svm->vmcb->save;
6aa8b732 708
bff78274
AK		 709 svm->vcpu.fpu_active = 1;
710
e0231715 711 control->intercept_cr_read = INTERCEPT_CR0_MASK |
6aa8b732 712 INTERCEPT_CR3_MASK |
649d6864 713 INTERCEPT_CR4_MASK;
6aa8b732 714
e0231715 715 control->intercept_cr_write = INTERCEPT_CR0_MASK |
6aa8b732 716 INTERCEPT_CR3_MASK |
80a8119c
AK		 717 INTERCEPT_CR4_MASK |
718 INTERCEPT_CR8_MASK;
6aa8b732 719
e0231715 720 control->intercept_dr_read = INTERCEPT_DR0_MASK |
6aa8b732
AK		 721 INTERCEPT_DR1_MASK |
722 INTERCEPT_DR2_MASK |
727f5a23
JK		 723 INTERCEPT_DR3_MASK |
724 INTERCEPT_DR4_MASK |
725 INTERCEPT_DR5_MASK |
726 INTERCEPT_DR6_MASK |
727 INTERCEPT_DR7_MASK;
6aa8b732 728
e0231715 729 control->intercept_dr_write = INTERCEPT_DR0_MASK |
6aa8b732
AK		 730 INTERCEPT_DR1_MASK |
731 INTERCEPT_DR2_MASK |
732 INTERCEPT_DR3_MASK |
727f5a23 733 INTERCEPT_DR4_MASK |
6aa8b732 734 INTERCEPT_DR5_MASK |
727f5a23 735 INTERCEPT_DR6_MASK |
6aa8b732
AK		 736 INTERCEPT_DR7_MASK;
737
7aa81cc0 738 control->intercept_exceptions = (1 << PF_VECTOR) |
53371b50
JR		 739 (1 << UD_VECTOR) |
740 (1 << MC_VECTOR);
6aa8b732
AK		 741
742
e0231715 743 control->intercept = (1ULL << INTERCEPT_INTR) |
6aa8b732 744 (1ULL << INTERCEPT_NMI) |
0152527b 745 (1ULL << INTERCEPT_SMI) |
d225157b 746 (1ULL << INTERCEPT_SELECTIVE_CR0) |
6aa8b732 747 (1ULL << INTERCEPT_CPUID) |
cf5a94d1 748 (1ULL << INTERCEPT_INVD) |
6aa8b732 749 (1ULL << INTERCEPT_HLT) |
a7052897 750 (1ULL << INTERCEPT_INVLPG) |
6aa8b732
AK		 751 (1ULL << INTERCEPT_INVLPGA) |
752 (1ULL << INTERCEPT_IOIO_PROT) |
753 (1ULL << INTERCEPT_MSR_PROT) |
754 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 755 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 756 (1ULL << INTERCEPT_VMRUN) |
757 (1ULL << INTERCEPT_VMMCALL) |
758 (1ULL << INTERCEPT_VMLOAD) |
759 (1ULL << INTERCEPT_VMSAVE) |
760 (1ULL << INTERCEPT_STGI) |
761 (1ULL << INTERCEPT_CLGI) |
916ce236 762 (1ULL << INTERCEPT_SKINIT) |
cf5a94d1 763 (1ULL << INTERCEPT_WBINVD) |
916ce236
JR		 764 (1ULL << INTERCEPT_MONITOR) |
765 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 766
767 control->iopm_base_pa = iopm_base;
f65c229c 768 control->msrpm_base_pa = __pa(svm->msrpm);
6aa8b732
AK		 769 control->int_ctl = V_INTR_MASKING_MASK;
770
771 init_seg(&save->es);
772 init_seg(&save->ss);
773 init_seg(&save->ds);
774 init_seg(&save->fs);
775 init_seg(&save->gs);
776
777 save->cs.selector = 0xf000;
778 /* Executable/Readable Code Segment */
779 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
780 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
781 save->cs.limit = 0xffff;
d92899a0
AK		 782 /*
783 * cs.base should really be 0xffff0000, but vmx can't handle that, so
784 * be consistent with it.
785 *
786 * Replace when we have real mode working for vmx.
787 */
788 save->cs.base = 0xf0000;
6aa8b732
AK		 789
790 save->gdtr.limit = 0xffff;
791 save->idtr.limit = 0xffff;
792
793 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
794 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
795
9962d032 796 save->efer = EFER_SVME;
d77c26fc 797 save->dr6 = 0xffff0ff0;
6aa8b732
AK		 798 save->dr7 = 0x400;
799 save->rflags = 2;
800 save->rip = 0x0000fff0;
5fdbf976 801 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
6aa8b732 802
e0231715
JR		 803 /*
804 * This is the guest-visible cr0 value.
18fa000a 805 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
6aa8b732 806 */
18fa000a 807 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
49a9b07e 808 (void)kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
18fa000a 809
66aee91a 810 save->cr4 = X86_CR4_PAE;
6aa8b732 811 /* rdx = ?? */
709ddebf
JR		 812
813 if (npt_enabled) {
814 /* Setup VMCB for Nested Paging */
815 control->nested_ctl = 1;
a7052897
MT		 816 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
817 (1ULL << INTERCEPT_INVLPG));
709ddebf 818 control->intercept_exceptions &= ~(1 << PF_VECTOR);
888f9f3e
AK		 819 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
820 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
709ddebf 821 save->g_pat = 0x0007040600070406ULL;
709ddebf
JR		 822 save->cr3 = 0;
823 save->cr4 = 0;
824 }
a79d2f18 825 force_new_asid(&svm->vcpu);
1371d904 826
e6aa9abd 827 svm->nested.vmcb = 0;
2af9194d
JR		 828 svm->vcpu.arch.hflags = 0;
829
565d0998
ML		 830 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
831 control->pause_filter_count = 3000;
832 control->intercept |= (1ULL << INTERCEPT_PAUSE);
833 }
834
2af9194d 835 enable_gif(svm);
6aa8b732
AK		 836}
837
e00c8cf2 838static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
04d2cc77
AK		 839{
840 struct vcpu_svm *svm = to_svm(vcpu);
841
e6101a96 842 init_vmcb(svm);
70433389 843
c5af89b6 844 if (!kvm_vcpu_is_bsp(vcpu)) {
5fdbf976 845 kvm_rip_write(vcpu, 0);
ad312c7c
ZX		 846 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
847 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
70433389 848 }
5fdbf976
MT		 849 vcpu->arch.regs_avail = ~0;
850 vcpu->arch.regs_dirty = ~0;
e00c8cf2
AK		 851
852 return 0;
04d2cc77
AK		 853}
854
fb3f0f51 855static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 856{
a2fa3e9f 857 struct vcpu_svm *svm;
6aa8b732 858 struct page *page;
f65c229c 859 struct page *msrpm_pages;
b286d5d8 860 struct page *hsave_page;
3d6368ef 861 struct page *nested_msrpm_pages;
fb3f0f51 862 int err;
6aa8b732 863
c16f862d 864 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
fb3f0f51
RR		 865 if (!svm) {
866 err = -ENOMEM;
867 goto out;
868 }
869
870 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
871 if (err)
872 goto free_svm;
873
b7af4043 874 err = -ENOMEM;
6aa8b732 875 page = alloc_page(GFP_KERNEL);
b7af4043 876 if (!page)
fb3f0f51 877 goto uninit;
6aa8b732 878
f65c229c
JR		 879 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
880 if (!msrpm_pages)
b7af4043 881 goto free_page1;
3d6368ef
AG		 882
883 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
884 if (!nested_msrpm_pages)
b7af4043 885 goto free_page2;
f65c229c 886
b286d5d8
AG		 887 hsave_page = alloc_page(GFP_KERNEL);
888 if (!hsave_page)
b7af4043
TY		 889 goto free_page3;
890
e6aa9abd 891 svm->nested.hsave = page_address(hsave_page);
b286d5d8 892
b7af4043
TY		 893 svm->msrpm = page_address(msrpm_pages);
894 svm_vcpu_init_msrpm(svm->msrpm);
895
e6aa9abd 896 svm->nested.msrpm = page_address(nested_msrpm_pages);
323c3d80 897 svm_vcpu_init_msrpm(svm->nested.msrpm);
3d6368ef 898
a2fa3e9f
GH		 899 svm->vmcb = page_address(page);
900 clear_page(svm->vmcb);
901 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
902 svm->asid_generation = 0;
e6101a96 903 init_vmcb(svm);
47008cd8 904 svm->vmcb->control.tsc_offset = 0-native_read_tsc();
a2fa3e9f 905
10ab25cd
JK		 906 err = fx_init(&svm->vcpu);
907 if (err)
908 goto free_page4;
909
ad312c7c 910 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 911 if (kvm_vcpu_is_bsp(&svm->vcpu))
ad312c7c 912 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 913
fb3f0f51 914 return &svm->vcpu;
36241b8c 915
10ab25cd
JK		 916free_page4:
917 __free_page(hsave_page);
b7af4043
TY		 918free_page3:
919 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
920free_page2:
921 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
922free_page1:
923 __free_page(page);
fb3f0f51
RR		 924uninit:
925 kvm_vcpu_uninit(&svm->vcpu);
926free_svm:
a4770347 927 kmem_cache_free(kvm_vcpu_cache, svm);
fb3f0f51
RR		 928out:
929 return ERR_PTR(err);
6aa8b732
AK		 930}
931
932static void svm_free_vcpu(struct kvm_vcpu *vcpu)
933{
a2fa3e9f
GH		 934 struct vcpu_svm *svm = to_svm(vcpu);
935
fb3f0f51 936 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
f65c229c 937 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
e6aa9abd
JR		 938 __free_page(virt_to_page(svm->nested.hsave));
939 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
fb3f0f51 940 kvm_vcpu_uninit(vcpu);
a4770347 941 kmem_cache_free(kvm_vcpu_cache, svm);
6aa8b732
AK		 942}
943
15ad7146 944static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 945{
a2fa3e9f 946 struct vcpu_svm *svm = to_svm(vcpu);
15ad7146 947 int i;
0cc5064d 948
0cc5064d 949 if (unlikely(cpu != vcpu->cpu)) {
e935d48e 950 u64 delta;
0cc5064d 951
953899b6
JR		 952 if (check_tsc_unstable()) {
953 /*
954 * Make sure that the guest sees a monotonically
955 * increasing TSC.
956 */
957 delta = vcpu->arch.host_tsc - native_read_tsc();
958 svm->vmcb->control.tsc_offset += delta;
959 if (is_nested(svm))
960 svm->nested.hsave->control.tsc_offset += delta;
961 }
0cc5064d 962 vcpu->cpu = cpu;
2f599714 963 kvm_migrate_timers(vcpu);
4b656b12 964 svm->asid_generation = 0;
0cc5064d 965 }
94dfbdb3
AL		 966
967 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 968 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
6aa8b732
AK		 969}
970
971static void svm_vcpu_put(struct kvm_vcpu *vcpu)
972{
a2fa3e9f 973 struct vcpu_svm *svm = to_svm(vcpu);
94dfbdb3
AL		 974 int i;
975
e1beb1d3 976 ++vcpu->stat.host_state_reload;
94dfbdb3 977 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
a2fa3e9f 978 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
94dfbdb3 979
e935d48e 980 vcpu->arch.host_tsc = native_read_tsc();
6aa8b732
AK		 981}
982
6aa8b732
AK		 983static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
984{
a2fa3e9f 985 return to_svm(vcpu)->vmcb->save.rflags;
6aa8b732
AK		 986}
987
988static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
989{
a2fa3e9f 990 to_svm(vcpu)->vmcb->save.rflags = rflags;
6aa8b732
AK		 991}
992
6de4f3ad
AK		 993static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
994{
995 switch (reg) {
996 case VCPU_EXREG_PDPTR:
997 BUG_ON(!npt_enabled);
998 load_pdptrs(vcpu, vcpu->arch.cr3);
999 break;
1000 default:
1001 BUG();
1002 }
1003}
1004
f0b85051
AG		 1005static void svm_set_vintr(struct vcpu_svm *svm)
1006{
1007 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1008}
1009
1010static void svm_clear_vintr(struct vcpu_svm *svm)
1011{
1012 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1013}
1014
6aa8b732
AK		 1015static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1016{
a2fa3e9f 1017 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
6aa8b732
AK		 1018
1019 switch (seg) {
1020 case VCPU_SREG_CS: return &save->cs;
1021 case VCPU_SREG_DS: return &save->ds;
1022 case VCPU_SREG_ES: return &save->es;
1023 case VCPU_SREG_FS: return &save->fs;
1024 case VCPU_SREG_GS: return &save->gs;
1025 case VCPU_SREG_SS: return &save->ss;
1026 case VCPU_SREG_TR: return &save->tr;
1027 case VCPU_SREG_LDTR: return &save->ldtr;
1028 }
1029 BUG();
8b6d44c7 1030 return NULL;
6aa8b732
AK		 1031}
1032
1033static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1034{
1035 struct vmcb_seg *s = svm_seg(vcpu, seg);
1036
1037 return s->base;
1038}
1039
1040static void svm_get_segment(struct kvm_vcpu *vcpu,
1041 struct kvm_segment *var, int seg)
1042{
1043 struct vmcb_seg *s = svm_seg(vcpu, seg);
1044
1045 var->base = s->base;
1046 var->limit = s->limit;
1047 var->selector = s->selector;
1048 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1049 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1050 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1051 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1052 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1053 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1054 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1055 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
25022acc 1056
e0231715
JR		 1057 /*
1058 * AMD's VMCB does not have an explicit unusable field, so emulate it
19bca6ab
AP		 1059 * for cross vendor migration purposes by "not present"
1060 */
1061 var->unusable = !var->present || (var->type == 0);
1062
1fbdc7a5
AP		 1063 switch (seg) {
1064 case VCPU_SREG_CS:
1065 /*
1066 * SVM always stores 0 for the 'G' bit in the CS selector in
1067 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1068 * Intel's VMENTRY has a check on the 'G' bit.
1069 */
25022acc 1070 var->g = s->limit > 0xfffff;
1fbdc7a5
AP		 1071 break;
1072 case VCPU_SREG_TR:
1073 /*
1074 * Work around a bug where the busy flag in the tr selector
1075 * isn't exposed
1076 */
c0d09828 1077 var->type |= 0x2;
1fbdc7a5
AP		 1078 break;
1079 case VCPU_SREG_DS:
1080 case VCPU_SREG_ES:
1081 case VCPU_SREG_FS:
1082 case VCPU_SREG_GS:
1083 /*
1084 * The accessed bit must always be set in the segment
1085 * descriptor cache, although it can be cleared in the
1086 * descriptor, the cached bit always remains at 1. Since
1087 * Intel has a check on this, set it here to support
1088 * cross-vendor migration.
1089 */
1090 if (!var->unusable)
1091 var->type |= 0x1;
1092 break;
b586eb02 1093 case VCPU_SREG_SS:
e0231715
JR		 1094 /*
1095 * On AMD CPUs sometimes the DB bit in the segment
b586eb02
AP		 1096 * descriptor is left as 1, although the whole segment has
1097 * been made unusable. Clear it here to pass an Intel VMX
1098 * entry check when cross vendor migrating.
1099 */
1100 if (var->unusable)
1101 var->db = 0;
1102 break;
1fbdc7a5 1103 }
6aa8b732
AK		 1104}
1105
2e4d2653
IE		 1106static int svm_get_cpl(struct kvm_vcpu *vcpu)
1107{
1108 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1109
1110 return save->cpl;
1111}
1112
89a27f4d 1113static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1114{
a2fa3e9f
GH		 1115 struct vcpu_svm *svm = to_svm(vcpu);
1116
89a27f4d
GN		 1117 dt->size = svm->vmcb->save.idtr.limit;
1118 dt->address = svm->vmcb->save.idtr.base;
6aa8b732
AK		 1119}
1120
89a27f4d 1121static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1122{
a2fa3e9f
GH		 1123 struct vcpu_svm *svm = to_svm(vcpu);
1124
89a27f4d
GN		 1125 svm->vmcb->save.idtr.limit = dt->size;
1126 svm->vmcb->save.idtr.base = dt->address ;
6aa8b732
AK		 1127}
1128
89a27f4d 1129static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1130{
a2fa3e9f
GH		 1131 struct vcpu_svm *svm = to_svm(vcpu);
1132
89a27f4d
GN		 1133 dt->size = svm->vmcb->save.gdtr.limit;
1134 dt->address = svm->vmcb->save.gdtr.base;
6aa8b732
AK		 1135}
1136
89a27f4d 1137static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1138{
a2fa3e9f
GH		 1139 struct vcpu_svm *svm = to_svm(vcpu);
1140
89a27f4d
GN		 1141 svm->vmcb->save.gdtr.limit = dt->size;
1142 svm->vmcb->save.gdtr.base = dt->address ;
6aa8b732
AK		 1143}
1144
e8467fda
AK		 1145static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1146{
1147}
1148
25c4c276 1149static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 1150{
1151}
1152
d225157b
AK		 1153static void update_cr0_intercept(struct vcpu_svm *svm)
1154{
66a562f7 1155 struct vmcb *vmcb = svm->vmcb;
d225157b
AK		 1156 ulong gcr0 = svm->vcpu.arch.cr0;
1157 u64 *hcr0 = &svm->vmcb->save.cr0;
1158
1159 if (!svm->vcpu.fpu_active)
1160 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1161 else
1162 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1163 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1164
1165
1166 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
66a562f7
JR		 1167 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1168 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1169 if (is_nested(svm)) {
1170 struct vmcb *hsave = svm->nested.hsave;
1171
1172 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1173 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1174 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1175 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1176 }
d225157b
AK		 1177 } else {
1178 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1179 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
66a562f7
JR		 1180 if (is_nested(svm)) {
1181 struct vmcb *hsave = svm->nested.hsave;
1182
1183 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1184 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1185 }
d225157b
AK		 1186 }
1187}
1188
6aa8b732
AK		 1189static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1190{
a2fa3e9f
GH		 1191 struct vcpu_svm *svm = to_svm(vcpu);
1192
7f5d8b56
JR		 1193 if (is_nested(svm)) {
1194 /*
1195 * We are here because we run in nested mode, the host kvm
1196 * intercepts cr0 writes but the l1 hypervisor does not.
1197 * But the L1 hypervisor may intercept selective cr0 writes.
1198 * This needs to be checked here.
1199 */
1200 unsigned long old, new;
1201
1202 /* Remove bits that would trigger a real cr0 write intercept */
1203 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1204 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1205
1206 if (old == new) {
1207 /* cr0 write with ts and mp unchanged */
1208 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1209 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1210 return;
1211 }
1212 }
1213
05b3e0c2 1214#ifdef CONFIG_X86_64
f6801dff 1215 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1216 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
f6801dff 1217 vcpu->arch.efer |= EFER_LMA;
2b5203ee 1218 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1219 }
1220
d77c26fc 1221 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
f6801dff 1222 vcpu->arch.efer &= ~EFER_LMA;
2b5203ee 1223 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
6aa8b732
AK		 1224 }
1225 }
1226#endif
ad312c7c 1227 vcpu->arch.cr0 = cr0;
888f9f3e
AK		 1228
1229 if (!npt_enabled)
1230 cr0 |= X86_CR0_PG | X86_CR0_WP;
02daab21
AK		 1231
1232 if (!vcpu->fpu_active)
334df50a 1233 cr0 |= X86_CR0_TS;
709ddebf
JR		 1234 /*
1235 * re-enable caching here because the QEMU bios
1236 * does not do it - this results in some delay at
1237 * reboot
1238 */
1239 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
a2fa3e9f 1240 svm->vmcb->save.cr0 = cr0;
d225157b 1241 update_cr0_intercept(svm);
6aa8b732
AK		 1242}
1243
1244static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1245{
6394b649 1246 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
e5eab0ce
JR		 1247 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1248
1249 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1250 force_new_asid(vcpu);
6394b649 1251
ec077263
JR		 1252 vcpu->arch.cr4 = cr4;
1253 if (!npt_enabled)
1254 cr4 |= X86_CR4_PAE;
6394b649 1255 cr4 |= host_cr4_mce;
ec077263 1256 to_svm(vcpu)->vmcb->save.cr4 = cr4;
6aa8b732
AK		 1257}
1258
1259static void svm_set_segment(struct kvm_vcpu *vcpu,
1260 struct kvm_segment *var, int seg)
1261{
a2fa3e9f 1262 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 1263 struct vmcb_seg *s = svm_seg(vcpu, seg);
1264
1265 s->base = var->base;
1266 s->limit = var->limit;
1267 s->selector = var->selector;
1268 if (var->unusable)
1269 s->attrib = 0;
1270 else {
1271 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1272 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1273 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1274 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1275 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1276 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1277 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1278 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1279 }
1280 if (seg == VCPU_SREG_CS)
a2fa3e9f
GH		 1281 svm->vmcb->save.cpl
1282 = (svm->vmcb->save.cs.attrib
6aa8b732
AK		 1283 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1284
1285}
1286
44c11430 1287static void update_db_intercept(struct kvm_vcpu *vcpu)
6aa8b732 1288{
d0bfb940
JK		 1289 struct vcpu_svm *svm = to_svm(vcpu);
1290
d0bfb940
JK		 1291 svm->vmcb->control.intercept_exceptions &=
1292 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
44c11430 1293
6be7d306 1294 if (svm->nmi_singlestep)
44c11430
GN		 1295 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1296
d0bfb940
JK		 1297 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1298 if (vcpu->guest_debug &
1299 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1300 svm->vmcb->control.intercept_exceptions |=
1301 1 << DB_VECTOR;
1302 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1303 svm->vmcb->control.intercept_exceptions |=
1304 1 << BP_VECTOR;
1305 } else
1306 vcpu->guest_debug = 0;
44c11430
GN		 1307}
1308
355be0b9 1309static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
44c11430 1310{
44c11430
GN		 1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
ae675ef0
JK		 1313 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1314 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1315 else
1316 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1317
355be0b9 1318 update_db_intercept(vcpu);
6aa8b732
AK		 1319}
1320
1321static void load_host_msrs(struct kvm_vcpu *vcpu)
1322{
94dfbdb3 1323#ifdef CONFIG_X86_64
a2fa3e9f 1324 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1325#endif
6aa8b732
AK		 1326}
1327
1328static void save_host_msrs(struct kvm_vcpu *vcpu)
1329{
94dfbdb3 1330#ifdef CONFIG_X86_64
a2fa3e9f 1331 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
94dfbdb3 1332#endif
6aa8b732
AK		 1333}
1334
0fe1e009 1335static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
6aa8b732 1336{
0fe1e009
TH		 1337 if (sd->next_asid > sd->max_asid) {
1338 ++sd->asid_generation;
1339 sd->next_asid = 1;
a2fa3e9f 1340 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
6aa8b732
AK		 1341 }
1342
0fe1e009
TH		 1343 svm->asid_generation = sd->asid_generation;
1344 svm->vmcb->control.asid = sd->next_asid++;
6aa8b732
AK		 1345}
1346
020df079 1347static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
6aa8b732 1348{
42dbaa5a 1349 struct vcpu_svm *svm = to_svm(vcpu);
42dbaa5a 1350
020df079 1351 svm->vmcb->save.dr7 = value;
6aa8b732
AK		 1352}
1353
851ba692 1354static int pf_interception(struct vcpu_svm *svm)
6aa8b732 1355{
6aa8b732
AK		 1356 u64 fault_address;
1357 u32 error_code;
6aa8b732 1358
a2fa3e9f
GH		 1359 fault_address = svm->vmcb->control.exit_info_2;
1360 error_code = svm->vmcb->control.exit_info_1;
af9ca2d7 1361
229456fc 1362 trace_kvm_page_fault(fault_address, error_code);
52c7847d
AK		 1363 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1364 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
3067714c 1365 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
6aa8b732
AK		 1366}
1367
851ba692 1368static int db_interception(struct vcpu_svm *svm)
d0bfb940 1369{
851ba692
AK		 1370 struct kvm_run *kvm_run = svm->vcpu.run;
1371
d0bfb940 1372 if (!(svm->vcpu.guest_debug &
44c11430 1373 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
6be7d306 1374 !svm->nmi_singlestep) {
d0bfb940
JK		 1375 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1376 return 1;
1377 }
44c11430 1378
6be7d306
JK		 1379 if (svm->nmi_singlestep) {
1380 svm->nmi_singlestep = false;
44c11430
GN		 1381 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1382 svm->vmcb->save.rflags &=
1383 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1384 update_db_intercept(&svm->vcpu);
1385 }
1386
1387 if (svm->vcpu.guest_debug &
e0231715 1388 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
44c11430
GN		 1389 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1390 kvm_run->debug.arch.pc =
1391 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1392 kvm_run->debug.arch.exception = DB_VECTOR;
1393 return 0;
1394 }
1395
1396 return 1;
d0bfb940
JK		 1397}
1398
851ba692 1399static int bp_interception(struct vcpu_svm *svm)
d0bfb940 1400{
851ba692
AK		 1401 struct kvm_run *kvm_run = svm->vcpu.run;
1402
d0bfb940
JK		 1403 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1404 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1405 kvm_run->debug.arch.exception = BP_VECTOR;
1406 return 0;
1407}
1408
851ba692 1409static int ud_interception(struct vcpu_svm *svm)
7aa81cc0
AL		 1410{
1411 int er;
1412
851ba692 1413 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 1414 if (er != EMULATE_DONE)
7ee5d940 1415 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
7aa81cc0
AL		 1416 return 1;
1417}
1418
6b52d186 1419static void svm_fpu_activate(struct kvm_vcpu *vcpu)
7807fa6c 1420{
6b52d186 1421 struct vcpu_svm *svm = to_svm(vcpu);
66a562f7
JR		 1422 u32 excp;
1423
1424 if (is_nested(svm)) {
1425 u32 h_excp, n_excp;
1426
1427 h_excp = svm->nested.hsave->control.intercept_exceptions;
1428 n_excp = svm->nested.intercept_exceptions;
1429 h_excp &= ~(1 << NM_VECTOR);
1430 excp = h_excp | n_excp;
1431 } else {
1432 excp = svm->vmcb->control.intercept_exceptions;
e0231715 1433 excp &= ~(1 << NM_VECTOR);
66a562f7
JR		 1434 }
1435
1436 svm->vmcb->control.intercept_exceptions = excp;
1437
e756fc62 1438 svm->vcpu.fpu_active = 1;
d225157b 1439 update_cr0_intercept(svm);
6b52d186 1440}
a2fa3e9f 1441
6b52d186
AK		 1442static int nm_interception(struct vcpu_svm *svm)
1443{
1444 svm_fpu_activate(&svm->vcpu);
a2fa3e9f 1445 return 1;
7807fa6c
AL		 1446}
1447
67ec6607
JR		 1448static bool is_erratum_383(void)
1449{
1450 int err, i;
1451 u64 value;
1452
1453 if (!erratum_383_found)
1454 return false;
1455
1456 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1457 if (err)
1458 return false;
1459
1460 /* Bit 62 may or may not be set for this mce */
1461 value &= ~(1ULL << 62);
1462
1463 if (value != 0xb600000000010015ULL)
1464 return false;
1465
1466 /* Clear MCi_STATUS registers */
1467 for (i = 0; i < 6; ++i)
1468 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1469
1470 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1471 if (!err) {
1472 u32 low, high;
1473
1474 value &= ~(1ULL << 2);
1475 low = lower_32_bits(value);
1476 high = upper_32_bits(value);
1477
1478 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1479 }
1480
1481 /* Flush tlb to evict multi-match entries */
1482 __flush_tlb_all();
1483
1484 return true;
1485}
1486
fe5913e4 1487static void svm_handle_mce(struct vcpu_svm *svm)
53371b50 1488{
67ec6607
JR		 1489 if (is_erratum_383()) {
1490 /*
1491 * Erratum 383 triggered. Guest state is corrupt so kill the
1492 * guest.
1493 */
1494 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1495
a8eeb04a 1496 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
67ec6607
JR		 1497
1498 return;
1499 }
1500
53371b50
JR		 1501 /*
1502 * On an #MC intercept the MCE handler is not called automatically in
1503 * the host. So do it by hand here.
1504 */
1505 asm volatile (
1506 "int $0x12\n");
1507 /* not sure if we ever come back to this point */
1508
fe5913e4
JR		 1509 return;
1510}
1511
1512static int mc_interception(struct vcpu_svm *svm)
1513{
53371b50
JR		 1514 return 1;
1515}
1516
851ba692 1517static int shutdown_interception(struct vcpu_svm *svm)
46fe4ddd 1518{
851ba692
AK		 1519 struct kvm_run *kvm_run = svm->vcpu.run;
1520
46fe4ddd
JR		 1521 /*
1522 * VMCB is undefined after a SHUTDOWN intercept
1523 * so reinitialize it.
1524 */
a2fa3e9f 1525 clear_page(svm->vmcb);
e6101a96 1526 init_vmcb(svm);
46fe4ddd
JR		 1527
1528 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1529 return 0;
1530}
1531
851ba692 1532static int io_interception(struct vcpu_svm *svm)
6aa8b732 1533{
cf8f70bf 1534 struct kvm_vcpu *vcpu = &svm->vcpu;
d77c26fc 1535 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
34c33d16 1536 int size, in, string;
039576c0 1537 unsigned port;
6aa8b732 1538
e756fc62 1539 ++svm->vcpu.stat.io_exits;
e70669ab 1540 string = (io_info & SVM_IOIO_STR_MASK) != 0;
039576c0 1541 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
cf8f70bf 1542 if (string || in)
6d77dbfc 1543 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
cf8f70bf 1544
039576c0
AK		 1545 port = io_info >> 16;
1546 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
cf8f70bf 1547 svm->next_rip = svm->vmcb->control.exit_info_2;
e93f36bc 1548 skip_emulated_instruction(&svm->vcpu);
cf8f70bf
GN		 1549
1550 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 1551}
1552
851ba692 1553static int nmi_interception(struct vcpu_svm *svm)
c47f098d
JR		 1554{
1555 return 1;
1556}
1557
851ba692 1558static int intr_interception(struct vcpu_svm *svm)
a0698055
JR		 1559{
1560 ++svm->vcpu.stat.irq_exits;
1561 return 1;
1562}
1563
851ba692 1564static int nop_on_interception(struct vcpu_svm *svm)
6aa8b732
AK		 1565{
1566 return 1;
1567}
1568
851ba692 1569static int halt_interception(struct vcpu_svm *svm)
6aa8b732 1570{
5fdbf976 1571 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
e756fc62
RR		 1572 skip_emulated_instruction(&svm->vcpu);
1573 return kvm_emulate_halt(&svm->vcpu);
6aa8b732
AK		 1574}
1575
851ba692 1576static int vmmcall_interception(struct vcpu_svm *svm)
02e235bc 1577{
5fdbf976 1578 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
e756fc62 1579 skip_emulated_instruction(&svm->vcpu);
7aa81cc0
AL		 1580 kvm_emulate_hypercall(&svm->vcpu);
1581 return 1;
02e235bc
AK		 1582}
1583
c0725420
AG		 1584static int nested_svm_check_permissions(struct vcpu_svm *svm)
1585{
f6801dff 1586 if (!(svm->vcpu.arch.efer & EFER_SVME)
c0725420
AG		 1587 || !is_paging(&svm->vcpu)) {
1588 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1589 return 1;
1590 }
1591
1592 if (svm->vmcb->save.cpl) {
1593 kvm_inject_gp(&svm->vcpu, 0);
1594 return 1;
1595 }
1596
1597 return 0;
1598}
1599
cf74a78b
AG		 1600static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1601 bool has_error_code, u32 error_code)
1602{
b8e88bc8
JR		 1603 int vmexit;
1604
0295ad7d
JR		 1605 if (!is_nested(svm))
1606 return 0;
cf74a78b 1607
0295ad7d
JR		 1608 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1609 svm->vmcb->control.exit_code_hi = 0;
1610 svm->vmcb->control.exit_info_1 = error_code;
1611 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1612
b8e88bc8
JR		 1613 vmexit = nested_svm_intercept(svm);
1614 if (vmexit == NESTED_EXIT_DONE)
1615 svm->nested.exit_required = true;
1616
1617 return vmexit;
cf74a78b
AG		 1618}
1619
8fe54654
JR		 1620/* This function returns true if it is save to enable the irq window */
1621static inline bool nested_svm_intr(struct vcpu_svm *svm)
cf74a78b 1622{
26666957 1623 if (!is_nested(svm))
8fe54654 1624 return true;
cf74a78b 1625
26666957 1626 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
8fe54654 1627 return true;
cf74a78b 1628
26666957 1629 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
8fe54654 1630 return false;
cf74a78b 1631
197717d5
JR		 1632 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1633 svm->vmcb->control.exit_info_1 = 0;
1634 svm->vmcb->control.exit_info_2 = 0;
26666957 1635
cd3ff653
JR		 1636 if (svm->nested.intercept & 1ULL) {
1637 /*
1638 * The #vmexit can't be emulated here directly because this
1639 * code path runs with irqs and preemtion disabled. A
1640 * #vmexit emulation might sleep. Only signal request for
1641 * the #vmexit here.
1642 */
1643 svm->nested.exit_required = true;
236649de 1644 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
8fe54654 1645 return false;
cf74a78b
AG		 1646 }
1647
8fe54654 1648 return true;
cf74a78b
AG		 1649}
1650
887f500c
JR		 1651/* This function returns true if it is save to enable the nmi window */
1652static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1653{
1654 if (!is_nested(svm))
1655 return true;
1656
1657 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1658 return true;
1659
1660 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1661 svm->nested.exit_required = true;
1662
1663 return false;
cf74a78b
AG		 1664}
1665
7597f129 1666static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
34f80cfa
JR		 1667{
1668 struct page *page;
1669
6c3bd3d7
JR		 1670 might_sleep();
1671
34f80cfa 1672 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
34f80cfa
JR		 1673 if (is_error_page(page))
1674 goto error;
1675
7597f129
JR		 1676 *_page = page;
1677
1678 return kmap(page);
34f80cfa
JR		 1679
1680error:
1681 kvm_release_page_clean(page);
1682 kvm_inject_gp(&svm->vcpu, 0);
1683
1684 return NULL;
1685}
1686
7597f129 1687static void nested_svm_unmap(struct page *page)
34f80cfa 1688{
7597f129 1689 kunmap(page);
34f80cfa
JR		 1690 kvm_release_page_dirty(page);
1691}
34f80cfa 1692
ce2ac085
JR		 1693static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1694{
1695 unsigned port;
1696 u8 val, bit;
1697 u64 gpa;
34f80cfa 1698
ce2ac085
JR		 1699 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1700 return NESTED_EXIT_HOST;
34f80cfa 1701
ce2ac085
JR		 1702 port = svm->vmcb->control.exit_info_1 >> 16;
1703 gpa = svm->nested.vmcb_iopm + (port / 8);
1704 bit = port % 8;
1705 val = 0;
1706
1707 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1708 val &= (1 << bit);
1709
1710 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
34f80cfa
JR		 1711}
1712
d2477826 1713static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
4c2161ae 1714{
0d6b3537
JR		 1715 u32 offset, msr, value;
1716 int write, mask;
4c2161ae 1717
3d62d9aa 1718 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
d2477826 1719 return NESTED_EXIT_HOST;
3d62d9aa 1720
0d6b3537
JR		 1721 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1722 offset = svm_msrpm_offset(msr);
1723 write = svm->vmcb->control.exit_info_1 & 1;
1724 mask = 1 << ((2 * (msr & 0xf)) + write);
3d62d9aa 1725
0d6b3537
JR		 1726 if (offset == MSR_INVALID)
1727 return NESTED_EXIT_DONE;
4c2161ae 1728
0d6b3537
JR		 1729 /* Offset is in 32 bit units but need in 8 bit units */
1730 offset *= 4;
4c2161ae 1731
0d6b3537
JR		 1732 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1733 return NESTED_EXIT_DONE;
3d62d9aa 1734
0d6b3537 1735 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
4c2161ae
JR		 1736}
1737
410e4d57 1738static int nested_svm_exit_special(struct vcpu_svm *svm)
cf74a78b 1739{
cf74a78b 1740 u32 exit_code = svm->vmcb->control.exit_code;
4c2161ae 1741
410e4d57
JR		 1742 switch (exit_code) {
1743 case SVM_EXIT_INTR:
1744 case SVM_EXIT_NMI:
ff47a49b 1745 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
410e4d57 1746 return NESTED_EXIT_HOST;
410e4d57 1747 case SVM_EXIT_NPF:
e0231715 1748 /* For now we are always handling NPFs when using them */
410e4d57
JR		 1749 if (npt_enabled)
1750 return NESTED_EXIT_HOST;
1751 break;
410e4d57 1752 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
e0231715 1753 /* When we're shadowing, trap PFs */
410e4d57
JR		 1754 if (!npt_enabled)
1755 return NESTED_EXIT_HOST;
1756 break;
66a562f7
JR		 1757 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1758 nm_interception(svm);
1759 break;
410e4d57
JR		 1760 default:
1761 break;
cf74a78b
AG		 1762 }
1763
410e4d57
JR		 1764 return NESTED_EXIT_CONTINUE;
1765}
1766
1767/*
1768 * If this function returns true, this #vmexit was already handled
1769 */
b8e88bc8 1770static int nested_svm_intercept(struct vcpu_svm *svm)
410e4d57
JR		 1771{
1772 u32 exit_code = svm->vmcb->control.exit_code;
1773 int vmexit = NESTED_EXIT_HOST;
1774
cf74a78b 1775 switch (exit_code) {
9c4e40b9 1776 case SVM_EXIT_MSR:
3d62d9aa 1777 vmexit = nested_svm_exit_handled_msr(svm);
9c4e40b9 1778 break;
ce2ac085
JR		 1779 case SVM_EXIT_IOIO:
1780 vmexit = nested_svm_intercept_ioio(svm);
1781 break;
cf74a78b
AG		 1782 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1783 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
aad42c64 1784 if (svm->nested.intercept_cr_read & cr_bits)
410e4d57 1785 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1786 break;
1787 }
1788 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1789 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
aad42c64 1790 if (svm->nested.intercept_cr_write & cr_bits)
410e4d57 1791 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1792 break;
1793 }
1794 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1795 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
aad42c64 1796 if (svm->nested.intercept_dr_read & dr_bits)
410e4d57 1797 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1798 break;
1799 }
1800 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1801 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
aad42c64 1802 if (svm->nested.intercept_dr_write & dr_bits)
410e4d57 1803 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1804 break;
1805 }
1806 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1807 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
aad42c64 1808 if (svm->nested.intercept_exceptions & excp_bits)
410e4d57 1809 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1810 break;
1811 }
228070b1
JR		 1812 case SVM_EXIT_ERR: {
1813 vmexit = NESTED_EXIT_DONE;
1814 break;
1815 }
cf74a78b
AG		 1816 default: {
1817 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
aad42c64 1818 if (svm->nested.intercept & exit_bits)
410e4d57 1819 vmexit = NESTED_EXIT_DONE;
cf74a78b
AG		 1820 }
1821 }
1822
b8e88bc8
JR		 1823 return vmexit;
1824}
1825
1826static int nested_svm_exit_handled(struct vcpu_svm *svm)
1827{
1828 int vmexit;
1829
1830 vmexit = nested_svm_intercept(svm);
1831
1832 if (vmexit == NESTED_EXIT_DONE)
9c4e40b9 1833 nested_svm_vmexit(svm);
9c4e40b9
JR		 1834
1835 return vmexit;
cf74a78b
AG		 1836}
1837
0460a979
JR		 1838static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1839{
1840 struct vmcb_control_area *dst = &dst_vmcb->control;
1841 struct vmcb_control_area *from = &from_vmcb->control;
1842
1843 dst->intercept_cr_read = from->intercept_cr_read;
1844 dst->intercept_cr_write = from->intercept_cr_write;
1845 dst->intercept_dr_read = from->intercept_dr_read;
1846 dst->intercept_dr_write = from->intercept_dr_write;
1847 dst->intercept_exceptions = from->intercept_exceptions;
1848 dst->intercept = from->intercept;
1849 dst->iopm_base_pa = from->iopm_base_pa;
1850 dst->msrpm_base_pa = from->msrpm_base_pa;
1851 dst->tsc_offset = from->tsc_offset;
1852 dst->asid = from->asid;
1853 dst->tlb_ctl = from->tlb_ctl;
1854 dst->int_ctl = from->int_ctl;
1855 dst->int_vector = from->int_vector;
1856 dst->int_state = from->int_state;
1857 dst->exit_code = from->exit_code;
1858 dst->exit_code_hi = from->exit_code_hi;
1859 dst->exit_info_1 = from->exit_info_1;
1860 dst->exit_info_2 = from->exit_info_2;
1861 dst->exit_int_info = from->exit_int_info;
1862 dst->exit_int_info_err = from->exit_int_info_err;
1863 dst->nested_ctl = from->nested_ctl;
1864 dst->event_inj = from->event_inj;
1865 dst->event_inj_err = from->event_inj_err;
1866 dst->nested_cr3 = from->nested_cr3;
1867 dst->lbr_ctl = from->lbr_ctl;
1868}
1869
34f80cfa 1870static int nested_svm_vmexit(struct vcpu_svm *svm)
cf74a78b 1871{
34f80cfa 1872 struct vmcb *nested_vmcb;
e6aa9abd 1873 struct vmcb *hsave = svm->nested.hsave;
33740e40 1874 struct vmcb *vmcb = svm->vmcb;
7597f129 1875 struct page *page;
cf74a78b 1876
17897f36
JR		 1877 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1878 vmcb->control.exit_info_1,
1879 vmcb->control.exit_info_2,
1880 vmcb->control.exit_int_info,
1881 vmcb->control.exit_int_info_err);
1882
7597f129 1883 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
34f80cfa
JR		 1884 if (!nested_vmcb)
1885 return 1;
1886
06fc7772
JR		 1887 /* Exit nested SVM mode */
1888 svm->nested.vmcb = 0;
1889
cf74a78b 1890 /* Give the current vmcb to the guest */
33740e40
JR		 1891 disable_gif(svm);
1892
1893 nested_vmcb->save.es = vmcb->save.es;
1894 nested_vmcb->save.cs = vmcb->save.cs;
1895 nested_vmcb->save.ss = vmcb->save.ss;
1896 nested_vmcb->save.ds = vmcb->save.ds;
1897 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1898 nested_vmcb->save.idtr = vmcb->save.idtr;
3f6a9d16 1899 nested_vmcb->save.efer = svm->vcpu.arch.efer;
cdbbdc12 1900 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2be4fc7a 1901 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
33740e40 1902 nested_vmcb->save.cr2 = vmcb->save.cr2;
cdbbdc12 1903 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
33740e40
JR		 1904 nested_vmcb->save.rflags = vmcb->save.rflags;
1905 nested_vmcb->save.rip = vmcb->save.rip;
1906 nested_vmcb->save.rsp = vmcb->save.rsp;
1907 nested_vmcb->save.rax = vmcb->save.rax;
1908 nested_vmcb->save.dr7 = vmcb->save.dr7;
1909 nested_vmcb->save.dr6 = vmcb->save.dr6;
1910 nested_vmcb->save.cpl = vmcb->save.cpl;
1911
1912 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1913 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1914 nested_vmcb->control.int_state = vmcb->control.int_state;
1915 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1916 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1917 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1918 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1919 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1920 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
7a190667 1921 nested_vmcb->control.next_rip = vmcb->control.next_rip;
8d23c466
AG		 1922
1923 /*
1924 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1925 * to make sure that we do not lose injected events. So check event_inj
1926 * here and copy it to exit_int_info if it is valid.
1927 * Exit_int_info and event_inj can't be both valid because the case
1928 * below only happens on a VMRUN instruction intercept which has
1929 * no valid exit_int_info set.
1930 */
1931 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1932 struct vmcb_control_area *nc = &nested_vmcb->control;
1933
1934 nc->exit_int_info = vmcb->control.event_inj;
1935 nc->exit_int_info_err = vmcb->control.event_inj_err;
1936 }
1937
33740e40
JR		 1938 nested_vmcb->control.tlb_ctl = 0;
1939 nested_vmcb->control.event_inj = 0;
1940 nested_vmcb->control.event_inj_err = 0;
cf74a78b
AG		 1941
1942 /* We always set V_INTR_MASKING and remember the old value in hflags */
1943 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1944 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1945
cf74a78b 1946 /* Restore the original control entries */
0460a979 1947 copy_vmcb_control_area(vmcb, hsave);
cf74a78b 1948
219b65dc
AG		 1949 kvm_clear_exception_queue(&svm->vcpu);
1950 kvm_clear_interrupt_queue(&svm->vcpu);
cf74a78b
AG		 1951
1952 /* Restore selected save entries */
1953 svm->vmcb->save.es = hsave->save.es;
1954 svm->vmcb->save.cs = hsave->save.cs;
1955 svm->vmcb->save.ss = hsave->save.ss;
1956 svm->vmcb->save.ds = hsave->save.ds;
1957 svm->vmcb->save.gdtr = hsave->save.gdtr;
1958 svm->vmcb->save.idtr = hsave->save.idtr;
1959 svm->vmcb->save.rflags = hsave->save.rflags;
1960 svm_set_efer(&svm->vcpu, hsave->save.efer);
1961 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1962 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1963 if (npt_enabled) {
1964 svm->vmcb->save.cr3 = hsave->save.cr3;
1965 svm->vcpu.arch.cr3 = hsave->save.cr3;
1966 } else {
2390218b 1967 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
cf74a78b
AG		 1968 }
1969 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1970 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1971 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1972 svm->vmcb->save.dr7 = 0;
1973 svm->vmcb->save.cpl = 0;
1974 svm->vmcb->control.exit_int_info = 0;
1975
7597f129 1976 nested_svm_unmap(page);
cf74a78b
AG		 1977
1978 kvm_mmu_reset_context(&svm->vcpu);
1979 kvm_mmu_load(&svm->vcpu);
1980
1981 return 0;
1982}
3d6368ef 1983
9738b2c9 1984static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
3d6368ef 1985{
323c3d80
JR		 1986 /*
1987 * This function merges the msr permission bitmaps of kvm and the
1988 * nested vmcb. It is omptimized in that it only merges the parts where
1989 * the kvm msr permission bitmap may contain zero bits
1990 */
3d6368ef 1991 int i;
9738b2c9 1992
323c3d80
JR		 1993 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1994 return true;
9738b2c9 1995
323c3d80
JR		 1996 for (i = 0; i < MSRPM_OFFSETS; i++) {
1997 u32 value, p;
1998 u64 offset;
9738b2c9 1999
323c3d80
JR		 2000 if (msrpm_offsets[i] == 0xffffffff)
2001 break;
3d6368ef 2002
0d6b3537
JR		 2003 p = msrpm_offsets[i];
2004 offset = svm->nested.vmcb_msrpm + (p * 4);
323c3d80
JR		 2005
2006 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2007 return false;
2008
2009 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2010 }
3d6368ef 2011
323c3d80 2012 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
9738b2c9
JR		 2013
2014 return true;
3d6368ef
AG		 2015}
2016
52c65a30
JR		 2017static bool nested_vmcb_checks(struct vmcb *vmcb)
2018{
2019 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2020 return false;
2021
dbe77584
JR		 2022 if (vmcb->control.asid == 0)
2023 return false;
2024
52c65a30
JR		 2025 return true;
2026}
2027
9738b2c9 2028static bool nested_svm_vmrun(struct vcpu_svm *svm)
3d6368ef 2029{
9738b2c9 2030 struct vmcb *nested_vmcb;
e6aa9abd 2031 struct vmcb *hsave = svm->nested.hsave;
defbba56 2032 struct vmcb *vmcb = svm->vmcb;
7597f129 2033 struct page *page;
06fc7772 2034 u64 vmcb_gpa;
3d6368ef 2035
06fc7772 2036 vmcb_gpa = svm->vmcb->save.rax;
3d6368ef 2037
7597f129 2038 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9738b2c9
JR		 2039 if (!nested_vmcb)
2040 return false;
2041
52c65a30
JR		 2042 if (!nested_vmcb_checks(nested_vmcb)) {
2043 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2044 nested_vmcb->control.exit_code_hi = 0;
2045 nested_vmcb->control.exit_info_1 = 0;
2046 nested_vmcb->control.exit_info_2 = 0;
2047
2048 nested_svm_unmap(page);
2049
2050 return false;
2051 }
2052
ecf1405d 2053 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
0ac406de
JR		 2054 nested_vmcb->save.rip,
2055 nested_vmcb->control.int_ctl,
2056 nested_vmcb->control.event_inj,
2057 nested_vmcb->control.nested_ctl);
2058
2e554e8d
JR		 2059 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2060 nested_vmcb->control.intercept_cr_write,
2061 nested_vmcb->control.intercept_exceptions,
2062 nested_vmcb->control.intercept);
2063
3d6368ef 2064 /* Clear internal status */
219b65dc
AG		 2065 kvm_clear_exception_queue(&svm->vcpu);
2066 kvm_clear_interrupt_queue(&svm->vcpu);
3d6368ef 2067
e0231715
JR		 2068 /*
2069 * Save the old vmcb, so we don't need to pick what we save, but can
2070 * restore everything when a VMEXIT occurs
2071 */
defbba56
JR		 2072 hsave->save.es = vmcb->save.es;
2073 hsave->save.cs = vmcb->save.cs;
2074 hsave->save.ss = vmcb->save.ss;
2075 hsave->save.ds = vmcb->save.ds;
2076 hsave->save.gdtr = vmcb->save.gdtr;
2077 hsave->save.idtr = vmcb->save.idtr;
f6801dff 2078 hsave->save.efer = svm->vcpu.arch.efer;
4d4ec087 2079 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
defbba56
JR		 2080 hsave->save.cr4 = svm->vcpu.arch.cr4;
2081 hsave->save.rflags = vmcb->save.rflags;
2082 hsave->save.rip = svm->next_rip;
2083 hsave->save.rsp = vmcb->save.rsp;
2084 hsave->save.rax = vmcb->save.rax;
2085 if (npt_enabled)
2086 hsave->save.cr3 = vmcb->save.cr3;
2087 else
2088 hsave->save.cr3 = svm->vcpu.arch.cr3;
2089
0460a979 2090 copy_vmcb_control_area(hsave, vmcb);
3d6368ef
AG		 2091
2092 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2093 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2094 else
2095 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2096
2097 /* Load the nested guest state */
2098 svm->vmcb->save.es = nested_vmcb->save.es;
2099 svm->vmcb->save.cs = nested_vmcb->save.cs;
2100 svm->vmcb->save.ss = nested_vmcb->save.ss;
2101 svm->vmcb->save.ds = nested_vmcb->save.ds;
2102 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2103 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2104 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2105 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2106 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2107 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2108 if (npt_enabled) {
2109 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2110 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
0e5cbe36 2111 } else
2390218b 2112 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
0e5cbe36
JR		 2113
2114 /* Guest paging mode is active - reset mmu */
2115 kvm_mmu_reset_context(&svm->vcpu);
2116
defbba56 2117 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3d6368ef
AG		 2118 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2119 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2120 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
e0231715 2121
3d6368ef
AG		 2122 /* In case we don't even reach vcpu_run, the fields are not updated */
2123 svm->vmcb->save.rax = nested_vmcb->save.rax;
2124 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2125 svm->vmcb->save.rip = nested_vmcb->save.rip;
2126 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2127 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2128 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2129
f7138538 2130 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
ce2ac085 2131 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3d6368ef 2132
aad42c64
JR		 2133 /* cache intercepts */
2134 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2135 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2136 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2137 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2138 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2139 svm->nested.intercept = nested_vmcb->control.intercept;
2140
3d6368ef 2141 force_new_asid(&svm->vcpu);
3d6368ef 2142 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3d6368ef
AG		 2143 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2144 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2145 else
2146 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2147
88ab24ad
JR		 2148 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2149 /* We only want the cr8 intercept bits of the guest */
2150 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2151 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2152 }
2153
0d945bd9
JR		 2154 /* We don't want to see VMMCALLs from a nested guest */
2155 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2156
e0231715
JR		 2157 /*
2158 * We don't want a nested guest to be more powerful than the guest, so
2159 * all intercepts are ORed
2160 */
88ab24ad
JR		 2161 svm->vmcb->control.intercept_cr_read |=
2162 nested_vmcb->control.intercept_cr_read;
2163 svm->vmcb->control.intercept_cr_write |=
2164 nested_vmcb->control.intercept_cr_write;
2165 svm->vmcb->control.intercept_dr_read |=
2166 nested_vmcb->control.intercept_dr_read;
2167 svm->vmcb->control.intercept_dr_write |=
2168 nested_vmcb->control.intercept_dr_write;
2169 svm->vmcb->control.intercept_exceptions |=
2170 nested_vmcb->control.intercept_exceptions;
2171
2172 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2173
2174 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
3d6368ef
AG		 2175 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2176 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2177 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3d6368ef
AG		 2178 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2179 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2180
7597f129 2181 nested_svm_unmap(page);
9738b2c9 2182
06fc7772
JR		 2183 /* nested_vmcb is our indicator if nested SVM is activated */
2184 svm->nested.vmcb = vmcb_gpa;
9738b2c9 2185
2af9194d 2186 enable_gif(svm);
3d6368ef 2187
9738b2c9 2188 return true;
3d6368ef
AG		 2189}
2190
9966bf68 2191static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
5542675b
AG		 2192{
2193 to_vmcb->save.fs = from_vmcb->save.fs;
2194 to_vmcb->save.gs = from_vmcb->save.gs;
2195 to_vmcb->save.tr = from_vmcb->save.tr;
2196 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2197 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2198 to_vmcb->save.star = from_vmcb->save.star;
2199 to_vmcb->save.lstar = from_vmcb->save.lstar;
2200 to_vmcb->save.cstar = from_vmcb->save.cstar;
2201 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2202 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2203 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2204 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
5542675b
AG		 2205}
2206
851ba692 2207static int vmload_interception(struct vcpu_svm *svm)
5542675b 2208{
9966bf68 2209 struct vmcb *nested_vmcb;
7597f129 2210 struct page *page;
9966bf68 2211
5542675b
AG		 2212 if (nested_svm_check_permissions(svm))
2213 return 1;
2214
2215 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2216 skip_emulated_instruction(&svm->vcpu);
2217
7597f129 2218 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2219 if (!nested_vmcb)
2220 return 1;
2221
2222 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
7597f129 2223 nested_svm_unmap(page);
5542675b
AG		 2224
2225 return 1;
2226}
2227
851ba692 2228static int vmsave_interception(struct vcpu_svm *svm)
5542675b 2229{
9966bf68 2230 struct vmcb *nested_vmcb;
7597f129 2231 struct page *page;
9966bf68 2232
5542675b
AG		 2233 if (nested_svm_check_permissions(svm))
2234 return 1;
2235
2236 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2237 skip_emulated_instruction(&svm->vcpu);
2238
7597f129 2239 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
9966bf68
JR		 2240 if (!nested_vmcb)
2241 return 1;
2242
2243 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
7597f129 2244 nested_svm_unmap(page);
5542675b
AG		 2245
2246 return 1;
2247}
2248
851ba692 2249static int vmrun_interception(struct vcpu_svm *svm)
3d6368ef 2250{
3d6368ef
AG		 2251 if (nested_svm_check_permissions(svm))
2252 return 1;
2253
2254 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2255 skip_emulated_instruction(&svm->vcpu);
2256
9738b2c9 2257 if (!nested_svm_vmrun(svm))
3d6368ef
AG		 2258 return 1;
2259
9738b2c9 2260 if (!nested_svm_vmrun_msrpm(svm))
1f8da478
JR		 2261 goto failed;
2262
2263 return 1;
2264
2265failed:
2266
2267 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2268 svm->vmcb->control.exit_code_hi = 0;
2269 svm->vmcb->control.exit_info_1 = 0;
2270 svm->vmcb->control.exit_info_2 = 0;
2271
2272 nested_svm_vmexit(svm);
3d6368ef
AG		 2273
2274 return 1;
2275}
2276
851ba692 2277static int stgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2278{
2279 if (nested_svm_check_permissions(svm))
2280 return 1;
2281
2282 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2283 skip_emulated_instruction(&svm->vcpu);
2284
2af9194d 2285 enable_gif(svm);
1371d904
AG		 2286
2287 return 1;
2288}
2289
851ba692 2290static int clgi_interception(struct vcpu_svm *svm)
1371d904
AG		 2291{
2292 if (nested_svm_check_permissions(svm))
2293 return 1;
2294
2295 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2296 skip_emulated_instruction(&svm->vcpu);
2297
2af9194d 2298 disable_gif(svm);
1371d904
AG		 2299
2300 /* After a CLGI no interrupts should come */
2301 svm_clear_vintr(svm);
2302 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2303
2304 return 1;
2305}
2306
851ba692 2307static int invlpga_interception(struct vcpu_svm *svm)
ff092385
AG		 2308{
2309 struct kvm_vcpu *vcpu = &svm->vcpu;
ff092385 2310
ec1ff790
JR		 2311 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2312 vcpu->arch.regs[VCPU_REGS_RAX]);
2313
ff092385
AG		 2314 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2315 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2316
2317 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2318 skip_emulated_instruction(&svm->vcpu);
2319 return 1;
2320}
2321
532a46b9
JR		 2322static int skinit_interception(struct vcpu_svm *svm)
2323{
2324 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2325
2326 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2327 return 1;
2328}
2329
851ba692 2330static int invalid_op_interception(struct vcpu_svm *svm)
6aa8b732 2331{
7ee5d940 2332 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
6aa8b732
AK		 2333 return 1;
2334}
2335
851ba692 2336static int task_switch_interception(struct vcpu_svm *svm)
6aa8b732 2337{
37817f29 2338 u16 tss_selector;
64a7ec06
GN		 2339 int reason;
2340 int int_type = svm->vmcb->control.exit_int_info &
2341 SVM_EXITINTINFO_TYPE_MASK;
8317c298 2342 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
fe8e7f83
GN		 2343 uint32_t type =
2344 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2345 uint32_t idt_v =
2346 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
e269fb21
JK		 2347 bool has_error_code = false;
2348 u32 error_code = 0;
37817f29
IE		 2349
2350 tss_selector = (u16)svm->vmcb->control.exit_info_1;
64a7ec06 2351
37817f29
IE		 2352 if (svm->vmcb->control.exit_info_2 &
2353 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
64a7ec06
GN		 2354 reason = TASK_SWITCH_IRET;
2355 else if (svm->vmcb->control.exit_info_2 &
2356 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2357 reason = TASK_SWITCH_JMP;
fe8e7f83 2358 else if (idt_v)
64a7ec06
GN		 2359 reason = TASK_SWITCH_GATE;
2360 else
2361 reason = TASK_SWITCH_CALL;
2362
fe8e7f83
GN		 2363 if (reason == TASK_SWITCH_GATE) {
2364 switch (type) {
2365 case SVM_EXITINTINFO_TYPE_NMI:
2366 svm->vcpu.arch.nmi_injected = false;
2367 break;
2368 case SVM_EXITINTINFO_TYPE_EXEPT:
e269fb21
JK		 2369 if (svm->vmcb->control.exit_info_2 &
2370 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2371 has_error_code = true;
2372 error_code =
2373 (u32)svm->vmcb->control.exit_info_2;
2374 }
fe8e7f83
GN		 2375 kvm_clear_exception_queue(&svm->vcpu);
2376 break;
2377 case SVM_EXITINTINFO_TYPE_INTR:
2378 kvm_clear_interrupt_queue(&svm->vcpu);
2379 break;
2380 default:
2381 break;
2382 }
2383 }
64a7ec06 2384
8317c298
GN		 2385 if (reason != TASK_SWITCH_GATE ||
2386 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2387 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
f629cf84
GN		 2388 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2389 skip_emulated_instruction(&svm->vcpu);
64a7ec06 2390
acb54517
GN		 2391 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2392 has_error_code, error_code) == EMULATE_FAIL) {
2393 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2394 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2395 svm->vcpu.run->internal.ndata = 0;
2396 return 0;
2397 }
2398 return 1;
6aa8b732
AK		 2399}
2400
851ba692 2401static int cpuid_interception(struct vcpu_svm *svm)
6aa8b732 2402{
5fdbf976 2403 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2404 kvm_emulate_cpuid(&svm->vcpu);
06465c5a 2405 return 1;
6aa8b732
AK		 2406}
2407
851ba692 2408static int iret_interception(struct vcpu_svm *svm)
95ba8273
GN		 2409{
2410 ++svm->vcpu.stat.nmi_window_exits;
061e2fd1 2411 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
44c11430 2412 svm->vcpu.arch.hflags |= HF_IRET_MASK;
95ba8273
GN		 2413 return 1;
2414}
2415
851ba692 2416static int invlpg_interception(struct vcpu_svm *svm)
a7052897 2417{
6d77dbfc 2418 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
a7052897
MT		 2419}
2420
851ba692 2421static int emulate_on_interception(struct vcpu_svm *svm)
6aa8b732 2422{
6d77dbfc 2423 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
6aa8b732
AK		 2424}
2425
851ba692 2426static int cr8_write_interception(struct vcpu_svm *svm)
1d075434 2427{
851ba692
AK		 2428 struct kvm_run *kvm_run = svm->vcpu.run;
2429
0a5fff19
GN		 2430 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2431 /* instruction emulation calls kvm_set_cr8() */
851ba692 2432 emulate_instruction(&svm->vcpu, 0, 0, 0);
95ba8273
GN		 2433 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2434 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1d075434 2435 return 1;
95ba8273 2436 }
0a5fff19
GN		 2437 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2438 return 1;
1d075434
JR		 2439 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2440 return 0;
2441}
2442
6aa8b732
AK		 2443static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2444{
a2fa3e9f
GH		 2445 struct vcpu_svm *svm = to_svm(vcpu);
2446
6aa8b732 2447 switch (ecx) {
af24a4e4 2448 case MSR_IA32_TSC: {
20824f30 2449 u64 tsc_offset;
6aa8b732 2450
20824f30
JR		 2451 if (is_nested(svm))
2452 tsc_offset = svm->nested.hsave->control.tsc_offset;
2453 else
2454 tsc_offset = svm->vmcb->control.tsc_offset;
2455
2456 *data = tsc_offset + native_read_tsc();
6aa8b732
AK		 2457 break;
2458 }
8c06585d 2459 case MSR_STAR:
a2fa3e9f 2460 *data = svm->vmcb->save.star;
6aa8b732 2461 break;
0e859cac 2462#ifdef CONFIG_X86_64
6aa8b732 2463 case MSR_LSTAR:
a2fa3e9f 2464 *data = svm->vmcb->save.lstar;
6aa8b732
AK		 2465 break;
2466 case MSR_CSTAR:
a2fa3e9f 2467 *data = svm->vmcb->save.cstar;
6aa8b732
AK		 2468 break;
2469 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2470 *data = svm->vmcb->save.kernel_gs_base;
6aa8b732
AK		 2471 break;
2472 case MSR_SYSCALL_MASK:
a2fa3e9f 2473 *data = svm->vmcb->save.sfmask;
6aa8b732
AK		 2474 break;
2475#endif
2476 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2477 *data = svm->vmcb->save.sysenter_cs;
6aa8b732
AK		 2478 break;
2479 case MSR_IA32_SYSENTER_EIP:
017cb99e 2480 *data = svm->sysenter_eip;
6aa8b732
AK		 2481 break;
2482 case MSR_IA32_SYSENTER_ESP:
017cb99e 2483 *data = svm->sysenter_esp;
6aa8b732 2484 break;
e0231715
JR		 2485 /*
2486 * Nobody will change the following 5 values in the VMCB so we can
2487 * safely return them on rdmsr. They will always be 0 until LBRV is
2488 * implemented.
2489 */
a2938c80
JR		 2490 case MSR_IA32_DEBUGCTLMSR:
2491 *data = svm->vmcb->save.dbgctl;
2492 break;
2493 case MSR_IA32_LASTBRANCHFROMIP:
2494 *data = svm->vmcb->save.br_from;
2495 break;
2496 case MSR_IA32_LASTBRANCHTOIP:
2497 *data = svm->vmcb->save.br_to;
2498 break;
2499 case MSR_IA32_LASTINTFROMIP:
2500 *data = svm->vmcb->save.last_excp_from;
2501 break;
2502 case MSR_IA32_LASTINTTOIP:
2503 *data = svm->vmcb->save.last_excp_to;
2504 break;
b286d5d8 2505 case MSR_VM_HSAVE_PA:
e6aa9abd 2506 *data = svm->nested.hsave_msr;
b286d5d8 2507 break;
eb6f302e 2508 case MSR_VM_CR:
4a810181 2509 *data = svm->nested.vm_cr_msr;
eb6f302e 2510 break;
c8a73f18
AG		 2511 case MSR_IA32_UCODE_REV:
2512 *data = 0x01000065;
2513 break;
6aa8b732 2514 default:
3bab1f5d 2515 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2516 }
2517 return 0;
2518}
2519
851ba692 2520static int rdmsr_interception(struct vcpu_svm *svm)
6aa8b732 2521{
ad312c7c 2522 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2523 u64 data;
2524
59200273
AK		 2525 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2526 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 2527 kvm_inject_gp(&svm->vcpu, 0);
59200273 2528 } else {
229456fc 2529 trace_kvm_msr_read(ecx, data);
af9ca2d7 2530
5fdbf976 2531 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
ad312c7c 2532 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
5fdbf976 2533 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
e756fc62 2534 skip_emulated_instruction(&svm->vcpu);
6aa8b732
AK		 2535 }
2536 return 1;
2537}
2538
4a810181
JR		 2539static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2540{
2541 struct vcpu_svm *svm = to_svm(vcpu);
2542 int svm_dis, chg_mask;
2543
2544 if (data & ~SVM_VM_CR_VALID_MASK)
2545 return 1;
2546
2547 chg_mask = SVM_VM_CR_VALID_MASK;
2548
2549 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2550 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2551
2552 svm->nested.vm_cr_msr &= ~chg_mask;
2553 svm->nested.vm_cr_msr |= (data & chg_mask);
2554
2555 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2556
2557 /* check for svm_disable while efer.svme is set */
2558 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2559 return 1;
2560
2561 return 0;
2562}
2563
6aa8b732
AK		 2564static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2565{
a2fa3e9f
GH		 2566 struct vcpu_svm *svm = to_svm(vcpu);
2567
6aa8b732 2568 switch (ecx) {
af24a4e4 2569 case MSR_IA32_TSC: {
20824f30
JR		 2570 u64 tsc_offset = data - native_read_tsc();
2571 u64 g_tsc_offset = 0;
2572
2573 if (is_nested(svm)) {
2574 g_tsc_offset = svm->vmcb->control.tsc_offset -
2575 svm->nested.hsave->control.tsc_offset;
2576 svm->nested.hsave->control.tsc_offset = tsc_offset;
2577 }
2578
2579 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
6aa8b732 2580
6aa8b732
AK		 2581 break;
2582 }
8c06585d 2583 case MSR_STAR:
a2fa3e9f 2584 svm->vmcb->save.star = data;
6aa8b732 2585 break;
49b14f24 2586#ifdef CONFIG_X86_64
6aa8b732 2587 case MSR_LSTAR:
a2fa3e9f 2588 svm->vmcb->save.lstar = data;
6aa8b732
AK		 2589 break;
2590 case MSR_CSTAR:
a2fa3e9f 2591 svm->vmcb->save.cstar = data;
6aa8b732
AK		 2592 break;
2593 case MSR_KERNEL_GS_BASE:
a2fa3e9f 2594 svm->vmcb->save.kernel_gs_base = data;
6aa8b732
AK		 2595 break;
2596 case MSR_SYSCALL_MASK:
a2fa3e9f 2597 svm->vmcb->save.sfmask = data;
6aa8b732
AK		 2598 break;
2599#endif
2600 case MSR_IA32_SYSENTER_CS:
a2fa3e9f 2601 svm->vmcb->save.sysenter_cs = data;
6aa8b732
AK		 2602 break;
2603 case MSR_IA32_SYSENTER_EIP:
017cb99e 2604 svm->sysenter_eip = data;
a2fa3e9f 2605 svm->vmcb->save.sysenter_eip = data;
6aa8b732
AK		 2606 break;
2607 case MSR_IA32_SYSENTER_ESP:
017cb99e 2608 svm->sysenter_esp = data;
a2fa3e9f 2609 svm->vmcb->save.sysenter_esp = data;
6aa8b732 2610 break;
a2938c80 2611 case MSR_IA32_DEBUGCTLMSR:
24e09cbf
JR		 2612 if (!svm_has(SVM_FEATURE_LBRV)) {
2613 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
b8688d51 2614 __func__, data);
24e09cbf
JR		 2615 break;
2616 }
2617 if (data & DEBUGCTL_RESERVED_BITS)
2618 return 1;
2619
2620 svm->vmcb->save.dbgctl = data;
2621 if (data & (1ULL<<0))
2622 svm_enable_lbrv(svm);
2623 else
2624 svm_disable_lbrv(svm);
a2938c80 2625 break;
b286d5d8 2626 case MSR_VM_HSAVE_PA:
e6aa9abd 2627 svm->nested.hsave_msr = data;
62b9abaa 2628 break;
3c5d0a44 2629 case MSR_VM_CR:
4a810181 2630 return svm_set_vm_cr(vcpu, data);
3c5d0a44 2631 case MSR_VM_IGNNE:
3c5d0a44
AG		 2632 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2633 break;
6aa8b732 2634 default:
3bab1f5d 2635 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 2636 }
2637 return 0;
2638}
2639
851ba692 2640static int wrmsr_interception(struct vcpu_svm *svm)
6aa8b732 2641{
ad312c7c 2642 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
5fdbf976 2643 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
ad312c7c 2644 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
af9ca2d7 2645
af9ca2d7 2646
5fdbf976 2647 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
59200273
AK		 2648 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2649 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 2650 kvm_inject_gp(&svm->vcpu, 0);
59200273
AK		 2651 } else {
2652 trace_kvm_msr_write(ecx, data);
e756fc62 2653 skip_emulated_instruction(&svm->vcpu);
59200273 2654 }
6aa8b732
AK		 2655 return 1;
2656}
2657
851ba692 2658static int msr_interception(struct vcpu_svm *svm)
6aa8b732 2659{
e756fc62 2660 if (svm->vmcb->control.exit_info_1)
851ba692 2661 return wrmsr_interception(svm);
6aa8b732 2662 else
851ba692 2663 return rdmsr_interception(svm);
6aa8b732
AK		 2664}
2665
851ba692 2666static int interrupt_window_interception(struct vcpu_svm *svm)
c1150d8c 2667{
851ba692
AK		 2668 struct kvm_run *kvm_run = svm->vcpu.run;
2669
f0b85051 2670 svm_clear_vintr(svm);
85f455f7 2671 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
c1150d8c
DL		 2672 /*
2673 * If the user space waits to inject interrupts, exit as soon as
2674 * possible
2675 */
8061823a
GN		 2676 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2677 kvm_run->request_interrupt_window &&
2678 !kvm_cpu_has_interrupt(&svm->vcpu)) {
e756fc62 2679 ++svm->vcpu.stat.irq_window_exits;
c1150d8c
DL		 2680 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2681 return 0;
2682 }
2683
2684 return 1;
2685}
2686
565d0998
ML		 2687static int pause_interception(struct vcpu_svm *svm)
2688{
2689 kvm_vcpu_on_spin(&(svm->vcpu));
2690 return 1;
2691}
2692
851ba692 2693static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
e0231715
JR		 2694 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2695 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2696 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2697 [SVM_EXIT_READ_CR8] = emulate_on_interception,
d225157b 2698 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
e0231715
JR		 2699 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2700 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2701 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2702 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2703 [SVM_EXIT_READ_DR0] = emulate_on_interception,
6aa8b732
AK		 2704 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2705 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2706 [SVM_EXIT_READ_DR3] = emulate_on_interception,
727f5a23
JK		 2707 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2708 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2709 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2710 [SVM_EXIT_READ_DR7] = emulate_on_interception,
6aa8b732
AK		 2711 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2712 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2713 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2714 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
727f5a23 2715 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
6aa8b732 2716 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
727f5a23 2717 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
6aa8b732 2718 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
d0bfb940
JK		 2719 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2720 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
7aa81cc0 2721 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
e0231715
JR		 2722 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2723 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2724 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2725 [SVM_EXIT_INTR] = intr_interception,
c47f098d 2726 [SVM_EXIT_NMI] = nmi_interception,
6aa8b732
AK		 2727 [SVM_EXIT_SMI] = nop_on_interception,
2728 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 2729 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732 2730 [SVM_EXIT_CPUID] = cpuid_interception,
95ba8273 2731 [SVM_EXIT_IRET] = iret_interception,
cf5a94d1 2732 [SVM_EXIT_INVD] = emulate_on_interception,
565d0998 2733 [SVM_EXIT_PAUSE] = pause_interception,
6aa8b732 2734 [SVM_EXIT_HLT] = halt_interception,
a7052897 2735 [SVM_EXIT_INVLPG] = invlpg_interception,
ff092385 2736 [SVM_EXIT_INVLPGA] = invlpga_interception,
e0231715 2737 [SVM_EXIT_IOIO] = io_interception,
6aa8b732
AK		 2738 [SVM_EXIT_MSR] = msr_interception,
2739 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 2740 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3d6368ef 2741 [SVM_EXIT_VMRUN] = vmrun_interception,
02e235bc 2742 [SVM_EXIT_VMMCALL] = vmmcall_interception,
5542675b
AG		 2743 [SVM_EXIT_VMLOAD] = vmload_interception,
2744 [SVM_EXIT_VMSAVE] = vmsave_interception,
1371d904
AG		 2745 [SVM_EXIT_STGI] = stgi_interception,
2746 [SVM_EXIT_CLGI] = clgi_interception,
532a46b9 2747 [SVM_EXIT_SKINIT] = skinit_interception,
cf5a94d1 2748 [SVM_EXIT_WBINVD] = emulate_on_interception,
916ce236
JR		 2749 [SVM_EXIT_MONITOR] = invalid_op_interception,
2750 [SVM_EXIT_MWAIT] = invalid_op_interception,
709ddebf 2751 [SVM_EXIT_NPF] = pf_interception,
6aa8b732
AK		 2752};
2753
3f10c846
JR		 2754void dump_vmcb(struct kvm_vcpu *vcpu)
2755{
2756 struct vcpu_svm *svm = to_svm(vcpu);
2757 struct vmcb_control_area *control = &svm->vmcb->control;
2758 struct vmcb_save_area *save = &svm->vmcb->save;
2759
2760 pr_err("VMCB Control Area:\n");
2761 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2762 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2763 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2764 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2765 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2766 pr_err("intercepts: %016llx\n", control->intercept);
2767 pr_err("pause filter count: %d\n", control->pause_filter_count);
2768 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2769 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2770 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2771 pr_err("asid: %d\n", control->asid);
2772 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2773 pr_err("int_ctl: %08x\n", control->int_ctl);
2774 pr_err("int_vector: %08x\n", control->int_vector);
2775 pr_err("int_state: %08x\n", control->int_state);
2776 pr_err("exit_code: %08x\n", control->exit_code);
2777 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2778 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2779 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2780 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2781 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2782 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2783 pr_err("event_inj: %08x\n", control->event_inj);
2784 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2785 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2786 pr_err("next_rip: %016llx\n", control->next_rip);
2787 pr_err("VMCB State Save Area:\n");
2788 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2789 save->es.selector, save->es.attrib,
2790 save->es.limit, save->es.base);
2791 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2792 save->cs.selector, save->cs.attrib,
2793 save->cs.limit, save->cs.base);
2794 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2795 save->ss.selector, save->ss.attrib,
2796 save->ss.limit, save->ss.base);
2797 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2798 save->ds.selector, save->ds.attrib,
2799 save->ds.limit, save->ds.base);
2800 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2801 save->fs.selector, save->fs.attrib,
2802 save->fs.limit, save->fs.base);
2803 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2804 save->gs.selector, save->gs.attrib,
2805 save->gs.limit, save->gs.base);
2806 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2807 save->gdtr.selector, save->gdtr.attrib,
2808 save->gdtr.limit, save->gdtr.base);
2809 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2810 save->ldtr.selector, save->ldtr.attrib,
2811 save->ldtr.limit, save->ldtr.base);
2812 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2813 save->idtr.selector, save->idtr.attrib,
2814 save->idtr.limit, save->idtr.base);
2815 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2816 save->tr.selector, save->tr.attrib,
2817 save->tr.limit, save->tr.base);
2818 pr_err("cpl: %d efer: %016llx\n",
2819 save->cpl, save->efer);
2820 pr_err("cr0: %016llx cr2: %016llx\n",
2821 save->cr0, save->cr2);
2822 pr_err("cr3: %016llx cr4: %016llx\n",
2823 save->cr3, save->cr4);
2824 pr_err("dr6: %016llx dr7: %016llx\n",
2825 save->dr6, save->dr7);
2826 pr_err("rip: %016llx rflags: %016llx\n",
2827 save->rip, save->rflags);
2828 pr_err("rsp: %016llx rax: %016llx\n",
2829 save->rsp, save->rax);
2830 pr_err("star: %016llx lstar: %016llx\n",
2831 save->star, save->lstar);
2832 pr_err("cstar: %016llx sfmask: %016llx\n",
2833 save->cstar, save->sfmask);
2834 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2835 save->kernel_gs_base, save->sysenter_cs);
2836 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2837 save->sysenter_esp, save->sysenter_eip);
2838 pr_err("gpat: %016llx dbgctl: %016llx\n",
2839 save->g_pat, save->dbgctl);
2840 pr_err("br_from: %016llx br_to: %016llx\n",
2841 save->br_from, save->br_to);
2842 pr_err("excp_from: %016llx excp_to: %016llx\n",
2843 save->last_excp_from, save->last_excp_to);
2844
2845}
2846
851ba692 2847static int handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 2848{
04d2cc77 2849 struct vcpu_svm *svm = to_svm(vcpu);
851ba692 2850 struct kvm_run *kvm_run = vcpu->run;
a2fa3e9f 2851 u32 exit_code = svm->vmcb->control.exit_code;
6aa8b732 2852
5bfd8b54 2853 trace_kvm_exit(exit_code, vcpu);
af9ca2d7 2854
2be4fc7a
JR		 2855 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2856 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2857 if (npt_enabled)
2858 vcpu->arch.cr3 = svm->vmcb->save.cr3;
af9ca2d7 2859
cd3ff653
JR		 2860 if (unlikely(svm->nested.exit_required)) {
2861 nested_svm_vmexit(svm);
2862 svm->nested.exit_required = false;
2863
2864 return 1;
2865 }
2866
cf74a78b 2867 if (is_nested(svm)) {
410e4d57
JR		 2868 int vmexit;
2869
d8cabddf
JR		 2870 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2871 svm->vmcb->control.exit_info_1,
2872 svm->vmcb->control.exit_info_2,
2873 svm->vmcb->control.exit_int_info,
2874 svm->vmcb->control.exit_int_info_err);
2875
410e4d57
JR		 2876 vmexit = nested_svm_exit_special(svm);
2877
2878 if (vmexit == NESTED_EXIT_CONTINUE)
2879 vmexit = nested_svm_exit_handled(svm);
2880
2881 if (vmexit == NESTED_EXIT_DONE)
cf74a78b 2882 return 1;
cf74a78b
AG		 2883 }
2884
a5c3832d
JR		 2885 svm_complete_interrupts(svm);
2886
04d2cc77
AK		 2887 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2888 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2889 kvm_run->fail_entry.hardware_entry_failure_reason
2890 = svm->vmcb->control.exit_code;
3f10c846
JR		 2891 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2892 dump_vmcb(vcpu);
04d2cc77
AK		 2893 return 0;
2894 }
2895
a2fa3e9f 2896 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
709ddebf 2897 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
fe8e7f83 2898 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
6aa8b732
AK		 2899 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2900 "exit_code 0x%x\n",
b8688d51 2901 __func__, svm->vmcb->control.exit_int_info,
6aa8b732
AK		 2902 exit_code);
2903
9d8f549d 2904 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
56919c5c 2905 || !svm_exit_handlers[exit_code]) {
6aa8b732 2906 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 2907 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 2908 return 0;
2909 }
2910
851ba692 2911 return svm_exit_handlers[exit_code](svm);
6aa8b732
AK		 2912}
2913
2914static void reload_tss(struct kvm_vcpu *vcpu)
2915{
2916 int cpu = raw_smp_processor_id();
2917
0fe1e009
TH		 2918 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2919 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
6aa8b732
AK		 2920 load_TR_desc();
2921}
2922
e756fc62 2923static void pre_svm_run(struct vcpu_svm *svm)
6aa8b732
AK		 2924{
2925 int cpu = raw_smp_processor_id();
2926
0fe1e009 2927 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
6aa8b732 2928
a2fa3e9f 2929 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4b656b12 2930 /* FIXME: handle wraparound of asid_generation */
0fe1e009
TH		 2931 if (svm->asid_generation != sd->asid_generation)
2932 new_asid(svm, sd);
6aa8b732
AK		 2933}
2934
95ba8273
GN		 2935static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2936{
2937 struct vcpu_svm *svm = to_svm(vcpu);
2938
2939 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2940 vcpu->arch.hflags |= HF_NMI_MASK;
061e2fd1 2941 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
95ba8273
GN		 2942 ++vcpu->stat.nmi_injections;
2943}
6aa8b732 2944
85f455f7 2945static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
6aa8b732
AK		 2946{
2947 struct vmcb_control_area *control;
2948
e756fc62 2949 control = &svm->vmcb->control;
85f455f7 2950 control->int_vector = irq;
6aa8b732
AK		 2951 control->int_ctl &= ~V_INTR_PRIO_MASK;
2952 control->int_ctl |= V_IRQ_MASK |
2953 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2954}
2955
66fd3f7f 2956static void svm_set_irq(struct kvm_vcpu *vcpu)
2a8067f1
ED		 2957{
2958 struct vcpu_svm *svm = to_svm(vcpu);
2959
2af9194d 2960 BUG_ON(!(gif_set(svm)));
cf74a78b 2961
9fb2d2b4
GN		 2962 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
2963 ++vcpu->stat.irq_injections;
2964
219b65dc
AG		 2965 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2966 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2a8067f1
ED		 2967}
2968
95ba8273 2969static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
aaacfc9a
JR		 2970{
2971 struct vcpu_svm *svm = to_svm(vcpu);
aaacfc9a 2972
88ab24ad
JR		 2973 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2974 return;
2975
95ba8273 2976 if (irr == -1)
aaacfc9a
JR		 2977 return;
2978
95ba8273
GN		 2979 if (tpr >= irr)
2980 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2981}
aaacfc9a 2982
95ba8273
GN		 2983static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2984{
2985 struct vcpu_svm *svm = to_svm(vcpu);
2986 struct vmcb *vmcb = svm->vmcb;
924584cc
JR		 2987 int ret;
2988 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2989 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2990 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2991
2992 return ret;
aaacfc9a
JR		 2993}
2994
3cfc3092
JK		 2995static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2996{
2997 struct vcpu_svm *svm = to_svm(vcpu);
2998
2999 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3000}
3001
3002static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3003{
3004 struct vcpu_svm *svm = to_svm(vcpu);
3005
3006 if (masked) {
3007 svm->vcpu.arch.hflags |= HF_NMI_MASK;
061e2fd1 3008 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3009 } else {
3010 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
061e2fd1 3011 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3cfc3092
JK		 3012 }
3013}
3014
78646121
GN		 3015static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3016{
3017 struct vcpu_svm *svm = to_svm(vcpu);
3018 struct vmcb *vmcb = svm->vmcb;
7fcdb510
JR		 3019 int ret;
3020
3021 if (!gif_set(svm) ||
3022 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3023 return 0;
3024
3025 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3026
3027 if (is_nested(svm))
3028 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3029
3030 return ret;
78646121
GN		 3031}
3032
9222be18 3033static void enable_irq_window(struct kvm_vcpu *vcpu)
6aa8b732 3034{
219b65dc 3035 struct vcpu_svm *svm = to_svm(vcpu);
219b65dc 3036
e0231715
JR		 3037 /*
3038 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3039 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3040 * get that intercept, this function will be called again though and
3041 * we'll get the vintr intercept.
3042 */
8fe54654 3043 if (gif_set(svm) && nested_svm_intr(svm)) {
219b65dc
AG		 3044 svm_set_vintr(svm);
3045 svm_inject_irq(svm, 0x0);
3046 }
85f455f7
ED		 3047}
3048
95ba8273 3049static void enable_nmi_window(struct kvm_vcpu *vcpu)
c1150d8c 3050{
04d2cc77 3051 struct vcpu_svm *svm = to_svm(vcpu);
c1150d8c 3052
44c11430
GN		 3053 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3054 == HF_NMI_MASK)
3055 return; /* IRET will cause a vm exit */
3056
e0231715
JR		 3057 /*
3058 * Something prevents NMI from been injected. Single step over possible
3059 * problem (IRET or exception injection or interrupt shadow)
3060 */
6be7d306 3061 svm->nmi_singlestep = true;
44c11430
GN		 3062 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3063 update_db_intercept(vcpu);
c1150d8c
DL		 3064}
3065
cbc94022
IE		 3066static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3067{
3068 return 0;
3069}
3070
d9e368d6
AK		 3071static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3072{
3073 force_new_asid(vcpu);
3074}
3075
04d2cc77
AK		 3076static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3077{
3078}
3079
d7bf8221
JR		 3080static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3081{
3082 struct vcpu_svm *svm = to_svm(vcpu);
3083
88ab24ad
JR		 3084 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3085 return;
3086
d7bf8221
JR		 3087 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3088 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
615d5193 3089 kvm_set_cr8(vcpu, cr8);
d7bf8221
JR		 3090 }
3091}
3092
649d6864
JR		 3093static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3094{
3095 struct vcpu_svm *svm = to_svm(vcpu);
3096 u64 cr8;
3097
88ab24ad
JR		 3098 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3099 return;
3100
649d6864
JR		 3101 cr8 = kvm_get_cr8(vcpu);
3102 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3103 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3104}
3105
9222be18
GN		 3106static void svm_complete_interrupts(struct vcpu_svm *svm)
3107{
3108 u8 vector;
3109 int type;
3110 u32 exitintinfo = svm->vmcb->control.exit_int_info;
66b7138f
JK		 3111 unsigned int3_injected = svm->int3_injected;
3112
3113 svm->int3_injected = 0;
9222be18 3114
44c11430
GN		 3115 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3116 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3117
9222be18
GN		 3118 svm->vcpu.arch.nmi_injected = false;
3119 kvm_clear_exception_queue(&svm->vcpu);
3120 kvm_clear_interrupt_queue(&svm->vcpu);
3121
3122 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3123 return;
3124
3125 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3126 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3127
3128 switch (type) {
3129 case SVM_EXITINTINFO_TYPE_NMI:
3130 svm->vcpu.arch.nmi_injected = true;
3131 break;
3132 case SVM_EXITINTINFO_TYPE_EXEPT:
66b7138f
JK		 3133 /*
3134 * In case of software exceptions, do not reinject the vector,
3135 * but re-execute the instruction instead. Rewind RIP first
3136 * if we emulated INT3 before.
3137 */
3138 if (kvm_exception_is_soft(vector)) {
3139 if (vector == BP_VECTOR && int3_injected &&
3140 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3141 kvm_rip_write(&svm->vcpu,
3142 kvm_rip_read(&svm->vcpu) -
3143 int3_injected);
9222be18 3144 break;
66b7138f 3145 }
9222be18
GN		 3146 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3147 u32 err = svm->vmcb->control.exit_int_info_err;
ce7ddec4 3148 kvm_requeue_exception_e(&svm->vcpu, vector, err);
9222be18
GN		 3149
3150 } else
ce7ddec4 3151 kvm_requeue_exception(&svm->vcpu, vector);
9222be18
GN		 3152 break;
3153 case SVM_EXITINTINFO_TYPE_INTR:
66fd3f7f 3154 kvm_queue_interrupt(&svm->vcpu, vector, false);
9222be18
GN		 3155 break;
3156 default:
3157 break;
3158 }
3159}
3160
80e31d4f
AK		 3161#ifdef CONFIG_X86_64
3162#define R "r"
3163#else
3164#define R "e"
3165#endif
3166
851ba692 3167static void svm_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3168{
a2fa3e9f 3169 struct vcpu_svm *svm = to_svm(vcpu);
6aa8b732
AK		 3170 u16 fs_selector;
3171 u16 gs_selector;
3172 u16 ldt_selector;
d9e368d6 3173
2041a06a
JR		 3174 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3175 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3176 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3177
cd3ff653
JR		 3178 /*
3179 * A vmexit emulation is required before the vcpu can be executed
3180 * again.
3181 */
3182 if (unlikely(svm->nested.exit_required))
3183 return;
3184
e756fc62 3185 pre_svm_run(svm);
6aa8b732 3186
649d6864
JR		 3187 sync_lapic_to_cr8(vcpu);
3188
6aa8b732 3189 save_host_msrs(vcpu);
9581d442
AK		 3190 savesegment(fs, fs_selector);
3191 savesegment(gs, gs_selector);
d6e88aec 3192 ldt_selector = kvm_read_ldt();
cda0ffdd 3193 svm->vmcb->save.cr2 = vcpu->arch.cr2;
709ddebf
JR		 3194 /* required for live migration with NPT */
3195 if (npt_enabled)
3196 svm->vmcb->save.cr3 = vcpu->arch.cr3;
6aa8b732 3197
04d2cc77
AK		 3198 clgi();
3199
3200 local_irq_enable();
36241b8c 3201
6aa8b732 3202 asm volatile (
80e31d4f
AK		 3203 "push %%"R"bp; \n\t"
3204 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3205 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3206 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3207 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3208 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3209 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
05b3e0c2 3210#ifdef CONFIG_X86_64
fb3f0f51
RR		 3211 "mov %c[r8](%[svm]), %%r8 \n\t"
3212 "mov %c[r9](%[svm]), %%r9 \n\t"
3213 "mov %c[r10](%[svm]), %%r10 \n\t"
3214 "mov %c[r11](%[svm]), %%r11 \n\t"
3215 "mov %c[r12](%[svm]), %%r12 \n\t"
3216 "mov %c[r13](%[svm]), %%r13 \n\t"
3217 "mov %c[r14](%[svm]), %%r14 \n\t"
3218 "mov %c[r15](%[svm]), %%r15 \n\t"
6aa8b732
AK		 3219#endif
3220
6aa8b732 3221 /* Enter guest mode */
80e31d4f
AK		 3222 "push %%"R"ax \n\t"
3223 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
4ecac3fd
AK		 3224 __ex(SVM_VMLOAD) "\n\t"
3225 __ex(SVM_VMRUN) "\n\t"
3226 __ex(SVM_VMSAVE) "\n\t"
80e31d4f 3227 "pop %%"R"ax \n\t"
6aa8b732
AK		 3228
3229 /* Save guest registers, load host registers */
80e31d4f
AK		 3230 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3231 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3232 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3233 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3234 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3235 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
05b3e0c2 3236#ifdef CONFIG_X86_64
fb3f0f51
RR		 3237 "mov %%r8, %c[r8](%[svm]) \n\t"
3238 "mov %%r9, %c[r9](%[svm]) \n\t"
3239 "mov %%r10, %c[r10](%[svm]) \n\t"
3240 "mov %%r11, %c[r11](%[svm]) \n\t"
3241 "mov %%r12, %c[r12](%[svm]) \n\t"
3242 "mov %%r13, %c[r13](%[svm]) \n\t"
3243 "mov %%r14, %c[r14](%[svm]) \n\t"
3244 "mov %%r15, %c[r15](%[svm]) \n\t"
6aa8b732 3245#endif
80e31d4f 3246 "pop %%"R"bp"
6aa8b732 3247 :
fb3f0f51 3248 : [svm]"a"(svm),
6aa8b732 3249 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
ad312c7c
ZX		 3250 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3251 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3252 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3253 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3254 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3255 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
05b3e0c2 3256#ifdef CONFIG_X86_64
ad312c7c
ZX		 3257 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3258 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3259 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3260 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3261 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3262 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3263 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3264 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
6aa8b732 3265#endif
54a08c04 3266 : "cc", "memory"
80e31d4f 3267 , R"bx", R"cx", R"dx", R"si", R"di"
54a08c04 3268#ifdef CONFIG_X86_64
54a08c04
LV		 3269 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3270#endif
3271 );
6aa8b732 3272
ad312c7c 3273 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5fdbf976
MT		 3274 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3275 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3276 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
6aa8b732 3277
6aa8b732 3278 load_host_msrs(vcpu);
9581d442
AK		 3279 loadsegment(fs, fs_selector);
3280#ifdef CONFIG_X86_64
3281 load_gs_index(gs_selector);
3282 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3283#else
3284 loadsegment(gs, gs_selector);
3285#endif
3286 kvm_load_ldt(ldt_selector);
6aa8b732
AK		 3287
3288 reload_tss(vcpu);
3289
56ba47dd
AK		 3290 local_irq_disable();
3291
3292 stgi();
3293
d7bf8221
JR		 3294 sync_cr8_to_lapic(vcpu);
3295
a2fa3e9f 3296 svm->next_rip = 0;
9222be18 3297
6de4f3ad
AK		 3298 if (npt_enabled) {
3299 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3300 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3301 }
fe5913e4
JR		 3302
3303 /*
3304 * We need to handle MC intercepts here before the vcpu has a chance to
3305 * change the physical cpu
3306 */
3307 if (unlikely(svm->vmcb->control.exit_code ==
3308 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3309 svm_handle_mce(svm);
6aa8b732
AK		 3310}
3311
80e31d4f
AK		 3312#undef R
3313
6aa8b732
AK		 3314static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3315{
a2fa3e9f
GH		 3316 struct vcpu_svm *svm = to_svm(vcpu);
3317
709ddebf
JR		 3318 if (npt_enabled) {
3319 svm->vmcb->control.nested_cr3 = root;
3320 force_new_asid(vcpu);
3321 return;
3322 }
3323
a2fa3e9f 3324 svm->vmcb->save.cr3 = root;
6aa8b732
AK		 3325 force_new_asid(vcpu);
3326}
3327
6aa8b732
AK		 3328static int is_disabled(void)
3329{
6031a61c
JR		 3330 u64 vm_cr;
3331
3332 rdmsrl(MSR_VM_CR, vm_cr);
3333 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3334 return 1;
3335
6aa8b732
AK		 3336 return 0;
3337}
3338
102d8325
IM		 3339static void
3340svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3341{
3342 /*
3343 * Patch in the VMMCALL instruction:
3344 */
3345 hypercall[0] = 0x0f;
3346 hypercall[1] = 0x01;
3347 hypercall[2] = 0xd9;
102d8325
IM		 3348}
3349
002c7f7c
YS		 3350static void svm_check_processor_compat(void *rtn)
3351{
3352 *(int *)rtn = 0;
3353}
3354
774ead3a
AK		 3355static bool svm_cpu_has_accelerated_tpr(void)
3356{
3357 return false;
3358}
3359
67253af5
SY		 3360static int get_npt_level(void)
3361{
3362#ifdef CONFIG_X86_64
3363 return PT64_ROOT_LEVEL;
3364#else
3365 return PT32E_ROOT_LEVEL;
3366#endif
3367}
3368
4b12f0de 3369static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521
SY		 3370{
3371 return 0;
3372}
3373
0e851880
SY		 3374static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3375{
3376}
3377
d4330ef2
JR		 3378static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3379{
c2c63a49
JR		 3380 switch (func) {
3381 case 0x8000000A:
3382 entry->eax = 1; /* SVM revision 1 */
3383 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3384 ASID emulation to nested SVM */
3385 entry->ecx = 0; /* Reserved */
7a190667
JR		 3386 entry->edx = 0; /* Per default do not support any
3387 additional features */
3388
3389 /* Support next_rip if host supports it */
3390 if (svm_has(SVM_FEATURE_NRIP))
3391 entry->edx |= SVM_FEATURE_NRIP;
c2c63a49
JR		 3392
3393 break;
3394 }
d4330ef2
JR		 3395}
3396
229456fc 3397static const struct trace_print_flags svm_exit_reasons_str[] = {
e0231715
JR		 3398 { SVM_EXIT_READ_CR0, "read_cr0" },
3399 { SVM_EXIT_READ_CR3, "read_cr3" },
3400 { SVM_EXIT_READ_CR4, "read_cr4" },
3401 { SVM_EXIT_READ_CR8, "read_cr8" },
3402 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3403 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3404 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3405 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3406 { SVM_EXIT_READ_DR0, "read_dr0" },
3407 { SVM_EXIT_READ_DR1, "read_dr1" },
3408 { SVM_EXIT_READ_DR2, "read_dr2" },
3409 { SVM_EXIT_READ_DR3, "read_dr3" },
3410 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3411 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3412 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3413 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3414 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3415 { SVM_EXIT_WRITE_DR7, "write_dr7" },
229456fc
MT		 3416 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3417 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3418 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3419 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3420 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3421 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3422 { SVM_EXIT_INTR, "interrupt" },
3423 { SVM_EXIT_NMI, "nmi" },
3424 { SVM_EXIT_SMI, "smi" },
3425 { SVM_EXIT_INIT, "init" },
3426 { SVM_EXIT_VINTR, "vintr" },
3427 { SVM_EXIT_CPUID, "cpuid" },
3428 { SVM_EXIT_INVD, "invd" },
3429 { SVM_EXIT_HLT, "hlt" },
3430 { SVM_EXIT_INVLPG, "invlpg" },
3431 { SVM_EXIT_INVLPGA, "invlpga" },
3432 { SVM_EXIT_IOIO, "io" },
3433 { SVM_EXIT_MSR, "msr" },
3434 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3435 { SVM_EXIT_SHUTDOWN, "shutdown" },
3436 { SVM_EXIT_VMRUN, "vmrun" },
3437 { SVM_EXIT_VMMCALL, "hypercall" },
3438 { SVM_EXIT_VMLOAD, "vmload" },
3439 { SVM_EXIT_VMSAVE, "vmsave" },
3440 { SVM_EXIT_STGI, "stgi" },
3441 { SVM_EXIT_CLGI, "clgi" },
3442 { SVM_EXIT_SKINIT, "skinit" },
3443 { SVM_EXIT_WBINVD, "wbinvd" },
3444 { SVM_EXIT_MONITOR, "monitor" },
3445 { SVM_EXIT_MWAIT, "mwait" },
3446 { SVM_EXIT_NPF, "npf" },
3447 { -1, NULL }
3448};
3449
17cc3935 3450static int svm_get_lpage_level(void)
344f414f 3451{
17cc3935 3452 return PT_PDPE_LEVEL;
344f414f
JR		 3453}
3454
4e47c7a6
SY		 3455static bool svm_rdtscp_supported(void)
3456{
3457 return false;
3458}
3459
f5f48ee1
SY		 3460static bool svm_has_wbinvd_exit(void)
3461{
3462 return true;
3463}
3464
02daab21
AK		 3465static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3466{
3467 struct vcpu_svm *svm = to_svm(vcpu);
3468
02daab21 3469 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
66a562f7
JR		 3470 if (is_nested(svm))
3471 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3472 update_cr0_intercept(svm);
02daab21
AK		 3473}
3474
cbdd1bea 3475static struct kvm_x86_ops svm_x86_ops = {
6aa8b732
AK		 3476 .cpu_has_kvm_support = has_svm,
3477 .disabled_by_bios = is_disabled,
3478 .hardware_setup = svm_hardware_setup,
3479 .hardware_unsetup = svm_hardware_unsetup,
002c7f7c 3480 .check_processor_compatibility = svm_check_processor_compat,
6aa8b732
AK		 3481 .hardware_enable = svm_hardware_enable,
3482 .hardware_disable = svm_hardware_disable,
774ead3a 3483 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
6aa8b732
AK		 3484
3485 .vcpu_create = svm_create_vcpu,
3486 .vcpu_free = svm_free_vcpu,
04d2cc77 3487 .vcpu_reset = svm_vcpu_reset,
6aa8b732 3488
04d2cc77 3489 .prepare_guest_switch = svm_prepare_guest_switch,
6aa8b732
AK		 3490 .vcpu_load = svm_vcpu_load,
3491 .vcpu_put = svm_vcpu_put,
3492
3493 .set_guest_debug = svm_guest_debug,
3494 .get_msr = svm_get_msr,
3495 .set_msr = svm_set_msr,
3496 .get_segment_base = svm_get_segment_base,
3497 .get_segment = svm_get_segment,
3498 .set_segment = svm_set_segment,
2e4d2653 3499 .get_cpl = svm_get_cpl,
1747fb71 3500 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
e8467fda 3501 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
25c4c276 3502 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 3503 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 3504 .set_cr3 = svm_set_cr3,
3505 .set_cr4 = svm_set_cr4,
3506 .set_efer = svm_set_efer,
3507 .get_idt = svm_get_idt,
3508 .set_idt = svm_set_idt,
3509 .get_gdt = svm_get_gdt,
3510 .set_gdt = svm_set_gdt,
020df079 3511 .set_dr7 = svm_set_dr7,
6de4f3ad 3512 .cache_reg = svm_cache_reg,
6aa8b732
AK		 3513 .get_rflags = svm_get_rflags,
3514 .set_rflags = svm_set_rflags,
6b52d186 3515 .fpu_activate = svm_fpu_activate,
02daab21 3516 .fpu_deactivate = svm_fpu_deactivate,
6aa8b732 3517
6aa8b732 3518 .tlb_flush = svm_flush_tlb,
6aa8b732 3519
6aa8b732 3520 .run = svm_vcpu_run,
04d2cc77 3521 .handle_exit = handle_exit,
6aa8b732 3522 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 3523 .set_interrupt_shadow = svm_set_interrupt_shadow,
3524 .get_interrupt_shadow = svm_get_interrupt_shadow,
102d8325 3525 .patch_hypercall = svm_patch_hypercall,
2a8067f1 3526 .set_irq = svm_set_irq,
95ba8273 3527 .set_nmi = svm_inject_nmi,
298101da 3528 .queue_exception = svm_queue_exception,
78646121 3529 .interrupt_allowed = svm_interrupt_allowed,
95ba8273 3530 .nmi_allowed = svm_nmi_allowed,
3cfc3092
JK		 3531 .get_nmi_mask = svm_get_nmi_mask,
3532 .set_nmi_mask = svm_set_nmi_mask,
95ba8273
GN		 3533 .enable_nmi_window = enable_nmi_window,
3534 .enable_irq_window = enable_irq_window,
3535 .update_cr8_intercept = update_cr8_intercept,
cbc94022
IE		 3536
3537 .set_tss_addr = svm_set_tss_addr,
67253af5 3538 .get_tdp_level = get_npt_level,
4b12f0de 3539 .get_mt_mask = svm_get_mt_mask,
229456fc
MT		 3540
3541 .exit_reasons_str = svm_exit_reasons_str,
17cc3935 3542 .get_lpage_level = svm_get_lpage_level,
0e851880
SY		 3543
3544 .cpuid_update = svm_cpuid_update,
4e47c7a6
SY		 3545
3546 .rdtscp_supported = svm_rdtscp_supported,
d4330ef2
JR		 3547
3548 .set_supported_cpuid = svm_set_supported_cpuid,
f5f48ee1
SY		 3549
3550 .has_wbinvd_exit = svm_has_wbinvd_exit,
6aa8b732
AK		 3551};
3552
3553static int __init svm_init(void)
3554{
cb498ea2 3555 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
0ee75bea 3556 __alignof__(struct vcpu_svm), THIS_MODULE);
6aa8b732
AK		 3557}
3558
3559static void __exit svm_exit(void)
3560{
cb498ea2 3561 kvm_exit();
6aa8b732
AK		 3562}
3563
3564module_init(svm_init)
3565module_exit(svm_exit)
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