2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
31 #include <asm/virtext.h>
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 #define IOPM_ALLOC_ORDER 2
39 #define MSRPM_ALLOC_ORDER 1
41 #define SEG_TYPE_LDT 2
42 #define SEG_TYPE_BUSY_TSS16 3
44 #define SVM_FEATURE_NPT (1 << 0)
45 #define SVM_FEATURE_LBRV (1 << 1)
46 #define SVM_FEATURE_SVML (1 << 2)
48 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
50 /* Turn on to get debugging output*/
51 /* #define NESTED_DEBUG */
54 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
56 #define nsvm_printk(fmt, args...) do {} while(0)
59 /* enable NPT for AMD64 and X86 with PAE */
60 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
61 static bool npt_enabled
= true;
63 static bool npt_enabled
= false;
67 module_param(npt
, int, S_IRUGO
);
69 static int nested
= 0;
70 module_param(nested
, int, S_IRUGO
);
72 static void kvm_reput_irq(struct vcpu_svm
*svm
);
73 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
75 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
);
76 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
77 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
78 void *arg2
, void *opaque
);
79 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
80 bool has_error_code
, u32 error_code
);
82 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
84 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
87 static inline bool is_nested(struct vcpu_svm
*svm
)
89 return svm
->nested_vmcb
;
92 static unsigned long iopm_base
;
94 struct kvm_ldttss_desc
{
97 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
98 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
101 } __attribute__((packed
));
103 struct svm_cpu_data
{
109 struct kvm_ldttss_desc
*tss_desc
;
111 struct page
*save_area
;
114 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
115 static uint32_t svm_features
;
117 struct svm_init_data
{
122 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
125 #define MSRS_RANGE_SIZE 2048
126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
128 #define MAX_INST_SIZE 15
130 static inline u32
svm_has(u32 feat
)
132 return svm_features
& feat
;
135 static inline u8
pop_irq(struct kvm_vcpu
*vcpu
)
137 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
138 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
139 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
141 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
142 if (!vcpu
->arch
.irq_pending
[word_index
])
143 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
147 static inline void push_irq(struct kvm_vcpu
*vcpu
, u8 irq
)
149 set_bit(irq
, vcpu
->arch
.irq_pending
);
150 set_bit(irq
/ BITS_PER_LONG
, &vcpu
->arch
.irq_summary
);
153 static inline void clgi(void)
155 asm volatile (__ex(SVM_CLGI
));
158 static inline void stgi(void)
160 asm volatile (__ex(SVM_STGI
));
163 static inline void invlpga(unsigned long addr
, u32 asid
)
165 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
168 static inline unsigned long kvm_read_cr2(void)
172 asm volatile ("mov %%cr2, %0" : "=r" (cr2
));
176 static inline void kvm_write_cr2(unsigned long val
)
178 asm volatile ("mov %0, %%cr2" :: "r" (val
));
181 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
183 to_svm(vcpu
)->asid_generation
--;
186 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
188 force_new_asid(vcpu
);
191 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
193 if (!npt_enabled
&& !(efer
& EFER_LMA
))
196 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
197 vcpu
->arch
.shadow_efer
= efer
;
200 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
201 bool has_error_code
, u32 error_code
)
203 struct vcpu_svm
*svm
= to_svm(vcpu
);
205 /* If we are within a nested VM we'd better #VMEXIT and let the
206 guest handle the exception */
207 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
210 svm
->vmcb
->control
.event_inj
= nr
212 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
213 | SVM_EVTINJ_TYPE_EXEPT
;
214 svm
->vmcb
->control
.event_inj_err
= error_code
;
217 static bool svm_exception_injected(struct kvm_vcpu
*vcpu
)
219 struct vcpu_svm
*svm
= to_svm(vcpu
);
221 return !(svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
);
224 static int is_external_interrupt(u32 info
)
226 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
227 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
230 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
232 struct vcpu_svm
*svm
= to_svm(vcpu
);
234 if (!svm
->next_rip
) {
235 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
238 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
239 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
240 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
242 kvm_rip_write(vcpu
, svm
->next_rip
);
243 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
245 vcpu
->arch
.interrupt_window_open
= (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
248 static int has_svm(void)
252 if (!cpu_has_svm(&msg
)) {
253 printk(KERN_INFO
"has_svm: %s\n", msg
);
260 static void svm_hardware_disable(void *garbage
)
265 static void svm_hardware_enable(void *garbage
)
268 struct svm_cpu_data
*svm_data
;
270 struct desc_ptr gdt_descr
;
271 struct desc_struct
*gdt
;
272 int me
= raw_smp_processor_id();
275 printk(KERN_ERR
"svm_cpu_init: err EOPNOTSUPP on %d\n", me
);
278 svm_data
= per_cpu(svm_data
, me
);
281 printk(KERN_ERR
"svm_cpu_init: svm_data is NULL on %d\n",
286 svm_data
->asid_generation
= 1;
287 svm_data
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
288 svm_data
->next_asid
= svm_data
->max_asid
+ 1;
290 asm volatile ("sgdt %0" : "=m"(gdt_descr
));
291 gdt
= (struct desc_struct
*)gdt_descr
.address
;
292 svm_data
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
294 rdmsrl(MSR_EFER
, efer
);
295 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
297 wrmsrl(MSR_VM_HSAVE_PA
,
298 page_to_pfn(svm_data
->save_area
) << PAGE_SHIFT
);
301 static void svm_cpu_uninit(int cpu
)
303 struct svm_cpu_data
*svm_data
304 = per_cpu(svm_data
, raw_smp_processor_id());
309 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
310 __free_page(svm_data
->save_area
);
314 static int svm_cpu_init(int cpu
)
316 struct svm_cpu_data
*svm_data
;
319 svm_data
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
323 svm_data
->save_area
= alloc_page(GFP_KERNEL
);
325 if (!svm_data
->save_area
)
328 per_cpu(svm_data
, cpu
) = svm_data
;
338 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
343 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
344 if (msr
>= msrpm_ranges
[i
] &&
345 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
346 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
347 msrpm_ranges
[i
]) * 2;
349 u32
*base
= msrpm
+ (msr_offset
/ 32);
350 u32 msr_shift
= msr_offset
% 32;
351 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
352 *base
= (*base
& ~(0x3 << msr_shift
)) |
360 static void svm_vcpu_init_msrpm(u32
*msrpm
)
362 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
365 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
366 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
367 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
368 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
369 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
370 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
372 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
373 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
374 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_ESP
, 1, 1);
375 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_EIP
, 1, 1);
378 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
380 u32
*msrpm
= svm
->msrpm
;
382 svm
->vmcb
->control
.lbr_ctl
= 1;
383 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
384 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
385 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
386 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
389 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
391 u32
*msrpm
= svm
->msrpm
;
393 svm
->vmcb
->control
.lbr_ctl
= 0;
394 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
395 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
396 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
397 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
400 static __init
int svm_hardware_setup(void)
403 struct page
*iopm_pages
;
407 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
412 iopm_va
= page_address(iopm_pages
);
413 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
414 clear_bit(0x80, iopm_va
); /* allow direct access to PC debug port */
415 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
417 if (boot_cpu_has(X86_FEATURE_NX
))
418 kvm_enable_efer_bits(EFER_NX
);
420 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
421 kvm_enable_efer_bits(EFER_FFXSR
);
424 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
425 kvm_enable_efer_bits(EFER_SVME
);
428 for_each_online_cpu(cpu
) {
429 r
= svm_cpu_init(cpu
);
434 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
436 if (!svm_has(SVM_FEATURE_NPT
))
439 if (npt_enabled
&& !npt
) {
440 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
445 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
453 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
458 static __exit
void svm_hardware_unsetup(void)
462 for_each_online_cpu(cpu
)
465 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
469 static void init_seg(struct vmcb_seg
*seg
)
472 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
473 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
478 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
481 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
486 static void init_vmcb(struct vcpu_svm
*svm
)
488 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
489 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
491 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
495 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
500 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
505 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
512 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
517 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
518 (1ULL << INTERCEPT_NMI
) |
519 (1ULL << INTERCEPT_SMI
) |
520 (1ULL << INTERCEPT_CPUID
) |
521 (1ULL << INTERCEPT_INVD
) |
522 (1ULL << INTERCEPT_HLT
) |
523 (1ULL << INTERCEPT_INVLPG
) |
524 (1ULL << INTERCEPT_INVLPGA
) |
525 (1ULL << INTERCEPT_IOIO_PROT
) |
526 (1ULL << INTERCEPT_MSR_PROT
) |
527 (1ULL << INTERCEPT_TASK_SWITCH
) |
528 (1ULL << INTERCEPT_SHUTDOWN
) |
529 (1ULL << INTERCEPT_VMRUN
) |
530 (1ULL << INTERCEPT_VMMCALL
) |
531 (1ULL << INTERCEPT_VMLOAD
) |
532 (1ULL << INTERCEPT_VMSAVE
) |
533 (1ULL << INTERCEPT_STGI
) |
534 (1ULL << INTERCEPT_CLGI
) |
535 (1ULL << INTERCEPT_SKINIT
) |
536 (1ULL << INTERCEPT_WBINVD
) |
537 (1ULL << INTERCEPT_MONITOR
) |
538 (1ULL << INTERCEPT_MWAIT
);
540 control
->iopm_base_pa
= iopm_base
;
541 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
542 control
->tsc_offset
= 0;
543 control
->int_ctl
= V_INTR_MASKING_MASK
;
551 save
->cs
.selector
= 0xf000;
552 /* Executable/Readable Code Segment */
553 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
554 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
555 save
->cs
.limit
= 0xffff;
557 * cs.base should really be 0xffff0000, but vmx can't handle that, so
558 * be consistent with it.
560 * Replace when we have real mode working for vmx.
562 save
->cs
.base
= 0xf0000;
564 save
->gdtr
.limit
= 0xffff;
565 save
->idtr
.limit
= 0xffff;
567 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
568 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
570 save
->efer
= EFER_SVME
;
571 save
->dr6
= 0xffff0ff0;
574 save
->rip
= 0x0000fff0;
575 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
578 * cr0 val on cpu init should be 0x60000010, we enable cpu
579 * cache by default. the orderly way is to enable cache in bios.
581 save
->cr0
= 0x00000010 | X86_CR0_PG
| X86_CR0_WP
;
582 save
->cr4
= X86_CR4_PAE
;
586 /* Setup VMCB for Nested Paging */
587 control
->nested_ctl
= 1;
588 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
589 (1ULL << INTERCEPT_INVLPG
));
590 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
591 control
->intercept_cr_read
&= ~(INTERCEPT_CR0_MASK
|
593 control
->intercept_cr_write
&= ~(INTERCEPT_CR0_MASK
|
595 save
->g_pat
= 0x0007040600070406ULL
;
596 /* enable caching because the QEMU Bios doesn't enable it */
597 save
->cr0
= X86_CR0_ET
;
601 force_new_asid(&svm
->vcpu
);
603 svm
->nested_vmcb
= 0;
604 svm
->vcpu
.arch
.hflags
= HF_GIF_MASK
;
607 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
609 struct vcpu_svm
*svm
= to_svm(vcpu
);
613 if (vcpu
->vcpu_id
!= 0) {
614 kvm_rip_write(vcpu
, 0);
615 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
616 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
618 vcpu
->arch
.regs_avail
= ~0;
619 vcpu
->arch
.regs_dirty
= ~0;
624 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
626 struct vcpu_svm
*svm
;
628 struct page
*msrpm_pages
;
629 struct page
*hsave_page
;
630 struct page
*nested_msrpm_pages
;
633 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
639 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
643 page
= alloc_page(GFP_KERNEL
);
650 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
654 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
655 if (!nested_msrpm_pages
)
658 svm
->msrpm
= page_address(msrpm_pages
);
659 svm_vcpu_init_msrpm(svm
->msrpm
);
661 hsave_page
= alloc_page(GFP_KERNEL
);
664 svm
->hsave
= page_address(hsave_page
);
666 svm
->nested_msrpm
= page_address(nested_msrpm_pages
);
668 svm
->vmcb
= page_address(page
);
669 clear_page(svm
->vmcb
);
670 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
671 svm
->asid_generation
= 0;
675 svm
->vcpu
.fpu_active
= 1;
676 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
677 if (svm
->vcpu
.vcpu_id
== 0)
678 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
683 kvm_vcpu_uninit(&svm
->vcpu
);
685 kmem_cache_free(kvm_vcpu_cache
, svm
);
690 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
692 struct vcpu_svm
*svm
= to_svm(vcpu
);
694 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
695 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
696 __free_page(virt_to_page(svm
->hsave
));
697 __free_pages(virt_to_page(svm
->nested_msrpm
), MSRPM_ALLOC_ORDER
);
698 kvm_vcpu_uninit(vcpu
);
699 kmem_cache_free(kvm_vcpu_cache
, svm
);
702 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
704 struct vcpu_svm
*svm
= to_svm(vcpu
);
707 if (unlikely(cpu
!= vcpu
->cpu
)) {
711 * Make sure that the guest sees a monotonically
715 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
716 svm
->vmcb
->control
.tsc_offset
+= delta
;
718 kvm_migrate_timers(vcpu
);
721 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
722 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
725 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
727 struct vcpu_svm
*svm
= to_svm(vcpu
);
730 ++vcpu
->stat
.host_state_reload
;
731 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
732 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
734 rdtscll(vcpu
->arch
.host_tsc
);
737 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
739 return to_svm(vcpu
)->vmcb
->save
.rflags
;
742 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
744 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
747 static void svm_set_vintr(struct vcpu_svm
*svm
)
749 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
752 static void svm_clear_vintr(struct vcpu_svm
*svm
)
754 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
757 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
759 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
762 case VCPU_SREG_CS
: return &save
->cs
;
763 case VCPU_SREG_DS
: return &save
->ds
;
764 case VCPU_SREG_ES
: return &save
->es
;
765 case VCPU_SREG_FS
: return &save
->fs
;
766 case VCPU_SREG_GS
: return &save
->gs
;
767 case VCPU_SREG_SS
: return &save
->ss
;
768 case VCPU_SREG_TR
: return &save
->tr
;
769 case VCPU_SREG_LDTR
: return &save
->ldtr
;
775 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
777 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
782 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
783 struct kvm_segment
*var
, int seg
)
785 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
788 var
->limit
= s
->limit
;
789 var
->selector
= s
->selector
;
790 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
791 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
792 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
793 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
794 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
795 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
796 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
797 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
800 * SVM always stores 0 for the 'G' bit in the CS selector in
801 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
802 * Intel's VMENTRY has a check on the 'G' bit.
804 if (seg
== VCPU_SREG_CS
)
805 var
->g
= s
->limit
> 0xfffff;
808 * Work around a bug where the busy flag in the tr selector
811 if (seg
== VCPU_SREG_TR
)
814 var
->unusable
= !var
->present
;
817 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
819 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
824 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
826 struct vcpu_svm
*svm
= to_svm(vcpu
);
828 dt
->limit
= svm
->vmcb
->save
.idtr
.limit
;
829 dt
->base
= svm
->vmcb
->save
.idtr
.base
;
832 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
834 struct vcpu_svm
*svm
= to_svm(vcpu
);
836 svm
->vmcb
->save
.idtr
.limit
= dt
->limit
;
837 svm
->vmcb
->save
.idtr
.base
= dt
->base
;
840 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
842 struct vcpu_svm
*svm
= to_svm(vcpu
);
844 dt
->limit
= svm
->vmcb
->save
.gdtr
.limit
;
845 dt
->base
= svm
->vmcb
->save
.gdtr
.base
;
848 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
850 struct vcpu_svm
*svm
= to_svm(vcpu
);
852 svm
->vmcb
->save
.gdtr
.limit
= dt
->limit
;
853 svm
->vmcb
->save
.gdtr
.base
= dt
->base
;
856 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
860 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
862 struct vcpu_svm
*svm
= to_svm(vcpu
);
865 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
866 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
867 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
868 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
871 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
872 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
873 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
880 if ((vcpu
->arch
.cr0
& X86_CR0_TS
) && !(cr0
& X86_CR0_TS
)) {
881 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
882 vcpu
->fpu_active
= 1;
885 vcpu
->arch
.cr0
= cr0
;
886 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
887 if (!vcpu
->fpu_active
) {
888 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
893 * re-enable caching here because the QEMU bios
894 * does not do it - this results in some delay at
897 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
898 svm
->vmcb
->save
.cr0
= cr0
;
901 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
903 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
904 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
906 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
907 force_new_asid(vcpu
);
909 vcpu
->arch
.cr4
= cr4
;
913 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
916 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
917 struct kvm_segment
*var
, int seg
)
919 struct vcpu_svm
*svm
= to_svm(vcpu
);
920 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
923 s
->limit
= var
->limit
;
924 s
->selector
= var
->selector
;
928 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
929 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
930 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
931 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
932 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
933 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
934 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
935 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
937 if (seg
== VCPU_SREG_CS
)
939 = (svm
->vmcb
->save
.cs
.attrib
940 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
944 static int svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
946 int old_debug
= vcpu
->guest_debug
;
947 struct vcpu_svm
*svm
= to_svm(vcpu
);
949 vcpu
->guest_debug
= dbg
->control
;
951 svm
->vmcb
->control
.intercept_exceptions
&=
952 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
953 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
954 if (vcpu
->guest_debug
&
955 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
956 svm
->vmcb
->control
.intercept_exceptions
|=
958 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
959 svm
->vmcb
->control
.intercept_exceptions
|=
962 vcpu
->guest_debug
= 0;
964 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
965 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
967 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
969 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
970 svm
->vmcb
->save
.rflags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
971 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
972 svm
->vmcb
->save
.rflags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
977 static int svm_get_irq(struct kvm_vcpu
*vcpu
)
979 struct vcpu_svm
*svm
= to_svm(vcpu
);
980 u32 exit_int_info
= svm
->vmcb
->control
.exit_int_info
;
982 if (is_external_interrupt(exit_int_info
))
983 return exit_int_info
& SVM_EVTINJ_VEC_MASK
;
987 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
990 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
994 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
997 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1001 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*svm_data
)
1003 if (svm_data
->next_asid
> svm_data
->max_asid
) {
1004 ++svm_data
->asid_generation
;
1005 svm_data
->next_asid
= 1;
1006 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1009 svm
->vcpu
.cpu
= svm_data
->cpu
;
1010 svm
->asid_generation
= svm_data
->asid_generation
;
1011 svm
->vmcb
->control
.asid
= svm_data
->next_asid
++;
1014 static unsigned long svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
)
1016 struct vcpu_svm
*svm
= to_svm(vcpu
);
1021 val
= vcpu
->arch
.db
[dr
];
1024 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1025 val
= vcpu
->arch
.dr6
;
1027 val
= svm
->vmcb
->save
.dr6
;
1030 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1031 val
= vcpu
->arch
.dr7
;
1033 val
= svm
->vmcb
->save
.dr7
;
1039 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
1043 static void svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
,
1046 struct vcpu_svm
*svm
= to_svm(vcpu
);
1048 KVMTRACE_2D(DR_WRITE
, vcpu
, (u32
)dr
, (u32
)value
, handler
);
1054 vcpu
->arch
.db
[dr
] = value
;
1055 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
1056 vcpu
->arch
.eff_db
[dr
] = value
;
1059 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
1060 *exception
= UD_VECTOR
;
1063 if (value
& 0xffffffff00000000ULL
) {
1064 *exception
= GP_VECTOR
;
1067 vcpu
->arch
.dr6
= (value
& DR6_VOLATILE
) | DR6_FIXED_1
;
1070 if (value
& 0xffffffff00000000ULL
) {
1071 *exception
= GP_VECTOR
;
1074 vcpu
->arch
.dr7
= (value
& DR7_VOLATILE
) | DR7_FIXED_1
;
1075 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
1076 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1077 vcpu
->arch
.switch_db_regs
= (value
& DR7_BP_EN_MASK
);
1081 /* FIXME: Possible case? */
1082 printk(KERN_DEBUG
"%s: unexpected dr %u\n",
1084 *exception
= UD_VECTOR
;
1089 static int pf_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1091 u32 exit_int_info
= svm
->vmcb
->control
.exit_int_info
;
1092 struct kvm
*kvm
= svm
->vcpu
.kvm
;
1095 bool event_injection
= false;
1097 if (!irqchip_in_kernel(kvm
) &&
1098 is_external_interrupt(exit_int_info
)) {
1099 event_injection
= true;
1100 push_irq(&svm
->vcpu
, exit_int_info
& SVM_EVTINJ_VEC_MASK
);
1103 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1104 error_code
= svm
->vmcb
->control
.exit_info_1
;
1107 KVMTRACE_3D(PAGE_FAULT
, &svm
->vcpu
, error_code
,
1108 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1111 KVMTRACE_3D(TDP_FAULT
, &svm
->vcpu
, error_code
,
1112 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1115 * FIXME: Tis shouldn't be necessary here, but there is a flush
1116 * missing in the MMU code. Until we find this bug, flush the
1117 * complete TLB here on an NPF
1120 svm_flush_tlb(&svm
->vcpu
);
1122 if (!npt_enabled
&& event_injection
)
1123 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1124 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1127 static int db_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1129 if (!(svm
->vcpu
.guest_debug
&
1130 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
1131 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1134 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1135 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1136 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1140 static int bp_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1142 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1143 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1144 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1148 static int ud_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1152 er
= emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1153 if (er
!= EMULATE_DONE
)
1154 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1158 static int nm_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1160 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1161 if (!(svm
->vcpu
.arch
.cr0
& X86_CR0_TS
))
1162 svm
->vmcb
->save
.cr0
&= ~X86_CR0_TS
;
1163 svm
->vcpu
.fpu_active
= 1;
1168 static int mc_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1171 * On an #MC intercept the MCE handler is not called automatically in
1172 * the host. So do it by hand here.
1176 /* not sure if we ever come back to this point */
1181 static int shutdown_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1184 * VMCB is undefined after a SHUTDOWN intercept
1185 * so reinitialize it.
1187 clear_page(svm
->vmcb
);
1190 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1194 static int io_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1196 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1197 int size
, in
, string
;
1200 ++svm
->vcpu
.stat
.io_exits
;
1202 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1204 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1207 if (emulate_instruction(&svm
->vcpu
,
1208 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1213 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1214 port
= io_info
>> 16;
1215 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1217 skip_emulated_instruction(&svm
->vcpu
);
1218 return kvm_emulate_pio(&svm
->vcpu
, kvm_run
, in
, size
, port
);
1221 static int nmi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1223 KVMTRACE_0D(NMI
, &svm
->vcpu
, handler
);
1227 static int intr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1229 ++svm
->vcpu
.stat
.irq_exits
;
1230 KVMTRACE_0D(INTR
, &svm
->vcpu
, handler
);
1234 static int nop_on_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1239 static int halt_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1241 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1242 skip_emulated_instruction(&svm
->vcpu
);
1243 return kvm_emulate_halt(&svm
->vcpu
);
1246 static int vmmcall_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1248 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1249 skip_emulated_instruction(&svm
->vcpu
);
1250 kvm_emulate_hypercall(&svm
->vcpu
);
1254 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1256 if (!(svm
->vcpu
.arch
.shadow_efer
& EFER_SVME
)
1257 || !is_paging(&svm
->vcpu
)) {
1258 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1262 if (svm
->vmcb
->save
.cpl
) {
1263 kvm_inject_gp(&svm
->vcpu
, 0);
1270 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1271 bool has_error_code
, u32 error_code
)
1273 if (is_nested(svm
)) {
1274 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1275 svm
->vmcb
->control
.exit_code_hi
= 0;
1276 svm
->vmcb
->control
.exit_info_1
= error_code
;
1277 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1278 if (nested_svm_exit_handled(svm
, false)) {
1279 nsvm_printk("VMexit -> EXCP 0x%x\n", nr
);
1281 nested_svm_vmexit(svm
);
1289 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1291 if (is_nested(svm
)) {
1292 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1295 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1298 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1300 if (nested_svm_exit_handled(svm
, false)) {
1301 nsvm_printk("VMexit -> INTR\n");
1302 nested_svm_vmexit(svm
);
1310 static struct page
*nested_svm_get_page(struct vcpu_svm
*svm
, u64 gpa
)
1314 down_read(¤t
->mm
->mmap_sem
);
1315 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1316 up_read(¤t
->mm
->mmap_sem
);
1318 if (is_error_page(page
)) {
1319 printk(KERN_INFO
"%s: could not find page at 0x%llx\n",
1321 kvm_release_page_clean(page
);
1322 kvm_inject_gp(&svm
->vcpu
, 0);
1328 static int nested_svm_do(struct vcpu_svm
*svm
,
1329 u64 arg1_gpa
, u64 arg2_gpa
, void *opaque
,
1330 int (*handler
)(struct vcpu_svm
*svm
,
1335 struct page
*arg1_page
;
1336 struct page
*arg2_page
= NULL
;
1341 arg1_page
= nested_svm_get_page(svm
, arg1_gpa
);
1342 if(arg1_page
== NULL
)
1346 arg2_page
= nested_svm_get_page(svm
, arg2_gpa
);
1347 if(arg2_page
== NULL
) {
1348 kvm_release_page_clean(arg1_page
);
1353 arg1
= kmap_atomic(arg1_page
, KM_USER0
);
1355 arg2
= kmap_atomic(arg2_page
, KM_USER1
);
1357 retval
= handler(svm
, arg1
, arg2
, opaque
);
1359 kunmap_atomic(arg1
, KM_USER0
);
1361 kunmap_atomic(arg2
, KM_USER1
);
1363 kvm_release_page_dirty(arg1_page
);
1365 kvm_release_page_dirty(arg2_page
);
1370 static int nested_svm_exit_handled_real(struct vcpu_svm
*svm
,
1375 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1376 bool kvm_overrides
= *(bool *)opaque
;
1377 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1379 if (kvm_overrides
) {
1380 switch (exit_code
) {
1384 /* For now we are always handling NPFs when using them */
1389 /* When we're shadowing, trap PFs */
1390 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1399 switch (exit_code
) {
1400 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1401 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1402 if (nested_vmcb
->control
.intercept_cr_read
& cr_bits
)
1406 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1407 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1408 if (nested_vmcb
->control
.intercept_cr_write
& cr_bits
)
1412 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1413 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1414 if (nested_vmcb
->control
.intercept_dr_read
& dr_bits
)
1418 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1419 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1420 if (nested_vmcb
->control
.intercept_dr_write
& dr_bits
)
1424 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1425 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1426 if (nested_vmcb
->control
.intercept_exceptions
& excp_bits
)
1431 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1432 nsvm_printk("exit code: 0x%x\n", exit_code
);
1433 if (nested_vmcb
->control
.intercept
& exit_bits
)
1441 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
,
1442 void *arg1
, void *arg2
,
1445 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1446 u8
*msrpm
= (u8
*)arg2
;
1448 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1449 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1451 if (!(nested_vmcb
->control
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1459 case 0xc0000000 ... 0xc0001fff:
1460 t0
= (8192 + msr
- 0xc0000000) * 2;
1464 case 0xc0010000 ... 0xc0011fff:
1465 t0
= (16384 + msr
- 0xc0010000) * 2;
1473 if (msrpm
[t1
] & ((1 << param
) << t0
))
1479 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
)
1481 bool k
= kvm_override
;
1483 switch (svm
->vmcb
->control
.exit_code
) {
1485 return nested_svm_do(svm
, svm
->nested_vmcb
,
1486 svm
->nested_vmcb_msrpm
, NULL
,
1487 nested_svm_exit_handled_msr
);
1491 return nested_svm_do(svm
, svm
->nested_vmcb
, 0, &k
,
1492 nested_svm_exit_handled_real
);
1495 static int nested_svm_vmexit_real(struct vcpu_svm
*svm
, void *arg1
,
1496 void *arg2
, void *opaque
)
1498 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1499 struct vmcb
*hsave
= svm
->hsave
;
1500 u64 nested_save
[] = { nested_vmcb
->save
.cr0
,
1501 nested_vmcb
->save
.cr3
,
1502 nested_vmcb
->save
.cr4
,
1503 nested_vmcb
->save
.efer
,
1504 nested_vmcb
->control
.intercept_cr_read
,
1505 nested_vmcb
->control
.intercept_cr_write
,
1506 nested_vmcb
->control
.intercept_dr_read
,
1507 nested_vmcb
->control
.intercept_dr_write
,
1508 nested_vmcb
->control
.intercept_exceptions
,
1509 nested_vmcb
->control
.intercept
,
1510 nested_vmcb
->control
.msrpm_base_pa
,
1511 nested_vmcb
->control
.iopm_base_pa
,
1512 nested_vmcb
->control
.tsc_offset
};
1514 /* Give the current vmcb to the guest */
1515 memcpy(nested_vmcb
, svm
->vmcb
, sizeof(struct vmcb
));
1516 nested_vmcb
->save
.cr0
= nested_save
[0];
1518 nested_vmcb
->save
.cr3
= nested_save
[1];
1519 nested_vmcb
->save
.cr4
= nested_save
[2];
1520 nested_vmcb
->save
.efer
= nested_save
[3];
1521 nested_vmcb
->control
.intercept_cr_read
= nested_save
[4];
1522 nested_vmcb
->control
.intercept_cr_write
= nested_save
[5];
1523 nested_vmcb
->control
.intercept_dr_read
= nested_save
[6];
1524 nested_vmcb
->control
.intercept_dr_write
= nested_save
[7];
1525 nested_vmcb
->control
.intercept_exceptions
= nested_save
[8];
1526 nested_vmcb
->control
.intercept
= nested_save
[9];
1527 nested_vmcb
->control
.msrpm_base_pa
= nested_save
[10];
1528 nested_vmcb
->control
.iopm_base_pa
= nested_save
[11];
1529 nested_vmcb
->control
.tsc_offset
= nested_save
[12];
1531 /* We always set V_INTR_MASKING and remember the old value in hflags */
1532 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1533 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1535 if ((nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) &&
1536 (nested_vmcb
->control
.int_vector
)) {
1537 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1538 nested_vmcb
->control
.int_vector
);
1541 /* Restore the original control entries */
1542 svm
->vmcb
->control
= hsave
->control
;
1544 /* Kill any pending exceptions */
1545 if (svm
->vcpu
.arch
.exception
.pending
== true)
1546 nsvm_printk("WARNING: Pending Exception\n");
1547 svm
->vcpu
.arch
.exception
.pending
= false;
1549 /* Restore selected save entries */
1550 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1551 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1552 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1553 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1554 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1555 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1556 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1557 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1558 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1559 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1561 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1562 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1564 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1566 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1567 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1568 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1569 svm
->vmcb
->save
.dr7
= 0;
1570 svm
->vmcb
->save
.cpl
= 0;
1571 svm
->vmcb
->control
.exit_int_info
= 0;
1573 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1574 /* Exit nested SVM mode */
1575 svm
->nested_vmcb
= 0;
1580 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1582 nsvm_printk("VMexit\n");
1583 if (nested_svm_do(svm
, svm
->nested_vmcb
, 0,
1584 NULL
, nested_svm_vmexit_real
))
1587 kvm_mmu_reset_context(&svm
->vcpu
);
1588 kvm_mmu_load(&svm
->vcpu
);
1593 static int nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
, void *arg1
,
1594 void *arg2
, void *opaque
)
1597 u32
*nested_msrpm
= (u32
*)arg1
;
1598 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1599 svm
->nested_msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1600 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested_msrpm
);
1605 static int nested_svm_vmrun(struct vcpu_svm
*svm
, void *arg1
,
1606 void *arg2
, void *opaque
)
1608 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1609 struct vmcb
*hsave
= svm
->hsave
;
1611 /* nested_vmcb is our indicator if nested SVM is activated */
1612 svm
->nested_vmcb
= svm
->vmcb
->save
.rax
;
1614 /* Clear internal status */
1615 svm
->vcpu
.arch
.exception
.pending
= false;
1617 /* Save the old vmcb, so we don't need to pick what we save, but
1618 can restore everything when a VMEXIT occurs */
1619 memcpy(hsave
, svm
->vmcb
, sizeof(struct vmcb
));
1620 /* We need to remember the original CR3 in the SPT case */
1622 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1623 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1624 hsave
->save
.rip
= svm
->next_rip
;
1626 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1627 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1629 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1631 /* Load the nested guest state */
1632 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1633 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1634 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1635 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1636 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1637 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1638 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1639 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1640 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1641 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1643 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1644 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1646 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1647 kvm_mmu_reset_context(&svm
->vcpu
);
1649 svm
->vmcb
->save
.cr2
= nested_vmcb
->save
.cr2
;
1650 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1651 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1652 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1653 /* In case we don't even reach vcpu_run, the fields are not updated */
1654 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1655 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1656 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1657 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1658 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1659 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1661 /* We don't want a nested guest to be more powerful than the guest,
1662 so all intercepts are ORed */
1663 svm
->vmcb
->control
.intercept_cr_read
|=
1664 nested_vmcb
->control
.intercept_cr_read
;
1665 svm
->vmcb
->control
.intercept_cr_write
|=
1666 nested_vmcb
->control
.intercept_cr_write
;
1667 svm
->vmcb
->control
.intercept_dr_read
|=
1668 nested_vmcb
->control
.intercept_dr_read
;
1669 svm
->vmcb
->control
.intercept_dr_write
|=
1670 nested_vmcb
->control
.intercept_dr_write
;
1671 svm
->vmcb
->control
.intercept_exceptions
|=
1672 nested_vmcb
->control
.intercept_exceptions
;
1674 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1676 svm
->nested_vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1678 force_new_asid(&svm
->vcpu
);
1679 svm
->vmcb
->control
.exit_int_info
= nested_vmcb
->control
.exit_int_info
;
1680 svm
->vmcb
->control
.exit_int_info_err
= nested_vmcb
->control
.exit_int_info_err
;
1681 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1682 if (nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) {
1683 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1684 nested_vmcb
->control
.int_ctl
);
1686 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1687 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1689 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1691 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1692 nested_vmcb
->control
.exit_int_info
,
1693 nested_vmcb
->control
.int_state
);
1695 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1696 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1697 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1698 if (nested_vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)
1699 nsvm_printk("Injecting Event: 0x%x\n",
1700 nested_vmcb
->control
.event_inj
);
1701 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1702 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1704 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1709 static int nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1711 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1712 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1713 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1714 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1715 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1716 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1717 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1718 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1719 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1720 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1721 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1722 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1727 static int nested_svm_vmload(struct vcpu_svm
*svm
, void *nested_vmcb
,
1728 void *arg2
, void *opaque
)
1730 return nested_svm_vmloadsave((struct vmcb
*)nested_vmcb
, svm
->vmcb
);
1733 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
1734 void *arg2
, void *opaque
)
1736 return nested_svm_vmloadsave(svm
->vmcb
, (struct vmcb
*)nested_vmcb
);
1739 static int vmload_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1741 if (nested_svm_check_permissions(svm
))
1744 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1745 skip_emulated_instruction(&svm
->vcpu
);
1747 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmload
);
1752 static int vmsave_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1754 if (nested_svm_check_permissions(svm
))
1757 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1758 skip_emulated_instruction(&svm
->vcpu
);
1760 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmsave
);
1765 static int vmrun_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1767 nsvm_printk("VMrun\n");
1768 if (nested_svm_check_permissions(svm
))
1771 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1772 skip_emulated_instruction(&svm
->vcpu
);
1774 if (nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0,
1775 NULL
, nested_svm_vmrun
))
1778 if (nested_svm_do(svm
, svm
->nested_vmcb_msrpm
, 0,
1779 NULL
, nested_svm_vmrun_msrpm
))
1785 static int stgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1787 if (nested_svm_check_permissions(svm
))
1790 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1791 skip_emulated_instruction(&svm
->vcpu
);
1793 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1798 static int clgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1800 if (nested_svm_check_permissions(svm
))
1803 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1804 skip_emulated_instruction(&svm
->vcpu
);
1806 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1808 /* After a CLGI no interrupts should come */
1809 svm_clear_vintr(svm
);
1810 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
1815 static int invalid_op_interception(struct vcpu_svm
*svm
,
1816 struct kvm_run
*kvm_run
)
1818 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1822 static int task_switch_interception(struct vcpu_svm
*svm
,
1823 struct kvm_run
*kvm_run
)
1827 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
1828 if (svm
->vmcb
->control
.exit_info_2
&
1829 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
1830 return kvm_task_switch(&svm
->vcpu
, tss_selector
,
1832 if (svm
->vmcb
->control
.exit_info_2
&
1833 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
1834 return kvm_task_switch(&svm
->vcpu
, tss_selector
,
1836 return kvm_task_switch(&svm
->vcpu
, tss_selector
, TASK_SWITCH_CALL
);
1839 static int cpuid_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1841 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1842 kvm_emulate_cpuid(&svm
->vcpu
);
1846 static int invlpg_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1848 if (emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, 0) != EMULATE_DONE
)
1849 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1853 static int emulate_on_interception(struct vcpu_svm
*svm
,
1854 struct kvm_run
*kvm_run
)
1856 if (emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0) != EMULATE_DONE
)
1857 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1861 static int cr8_write_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1863 emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0);
1864 if (irqchip_in_kernel(svm
->vcpu
.kvm
))
1866 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
1870 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
1872 struct vcpu_svm
*svm
= to_svm(vcpu
);
1875 case MSR_IA32_TIME_STAMP_COUNTER
: {
1879 *data
= svm
->vmcb
->control
.tsc_offset
+ tsc
;
1883 *data
= svm
->vmcb
->save
.star
;
1885 #ifdef CONFIG_X86_64
1887 *data
= svm
->vmcb
->save
.lstar
;
1890 *data
= svm
->vmcb
->save
.cstar
;
1892 case MSR_KERNEL_GS_BASE
:
1893 *data
= svm
->vmcb
->save
.kernel_gs_base
;
1895 case MSR_SYSCALL_MASK
:
1896 *data
= svm
->vmcb
->save
.sfmask
;
1899 case MSR_IA32_SYSENTER_CS
:
1900 *data
= svm
->vmcb
->save
.sysenter_cs
;
1902 case MSR_IA32_SYSENTER_EIP
:
1903 *data
= svm
->vmcb
->save
.sysenter_eip
;
1905 case MSR_IA32_SYSENTER_ESP
:
1906 *data
= svm
->vmcb
->save
.sysenter_esp
;
1908 /* Nobody will change the following 5 values in the VMCB so
1909 we can safely return them on rdmsr. They will always be 0
1910 until LBRV is implemented. */
1911 case MSR_IA32_DEBUGCTLMSR
:
1912 *data
= svm
->vmcb
->save
.dbgctl
;
1914 case MSR_IA32_LASTBRANCHFROMIP
:
1915 *data
= svm
->vmcb
->save
.br_from
;
1917 case MSR_IA32_LASTBRANCHTOIP
:
1918 *data
= svm
->vmcb
->save
.br_to
;
1920 case MSR_IA32_LASTINTFROMIP
:
1921 *data
= svm
->vmcb
->save
.last_excp_from
;
1923 case MSR_IA32_LASTINTTOIP
:
1924 *data
= svm
->vmcb
->save
.last_excp_to
;
1926 case MSR_VM_HSAVE_PA
:
1927 *data
= svm
->hsave_msr
;
1932 case MSR_IA32_UCODE_REV
:
1936 return kvm_get_msr_common(vcpu
, ecx
, data
);
1941 static int rdmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1943 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1946 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
))
1947 kvm_inject_gp(&svm
->vcpu
, 0);
1949 KVMTRACE_3D(MSR_READ
, &svm
->vcpu
, ecx
, (u32
)data
,
1950 (u32
)(data
>> 32), handler
);
1952 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
1953 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
1954 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1955 skip_emulated_instruction(&svm
->vcpu
);
1960 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
1962 struct vcpu_svm
*svm
= to_svm(vcpu
);
1965 case MSR_IA32_TIME_STAMP_COUNTER
: {
1969 svm
->vmcb
->control
.tsc_offset
= data
- tsc
;
1973 svm
->vmcb
->save
.star
= data
;
1975 #ifdef CONFIG_X86_64
1977 svm
->vmcb
->save
.lstar
= data
;
1980 svm
->vmcb
->save
.cstar
= data
;
1982 case MSR_KERNEL_GS_BASE
:
1983 svm
->vmcb
->save
.kernel_gs_base
= data
;
1985 case MSR_SYSCALL_MASK
:
1986 svm
->vmcb
->save
.sfmask
= data
;
1989 case MSR_IA32_SYSENTER_CS
:
1990 svm
->vmcb
->save
.sysenter_cs
= data
;
1992 case MSR_IA32_SYSENTER_EIP
:
1993 svm
->vmcb
->save
.sysenter_eip
= data
;
1995 case MSR_IA32_SYSENTER_ESP
:
1996 svm
->vmcb
->save
.sysenter_esp
= data
;
1998 case MSR_IA32_DEBUGCTLMSR
:
1999 if (!svm_has(SVM_FEATURE_LBRV
)) {
2000 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2004 if (data
& DEBUGCTL_RESERVED_BITS
)
2007 svm
->vmcb
->save
.dbgctl
= data
;
2008 if (data
& (1ULL<<0))
2009 svm_enable_lbrv(svm
);
2011 svm_disable_lbrv(svm
);
2013 case MSR_K7_EVNTSEL0
:
2014 case MSR_K7_EVNTSEL1
:
2015 case MSR_K7_EVNTSEL2
:
2016 case MSR_K7_EVNTSEL3
:
2017 case MSR_K7_PERFCTR0
:
2018 case MSR_K7_PERFCTR1
:
2019 case MSR_K7_PERFCTR2
:
2020 case MSR_K7_PERFCTR3
:
2022 * Just discard all writes to the performance counters; this
2023 * should keep both older linux and windows 64-bit guests
2026 pr_unimpl(vcpu
, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2029 case MSR_VM_HSAVE_PA
:
2030 svm
->hsave_msr
= data
;
2033 return kvm_set_msr_common(vcpu
, ecx
, data
);
2038 static int wrmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2040 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2041 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2042 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2044 KVMTRACE_3D(MSR_WRITE
, &svm
->vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2047 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2048 if (svm_set_msr(&svm
->vcpu
, ecx
, data
))
2049 kvm_inject_gp(&svm
->vcpu
, 0);
2051 skip_emulated_instruction(&svm
->vcpu
);
2055 static int msr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2057 if (svm
->vmcb
->control
.exit_info_1
)
2058 return wrmsr_interception(svm
, kvm_run
);
2060 return rdmsr_interception(svm
, kvm_run
);
2063 static int interrupt_window_interception(struct vcpu_svm
*svm
,
2064 struct kvm_run
*kvm_run
)
2066 KVMTRACE_0D(PEND_INTR
, &svm
->vcpu
, handler
);
2068 svm_clear_vintr(svm
);
2069 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2071 * If the user space waits to inject interrupts, exit as soon as
2074 if (kvm_run
->request_interrupt_window
&&
2075 !svm
->vcpu
.arch
.irq_summary
) {
2076 ++svm
->vcpu
.stat
.irq_window_exits
;
2077 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2084 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
,
2085 struct kvm_run
*kvm_run
) = {
2086 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2087 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2088 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2089 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2091 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2092 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2093 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2094 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2095 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2096 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2097 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2098 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2099 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2100 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2101 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2102 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2103 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2104 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2105 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2106 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2107 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2108 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2109 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2110 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2111 [SVM_EXIT_INTR
] = intr_interception
,
2112 [SVM_EXIT_NMI
] = nmi_interception
,
2113 [SVM_EXIT_SMI
] = nop_on_interception
,
2114 [SVM_EXIT_INIT
] = nop_on_interception
,
2115 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2116 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2117 [SVM_EXIT_CPUID
] = cpuid_interception
,
2118 [SVM_EXIT_INVD
] = emulate_on_interception
,
2119 [SVM_EXIT_HLT
] = halt_interception
,
2120 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2121 [SVM_EXIT_INVLPGA
] = invalid_op_interception
,
2122 [SVM_EXIT_IOIO
] = io_interception
,
2123 [SVM_EXIT_MSR
] = msr_interception
,
2124 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2125 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2126 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2127 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2128 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2129 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2130 [SVM_EXIT_STGI
] = stgi_interception
,
2131 [SVM_EXIT_CLGI
] = clgi_interception
,
2132 [SVM_EXIT_SKINIT
] = invalid_op_interception
,
2133 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2134 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2135 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2136 [SVM_EXIT_NPF
] = pf_interception
,
2139 static int handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2141 struct vcpu_svm
*svm
= to_svm(vcpu
);
2142 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2144 KVMTRACE_3D(VMEXIT
, vcpu
, exit_code
, (u32
)svm
->vmcb
->save
.rip
,
2145 (u32
)((u64
)svm
->vmcb
->save
.rip
>> 32), entryexit
);
2147 if (is_nested(svm
)) {
2148 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2149 exit_code
, svm
->vmcb
->control
.exit_info_1
,
2150 svm
->vmcb
->control
.exit_info_2
, svm
->vmcb
->save
.rip
);
2151 if (nested_svm_exit_handled(svm
, true)) {
2152 nested_svm_vmexit(svm
);
2153 nsvm_printk("-> #VMEXIT\n");
2160 if ((vcpu
->arch
.cr0
^ svm
->vmcb
->save
.cr0
) & X86_CR0_PG
) {
2161 svm_set_cr0(vcpu
, svm
->vmcb
->save
.cr0
);
2164 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2165 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2166 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2167 if (!load_pdptrs(vcpu
, vcpu
->arch
.cr3
)) {
2168 kvm_inject_gp(vcpu
, 0);
2173 kvm_mmu_reset_context(vcpu
);
2180 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2181 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2182 kvm_run
->fail_entry
.hardware_entry_failure_reason
2183 = svm
->vmcb
->control
.exit_code
;
2187 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2188 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2189 exit_code
!= SVM_EXIT_NPF
)
2190 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2192 __func__
, svm
->vmcb
->control
.exit_int_info
,
2195 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2196 || !svm_exit_handlers
[exit_code
]) {
2197 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2198 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2202 return svm_exit_handlers
[exit_code
](svm
, kvm_run
);
2205 static void reload_tss(struct kvm_vcpu
*vcpu
)
2207 int cpu
= raw_smp_processor_id();
2209 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2210 svm_data
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2214 static void pre_svm_run(struct vcpu_svm
*svm
)
2216 int cpu
= raw_smp_processor_id();
2218 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2220 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2221 if (svm
->vcpu
.cpu
!= cpu
||
2222 svm
->asid_generation
!= svm_data
->asid_generation
)
2223 new_asid(svm
, svm_data
);
2227 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2229 struct vmcb_control_area
*control
;
2231 KVMTRACE_1D(INJ_VIRQ
, &svm
->vcpu
, (u32
)irq
, handler
);
2233 ++svm
->vcpu
.stat
.irq_injections
;
2234 control
= &svm
->vmcb
->control
;
2235 control
->int_vector
= irq
;
2236 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2237 control
->int_ctl
|= V_IRQ_MASK
|
2238 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2241 static void svm_set_irq(struct kvm_vcpu
*vcpu
, int irq
)
2243 struct vcpu_svm
*svm
= to_svm(vcpu
);
2245 nested_svm_intr(svm
);
2247 svm_inject_irq(svm
, irq
);
2250 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
)
2252 struct vcpu_svm
*svm
= to_svm(vcpu
);
2253 struct vmcb
*vmcb
= svm
->vmcb
;
2256 if (!irqchip_in_kernel(vcpu
->kvm
) || vcpu
->arch
.apic
->vapic_addr
)
2259 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2261 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
2265 tpr
= kvm_lapic_get_cr8(vcpu
) << 4;
2267 if (tpr
>= (max_irr
& 0xf0))
2268 vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2271 static void svm_intr_assist(struct kvm_vcpu
*vcpu
)
2273 struct vcpu_svm
*svm
= to_svm(vcpu
);
2274 struct vmcb
*vmcb
= svm
->vmcb
;
2275 int intr_vector
= -1;
2277 if ((vmcb
->control
.exit_int_info
& SVM_EVTINJ_VALID
) &&
2278 ((vmcb
->control
.exit_int_info
& SVM_EVTINJ_TYPE_MASK
) == 0)) {
2279 intr_vector
= vmcb
->control
.exit_int_info
&
2280 SVM_EVTINJ_VEC_MASK
;
2281 vmcb
->control
.exit_int_info
= 0;
2282 svm_inject_irq(svm
, intr_vector
);
2286 if (vmcb
->control
.int_ctl
& V_IRQ_MASK
)
2289 if (!kvm_cpu_has_interrupt(vcpu
))
2292 if (nested_svm_intr(svm
))
2295 if (!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
))
2298 if (!(vmcb
->save
.rflags
& X86_EFLAGS_IF
) ||
2299 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) ||
2300 (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)) {
2301 /* unable to deliver irq, set pending irq */
2303 svm_inject_irq(svm
, 0x0);
2306 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2307 intr_vector
= kvm_cpu_get_interrupt(vcpu
);
2308 svm_inject_irq(svm
, intr_vector
);
2310 update_cr8_intercept(vcpu
);
2313 static void kvm_reput_irq(struct vcpu_svm
*svm
)
2315 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2317 if ((control
->int_ctl
& V_IRQ_MASK
)
2318 && !irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2319 control
->int_ctl
&= ~V_IRQ_MASK
;
2320 push_irq(&svm
->vcpu
, control
->int_vector
);
2323 svm
->vcpu
.arch
.interrupt_window_open
=
2324 !(control
->int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2325 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
2328 static void svm_do_inject_vector(struct vcpu_svm
*svm
)
2330 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2331 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
2332 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
2333 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
2335 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
2336 if (!vcpu
->arch
.irq_pending
[word_index
])
2337 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
2338 svm_inject_irq(svm
, irq
);
2341 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
2342 struct kvm_run
*kvm_run
)
2344 struct vcpu_svm
*svm
= to_svm(vcpu
);
2345 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2347 if (nested_svm_intr(svm
))
2350 svm
->vcpu
.arch
.interrupt_window_open
=
2351 (!(control
->int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2352 (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
) &&
2353 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
));
2355 if (svm
->vcpu
.arch
.interrupt_window_open
&& svm
->vcpu
.arch
.irq_summary
)
2357 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2359 svm_do_inject_vector(svm
);
2362 * Interrupts blocked. Wait for unblock.
2364 if (!svm
->vcpu
.arch
.interrupt_window_open
&&
2365 (svm
->vcpu
.arch
.irq_summary
|| kvm_run
->request_interrupt_window
))
2368 svm_clear_vintr(svm
);
2371 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2376 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2378 force_new_asid(vcpu
);
2381 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2385 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2387 struct vcpu_svm
*svm
= to_svm(vcpu
);
2389 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2390 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2391 kvm_lapic_set_tpr(vcpu
, cr8
);
2395 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2397 struct vcpu_svm
*svm
= to_svm(vcpu
);
2400 if (!irqchip_in_kernel(vcpu
->kvm
))
2403 cr8
= kvm_get_cr8(vcpu
);
2404 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2405 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2408 #ifdef CONFIG_X86_64
2414 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2416 struct vcpu_svm
*svm
= to_svm(vcpu
);
2421 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2422 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2423 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2427 sync_lapic_to_cr8(vcpu
);
2429 save_host_msrs(vcpu
);
2430 fs_selector
= kvm_read_fs();
2431 gs_selector
= kvm_read_gs();
2432 ldt_selector
= kvm_read_ldt();
2433 svm
->host_cr2
= kvm_read_cr2();
2434 if (!is_nested(svm
))
2435 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2436 /* required for live migration with NPT */
2438 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2445 "push %%"R
"bp; \n\t"
2446 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2447 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2448 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2449 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2450 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2451 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2452 #ifdef CONFIG_X86_64
2453 "mov %c[r8](%[svm]), %%r8 \n\t"
2454 "mov %c[r9](%[svm]), %%r9 \n\t"
2455 "mov %c[r10](%[svm]), %%r10 \n\t"
2456 "mov %c[r11](%[svm]), %%r11 \n\t"
2457 "mov %c[r12](%[svm]), %%r12 \n\t"
2458 "mov %c[r13](%[svm]), %%r13 \n\t"
2459 "mov %c[r14](%[svm]), %%r14 \n\t"
2460 "mov %c[r15](%[svm]), %%r15 \n\t"
2463 /* Enter guest mode */
2465 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2466 __ex(SVM_VMLOAD
) "\n\t"
2467 __ex(SVM_VMRUN
) "\n\t"
2468 __ex(SVM_VMSAVE
) "\n\t"
2471 /* Save guest registers, load host registers */
2472 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2473 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2474 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2475 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2476 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2477 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2478 #ifdef CONFIG_X86_64
2479 "mov %%r8, %c[r8](%[svm]) \n\t"
2480 "mov %%r9, %c[r9](%[svm]) \n\t"
2481 "mov %%r10, %c[r10](%[svm]) \n\t"
2482 "mov %%r11, %c[r11](%[svm]) \n\t"
2483 "mov %%r12, %c[r12](%[svm]) \n\t"
2484 "mov %%r13, %c[r13](%[svm]) \n\t"
2485 "mov %%r14, %c[r14](%[svm]) \n\t"
2486 "mov %%r15, %c[r15](%[svm]) \n\t"
2491 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2492 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2493 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2494 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2495 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2496 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2497 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2498 #ifdef CONFIG_X86_64
2499 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2500 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2501 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2502 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2503 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2504 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2505 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2506 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2509 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2510 #ifdef CONFIG_X86_64
2511 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2515 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2516 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2517 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2518 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2520 kvm_write_cr2(svm
->host_cr2
);
2522 kvm_load_fs(fs_selector
);
2523 kvm_load_gs(gs_selector
);
2524 kvm_load_ldt(ldt_selector
);
2525 load_host_msrs(vcpu
);
2529 local_irq_disable();
2533 sync_cr8_to_lapic(vcpu
);
2540 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2542 struct vcpu_svm
*svm
= to_svm(vcpu
);
2545 svm
->vmcb
->control
.nested_cr3
= root
;
2546 force_new_asid(vcpu
);
2550 svm
->vmcb
->save
.cr3
= root
;
2551 force_new_asid(vcpu
);
2553 if (vcpu
->fpu_active
) {
2554 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
2555 svm
->vmcb
->save
.cr0
|= X86_CR0_TS
;
2556 vcpu
->fpu_active
= 0;
2560 static int is_disabled(void)
2564 rdmsrl(MSR_VM_CR
, vm_cr
);
2565 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2572 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2575 * Patch in the VMMCALL instruction:
2577 hypercall
[0] = 0x0f;
2578 hypercall
[1] = 0x01;
2579 hypercall
[2] = 0xd9;
2582 static void svm_check_processor_compat(void *rtn
)
2587 static bool svm_cpu_has_accelerated_tpr(void)
2592 static int get_npt_level(void)
2594 #ifdef CONFIG_X86_64
2595 return PT64_ROOT_LEVEL
;
2597 return PT32E_ROOT_LEVEL
;
2601 static int svm_get_mt_mask_shift(void)
2606 static struct kvm_x86_ops svm_x86_ops
= {
2607 .cpu_has_kvm_support
= has_svm
,
2608 .disabled_by_bios
= is_disabled
,
2609 .hardware_setup
= svm_hardware_setup
,
2610 .hardware_unsetup
= svm_hardware_unsetup
,
2611 .check_processor_compatibility
= svm_check_processor_compat
,
2612 .hardware_enable
= svm_hardware_enable
,
2613 .hardware_disable
= svm_hardware_disable
,
2614 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2616 .vcpu_create
= svm_create_vcpu
,
2617 .vcpu_free
= svm_free_vcpu
,
2618 .vcpu_reset
= svm_vcpu_reset
,
2620 .prepare_guest_switch
= svm_prepare_guest_switch
,
2621 .vcpu_load
= svm_vcpu_load
,
2622 .vcpu_put
= svm_vcpu_put
,
2624 .set_guest_debug
= svm_guest_debug
,
2625 .get_msr
= svm_get_msr
,
2626 .set_msr
= svm_set_msr
,
2627 .get_segment_base
= svm_get_segment_base
,
2628 .get_segment
= svm_get_segment
,
2629 .set_segment
= svm_set_segment
,
2630 .get_cpl
= svm_get_cpl
,
2631 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
2632 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
2633 .set_cr0
= svm_set_cr0
,
2634 .set_cr3
= svm_set_cr3
,
2635 .set_cr4
= svm_set_cr4
,
2636 .set_efer
= svm_set_efer
,
2637 .get_idt
= svm_get_idt
,
2638 .set_idt
= svm_set_idt
,
2639 .get_gdt
= svm_get_gdt
,
2640 .set_gdt
= svm_set_gdt
,
2641 .get_dr
= svm_get_dr
,
2642 .set_dr
= svm_set_dr
,
2643 .get_rflags
= svm_get_rflags
,
2644 .set_rflags
= svm_set_rflags
,
2646 .tlb_flush
= svm_flush_tlb
,
2648 .run
= svm_vcpu_run
,
2649 .handle_exit
= handle_exit
,
2650 .skip_emulated_instruction
= skip_emulated_instruction
,
2651 .patch_hypercall
= svm_patch_hypercall
,
2652 .get_irq
= svm_get_irq
,
2653 .set_irq
= svm_set_irq
,
2654 .queue_exception
= svm_queue_exception
,
2655 .exception_injected
= svm_exception_injected
,
2656 .inject_pending_irq
= svm_intr_assist
,
2657 .inject_pending_vectors
= do_interrupt_requests
,
2659 .set_tss_addr
= svm_set_tss_addr
,
2660 .get_tdp_level
= get_npt_level
,
2661 .get_mt_mask_shift
= svm_get_mt_mask_shift
,
2664 static int __init
svm_init(void)
2666 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
2670 static void __exit
svm_exit(void)
2675 module_init(svm_init
)
2676 module_exit(svm_exit
)