2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
131 module_param(ple_gap
, int, S_IRUGO
);
133 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
134 module_param(ple_window
, int, S_IRUGO
);
136 extern const ulong vmx_return
;
138 #define NR_AUTOLOAD_MSRS 8
139 #define VMCS02_POOL_SIZE 1
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
156 struct list_head loaded_vmcss_on_cpu_link
;
159 struct shared_msr_entry
{
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
178 typedef u64 natural_width
;
179 struct __packed vmcs12
{
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
186 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding
[7]; /* room for future expansion */
192 u64 vm_exit_msr_store_addr
;
193 u64 vm_exit_msr_load_addr
;
194 u64 vm_entry_msr_load_addr
;
196 u64 virtual_apic_page_addr
;
197 u64 apic_access_addr
;
199 u64 guest_physical_address
;
200 u64 vmcs_link_pointer
;
201 u64 guest_ia32_debugctl
;
204 u64 guest_ia32_perf_global_ctrl
;
212 u64 host_ia32_perf_global_ctrl
;
213 u64 padding64
[8]; /* room for future expansion */
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
220 natural_width cr0_guest_host_mask
;
221 natural_width cr4_guest_host_mask
;
222 natural_width cr0_read_shadow
;
223 natural_width cr4_read_shadow
;
224 natural_width cr3_target_value0
;
225 natural_width cr3_target_value1
;
226 natural_width cr3_target_value2
;
227 natural_width cr3_target_value3
;
228 natural_width exit_qualification
;
229 natural_width guest_linear_address
;
230 natural_width guest_cr0
;
231 natural_width guest_cr3
;
232 natural_width guest_cr4
;
233 natural_width guest_es_base
;
234 natural_width guest_cs_base
;
235 natural_width guest_ss_base
;
236 natural_width guest_ds_base
;
237 natural_width guest_fs_base
;
238 natural_width guest_gs_base
;
239 natural_width guest_ldtr_base
;
240 natural_width guest_tr_base
;
241 natural_width guest_gdtr_base
;
242 natural_width guest_idtr_base
;
243 natural_width guest_dr7
;
244 natural_width guest_rsp
;
245 natural_width guest_rip
;
246 natural_width guest_rflags
;
247 natural_width guest_pending_dbg_exceptions
;
248 natural_width guest_sysenter_esp
;
249 natural_width guest_sysenter_eip
;
250 natural_width host_cr0
;
251 natural_width host_cr3
;
252 natural_width host_cr4
;
253 natural_width host_fs_base
;
254 natural_width host_gs_base
;
255 natural_width host_tr_base
;
256 natural_width host_gdtr_base
;
257 natural_width host_idtr_base
;
258 natural_width host_ia32_sysenter_esp
;
259 natural_width host_ia32_sysenter_eip
;
260 natural_width host_rsp
;
261 natural_width host_rip
;
262 natural_width paddingl
[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control
;
264 u32 cpu_based_vm_exec_control
;
265 u32 exception_bitmap
;
266 u32 page_fault_error_code_mask
;
267 u32 page_fault_error_code_match
;
268 u32 cr3_target_count
;
269 u32 vm_exit_controls
;
270 u32 vm_exit_msr_store_count
;
271 u32 vm_exit_msr_load_count
;
272 u32 vm_entry_controls
;
273 u32 vm_entry_msr_load_count
;
274 u32 vm_entry_intr_info_field
;
275 u32 vm_entry_exception_error_code
;
276 u32 vm_entry_instruction_len
;
278 u32 secondary_vm_exec_control
;
279 u32 vm_instruction_error
;
281 u32 vm_exit_intr_info
;
282 u32 vm_exit_intr_error_code
;
283 u32 idt_vectoring_info_field
;
284 u32 idt_vectoring_error_code
;
285 u32 vm_exit_instruction_len
;
286 u32 vmx_instruction_info
;
293 u32 guest_ldtr_limit
;
295 u32 guest_gdtr_limit
;
296 u32 guest_idtr_limit
;
297 u32 guest_es_ar_bytes
;
298 u32 guest_cs_ar_bytes
;
299 u32 guest_ss_ar_bytes
;
300 u32 guest_ds_ar_bytes
;
301 u32 guest_fs_ar_bytes
;
302 u32 guest_gs_ar_bytes
;
303 u32 guest_ldtr_ar_bytes
;
304 u32 guest_tr_ar_bytes
;
305 u32 guest_interruptibility_info
;
306 u32 guest_activity_state
;
307 u32 guest_sysenter_cs
;
308 u32 host_ia32_sysenter_cs
;
309 u32 vmx_preemption_timer_value
;
310 u32 padding32
[7]; /* room for future expansion */
311 u16 virtual_processor_id
;
312 u16 guest_es_selector
;
313 u16 guest_cs_selector
;
314 u16 guest_ss_selector
;
315 u16 guest_ds_selector
;
316 u16 guest_fs_selector
;
317 u16 guest_gs_selector
;
318 u16 guest_ldtr_selector
;
319 u16 guest_tr_selector
;
320 u16 host_es_selector
;
321 u16 host_cs_selector
;
322 u16 host_ss_selector
;
323 u16 host_ds_selector
;
324 u16 host_fs_selector
;
325 u16 host_gs_selector
;
326 u16 host_tr_selector
;
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
334 #define VMCS12_REVISION 0x11e57ed0
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
341 #define VMCS12_SIZE 0x1000
343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
345 struct list_head list
;
347 struct loaded_vmcs vmcs02
;
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
355 /* Has the level1 guest done vmxon? */
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
361 /* The host-usable pointer to the above */
362 struct page
*current_vmcs12_page
;
363 struct vmcs12
*current_vmcs12
;
364 struct vmcs
*current_shadow_vmcs
;
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
369 bool sync_shadow_vmcs
;
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool
;
374 u64 vmcs01_tsc_offset
;
375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending
;
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
381 struct page
*apic_access_page
;
382 u64 msr_ia32_feature_control
;
384 struct hrtimer preemption_timer
;
385 bool preemption_timer_expired
;
387 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
391 #define POSTED_INTR_ON 0
392 /* Posted-Interrupt Descriptor */
394 u32 pir
[8]; /* Posted interrupt requested */
395 u32 control
; /* bit 0 of control is outstanding notification bit */
399 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
401 return test_and_set_bit(POSTED_INTR_ON
,
402 (unsigned long *)&pi_desc
->control
);
405 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
407 return test_and_clear_bit(POSTED_INTR_ON
,
408 (unsigned long *)&pi_desc
->control
);
411 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
413 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
417 struct kvm_vcpu vcpu
;
418 unsigned long host_rsp
;
420 bool nmi_known_unmasked
;
422 u32 idt_vectoring_info
;
424 struct shared_msr_entry
*guest_msrs
;
427 unsigned long host_idt_base
;
429 u64 msr_host_kernel_gs_base
;
430 u64 msr_guest_kernel_gs_base
;
432 u32 vm_entry_controls_shadow
;
433 u32 vm_exit_controls_shadow
;
435 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
436 * non-nested (L1) guest, it always points to vmcs01. For a nested
437 * guest (L2), it points to a different VMCS.
439 struct loaded_vmcs vmcs01
;
440 struct loaded_vmcs
*loaded_vmcs
;
441 bool __launched
; /* temporary, used in vmx_vcpu_run */
442 struct msr_autoload
{
444 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
445 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
449 u16 fs_sel
, gs_sel
, ldt_sel
;
453 int gs_ldt_reload_needed
;
454 int fs_reload_needed
;
455 u64 msr_host_bndcfgs
;
460 struct kvm_segment segs
[8];
463 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
464 struct kvm_save_segment
{
472 bool emulation_required
;
474 /* Support for vnmi-less CPUs */
475 int soft_vnmi_blocked
;
477 s64 vnmi_blocked_time
;
482 /* Posted interrupt descriptor */
483 struct pi_desc pi_desc
;
485 /* Support for a guest hypervisor (nested VMX) */
486 struct nested_vmx nested
;
488 /* Dynamic PLE window. */
490 bool ple_window_dirty
;
493 enum segment_cache_field
{
502 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
504 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
507 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
508 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
509 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
510 [number##_HIGH] = VMCS12_OFFSET(name)+4
513 static unsigned long shadow_read_only_fields
[] = {
515 * We do NOT shadow fields that are modified when L0
516 * traps and emulates any vmx instruction (e.g. VMPTRLD,
517 * VMXON...) executed by L1.
518 * For example, VM_INSTRUCTION_ERROR is read
519 * by L1 if a vmx instruction fails (part of the error path).
520 * Note the code assumes this logic. If for some reason
521 * we start shadowing these fields then we need to
522 * force a shadow sync when L0 emulates vmx instructions
523 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
524 * by nested_vmx_failValid)
528 VM_EXIT_INSTRUCTION_LEN
,
529 IDT_VECTORING_INFO_FIELD
,
530 IDT_VECTORING_ERROR_CODE
,
531 VM_EXIT_INTR_ERROR_CODE
,
533 GUEST_LINEAR_ADDRESS
,
534 GUEST_PHYSICAL_ADDRESS
536 static int max_shadow_read_only_fields
=
537 ARRAY_SIZE(shadow_read_only_fields
);
539 static unsigned long shadow_read_write_fields
[] = {
545 GUEST_INTERRUPTIBILITY_INFO
,
558 CPU_BASED_VM_EXEC_CONTROL
,
559 VM_ENTRY_EXCEPTION_ERROR_CODE
,
560 VM_ENTRY_INTR_INFO_FIELD
,
561 VM_ENTRY_INSTRUCTION_LEN
,
562 VM_ENTRY_EXCEPTION_ERROR_CODE
,
568 static int max_shadow_read_write_fields
=
569 ARRAY_SIZE(shadow_read_write_fields
);
571 static const unsigned short vmcs_field_to_offset_table
[] = {
572 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
573 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
574 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
575 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
576 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
577 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
578 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
579 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
580 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
581 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
582 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
583 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
584 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
585 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
586 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
587 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
588 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
589 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
590 FIELD64(MSR_BITMAP
, msr_bitmap
),
591 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
592 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
593 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
594 FIELD64(TSC_OFFSET
, tsc_offset
),
595 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
596 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
597 FIELD64(EPT_POINTER
, ept_pointer
),
598 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
599 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
600 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
601 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
602 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
603 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
604 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
605 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
606 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
607 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
608 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
609 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
610 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
611 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
612 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
613 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
614 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
615 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
616 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
617 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
618 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
619 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
620 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
621 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
622 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
623 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
624 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
625 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
626 FIELD(TPR_THRESHOLD
, tpr_threshold
),
627 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
628 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
629 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
630 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
631 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
632 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
633 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
634 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
635 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
636 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
637 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
638 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
639 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
640 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
641 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
642 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
643 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
644 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
645 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
646 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
647 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
648 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
649 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
650 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
651 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
652 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
653 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
654 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
655 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
656 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
657 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
658 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
659 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
660 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
661 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
662 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
663 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
664 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
665 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
666 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
667 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
668 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
669 FIELD(GUEST_CR0
, guest_cr0
),
670 FIELD(GUEST_CR3
, guest_cr3
),
671 FIELD(GUEST_CR4
, guest_cr4
),
672 FIELD(GUEST_ES_BASE
, guest_es_base
),
673 FIELD(GUEST_CS_BASE
, guest_cs_base
),
674 FIELD(GUEST_SS_BASE
, guest_ss_base
),
675 FIELD(GUEST_DS_BASE
, guest_ds_base
),
676 FIELD(GUEST_FS_BASE
, guest_fs_base
),
677 FIELD(GUEST_GS_BASE
, guest_gs_base
),
678 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
679 FIELD(GUEST_TR_BASE
, guest_tr_base
),
680 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
681 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
682 FIELD(GUEST_DR7
, guest_dr7
),
683 FIELD(GUEST_RSP
, guest_rsp
),
684 FIELD(GUEST_RIP
, guest_rip
),
685 FIELD(GUEST_RFLAGS
, guest_rflags
),
686 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
687 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
688 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
689 FIELD(HOST_CR0
, host_cr0
),
690 FIELD(HOST_CR3
, host_cr3
),
691 FIELD(HOST_CR4
, host_cr4
),
692 FIELD(HOST_FS_BASE
, host_fs_base
),
693 FIELD(HOST_GS_BASE
, host_gs_base
),
694 FIELD(HOST_TR_BASE
, host_tr_base
),
695 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
696 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
697 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
698 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
699 FIELD(HOST_RSP
, host_rsp
),
700 FIELD(HOST_RIP
, host_rip
),
702 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
704 static inline short vmcs_field_to_offset(unsigned long field
)
706 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
708 return vmcs_field_to_offset_table
[field
];
711 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
713 return to_vmx(vcpu
)->nested
.current_vmcs12
;
716 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
718 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
719 if (is_error_page(page
))
725 static void nested_release_page(struct page
*page
)
727 kvm_release_page_dirty(page
);
730 static void nested_release_page_clean(struct page
*page
)
732 kvm_release_page_clean(page
);
735 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
736 static u64
construct_eptp(unsigned long root_hpa
);
737 static void kvm_cpu_vmxon(u64 addr
);
738 static void kvm_cpu_vmxoff(void);
739 static bool vmx_mpx_supported(void);
740 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
741 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
742 struct kvm_segment
*var
, int seg
);
743 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
744 struct kvm_segment
*var
, int seg
);
745 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
746 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
747 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
748 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
749 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
751 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
752 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
754 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
755 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
757 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
758 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
760 static unsigned long *vmx_io_bitmap_a
;
761 static unsigned long *vmx_io_bitmap_b
;
762 static unsigned long *vmx_msr_bitmap_legacy
;
763 static unsigned long *vmx_msr_bitmap_longmode
;
764 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
765 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
766 static unsigned long *vmx_vmread_bitmap
;
767 static unsigned long *vmx_vmwrite_bitmap
;
769 static bool cpu_has_load_ia32_efer
;
770 static bool cpu_has_load_perf_global_ctrl
;
772 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
773 static DEFINE_SPINLOCK(vmx_vpid_lock
);
775 static struct vmcs_config
{
779 u32 pin_based_exec_ctrl
;
780 u32 cpu_based_exec_ctrl
;
781 u32 cpu_based_2nd_exec_ctrl
;
786 static struct vmx_capability
{
791 #define VMX_SEGMENT_FIELD(seg) \
792 [VCPU_SREG_##seg] = { \
793 .selector = GUEST_##seg##_SELECTOR, \
794 .base = GUEST_##seg##_BASE, \
795 .limit = GUEST_##seg##_LIMIT, \
796 .ar_bytes = GUEST_##seg##_AR_BYTES, \
799 static const struct kvm_vmx_segment_field
{
804 } kvm_vmx_segment_fields
[] = {
805 VMX_SEGMENT_FIELD(CS
),
806 VMX_SEGMENT_FIELD(DS
),
807 VMX_SEGMENT_FIELD(ES
),
808 VMX_SEGMENT_FIELD(FS
),
809 VMX_SEGMENT_FIELD(GS
),
810 VMX_SEGMENT_FIELD(SS
),
811 VMX_SEGMENT_FIELD(TR
),
812 VMX_SEGMENT_FIELD(LDTR
),
815 static u64 host_efer
;
817 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
820 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
821 * away by decrementing the array size.
823 static const u32 vmx_msr_index
[] = {
825 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
827 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
830 static inline bool is_page_fault(u32 intr_info
)
832 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
833 INTR_INFO_VALID_MASK
)) ==
834 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
837 static inline bool is_no_device(u32 intr_info
)
839 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
840 INTR_INFO_VALID_MASK
)) ==
841 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
844 static inline bool is_invalid_opcode(u32 intr_info
)
846 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
847 INTR_INFO_VALID_MASK
)) ==
848 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
851 static inline bool is_external_interrupt(u32 intr_info
)
853 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
854 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
857 static inline bool is_machine_check(u32 intr_info
)
859 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
860 INTR_INFO_VALID_MASK
)) ==
861 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
864 static inline bool cpu_has_vmx_msr_bitmap(void)
866 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
869 static inline bool cpu_has_vmx_tpr_shadow(void)
871 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
874 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
876 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
879 static inline bool cpu_has_secondary_exec_ctrls(void)
881 return vmcs_config
.cpu_based_exec_ctrl
&
882 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
885 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
887 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
888 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
891 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
893 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
894 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
897 static inline bool cpu_has_vmx_apic_register_virt(void)
899 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
900 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
903 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
905 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
906 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
909 static inline bool cpu_has_vmx_posted_intr(void)
911 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
914 static inline bool cpu_has_vmx_apicv(void)
916 return cpu_has_vmx_apic_register_virt() &&
917 cpu_has_vmx_virtual_intr_delivery() &&
918 cpu_has_vmx_posted_intr();
921 static inline bool cpu_has_vmx_flexpriority(void)
923 return cpu_has_vmx_tpr_shadow() &&
924 cpu_has_vmx_virtualize_apic_accesses();
927 static inline bool cpu_has_vmx_ept_execute_only(void)
929 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
932 static inline bool cpu_has_vmx_eptp_uncacheable(void)
934 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
937 static inline bool cpu_has_vmx_eptp_writeback(void)
939 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
942 static inline bool cpu_has_vmx_ept_2m_page(void)
944 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
947 static inline bool cpu_has_vmx_ept_1g_page(void)
949 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
952 static inline bool cpu_has_vmx_ept_4levels(void)
954 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
957 static inline bool cpu_has_vmx_ept_ad_bits(void)
959 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
962 static inline bool cpu_has_vmx_invept_context(void)
964 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
967 static inline bool cpu_has_vmx_invept_global(void)
969 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
972 static inline bool cpu_has_vmx_invvpid_single(void)
974 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
977 static inline bool cpu_has_vmx_invvpid_global(void)
979 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
982 static inline bool cpu_has_vmx_ept(void)
984 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
985 SECONDARY_EXEC_ENABLE_EPT
;
988 static inline bool cpu_has_vmx_unrestricted_guest(void)
990 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
991 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
994 static inline bool cpu_has_vmx_ple(void)
996 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
997 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1000 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1002 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1005 static inline bool cpu_has_vmx_vpid(void)
1007 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1008 SECONDARY_EXEC_ENABLE_VPID
;
1011 static inline bool cpu_has_vmx_rdtscp(void)
1013 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1014 SECONDARY_EXEC_RDTSCP
;
1017 static inline bool cpu_has_vmx_invpcid(void)
1019 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1020 SECONDARY_EXEC_ENABLE_INVPCID
;
1023 static inline bool cpu_has_virtual_nmis(void)
1025 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1028 static inline bool cpu_has_vmx_wbinvd_exit(void)
1030 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1031 SECONDARY_EXEC_WBINVD_EXITING
;
1034 static inline bool cpu_has_vmx_shadow_vmcs(void)
1037 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1038 /* check if the cpu supports writing r/o exit information fields */
1039 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1042 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1043 SECONDARY_EXEC_SHADOW_VMCS
;
1046 static inline bool report_flexpriority(void)
1048 return flexpriority_enabled
;
1051 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1053 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1056 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1058 return (vmcs12
->cpu_based_vm_exec_control
&
1059 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1060 (vmcs12
->secondary_vm_exec_control
& bit
);
1063 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1065 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1068 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1070 return vmcs12
->pin_based_vm_exec_control
&
1071 PIN_BASED_VMX_PREEMPTION_TIMER
;
1074 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1076 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1079 static inline bool is_exception(u32 intr_info
)
1081 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1082 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1085 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1087 unsigned long exit_qualification
);
1088 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1089 struct vmcs12
*vmcs12
,
1090 u32 reason
, unsigned long qualification
);
1092 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1096 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1097 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1102 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1108 } operand
= { vpid
, 0, gva
};
1110 asm volatile (__ex(ASM_VMX_INVVPID
)
1111 /* CF==1 or ZF==1 --> rc = -1 */
1112 "; ja 1f ; ud2 ; 1:"
1113 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1116 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1120 } operand
= {eptp
, gpa
};
1122 asm volatile (__ex(ASM_VMX_INVEPT
)
1123 /* CF==1 or ZF==1 --> rc = -1 */
1124 "; ja 1f ; ud2 ; 1:\n"
1125 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1128 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1132 i
= __find_msr_index(vmx
, msr
);
1134 return &vmx
->guest_msrs
[i
];
1138 static void vmcs_clear(struct vmcs
*vmcs
)
1140 u64 phys_addr
= __pa(vmcs
);
1143 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1144 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1147 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1151 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1153 vmcs_clear(loaded_vmcs
->vmcs
);
1154 loaded_vmcs
->cpu
= -1;
1155 loaded_vmcs
->launched
= 0;
1158 static void vmcs_load(struct vmcs
*vmcs
)
1160 u64 phys_addr
= __pa(vmcs
);
1163 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1164 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1167 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1173 * This bitmap is used to indicate whether the vmclear
1174 * operation is enabled on all cpus. All disabled by
1177 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1179 static inline void crash_enable_local_vmclear(int cpu
)
1181 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1184 static inline void crash_disable_local_vmclear(int cpu
)
1186 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1189 static inline int crash_local_vmclear_enabled(int cpu
)
1191 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1194 static void crash_vmclear_local_loaded_vmcss(void)
1196 int cpu
= raw_smp_processor_id();
1197 struct loaded_vmcs
*v
;
1199 if (!crash_local_vmclear_enabled(cpu
))
1202 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1203 loaded_vmcss_on_cpu_link
)
1204 vmcs_clear(v
->vmcs
);
1207 static inline void crash_enable_local_vmclear(int cpu
) { }
1208 static inline void crash_disable_local_vmclear(int cpu
) { }
1209 #endif /* CONFIG_KEXEC */
1211 static void __loaded_vmcs_clear(void *arg
)
1213 struct loaded_vmcs
*loaded_vmcs
= arg
;
1214 int cpu
= raw_smp_processor_id();
1216 if (loaded_vmcs
->cpu
!= cpu
)
1217 return; /* vcpu migration can race with cpu offline */
1218 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1219 per_cpu(current_vmcs
, cpu
) = NULL
;
1220 crash_disable_local_vmclear(cpu
);
1221 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1224 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1225 * is before setting loaded_vmcs->vcpu to -1 which is done in
1226 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1227 * then adds the vmcs into percpu list before it is deleted.
1231 loaded_vmcs_init(loaded_vmcs
);
1232 crash_enable_local_vmclear(cpu
);
1235 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1237 int cpu
= loaded_vmcs
->cpu
;
1240 smp_call_function_single(cpu
,
1241 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1244 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1249 if (cpu_has_vmx_invvpid_single())
1250 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1253 static inline void vpid_sync_vcpu_global(void)
1255 if (cpu_has_vmx_invvpid_global())
1256 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1259 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1261 if (cpu_has_vmx_invvpid_single())
1262 vpid_sync_vcpu_single(vmx
);
1264 vpid_sync_vcpu_global();
1267 static inline void ept_sync_global(void)
1269 if (cpu_has_vmx_invept_global())
1270 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1273 static inline void ept_sync_context(u64 eptp
)
1276 if (cpu_has_vmx_invept_context())
1277 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1283 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1285 unsigned long value
;
1287 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1288 : "=a"(value
) : "d"(field
) : "cc");
1292 static __always_inline u16
vmcs_read16(unsigned long field
)
1294 return vmcs_readl(field
);
1297 static __always_inline u32
vmcs_read32(unsigned long field
)
1299 return vmcs_readl(field
);
1302 static __always_inline u64
vmcs_read64(unsigned long field
)
1304 #ifdef CONFIG_X86_64
1305 return vmcs_readl(field
);
1307 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1311 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1313 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1314 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1318 static void vmcs_writel(unsigned long field
, unsigned long value
)
1322 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1323 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1324 if (unlikely(error
))
1325 vmwrite_error(field
, value
);
1328 static void vmcs_write16(unsigned long field
, u16 value
)
1330 vmcs_writel(field
, value
);
1333 static void vmcs_write32(unsigned long field
, u32 value
)
1335 vmcs_writel(field
, value
);
1338 static void vmcs_write64(unsigned long field
, u64 value
)
1340 vmcs_writel(field
, value
);
1341 #ifndef CONFIG_X86_64
1343 vmcs_writel(field
+1, value
>> 32);
1347 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1349 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1352 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1354 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1357 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1359 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1360 vmx
->vm_entry_controls_shadow
= val
;
1363 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1365 if (vmx
->vm_entry_controls_shadow
!= val
)
1366 vm_entry_controls_init(vmx
, val
);
1369 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1371 return vmx
->vm_entry_controls_shadow
;
1375 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1377 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1380 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1382 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1385 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1387 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1388 vmx
->vm_exit_controls_shadow
= val
;
1391 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1393 if (vmx
->vm_exit_controls_shadow
!= val
)
1394 vm_exit_controls_init(vmx
, val
);
1397 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1399 return vmx
->vm_exit_controls_shadow
;
1403 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1405 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1408 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1410 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1413 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1415 vmx
->segment_cache
.bitmask
= 0;
1418 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1422 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1424 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1425 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1426 vmx
->segment_cache
.bitmask
= 0;
1428 ret
= vmx
->segment_cache
.bitmask
& mask
;
1429 vmx
->segment_cache
.bitmask
|= mask
;
1433 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1435 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1437 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1438 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1442 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1444 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1446 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1447 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1451 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1453 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1455 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1456 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1460 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1462 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1464 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1465 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1469 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1473 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1474 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1475 if ((vcpu
->guest_debug
&
1476 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1477 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1478 eb
|= 1u << BP_VECTOR
;
1479 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1482 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1483 if (vcpu
->fpu_active
)
1484 eb
&= ~(1u << NM_VECTOR
);
1486 /* When we are running a nested L2 guest and L1 specified for it a
1487 * certain exception bitmap, we must trap the same exceptions and pass
1488 * them to L1. When running L2, we will only handle the exceptions
1489 * specified above if L1 did not want them.
1491 if (is_guest_mode(vcpu
))
1492 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1494 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1497 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1498 unsigned long entry
, unsigned long exit
)
1500 vm_entry_controls_clearbit(vmx
, entry
);
1501 vm_exit_controls_clearbit(vmx
, exit
);
1504 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1507 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1511 if (cpu_has_load_ia32_efer
) {
1512 clear_atomic_switch_msr_special(vmx
,
1513 VM_ENTRY_LOAD_IA32_EFER
,
1514 VM_EXIT_LOAD_IA32_EFER
);
1518 case MSR_CORE_PERF_GLOBAL_CTRL
:
1519 if (cpu_has_load_perf_global_ctrl
) {
1520 clear_atomic_switch_msr_special(vmx
,
1521 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1522 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1528 for (i
= 0; i
< m
->nr
; ++i
)
1529 if (m
->guest
[i
].index
== msr
)
1535 m
->guest
[i
] = m
->guest
[m
->nr
];
1536 m
->host
[i
] = m
->host
[m
->nr
];
1537 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1538 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1541 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1542 unsigned long entry
, unsigned long exit
,
1543 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1544 u64 guest_val
, u64 host_val
)
1546 vmcs_write64(guest_val_vmcs
, guest_val
);
1547 vmcs_write64(host_val_vmcs
, host_val
);
1548 vm_entry_controls_setbit(vmx
, entry
);
1549 vm_exit_controls_setbit(vmx
, exit
);
1552 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1553 u64 guest_val
, u64 host_val
)
1556 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1560 if (cpu_has_load_ia32_efer
) {
1561 add_atomic_switch_msr_special(vmx
,
1562 VM_ENTRY_LOAD_IA32_EFER
,
1563 VM_EXIT_LOAD_IA32_EFER
,
1566 guest_val
, host_val
);
1570 case MSR_CORE_PERF_GLOBAL_CTRL
:
1571 if (cpu_has_load_perf_global_ctrl
) {
1572 add_atomic_switch_msr_special(vmx
,
1573 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1574 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1575 GUEST_IA32_PERF_GLOBAL_CTRL
,
1576 HOST_IA32_PERF_GLOBAL_CTRL
,
1577 guest_val
, host_val
);
1583 for (i
= 0; i
< m
->nr
; ++i
)
1584 if (m
->guest
[i
].index
== msr
)
1587 if (i
== NR_AUTOLOAD_MSRS
) {
1588 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1589 "Can't add msr %x\n", msr
);
1591 } else if (i
== m
->nr
) {
1593 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1594 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1597 m
->guest
[i
].index
= msr
;
1598 m
->guest
[i
].value
= guest_val
;
1599 m
->host
[i
].index
= msr
;
1600 m
->host
[i
].value
= host_val
;
1603 static void reload_tss(void)
1606 * VT restores TR but not its size. Useless.
1608 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1609 struct desc_struct
*descs
;
1611 descs
= (void *)gdt
->address
;
1612 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1616 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1621 guest_efer
= vmx
->vcpu
.arch
.efer
;
1624 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1627 ignore_bits
= EFER_NX
| EFER_SCE
;
1628 #ifdef CONFIG_X86_64
1629 ignore_bits
|= EFER_LMA
| EFER_LME
;
1630 /* SCE is meaningful only in long mode on Intel */
1631 if (guest_efer
& EFER_LMA
)
1632 ignore_bits
&= ~(u64
)EFER_SCE
;
1634 guest_efer
&= ~ignore_bits
;
1635 guest_efer
|= host_efer
& ignore_bits
;
1636 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1637 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1639 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1640 /* On ept, can't emulate nx, and must switch nx atomically */
1641 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1642 guest_efer
= vmx
->vcpu
.arch
.efer
;
1643 if (!(guest_efer
& EFER_LMA
))
1644 guest_efer
&= ~EFER_LME
;
1645 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1652 static unsigned long segment_base(u16 selector
)
1654 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1655 struct desc_struct
*d
;
1656 unsigned long table_base
;
1659 if (!(selector
& ~3))
1662 table_base
= gdt
->address
;
1664 if (selector
& 4) { /* from ldt */
1665 u16 ldt_selector
= kvm_read_ldt();
1667 if (!(ldt_selector
& ~3))
1670 table_base
= segment_base(ldt_selector
);
1672 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1673 v
= get_desc_base(d
);
1674 #ifdef CONFIG_X86_64
1675 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1676 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1681 static inline unsigned long kvm_read_tr_base(void)
1684 asm("str %0" : "=g"(tr
));
1685 return segment_base(tr
);
1688 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1690 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1693 if (vmx
->host_state
.loaded
)
1696 vmx
->host_state
.loaded
= 1;
1698 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1699 * allow segment selectors with cpl > 0 or ti == 1.
1701 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1702 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1703 savesegment(fs
, vmx
->host_state
.fs_sel
);
1704 if (!(vmx
->host_state
.fs_sel
& 7)) {
1705 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1706 vmx
->host_state
.fs_reload_needed
= 0;
1708 vmcs_write16(HOST_FS_SELECTOR
, 0);
1709 vmx
->host_state
.fs_reload_needed
= 1;
1711 savesegment(gs
, vmx
->host_state
.gs_sel
);
1712 if (!(vmx
->host_state
.gs_sel
& 7))
1713 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1715 vmcs_write16(HOST_GS_SELECTOR
, 0);
1716 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1719 #ifdef CONFIG_X86_64
1720 savesegment(ds
, vmx
->host_state
.ds_sel
);
1721 savesegment(es
, vmx
->host_state
.es_sel
);
1724 #ifdef CONFIG_X86_64
1725 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1726 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1728 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1729 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1732 #ifdef CONFIG_X86_64
1733 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1734 if (is_long_mode(&vmx
->vcpu
))
1735 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1737 if (boot_cpu_has(X86_FEATURE_MPX
))
1738 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1739 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1740 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1741 vmx
->guest_msrs
[i
].data
,
1742 vmx
->guest_msrs
[i
].mask
);
1745 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1747 if (!vmx
->host_state
.loaded
)
1750 ++vmx
->vcpu
.stat
.host_state_reload
;
1751 vmx
->host_state
.loaded
= 0;
1752 #ifdef CONFIG_X86_64
1753 if (is_long_mode(&vmx
->vcpu
))
1754 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1756 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1757 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1758 #ifdef CONFIG_X86_64
1759 load_gs_index(vmx
->host_state
.gs_sel
);
1761 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1764 if (vmx
->host_state
.fs_reload_needed
)
1765 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1766 #ifdef CONFIG_X86_64
1767 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1768 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1769 loadsegment(es
, vmx
->host_state
.es_sel
);
1773 #ifdef CONFIG_X86_64
1774 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1776 if (vmx
->host_state
.msr_host_bndcfgs
)
1777 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1779 * If the FPU is not active (through the host task or
1780 * the guest vcpu), then restore the cr0.TS bit.
1782 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1784 load_gdt(&__get_cpu_var(host_gdt
));
1787 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1790 __vmx_load_host_state(vmx
);
1795 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1796 * vcpu mutex is already taken.
1798 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1800 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1801 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1804 kvm_cpu_vmxon(phys_addr
);
1805 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1806 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1808 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1809 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1810 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1813 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1814 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1815 unsigned long sysenter_esp
;
1817 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1818 local_irq_disable();
1819 crash_disable_local_vmclear(cpu
);
1822 * Read loaded_vmcs->cpu should be before fetching
1823 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1824 * See the comments in __loaded_vmcs_clear().
1828 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1829 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1830 crash_enable_local_vmclear(cpu
);
1834 * Linux uses per-cpu TSS and GDT, so set these when switching
1837 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1838 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1840 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1841 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1842 vmx
->loaded_vmcs
->cpu
= cpu
;
1846 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1848 __vmx_load_host_state(to_vmx(vcpu
));
1849 if (!vmm_exclusive
) {
1850 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1856 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1860 if (vcpu
->fpu_active
)
1862 vcpu
->fpu_active
= 1;
1863 cr0
= vmcs_readl(GUEST_CR0
);
1864 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1865 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1866 vmcs_writel(GUEST_CR0
, cr0
);
1867 update_exception_bitmap(vcpu
);
1868 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1869 if (is_guest_mode(vcpu
))
1870 vcpu
->arch
.cr0_guest_owned_bits
&=
1871 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1872 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1875 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1878 * Return the cr0 value that a nested guest would read. This is a combination
1879 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1880 * its hypervisor (cr0_read_shadow).
1882 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1884 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1885 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1887 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1889 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1890 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1893 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1895 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1896 * set this *before* calling this function.
1898 vmx_decache_cr0_guest_bits(vcpu
);
1899 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1900 update_exception_bitmap(vcpu
);
1901 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1902 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1903 if (is_guest_mode(vcpu
)) {
1905 * L1's specified read shadow might not contain the TS bit,
1906 * so now that we turned on shadowing of this bit, we need to
1907 * set this bit of the shadow. Like in nested_vmx_run we need
1908 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1909 * up-to-date here because we just decached cr0.TS (and we'll
1910 * only update vmcs12->guest_cr0 on nested exit).
1912 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1913 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1914 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1915 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1917 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1920 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1922 unsigned long rflags
, save_rflags
;
1924 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1925 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1926 rflags
= vmcs_readl(GUEST_RFLAGS
);
1927 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1928 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1929 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1930 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1932 to_vmx(vcpu
)->rflags
= rflags
;
1934 return to_vmx(vcpu
)->rflags
;
1937 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1939 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1940 to_vmx(vcpu
)->rflags
= rflags
;
1941 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1942 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1943 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1945 vmcs_writel(GUEST_RFLAGS
, rflags
);
1948 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1950 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1953 if (interruptibility
& GUEST_INTR_STATE_STI
)
1954 ret
|= KVM_X86_SHADOW_INT_STI
;
1955 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1956 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1961 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1963 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1964 u32 interruptibility
= interruptibility_old
;
1966 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1968 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1969 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1970 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1971 interruptibility
|= GUEST_INTR_STATE_STI
;
1973 if ((interruptibility
!= interruptibility_old
))
1974 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1977 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1981 rip
= kvm_rip_read(vcpu
);
1982 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1983 kvm_rip_write(vcpu
, rip
);
1985 /* skipping an emulated instruction also counts */
1986 vmx_set_interrupt_shadow(vcpu
, 0);
1990 * KVM wants to inject page-faults which it got to the guest. This function
1991 * checks whether in a nested guest, we need to inject them to L1 or L2.
1993 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1995 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1997 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2000 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2001 vmcs_read32(VM_EXIT_INTR_INFO
),
2002 vmcs_readl(EXIT_QUALIFICATION
));
2006 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2007 bool has_error_code
, u32 error_code
,
2010 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2011 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2013 if (!reinject
&& is_guest_mode(vcpu
) &&
2014 nested_vmx_check_exception(vcpu
, nr
))
2017 if (has_error_code
) {
2018 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2019 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2022 if (vmx
->rmode
.vm86_active
) {
2024 if (kvm_exception_is_soft(nr
))
2025 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2026 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2027 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2031 if (kvm_exception_is_soft(nr
)) {
2032 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2033 vmx
->vcpu
.arch
.event_exit_inst_len
);
2034 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2036 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2041 static bool vmx_rdtscp_supported(void)
2043 return cpu_has_vmx_rdtscp();
2046 static bool vmx_invpcid_supported(void)
2048 return cpu_has_vmx_invpcid() && enable_ept
;
2052 * Swap MSR entry in host/guest MSR entry array.
2054 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2056 struct shared_msr_entry tmp
;
2058 tmp
= vmx
->guest_msrs
[to
];
2059 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2060 vmx
->guest_msrs
[from
] = tmp
;
2063 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2065 unsigned long *msr_bitmap
;
2067 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2068 if (is_long_mode(vcpu
))
2069 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2071 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2073 if (is_long_mode(vcpu
))
2074 msr_bitmap
= vmx_msr_bitmap_longmode
;
2076 msr_bitmap
= vmx_msr_bitmap_legacy
;
2079 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2083 * Set up the vmcs to automatically save and restore system
2084 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2085 * mode, as fiddling with msrs is very expensive.
2087 static void setup_msrs(struct vcpu_vmx
*vmx
)
2089 int save_nmsrs
, index
;
2092 #ifdef CONFIG_X86_64
2093 if (is_long_mode(&vmx
->vcpu
)) {
2094 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2096 move_msr_up(vmx
, index
, save_nmsrs
++);
2097 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2099 move_msr_up(vmx
, index
, save_nmsrs
++);
2100 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2102 move_msr_up(vmx
, index
, save_nmsrs
++);
2103 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2104 if (index
>= 0 && vmx
->rdtscp_enabled
)
2105 move_msr_up(vmx
, index
, save_nmsrs
++);
2107 * MSR_STAR is only needed on long mode guests, and only
2108 * if efer.sce is enabled.
2110 index
= __find_msr_index(vmx
, MSR_STAR
);
2111 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2112 move_msr_up(vmx
, index
, save_nmsrs
++);
2115 index
= __find_msr_index(vmx
, MSR_EFER
);
2116 if (index
>= 0 && update_transition_efer(vmx
, index
))
2117 move_msr_up(vmx
, index
, save_nmsrs
++);
2119 vmx
->save_nmsrs
= save_nmsrs
;
2121 if (cpu_has_vmx_msr_bitmap())
2122 vmx_set_msr_bitmap(&vmx
->vcpu
);
2126 * reads and returns guest's timestamp counter "register"
2127 * guest_tsc = host_tsc + tsc_offset -- 21.3
2129 static u64
guest_read_tsc(void)
2131 u64 host_tsc
, tsc_offset
;
2134 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2135 return host_tsc
+ tsc_offset
;
2139 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2140 * counter, even if a nested guest (L2) is currently running.
2142 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2146 tsc_offset
= is_guest_mode(vcpu
) ?
2147 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2148 vmcs_read64(TSC_OFFSET
);
2149 return host_tsc
+ tsc_offset
;
2153 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2154 * software catchup for faster rates on slower CPUs.
2156 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2161 if (user_tsc_khz
> tsc_khz
) {
2162 vcpu
->arch
.tsc_catchup
= 1;
2163 vcpu
->arch
.tsc_always_catchup
= 1;
2165 WARN(1, "user requested TSC rate below hardware speed\n");
2168 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2170 return vmcs_read64(TSC_OFFSET
);
2174 * writes 'offset' into guest's timestamp counter offset register
2176 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2178 if (is_guest_mode(vcpu
)) {
2180 * We're here if L1 chose not to trap WRMSR to TSC. According
2181 * to the spec, this should set L1's TSC; The offset that L1
2182 * set for L2 remains unchanged, and still needs to be added
2183 * to the newly set TSC to get L2's TSC.
2185 struct vmcs12
*vmcs12
;
2186 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2187 /* recalculate vmcs02.TSC_OFFSET: */
2188 vmcs12
= get_vmcs12(vcpu
);
2189 vmcs_write64(TSC_OFFSET
, offset
+
2190 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2191 vmcs12
->tsc_offset
: 0));
2193 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2194 vmcs_read64(TSC_OFFSET
), offset
);
2195 vmcs_write64(TSC_OFFSET
, offset
);
2199 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2201 u64 offset
= vmcs_read64(TSC_OFFSET
);
2203 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2204 if (is_guest_mode(vcpu
)) {
2205 /* Even when running L2, the adjustment needs to apply to L1 */
2206 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2208 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2209 offset
+ adjustment
);
2212 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2214 return target_tsc
- native_read_tsc();
2217 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2219 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2220 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2224 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2225 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2226 * all guests if the "nested" module option is off, and can also be disabled
2227 * for a single guest by disabling its VMX cpuid bit.
2229 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2231 return nested
&& guest_cpuid_has_vmx(vcpu
);
2235 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2236 * returned for the various VMX controls MSRs when nested VMX is enabled.
2237 * The same values should also be used to verify that vmcs12 control fields are
2238 * valid during nested entry from L1 to L2.
2239 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2240 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2241 * bit in the high half is on if the corresponding bit in the control field
2242 * may be on. See also vmx_control_verify().
2243 * TODO: allow these variables to be modified (downgraded) by module options
2246 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2247 static u32 nested_vmx_true_procbased_ctls_low
;
2248 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2249 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2250 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2251 static u32 nested_vmx_true_exit_ctls_low
;
2252 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2253 static u32 nested_vmx_true_entry_ctls_low
;
2254 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2255 static u32 nested_vmx_ept_caps
;
2256 static __init
void nested_vmx_setup_ctls_msrs(void)
2259 * Note that as a general rule, the high half of the MSRs (bits in
2260 * the control fields which may be 1) should be initialized by the
2261 * intersection of the underlying hardware's MSR (i.e., features which
2262 * can be supported) and the list of features we want to expose -
2263 * because they are known to be properly supported in our code.
2264 * Also, usually, the low half of the MSRs (bits which must be 1) can
2265 * be set to 0, meaning that L1 may turn off any of these bits. The
2266 * reason is that if one of these bits is necessary, it will appear
2267 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2268 * fields of vmcs01 and vmcs02, will turn these bits off - and
2269 * nested_vmx_exit_handled() will not pass related exits to L1.
2270 * These rules have exceptions below.
2273 /* pin-based controls */
2274 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2275 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2276 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2277 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2278 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2279 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2280 PIN_BASED_VMX_PREEMPTION_TIMER
;
2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2284 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2285 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2287 nested_vmx_exit_ctls_high
&=
2288 #ifdef CONFIG_X86_64
2289 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2291 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2292 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2293 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2296 if (vmx_mpx_supported())
2297 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2299 /* We support free control of debug control saving. */
2300 nested_vmx_true_exit_ctls_low
= nested_vmx_exit_ctls_low
&
2301 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2303 /* entry controls */
2304 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2305 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2306 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2307 nested_vmx_entry_ctls_high
&=
2308 #ifdef CONFIG_X86_64
2309 VM_ENTRY_IA32E_MODE
|
2311 VM_ENTRY_LOAD_IA32_PAT
;
2312 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2313 VM_ENTRY_LOAD_IA32_EFER
);
2314 if (vmx_mpx_supported())
2315 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2317 /* We support free control of debug control loading. */
2318 nested_vmx_true_entry_ctls_low
= nested_vmx_entry_ctls_low
&
2319 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2321 /* cpu-based controls */
2322 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2323 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2324 nested_vmx_procbased_ctls_low
= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2325 nested_vmx_procbased_ctls_high
&=
2326 CPU_BASED_VIRTUAL_INTR_PENDING
|
2327 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2328 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2329 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2330 CPU_BASED_CR3_STORE_EXITING
|
2331 #ifdef CONFIG_X86_64
2332 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2334 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2335 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2336 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2337 CPU_BASED_PAUSE_EXITING
|
2338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2340 * We can allow some features even when not supported by the
2341 * hardware. For example, L1 can specify an MSR bitmap - and we
2342 * can use it to avoid exits to L1 - even when L0 runs L2
2343 * without MSR bitmaps.
2345 nested_vmx_procbased_ctls_high
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2346 CPU_BASED_USE_MSR_BITMAPS
;
2348 /* We support free control of CR3 access interception. */
2349 nested_vmx_true_procbased_ctls_low
= nested_vmx_procbased_ctls_low
&
2350 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2352 /* secondary cpu-based controls */
2353 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2354 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2355 nested_vmx_secondary_ctls_low
= 0;
2356 nested_vmx_secondary_ctls_high
&=
2357 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2358 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2359 SECONDARY_EXEC_WBINVD_EXITING
;
2362 /* nested EPT: emulate EPT also to L1 */
2363 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2364 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2365 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2367 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2369 * For nested guests, we don't do anything specific
2370 * for single context invalidation. Hence, only advertise
2371 * support for global context invalidation.
2373 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2375 nested_vmx_ept_caps
= 0;
2377 /* miscellaneous data */
2378 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2379 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2380 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2381 VMX_MISC_ACTIVITY_HLT
;
2382 nested_vmx_misc_high
= 0;
2385 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2388 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2390 return ((control
& high
) | low
) == control
;
2393 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2395 return low
| ((u64
)high
<< 32);
2398 /* Returns 0 on success, non-0 otherwise. */
2399 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2401 switch (msr_index
) {
2402 case MSR_IA32_VMX_BASIC
:
2404 * This MSR reports some information about VMX support. We
2405 * should return information about the VMX we emulate for the
2406 * guest, and the VMCS structure we give it - not about the
2407 * VMX support of the underlying hardware.
2409 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2410 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2411 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2413 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2414 case MSR_IA32_VMX_PINBASED_CTLS
:
2415 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2416 nested_vmx_pinbased_ctls_high
);
2418 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2419 *pdata
= vmx_control_msr(nested_vmx_true_procbased_ctls_low
,
2420 nested_vmx_procbased_ctls_high
);
2422 case MSR_IA32_VMX_PROCBASED_CTLS
:
2423 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2424 nested_vmx_procbased_ctls_high
);
2426 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2427 *pdata
= vmx_control_msr(nested_vmx_true_exit_ctls_low
,
2428 nested_vmx_exit_ctls_high
);
2430 case MSR_IA32_VMX_EXIT_CTLS
:
2431 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2432 nested_vmx_exit_ctls_high
);
2434 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2435 *pdata
= vmx_control_msr(nested_vmx_true_entry_ctls_low
,
2436 nested_vmx_entry_ctls_high
);
2438 case MSR_IA32_VMX_ENTRY_CTLS
:
2439 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2440 nested_vmx_entry_ctls_high
);
2442 case MSR_IA32_VMX_MISC
:
2443 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2444 nested_vmx_misc_high
);
2447 * These MSRs specify bits which the guest must keep fixed (on or off)
2448 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2449 * We picked the standard core2 setting.
2451 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2452 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2453 case MSR_IA32_VMX_CR0_FIXED0
:
2454 *pdata
= VMXON_CR0_ALWAYSON
;
2456 case MSR_IA32_VMX_CR0_FIXED1
:
2459 case MSR_IA32_VMX_CR4_FIXED0
:
2460 *pdata
= VMXON_CR4_ALWAYSON
;
2462 case MSR_IA32_VMX_CR4_FIXED1
:
2465 case MSR_IA32_VMX_VMCS_ENUM
:
2466 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2468 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2469 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2470 nested_vmx_secondary_ctls_high
);
2472 case MSR_IA32_VMX_EPT_VPID_CAP
:
2473 /* Currently, no nested vpid support */
2474 *pdata
= nested_vmx_ept_caps
;
2484 * Reads an msr value (of 'msr_index') into 'pdata'.
2485 * Returns 0 on success, non-0 otherwise.
2486 * Assumes vcpu_load() was already called.
2488 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2491 struct shared_msr_entry
*msr
;
2494 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2498 switch (msr_index
) {
2499 #ifdef CONFIG_X86_64
2501 data
= vmcs_readl(GUEST_FS_BASE
);
2504 data
= vmcs_readl(GUEST_GS_BASE
);
2506 case MSR_KERNEL_GS_BASE
:
2507 vmx_load_host_state(to_vmx(vcpu
));
2508 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2512 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2514 data
= guest_read_tsc();
2516 case MSR_IA32_SYSENTER_CS
:
2517 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2519 case MSR_IA32_SYSENTER_EIP
:
2520 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2522 case MSR_IA32_SYSENTER_ESP
:
2523 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2525 case MSR_IA32_BNDCFGS
:
2526 if (!vmx_mpx_supported())
2528 data
= vmcs_read64(GUEST_BNDCFGS
);
2530 case MSR_IA32_FEATURE_CONTROL
:
2531 if (!nested_vmx_allowed(vcpu
))
2533 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2535 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2536 if (!nested_vmx_allowed(vcpu
))
2538 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2540 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2542 /* Otherwise falls through */
2544 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2549 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2556 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2559 * Writes msr value into into the appropriate "register".
2560 * Returns 0 on success, non-0 otherwise.
2561 * Assumes vcpu_load() was already called.
2563 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2565 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2566 struct shared_msr_entry
*msr
;
2568 u32 msr_index
= msr_info
->index
;
2569 u64 data
= msr_info
->data
;
2571 switch (msr_index
) {
2573 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2575 #ifdef CONFIG_X86_64
2577 vmx_segment_cache_clear(vmx
);
2578 vmcs_writel(GUEST_FS_BASE
, data
);
2581 vmx_segment_cache_clear(vmx
);
2582 vmcs_writel(GUEST_GS_BASE
, data
);
2584 case MSR_KERNEL_GS_BASE
:
2585 vmx_load_host_state(vmx
);
2586 vmx
->msr_guest_kernel_gs_base
= data
;
2589 case MSR_IA32_SYSENTER_CS
:
2590 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2592 case MSR_IA32_SYSENTER_EIP
:
2593 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2595 case MSR_IA32_SYSENTER_ESP
:
2596 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2598 case MSR_IA32_BNDCFGS
:
2599 if (!vmx_mpx_supported())
2601 vmcs_write64(GUEST_BNDCFGS
, data
);
2604 kvm_write_tsc(vcpu
, msr_info
);
2606 case MSR_IA32_CR_PAT
:
2607 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2608 vmcs_write64(GUEST_IA32_PAT
, data
);
2609 vcpu
->arch
.pat
= data
;
2612 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2614 case MSR_IA32_TSC_ADJUST
:
2615 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2617 case MSR_IA32_FEATURE_CONTROL
:
2618 if (!nested_vmx_allowed(vcpu
) ||
2619 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2620 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2622 vmx
->nested
.msr_ia32_feature_control
= data
;
2623 if (msr_info
->host_initiated
&& data
== 0)
2624 vmx_leave_nested(vcpu
);
2626 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2627 return 1; /* they are read-only */
2629 if (!vmx
->rdtscp_enabled
)
2631 /* Check reserved bit, higher 32 bits should be zero */
2632 if ((data
>> 32) != 0)
2634 /* Otherwise falls through */
2636 msr
= find_msr_entry(vmx
, msr_index
);
2639 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2641 kvm_set_shared_msr(msr
->index
, msr
->data
,
2647 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2653 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2655 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2658 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2661 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2663 case VCPU_EXREG_PDPTR
:
2665 ept_save_pdptrs(vcpu
);
2672 static __init
int cpu_has_kvm_support(void)
2674 return cpu_has_vmx();
2677 static __init
int vmx_disabled_by_bios(void)
2681 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2682 if (msr
& FEATURE_CONTROL_LOCKED
) {
2683 /* launched w/ TXT and VMX disabled */
2684 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2687 /* launched w/o TXT and VMX only enabled w/ TXT */
2688 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2689 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2690 && !tboot_enabled()) {
2691 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2692 "activate TXT before enabling KVM\n");
2695 /* launched w/o TXT and VMX disabled */
2696 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2697 && !tboot_enabled())
2704 static void kvm_cpu_vmxon(u64 addr
)
2706 asm volatile (ASM_VMX_VMXON_RAX
2707 : : "a"(&addr
), "m"(addr
)
2711 static int hardware_enable(void *garbage
)
2713 int cpu
= raw_smp_processor_id();
2714 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2717 if (read_cr4() & X86_CR4_VMXE
)
2720 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2723 * Now we can enable the vmclear operation in kdump
2724 * since the loaded_vmcss_on_cpu list on this cpu
2725 * has been initialized.
2727 * Though the cpu is not in VMX operation now, there
2728 * is no problem to enable the vmclear operation
2729 * for the loaded_vmcss_on_cpu list is empty!
2731 crash_enable_local_vmclear(cpu
);
2733 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2735 test_bits
= FEATURE_CONTROL_LOCKED
;
2736 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2737 if (tboot_enabled())
2738 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2740 if ((old
& test_bits
) != test_bits
) {
2741 /* enable and lock */
2742 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2744 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2746 if (vmm_exclusive
) {
2747 kvm_cpu_vmxon(phys_addr
);
2751 native_store_gdt(&__get_cpu_var(host_gdt
));
2756 static void vmclear_local_loaded_vmcss(void)
2758 int cpu
= raw_smp_processor_id();
2759 struct loaded_vmcs
*v
, *n
;
2761 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2762 loaded_vmcss_on_cpu_link
)
2763 __loaded_vmcs_clear(v
);
2767 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2770 static void kvm_cpu_vmxoff(void)
2772 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2775 static void hardware_disable(void *garbage
)
2777 if (vmm_exclusive
) {
2778 vmclear_local_loaded_vmcss();
2781 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2784 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2785 u32 msr
, u32
*result
)
2787 u32 vmx_msr_low
, vmx_msr_high
;
2788 u32 ctl
= ctl_min
| ctl_opt
;
2790 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2792 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2793 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2795 /* Ensure minimum (required) set of control bits are supported. */
2803 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2805 u32 vmx_msr_low
, vmx_msr_high
;
2807 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2808 return vmx_msr_high
& ctl
;
2811 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2813 u32 vmx_msr_low
, vmx_msr_high
;
2814 u32 min
, opt
, min2
, opt2
;
2815 u32 _pin_based_exec_control
= 0;
2816 u32 _cpu_based_exec_control
= 0;
2817 u32 _cpu_based_2nd_exec_control
= 0;
2818 u32 _vmexit_control
= 0;
2819 u32 _vmentry_control
= 0;
2821 min
= CPU_BASED_HLT_EXITING
|
2822 #ifdef CONFIG_X86_64
2823 CPU_BASED_CR8_LOAD_EXITING
|
2824 CPU_BASED_CR8_STORE_EXITING
|
2826 CPU_BASED_CR3_LOAD_EXITING
|
2827 CPU_BASED_CR3_STORE_EXITING
|
2828 CPU_BASED_USE_IO_BITMAPS
|
2829 CPU_BASED_MOV_DR_EXITING
|
2830 CPU_BASED_USE_TSC_OFFSETING
|
2831 CPU_BASED_MWAIT_EXITING
|
2832 CPU_BASED_MONITOR_EXITING
|
2833 CPU_BASED_INVLPG_EXITING
|
2834 CPU_BASED_RDPMC_EXITING
;
2836 opt
= CPU_BASED_TPR_SHADOW
|
2837 CPU_BASED_USE_MSR_BITMAPS
|
2838 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2839 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2840 &_cpu_based_exec_control
) < 0)
2842 #ifdef CONFIG_X86_64
2843 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2844 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2845 ~CPU_BASED_CR8_STORE_EXITING
;
2847 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2849 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2850 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2851 SECONDARY_EXEC_WBINVD_EXITING
|
2852 SECONDARY_EXEC_ENABLE_VPID
|
2853 SECONDARY_EXEC_ENABLE_EPT
|
2854 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2855 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2856 SECONDARY_EXEC_RDTSCP
|
2857 SECONDARY_EXEC_ENABLE_INVPCID
|
2858 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2859 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2860 SECONDARY_EXEC_SHADOW_VMCS
;
2861 if (adjust_vmx_controls(min2
, opt2
,
2862 MSR_IA32_VMX_PROCBASED_CTLS2
,
2863 &_cpu_based_2nd_exec_control
) < 0)
2866 #ifndef CONFIG_X86_64
2867 if (!(_cpu_based_2nd_exec_control
&
2868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2869 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2872 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2873 _cpu_based_2nd_exec_control
&= ~(
2874 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2875 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2876 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2878 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2879 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2881 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2882 CPU_BASED_CR3_STORE_EXITING
|
2883 CPU_BASED_INVLPG_EXITING
);
2884 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2885 vmx_capability
.ept
, vmx_capability
.vpid
);
2888 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2889 #ifdef CONFIG_X86_64
2890 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2892 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2893 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2894 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2895 &_vmexit_control
) < 0)
2898 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2899 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2900 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2901 &_pin_based_exec_control
) < 0)
2904 if (!(_cpu_based_2nd_exec_control
&
2905 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2906 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2907 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2909 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2910 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2911 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2912 &_vmentry_control
) < 0)
2915 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2917 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2918 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2921 #ifdef CONFIG_X86_64
2922 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2923 if (vmx_msr_high
& (1u<<16))
2927 /* Require Write-Back (WB) memory type for VMCS accesses. */
2928 if (((vmx_msr_high
>> 18) & 15) != 6)
2931 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2932 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2933 vmcs_conf
->revision_id
= vmx_msr_low
;
2935 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2936 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2937 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2938 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2939 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2941 cpu_has_load_ia32_efer
=
2942 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2943 VM_ENTRY_LOAD_IA32_EFER
)
2944 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2945 VM_EXIT_LOAD_IA32_EFER
);
2947 cpu_has_load_perf_global_ctrl
=
2948 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2949 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2950 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2951 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2954 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2955 * but due to arrata below it can't be used. Workaround is to use
2956 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2958 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2963 * BC86,AAY89,BD102 (model 44)
2967 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2968 switch (boot_cpu_data
.x86_model
) {
2974 cpu_has_load_perf_global_ctrl
= false;
2975 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2976 "does not work properly. Using workaround\n");
2986 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2988 int node
= cpu_to_node(cpu
);
2992 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2995 vmcs
= page_address(pages
);
2996 memset(vmcs
, 0, vmcs_config
.size
);
2997 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3001 static struct vmcs
*alloc_vmcs(void)
3003 return alloc_vmcs_cpu(raw_smp_processor_id());
3006 static void free_vmcs(struct vmcs
*vmcs
)
3008 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3012 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3014 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3016 if (!loaded_vmcs
->vmcs
)
3018 loaded_vmcs_clear(loaded_vmcs
);
3019 free_vmcs(loaded_vmcs
->vmcs
);
3020 loaded_vmcs
->vmcs
= NULL
;
3023 static void free_kvm_area(void)
3027 for_each_possible_cpu(cpu
) {
3028 free_vmcs(per_cpu(vmxarea
, cpu
));
3029 per_cpu(vmxarea
, cpu
) = NULL
;
3033 static void init_vmcs_shadow_fields(void)
3037 /* No checks for read only fields yet */
3039 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3040 switch (shadow_read_write_fields
[i
]) {
3042 if (!vmx_mpx_supported())
3050 shadow_read_write_fields
[j
] =
3051 shadow_read_write_fields
[i
];
3054 max_shadow_read_write_fields
= j
;
3056 /* shadowed fields guest access without vmexit */
3057 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3058 clear_bit(shadow_read_write_fields
[i
],
3059 vmx_vmwrite_bitmap
);
3060 clear_bit(shadow_read_write_fields
[i
],
3063 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3064 clear_bit(shadow_read_only_fields
[i
],
3068 static __init
int alloc_kvm_area(void)
3072 for_each_possible_cpu(cpu
) {
3075 vmcs
= alloc_vmcs_cpu(cpu
);
3081 per_cpu(vmxarea
, cpu
) = vmcs
;
3086 static __init
int hardware_setup(void)
3088 if (setup_vmcs_config(&vmcs_config
) < 0)
3091 if (boot_cpu_has(X86_FEATURE_NX
))
3092 kvm_enable_efer_bits(EFER_NX
);
3094 if (!cpu_has_vmx_vpid())
3096 if (!cpu_has_vmx_shadow_vmcs())
3097 enable_shadow_vmcs
= 0;
3098 if (enable_shadow_vmcs
)
3099 init_vmcs_shadow_fields();
3101 if (!cpu_has_vmx_ept() ||
3102 !cpu_has_vmx_ept_4levels()) {
3104 enable_unrestricted_guest
= 0;
3105 enable_ept_ad_bits
= 0;
3108 if (!cpu_has_vmx_ept_ad_bits())
3109 enable_ept_ad_bits
= 0;
3111 if (!cpu_has_vmx_unrestricted_guest())
3112 enable_unrestricted_guest
= 0;
3114 if (!cpu_has_vmx_flexpriority())
3115 flexpriority_enabled
= 0;
3117 if (!cpu_has_vmx_tpr_shadow())
3118 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3120 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3121 kvm_disable_largepages();
3123 if (!cpu_has_vmx_ple())
3126 if (!cpu_has_vmx_apicv())
3130 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3132 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3133 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3134 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3138 nested_vmx_setup_ctls_msrs();
3140 return alloc_kvm_area();
3143 static __exit
void hardware_unsetup(void)
3148 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3150 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3153 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3154 struct kvm_segment
*save
)
3156 if (!emulate_invalid_guest_state
) {
3158 * CS and SS RPL should be equal during guest entry according
3159 * to VMX spec, but in reality it is not always so. Since vcpu
3160 * is in the middle of the transition from real mode to
3161 * protected mode it is safe to assume that RPL 0 is a good
3164 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3165 save
->selector
&= ~SELECTOR_RPL_MASK
;
3166 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3169 vmx_set_segment(vcpu
, save
, seg
);
3172 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3174 unsigned long flags
;
3175 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3178 * Update real mode segment cache. It may be not up-to-date if sement
3179 * register was written while vcpu was in a guest mode.
3181 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3182 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3183 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3184 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3185 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3186 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3188 vmx
->rmode
.vm86_active
= 0;
3190 vmx_segment_cache_clear(vmx
);
3192 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3194 flags
= vmcs_readl(GUEST_RFLAGS
);
3195 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3196 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3197 vmcs_writel(GUEST_RFLAGS
, flags
);
3199 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3200 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3202 update_exception_bitmap(vcpu
);
3204 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3205 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3206 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3207 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3208 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3209 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3212 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3214 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3215 struct kvm_segment var
= *save
;
3218 if (seg
== VCPU_SREG_CS
)
3221 if (!emulate_invalid_guest_state
) {
3222 var
.selector
= var
.base
>> 4;
3223 var
.base
= var
.base
& 0xffff0;
3233 if (save
->base
& 0xf)
3234 printk_once(KERN_WARNING
"kvm: segment base is not "
3235 "paragraph aligned when entering "
3236 "protected mode (seg=%d)", seg
);
3239 vmcs_write16(sf
->selector
, var
.selector
);
3240 vmcs_write32(sf
->base
, var
.base
);
3241 vmcs_write32(sf
->limit
, var
.limit
);
3242 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3245 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3247 unsigned long flags
;
3248 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3250 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3251 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3252 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3253 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3254 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3255 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3256 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3258 vmx
->rmode
.vm86_active
= 1;
3261 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3262 * vcpu. Warn the user that an update is overdue.
3264 if (!vcpu
->kvm
->arch
.tss_addr
)
3265 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3266 "called before entering vcpu\n");
3268 vmx_segment_cache_clear(vmx
);
3270 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3271 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3272 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3274 flags
= vmcs_readl(GUEST_RFLAGS
);
3275 vmx
->rmode
.save_rflags
= flags
;
3277 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3279 vmcs_writel(GUEST_RFLAGS
, flags
);
3280 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3281 update_exception_bitmap(vcpu
);
3283 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3284 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3285 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3286 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3287 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3288 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3290 kvm_mmu_reset_context(vcpu
);
3293 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3296 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3302 * Force kernel_gs_base reloading before EFER changes, as control
3303 * of this msr depends on is_long_mode().
3305 vmx_load_host_state(to_vmx(vcpu
));
3306 vcpu
->arch
.efer
= efer
;
3307 if (efer
& EFER_LMA
) {
3308 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3311 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3313 msr
->data
= efer
& ~EFER_LME
;
3318 #ifdef CONFIG_X86_64
3320 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3324 vmx_segment_cache_clear(to_vmx(vcpu
));
3326 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3327 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3328 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3330 vmcs_write32(GUEST_TR_AR_BYTES
,
3331 (guest_tr_ar
& ~AR_TYPE_MASK
)
3332 | AR_TYPE_BUSY_64_TSS
);
3334 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3337 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3339 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3340 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3345 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3347 vpid_sync_context(to_vmx(vcpu
));
3349 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3351 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3355 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3357 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3359 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3360 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3363 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3365 if (enable_ept
&& is_paging(vcpu
))
3366 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3367 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3370 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3372 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3374 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3375 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3378 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3380 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3382 if (!test_bit(VCPU_EXREG_PDPTR
,
3383 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3386 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3387 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3388 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3389 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3390 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3394 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3396 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3398 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3399 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3400 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3401 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3402 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3405 __set_bit(VCPU_EXREG_PDPTR
,
3406 (unsigned long *)&vcpu
->arch
.regs_avail
);
3407 __set_bit(VCPU_EXREG_PDPTR
,
3408 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3411 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3413 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3415 struct kvm_vcpu
*vcpu
)
3417 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3418 vmx_decache_cr3(vcpu
);
3419 if (!(cr0
& X86_CR0_PG
)) {
3420 /* From paging/starting to nonpaging */
3421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3422 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3423 (CPU_BASED_CR3_LOAD_EXITING
|
3424 CPU_BASED_CR3_STORE_EXITING
));
3425 vcpu
->arch
.cr0
= cr0
;
3426 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3427 } else if (!is_paging(vcpu
)) {
3428 /* From nonpaging to paging */
3429 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3430 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3431 ~(CPU_BASED_CR3_LOAD_EXITING
|
3432 CPU_BASED_CR3_STORE_EXITING
));
3433 vcpu
->arch
.cr0
= cr0
;
3434 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3437 if (!(cr0
& X86_CR0_WP
))
3438 *hw_cr0
&= ~X86_CR0_WP
;
3441 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3443 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3444 unsigned long hw_cr0
;
3446 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3447 if (enable_unrestricted_guest
)
3448 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3450 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3452 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3455 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3459 #ifdef CONFIG_X86_64
3460 if (vcpu
->arch
.efer
& EFER_LME
) {
3461 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3463 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3469 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3471 if (!vcpu
->fpu_active
)
3472 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3474 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3475 vmcs_writel(GUEST_CR0
, hw_cr0
);
3476 vcpu
->arch
.cr0
= cr0
;
3478 /* depends on vcpu->arch.cr0 to be set to a new value */
3479 vmx
->emulation_required
= emulation_required(vcpu
);
3482 static u64
construct_eptp(unsigned long root_hpa
)
3486 /* TODO write the value reading from MSR */
3487 eptp
= VMX_EPT_DEFAULT_MT
|
3488 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3489 if (enable_ept_ad_bits
)
3490 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3491 eptp
|= (root_hpa
& PAGE_MASK
);
3496 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3498 unsigned long guest_cr3
;
3503 eptp
= construct_eptp(cr3
);
3504 vmcs_write64(EPT_POINTER
, eptp
);
3505 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3506 guest_cr3
= kvm_read_cr3(vcpu
);
3508 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3509 ept_load_pdptrs(vcpu
);
3512 vmx_flush_tlb(vcpu
);
3513 vmcs_writel(GUEST_CR3
, guest_cr3
);
3516 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3518 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3519 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3521 if (cr4
& X86_CR4_VMXE
) {
3523 * To use VMXON (and later other VMX instructions), a guest
3524 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3525 * So basically the check on whether to allow nested VMX
3528 if (!nested_vmx_allowed(vcpu
))
3531 if (to_vmx(vcpu
)->nested
.vmxon
&&
3532 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3535 vcpu
->arch
.cr4
= cr4
;
3537 if (!is_paging(vcpu
)) {
3538 hw_cr4
&= ~X86_CR4_PAE
;
3539 hw_cr4
|= X86_CR4_PSE
;
3541 * SMEP/SMAP is disabled if CPU is in non-paging mode
3542 * in hardware. However KVM always uses paging mode to
3543 * emulate guest non-paging mode with TDP.
3544 * To emulate this behavior, SMEP/SMAP needs to be
3545 * manually disabled when guest switches to non-paging
3548 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3549 } else if (!(cr4
& X86_CR4_PAE
)) {
3550 hw_cr4
&= ~X86_CR4_PAE
;
3554 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3555 vmcs_writel(GUEST_CR4
, hw_cr4
);
3559 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3560 struct kvm_segment
*var
, int seg
)
3562 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3565 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3566 *var
= vmx
->rmode
.segs
[seg
];
3567 if (seg
== VCPU_SREG_TR
3568 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3570 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3571 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3574 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3575 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3576 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3577 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3578 var
->unusable
= (ar
>> 16) & 1;
3579 var
->type
= ar
& 15;
3580 var
->s
= (ar
>> 4) & 1;
3581 var
->dpl
= (ar
>> 5) & 3;
3583 * Some userspaces do not preserve unusable property. Since usable
3584 * segment has to be present according to VMX spec we can use present
3585 * property to amend userspace bug by making unusable segment always
3586 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3587 * segment as unusable.
3589 var
->present
= !var
->unusable
;
3590 var
->avl
= (ar
>> 12) & 1;
3591 var
->l
= (ar
>> 13) & 1;
3592 var
->db
= (ar
>> 14) & 1;
3593 var
->g
= (ar
>> 15) & 1;
3596 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3598 struct kvm_segment s
;
3600 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3601 vmx_get_segment(vcpu
, &s
, seg
);
3604 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3607 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3609 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3611 if (unlikely(vmx
->rmode
.vm86_active
))
3614 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3619 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3623 if (var
->unusable
|| !var
->present
)
3626 ar
= var
->type
& 15;
3627 ar
|= (var
->s
& 1) << 4;
3628 ar
|= (var
->dpl
& 3) << 5;
3629 ar
|= (var
->present
& 1) << 7;
3630 ar
|= (var
->avl
& 1) << 12;
3631 ar
|= (var
->l
& 1) << 13;
3632 ar
|= (var
->db
& 1) << 14;
3633 ar
|= (var
->g
& 1) << 15;
3639 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3640 struct kvm_segment
*var
, int seg
)
3642 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3643 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3645 vmx_segment_cache_clear(vmx
);
3647 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3648 vmx
->rmode
.segs
[seg
] = *var
;
3649 if (seg
== VCPU_SREG_TR
)
3650 vmcs_write16(sf
->selector
, var
->selector
);
3652 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3656 vmcs_writel(sf
->base
, var
->base
);
3657 vmcs_write32(sf
->limit
, var
->limit
);
3658 vmcs_write16(sf
->selector
, var
->selector
);
3661 * Fix the "Accessed" bit in AR field of segment registers for older
3663 * IA32 arch specifies that at the time of processor reset the
3664 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3665 * is setting it to 0 in the userland code. This causes invalid guest
3666 * state vmexit when "unrestricted guest" mode is turned on.
3667 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3668 * tree. Newer qemu binaries with that qemu fix would not need this
3671 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3672 var
->type
|= 0x1; /* Accessed */
3674 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3677 vmx
->emulation_required
= emulation_required(vcpu
);
3680 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3682 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3684 *db
= (ar
>> 14) & 1;
3685 *l
= (ar
>> 13) & 1;
3688 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3690 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3691 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3694 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3696 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3697 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3700 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3702 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3703 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3706 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3708 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3709 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3712 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3714 struct kvm_segment var
;
3717 vmx_get_segment(vcpu
, &var
, seg
);
3719 if (seg
== VCPU_SREG_CS
)
3721 ar
= vmx_segment_access_rights(&var
);
3723 if (var
.base
!= (var
.selector
<< 4))
3725 if (var
.limit
!= 0xffff)
3733 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3735 struct kvm_segment cs
;
3736 unsigned int cs_rpl
;
3738 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3739 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3743 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3747 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3748 if (cs
.dpl
> cs_rpl
)
3751 if (cs
.dpl
!= cs_rpl
)
3757 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3761 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3763 struct kvm_segment ss
;
3764 unsigned int ss_rpl
;
3766 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3767 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3771 if (ss
.type
!= 3 && ss
.type
!= 7)
3775 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3783 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3785 struct kvm_segment var
;
3788 vmx_get_segment(vcpu
, &var
, seg
);
3789 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3797 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3798 if (var
.dpl
< rpl
) /* DPL < RPL */
3802 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3808 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3810 struct kvm_segment tr
;
3812 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3816 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3818 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3826 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3828 struct kvm_segment ldtr
;
3830 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3834 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3844 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3846 struct kvm_segment cs
, ss
;
3848 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3849 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3851 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3852 (ss
.selector
& SELECTOR_RPL_MASK
));
3856 * Check if guest state is valid. Returns true if valid, false if
3858 * We assume that registers are always usable
3860 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3862 if (enable_unrestricted_guest
)
3865 /* real mode guest state checks */
3866 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3867 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3869 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3871 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3873 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3875 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3877 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3880 /* protected mode guest state checks */
3881 if (!cs_ss_rpl_check(vcpu
))
3883 if (!code_segment_valid(vcpu
))
3885 if (!stack_segment_valid(vcpu
))
3887 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3889 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3891 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3893 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3895 if (!tr_valid(vcpu
))
3897 if (!ldtr_valid(vcpu
))
3901 * - Add checks on RIP
3902 * - Add checks on RFLAGS
3908 static int init_rmode_tss(struct kvm
*kvm
)
3912 int r
, idx
, ret
= 0;
3914 idx
= srcu_read_lock(&kvm
->srcu
);
3915 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3916 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3919 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3920 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3921 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3924 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3927 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3931 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3932 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3939 srcu_read_unlock(&kvm
->srcu
, idx
);
3943 static int init_rmode_identity_map(struct kvm
*kvm
)
3946 pfn_t identity_map_pfn
;
3951 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3952 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3953 "haven't been allocated!\n");
3956 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3959 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3960 idx
= srcu_read_lock(&kvm
->srcu
);
3961 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3964 /* Set up identity-mapping pagetable for EPT in real mode */
3965 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3966 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3967 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3968 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3969 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3973 kvm
->arch
.ept_identity_pagetable_done
= true;
3976 srcu_read_unlock(&kvm
->srcu
, idx
);
3980 static void seg_setup(int seg
)
3982 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3985 vmcs_write16(sf
->selector
, 0);
3986 vmcs_writel(sf
->base
, 0);
3987 vmcs_write32(sf
->limit
, 0xffff);
3989 if (seg
== VCPU_SREG_CS
)
3990 ar
|= 0x08; /* code segment */
3992 vmcs_write32(sf
->ar_bytes
, ar
);
3995 static int alloc_apic_access_page(struct kvm
*kvm
)
3998 struct kvm_userspace_memory_region kvm_userspace_mem
;
4001 mutex_lock(&kvm
->slots_lock
);
4002 if (kvm
->arch
.apic_access_page
)
4004 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4005 kvm_userspace_mem
.flags
= 0;
4006 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
4007 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4008 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4012 page
= gfn_to_page(kvm
, 0xfee00);
4013 if (is_error_page(page
)) {
4018 kvm
->arch
.apic_access_page
= page
;
4020 mutex_unlock(&kvm
->slots_lock
);
4024 static int alloc_identity_pagetable(struct kvm
*kvm
)
4027 struct kvm_userspace_memory_region kvm_userspace_mem
;
4030 mutex_lock(&kvm
->slots_lock
);
4031 if (kvm
->arch
.ept_identity_pagetable
)
4033 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4034 kvm_userspace_mem
.flags
= 0;
4035 kvm_userspace_mem
.guest_phys_addr
=
4036 kvm
->arch
.ept_identity_map_addr
;
4037 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4038 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4042 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
4043 if (is_error_page(page
)) {
4048 kvm
->arch
.ept_identity_pagetable
= page
;
4050 mutex_unlock(&kvm
->slots_lock
);
4054 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4061 spin_lock(&vmx_vpid_lock
);
4062 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4063 if (vpid
< VMX_NR_VPIDS
) {
4065 __set_bit(vpid
, vmx_vpid_bitmap
);
4067 spin_unlock(&vmx_vpid_lock
);
4070 static void free_vpid(struct vcpu_vmx
*vmx
)
4074 spin_lock(&vmx_vpid_lock
);
4076 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4077 spin_unlock(&vmx_vpid_lock
);
4080 #define MSR_TYPE_R 1
4081 #define MSR_TYPE_W 2
4082 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4085 int f
= sizeof(unsigned long);
4087 if (!cpu_has_vmx_msr_bitmap())
4091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4092 * have the write-low and read-high bitmap offsets the wrong way round.
4093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4095 if (msr
<= 0x1fff) {
4096 if (type
& MSR_TYPE_R
)
4098 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4100 if (type
& MSR_TYPE_W
)
4102 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4104 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4106 if (type
& MSR_TYPE_R
)
4108 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4110 if (type
& MSR_TYPE_W
)
4112 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4117 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4120 int f
= sizeof(unsigned long);
4122 if (!cpu_has_vmx_msr_bitmap())
4126 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4127 * have the write-low and read-high bitmap offsets the wrong way round.
4128 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4130 if (msr
<= 0x1fff) {
4131 if (type
& MSR_TYPE_R
)
4133 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4135 if (type
& MSR_TYPE_W
)
4137 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4139 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4141 if (type
& MSR_TYPE_R
)
4143 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4145 if (type
& MSR_TYPE_W
)
4147 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4152 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4155 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4156 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4157 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4158 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4161 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4163 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4165 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4169 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4171 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4173 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4177 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4179 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4181 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4185 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4187 return enable_apicv
&& irqchip_in_kernel(kvm
);
4191 * Send interrupt to vcpu via posted interrupt way.
4192 * 1. If target vcpu is running(non-root mode), send posted interrupt
4193 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4194 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4195 * interrupt from PIR in next vmentry.
4197 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4199 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4202 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4205 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4206 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4208 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4209 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4210 POSTED_INTR_VECTOR
);
4213 kvm_vcpu_kick(vcpu
);
4216 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4218 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4220 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4223 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4226 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4232 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4233 * will not change in the lifetime of the guest.
4234 * Note that host-state that does change is set elsewhere. E.g., host-state
4235 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4237 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4243 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4244 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4245 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4247 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4248 #ifdef CONFIG_X86_64
4250 * Load null selectors, so we can avoid reloading them in
4251 * __vmx_load_host_state(), in case userspace uses the null selectors
4252 * too (the expected case).
4254 vmcs_write16(HOST_DS_SELECTOR
, 0);
4255 vmcs_write16(HOST_ES_SELECTOR
, 0);
4257 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4258 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4260 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4261 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4263 native_store_idt(&dt
);
4264 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4265 vmx
->host_idt_base
= dt
.address
;
4267 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4269 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4270 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4271 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4272 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4274 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4275 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4276 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4280 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4282 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4284 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4285 if (is_guest_mode(&vmx
->vcpu
))
4286 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4287 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4288 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4291 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4293 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4295 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4296 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4297 return pin_based_exec_ctrl
;
4300 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4302 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4304 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4305 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4307 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4308 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4309 #ifdef CONFIG_X86_64
4310 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4311 CPU_BASED_CR8_LOAD_EXITING
;
4315 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4316 CPU_BASED_CR3_LOAD_EXITING
|
4317 CPU_BASED_INVLPG_EXITING
;
4318 return exec_control
;
4321 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4323 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4324 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4325 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4327 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4329 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4330 enable_unrestricted_guest
= 0;
4331 /* Enable INVPCID for non-ept guests may cause performance regression. */
4332 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4334 if (!enable_unrestricted_guest
)
4335 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4337 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4338 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4339 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4340 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4341 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4342 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4344 We can NOT enable shadow_vmcs here because we don't have yet
4347 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4348 return exec_control
;
4351 static void ept_set_mmio_spte_mask(void)
4354 * EPT Misconfigurations can be generated if the value of bits 2:0
4355 * of an EPT paging-structure entry is 110b (write/execute).
4356 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4359 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4363 * Sets up the vmcs for emulated real mode.
4365 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4367 #ifdef CONFIG_X86_64
4373 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4374 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4376 if (enable_shadow_vmcs
) {
4377 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4378 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4380 if (cpu_has_vmx_msr_bitmap())
4381 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4383 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4386 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4388 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4390 if (cpu_has_secondary_exec_ctrls()) {
4391 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4392 vmx_secondary_exec_control(vmx
));
4395 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4396 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4397 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4398 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4399 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4401 vmcs_write16(GUEST_INTR_STATUS
, 0);
4403 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4404 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4408 vmcs_write32(PLE_GAP
, ple_gap
);
4409 vmx
->ple_window
= ple_window
;
4410 vmx
->ple_window_dirty
= true;
4413 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4414 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4415 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4417 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4418 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4419 vmx_set_constant_host_state(vmx
);
4420 #ifdef CONFIG_X86_64
4421 rdmsrl(MSR_FS_BASE
, a
);
4422 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4423 rdmsrl(MSR_GS_BASE
, a
);
4424 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4426 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4427 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4430 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4431 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4432 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4433 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4434 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4436 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4437 u32 msr_low
, msr_high
;
4439 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4440 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4441 /* Write the default value follow host pat */
4442 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4443 /* Keep arch.pat sync with GUEST_IA32_PAT */
4444 vmx
->vcpu
.arch
.pat
= host_pat
;
4447 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4448 u32 index
= vmx_msr_index
[i
];
4449 u32 data_low
, data_high
;
4452 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4454 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4456 vmx
->guest_msrs
[j
].index
= i
;
4457 vmx
->guest_msrs
[j
].data
= 0;
4458 vmx
->guest_msrs
[j
].mask
= -1ull;
4463 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4465 /* 22.2.1, 20.8.1 */
4466 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4468 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4469 set_cr4_guest_host_mask(vmx
);
4474 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4477 struct msr_data apic_base_msr
;
4479 vmx
->rmode
.vm86_active
= 0;
4481 vmx
->soft_vnmi_blocked
= 0;
4483 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4484 kvm_set_cr8(&vmx
->vcpu
, 0);
4485 apic_base_msr
.data
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4486 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4487 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4488 apic_base_msr
.host_initiated
= true;
4489 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4491 vmx_segment_cache_clear(vmx
);
4493 seg_setup(VCPU_SREG_CS
);
4494 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4495 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4497 seg_setup(VCPU_SREG_DS
);
4498 seg_setup(VCPU_SREG_ES
);
4499 seg_setup(VCPU_SREG_FS
);
4500 seg_setup(VCPU_SREG_GS
);
4501 seg_setup(VCPU_SREG_SS
);
4503 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4504 vmcs_writel(GUEST_TR_BASE
, 0);
4505 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4506 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4508 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4509 vmcs_writel(GUEST_LDTR_BASE
, 0);
4510 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4511 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4513 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4514 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4515 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4517 vmcs_writel(GUEST_RFLAGS
, 0x02);
4518 kvm_rip_write(vcpu
, 0xfff0);
4520 vmcs_writel(GUEST_GDTR_BASE
, 0);
4521 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4523 vmcs_writel(GUEST_IDTR_BASE
, 0);
4524 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4526 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4527 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4528 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4530 /* Special registers */
4531 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4535 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4537 if (cpu_has_vmx_tpr_shadow()) {
4538 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4539 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4540 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4541 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4542 vmcs_write32(TPR_THRESHOLD
, 0);
4545 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4546 vmcs_write64(APIC_ACCESS_ADDR
,
4547 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4549 if (vmx_vm_has_apicv(vcpu
->kvm
))
4550 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4553 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4555 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4556 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4557 vmx_set_cr4(&vmx
->vcpu
, 0);
4558 vmx_set_efer(&vmx
->vcpu
, 0);
4559 vmx_fpu_activate(&vmx
->vcpu
);
4560 update_exception_bitmap(&vmx
->vcpu
);
4562 vpid_sync_context(vmx
);
4566 * In nested virtualization, check if L1 asked to exit on external interrupts.
4567 * For most existing hypervisors, this will always return true.
4569 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4571 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4572 PIN_BASED_EXT_INTR_MASK
;
4576 * In nested virtualization, check if L1 has set
4577 * VM_EXIT_ACK_INTR_ON_EXIT
4579 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4581 return get_vmcs12(vcpu
)->vm_exit_controls
&
4582 VM_EXIT_ACK_INTR_ON_EXIT
;
4585 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4587 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4588 PIN_BASED_NMI_EXITING
;
4591 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4593 u32 cpu_based_vm_exec_control
;
4595 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4596 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4597 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4600 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4602 u32 cpu_based_vm_exec_control
;
4604 if (!cpu_has_virtual_nmis() ||
4605 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4606 enable_irq_window(vcpu
);
4610 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4611 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4612 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4615 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4617 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4619 int irq
= vcpu
->arch
.interrupt
.nr
;
4621 trace_kvm_inj_virq(irq
);
4623 ++vcpu
->stat
.irq_injections
;
4624 if (vmx
->rmode
.vm86_active
) {
4626 if (vcpu
->arch
.interrupt
.soft
)
4627 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4628 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4629 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4632 intr
= irq
| INTR_INFO_VALID_MASK
;
4633 if (vcpu
->arch
.interrupt
.soft
) {
4634 intr
|= INTR_TYPE_SOFT_INTR
;
4635 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4636 vmx
->vcpu
.arch
.event_exit_inst_len
);
4638 intr
|= INTR_TYPE_EXT_INTR
;
4639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4642 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4644 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4646 if (is_guest_mode(vcpu
))
4649 if (!cpu_has_virtual_nmis()) {
4651 * Tracking the NMI-blocked state in software is built upon
4652 * finding the next open IRQ window. This, in turn, depends on
4653 * well-behaving guests: They have to keep IRQs disabled at
4654 * least as long as the NMI handler runs. Otherwise we may
4655 * cause NMI nesting, maybe breaking the guest. But as this is
4656 * highly unlikely, we can live with the residual risk.
4658 vmx
->soft_vnmi_blocked
= 1;
4659 vmx
->vnmi_blocked_time
= 0;
4662 ++vcpu
->stat
.nmi_injections
;
4663 vmx
->nmi_known_unmasked
= false;
4664 if (vmx
->rmode
.vm86_active
) {
4665 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4666 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4669 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4670 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4673 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4675 if (!cpu_has_virtual_nmis())
4676 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4677 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4679 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4682 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4686 if (!cpu_has_virtual_nmis()) {
4687 if (vmx
->soft_vnmi_blocked
!= masked
) {
4688 vmx
->soft_vnmi_blocked
= masked
;
4689 vmx
->vnmi_blocked_time
= 0;
4692 vmx
->nmi_known_unmasked
= !masked
;
4694 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4695 GUEST_INTR_STATE_NMI
);
4697 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4698 GUEST_INTR_STATE_NMI
);
4702 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4704 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4707 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4710 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4711 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4712 | GUEST_INTR_STATE_NMI
));
4715 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4717 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4718 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4719 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4720 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4723 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4726 struct kvm_userspace_memory_region tss_mem
= {
4727 .slot
= TSS_PRIVATE_MEMSLOT
,
4728 .guest_phys_addr
= addr
,
4729 .memory_size
= PAGE_SIZE
* 3,
4733 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4736 kvm
->arch
.tss_addr
= addr
;
4737 if (!init_rmode_tss(kvm
))
4743 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4748 * Update instruction length as we may reinject the exception
4749 * from user space while in guest debugging mode.
4751 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4752 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4753 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4757 if (vcpu
->guest_debug
&
4758 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4775 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4776 int vec
, u32 err_code
)
4779 * Instruction with address size override prefix opcode 0x67
4780 * Cause the #SS fault with 0 error code in VM86 mode.
4782 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4783 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4784 if (vcpu
->arch
.halt_request
) {
4785 vcpu
->arch
.halt_request
= 0;
4786 return kvm_emulate_halt(vcpu
);
4794 * Forward all other exceptions that are valid in real mode.
4795 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4796 * the required debugging infrastructure rework.
4798 kvm_queue_exception(vcpu
, vec
);
4803 * Trigger machine check on the host. We assume all the MSRs are already set up
4804 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4805 * We pass a fake environment to the machine check handler because we want
4806 * the guest to be always treated like user space, no matter what context
4807 * it used internally.
4809 static void kvm_machine_check(void)
4811 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4812 struct pt_regs regs
= {
4813 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4814 .flags
= X86_EFLAGS_IF
,
4817 do_machine_check(®s
, 0);
4821 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4823 /* already handled by vcpu_run */
4827 static int handle_exception(struct kvm_vcpu
*vcpu
)
4829 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4830 struct kvm_run
*kvm_run
= vcpu
->run
;
4831 u32 intr_info
, ex_no
, error_code
;
4832 unsigned long cr2
, rip
, dr6
;
4834 enum emulation_result er
;
4836 vect_info
= vmx
->idt_vectoring_info
;
4837 intr_info
= vmx
->exit_intr_info
;
4839 if (is_machine_check(intr_info
))
4840 return handle_machine_check(vcpu
);
4842 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4843 return 1; /* already handled by vmx_vcpu_run() */
4845 if (is_no_device(intr_info
)) {
4846 vmx_fpu_activate(vcpu
);
4850 if (is_invalid_opcode(intr_info
)) {
4851 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4852 if (er
!= EMULATE_DONE
)
4853 kvm_queue_exception(vcpu
, UD_VECTOR
);
4858 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4859 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4862 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4863 * MMIO, it is better to report an internal error.
4864 * See the comments in vmx_handle_exit.
4866 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4867 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4868 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4869 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4870 vcpu
->run
->internal
.ndata
= 2;
4871 vcpu
->run
->internal
.data
[0] = vect_info
;
4872 vcpu
->run
->internal
.data
[1] = intr_info
;
4876 if (is_page_fault(intr_info
)) {
4877 /* EPT won't cause page fault directly */
4879 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4880 trace_kvm_page_fault(cr2
, error_code
);
4882 if (kvm_event_needs_reinjection(vcpu
))
4883 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4884 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4887 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4889 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4890 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4894 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4895 if (!(vcpu
->guest_debug
&
4896 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4897 vcpu
->arch
.dr6
&= ~15;
4898 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
4899 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
4900 skip_emulated_instruction(vcpu
);
4902 kvm_queue_exception(vcpu
, DB_VECTOR
);
4905 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4906 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4910 * Update instruction length as we may reinject #BP from
4911 * user space while in guest debugging mode. Reading it for
4912 * #DB as well causes no harm, it is not used in that case.
4914 vmx
->vcpu
.arch
.event_exit_inst_len
=
4915 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4916 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4917 rip
= kvm_rip_read(vcpu
);
4918 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4919 kvm_run
->debug
.arch
.exception
= ex_no
;
4922 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4923 kvm_run
->ex
.exception
= ex_no
;
4924 kvm_run
->ex
.error_code
= error_code
;
4930 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4932 ++vcpu
->stat
.irq_exits
;
4936 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4938 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4942 static int handle_io(struct kvm_vcpu
*vcpu
)
4944 unsigned long exit_qualification
;
4945 int size
, in
, string
;
4948 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4949 string
= (exit_qualification
& 16) != 0;
4950 in
= (exit_qualification
& 8) != 0;
4952 ++vcpu
->stat
.io_exits
;
4955 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4957 port
= exit_qualification
>> 16;
4958 size
= (exit_qualification
& 7) + 1;
4959 skip_emulated_instruction(vcpu
);
4961 return kvm_fast_pio_out(vcpu
, size
, port
);
4965 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4968 * Patch in the VMCALL instruction:
4970 hypercall
[0] = 0x0f;
4971 hypercall
[1] = 0x01;
4972 hypercall
[2] = 0xc1;
4975 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4977 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4979 if (nested_vmx_secondary_ctls_high
&
4980 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4981 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4982 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4983 return (val
& always_on
) == always_on
;
4986 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4987 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4989 if (is_guest_mode(vcpu
)) {
4990 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4991 unsigned long orig_val
= val
;
4994 * We get here when L2 changed cr0 in a way that did not change
4995 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4996 * but did change L0 shadowed bits. So we first calculate the
4997 * effective cr0 value that L1 would like to write into the
4998 * hardware. It consists of the L2-owned bits from the new
4999 * value combined with the L1-owned bits from L1's guest_cr0.
5001 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5002 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5004 if (!nested_cr0_valid(vmcs12
, val
))
5007 if (kvm_set_cr0(vcpu
, val
))
5009 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5012 if (to_vmx(vcpu
)->nested
.vmxon
&&
5013 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5015 return kvm_set_cr0(vcpu
, val
);
5019 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5021 if (is_guest_mode(vcpu
)) {
5022 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5023 unsigned long orig_val
= val
;
5025 /* analogously to handle_set_cr0 */
5026 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5027 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5028 if (kvm_set_cr4(vcpu
, val
))
5030 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5033 return kvm_set_cr4(vcpu
, val
);
5036 /* called to set cr0 as approriate for clts instruction exit. */
5037 static void handle_clts(struct kvm_vcpu
*vcpu
)
5039 if (is_guest_mode(vcpu
)) {
5041 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5042 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5043 * just pretend it's off (also in arch.cr0 for fpu_activate).
5045 vmcs_writel(CR0_READ_SHADOW
,
5046 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5047 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5049 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5052 static int handle_cr(struct kvm_vcpu
*vcpu
)
5054 unsigned long exit_qualification
, val
;
5059 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5060 cr
= exit_qualification
& 15;
5061 reg
= (exit_qualification
>> 8) & 15;
5062 switch ((exit_qualification
>> 4) & 3) {
5063 case 0: /* mov to cr */
5064 val
= kvm_register_readl(vcpu
, reg
);
5065 trace_kvm_cr_write(cr
, val
);
5068 err
= handle_set_cr0(vcpu
, val
);
5069 kvm_complete_insn_gp(vcpu
, err
);
5072 err
= kvm_set_cr3(vcpu
, val
);
5073 kvm_complete_insn_gp(vcpu
, err
);
5076 err
= handle_set_cr4(vcpu
, val
);
5077 kvm_complete_insn_gp(vcpu
, err
);
5080 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5082 err
= kvm_set_cr8(vcpu
, cr8
);
5083 kvm_complete_insn_gp(vcpu
, err
);
5084 if (irqchip_in_kernel(vcpu
->kvm
))
5086 if (cr8_prev
<= cr8
)
5088 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5095 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5096 skip_emulated_instruction(vcpu
);
5097 vmx_fpu_activate(vcpu
);
5099 case 1: /*mov from cr*/
5102 val
= kvm_read_cr3(vcpu
);
5103 kvm_register_write(vcpu
, reg
, val
);
5104 trace_kvm_cr_read(cr
, val
);
5105 skip_emulated_instruction(vcpu
);
5108 val
= kvm_get_cr8(vcpu
);
5109 kvm_register_write(vcpu
, reg
, val
);
5110 trace_kvm_cr_read(cr
, val
);
5111 skip_emulated_instruction(vcpu
);
5116 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5117 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5118 kvm_lmsw(vcpu
, val
);
5120 skip_emulated_instruction(vcpu
);
5125 vcpu
->run
->exit_reason
= 0;
5126 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5127 (int)(exit_qualification
>> 4) & 3, cr
);
5131 static int handle_dr(struct kvm_vcpu
*vcpu
)
5133 unsigned long exit_qualification
;
5136 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5137 if (!kvm_require_cpl(vcpu
, 0))
5139 dr
= vmcs_readl(GUEST_DR7
);
5142 * As the vm-exit takes precedence over the debug trap, we
5143 * need to emulate the latter, either for the host or the
5144 * guest debugging itself.
5146 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5147 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5148 vcpu
->run
->debug
.arch
.dr7
= dr
;
5149 vcpu
->run
->debug
.arch
.pc
=
5150 vmcs_readl(GUEST_CS_BASE
) +
5151 vmcs_readl(GUEST_RIP
);
5152 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5153 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5156 vcpu
->arch
.dr7
&= ~DR7_GD
;
5157 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5158 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5159 kvm_queue_exception(vcpu
, DB_VECTOR
);
5164 if (vcpu
->guest_debug
== 0) {
5165 u32 cpu_based_vm_exec_control
;
5167 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5168 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5172 * No more DR vmexits; force a reload of the debug registers
5173 * and reenter on this instruction. The next vmexit will
5174 * retrieve the full state of the debug registers.
5176 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5180 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5181 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5182 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5183 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5186 if (kvm_get_dr(vcpu
, dr
, &val
))
5188 kvm_register_write(vcpu
, reg
, val
);
5190 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5193 skip_emulated_instruction(vcpu
);
5197 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5199 return vcpu
->arch
.dr6
;
5202 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5206 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5208 u32 cpu_based_vm_exec_control
;
5210 get_debugreg(vcpu
->arch
.db
[0], 0);
5211 get_debugreg(vcpu
->arch
.db
[1], 1);
5212 get_debugreg(vcpu
->arch
.db
[2], 2);
5213 get_debugreg(vcpu
->arch
.db
[3], 3);
5214 get_debugreg(vcpu
->arch
.dr6
, 6);
5215 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5217 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5219 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5220 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5221 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5224 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5226 vmcs_writel(GUEST_DR7
, val
);
5229 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5231 kvm_emulate_cpuid(vcpu
);
5235 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5237 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5240 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5241 trace_kvm_msr_read_ex(ecx
);
5242 kvm_inject_gp(vcpu
, 0);
5246 trace_kvm_msr_read(ecx
, data
);
5248 /* FIXME: handling of bits 32:63 of rax, rdx */
5249 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5250 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5251 skip_emulated_instruction(vcpu
);
5255 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5257 struct msr_data msr
;
5258 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5259 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5260 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5264 msr
.host_initiated
= false;
5265 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5266 trace_kvm_msr_write_ex(ecx
, data
);
5267 kvm_inject_gp(vcpu
, 0);
5271 trace_kvm_msr_write(ecx
, data
);
5272 skip_emulated_instruction(vcpu
);
5276 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5278 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5282 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5284 u32 cpu_based_vm_exec_control
;
5286 /* clear pending irq */
5287 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5288 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5289 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5291 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5293 ++vcpu
->stat
.irq_window_exits
;
5296 * If the user space waits to inject interrupts, exit as soon as
5299 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5300 vcpu
->run
->request_interrupt_window
&&
5301 !kvm_cpu_has_interrupt(vcpu
)) {
5302 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5308 static int handle_halt(struct kvm_vcpu
*vcpu
)
5310 skip_emulated_instruction(vcpu
);
5311 return kvm_emulate_halt(vcpu
);
5314 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5316 skip_emulated_instruction(vcpu
);
5317 kvm_emulate_hypercall(vcpu
);
5321 static int handle_invd(struct kvm_vcpu
*vcpu
)
5323 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5326 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5328 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5330 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5331 skip_emulated_instruction(vcpu
);
5335 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5339 err
= kvm_rdpmc(vcpu
);
5340 kvm_complete_insn_gp(vcpu
, err
);
5345 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5347 skip_emulated_instruction(vcpu
);
5348 kvm_emulate_wbinvd(vcpu
);
5352 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5354 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5355 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5357 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5358 skip_emulated_instruction(vcpu
);
5362 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5364 if (likely(fasteoi
)) {
5365 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5366 int access_type
, offset
;
5368 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5369 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5371 * Sane guest uses MOV to write EOI, with written value
5372 * not cared. So make a short-circuit here by avoiding
5373 * heavy instruction emulation.
5375 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5376 (offset
== APIC_EOI
)) {
5377 kvm_lapic_set_eoi(vcpu
);
5378 skip_emulated_instruction(vcpu
);
5382 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5385 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5387 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5388 int vector
= exit_qualification
& 0xff;
5390 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5391 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5395 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5397 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5398 u32 offset
= exit_qualification
& 0xfff;
5400 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5401 kvm_apic_write_nodecode(vcpu
, offset
);
5405 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5408 unsigned long exit_qualification
;
5409 bool has_error_code
= false;
5412 int reason
, type
, idt_v
, idt_index
;
5414 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5415 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5416 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5418 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5420 reason
= (u32
)exit_qualification
>> 30;
5421 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5423 case INTR_TYPE_NMI_INTR
:
5424 vcpu
->arch
.nmi_injected
= false;
5425 vmx_set_nmi_mask(vcpu
, true);
5427 case INTR_TYPE_EXT_INTR
:
5428 case INTR_TYPE_SOFT_INTR
:
5429 kvm_clear_interrupt_queue(vcpu
);
5431 case INTR_TYPE_HARD_EXCEPTION
:
5432 if (vmx
->idt_vectoring_info
&
5433 VECTORING_INFO_DELIVER_CODE_MASK
) {
5434 has_error_code
= true;
5436 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5439 case INTR_TYPE_SOFT_EXCEPTION
:
5440 kvm_clear_exception_queue(vcpu
);
5446 tss_selector
= exit_qualification
;
5448 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5449 type
!= INTR_TYPE_EXT_INTR
&&
5450 type
!= INTR_TYPE_NMI_INTR
))
5451 skip_emulated_instruction(vcpu
);
5453 if (kvm_task_switch(vcpu
, tss_selector
,
5454 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5455 has_error_code
, error_code
) == EMULATE_FAIL
) {
5456 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5457 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5458 vcpu
->run
->internal
.ndata
= 0;
5462 /* clear all local breakpoint enable flags */
5463 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x55);
5466 * TODO: What about debug traps on tss switch?
5467 * Are we supposed to inject them and update dr6?
5473 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5475 unsigned long exit_qualification
;
5480 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5482 gla_validity
= (exit_qualification
>> 7) & 0x3;
5483 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5484 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5485 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5486 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5487 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5488 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5489 (long unsigned int)exit_qualification
);
5490 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5491 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5496 * EPT violation happened while executing iret from NMI,
5497 * "blocked by NMI" bit has to be set before next VM entry.
5498 * There are errata that may cause this bit to not be set:
5501 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5502 cpu_has_virtual_nmis() &&
5503 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5504 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5506 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5507 trace_kvm_page_fault(gpa
, exit_qualification
);
5509 /* It is a write fault? */
5510 error_code
= exit_qualification
& (1U << 1);
5511 /* It is a fetch fault? */
5512 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5513 /* ept page table is present? */
5514 error_code
|= (exit_qualification
>> 3) & 0x1;
5516 vcpu
->arch
.exit_qualification
= exit_qualification
;
5518 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5521 static u64
ept_rsvd_mask(u64 spte
, int level
)
5526 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5527 mask
|= (1ULL << i
);
5530 /* bits 7:3 reserved */
5532 else if (spte
& (1ULL << 7))
5534 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5535 * level == 1 if the hypervisor is using the ignored bit 7.
5537 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5539 /* bits 6:3 reserved */
5545 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5548 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5550 /* 010b (write-only) */
5551 WARN_ON((spte
& 0x7) == 0x2);
5553 /* 110b (write/execute) */
5554 WARN_ON((spte
& 0x7) == 0x6);
5556 /* 100b (execute-only) and value not supported by logical processor */
5557 if (!cpu_has_vmx_ept_execute_only())
5558 WARN_ON((spte
& 0x7) == 0x4);
5562 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5564 if (rsvd_bits
!= 0) {
5565 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5566 __func__
, rsvd_bits
);
5570 /* bits 5:3 are _not_ reserved for large page or leaf page */
5571 if ((rsvd_bits
& 0x38) == 0) {
5572 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5574 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5575 ept_mem_type
== 7) {
5576 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5577 __func__
, ept_mem_type
);
5584 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5587 int nr_sptes
, i
, ret
;
5590 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5591 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5592 skip_emulated_instruction(vcpu
);
5596 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5597 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5598 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5601 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5602 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5604 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5607 /* It is the real ept misconfig */
5608 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5609 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5611 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5613 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5614 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5616 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5617 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5622 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5624 u32 cpu_based_vm_exec_control
;
5626 /* clear pending NMI */
5627 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5628 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5630 ++vcpu
->stat
.nmi_window_exits
;
5631 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5636 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5638 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5639 enum emulation_result err
= EMULATE_DONE
;
5642 bool intr_window_requested
;
5643 unsigned count
= 130;
5645 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5646 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5648 while (vmx
->emulation_required
&& count
-- != 0) {
5649 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5650 return handle_interrupt_window(&vmx
->vcpu
);
5652 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5655 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5657 if (err
== EMULATE_USER_EXIT
) {
5658 ++vcpu
->stat
.mmio_exits
;
5663 if (err
!= EMULATE_DONE
) {
5664 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5665 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5666 vcpu
->run
->internal
.ndata
= 0;
5670 if (vcpu
->arch
.halt_request
) {
5671 vcpu
->arch
.halt_request
= 0;
5672 ret
= kvm_emulate_halt(vcpu
);
5676 if (signal_pending(current
))
5687 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5688 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5690 static int handle_pause(struct kvm_vcpu
*vcpu
)
5692 skip_emulated_instruction(vcpu
);
5693 kvm_vcpu_on_spin(vcpu
);
5698 static int handle_nop(struct kvm_vcpu
*vcpu
)
5700 skip_emulated_instruction(vcpu
);
5704 static int handle_mwait(struct kvm_vcpu
*vcpu
)
5706 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
5707 return handle_nop(vcpu
);
5710 static int handle_monitor(struct kvm_vcpu
*vcpu
)
5712 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
5713 return handle_nop(vcpu
);
5717 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5718 * We could reuse a single VMCS for all the L2 guests, but we also want the
5719 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5720 * allows keeping them loaded on the processor, and in the future will allow
5721 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5722 * every entry if they never change.
5723 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5724 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5726 * The following functions allocate and free a vmcs02 in this pool.
5729 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5730 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5732 struct vmcs02_list
*item
;
5733 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5734 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5735 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5736 return &item
->vmcs02
;
5739 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5740 /* Recycle the least recently used VMCS. */
5741 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5742 struct vmcs02_list
, list
);
5743 item
->vmptr
= vmx
->nested
.current_vmptr
;
5744 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5745 return &item
->vmcs02
;
5748 /* Create a new VMCS */
5749 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5752 item
->vmcs02
.vmcs
= alloc_vmcs();
5753 if (!item
->vmcs02
.vmcs
) {
5757 loaded_vmcs_init(&item
->vmcs02
);
5758 item
->vmptr
= vmx
->nested
.current_vmptr
;
5759 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5760 vmx
->nested
.vmcs02_num
++;
5761 return &item
->vmcs02
;
5764 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5765 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5767 struct vmcs02_list
*item
;
5768 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5769 if (item
->vmptr
== vmptr
) {
5770 free_loaded_vmcs(&item
->vmcs02
);
5771 list_del(&item
->list
);
5773 vmx
->nested
.vmcs02_num
--;
5779 * Free all VMCSs saved for this vcpu, except the one pointed by
5780 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5781 * must be &vmx->vmcs01.
5783 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5785 struct vmcs02_list
*item
, *n
;
5787 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
5788 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5790 * Something will leak if the above WARN triggers. Better than
5793 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
5796 free_loaded_vmcs(&item
->vmcs02
);
5797 list_del(&item
->list
);
5799 vmx
->nested
.vmcs02_num
--;
5804 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5805 * set the success or error code of an emulated VMX instruction, as specified
5806 * by Vol 2B, VMX Instruction Reference, "Conventions".
5808 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5810 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5811 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5812 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5815 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5817 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5818 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5819 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5823 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5824 u32 vm_instruction_error
)
5826 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5828 * failValid writes the error number to the current VMCS, which
5829 * can't be done there isn't a current VMCS.
5831 nested_vmx_failInvalid(vcpu
);
5834 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5835 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5836 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5838 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5840 * We don't need to force a shadow sync because
5841 * VM_INSTRUCTION_ERROR is not shadowed
5845 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
5847 struct vcpu_vmx
*vmx
=
5848 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
5850 vmx
->nested
.preemption_timer_expired
= true;
5851 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5852 kvm_vcpu_kick(&vmx
->vcpu
);
5854 return HRTIMER_NORESTART
;
5858 * Decode the memory-address operand of a vmx instruction, as recorded on an
5859 * exit caused by such an instruction (run by a guest hypervisor).
5860 * On success, returns 0. When the operand is invalid, returns 1 and throws
5863 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5864 unsigned long exit_qualification
,
5865 u32 vmx_instruction_info
, gva_t
*ret
)
5868 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5869 * Execution", on an exit, vmx_instruction_info holds most of the
5870 * addressing components of the operand. Only the displacement part
5871 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5872 * For how an actual address is calculated from all these components,
5873 * refer to Vol. 1, "Operand Addressing".
5875 int scaling
= vmx_instruction_info
& 3;
5876 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5877 bool is_reg
= vmx_instruction_info
& (1u << 10);
5878 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5879 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5880 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5881 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5882 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5885 kvm_queue_exception(vcpu
, UD_VECTOR
);
5889 /* Addr = segment_base + offset */
5890 /* offset = base + [index * scale] + displacement */
5891 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5893 *ret
+= kvm_register_read(vcpu
, base_reg
);
5895 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5896 *ret
+= exit_qualification
; /* holds the displacement */
5898 if (addr_size
== 1) /* 32 bit */
5902 * TODO: throw #GP (and return 1) in various cases that the VM*
5903 * instructions require it - e.g., offset beyond segment limit,
5904 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5905 * address, and so on. Currently these are not checked.
5911 * This function performs the various checks including
5912 * - if it's 4KB aligned
5913 * - No bits beyond the physical address width are set
5914 * - Returns 0 on success or else 1
5915 * (Intel SDM Section 30.3)
5917 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
5922 struct x86_exception e
;
5924 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5925 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
5927 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5928 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5931 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5932 sizeof(vmptr
), &e
)) {
5933 kvm_inject_page_fault(vcpu
, &e
);
5937 switch (exit_reason
) {
5938 case EXIT_REASON_VMON
:
5941 * The first 4 bytes of VMXON region contain the supported
5942 * VMCS revision identifier
5944 * Note - IA32_VMX_BASIC[48] will never be 1
5945 * for the nested case;
5946 * which replaces physical address width with 32
5949 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
5950 nested_vmx_failInvalid(vcpu
);
5951 skip_emulated_instruction(vcpu
);
5955 page
= nested_get_page(vcpu
, vmptr
);
5957 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
5958 nested_vmx_failInvalid(vcpu
);
5960 skip_emulated_instruction(vcpu
);
5964 vmx
->nested
.vmxon_ptr
= vmptr
;
5966 case EXIT_REASON_VMCLEAR
:
5967 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
5968 nested_vmx_failValid(vcpu
,
5969 VMXERR_VMCLEAR_INVALID_ADDRESS
);
5970 skip_emulated_instruction(vcpu
);
5974 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
5975 nested_vmx_failValid(vcpu
,
5976 VMXERR_VMCLEAR_VMXON_POINTER
);
5977 skip_emulated_instruction(vcpu
);
5981 case EXIT_REASON_VMPTRLD
:
5982 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
5983 nested_vmx_failValid(vcpu
,
5984 VMXERR_VMPTRLD_INVALID_ADDRESS
);
5985 skip_emulated_instruction(vcpu
);
5989 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
5990 nested_vmx_failValid(vcpu
,
5991 VMXERR_VMCLEAR_VMXON_POINTER
);
5992 skip_emulated_instruction(vcpu
);
5997 return 1; /* shouldn't happen */
6006 * Emulate the VMXON instruction.
6007 * Currently, we just remember that VMX is active, and do not save or even
6008 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6009 * do not currently need to store anything in that guest-allocated memory
6010 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6011 * argument is different from the VMXON pointer (which the spec says they do).
6013 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6015 struct kvm_segment cs
;
6016 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6017 struct vmcs
*shadow_vmcs
;
6018 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6019 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6021 /* The Intel VMX Instruction Reference lists a bunch of bits that
6022 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6023 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6024 * Otherwise, we should fail with #UD. We test these now:
6026 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6027 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6028 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6029 kvm_queue_exception(vcpu
, UD_VECTOR
);
6033 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6034 if (is_long_mode(vcpu
) && !cs
.l
) {
6035 kvm_queue_exception(vcpu
, UD_VECTOR
);
6039 if (vmx_get_cpl(vcpu
)) {
6040 kvm_inject_gp(vcpu
, 0);
6044 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6047 if (vmx
->nested
.vmxon
) {
6048 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6049 skip_emulated_instruction(vcpu
);
6053 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6054 != VMXON_NEEDED_FEATURES
) {
6055 kvm_inject_gp(vcpu
, 0);
6059 if (enable_shadow_vmcs
) {
6060 shadow_vmcs
= alloc_vmcs();
6063 /* mark vmcs as shadow */
6064 shadow_vmcs
->revision_id
|= (1u << 31);
6065 /* init shadow vmcs */
6066 vmcs_clear(shadow_vmcs
);
6067 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6070 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6071 vmx
->nested
.vmcs02_num
= 0;
6073 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6075 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6077 vmx
->nested
.vmxon
= true;
6079 skip_emulated_instruction(vcpu
);
6080 nested_vmx_succeed(vcpu
);
6085 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6086 * for running VMX instructions (except VMXON, whose prerequisites are
6087 * slightly different). It also specifies what exception to inject otherwise.
6089 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6091 struct kvm_segment cs
;
6092 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6094 if (!vmx
->nested
.vmxon
) {
6095 kvm_queue_exception(vcpu
, UD_VECTOR
);
6099 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6100 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6101 (is_long_mode(vcpu
) && !cs
.l
)) {
6102 kvm_queue_exception(vcpu
, UD_VECTOR
);
6106 if (vmx_get_cpl(vcpu
)) {
6107 kvm_inject_gp(vcpu
, 0);
6114 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6117 if (vmx
->nested
.current_vmptr
== -1ull)
6120 /* current_vmptr and current_vmcs12 are always set/reset together */
6121 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6124 if (enable_shadow_vmcs
) {
6125 /* copy to memory all shadowed fields in case
6126 they were modified */
6127 copy_shadow_to_vmcs12(vmx
);
6128 vmx
->nested
.sync_shadow_vmcs
= false;
6129 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6130 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6131 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6132 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6134 kunmap(vmx
->nested
.current_vmcs12_page
);
6135 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6136 vmx
->nested
.current_vmptr
= -1ull;
6137 vmx
->nested
.current_vmcs12
= NULL
;
6141 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6142 * just stops using VMX.
6144 static void free_nested(struct vcpu_vmx
*vmx
)
6146 if (!vmx
->nested
.vmxon
)
6149 vmx
->nested
.vmxon
= false;
6150 nested_release_vmcs12(vmx
);
6151 if (enable_shadow_vmcs
)
6152 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6153 /* Unpin physical memory we referred to in current vmcs02 */
6154 if (vmx
->nested
.apic_access_page
) {
6155 nested_release_page(vmx
->nested
.apic_access_page
);
6156 vmx
->nested
.apic_access_page
= 0;
6159 nested_free_all_saved_vmcss(vmx
);
6162 /* Emulate the VMXOFF instruction */
6163 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6165 if (!nested_vmx_check_permission(vcpu
))
6167 free_nested(to_vmx(vcpu
));
6168 skip_emulated_instruction(vcpu
);
6169 nested_vmx_succeed(vcpu
);
6173 /* Emulate the VMCLEAR instruction */
6174 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6178 struct vmcs12
*vmcs12
;
6181 if (!nested_vmx_check_permission(vcpu
))
6184 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6187 if (vmptr
== vmx
->nested
.current_vmptr
)
6188 nested_release_vmcs12(vmx
);
6190 page
= nested_get_page(vcpu
, vmptr
);
6193 * For accurate processor emulation, VMCLEAR beyond available
6194 * physical memory should do nothing at all. However, it is
6195 * possible that a nested vmx bug, not a guest hypervisor bug,
6196 * resulted in this case, so let's shut down before doing any
6199 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6202 vmcs12
= kmap(page
);
6203 vmcs12
->launch_state
= 0;
6205 nested_release_page(page
);
6207 nested_free_vmcs02(vmx
, vmptr
);
6209 skip_emulated_instruction(vcpu
);
6210 nested_vmx_succeed(vcpu
);
6214 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6216 /* Emulate the VMLAUNCH instruction */
6217 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6219 return nested_vmx_run(vcpu
, true);
6222 /* Emulate the VMRESUME instruction */
6223 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6226 return nested_vmx_run(vcpu
, false);
6229 enum vmcs_field_type
{
6230 VMCS_FIELD_TYPE_U16
= 0,
6231 VMCS_FIELD_TYPE_U64
= 1,
6232 VMCS_FIELD_TYPE_U32
= 2,
6233 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6236 static inline int vmcs_field_type(unsigned long field
)
6238 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6239 return VMCS_FIELD_TYPE_U32
;
6240 return (field
>> 13) & 0x3 ;
6243 static inline int vmcs_field_readonly(unsigned long field
)
6245 return (((field
>> 10) & 0x3) == 1);
6249 * Read a vmcs12 field. Since these can have varying lengths and we return
6250 * one type, we chose the biggest type (u64) and zero-extend the return value
6251 * to that size. Note that the caller, handle_vmread, might need to use only
6252 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6253 * 64-bit fields are to be returned).
6255 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6256 unsigned long field
, u64
*ret
)
6258 short offset
= vmcs_field_to_offset(field
);
6264 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6266 switch (vmcs_field_type(field
)) {
6267 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6268 *ret
= *((natural_width
*)p
);
6270 case VMCS_FIELD_TYPE_U16
:
6273 case VMCS_FIELD_TYPE_U32
:
6276 case VMCS_FIELD_TYPE_U64
:
6280 return 0; /* can never happen. */
6285 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6286 unsigned long field
, u64 field_value
){
6287 short offset
= vmcs_field_to_offset(field
);
6288 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6292 switch (vmcs_field_type(field
)) {
6293 case VMCS_FIELD_TYPE_U16
:
6294 *(u16
*)p
= field_value
;
6296 case VMCS_FIELD_TYPE_U32
:
6297 *(u32
*)p
= field_value
;
6299 case VMCS_FIELD_TYPE_U64
:
6300 *(u64
*)p
= field_value
;
6302 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6303 *(natural_width
*)p
= field_value
;
6306 return false; /* can never happen. */
6311 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6314 unsigned long field
;
6316 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6317 const unsigned long *fields
= shadow_read_write_fields
;
6318 const int num_fields
= max_shadow_read_write_fields
;
6320 vmcs_load(shadow_vmcs
);
6322 for (i
= 0; i
< num_fields
; i
++) {
6324 switch (vmcs_field_type(field
)) {
6325 case VMCS_FIELD_TYPE_U16
:
6326 field_value
= vmcs_read16(field
);
6328 case VMCS_FIELD_TYPE_U32
:
6329 field_value
= vmcs_read32(field
);
6331 case VMCS_FIELD_TYPE_U64
:
6332 field_value
= vmcs_read64(field
);
6334 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6335 field_value
= vmcs_readl(field
);
6338 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6341 vmcs_clear(shadow_vmcs
);
6342 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6345 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6347 const unsigned long *fields
[] = {
6348 shadow_read_write_fields
,
6349 shadow_read_only_fields
6351 const int max_fields
[] = {
6352 max_shadow_read_write_fields
,
6353 max_shadow_read_only_fields
6356 unsigned long field
;
6357 u64 field_value
= 0;
6358 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6360 vmcs_load(shadow_vmcs
);
6362 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6363 for (i
= 0; i
< max_fields
[q
]; i
++) {
6364 field
= fields
[q
][i
];
6365 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6367 switch (vmcs_field_type(field
)) {
6368 case VMCS_FIELD_TYPE_U16
:
6369 vmcs_write16(field
, (u16
)field_value
);
6371 case VMCS_FIELD_TYPE_U32
:
6372 vmcs_write32(field
, (u32
)field_value
);
6374 case VMCS_FIELD_TYPE_U64
:
6375 vmcs_write64(field
, (u64
)field_value
);
6377 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6378 vmcs_writel(field
, (long)field_value
);
6384 vmcs_clear(shadow_vmcs
);
6385 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6389 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6390 * used before) all generate the same failure when it is missing.
6392 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6394 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6395 if (vmx
->nested
.current_vmptr
== -1ull) {
6396 nested_vmx_failInvalid(vcpu
);
6397 skip_emulated_instruction(vcpu
);
6403 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6405 unsigned long field
;
6407 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6408 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6411 if (!nested_vmx_check_permission(vcpu
) ||
6412 !nested_vmx_check_vmcs12(vcpu
))
6415 /* Decode instruction info and find the field to read */
6416 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6417 /* Read the field, zero-extended to a u64 field_value */
6418 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6419 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6420 skip_emulated_instruction(vcpu
);
6424 * Now copy part of this value to register or memory, as requested.
6425 * Note that the number of bits actually copied is 32 or 64 depending
6426 * on the guest's mode (32 or 64 bit), not on the given field's length.
6428 if (vmx_instruction_info
& (1u << 10)) {
6429 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6432 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6433 vmx_instruction_info
, &gva
))
6435 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6436 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6437 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6440 nested_vmx_succeed(vcpu
);
6441 skip_emulated_instruction(vcpu
);
6446 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6448 unsigned long field
;
6450 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6451 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6452 /* The value to write might be 32 or 64 bits, depending on L1's long
6453 * mode, and eventually we need to write that into a field of several
6454 * possible lengths. The code below first zero-extends the value to 64
6455 * bit (field_value), and then copies only the approriate number of
6456 * bits into the vmcs12 field.
6458 u64 field_value
= 0;
6459 struct x86_exception e
;
6461 if (!nested_vmx_check_permission(vcpu
) ||
6462 !nested_vmx_check_vmcs12(vcpu
))
6465 if (vmx_instruction_info
& (1u << 10))
6466 field_value
= kvm_register_readl(vcpu
,
6467 (((vmx_instruction_info
) >> 3) & 0xf));
6469 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6470 vmx_instruction_info
, &gva
))
6472 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6473 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
6474 kvm_inject_page_fault(vcpu
, &e
);
6480 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6481 if (vmcs_field_readonly(field
)) {
6482 nested_vmx_failValid(vcpu
,
6483 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6484 skip_emulated_instruction(vcpu
);
6488 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6489 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6490 skip_emulated_instruction(vcpu
);
6494 nested_vmx_succeed(vcpu
);
6495 skip_emulated_instruction(vcpu
);
6499 /* Emulate the VMPTRLD instruction */
6500 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6506 if (!nested_vmx_check_permission(vcpu
))
6509 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6512 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6513 struct vmcs12
*new_vmcs12
;
6515 page
= nested_get_page(vcpu
, vmptr
);
6517 nested_vmx_failInvalid(vcpu
);
6518 skip_emulated_instruction(vcpu
);
6521 new_vmcs12
= kmap(page
);
6522 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6524 nested_release_page_clean(page
);
6525 nested_vmx_failValid(vcpu
,
6526 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6527 skip_emulated_instruction(vcpu
);
6531 nested_release_vmcs12(vmx
);
6532 vmx
->nested
.current_vmptr
= vmptr
;
6533 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6534 vmx
->nested
.current_vmcs12_page
= page
;
6535 if (enable_shadow_vmcs
) {
6536 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6537 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6538 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6539 vmcs_write64(VMCS_LINK_POINTER
,
6540 __pa(vmx
->nested
.current_shadow_vmcs
));
6541 vmx
->nested
.sync_shadow_vmcs
= true;
6545 nested_vmx_succeed(vcpu
);
6546 skip_emulated_instruction(vcpu
);
6550 /* Emulate the VMPTRST instruction */
6551 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6553 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6554 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6556 struct x86_exception e
;
6558 if (!nested_vmx_check_permission(vcpu
))
6561 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6562 vmx_instruction_info
, &vmcs_gva
))
6564 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6565 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6566 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6568 kvm_inject_page_fault(vcpu
, &e
);
6571 nested_vmx_succeed(vcpu
);
6572 skip_emulated_instruction(vcpu
);
6576 /* Emulate the INVEPT instruction */
6577 static int handle_invept(struct kvm_vcpu
*vcpu
)
6579 u32 vmx_instruction_info
, types
;
6582 struct x86_exception e
;
6587 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6588 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6589 kvm_queue_exception(vcpu
, UD_VECTOR
);
6593 if (!nested_vmx_check_permission(vcpu
))
6596 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6597 kvm_queue_exception(vcpu
, UD_VECTOR
);
6601 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6602 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6604 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6606 if (!(types
& (1UL << type
))) {
6607 nested_vmx_failValid(vcpu
,
6608 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6612 /* According to the Intel VMX instruction reference, the memory
6613 * operand is read even if it isn't needed (e.g., for type==global)
6615 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6616 vmx_instruction_info
, &gva
))
6618 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6619 sizeof(operand
), &e
)) {
6620 kvm_inject_page_fault(vcpu
, &e
);
6625 case VMX_EPT_EXTENT_GLOBAL
:
6626 kvm_mmu_sync_roots(vcpu
);
6627 kvm_mmu_flush_tlb(vcpu
);
6628 nested_vmx_succeed(vcpu
);
6631 /* Trap single context invalidation invept calls */
6636 skip_emulated_instruction(vcpu
);
6641 * The exit handlers return 1 if the exit was handled fully and guest execution
6642 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6643 * to be done to userspace and return 0.
6645 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6646 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6647 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6648 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6649 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6650 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6651 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6652 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6653 [EXIT_REASON_CPUID
] = handle_cpuid
,
6654 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6655 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6656 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6657 [EXIT_REASON_HLT
] = handle_halt
,
6658 [EXIT_REASON_INVD
] = handle_invd
,
6659 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6660 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6661 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6662 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6663 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6664 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6665 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6666 [EXIT_REASON_VMREAD
] = handle_vmread
,
6667 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6668 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6669 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6670 [EXIT_REASON_VMON
] = handle_vmon
,
6671 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6672 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6673 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6674 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6675 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6676 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6677 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6678 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6679 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6680 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6681 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6682 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
6683 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
6684 [EXIT_REASON_INVEPT
] = handle_invept
,
6687 static const int kvm_vmx_max_exit_handlers
=
6688 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6690 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6691 struct vmcs12
*vmcs12
)
6693 unsigned long exit_qualification
;
6694 gpa_t bitmap
, last_bitmap
;
6699 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6700 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6702 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6704 port
= exit_qualification
>> 16;
6705 size
= (exit_qualification
& 7) + 1;
6707 last_bitmap
= (gpa_t
)-1;
6712 bitmap
= vmcs12
->io_bitmap_a
;
6713 else if (port
< 0x10000)
6714 bitmap
= vmcs12
->io_bitmap_b
;
6717 bitmap
+= (port
& 0x7fff) / 8;
6719 if (last_bitmap
!= bitmap
)
6720 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6722 if (b
& (1 << (port
& 7)))
6727 last_bitmap
= bitmap
;
6734 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6735 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6736 * disinterest in the current event (read or write a specific MSR) by using an
6737 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6739 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6740 struct vmcs12
*vmcs12
, u32 exit_reason
)
6742 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6745 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6749 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6750 * for the four combinations of read/write and low/high MSR numbers.
6751 * First we need to figure out which of the four to use:
6753 bitmap
= vmcs12
->msr_bitmap
;
6754 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6756 if (msr_index
>= 0xc0000000) {
6757 msr_index
-= 0xc0000000;
6761 /* Then read the msr_index'th bit from this bitmap: */
6762 if (msr_index
< 1024*8) {
6764 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6766 return 1 & (b
>> (msr_index
& 7));
6768 return 1; /* let L1 handle the wrong parameter */
6772 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6773 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6774 * intercept (via guest_host_mask etc.) the current event.
6776 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6777 struct vmcs12
*vmcs12
)
6779 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6780 int cr
= exit_qualification
& 15;
6781 int reg
= (exit_qualification
>> 8) & 15;
6782 unsigned long val
= kvm_register_readl(vcpu
, reg
);
6784 switch ((exit_qualification
>> 4) & 3) {
6785 case 0: /* mov to cr */
6788 if (vmcs12
->cr0_guest_host_mask
&
6789 (val
^ vmcs12
->cr0_read_shadow
))
6793 if ((vmcs12
->cr3_target_count
>= 1 &&
6794 vmcs12
->cr3_target_value0
== val
) ||
6795 (vmcs12
->cr3_target_count
>= 2 &&
6796 vmcs12
->cr3_target_value1
== val
) ||
6797 (vmcs12
->cr3_target_count
>= 3 &&
6798 vmcs12
->cr3_target_value2
== val
) ||
6799 (vmcs12
->cr3_target_count
>= 4 &&
6800 vmcs12
->cr3_target_value3
== val
))
6802 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6806 if (vmcs12
->cr4_guest_host_mask
&
6807 (vmcs12
->cr4_read_shadow
^ val
))
6811 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6817 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6818 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6821 case 1: /* mov from cr */
6824 if (vmcs12
->cpu_based_vm_exec_control
&
6825 CPU_BASED_CR3_STORE_EXITING
)
6829 if (vmcs12
->cpu_based_vm_exec_control
&
6830 CPU_BASED_CR8_STORE_EXITING
)
6837 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6838 * cr0. Other attempted changes are ignored, with no exit.
6840 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6841 (val
^ vmcs12
->cr0_read_shadow
))
6843 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6844 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6853 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6854 * should handle it ourselves in L0 (and then continue L2). Only call this
6855 * when in is_guest_mode (L2).
6857 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6859 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6861 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6862 u32 exit_reason
= vmx
->exit_reason
;
6864 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6865 vmcs_readl(EXIT_QUALIFICATION
),
6866 vmx
->idt_vectoring_info
,
6868 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6871 if (vmx
->nested
.nested_run_pending
)
6874 if (unlikely(vmx
->fail
)) {
6875 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6876 vmcs_read32(VM_INSTRUCTION_ERROR
));
6880 switch (exit_reason
) {
6881 case EXIT_REASON_EXCEPTION_NMI
:
6882 if (!is_exception(intr_info
))
6884 else if (is_page_fault(intr_info
))
6886 else if (is_no_device(intr_info
) &&
6887 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
6889 return vmcs12
->exception_bitmap
&
6890 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6891 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6893 case EXIT_REASON_TRIPLE_FAULT
:
6895 case EXIT_REASON_PENDING_INTERRUPT
:
6896 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6897 case EXIT_REASON_NMI_WINDOW
:
6898 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6899 case EXIT_REASON_TASK_SWITCH
:
6901 case EXIT_REASON_CPUID
:
6903 case EXIT_REASON_HLT
:
6904 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6905 case EXIT_REASON_INVD
:
6907 case EXIT_REASON_INVLPG
:
6908 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6909 case EXIT_REASON_RDPMC
:
6910 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6911 case EXIT_REASON_RDTSC
:
6912 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6913 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6914 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6915 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6916 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6917 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6918 case EXIT_REASON_INVEPT
:
6920 * VMX instructions trap unconditionally. This allows L1 to
6921 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6924 case EXIT_REASON_CR_ACCESS
:
6925 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6926 case EXIT_REASON_DR_ACCESS
:
6927 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6928 case EXIT_REASON_IO_INSTRUCTION
:
6929 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6930 case EXIT_REASON_MSR_READ
:
6931 case EXIT_REASON_MSR_WRITE
:
6932 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6933 case EXIT_REASON_INVALID_STATE
:
6935 case EXIT_REASON_MWAIT_INSTRUCTION
:
6936 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6937 case EXIT_REASON_MONITOR_INSTRUCTION
:
6938 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6939 case EXIT_REASON_PAUSE_INSTRUCTION
:
6940 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6941 nested_cpu_has2(vmcs12
,
6942 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6943 case EXIT_REASON_MCE_DURING_VMENTRY
:
6945 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6947 case EXIT_REASON_APIC_ACCESS
:
6948 return nested_cpu_has2(vmcs12
,
6949 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6950 case EXIT_REASON_EPT_VIOLATION
:
6952 * L0 always deals with the EPT violation. If nested EPT is
6953 * used, and the nested mmu code discovers that the address is
6954 * missing in the guest EPT table (EPT12), the EPT violation
6955 * will be injected with nested_ept_inject_page_fault()
6958 case EXIT_REASON_EPT_MISCONFIG
:
6960 * L2 never uses directly L1's EPT, but rather L0's own EPT
6961 * table (shadow on EPT) or a merged EPT table that L0 built
6962 * (EPT on EPT). So any problems with the structure of the
6963 * table is L0's fault.
6966 case EXIT_REASON_WBINVD
:
6967 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6968 case EXIT_REASON_XSETBV
:
6975 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6977 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6978 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6982 * The guest has exited. See if we can fix it or if we need userspace
6985 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6987 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6988 u32 exit_reason
= vmx
->exit_reason
;
6989 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6991 /* If guest state is invalid, start emulating */
6992 if (vmx
->emulation_required
)
6993 return handle_invalid_guest_state(vcpu
);
6995 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6996 nested_vmx_vmexit(vcpu
, exit_reason
,
6997 vmcs_read32(VM_EXIT_INTR_INFO
),
6998 vmcs_readl(EXIT_QUALIFICATION
));
7002 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7003 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7004 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7009 if (unlikely(vmx
->fail
)) {
7010 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7011 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7012 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7018 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7019 * delivery event since it indicates guest is accessing MMIO.
7020 * The vm-exit can be triggered again after return to guest that
7021 * will cause infinite loop.
7023 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7024 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7025 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7026 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7027 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7028 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7029 vcpu
->run
->internal
.ndata
= 2;
7030 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7031 vcpu
->run
->internal
.data
[1] = exit_reason
;
7035 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7036 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7037 get_vmcs12(vcpu
))))) {
7038 if (vmx_interrupt_allowed(vcpu
)) {
7039 vmx
->soft_vnmi_blocked
= 0;
7040 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7041 vcpu
->arch
.nmi_pending
) {
7043 * This CPU don't support us in finding the end of an
7044 * NMI-blocked window if the guest runs with IRQs
7045 * disabled. So we pull the trigger after 1 s of
7046 * futile waiting, but inform the user about this.
7048 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7049 "state on VCPU %d after 1 s timeout\n",
7050 __func__
, vcpu
->vcpu_id
);
7051 vmx
->soft_vnmi_blocked
= 0;
7055 if (exit_reason
< kvm_vmx_max_exit_handlers
7056 && kvm_vmx_exit_handlers
[exit_reason
])
7057 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7059 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
7060 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
7065 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7067 if (irr
== -1 || tpr
< irr
) {
7068 vmcs_write32(TPR_THRESHOLD
, 0);
7072 vmcs_write32(TPR_THRESHOLD
, irr
);
7075 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7077 u32 sec_exec_control
;
7080 * There is not point to enable virtualize x2apic without enable
7083 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7084 !vmx_vm_has_apicv(vcpu
->kvm
))
7087 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7090 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7093 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7094 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7096 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7097 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7099 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7101 vmx_set_msr_bitmap(vcpu
);
7104 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7109 if (!vmx_vm_has_apicv(kvm
))
7115 status
= vmcs_read16(GUEST_INTR_STATUS
);
7120 vmcs_write16(GUEST_INTR_STATUS
, status
);
7124 static void vmx_set_rvi(int vector
)
7129 status
= vmcs_read16(GUEST_INTR_STATUS
);
7130 old
= (u8
)status
& 0xff;
7131 if ((u8
)vector
!= old
) {
7133 status
|= (u8
)vector
;
7134 vmcs_write16(GUEST_INTR_STATUS
, status
);
7138 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7144 * If a vmexit is needed, vmx_check_nested_events handles it.
7146 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
7149 if (!is_guest_mode(vcpu
)) {
7150 vmx_set_rvi(max_irr
);
7155 * Fall back to pre-APICv interrupt injection since L2
7156 * is run without virtual interrupt delivery.
7158 if (!kvm_event_needs_reinjection(vcpu
) &&
7159 vmx_interrupt_allowed(vcpu
)) {
7160 kvm_queue_interrupt(vcpu
, max_irr
, false);
7161 vmx_inject_irq(vcpu
);
7165 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7167 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7170 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7171 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7172 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7173 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7176 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7180 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7181 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7184 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7185 exit_intr_info
= vmx
->exit_intr_info
;
7187 /* Handle machine checks before interrupts are enabled */
7188 if (is_machine_check(exit_intr_info
))
7189 kvm_machine_check();
7191 /* We need to handle NMIs before interrupts are enabled */
7192 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7193 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7194 kvm_before_handle_nmi(&vmx
->vcpu
);
7196 kvm_after_handle_nmi(&vmx
->vcpu
);
7200 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7202 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7205 * If external interrupt exists, IF bit is set in rflags/eflags on the
7206 * interrupt stack frame, and interrupt will be enabled on a return
7207 * from interrupt handler.
7209 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7210 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7211 unsigned int vector
;
7212 unsigned long entry
;
7214 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7215 #ifdef CONFIG_X86_64
7219 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7220 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7221 entry
= gate_offset(*desc
);
7223 #ifdef CONFIG_X86_64
7224 "mov %%" _ASM_SP
", %[sp]\n\t"
7225 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7230 "orl $0x200, (%%" _ASM_SP
")\n\t"
7231 __ASM_SIZE(push
) " $%c[cs]\n\t"
7232 "call *%[entry]\n\t"
7234 #ifdef CONFIG_X86_64
7239 [ss
]"i"(__KERNEL_DS
),
7240 [cs
]"i"(__KERNEL_CS
)
7246 static bool vmx_mpx_supported(void)
7248 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7249 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7252 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7257 bool idtv_info_valid
;
7259 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7261 if (cpu_has_virtual_nmis()) {
7262 if (vmx
->nmi_known_unmasked
)
7265 * Can't use vmx->exit_intr_info since we're not sure what
7266 * the exit reason is.
7268 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7269 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7270 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7272 * SDM 3: 27.7.1.2 (September 2008)
7273 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7274 * a guest IRET fault.
7275 * SDM 3: 23.2.2 (September 2008)
7276 * Bit 12 is undefined in any of the following cases:
7277 * If the VM exit sets the valid bit in the IDT-vectoring
7278 * information field.
7279 * If the VM exit is due to a double fault.
7281 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7282 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7283 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7284 GUEST_INTR_STATE_NMI
);
7286 vmx
->nmi_known_unmasked
=
7287 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7288 & GUEST_INTR_STATE_NMI
);
7289 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7290 vmx
->vnmi_blocked_time
+=
7291 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7294 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7295 u32 idt_vectoring_info
,
7296 int instr_len_field
,
7297 int error_code_field
)
7301 bool idtv_info_valid
;
7303 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7305 vcpu
->arch
.nmi_injected
= false;
7306 kvm_clear_exception_queue(vcpu
);
7307 kvm_clear_interrupt_queue(vcpu
);
7309 if (!idtv_info_valid
)
7312 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7314 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7315 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7318 case INTR_TYPE_NMI_INTR
:
7319 vcpu
->arch
.nmi_injected
= true;
7321 * SDM 3: 27.7.1.2 (September 2008)
7322 * Clear bit "block by NMI" before VM entry if a NMI
7325 vmx_set_nmi_mask(vcpu
, false);
7327 case INTR_TYPE_SOFT_EXCEPTION
:
7328 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7330 case INTR_TYPE_HARD_EXCEPTION
:
7331 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7332 u32 err
= vmcs_read32(error_code_field
);
7333 kvm_requeue_exception_e(vcpu
, vector
, err
);
7335 kvm_requeue_exception(vcpu
, vector
);
7337 case INTR_TYPE_SOFT_INTR
:
7338 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7340 case INTR_TYPE_EXT_INTR
:
7341 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7348 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7350 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7351 VM_EXIT_INSTRUCTION_LEN
,
7352 IDT_VECTORING_ERROR_CODE
);
7355 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7357 __vmx_complete_interrupts(vcpu
,
7358 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7359 VM_ENTRY_INSTRUCTION_LEN
,
7360 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7362 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7365 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7368 struct perf_guest_switch_msr
*msrs
;
7370 msrs
= perf_guest_get_msrs(&nr_msrs
);
7375 for (i
= 0; i
< nr_msrs
; i
++)
7376 if (msrs
[i
].host
== msrs
[i
].guest
)
7377 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7379 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7383 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7385 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7386 unsigned long debugctlmsr
;
7388 /* Record the guest's net vcpu time for enforced NMI injections. */
7389 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7390 vmx
->entry_time
= ktime_get();
7392 /* Don't enter VMX if guest state is invalid, let the exit handler
7393 start emulation until we arrive back to a valid state */
7394 if (vmx
->emulation_required
)
7397 if (vmx
->ple_window_dirty
) {
7398 vmx
->ple_window_dirty
= false;
7399 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
7402 if (vmx
->nested
.sync_shadow_vmcs
) {
7403 copy_vmcs12_to_shadow(vmx
);
7404 vmx
->nested
.sync_shadow_vmcs
= false;
7407 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7408 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7409 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7410 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7412 /* When single-stepping over STI and MOV SS, we must clear the
7413 * corresponding interruptibility bits in the guest state. Otherwise
7414 * vmentry fails as it then expects bit 14 (BS) in pending debug
7415 * exceptions being set, but that's not correct for the guest debugging
7417 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7418 vmx_set_interrupt_shadow(vcpu
, 0);
7420 atomic_switch_perf_msrs(vmx
);
7421 debugctlmsr
= get_debugctlmsr();
7423 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7425 /* Store host registers */
7426 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7427 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7428 "push %%" _ASM_CX
" \n\t"
7429 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7431 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7432 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7434 /* Reload cr2 if changed */
7435 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7436 "mov %%cr2, %%" _ASM_DX
" \n\t"
7437 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7439 "mov %%" _ASM_AX
", %%cr2 \n\t"
7441 /* Check if vmlaunch of vmresume is needed */
7442 "cmpl $0, %c[launched](%0) \n\t"
7443 /* Load guest registers. Don't clobber flags. */
7444 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7445 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7446 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7447 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7448 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7449 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7450 #ifdef CONFIG_X86_64
7451 "mov %c[r8](%0), %%r8 \n\t"
7452 "mov %c[r9](%0), %%r9 \n\t"
7453 "mov %c[r10](%0), %%r10 \n\t"
7454 "mov %c[r11](%0), %%r11 \n\t"
7455 "mov %c[r12](%0), %%r12 \n\t"
7456 "mov %c[r13](%0), %%r13 \n\t"
7457 "mov %c[r14](%0), %%r14 \n\t"
7458 "mov %c[r15](%0), %%r15 \n\t"
7460 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7462 /* Enter guest mode */
7464 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7466 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7468 /* Save guest registers, load host registers, keep flags */
7469 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7471 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7472 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7473 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7474 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7475 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7476 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7477 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7478 #ifdef CONFIG_X86_64
7479 "mov %%r8, %c[r8](%0) \n\t"
7480 "mov %%r9, %c[r9](%0) \n\t"
7481 "mov %%r10, %c[r10](%0) \n\t"
7482 "mov %%r11, %c[r11](%0) \n\t"
7483 "mov %%r12, %c[r12](%0) \n\t"
7484 "mov %%r13, %c[r13](%0) \n\t"
7485 "mov %%r14, %c[r14](%0) \n\t"
7486 "mov %%r15, %c[r15](%0) \n\t"
7488 "mov %%cr2, %%" _ASM_AX
" \n\t"
7489 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7491 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7492 "setbe %c[fail](%0) \n\t"
7493 ".pushsection .rodata \n\t"
7494 ".global vmx_return \n\t"
7495 "vmx_return: " _ASM_PTR
" 2b \n\t"
7497 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7498 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7499 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7500 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7501 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7502 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7503 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7504 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7505 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7506 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7507 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7508 #ifdef CONFIG_X86_64
7509 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7510 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7511 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7512 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7513 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7514 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7515 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7516 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7518 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7519 [wordsize
]"i"(sizeof(ulong
))
7521 #ifdef CONFIG_X86_64
7522 , "rax", "rbx", "rdi", "rsi"
7523 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7525 , "eax", "ebx", "edi", "esi"
7529 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7531 update_debugctlmsr(debugctlmsr
);
7533 #ifndef CONFIG_X86_64
7535 * The sysexit path does not restore ds/es, so we must set them to
7536 * a reasonable value ourselves.
7538 * We can't defer this to vmx_load_host_state() since that function
7539 * may be executed in interrupt context, which saves and restore segments
7540 * around it, nullifying its effect.
7542 loadsegment(ds
, __USER_DS
);
7543 loadsegment(es
, __USER_DS
);
7546 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7547 | (1 << VCPU_EXREG_RFLAGS
)
7548 | (1 << VCPU_EXREG_PDPTR
)
7549 | (1 << VCPU_EXREG_SEGMENTS
)
7550 | (1 << VCPU_EXREG_CR3
));
7551 vcpu
->arch
.regs_dirty
= 0;
7553 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7555 vmx
->loaded_vmcs
->launched
= 1;
7557 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7558 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7561 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7562 * we did not inject a still-pending event to L1 now because of
7563 * nested_run_pending, we need to re-enable this bit.
7565 if (vmx
->nested
.nested_run_pending
)
7566 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7568 vmx
->nested
.nested_run_pending
= 0;
7570 vmx_complete_atomic_exit(vmx
);
7571 vmx_recover_nmi_blocking(vmx
);
7572 vmx_complete_interrupts(vmx
);
7575 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
7577 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7580 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
7584 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7586 vmx_vcpu_load(vcpu
, cpu
);
7591 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7593 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7596 leave_guest_mode(vcpu
);
7597 vmx_load_vmcs01(vcpu
);
7599 free_loaded_vmcs(vmx
->loaded_vmcs
);
7600 kfree(vmx
->guest_msrs
);
7601 kvm_vcpu_uninit(vcpu
);
7602 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7605 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7608 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7612 return ERR_PTR(-ENOMEM
);
7616 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7620 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7621 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
7625 if (!vmx
->guest_msrs
) {
7629 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7630 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7631 if (!vmx
->loaded_vmcs
->vmcs
)
7634 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7635 loaded_vmcs_init(vmx
->loaded_vmcs
);
7640 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7641 vmx
->vcpu
.cpu
= cpu
;
7642 err
= vmx_vcpu_setup(vmx
);
7643 vmx_vcpu_put(&vmx
->vcpu
);
7647 if (vm_need_virtualize_apic_accesses(kvm
)) {
7648 err
= alloc_apic_access_page(kvm
);
7654 if (!kvm
->arch
.ept_identity_map_addr
)
7655 kvm
->arch
.ept_identity_map_addr
=
7656 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7658 if (alloc_identity_pagetable(kvm
) != 0)
7660 if (!init_rmode_identity_map(kvm
))
7664 vmx
->nested
.current_vmptr
= -1ull;
7665 vmx
->nested
.current_vmcs12
= NULL
;
7670 free_loaded_vmcs(vmx
->loaded_vmcs
);
7672 kfree(vmx
->guest_msrs
);
7674 kvm_vcpu_uninit(&vmx
->vcpu
);
7677 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7678 return ERR_PTR(err
);
7681 static void __init
vmx_check_processor_compat(void *rtn
)
7683 struct vmcs_config vmcs_conf
;
7686 if (setup_vmcs_config(&vmcs_conf
) < 0)
7688 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7689 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7690 smp_processor_id());
7695 static int get_ept_level(void)
7697 return VMX_EPT_DEFAULT_GAW
+ 1;
7700 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7704 /* For VT-d and EPT combination
7705 * 1. MMIO: always map as UC
7707 * a. VT-d without snooping control feature: can't guarantee the
7708 * result, try to trust guest.
7709 * b. VT-d with snooping control feature: snooping control feature of
7710 * VT-d engine can guarantee the cache correctness. Just set it
7711 * to WB to keep consistent with host. So the same as item 3.
7712 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7713 * consistent with host MTRR
7716 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7717 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7718 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7719 VMX_EPT_MT_EPTE_SHIFT
;
7721 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7727 static int vmx_get_lpage_level(void)
7729 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7730 return PT_DIRECTORY_LEVEL
;
7732 /* For shadow and EPT supported 1GB page */
7733 return PT_PDPE_LEVEL
;
7736 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7738 struct kvm_cpuid_entry2
*best
;
7739 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7742 vmx
->rdtscp_enabled
= false;
7743 if (vmx_rdtscp_supported()) {
7744 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7745 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7746 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7747 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7748 vmx
->rdtscp_enabled
= true;
7750 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7751 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7757 /* Exposing INVPCID only when PCID is exposed */
7758 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7759 if (vmx_invpcid_supported() &&
7760 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7761 guest_cpuid_has_pcid(vcpu
)) {
7762 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7763 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7764 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7767 if (cpu_has_secondary_exec_ctrls()) {
7768 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7769 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7770 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7774 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7778 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7780 if (func
== 1 && nested
)
7781 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7784 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7785 struct x86_exception
*fault
)
7787 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7790 if (fault
->error_code
& PFERR_RSVD_MASK
)
7791 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7793 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7794 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7795 vmcs12
->guest_physical_address
= fault
->address
;
7798 /* Callbacks for nested_ept_init_mmu_context: */
7800 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7802 /* return the page table to be shadowed - in our case, EPT12 */
7803 return get_vmcs12(vcpu
)->ept_pointer
;
7806 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7808 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7809 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7811 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7812 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7813 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7815 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7818 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7820 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7823 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7824 struct x86_exception
*fault
)
7826 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7828 WARN_ON(!is_guest_mode(vcpu
));
7830 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7831 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7832 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7833 vmcs_read32(VM_EXIT_INTR_INFO
),
7834 vmcs_readl(EXIT_QUALIFICATION
));
7836 kvm_inject_page_fault(vcpu
, fault
);
7839 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
7841 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
7842 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7844 if (vcpu
->arch
.virtual_tsc_khz
== 0)
7847 /* Make sure short timeouts reliably trigger an immediate vmexit.
7848 * hrtimer_start does not guarantee this. */
7849 if (preemption_timeout
<= 1) {
7850 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
7854 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
7855 preemption_timeout
*= 1000000;
7856 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
7857 hrtimer_start(&vmx
->nested
.preemption_timer
,
7858 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
7862 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7863 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7864 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7865 * guest in a way that will both be appropriate to L1's requests, and our
7866 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7867 * function also has additional necessary side-effects, like setting various
7868 * vcpu->arch fields.
7870 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7872 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7875 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7876 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7877 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7878 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7879 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7880 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7881 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7882 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7883 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7884 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7885 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7886 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7887 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7888 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7889 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7890 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7891 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7892 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7893 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7894 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7895 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7896 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7897 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7898 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7899 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7900 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7901 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7902 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7903 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7904 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7905 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7906 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7907 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7908 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7909 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7910 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7912 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
7913 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7914 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7916 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
7917 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
7919 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7920 vmcs12
->vm_entry_intr_info_field
);
7921 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7922 vmcs12
->vm_entry_exception_error_code
);
7923 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7924 vmcs12
->vm_entry_instruction_len
);
7925 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7926 vmcs12
->guest_interruptibility_info
);
7927 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7928 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7929 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7930 vmcs12
->guest_pending_dbg_exceptions
);
7931 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7932 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7934 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7936 exec_control
= vmcs12
->pin_based_vm_exec_control
;
7937 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
7938 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
7939 PIN_BASED_POSTED_INTR
);
7940 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
7942 vmx
->nested
.preemption_timer_expired
= false;
7943 if (nested_cpu_has_preemption_timer(vmcs12
))
7944 vmx_start_preemption_timer(vcpu
);
7947 * Whether page-faults are trapped is determined by a combination of
7948 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7949 * If enable_ept, L0 doesn't care about page faults and we should
7950 * set all of these to L1's desires. However, if !enable_ept, L0 does
7951 * care about (at least some) page faults, and because it is not easy
7952 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7953 * to exit on each and every L2 page fault. This is done by setting
7954 * MASK=MATCH=0 and (see below) EB.PF=1.
7955 * Note that below we don't need special code to set EB.PF beyond the
7956 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7957 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7958 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7960 * A problem with this approach (when !enable_ept) is that L1 may be
7961 * injected with more page faults than it asked for. This could have
7962 * caused problems, but in practice existing hypervisors don't care.
7963 * To fix this, we will need to emulate the PFEC checking (on the L1
7964 * page tables), using walk_addr(), when injecting PFs to L1.
7966 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7967 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7968 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7969 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7971 if (cpu_has_secondary_exec_ctrls()) {
7972 exec_control
= vmx_secondary_exec_control(vmx
);
7973 if (!vmx
->rdtscp_enabled
)
7974 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7975 /* Take the following fields only from vmcs12 */
7976 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
7977 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
7978 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
7979 if (nested_cpu_has(vmcs12
,
7980 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7981 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7983 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7985 * Translate L1 physical address to host physical
7986 * address for vmcs02. Keep the page pinned, so this
7987 * physical address remains valid. We keep a reference
7988 * to it so we can release it later.
7990 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7991 nested_release_page(vmx
->nested
.apic_access_page
);
7992 vmx
->nested
.apic_access_page
=
7993 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7995 * If translation failed, no matter: This feature asks
7996 * to exit when accessing the given address, and if it
7997 * can never be accessed, this feature won't do
8000 if (!vmx
->nested
.apic_access_page
)
8002 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8004 vmcs_write64(APIC_ACCESS_ADDR
,
8005 page_to_phys(vmx
->nested
.apic_access_page
));
8006 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
8008 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8009 vmcs_write64(APIC_ACCESS_ADDR
,
8010 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
8013 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
8018 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8019 * Some constant fields are set here by vmx_set_constant_host_state().
8020 * Other fields are different per CPU, and will be set later when
8021 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8023 vmx_set_constant_host_state(vmx
);
8026 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8027 * entry, but only if the current (host) sp changed from the value
8028 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8029 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8030 * here we just force the write to happen on entry.
8034 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
8035 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
8036 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
8037 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
8038 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
8040 * Merging of IO and MSR bitmaps not currently supported.
8041 * Rather, exit every time.
8043 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
8044 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
8045 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
8047 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
8049 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8050 * bitwise-or of what L1 wants to trap for L2, and what we want to
8051 * trap. Note that CR0.TS also needs updating - we do this later.
8053 update_exception_bitmap(vcpu
);
8054 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
8055 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8057 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8058 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8059 * bits are further modified by vmx_set_efer() below.
8061 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
8063 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8064 * emulated by vmx_set_efer(), below.
8066 vm_entry_controls_init(vmx
,
8067 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
8068 ~VM_ENTRY_IA32E_MODE
) |
8069 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
8071 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
8072 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
8073 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
8074 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
8075 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
8078 set_cr4_guest_host_mask(vmx
);
8080 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
8081 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
8083 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
8084 vmcs_write64(TSC_OFFSET
,
8085 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
8087 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8091 * Trivially support vpid by letting L2s share their parent
8092 * L1's vpid. TODO: move to a more elaborate solution, giving
8093 * each L2 its own vpid and exposing the vpid feature to L1.
8095 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
8096 vmx_flush_tlb(vcpu
);
8099 if (nested_cpu_has_ept(vmcs12
)) {
8100 kvm_mmu_unload(vcpu
);
8101 nested_ept_init_mmu_context(vcpu
);
8104 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
8105 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
8106 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
8107 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8109 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8110 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8111 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8114 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8115 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8116 * The CR0_READ_SHADOW is what L2 should have expected to read given
8117 * the specifications by L1; It's not enough to take
8118 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8119 * have more bits than L1 expected.
8121 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
8122 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
8124 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
8125 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
8127 /* shadow page tables on either EPT or shadow page tables */
8128 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
8129 kvm_mmu_reset_context(vcpu
);
8132 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
8135 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8138 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
8139 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
8140 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
8141 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
8144 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
8145 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
8149 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8150 * for running an L2 nested guest.
8152 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
8154 struct vmcs12
*vmcs12
;
8155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8157 struct loaded_vmcs
*vmcs02
;
8160 if (!nested_vmx_check_permission(vcpu
) ||
8161 !nested_vmx_check_vmcs12(vcpu
))
8164 skip_emulated_instruction(vcpu
);
8165 vmcs12
= get_vmcs12(vcpu
);
8167 if (enable_shadow_vmcs
)
8168 copy_shadow_to_vmcs12(vmx
);
8171 * The nested entry process starts with enforcing various prerequisites
8172 * on vmcs12 as required by the Intel SDM, and act appropriately when
8173 * they fail: As the SDM explains, some conditions should cause the
8174 * instruction to fail, while others will cause the instruction to seem
8175 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8176 * To speed up the normal (success) code path, we should avoid checking
8177 * for misconfigurations which will anyway be caught by the processor
8178 * when using the merged vmcs02.
8180 if (vmcs12
->launch_state
== launch
) {
8181 nested_vmx_failValid(vcpu
,
8182 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8183 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
8187 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
8188 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
8189 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8193 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
8194 !PAGE_ALIGNED(vmcs12
->msr_bitmap
)) {
8195 /*TODO: Also verify bits beyond physical address width are 0*/
8196 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8200 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
8201 !PAGE_ALIGNED(vmcs12
->apic_access_addr
)) {
8202 /*TODO: Also verify bits beyond physical address width are 0*/
8203 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8207 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8208 vmcs12
->vm_exit_msr_load_count
> 0 ||
8209 vmcs12
->vm_exit_msr_store_count
> 0) {
8210 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8212 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8216 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8217 nested_vmx_true_procbased_ctls_low
,
8218 nested_vmx_procbased_ctls_high
) ||
8219 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8220 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8221 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8222 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8223 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8224 nested_vmx_true_exit_ctls_low
,
8225 nested_vmx_exit_ctls_high
) ||
8226 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8227 nested_vmx_true_entry_ctls_low
,
8228 nested_vmx_entry_ctls_high
))
8230 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8234 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8235 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8236 nested_vmx_failValid(vcpu
,
8237 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8241 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8242 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8243 nested_vmx_entry_failure(vcpu
, vmcs12
,
8244 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8247 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8248 nested_vmx_entry_failure(vcpu
, vmcs12
,
8249 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8254 * If the load IA32_EFER VM-entry control is 1, the following checks
8255 * are performed on the field for the IA32_EFER MSR:
8256 * - Bits reserved in the IA32_EFER MSR must be 0.
8257 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8258 * the IA-32e mode guest VM-exit control. It must also be identical
8259 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8262 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8263 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8264 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8265 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8266 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8267 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8268 nested_vmx_entry_failure(vcpu
, vmcs12
,
8269 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8275 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8276 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8277 * the values of the LMA and LME bits in the field must each be that of
8278 * the host address-space size VM-exit control.
8280 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8281 ia32e
= (vmcs12
->vm_exit_controls
&
8282 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8283 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8284 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8285 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8286 nested_vmx_entry_failure(vcpu
, vmcs12
,
8287 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8293 * We're finally done with prerequisite checking, and can start with
8297 vmcs02
= nested_get_current_vmcs02(vmx
);
8301 enter_guest_mode(vcpu
);
8303 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8305 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
8306 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8309 vmx
->loaded_vmcs
= vmcs02
;
8311 vmx_vcpu_load(vcpu
, cpu
);
8315 vmx_segment_cache_clear(vmx
);
8317 vmcs12
->launch_state
= 1;
8319 prepare_vmcs02(vcpu
, vmcs12
);
8321 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8322 return kvm_emulate_halt(vcpu
);
8324 vmx
->nested
.nested_run_pending
= 1;
8327 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8328 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8329 * returned as far as L1 is concerned. It will only return (and set
8330 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8336 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8337 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8338 * This function returns the new value we should put in vmcs12.guest_cr0.
8339 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8340 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8341 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8342 * didn't trap the bit, because if L1 did, so would L0).
8343 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8344 * been modified by L2, and L1 knows it. So just leave the old value of
8345 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8346 * isn't relevant, because if L0 traps this bit it can set it to anything.
8347 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8348 * changed these bits, and therefore they need to be updated, but L0
8349 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8350 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8352 static inline unsigned long
8353 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8356 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8357 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8358 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8359 vcpu
->arch
.cr0_guest_owned_bits
));
8362 static inline unsigned long
8363 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8366 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8367 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8368 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8369 vcpu
->arch
.cr4_guest_owned_bits
));
8372 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8373 struct vmcs12
*vmcs12
)
8378 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8379 nr
= vcpu
->arch
.exception
.nr
;
8380 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8382 if (kvm_exception_is_soft(nr
)) {
8383 vmcs12
->vm_exit_instruction_len
=
8384 vcpu
->arch
.event_exit_inst_len
;
8385 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8387 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8389 if (vcpu
->arch
.exception
.has_error_code
) {
8390 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8391 vmcs12
->idt_vectoring_error_code
=
8392 vcpu
->arch
.exception
.error_code
;
8395 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8396 } else if (vcpu
->arch
.nmi_injected
) {
8397 vmcs12
->idt_vectoring_info_field
=
8398 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8399 } else if (vcpu
->arch
.interrupt
.pending
) {
8400 nr
= vcpu
->arch
.interrupt
.nr
;
8401 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8403 if (vcpu
->arch
.interrupt
.soft
) {
8404 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8405 vmcs12
->vm_entry_instruction_len
=
8406 vcpu
->arch
.event_exit_inst_len
;
8408 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8410 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8414 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8416 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8418 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8419 vmx
->nested
.preemption_timer_expired
) {
8420 if (vmx
->nested
.nested_run_pending
)
8422 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8426 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8427 if (vmx
->nested
.nested_run_pending
||
8428 vcpu
->arch
.interrupt
.pending
)
8430 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8431 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8432 INTR_INFO_VALID_MASK
, 0);
8434 * The NMI-triggered VM exit counts as injection:
8435 * clear this one and block further NMIs.
8437 vcpu
->arch
.nmi_pending
= 0;
8438 vmx_set_nmi_mask(vcpu
, true);
8442 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8443 nested_exit_on_intr(vcpu
)) {
8444 if (vmx
->nested
.nested_run_pending
)
8446 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8452 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8455 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8458 if (ktime_to_ns(remaining
) <= 0)
8461 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8462 do_div(value
, 1000000);
8463 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8467 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8468 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8469 * and this function updates it to reflect the changes to the guest state while
8470 * L2 was running (and perhaps made some exits which were handled directly by L0
8471 * without going back to L1), and to reflect the exit reason.
8472 * Note that we do not have to copy here all VMCS fields, just those that
8473 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8474 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8475 * which already writes to vmcs12 directly.
8477 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8478 u32 exit_reason
, u32 exit_intr_info
,
8479 unsigned long exit_qualification
)
8481 /* update guest state fields: */
8482 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8483 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8485 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8486 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8487 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8489 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8490 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8491 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8492 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8493 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8494 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8495 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8496 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8497 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8498 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8499 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8500 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8501 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8502 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8503 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8504 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8505 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8506 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8507 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8508 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8509 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8510 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8511 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8512 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8513 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8514 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8515 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8516 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8517 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8518 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8519 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8520 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8521 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8522 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8523 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8524 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8526 vmcs12
->guest_interruptibility_info
=
8527 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8528 vmcs12
->guest_pending_dbg_exceptions
=
8529 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8530 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8531 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8533 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8535 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8536 if (vmcs12
->vm_exit_controls
&
8537 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8538 vmcs12
->vmx_preemption_timer_value
=
8539 vmx_get_preemption_timer_value(vcpu
);
8540 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8544 * In some cases (usually, nested EPT), L2 is allowed to change its
8545 * own CR3 without exiting. If it has changed it, we must keep it.
8546 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8547 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8549 * Additionally, restore L2's PDPTR to vmcs12.
8552 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8553 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8554 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8555 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8556 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8559 vmcs12
->vm_entry_controls
=
8560 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8561 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8563 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
8564 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8565 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8568 /* TODO: These cannot have changed unless we have MSR bitmaps and
8569 * the relevant bit asks not to trap the change */
8570 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8571 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8572 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8573 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8574 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8575 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8576 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8577 if (vmx_mpx_supported())
8578 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8580 /* update exit information fields: */
8582 vmcs12
->vm_exit_reason
= exit_reason
;
8583 vmcs12
->exit_qualification
= exit_qualification
;
8585 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8586 if ((vmcs12
->vm_exit_intr_info
&
8587 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8588 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8589 vmcs12
->vm_exit_intr_error_code
=
8590 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8591 vmcs12
->idt_vectoring_info_field
= 0;
8592 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8593 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8595 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8596 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8597 * instead of reading the real value. */
8598 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8601 * Transfer the event that L0 or L1 may wanted to inject into
8602 * L2 to IDT_VECTORING_INFO_FIELD.
8604 vmcs12_save_pending_event(vcpu
, vmcs12
);
8608 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8609 * preserved above and would only end up incorrectly in L1.
8611 vcpu
->arch
.nmi_injected
= false;
8612 kvm_clear_exception_queue(vcpu
);
8613 kvm_clear_interrupt_queue(vcpu
);
8617 * A part of what we need to when the nested L2 guest exits and we want to
8618 * run its L1 parent, is to reset L1's guest state to the host state specified
8620 * This function is to be called not only on normal nested exit, but also on
8621 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8622 * Failures During or After Loading Guest State").
8623 * This function should be called when the active VMCS is L1's (vmcs01).
8625 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8626 struct vmcs12
*vmcs12
)
8628 struct kvm_segment seg
;
8630 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8631 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8632 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8633 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8635 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8636 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8638 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8639 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8640 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8642 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8643 * actually changed, because it depends on the current state of
8644 * fpu_active (which may have changed).
8645 * Note that vmx_set_cr0 refers to efer set above.
8647 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8649 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8650 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8651 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8653 update_exception_bitmap(vcpu
);
8654 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8655 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8658 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8659 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8661 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8662 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8664 nested_ept_uninit_mmu_context(vcpu
);
8666 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8667 kvm_mmu_reset_context(vcpu
);
8670 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8674 * Trivially support vpid by letting L2s share their parent
8675 * L1's vpid. TODO: move to a more elaborate solution, giving
8676 * each L2 its own vpid and exposing the vpid feature to L1.
8678 vmx_flush_tlb(vcpu
);
8682 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8683 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8684 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8685 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8686 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8688 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8689 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
8690 vmcs_write64(GUEST_BNDCFGS
, 0);
8692 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8693 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8694 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8696 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8697 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8698 vmcs12
->host_ia32_perf_global_ctrl
);
8700 /* Set L1 segment info according to Intel SDM
8701 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8702 seg
= (struct kvm_segment
) {
8704 .limit
= 0xFFFFFFFF,
8705 .selector
= vmcs12
->host_cs_selector
,
8711 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8715 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8716 seg
= (struct kvm_segment
) {
8718 .limit
= 0xFFFFFFFF,
8725 seg
.selector
= vmcs12
->host_ds_selector
;
8726 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8727 seg
.selector
= vmcs12
->host_es_selector
;
8728 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8729 seg
.selector
= vmcs12
->host_ss_selector
;
8730 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8731 seg
.selector
= vmcs12
->host_fs_selector
;
8732 seg
.base
= vmcs12
->host_fs_base
;
8733 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8734 seg
.selector
= vmcs12
->host_gs_selector
;
8735 seg
.base
= vmcs12
->host_gs_base
;
8736 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8737 seg
= (struct kvm_segment
) {
8738 .base
= vmcs12
->host_tr_base
,
8740 .selector
= vmcs12
->host_tr_selector
,
8744 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8746 kvm_set_dr(vcpu
, 7, 0x400);
8747 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8751 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8752 * and modify vmcs12 to make it see what it would expect to see there if
8753 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8755 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8757 unsigned long exit_qualification
)
8759 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8760 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8762 /* trying to cancel vmlaunch/vmresume is a bug */
8763 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8765 leave_guest_mode(vcpu
);
8766 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8767 exit_qualification
);
8769 vmx_load_vmcs01(vcpu
);
8771 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
8772 && nested_exit_intr_ack_set(vcpu
)) {
8773 int irq
= kvm_cpu_get_interrupt(vcpu
);
8775 vmcs12
->vm_exit_intr_info
= irq
|
8776 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
8779 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8780 vmcs12
->exit_qualification
,
8781 vmcs12
->idt_vectoring_info_field
,
8782 vmcs12
->vm_exit_intr_info
,
8783 vmcs12
->vm_exit_intr_error_code
,
8786 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8787 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8788 vmx_segment_cache_clear(vmx
);
8790 /* if no vmcs02 cache requested, remove the one we used */
8791 if (VMCS02_POOL_SIZE
== 0)
8792 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8794 load_vmcs12_host_state(vcpu
, vmcs12
);
8796 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8797 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8799 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8802 /* Unpin physical memory we referred to in vmcs02 */
8803 if (vmx
->nested
.apic_access_page
) {
8804 nested_release_page(vmx
->nested
.apic_access_page
);
8805 vmx
->nested
.apic_access_page
= 0;
8809 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8810 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8811 * success or failure flag accordingly.
8813 if (unlikely(vmx
->fail
)) {
8815 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8817 nested_vmx_succeed(vcpu
);
8818 if (enable_shadow_vmcs
)
8819 vmx
->nested
.sync_shadow_vmcs
= true;
8821 /* in case we halted in L2 */
8822 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
8826 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8828 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8830 if (is_guest_mode(vcpu
))
8831 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8832 free_nested(to_vmx(vcpu
));
8836 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8837 * 23.7 "VM-entry failures during or after loading guest state" (this also
8838 * lists the acceptable exit-reason and exit-qualification parameters).
8839 * It should only be called before L2 actually succeeded to run, and when
8840 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8842 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8843 struct vmcs12
*vmcs12
,
8844 u32 reason
, unsigned long qualification
)
8846 load_vmcs12_host_state(vcpu
, vmcs12
);
8847 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8848 vmcs12
->exit_qualification
= qualification
;
8849 nested_vmx_succeed(vcpu
);
8850 if (enable_shadow_vmcs
)
8851 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8854 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8855 struct x86_instruction_info
*info
,
8856 enum x86_intercept_stage stage
)
8858 return X86EMUL_CONTINUE
;
8861 void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
8865 static struct kvm_x86_ops vmx_x86_ops
= {
8866 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8867 .disabled_by_bios
= vmx_disabled_by_bios
,
8868 .hardware_setup
= hardware_setup
,
8869 .hardware_unsetup
= hardware_unsetup
,
8870 .check_processor_compatibility
= vmx_check_processor_compat
,
8871 .hardware_enable
= hardware_enable
,
8872 .hardware_disable
= hardware_disable
,
8873 .cpu_has_accelerated_tpr
= report_flexpriority
,
8875 .vcpu_create
= vmx_create_vcpu
,
8876 .vcpu_free
= vmx_free_vcpu
,
8877 .vcpu_reset
= vmx_vcpu_reset
,
8879 .prepare_guest_switch
= vmx_save_host_state
,
8880 .vcpu_load
= vmx_vcpu_load
,
8881 .vcpu_put
= vmx_vcpu_put
,
8883 .update_db_bp_intercept
= update_exception_bitmap
,
8884 .get_msr
= vmx_get_msr
,
8885 .set_msr
= vmx_set_msr
,
8886 .get_segment_base
= vmx_get_segment_base
,
8887 .get_segment
= vmx_get_segment
,
8888 .set_segment
= vmx_set_segment
,
8889 .get_cpl
= vmx_get_cpl
,
8890 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8891 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8892 .decache_cr3
= vmx_decache_cr3
,
8893 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8894 .set_cr0
= vmx_set_cr0
,
8895 .set_cr3
= vmx_set_cr3
,
8896 .set_cr4
= vmx_set_cr4
,
8897 .set_efer
= vmx_set_efer
,
8898 .get_idt
= vmx_get_idt
,
8899 .set_idt
= vmx_set_idt
,
8900 .get_gdt
= vmx_get_gdt
,
8901 .set_gdt
= vmx_set_gdt
,
8902 .get_dr6
= vmx_get_dr6
,
8903 .set_dr6
= vmx_set_dr6
,
8904 .set_dr7
= vmx_set_dr7
,
8905 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
8906 .cache_reg
= vmx_cache_reg
,
8907 .get_rflags
= vmx_get_rflags
,
8908 .set_rflags
= vmx_set_rflags
,
8909 .fpu_deactivate
= vmx_fpu_deactivate
,
8911 .tlb_flush
= vmx_flush_tlb
,
8913 .run
= vmx_vcpu_run
,
8914 .handle_exit
= vmx_handle_exit
,
8915 .skip_emulated_instruction
= skip_emulated_instruction
,
8916 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8917 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8918 .patch_hypercall
= vmx_patch_hypercall
,
8919 .set_irq
= vmx_inject_irq
,
8920 .set_nmi
= vmx_inject_nmi
,
8921 .queue_exception
= vmx_queue_exception
,
8922 .cancel_injection
= vmx_cancel_injection
,
8923 .interrupt_allowed
= vmx_interrupt_allowed
,
8924 .nmi_allowed
= vmx_nmi_allowed
,
8925 .get_nmi_mask
= vmx_get_nmi_mask
,
8926 .set_nmi_mask
= vmx_set_nmi_mask
,
8927 .enable_nmi_window
= enable_nmi_window
,
8928 .enable_irq_window
= enable_irq_window
,
8929 .update_cr8_intercept
= update_cr8_intercept
,
8930 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8931 .vm_has_apicv
= vmx_vm_has_apicv
,
8932 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8933 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8934 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8935 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8936 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8938 .set_tss_addr
= vmx_set_tss_addr
,
8939 .get_tdp_level
= get_ept_level
,
8940 .get_mt_mask
= vmx_get_mt_mask
,
8942 .get_exit_info
= vmx_get_exit_info
,
8944 .get_lpage_level
= vmx_get_lpage_level
,
8946 .cpuid_update
= vmx_cpuid_update
,
8948 .rdtscp_supported
= vmx_rdtscp_supported
,
8949 .invpcid_supported
= vmx_invpcid_supported
,
8951 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8953 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8955 .set_tsc_khz
= vmx_set_tsc_khz
,
8956 .read_tsc_offset
= vmx_read_tsc_offset
,
8957 .write_tsc_offset
= vmx_write_tsc_offset
,
8958 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8959 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8960 .read_l1_tsc
= vmx_read_l1_tsc
,
8962 .set_tdp_cr3
= vmx_set_cr3
,
8964 .check_intercept
= vmx_check_intercept
,
8965 .handle_external_intr
= vmx_handle_external_intr
,
8966 .mpx_supported
= vmx_mpx_supported
,
8968 .check_nested_events
= vmx_check_nested_events
,
8970 .sched_in
= vmx_sched_in
,
8973 static int __init
vmx_init(void)
8977 rdmsrl_safe(MSR_EFER
, &host_efer
);
8979 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
8980 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8982 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8983 if (!vmx_io_bitmap_a
)
8988 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8989 if (!vmx_io_bitmap_b
)
8992 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8993 if (!vmx_msr_bitmap_legacy
)
8996 vmx_msr_bitmap_legacy_x2apic
=
8997 (unsigned long *)__get_free_page(GFP_KERNEL
);
8998 if (!vmx_msr_bitmap_legacy_x2apic
)
9001 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9002 if (!vmx_msr_bitmap_longmode
)
9005 vmx_msr_bitmap_longmode_x2apic
=
9006 (unsigned long *)__get_free_page(GFP_KERNEL
);
9007 if (!vmx_msr_bitmap_longmode_x2apic
)
9009 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9010 if (!vmx_vmread_bitmap
)
9013 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
9014 if (!vmx_vmwrite_bitmap
)
9017 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
9018 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
9021 * Allow direct access to the PC debug port (it is often used for I/O
9022 * delays, but the vmexits simply slow things down).
9024 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
9025 clear_bit(0x80, vmx_io_bitmap_a
);
9027 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
9029 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
9030 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
9032 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
9034 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
9035 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
9040 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
9041 crash_vmclear_local_loaded_vmcss
);
9044 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
9045 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
9046 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
9047 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
9048 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
9049 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
9050 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
9052 memcpy(vmx_msr_bitmap_legacy_x2apic
,
9053 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
9054 memcpy(vmx_msr_bitmap_longmode_x2apic
,
9055 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
9058 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9059 vmx_disable_intercept_msr_read_x2apic(msr
);
9061 /* According SDM, in x2apic mode, the whole id reg is used.
9062 * But in KVM, it only use the highest eight bits. Need to
9064 vmx_enable_intercept_msr_read_x2apic(0x802);
9066 vmx_enable_intercept_msr_read_x2apic(0x839);
9068 vmx_disable_intercept_msr_write_x2apic(0x808);
9070 vmx_disable_intercept_msr_write_x2apic(0x80b);
9072 vmx_disable_intercept_msr_write_x2apic(0x83f);
9076 kvm_mmu_set_mask_ptes(0ull,
9077 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
9078 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
9079 0ull, VMX_EPT_EXECUTABLE_MASK
);
9080 ept_set_mmio_spte_mask();
9088 free_page((unsigned long)vmx_vmwrite_bitmap
);
9090 free_page((unsigned long)vmx_vmread_bitmap
);
9092 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9094 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9096 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9098 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9100 free_page((unsigned long)vmx_io_bitmap_b
);
9102 free_page((unsigned long)vmx_io_bitmap_a
);
9106 static void __exit
vmx_exit(void)
9108 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9109 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9110 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9111 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9112 free_page((unsigned long)vmx_io_bitmap_b
);
9113 free_page((unsigned long)vmx_io_bitmap_a
);
9114 free_page((unsigned long)vmx_vmwrite_bitmap
);
9115 free_page((unsigned long)vmx_vmread_bitmap
);
9118 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
9125 module_init(vmx_init
)
9126 module_exit(vmx_exit
)