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KVM: VMX: make PLE window per-VCPU
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
3573e22c 357 gpa_t vmxon_ptr;
a9d30f33
NHE		 358
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 gpa_t current_vmptr;
361 /* The host-usable pointer to the above */
362 struct page *current_vmcs12_page;
363 struct vmcs12 *current_vmcs12;
8de48833 364 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 365 /*
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
368 */
369 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 370
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool;
373 int vmcs02_num;
fe3ef05c 374 u64 vmcs01_tsc_offset;
644d711a
NHE		 375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending;
fe3ef05c
NHE		 377 /*
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
380 */
381 struct page *apic_access_page;
b3897a49 382 u64 msr_ia32_feature_control;
f4124500
JK		 383
384 struct hrtimer preemption_timer;
385 bool preemption_timer_expired;
2996fca0
JK		 386
387 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
388 u64 vmcs01_debugctl;
ec378aee
NHE		 389};
390
01e439be
YZ		 391#define POSTED_INTR_ON 0
392/* Posted-Interrupt Descriptor */
393struct pi_desc {
394 u32 pir[8]; /* Posted interrupt requested */
395 u32 control; /* bit 0 of control is outstanding notification bit */
396 u32 rsvd[7];
397} __aligned(64);
398
a20ed54d
YZ		 399static bool pi_test_and_set_on(struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(POSTED_INTR_ON,
402 (unsigned long *)&pi_desc->control);
403}
404
405static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
406{
407 return test_and_clear_bit(POSTED_INTR_ON,
408 (unsigned long *)&pi_desc->control);
409}
410
411static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
412{
413 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
414}
415
a2fa3e9f 416struct vcpu_vmx {
fb3f0f51 417 struct kvm_vcpu vcpu;
313dbd49 418 unsigned long host_rsp;
29bd8a78 419 u8 fail;
9d58b931 420 bool nmi_known_unmasked;
51aa01d1 421 u32 exit_intr_info;
1155f76a 422 u32 idt_vectoring_info;
6de12732 423 ulong rflags;
26bb0981 424 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 425 int nmsrs;
426 int save_nmsrs;
a547c6db 427 unsigned long host_idt_base;
a2fa3e9f 428#ifdef CONFIG_X86_64
44ea2b17
AK		 429 u64 msr_host_kernel_gs_base;
430 u64 msr_guest_kernel_gs_base;
a2fa3e9f 431#endif
2961e876
GN		 432 u32 vm_entry_controls_shadow;
433 u32 vm_exit_controls_shadow;
d462b819
NHE		 434 /*
435 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
436 * non-nested (L1) guest, it always points to vmcs01. For a nested
437 * guest (L2), it points to a different VMCS.
438 */
439 struct loaded_vmcs vmcs01;
440 struct loaded_vmcs *loaded_vmcs;
441 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 442 struct msr_autoload {
443 unsigned nr;
444 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
445 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
446 } msr_autoload;
a2fa3e9f
GH		 447 struct {
448 int loaded;
449 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 450#ifdef CONFIG_X86_64
451 u16 ds_sel, es_sel;
452#endif
152d3f2f
LV		 453 int gs_ldt_reload_needed;
454 int fs_reload_needed;
da8999d3 455 u64 msr_host_bndcfgs;
d77c26fc 456 } host_state;
9c8cba37 457 struct {
7ffd92c5 458 int vm86_active;
78ac8b47 459 ulong save_rflags;
f5f7b2fe
AK		 460 struct kvm_segment segs[8];
461 } rmode;
462 struct {
463 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 464 struct kvm_save_segment {
465 u16 selector;
466 unsigned long base;
467 u32 limit;
468 u32 ar;
f5f7b2fe 469 } seg[8];
2fb92db1 470 } segment_cache;
2384d2b3 471 int vpid;
04fa4d32 472 bool emulation_required;
3b86cd99
JK		 473
474 /* Support for vnmi-less CPUs */
475 int soft_vnmi_blocked;
476 ktime_t entry_time;
477 s64 vnmi_blocked_time;
a0861c02 478 u32 exit_reason;
4e47c7a6
SY		 479
480 bool rdtscp_enabled;
ec378aee 481
01e439be
YZ		 482 /* Posted interrupt descriptor */
483 struct pi_desc pi_desc;
484
ec378aee
NHE		 485 /* Support for a guest hypervisor (nested VMX) */
486 struct nested_vmx nested;
a7653ecd
RK		 487
488 /* Dynamic PLE window. */
489 int ple_window;
490 bool ple_window_dirty;
a2fa3e9f
GH		 491};
492
2fb92db1
AK		 493enum segment_cache_field {
494 SEG_FIELD_SEL = 0,
495 SEG_FIELD_BASE = 1,
496 SEG_FIELD_LIMIT = 2,
497 SEG_FIELD_AR = 3,
498
499 SEG_FIELD_NR = 4
500};
501
a2fa3e9f
GH		 502static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
503{
fb3f0f51 504 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 505}
506
22bd0358
NHE		 507#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
508#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
509#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
510 [number##_HIGH] = VMCS12_OFFSET(name)+4
511
4607c2d7 512
fe2b201b 513static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 514 /*
515 * We do NOT shadow fields that are modified when L0
516 * traps and emulates any vmx instruction (e.g. VMPTRLD,
517 * VMXON...) executed by L1.
518 * For example, VM_INSTRUCTION_ERROR is read
519 * by L1 if a vmx instruction fails (part of the error path).
520 * Note the code assumes this logic. If for some reason
521 * we start shadowing these fields then we need to
522 * force a shadow sync when L0 emulates vmx instructions
523 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
524 * by nested_vmx_failValid)
525 */
526 VM_EXIT_REASON,
527 VM_EXIT_INTR_INFO,
528 VM_EXIT_INSTRUCTION_LEN,
529 IDT_VECTORING_INFO_FIELD,
530 IDT_VECTORING_ERROR_CODE,
531 VM_EXIT_INTR_ERROR_CODE,
532 EXIT_QUALIFICATION,
533 GUEST_LINEAR_ADDRESS,
534 GUEST_PHYSICAL_ADDRESS
535};
fe2b201b 536static int max_shadow_read_only_fields =
4607c2d7
AG		 537 ARRAY_SIZE(shadow_read_only_fields);
538
fe2b201b 539static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 540 GUEST_RIP,
541 GUEST_RSP,
542 GUEST_CR0,
543 GUEST_CR3,
544 GUEST_CR4,
545 GUEST_INTERRUPTIBILITY_INFO,
546 GUEST_RFLAGS,
547 GUEST_CS_SELECTOR,
548 GUEST_CS_AR_BYTES,
549 GUEST_CS_LIMIT,
550 GUEST_CS_BASE,
551 GUEST_ES_BASE,
36be0b9d 552 GUEST_BNDCFGS,
4607c2d7
AG		 553 CR0_GUEST_HOST_MASK,
554 CR0_READ_SHADOW,
555 CR4_READ_SHADOW,
556 TSC_OFFSET,
557 EXCEPTION_BITMAP,
558 CPU_BASED_VM_EXEC_CONTROL,
559 VM_ENTRY_EXCEPTION_ERROR_CODE,
560 VM_ENTRY_INTR_INFO_FIELD,
561 VM_ENTRY_INSTRUCTION_LEN,
562 VM_ENTRY_EXCEPTION_ERROR_CODE,
563 HOST_FS_BASE,
564 HOST_GS_BASE,
565 HOST_FS_SELECTOR,
566 HOST_GS_SELECTOR
567};
fe2b201b 568static int max_shadow_read_write_fields =
4607c2d7
AG		 569 ARRAY_SIZE(shadow_read_write_fields);
570
772e0318 571static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 572 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
573 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
574 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
575 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
576 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
577 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
578 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
579 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
580 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
581 FIELD(HOST_ES_SELECTOR, host_es_selector),
582 FIELD(HOST_CS_SELECTOR, host_cs_selector),
583 FIELD(HOST_SS_SELECTOR, host_ss_selector),
584 FIELD(HOST_DS_SELECTOR, host_ds_selector),
585 FIELD(HOST_FS_SELECTOR, host_fs_selector),
586 FIELD(HOST_GS_SELECTOR, host_gs_selector),
587 FIELD(HOST_TR_SELECTOR, host_tr_selector),
588 FIELD64(IO_BITMAP_A, io_bitmap_a),
589 FIELD64(IO_BITMAP_B, io_bitmap_b),
590 FIELD64(MSR_BITMAP, msr_bitmap),
591 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
592 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
593 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
594 FIELD64(TSC_OFFSET, tsc_offset),
595 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
596 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
597 FIELD64(EPT_POINTER, ept_pointer),
598 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
599 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
600 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
601 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
602 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
603 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
604 FIELD64(GUEST_PDPTR0, guest_pdptr0),
605 FIELD64(GUEST_PDPTR1, guest_pdptr1),
606 FIELD64(GUEST_PDPTR2, guest_pdptr2),
607 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 608 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 609 FIELD64(HOST_IA32_PAT, host_ia32_pat),
610 FIELD64(HOST_IA32_EFER, host_ia32_efer),
611 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
612 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
613 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
614 FIELD(EXCEPTION_BITMAP, exception_bitmap),
615 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
616 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
617 FIELD(CR3_TARGET_COUNT, cr3_target_count),
618 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
619 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
620 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
621 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
622 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
623 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
624 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
625 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
626 FIELD(TPR_THRESHOLD, tpr_threshold),
627 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
628 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
629 FIELD(VM_EXIT_REASON, vm_exit_reason),
630 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
631 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
632 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
633 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
634 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
635 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
636 FIELD(GUEST_ES_LIMIT, guest_es_limit),
637 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
638 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
639 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
640 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
641 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
642 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
643 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
644 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
645 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
646 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
647 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
648 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
649 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
650 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
651 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
652 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
653 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
654 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
655 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
656 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
657 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 658 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 659 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
660 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
661 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
662 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
663 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
664 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
665 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
666 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
667 FIELD(EXIT_QUALIFICATION, exit_qualification),
668 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
669 FIELD(GUEST_CR0, guest_cr0),
670 FIELD(GUEST_CR3, guest_cr3),
671 FIELD(GUEST_CR4, guest_cr4),
672 FIELD(GUEST_ES_BASE, guest_es_base),
673 FIELD(GUEST_CS_BASE, guest_cs_base),
674 FIELD(GUEST_SS_BASE, guest_ss_base),
675 FIELD(GUEST_DS_BASE, guest_ds_base),
676 FIELD(GUEST_FS_BASE, guest_fs_base),
677 FIELD(GUEST_GS_BASE, guest_gs_base),
678 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
679 FIELD(GUEST_TR_BASE, guest_tr_base),
680 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
681 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
682 FIELD(GUEST_DR7, guest_dr7),
683 FIELD(GUEST_RSP, guest_rsp),
684 FIELD(GUEST_RIP, guest_rip),
685 FIELD(GUEST_RFLAGS, guest_rflags),
686 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
687 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
688 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
689 FIELD(HOST_CR0, host_cr0),
690 FIELD(HOST_CR3, host_cr3),
691 FIELD(HOST_CR4, host_cr4),
692 FIELD(HOST_FS_BASE, host_fs_base),
693 FIELD(HOST_GS_BASE, host_gs_base),
694 FIELD(HOST_TR_BASE, host_tr_base),
695 FIELD(HOST_GDTR_BASE, host_gdtr_base),
696 FIELD(HOST_IDTR_BASE, host_idtr_base),
697 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
698 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
699 FIELD(HOST_RSP, host_rsp),
700 FIELD(HOST_RIP, host_rip),
701};
702static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
703
704static inline short vmcs_field_to_offset(unsigned long field)
705{
706 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
707 return -1;
708 return vmcs_field_to_offset_table[field];
709}
710
a9d30f33
NHE		 711static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
712{
713 return to_vmx(vcpu)->nested.current_vmcs12;
714}
715
716static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
717{
718 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 719 if (is_error_page(page))
a9d30f33 720 return NULL;
32cad84f 721
a9d30f33
NHE		 722 return page;
723}
724
725static void nested_release_page(struct page *page)
726{
727 kvm_release_page_dirty(page);
728}
729
730static void nested_release_page_clean(struct page *page)
731{
732 kvm_release_page_clean(page);
733}
734
bfd0a56b 735static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 736static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 737static void kvm_cpu_vmxon(u64 addr);
738static void kvm_cpu_vmxoff(void);
93c4adc7 739static bool vmx_mpx_supported(void);
776e58ea 740static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 741static void vmx_set_segment(struct kvm_vcpu *vcpu,
742 struct kvm_segment *var, int seg);
743static void vmx_get_segment(struct kvm_vcpu *vcpu,
744 struct kvm_segment *var, int seg);
d99e4152
GN		 745static bool guest_state_valid(struct kvm_vcpu *vcpu);
746static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 747static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 748static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 749static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 750
6aa8b732
AK		 751static DEFINE_PER_CPU(struct vmcs *, vmxarea);
752static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 753/*
754 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
755 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
756 */
757static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 758static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 759
3e7c73e9
AK		 760static unsigned long *vmx_io_bitmap_a;
761static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 762static unsigned long *vmx_msr_bitmap_legacy;
763static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 764static unsigned long *vmx_msr_bitmap_legacy_x2apic;
765static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 766static unsigned long *vmx_vmread_bitmap;
767static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 768
110312c8 769static bool cpu_has_load_ia32_efer;
8bf00a52 770static bool cpu_has_load_perf_global_ctrl;
110312c8 771
2384d2b3
SY		 772static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
773static DEFINE_SPINLOCK(vmx_vpid_lock);
774
1c3d14fe 775static struct vmcs_config {
6aa8b732
AK		 776 int size;
777 int order;
778 u32 revision_id;
1c3d14fe
YS		 779 u32 pin_based_exec_ctrl;
780 u32 cpu_based_exec_ctrl;
f78e0e2e 781 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 782 u32 vmexit_ctrl;
783 u32 vmentry_ctrl;
784} vmcs_config;
6aa8b732 785
efff9e53 786static struct vmx_capability {
d56f546d
SY		 787 u32 ept;
788 u32 vpid;
789} vmx_capability;
790
6aa8b732
AK		 791#define VMX_SEGMENT_FIELD(seg) \
792 [VCPU_SREG_##seg] = { \
793 .selector = GUEST_##seg##_SELECTOR, \
794 .base = GUEST_##seg##_BASE, \
795 .limit = GUEST_##seg##_LIMIT, \
796 .ar_bytes = GUEST_##seg##_AR_BYTES, \
797 }
798
772e0318 799static const struct kvm_vmx_segment_field {
6aa8b732
AK		 800 unsigned selector;
801 unsigned base;
802 unsigned limit;
803 unsigned ar_bytes;
804} kvm_vmx_segment_fields[] = {
805 VMX_SEGMENT_FIELD(CS),
806 VMX_SEGMENT_FIELD(DS),
807 VMX_SEGMENT_FIELD(ES),
808 VMX_SEGMENT_FIELD(FS),
809 VMX_SEGMENT_FIELD(GS),
810 VMX_SEGMENT_FIELD(SS),
811 VMX_SEGMENT_FIELD(TR),
812 VMX_SEGMENT_FIELD(LDTR),
813};
814
26bb0981
AK		 815static u64 host_efer;
816
6de4f3ad
AK		 817static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
818
4d56c8a7 819/*
8c06585d 820 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 821 * away by decrementing the array size.
822 */
6aa8b732 823static const u32 vmx_msr_index[] = {
05b3e0c2 824#ifdef CONFIG_X86_64
44ea2b17 825 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 826#endif
8c06585d 827 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 828};
6aa8b732 829
31299944 830static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 831{
832 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
833 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 834 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 835}
836
31299944 837static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 841 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 842}
843
31299944 844static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 845{
846 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
847 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 848 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 849}
850
31299944 851static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 852{
853 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
854 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
855}
856
31299944 857static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 858{
859 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
860 INTR_INFO_VALID_MASK)) ==
861 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
862}
863
31299944 864static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 865{
04547156 866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 867}
868
31299944 869static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 870{
04547156 871 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 872}
873
31299944 874static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 875{
04547156 876 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 877}
878
31299944 879static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 880{
04547156
SY		 881 return vmcs_config.cpu_based_exec_ctrl &
882 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 883}
884
774ead3a 885static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 886{
04547156
SY		 887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
889}
890
8d14695f
YZ		 891static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
892{
893 return vmcs_config.cpu_based_2nd_exec_ctrl &
894 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
895}
896
83d4c286
YZ		 897static inline bool cpu_has_vmx_apic_register_virt(void)
898{
899 return vmcs_config.cpu_based_2nd_exec_ctrl &
900 SECONDARY_EXEC_APIC_REGISTER_VIRT;
901}
902
c7c9c56c
YZ		 903static inline bool cpu_has_vmx_virtual_intr_delivery(void)
904{
905 return vmcs_config.cpu_based_2nd_exec_ctrl &
906 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
907}
908
01e439be
YZ		 909static inline bool cpu_has_vmx_posted_intr(void)
910{
911 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
912}
913
914static inline bool cpu_has_vmx_apicv(void)
915{
916 return cpu_has_vmx_apic_register_virt() &&
917 cpu_has_vmx_virtual_intr_delivery() &&
918 cpu_has_vmx_posted_intr();
919}
920
04547156
SY		 921static inline bool cpu_has_vmx_flexpriority(void)
922{
923 return cpu_has_vmx_tpr_shadow() &&
924 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 925}
926
e799794e
MT		 927static inline bool cpu_has_vmx_ept_execute_only(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_eptp_uncacheable(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 935}
936
937static inline bool cpu_has_vmx_eptp_writeback(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 940}
941
942static inline bool cpu_has_vmx_ept_2m_page(void)
943{
31299944 944 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 945}
946
878403b7
SY		 947static inline bool cpu_has_vmx_ept_1g_page(void)
948{
31299944 949 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 950}
951
4bc9b982
SY		 952static inline bool cpu_has_vmx_ept_4levels(void)
953{
954 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
955}
956
83c3a331
XH		 957static inline bool cpu_has_vmx_ept_ad_bits(void)
958{
959 return vmx_capability.ept & VMX_EPT_AD_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_invept_context(void)
d56f546d 963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 965}
966
31299944 967static inline bool cpu_has_vmx_invept_global(void)
d56f546d 968{
31299944 969 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 970}
971
518c8aee
GJ		 972static inline bool cpu_has_vmx_invvpid_single(void)
973{
974 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
975}
976
b9d762fa
GJ		 977static inline bool cpu_has_vmx_invvpid_global(void)
978{
979 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
980}
981
31299944 982static inline bool cpu_has_vmx_ept(void)
d56f546d 983{
04547156
SY		 984 return vmcs_config.cpu_based_2nd_exec_ctrl &
985 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 986}
987
31299944 988static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 989{
990 return vmcs_config.cpu_based_2nd_exec_ctrl &
991 SECONDARY_EXEC_UNRESTRICTED_GUEST;
992}
993
31299944 994static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 995{
996 return vmcs_config.cpu_based_2nd_exec_ctrl &
997 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
998}
999
31299944 1000static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 1001{
6d3e435e 1002 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1003}
1004
31299944 1005static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1006{
04547156
SY		 1007 return vmcs_config.cpu_based_2nd_exec_ctrl &
1008 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1009}
1010
31299944 1011static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1012{
1013 return vmcs_config.cpu_based_2nd_exec_ctrl &
1014 SECONDARY_EXEC_RDTSCP;
1015}
1016
ad756a16
MJ		 1017static inline bool cpu_has_vmx_invpcid(void)
1018{
1019 return vmcs_config.cpu_based_2nd_exec_ctrl &
1020 SECONDARY_EXEC_ENABLE_INVPCID;
1021}
1022
31299944 1023static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1024{
1025 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1026}
1027
f5f48ee1
SY		 1028static inline bool cpu_has_vmx_wbinvd_exit(void)
1029{
1030 return vmcs_config.cpu_based_2nd_exec_ctrl &
1031 SECONDARY_EXEC_WBINVD_EXITING;
1032}
1033
abc4fc58
AG		 1034static inline bool cpu_has_vmx_shadow_vmcs(void)
1035{
1036 u64 vmx_msr;
1037 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1038 /* check if the cpu supports writing r/o exit information fields */
1039 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1040 return false;
1041
1042 return vmcs_config.cpu_based_2nd_exec_ctrl &
1043 SECONDARY_EXEC_SHADOW_VMCS;
1044}
1045
04547156
SY		 1046static inline bool report_flexpriority(void)
1047{
1048 return flexpriority_enabled;
1049}
1050
fe3ef05c
NHE		 1051static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1052{
1053 return vmcs12->cpu_based_vm_exec_control & bit;
1054}
1055
1056static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1057{
1058 return (vmcs12->cpu_based_vm_exec_control &
1059 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1060 (vmcs12->secondary_vm_exec_control & bit);
1061}
1062
f5c4368f 1063static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1064{
1065 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1066}
1067
f4124500
JK		 1068static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1069{
1070 return vmcs12->pin_based_vm_exec_control &
1071 PIN_BASED_VMX_PREEMPTION_TIMER;
1072}
1073
155a97a3
NHE		 1074static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1075{
1076 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1077}
1078
644d711a
NHE		 1079static inline bool is_exception(u32 intr_info)
1080{
1081 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1082 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1083}
1084
533558bc
JK		 1085static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1086 u32 exit_intr_info,
1087 unsigned long exit_qualification);
7c177938
NHE		 1088static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1089 struct vmcs12 *vmcs12,
1090 u32 reason, unsigned long qualification);
1091
8b9cf98c 1092static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1093{
1094 int i;
1095
a2fa3e9f 1096 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1097 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1098 return i;
1099 return -1;
1100}
1101
2384d2b3
SY		 1102static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1103{
1104 struct {
1105 u64 vpid : 16;
1106 u64 rsvd : 48;
1107 u64 gva;
1108 } operand = { vpid, 0, gva };
1109
4ecac3fd 1110 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1111 /* CF==1 or ZF==1 --> rc = -1 */
1112 "; ja 1f ; ud2 ; 1:"
1113 : : "a"(&operand), "c"(ext) : "cc", "memory");
1114}
1115
1439442c
SY		 1116static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1117{
1118 struct {
1119 u64 eptp, gpa;
1120 } operand = {eptp, gpa};
1121
4ecac3fd 1122 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1123 /* CF==1 or ZF==1 --> rc = -1 */
1124 "; ja 1f ; ud2 ; 1:\n"
1125 : : "a" (&operand), "c" (ext) : "cc", "memory");
1126}
1127
26bb0981 1128static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1129{
1130 int i;
1131
8b9cf98c 1132 i = __find_msr_index(vmx, msr);
a75beee6 1133 if (i >= 0)
a2fa3e9f 1134 return &vmx->guest_msrs[i];
8b6d44c7 1135 return NULL;
7725f0ba
AK		 1136}
1137
6aa8b732
AK		 1138static void vmcs_clear(struct vmcs *vmcs)
1139{
1140 u64 phys_addr = __pa(vmcs);
1141 u8 error;
1142
4ecac3fd 1143 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1144 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1145 : "cc", "memory");
1146 if (error)
1147 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1148 vmcs, phys_addr);
1149}
1150
d462b819
NHE		 1151static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1152{
1153 vmcs_clear(loaded_vmcs->vmcs);
1154 loaded_vmcs->cpu = -1;
1155 loaded_vmcs->launched = 0;
1156}
1157
7725b894
DX		 1158static void vmcs_load(struct vmcs *vmcs)
1159{
1160 u64 phys_addr = __pa(vmcs);
1161 u8 error;
1162
1163 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1164 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1165 : "cc", "memory");
1166 if (error)
2844d849 1167 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1168 vmcs, phys_addr);
1169}
1170
8f536b76
ZY		 1171#ifdef CONFIG_KEXEC
1172/*
1173 * This bitmap is used to indicate whether the vmclear
1174 * operation is enabled on all cpus. All disabled by
1175 * default.
1176 */
1177static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1178
1179static inline void crash_enable_local_vmclear(int cpu)
1180{
1181 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static inline void crash_disable_local_vmclear(int cpu)
1185{
1186 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187}
1188
1189static inline int crash_local_vmclear_enabled(int cpu)
1190{
1191 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1192}
1193
1194static void crash_vmclear_local_loaded_vmcss(void)
1195{
1196 int cpu = raw_smp_processor_id();
1197 struct loaded_vmcs *v;
1198
1199 if (!crash_local_vmclear_enabled(cpu))
1200 return;
1201
1202 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1203 loaded_vmcss_on_cpu_link)
1204 vmcs_clear(v->vmcs);
1205}
1206#else
1207static inline void crash_enable_local_vmclear(int cpu) { }
1208static inline void crash_disable_local_vmclear(int cpu) { }
1209#endif /* CONFIG_KEXEC */
1210
d462b819 1211static void __loaded_vmcs_clear(void *arg)
6aa8b732 1212{
d462b819 1213 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1214 int cpu = raw_smp_processor_id();
6aa8b732 1215
d462b819
NHE		 1216 if (loaded_vmcs->cpu != cpu)
1217 return; /* vcpu migration can race with cpu offline */
1218 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1219 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1220 crash_disable_local_vmclear(cpu);
d462b819 1221 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1222
1223 /*
1224 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1225 * is before setting loaded_vmcs->vcpu to -1 which is done in
1226 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1227 * then adds the vmcs into percpu list before it is deleted.
1228 */
1229 smp_wmb();
1230
d462b819 1231 loaded_vmcs_init(loaded_vmcs);
8f536b76 1232 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1233}
1234
d462b819 1235static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1236{
e6c7d321
XG		 1237 int cpu = loaded_vmcs->cpu;
1238
1239 if (cpu != -1)
1240 smp_call_function_single(cpu,
1241 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1242}
1243
1760dd49 1244static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1245{
1246 if (vmx->vpid == 0)
1247 return;
1248
518c8aee
GJ		 1249 if (cpu_has_vmx_invvpid_single())
1250 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1251}
1252
b9d762fa
GJ		 1253static inline void vpid_sync_vcpu_global(void)
1254{
1255 if (cpu_has_vmx_invvpid_global())
1256 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1257}
1258
1259static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1260{
1261 if (cpu_has_vmx_invvpid_single())
1760dd49 1262 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1263 else
1264 vpid_sync_vcpu_global();
1265}
1266
1439442c
SY		 1267static inline void ept_sync_global(void)
1268{
1269 if (cpu_has_vmx_invept_global())
1270 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1271}
1272
1273static inline void ept_sync_context(u64 eptp)
1274{
089d034e 1275 if (enable_ept) {
1439442c
SY		 1276 if (cpu_has_vmx_invept_context())
1277 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1278 else
1279 ept_sync_global();
1280 }
1281}
1282
96304217 1283static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1284{
5e520e62 1285 unsigned long value;
6aa8b732 1286
5e520e62
AK		 1287 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1288 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1289 return value;
1290}
1291
96304217 1292static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1293{
1294 return vmcs_readl(field);
1295}
1296
96304217 1297static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1298{
1299 return vmcs_readl(field);
1300}
1301
96304217 1302static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1303{
05b3e0c2 1304#ifdef CONFIG_X86_64
6aa8b732
AK		 1305 return vmcs_readl(field);
1306#else
1307 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1308#endif
1309}
1310
e52de1b8
AK		 1311static noinline void vmwrite_error(unsigned long field, unsigned long value)
1312{
1313 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1314 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1315 dump_stack();
1316}
1317
6aa8b732
AK		 1318static void vmcs_writel(unsigned long field, unsigned long value)
1319{
1320 u8 error;
1321
4ecac3fd 1322 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1323 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1324 if (unlikely(error))
1325 vmwrite_error(field, value);
6aa8b732
AK		 1326}
1327
1328static void vmcs_write16(unsigned long field, u16 value)
1329{
1330 vmcs_writel(field, value);
1331}
1332
1333static void vmcs_write32(unsigned long field, u32 value)
1334{
1335 vmcs_writel(field, value);
1336}
1337
1338static void vmcs_write64(unsigned long field, u64 value)
1339{
6aa8b732 1340 vmcs_writel(field, value);
7682f2d0 1341#ifndef CONFIG_X86_64
6aa8b732
AK		 1342 asm volatile ("");
1343 vmcs_writel(field+1, value >> 32);
1344#endif
1345}
1346
2ab455cc
AL		 1347static void vmcs_clear_bits(unsigned long field, u32 mask)
1348{
1349 vmcs_writel(field, vmcs_readl(field) & ~mask);
1350}
1351
1352static void vmcs_set_bits(unsigned long field, u32 mask)
1353{
1354 vmcs_writel(field, vmcs_readl(field) | mask);
1355}
1356
2961e876
GN		 1357static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1358{
1359 vmcs_write32(VM_ENTRY_CONTROLS, val);
1360 vmx->vm_entry_controls_shadow = val;
1361}
1362
1363static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1364{
1365 if (vmx->vm_entry_controls_shadow != val)
1366 vm_entry_controls_init(vmx, val);
1367}
1368
1369static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1370{
1371 return vmx->vm_entry_controls_shadow;
1372}
1373
1374
1375static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1378}
1379
1380static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1383}
1384
1385static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1386{
1387 vmcs_write32(VM_EXIT_CONTROLS, val);
1388 vmx->vm_exit_controls_shadow = val;
1389}
1390
1391static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1392{
1393 if (vmx->vm_exit_controls_shadow != val)
1394 vm_exit_controls_init(vmx, val);
1395}
1396
1397static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1398{
1399 return vmx->vm_exit_controls_shadow;
1400}
1401
1402
1403static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1406}
1407
1408static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1409{
1410 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1411}
1412
2fb92db1
AK		 1413static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1414{
1415 vmx->segment_cache.bitmask = 0;
1416}
1417
1418static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1419 unsigned field)
1420{
1421 bool ret;
1422 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1423
1424 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1425 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1426 vmx->segment_cache.bitmask = 0;
1427 }
1428 ret = vmx->segment_cache.bitmask & mask;
1429 vmx->segment_cache.bitmask |= mask;
1430 return ret;
1431}
1432
1433static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1434{
1435 u16 *p = &vmx->segment_cache.seg[seg].selector;
1436
1437 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1438 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1439 return *p;
1440}
1441
1442static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1443{
1444 ulong *p = &vmx->segment_cache.seg[seg].base;
1445
1446 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1447 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1448 return *p;
1449}
1450
1451static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1452{
1453 u32 *p = &vmx->segment_cache.seg[seg].limit;
1454
1455 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1456 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1457 return *p;
1458}
1459
1460static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1461{
1462 u32 *p = &vmx->segment_cache.seg[seg].ar;
1463
1464 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1465 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1466 return *p;
1467}
1468
abd3f2d6
AK		 1469static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1470{
1471 u32 eb;
1472
fd7373cc
JK		 1473 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1474 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1475 if ((vcpu->guest_debug &
1476 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1477 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1478 eb |= 1u << BP_VECTOR;
7ffd92c5 1479 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1480 eb = ~0;
089d034e 1481 if (enable_ept)
1439442c 1482 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1483 if (vcpu->fpu_active)
1484 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1485
1486 /* When we are running a nested L2 guest and L1 specified for it a
1487 * certain exception bitmap, we must trap the same exceptions and pass
1488 * them to L1. When running L2, we will only handle the exceptions
1489 * specified above if L1 did not want them.
1490 */
1491 if (is_guest_mode(vcpu))
1492 eb |= get_vmcs12(vcpu)->exception_bitmap;
1493
abd3f2d6
AK		 1494 vmcs_write32(EXCEPTION_BITMAP, eb);
1495}
1496
2961e876
GN		 1497static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1498 unsigned long entry, unsigned long exit)
8bf00a52 1499{
2961e876
GN		 1500 vm_entry_controls_clearbit(vmx, entry);
1501 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1502}
1503
61d2ef2c
AK		 1504static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1505{
1506 unsigned i;
1507 struct msr_autoload *m = &vmx->msr_autoload;
1508
8bf00a52
GN		 1509 switch (msr) {
1510 case MSR_EFER:
1511 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1512 clear_atomic_switch_msr_special(vmx,
1513 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1514 VM_EXIT_LOAD_IA32_EFER);
1515 return;
1516 }
1517 break;
1518 case MSR_CORE_PERF_GLOBAL_CTRL:
1519 if (cpu_has_load_perf_global_ctrl) {
2961e876 1520 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1521 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1522 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1523 return;
1524 }
1525 break;
110312c8
AK		 1526 }
1527
61d2ef2c
AK		 1528 for (i = 0; i < m->nr; ++i)
1529 if (m->guest[i].index == msr)
1530 break;
1531
1532 if (i == m->nr)
1533 return;
1534 --m->nr;
1535 m->guest[i] = m->guest[m->nr];
1536 m->host[i] = m->host[m->nr];
1537 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1538 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1539}
1540
2961e876
GN		 1541static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1542 unsigned long entry, unsigned long exit,
1543 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1544 u64 guest_val, u64 host_val)
8bf00a52
GN		 1545{
1546 vmcs_write64(guest_val_vmcs, guest_val);
1547 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1548 vm_entry_controls_setbit(vmx, entry);
1549 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1550}
1551
61d2ef2c
AK		 1552static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1553 u64 guest_val, u64 host_val)
1554{
1555 unsigned i;
1556 struct msr_autoload *m = &vmx->msr_autoload;
1557
8bf00a52
GN		 1558 switch (msr) {
1559 case MSR_EFER:
1560 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1561 add_atomic_switch_msr_special(vmx,
1562 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1563 VM_EXIT_LOAD_IA32_EFER,
1564 GUEST_IA32_EFER,
1565 HOST_IA32_EFER,
1566 guest_val, host_val);
1567 return;
1568 }
1569 break;
1570 case MSR_CORE_PERF_GLOBAL_CTRL:
1571 if (cpu_has_load_perf_global_ctrl) {
2961e876 1572 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1573 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1574 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1575 GUEST_IA32_PERF_GLOBAL_CTRL,
1576 HOST_IA32_PERF_GLOBAL_CTRL,
1577 guest_val, host_val);
1578 return;
1579 }
1580 break;
110312c8
AK		 1581 }
1582
61d2ef2c
AK		 1583 for (i = 0; i < m->nr; ++i)
1584 if (m->guest[i].index == msr)
1585 break;
1586
e7fc6f93 1587 if (i == NR_AUTOLOAD_MSRS) {
60266204 1588 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1589 "Can't add msr %x\n", msr);
1590 return;
1591 } else if (i == m->nr) {
61d2ef2c
AK		 1592 ++m->nr;
1593 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1594 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1595 }
1596
1597 m->guest[i].index = msr;
1598 m->guest[i].value = guest_val;
1599 m->host[i].index = msr;
1600 m->host[i].value = host_val;
1601}
1602
33ed6329
AK		 1603static void reload_tss(void)
1604{
33ed6329
AK		 1605 /*
1606 * VT restores TR but not its size. Useless.
1607 */
d359192f 1608 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1609 struct desc_struct *descs;
33ed6329 1610
d359192f 1611 descs = (void *)gdt->address;
33ed6329
AK		 1612 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1613 load_TR_desc();
33ed6329
AK		 1614}
1615
92c0d900 1616static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1617{
3a34a881 1618 u64 guest_efer;
51c6cf66
AK		 1619 u64 ignore_bits;
1620
f6801dff 1621 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1622
51c6cf66 1623 /*
0fa06071 1624 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1625 * outside long mode
1626 */
1627 ignore_bits = EFER_NX | EFER_SCE;
1628#ifdef CONFIG_X86_64
1629 ignore_bits |= EFER_LMA | EFER_LME;
1630 /* SCE is meaningful only in long mode on Intel */
1631 if (guest_efer & EFER_LMA)
1632 ignore_bits &= ~(u64)EFER_SCE;
1633#endif
51c6cf66
AK		 1634 guest_efer &= ~ignore_bits;
1635 guest_efer |= host_efer & ignore_bits;
26bb0981 1636 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1637 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1638
1639 clear_atomic_switch_msr(vmx, MSR_EFER);
1640 /* On ept, can't emulate nx, and must switch nx atomically */
1641 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1642 guest_efer = vmx->vcpu.arch.efer;
1643 if (!(guest_efer & EFER_LMA))
1644 guest_efer &= ~EFER_LME;
1645 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1646 return false;
1647 }
1648
26bb0981 1649 return true;
51c6cf66
AK		 1650}
1651
2d49ec72
GN		 1652static unsigned long segment_base(u16 selector)
1653{
d359192f 1654 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1655 struct desc_struct *d;
1656 unsigned long table_base;
1657 unsigned long v;
1658
1659 if (!(selector & ~3))
1660 return 0;
1661
d359192f 1662 table_base = gdt->address;
2d49ec72
GN		 1663
1664 if (selector & 4) { /* from ldt */
1665 u16 ldt_selector = kvm_read_ldt();
1666
1667 if (!(ldt_selector & ~3))
1668 return 0;
1669
1670 table_base = segment_base(ldt_selector);
1671 }
1672 d = (struct desc_struct *)(table_base + (selector & ~7));
1673 v = get_desc_base(d);
1674#ifdef CONFIG_X86_64
1675 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1676 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1677#endif
1678 return v;
1679}
1680
1681static inline unsigned long kvm_read_tr_base(void)
1682{
1683 u16 tr;
1684 asm("str %0" : "=g"(tr));
1685 return segment_base(tr);
1686}
1687
04d2cc77 1688static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1689{
04d2cc77 1690 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1691 int i;
04d2cc77 1692
a2fa3e9f 1693 if (vmx->host_state.loaded)
33ed6329
AK		 1694 return;
1695
a2fa3e9f 1696 vmx->host_state.loaded = 1;
33ed6329
AK		 1697 /*
1698 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1699 * allow segment selectors with cpl > 0 or ti == 1.
1700 */
d6e88aec 1701 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1702 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1703 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1704 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1705 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1706 vmx->host_state.fs_reload_needed = 0;
1707 } else {
33ed6329 1708 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1709 vmx->host_state.fs_reload_needed = 1;
33ed6329 1710 }
9581d442 1711 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1712 if (!(vmx->host_state.gs_sel & 7))
1713 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1714 else {
1715 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1716 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1717 }
1718
b2da15ac
AK		 1719#ifdef CONFIG_X86_64
1720 savesegment(ds, vmx->host_state.ds_sel);
1721 savesegment(es, vmx->host_state.es_sel);
1722#endif
1723
33ed6329
AK		 1724#ifdef CONFIG_X86_64
1725 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1726 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1727#else
a2fa3e9f
GH		 1728 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1729 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1730#endif
707c0874
AK		 1731
1732#ifdef CONFIG_X86_64
c8770e7b
AK		 1733 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1734 if (is_long_mode(&vmx->vcpu))
44ea2b17 1735 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1736#endif
da8999d3
LJ		 1737 if (boot_cpu_has(X86_FEATURE_MPX))
1738 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1739 for (i = 0; i < vmx->save_nmsrs; ++i)
1740 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1741 vmx->guest_msrs[i].data,
1742 vmx->guest_msrs[i].mask);
33ed6329
AK		 1743}
1744
a9b21b62 1745static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1746{
a2fa3e9f 1747 if (!vmx->host_state.loaded)
33ed6329
AK		 1748 return;
1749
e1beb1d3 1750 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1751 vmx->host_state.loaded = 0;
c8770e7b
AK		 1752#ifdef CONFIG_X86_64
1753 if (is_long_mode(&vmx->vcpu))
1754 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1755#endif
152d3f2f 1756 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1757 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1758#ifdef CONFIG_X86_64
9581d442 1759 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1760#else
1761 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1762#endif
33ed6329 1763 }
0a77fe4c
AK		 1764 if (vmx->host_state.fs_reload_needed)
1765 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1766#ifdef CONFIG_X86_64
1767 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1768 loadsegment(ds, vmx->host_state.ds_sel);
1769 loadsegment(es, vmx->host_state.es_sel);
1770 }
b2da15ac 1771#endif
152d3f2f 1772 reload_tss();
44ea2b17 1773#ifdef CONFIG_X86_64
c8770e7b 1774 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1775#endif
da8999d3
LJ		 1776 if (vmx->host_state.msr_host_bndcfgs)
1777 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1778 /*
1779 * If the FPU is not active (through the host task or
1780 * the guest vcpu), then restore the cr0.TS bit.
1781 */
1782 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1783 stts();
3444d7da 1784 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1785}
1786
a9b21b62
AK		 1787static void vmx_load_host_state(struct vcpu_vmx *vmx)
1788{
1789 preempt_disable();
1790 __vmx_load_host_state(vmx);
1791 preempt_enable();
1792}
1793
6aa8b732
AK		 1794/*
1795 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1796 * vcpu mutex is already taken.
1797 */
15ad7146 1798static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1799{
a2fa3e9f 1800 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1801 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1802
4610c9cc
DX		 1803 if (!vmm_exclusive)
1804 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1805 else if (vmx->loaded_vmcs->cpu != cpu)
1806 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1807
d462b819
NHE		 1808 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1809 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1810 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1811 }
1812
d462b819 1813 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1814 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1815 unsigned long sysenter_esp;
1816
a8eeb04a 1817 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1818 local_irq_disable();
8f536b76 1819 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1820
1821 /*
1822 * Read loaded_vmcs->cpu should be before fetching
1823 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1824 * See the comments in __loaded_vmcs_clear().
1825 */
1826 smp_rmb();
1827
d462b819
NHE		 1828 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1829 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1830 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1831 local_irq_enable();
1832
6aa8b732
AK		 1833 /*
1834 * Linux uses per-cpu TSS and GDT, so set these when switching
1835 * processors.
1836 */
d6e88aec 1837 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1838 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1839
1840 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1841 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1842 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1843 }
6aa8b732
AK		 1844}
1845
1846static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1847{
a9b21b62 1848 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1849 if (!vmm_exclusive) {
d462b819
NHE		 1850 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1851 vcpu->cpu = -1;
4610c9cc
DX		 1852 kvm_cpu_vmxoff();
1853 }
6aa8b732
AK		 1854}
1855
5fd86fcf
AK		 1856static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1857{
81231c69
AK		 1858 ulong cr0;
1859
5fd86fcf
AK		 1860 if (vcpu->fpu_active)
1861 return;
1862 vcpu->fpu_active = 1;
81231c69
AK		 1863 cr0 = vmcs_readl(GUEST_CR0);
1864 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1865 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1866 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1867 update_exception_bitmap(vcpu);
edcafe3c 1868 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1869 if (is_guest_mode(vcpu))
1870 vcpu->arch.cr0_guest_owned_bits &=
1871 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1872 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1873}
1874
edcafe3c
AK		 1875static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1876
fe3ef05c
NHE		 1877/*
1878 * Return the cr0 value that a nested guest would read. This is a combination
1879 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1880 * its hypervisor (cr0_read_shadow).
1881 */
1882static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1883{
1884 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1885 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1886}
1887static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1888{
1889 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1890 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1891}
1892
5fd86fcf
AK		 1893static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1894{
36cf24e0
NHE		 1895 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1896 * set this *before* calling this function.
1897 */
edcafe3c 1898 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1899 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1900 update_exception_bitmap(vcpu);
edcafe3c
AK		 1901 vcpu->arch.cr0_guest_owned_bits = 0;
1902 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1903 if (is_guest_mode(vcpu)) {
1904 /*
1905 * L1's specified read shadow might not contain the TS bit,
1906 * so now that we turned on shadowing of this bit, we need to
1907 * set this bit of the shadow. Like in nested_vmx_run we need
1908 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1909 * up-to-date here because we just decached cr0.TS (and we'll
1910 * only update vmcs12->guest_cr0 on nested exit).
1911 */
1912 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1913 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1914 (vcpu->arch.cr0 & X86_CR0_TS);
1915 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1916 } else
1917 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1918}
1919
6aa8b732
AK		 1920static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1921{
78ac8b47 1922 unsigned long rflags, save_rflags;
345dcaa8 1923
6de12732
AK		 1924 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1925 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1926 rflags = vmcs_readl(GUEST_RFLAGS);
1927 if (to_vmx(vcpu)->rmode.vm86_active) {
1928 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1929 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1930 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1931 }
1932 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1933 }
6de12732 1934 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1935}
1936
1937static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1938{
6de12732
AK		 1939 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1940 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1941 if (to_vmx(vcpu)->rmode.vm86_active) {
1942 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1943 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1944 }
6aa8b732
AK		 1945 vmcs_writel(GUEST_RFLAGS, rflags);
1946}
1947
37ccdcbe 1948static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1949{
1950 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1951 int ret = 0;
1952
1953 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1954 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1955 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1956 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1957
37ccdcbe 1958 return ret;
2809f5d2
GC		 1959}
1960
1961static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1962{
1963 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1964 u32 interruptibility = interruptibility_old;
1965
1966 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1967
48005f64 1968 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1969 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1970 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1971 interruptibility |= GUEST_INTR_STATE_STI;
1972
1973 if ((interruptibility != interruptibility_old))
1974 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1975}
1976
6aa8b732
AK		 1977static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1978{
1979 unsigned long rip;
6aa8b732 1980
5fdbf976 1981 rip = kvm_rip_read(vcpu);
6aa8b732 1982 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1983 kvm_rip_write(vcpu, rip);
6aa8b732 1984
2809f5d2
GC		 1985 /* skipping an emulated instruction also counts */
1986 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1987}
1988
0b6ac343
NHE		 1989/*
1990 * KVM wants to inject page-faults which it got to the guest. This function
1991 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1992 */
e011c663 1993static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1994{
1995 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1996
e011c663 1997 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1998 return 0;
1999
533558bc
JK		 2000 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2001 vmcs_read32(VM_EXIT_INTR_INFO),
2002 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2003 return 1;
2004}
2005
298101da 2006static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2007 bool has_error_code, u32 error_code,
2008 bool reinject)
298101da 2009{
77ab6db0 2010 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2011 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2012
e011c663
GN		 2013 if (!reinject && is_guest_mode(vcpu) &&
2014 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2015 return;
2016
8ab2d2e2 2017 if (has_error_code) {
77ab6db0 2018 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2019 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2020 }
77ab6db0 2021
7ffd92c5 2022 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2023 int inc_eip = 0;
2024 if (kvm_exception_is_soft(nr))
2025 inc_eip = vcpu->arch.event_exit_inst_len;
2026 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2027 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2028 return;
2029 }
2030
66fd3f7f
GN		 2031 if (kvm_exception_is_soft(nr)) {
2032 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2033 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2034 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2035 } else
2036 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2037
2038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2039}
2040
4e47c7a6
SY		 2041static bool vmx_rdtscp_supported(void)
2042{
2043 return cpu_has_vmx_rdtscp();
2044}
2045
ad756a16
MJ		 2046static bool vmx_invpcid_supported(void)
2047{
2048 return cpu_has_vmx_invpcid() && enable_ept;
2049}
2050
a75beee6
ED		 2051/*
2052 * Swap MSR entry in host/guest MSR entry array.
2053 */
8b9cf98c 2054static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2055{
26bb0981 2056 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2057
2058 tmp = vmx->guest_msrs[to];
2059 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2060 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2061}
2062
8d14695f
YZ		 2063static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2064{
2065 unsigned long *msr_bitmap;
2066
2067 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2070 else
2071 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2072 } else {
2073 if (is_long_mode(vcpu))
2074 msr_bitmap = vmx_msr_bitmap_longmode;
2075 else
2076 msr_bitmap = vmx_msr_bitmap_legacy;
2077 }
2078
2079 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2080}
2081
e38aea3e
AK		 2082/*
2083 * Set up the vmcs to automatically save and restore system
2084 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2085 * mode, as fiddling with msrs is very expensive.
2086 */
8b9cf98c 2087static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2088{
26bb0981 2089 int save_nmsrs, index;
e38aea3e 2090
a75beee6
ED		 2091 save_nmsrs = 0;
2092#ifdef CONFIG_X86_64
8b9cf98c 2093 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2094 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2095 if (index >= 0)
8b9cf98c
RR		 2096 move_msr_up(vmx, index, save_nmsrs++);
2097 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2098 if (index >= 0)
8b9cf98c
RR		 2099 move_msr_up(vmx, index, save_nmsrs++);
2100 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2101 if (index >= 0)
8b9cf98c 2102 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2103 index = __find_msr_index(vmx, MSR_TSC_AUX);
2104 if (index >= 0 && vmx->rdtscp_enabled)
2105 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2106 /*
8c06585d 2107 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2108 * if efer.sce is enabled.
2109 */
8c06585d 2110 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2111 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2112 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2113 }
2114#endif
92c0d900
AK		 2115 index = __find_msr_index(vmx, MSR_EFER);
2116 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2117 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2118
26bb0981 2119 vmx->save_nmsrs = save_nmsrs;
5897297b 2120
8d14695f
YZ		 2121 if (cpu_has_vmx_msr_bitmap())
2122 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2123}
2124
6aa8b732
AK		 2125/*
2126 * reads and returns guest's timestamp counter "register"
2127 * guest_tsc = host_tsc + tsc_offset -- 21.3
2128 */
2129static u64 guest_read_tsc(void)
2130{
2131 u64 host_tsc, tsc_offset;
2132
2133 rdtscll(host_tsc);
2134 tsc_offset = vmcs_read64(TSC_OFFSET);
2135 return host_tsc + tsc_offset;
2136}
2137
d5c1785d
NHE		 2138/*
2139 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2140 * counter, even if a nested guest (L2) is currently running.
2141 */
886b470c 2142u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2143{
886b470c 2144 u64 tsc_offset;
d5c1785d 2145
d5c1785d
NHE		 2146 tsc_offset = is_guest_mode(vcpu) ?
2147 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2148 vmcs_read64(TSC_OFFSET);
2149 return host_tsc + tsc_offset;
2150}
2151
4051b188 2152/*
cc578287
ZA		 2153 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2154 * software catchup for faster rates on slower CPUs.
4051b188 2155 */
cc578287 2156static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2157{
cc578287
ZA		 2158 if (!scale)
2159 return;
2160
2161 if (user_tsc_khz > tsc_khz) {
2162 vcpu->arch.tsc_catchup = 1;
2163 vcpu->arch.tsc_always_catchup = 1;
2164 } else
2165 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2166}
2167
ba904635
WA		 2168static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2169{
2170 return vmcs_read64(TSC_OFFSET);
2171}
2172
6aa8b732 2173/*
99e3e30a 2174 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2175 */
99e3e30a 2176static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2177{
27fc51b2 2178 if (is_guest_mode(vcpu)) {
7991825b 2179 /*
27fc51b2
NHE		 2180 * We're here if L1 chose not to trap WRMSR to TSC. According
2181 * to the spec, this should set L1's TSC; The offset that L1
2182 * set for L2 remains unchanged, and still needs to be added
2183 * to the newly set TSC to get L2's TSC.
7991825b 2184 */
27fc51b2
NHE		 2185 struct vmcs12 *vmcs12;
2186 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2187 /* recalculate vmcs02.TSC_OFFSET: */
2188 vmcs12 = get_vmcs12(vcpu);
2189 vmcs_write64(TSC_OFFSET, offset +
2190 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2191 vmcs12->tsc_offset : 0));
2192 } else {
489223ed
YY		 2193 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2194 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2195 vmcs_write64(TSC_OFFSET, offset);
2196 }
6aa8b732
AK		 2197}
2198
f1e2b260 2199static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2200{
2201 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2202
e48672fa 2203 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2204 if (is_guest_mode(vcpu)) {
2205 /* Even when running L2, the adjustment needs to apply to L1 */
2206 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2207 } else
2208 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2209 offset + adjustment);
e48672fa
ZA		 2210}
2211
857e4099
JR		 2212static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2213{
2214 return target_tsc - native_read_tsc();
2215}
2216
801d3424
NHE		 2217static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2218{
2219 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2220 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2221}
2222
2223/*
2224 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2225 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2226 * all guests if the "nested" module option is off, and can also be disabled
2227 * for a single guest by disabling its VMX cpuid bit.
2228 */
2229static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2230{
2231 return nested && guest_cpuid_has_vmx(vcpu);
2232}
2233
b87a51ae
NHE		 2234/*
2235 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2236 * returned for the various VMX controls MSRs when nested VMX is enabled.
2237 * The same values should also be used to verify that vmcs12 control fields are
2238 * valid during nested entry from L1 to L2.
2239 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2240 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2241 * bit in the high half is on if the corresponding bit in the control field
2242 * may be on. See also vmx_control_verify().
2243 * TODO: allow these variables to be modified (downgraded) by module options
2244 * or other means.
2245 */
2246static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2247static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2248static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2249static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2250static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2251static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2252static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2253static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2254static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2255static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2256static __init void nested_vmx_setup_ctls_msrs(void)
2257{
2258 /*
2259 * Note that as a general rule, the high half of the MSRs (bits in
2260 * the control fields which may be 1) should be initialized by the
2261 * intersection of the underlying hardware's MSR (i.e., features which
2262 * can be supported) and the list of features we want to expose -
2263 * because they are known to be properly supported in our code.
2264 * Also, usually, the low half of the MSRs (bits which must be 1) can
2265 * be set to 0, meaning that L1 may turn off any of these bits. The
2266 * reason is that if one of these bits is necessary, it will appear
2267 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2268 * fields of vmcs01 and vmcs02, will turn these bits off - and
2269 * nested_vmx_exit_handled() will not pass related exits to L1.
2270 * These rules have exceptions below.
2271 */
2272
2273 /* pin-based controls */
eabeaacc
JK		 2274 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2275 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2276 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2277 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2278 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2279 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2280 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2281
3dbcd8da 2282 /* exit controls */
c0dfee58
ACL		 2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2284 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2285 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2286
c0dfee58 2287 nested_vmx_exit_ctls_high &=
b87a51ae 2288#ifdef CONFIG_X86_64
c0dfee58 2289 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2290#endif
f4124500
JK		 2291 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2292 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2293 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2295
36be0b9d
PB		 2296 if (vmx_mpx_supported())
2297 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2298
2996fca0
JK		 2299 /* We support free control of debug control saving. */
2300 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2301 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2302
b87a51ae
NHE		 2303 /* entry controls */
2304 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2305 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2306 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2307 nested_vmx_entry_ctls_high &=
57435349
JK		 2308#ifdef CONFIG_X86_64
2309 VM_ENTRY_IA32E_MODE |
2310#endif
2311 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2312 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2313 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2314 if (vmx_mpx_supported())
2315 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2316
2996fca0
JK		 2317 /* We support free control of debug control loading. */
2318 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2319 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2320
b87a51ae
NHE		 2321 /* cpu-based controls */
2322 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2323 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2324 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2325 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2326 CPU_BASED_VIRTUAL_INTR_PENDING |
2327 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2328 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2329 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2330 CPU_BASED_CR3_STORE_EXITING |
2331#ifdef CONFIG_X86_64
2332 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2333#endif
2334 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2335 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2336 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2337 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2339 /*
2340 * We can allow some features even when not supported by the
2341 * hardware. For example, L1 can specify an MSR bitmap - and we
2342 * can use it to avoid exits to L1 - even when L0 runs L2
2343 * without MSR bitmaps.
2344 */
560b7ee1
JK		 2345 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2346 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2347
3dcdf3ec
JK		 2348 /* We support free control of CR3 access interception. */
2349 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2350 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2351
b87a51ae
NHE		 2352 /* secondary cpu-based controls */
2353 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2354 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2355 nested_vmx_secondary_ctls_low = 0;
2356 nested_vmx_secondary_ctls_high &=
d6851fbe 2357 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2358 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2359 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2360
afa61f75
NHE		 2361 if (enable_ept) {
2362 /* nested EPT: emulate EPT also to L1 */
2363 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2364 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2365 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2366 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2367 nested_vmx_ept_caps &= vmx_capability.ept;
2368 /*
4b855078
BD		 2369 * For nested guests, we don't do anything specific
2370 * for single context invalidation. Hence, only advertise
2371 * support for global context invalidation.
afa61f75 2372 */
4b855078 2373 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2374 } else
2375 nested_vmx_ept_caps = 0;
2376
c18911a2
JK		 2377 /* miscellaneous data */
2378 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2379 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2380 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2381 VMX_MISC_ACTIVITY_HLT;
c18911a2 2382 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2383}
2384
2385static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2386{
2387 /*
2388 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2389 */
2390 return ((control & high) | low) == control;
2391}
2392
2393static inline u64 vmx_control_msr(u32 low, u32 high)
2394{
2395 return low | ((u64)high << 32);
2396}
2397
cae50139 2398/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2399static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2400{
b87a51ae 2401 switch (msr_index) {
b87a51ae
NHE		 2402 case MSR_IA32_VMX_BASIC:
2403 /*
2404 * This MSR reports some information about VMX support. We
2405 * should return information about the VMX we emulate for the
2406 * guest, and the VMCS structure we give it - not about the
2407 * VMX support of the underlying hardware.
2408 */
3dbcd8da 2409 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2410 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2411 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2412 break;
2413 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2414 case MSR_IA32_VMX_PINBASED_CTLS:
2415 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2416 nested_vmx_pinbased_ctls_high);
2417 break;
2418 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2419 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2420 nested_vmx_procbased_ctls_high);
2421 break;
b87a51ae
NHE		 2422 case MSR_IA32_VMX_PROCBASED_CTLS:
2423 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2424 nested_vmx_procbased_ctls_high);
2425 break;
2426 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2427 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2428 nested_vmx_exit_ctls_high);
2429 break;
b87a51ae
NHE		 2430 case MSR_IA32_VMX_EXIT_CTLS:
2431 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2432 nested_vmx_exit_ctls_high);
2433 break;
2434 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2435 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2436 nested_vmx_entry_ctls_high);
2437 break;
b87a51ae
NHE		 2438 case MSR_IA32_VMX_ENTRY_CTLS:
2439 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2440 nested_vmx_entry_ctls_high);
2441 break;
2442 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2443 *pdata = vmx_control_msr(nested_vmx_misc_low,
2444 nested_vmx_misc_high);
b87a51ae
NHE		 2445 break;
2446 /*
2447 * These MSRs specify bits which the guest must keep fixed (on or off)
2448 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2449 * We picked the standard core2 setting.
2450 */
2451#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2452#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2453 case MSR_IA32_VMX_CR0_FIXED0:
2454 *pdata = VMXON_CR0_ALWAYSON;
2455 break;
2456 case MSR_IA32_VMX_CR0_FIXED1:
2457 *pdata = -1ULL;
2458 break;
2459 case MSR_IA32_VMX_CR4_FIXED0:
2460 *pdata = VMXON_CR4_ALWAYSON;
2461 break;
2462 case MSR_IA32_VMX_CR4_FIXED1:
2463 *pdata = -1ULL;
2464 break;
2465 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2466 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2467 break;
2468 case MSR_IA32_VMX_PROCBASED_CTLS2:
2469 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2470 nested_vmx_secondary_ctls_high);
2471 break;
2472 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2473 /* Currently, no nested vpid support */
2474 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2475 break;
2476 default:
b87a51ae 2477 return 1;
b3897a49
NHE		 2478 }
2479
b87a51ae
NHE		 2480 return 0;
2481}
2482
6aa8b732
AK		 2483/*
2484 * Reads an msr value (of 'msr_index') into 'pdata'.
2485 * Returns 0 on success, non-0 otherwise.
2486 * Assumes vcpu_load() was already called.
2487 */
2488static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2489{
2490 u64 data;
26bb0981 2491 struct shared_msr_entry *msr;
6aa8b732
AK		 2492
2493 if (!pdata) {
2494 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2495 return -EINVAL;
2496 }
2497
2498 switch (msr_index) {
05b3e0c2 2499#ifdef CONFIG_X86_64
6aa8b732
AK		 2500 case MSR_FS_BASE:
2501 data = vmcs_readl(GUEST_FS_BASE);
2502 break;
2503 case MSR_GS_BASE:
2504 data = vmcs_readl(GUEST_GS_BASE);
2505 break;
44ea2b17
AK		 2506 case MSR_KERNEL_GS_BASE:
2507 vmx_load_host_state(to_vmx(vcpu));
2508 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2509 break;
26bb0981 2510#endif
6aa8b732 2511 case MSR_EFER:
3bab1f5d 2512 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2513 case MSR_IA32_TSC:
6aa8b732
AK		 2514 data = guest_read_tsc();
2515 break;
2516 case MSR_IA32_SYSENTER_CS:
2517 data = vmcs_read32(GUEST_SYSENTER_CS);
2518 break;
2519 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2520 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2521 break;
2522 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2523 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2524 break;
0dd376e7 2525 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2526 if (!vmx_mpx_supported())
2527 return 1;
0dd376e7
LJ		 2528 data = vmcs_read64(GUEST_BNDCFGS);
2529 break;
cae50139
JK		 2530 case MSR_IA32_FEATURE_CONTROL:
2531 if (!nested_vmx_allowed(vcpu))
2532 return 1;
2533 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2534 break;
2535 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2536 if (!nested_vmx_allowed(vcpu))
2537 return 1;
2538 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2539 case MSR_TSC_AUX:
2540 if (!to_vmx(vcpu)->rdtscp_enabled)
2541 return 1;
2542 /* Otherwise falls through */
6aa8b732 2543 default:
8b9cf98c 2544 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2545 if (msr) {
2546 data = msr->data;
2547 break;
6aa8b732 2548 }
3bab1f5d 2549 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2550 }
2551
2552 *pdata = data;
2553 return 0;
2554}
2555
cae50139
JK		 2556static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2557
6aa8b732
AK		 2558/*
2559 * Writes msr value into into the appropriate "register".
2560 * Returns 0 on success, non-0 otherwise.
2561 * Assumes vcpu_load() was already called.
2562 */
8fe8ab46 2563static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2564{
a2fa3e9f 2565 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2566 struct shared_msr_entry *msr;
2cc51560 2567 int ret = 0;
8fe8ab46
WA		 2568 u32 msr_index = msr_info->index;
2569 u64 data = msr_info->data;
2cc51560 2570
6aa8b732 2571 switch (msr_index) {
3bab1f5d 2572 case MSR_EFER:
8fe8ab46 2573 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2574 break;
16175a79 2575#ifdef CONFIG_X86_64
6aa8b732 2576 case MSR_FS_BASE:
2fb92db1 2577 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2578 vmcs_writel(GUEST_FS_BASE, data);
2579 break;
2580 case MSR_GS_BASE:
2fb92db1 2581 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2582 vmcs_writel(GUEST_GS_BASE, data);
2583 break;
44ea2b17
AK		 2584 case MSR_KERNEL_GS_BASE:
2585 vmx_load_host_state(vmx);
2586 vmx->msr_guest_kernel_gs_base = data;
2587 break;
6aa8b732
AK		 2588#endif
2589 case MSR_IA32_SYSENTER_CS:
2590 vmcs_write32(GUEST_SYSENTER_CS, data);
2591 break;
2592 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2593 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2594 break;
2595 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2596 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2597 break;
0dd376e7 2598 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2599 if (!vmx_mpx_supported())
2600 return 1;
0dd376e7
LJ		 2601 vmcs_write64(GUEST_BNDCFGS, data);
2602 break;
af24a4e4 2603 case MSR_IA32_TSC:
8fe8ab46 2604 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2605 break;
468d472f
SY		 2606 case MSR_IA32_CR_PAT:
2607 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2608 vmcs_write64(GUEST_IA32_PAT, data);
2609 vcpu->arch.pat = data;
2610 break;
2611 }
8fe8ab46 2612 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2613 break;
ba904635
WA		 2614 case MSR_IA32_TSC_ADJUST:
2615 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2616 break;
cae50139
JK		 2617 case MSR_IA32_FEATURE_CONTROL:
2618 if (!nested_vmx_allowed(vcpu) ||
2619 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2620 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2621 return 1;
2622 vmx->nested.msr_ia32_feature_control = data;
2623 if (msr_info->host_initiated && data == 0)
2624 vmx_leave_nested(vcpu);
2625 break;
2626 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2627 return 1; /* they are read-only */
4e47c7a6
SY		 2628 case MSR_TSC_AUX:
2629 if (!vmx->rdtscp_enabled)
2630 return 1;
2631 /* Check reserved bit, higher 32 bits should be zero */
2632 if ((data >> 32) != 0)
2633 return 1;
2634 /* Otherwise falls through */
6aa8b732 2635 default:
8b9cf98c 2636 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2637 if (msr) {
2638 msr->data = data;
2225fd56
AK		 2639 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2640 preempt_disable();
9ee73970
AK		 2641 kvm_set_shared_msr(msr->index, msr->data,
2642 msr->mask);
2225fd56
AK		 2643 preempt_enable();
2644 }
3bab1f5d 2645 break;
6aa8b732 2646 }
8fe8ab46 2647 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2648 }
2649
2cc51560 2650 return ret;
6aa8b732
AK		 2651}
2652
5fdbf976 2653static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2654{
5fdbf976
MT		 2655 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2656 switch (reg) {
2657 case VCPU_REGS_RSP:
2658 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2659 break;
2660 case VCPU_REGS_RIP:
2661 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2662 break;
6de4f3ad
AK		 2663 case VCPU_EXREG_PDPTR:
2664 if (enable_ept)
2665 ept_save_pdptrs(vcpu);
2666 break;
5fdbf976
MT		 2667 default:
2668 break;
2669 }
6aa8b732
AK		 2670}
2671
6aa8b732
AK		 2672static __init int cpu_has_kvm_support(void)
2673{
6210e37b 2674 return cpu_has_vmx();
6aa8b732
AK		 2675}
2676
2677static __init int vmx_disabled_by_bios(void)
2678{
2679 u64 msr;
2680
2681 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2682 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2683 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2684 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2685 && tboot_enabled())
2686 return 1;
23f3e991 2687 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2688 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2689 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2690 && !tboot_enabled()) {
2691 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2692 "activate TXT before enabling KVM\n");
cafd6659 2693 return 1;
f9335afe 2694 }
23f3e991
JC		 2695 /* launched w/o TXT and VMX disabled */
2696 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2697 && !tboot_enabled())
2698 return 1;
cafd6659
SW		 2699 }
2700
2701 return 0;
6aa8b732
AK		 2702}
2703
7725b894
DX		 2704static void kvm_cpu_vmxon(u64 addr)
2705{
2706 asm volatile (ASM_VMX_VMXON_RAX
2707 : : "a"(&addr), "m"(addr)
2708 : "memory", "cc");
2709}
2710
10474ae8 2711static int hardware_enable(void *garbage)
6aa8b732
AK		 2712{
2713 int cpu = raw_smp_processor_id();
2714 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2715 u64 old, test_bits;
6aa8b732 2716
10474ae8
AG		 2717 if (read_cr4() & X86_CR4_VMXE)
2718 return -EBUSY;
2719
d462b819 2720 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2721
2722 /*
2723 * Now we can enable the vmclear operation in kdump
2724 * since the loaded_vmcss_on_cpu list on this cpu
2725 * has been initialized.
2726 *
2727 * Though the cpu is not in VMX operation now, there
2728 * is no problem to enable the vmclear operation
2729 * for the loaded_vmcss_on_cpu list is empty!
2730 */
2731 crash_enable_local_vmclear(cpu);
2732
6aa8b732 2733 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2734
2735 test_bits = FEATURE_CONTROL_LOCKED;
2736 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2737 if (tboot_enabled())
2738 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2739
2740 if ((old & test_bits) != test_bits) {
6aa8b732 2741 /* enable and lock */
cafd6659
SW		 2742 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2743 }
66aee91a 2744 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2745
4610c9cc
DX		 2746 if (vmm_exclusive) {
2747 kvm_cpu_vmxon(phys_addr);
2748 ept_sync_global();
2749 }
10474ae8 2750
357d1226 2751 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2752
10474ae8 2753 return 0;
6aa8b732
AK		 2754}
2755
d462b819 2756static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2757{
2758 int cpu = raw_smp_processor_id();
d462b819 2759 struct loaded_vmcs *v, *n;
543e4243 2760
d462b819
NHE		 2761 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2762 loaded_vmcss_on_cpu_link)
2763 __loaded_vmcs_clear(v);
543e4243
AK		 2764}
2765
710ff4a8
EH		 2766
2767/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2768 * tricks.
2769 */
2770static void kvm_cpu_vmxoff(void)
6aa8b732 2771{
4ecac3fd 2772 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2773}
2774
710ff4a8
EH		 2775static void hardware_disable(void *garbage)
2776{
4610c9cc 2777 if (vmm_exclusive) {
d462b819 2778 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2779 kvm_cpu_vmxoff();
2780 }
7725b894 2781 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2782}
2783
1c3d14fe 2784static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2785 u32 msr, u32 *result)
1c3d14fe
YS		 2786{
2787 u32 vmx_msr_low, vmx_msr_high;
2788 u32 ctl = ctl_min | ctl_opt;
2789
2790 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2791
2792 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2793 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2794
2795 /* Ensure minimum (required) set of control bits are supported. */
2796 if (ctl_min & ~ctl)
002c7f7c 2797 return -EIO;
1c3d14fe
YS		 2798
2799 *result = ctl;
2800 return 0;
2801}
2802
110312c8
AK		 2803static __init bool allow_1_setting(u32 msr, u32 ctl)
2804{
2805 u32 vmx_msr_low, vmx_msr_high;
2806
2807 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2808 return vmx_msr_high & ctl;
2809}
2810
002c7f7c 2811static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2812{
2813 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2814 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2815 u32 _pin_based_exec_control = 0;
2816 u32 _cpu_based_exec_control = 0;
f78e0e2e 2817 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2818 u32 _vmexit_control = 0;
2819 u32 _vmentry_control = 0;
2820
10166744 2821 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2822#ifdef CONFIG_X86_64
2823 CPU_BASED_CR8_LOAD_EXITING |
2824 CPU_BASED_CR8_STORE_EXITING |
2825#endif
d56f546d
SY		 2826 CPU_BASED_CR3_LOAD_EXITING |
2827 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2828 CPU_BASED_USE_IO_BITMAPS |
2829 CPU_BASED_MOV_DR_EXITING |
a7052897 2830 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2831 CPU_BASED_MWAIT_EXITING |
2832 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2833 CPU_BASED_INVLPG_EXITING |
2834 CPU_BASED_RDPMC_EXITING;
443381a8 2835
f78e0e2e 2836 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2837 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2838 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2839 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2840 &_cpu_based_exec_control) < 0)
002c7f7c 2841 return -EIO;
6e5d865c
YS		 2842#ifdef CONFIG_X86_64
2843 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2844 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2845 ~CPU_BASED_CR8_STORE_EXITING;
2846#endif
f78e0e2e 2847 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2848 min2 = 0;
2849 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2850 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2851 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2852 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2853 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2854 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2855 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2856 SECONDARY_EXEC_RDTSCP |
83d4c286 2857 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2858 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2859 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2860 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2861 if (adjust_vmx_controls(min2, opt2,
2862 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2863 &_cpu_based_2nd_exec_control) < 0)
2864 return -EIO;
2865 }
2866#ifndef CONFIG_X86_64
2867 if (!(_cpu_based_2nd_exec_control &
2868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2869 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2870#endif
83d4c286
YZ		 2871
2872 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2873 _cpu_based_2nd_exec_control &= ~(
8d14695f 2874 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2875 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2876 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2877
d56f546d 2878 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2879 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2880 enabled */
5fff7d27
GN		 2881 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2882 CPU_BASED_CR3_STORE_EXITING |
2883 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2884 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2885 vmx_capability.ept, vmx_capability.vpid);
2886 }
1c3d14fe 2887
81908bf4 2888 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2889#ifdef CONFIG_X86_64
2890 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2891#endif
a547c6db 2892 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2893 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2894 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2895 &_vmexit_control) < 0)
002c7f7c 2896 return -EIO;
1c3d14fe 2897
01e439be
YZ		 2898 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2899 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2900 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2901 &_pin_based_exec_control) < 0)
2902 return -EIO;
2903
2904 if (!(_cpu_based_2nd_exec_control &
2905 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2906 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2907 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2908
c845f9c6 2909 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2910 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2911 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2912 &_vmentry_control) < 0)
002c7f7c 2913 return -EIO;
6aa8b732 2914
c68876fd 2915 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2916
2917 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2918 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2919 return -EIO;
1c3d14fe
YS		 2920
2921#ifdef CONFIG_X86_64
2922 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2923 if (vmx_msr_high & (1u<<16))
002c7f7c 2924 return -EIO;
1c3d14fe
YS		 2925#endif
2926
2927 /* Require Write-Back (WB) memory type for VMCS accesses. */
2928 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2929 return -EIO;
1c3d14fe 2930
002c7f7c
YS		 2931 vmcs_conf->size = vmx_msr_high & 0x1fff;
2932 vmcs_conf->order = get_order(vmcs_config.size);
2933 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2934
002c7f7c
YS		 2935 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2936 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2937 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2938 vmcs_conf->vmexit_ctrl = _vmexit_control;
2939 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2940
110312c8
AK		 2941 cpu_has_load_ia32_efer =
2942 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2943 VM_ENTRY_LOAD_IA32_EFER)
2944 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2945 VM_EXIT_LOAD_IA32_EFER);
2946
8bf00a52
GN		 2947 cpu_has_load_perf_global_ctrl =
2948 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2949 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2950 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2951 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2952
2953 /*
2954 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2955 * but due to arrata below it can't be used. Workaround is to use
2956 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2957 *
2958 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2959 *
2960 * AAK155 (model 26)
2961 * AAP115 (model 30)
2962 * AAT100 (model 37)
2963 * BC86,AAY89,BD102 (model 44)
2964 * BA97 (model 46)
2965 *
2966 */
2967 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2968 switch (boot_cpu_data.x86_model) {
2969 case 26:
2970 case 30:
2971 case 37:
2972 case 44:
2973 case 46:
2974 cpu_has_load_perf_global_ctrl = false;
2975 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2976 "does not work properly. Using workaround\n");
2977 break;
2978 default:
2979 break;
2980 }
2981 }
2982
1c3d14fe 2983 return 0;
c68876fd 2984}
6aa8b732
AK		 2985
2986static struct vmcs *alloc_vmcs_cpu(int cpu)
2987{
2988 int node = cpu_to_node(cpu);
2989 struct page *pages;
2990 struct vmcs *vmcs;
2991
6484eb3e 2992 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2993 if (!pages)
2994 return NULL;
2995 vmcs = page_address(pages);
1c3d14fe
YS		 2996 memset(vmcs, 0, vmcs_config.size);
2997 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2998 return vmcs;
2999}
3000
3001static struct vmcs *alloc_vmcs(void)
3002{
d3b2c338 3003 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3004}
3005
3006static void free_vmcs(struct vmcs *vmcs)
3007{
1c3d14fe 3008 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3009}
3010
d462b819
NHE		 3011/*
3012 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3013 */
3014static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3015{
3016 if (!loaded_vmcs->vmcs)
3017 return;
3018 loaded_vmcs_clear(loaded_vmcs);
3019 free_vmcs(loaded_vmcs->vmcs);
3020 loaded_vmcs->vmcs = NULL;
3021}
3022
39959588 3023static void free_kvm_area(void)
6aa8b732
AK		 3024{
3025 int cpu;
3026
3230bb47 3027 for_each_possible_cpu(cpu) {
6aa8b732 3028 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3029 per_cpu(vmxarea, cpu) = NULL;
3030 }
6aa8b732
AK		 3031}
3032
fe2b201b
BD		 3033static void init_vmcs_shadow_fields(void)
3034{
3035 int i, j;
3036
3037 /* No checks for read only fields yet */
3038
3039 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3040 switch (shadow_read_write_fields[i]) {
3041 case GUEST_BNDCFGS:
3042 if (!vmx_mpx_supported())
3043 continue;
3044 break;
3045 default:
3046 break;
3047 }
3048
3049 if (j < i)
3050 shadow_read_write_fields[j] =
3051 shadow_read_write_fields[i];
3052 j++;
3053 }
3054 max_shadow_read_write_fields = j;
3055
3056 /* shadowed fields guest access without vmexit */
3057 for (i = 0; i < max_shadow_read_write_fields; i++) {
3058 clear_bit(shadow_read_write_fields[i],
3059 vmx_vmwrite_bitmap);
3060 clear_bit(shadow_read_write_fields[i],
3061 vmx_vmread_bitmap);
3062 }
3063 for (i = 0; i < max_shadow_read_only_fields; i++)
3064 clear_bit(shadow_read_only_fields[i],
3065 vmx_vmread_bitmap);
3066}
3067
6aa8b732
AK		 3068static __init int alloc_kvm_area(void)
3069{
3070 int cpu;
3071
3230bb47 3072 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3073 struct vmcs *vmcs;
3074
3075 vmcs = alloc_vmcs_cpu(cpu);
3076 if (!vmcs) {
3077 free_kvm_area();
3078 return -ENOMEM;
3079 }
3080
3081 per_cpu(vmxarea, cpu) = vmcs;
3082 }
3083 return 0;
3084}
3085
3086static __init int hardware_setup(void)
3087{
002c7f7c
YS		 3088 if (setup_vmcs_config(&vmcs_config) < 0)
3089 return -EIO;
50a37eb4
JR		 3090
3091 if (boot_cpu_has(X86_FEATURE_NX))
3092 kvm_enable_efer_bits(EFER_NX);
3093
93ba03c2
SY		 3094 if (!cpu_has_vmx_vpid())
3095 enable_vpid = 0;
abc4fc58
AG		 3096 if (!cpu_has_vmx_shadow_vmcs())
3097 enable_shadow_vmcs = 0;
fe2b201b
BD		 3098 if (enable_shadow_vmcs)
3099 init_vmcs_shadow_fields();
93ba03c2 3100
4bc9b982
SY		 3101 if (!cpu_has_vmx_ept() ||
3102 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3103 enable_ept = 0;
3a624e29 3104 enable_unrestricted_guest = 0;
83c3a331 3105 enable_ept_ad_bits = 0;
3a624e29
NK		 3106 }
3107
83c3a331
XH		 3108 if (!cpu_has_vmx_ept_ad_bits())
3109 enable_ept_ad_bits = 0;
3110
3a624e29
NK		 3111 if (!cpu_has_vmx_unrestricted_guest())
3112 enable_unrestricted_guest = 0;
93ba03c2
SY		 3113
3114 if (!cpu_has_vmx_flexpriority())
3115 flexpriority_enabled = 0;
3116
95ba8273
GN		 3117 if (!cpu_has_vmx_tpr_shadow())
3118 kvm_x86_ops->update_cr8_intercept = NULL;
3119
54dee993
MT		 3120 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3121 kvm_disable_largepages();
3122
4b8d54f9
ZE		 3123 if (!cpu_has_vmx_ple())
3124 ple_gap = 0;
3125
01e439be
YZ		 3126 if (!cpu_has_vmx_apicv())
3127 enable_apicv = 0;
c7c9c56c 3128
01e439be 3129 if (enable_apicv)
c7c9c56c 3130 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3131 else {
c7c9c56c 3132 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3133 kvm_x86_ops->deliver_posted_interrupt = NULL;
3134 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3135 }
83d4c286 3136
b87a51ae
NHE		 3137 if (nested)
3138 nested_vmx_setup_ctls_msrs();
3139
6aa8b732
AK		 3140 return alloc_kvm_area();
3141}
3142
3143static __exit void hardware_unsetup(void)
3144{
3145 free_kvm_area();
3146}
3147
14168786
GN		 3148static bool emulation_required(struct kvm_vcpu *vcpu)
3149{
3150 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3151}
3152
91b0aa2c 3153static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3154 struct kvm_segment *save)
6aa8b732 3155{
d99e4152
GN		 3156 if (!emulate_invalid_guest_state) {
3157 /*
3158 * CS and SS RPL should be equal during guest entry according
3159 * to VMX spec, but in reality it is not always so. Since vcpu
3160 * is in the middle of the transition from real mode to
3161 * protected mode it is safe to assume that RPL 0 is a good
3162 * default value.
3163 */
3164 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3165 save->selector &= ~SELECTOR_RPL_MASK;
3166 save->dpl = save->selector & SELECTOR_RPL_MASK;
3167 save->s = 1;
6aa8b732 3168 }
d99e4152 3169 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3170}
3171
3172static void enter_pmode(struct kvm_vcpu *vcpu)
3173{
3174 unsigned long flags;
a89a8fb9 3175 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3176
d99e4152
GN		 3177 /*
3178 * Update real mode segment cache. It may be not up-to-date if sement
3179 * register was written while vcpu was in a guest mode.
3180 */
3181 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3182 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3183 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3184 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3185 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3186 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3187
7ffd92c5 3188 vmx->rmode.vm86_active = 0;
6aa8b732 3189
2fb92db1
AK		 3190 vmx_segment_cache_clear(vmx);
3191
f5f7b2fe 3192 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3193
3194 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3195 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3196 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3197 vmcs_writel(GUEST_RFLAGS, flags);
3198
66aee91a
RR		 3199 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3200 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3201
3202 update_exception_bitmap(vcpu);
3203
91b0aa2c
GN		 3204 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3205 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3206 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3207 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3208 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3209 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3210}
3211
f5f7b2fe 3212static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3213{
772e0318 3214 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3215 struct kvm_segment var = *save;
3216
3217 var.dpl = 0x3;
3218 if (seg == VCPU_SREG_CS)
3219 var.type = 0x3;
3220
3221 if (!emulate_invalid_guest_state) {
3222 var.selector = var.base >> 4;
3223 var.base = var.base & 0xffff0;
3224 var.limit = 0xffff;
3225 var.g = 0;
3226 var.db = 0;
3227 var.present = 1;
3228 var.s = 1;
3229 var.l = 0;
3230 var.unusable = 0;
3231 var.type = 0x3;
3232 var.avl = 0;
3233 if (save->base & 0xf)
3234 printk_once(KERN_WARNING "kvm: segment base is not "
3235 "paragraph aligned when entering "
3236 "protected mode (seg=%d)", seg);
3237 }
6aa8b732 3238
d99e4152
GN		 3239 vmcs_write16(sf->selector, var.selector);
3240 vmcs_write32(sf->base, var.base);
3241 vmcs_write32(sf->limit, var.limit);
3242 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3243}
3244
3245static void enter_rmode(struct kvm_vcpu *vcpu)
3246{
3247 unsigned long flags;
a89a8fb9 3248 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3249
f5f7b2fe
AK		 3250 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3251 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3252 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3253 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3254 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3255 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3256 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3257
7ffd92c5 3258 vmx->rmode.vm86_active = 1;
6aa8b732 3259
776e58ea
GN		 3260 /*
3261 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3262 * vcpu. Warn the user that an update is overdue.
776e58ea 3263 */
4918c6ca 3264 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3265 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3266 "called before entering vcpu\n");
776e58ea 3267
2fb92db1
AK		 3268 vmx_segment_cache_clear(vmx);
3269
4918c6ca 3270 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3271 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3272 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3273
3274 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3275 vmx->rmode.save_rflags = flags;
6aa8b732 3276
053de044 3277 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3278
3279 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3280 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3281 update_exception_bitmap(vcpu);
3282
d99e4152
GN		 3283 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3284 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3285 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3286 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3287 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3288 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3289
8668a3c4 3290 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3291}
3292
401d10de
AS		 3293static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3294{
3295 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3296 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3297
3298 if (!msr)
3299 return;
401d10de 3300
44ea2b17
AK		 3301 /*
3302 * Force kernel_gs_base reloading before EFER changes, as control
3303 * of this msr depends on is_long_mode().
3304 */
3305 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3306 vcpu->arch.efer = efer;
401d10de 3307 if (efer & EFER_LMA) {
2961e876 3308 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3309 msr->data = efer;
3310 } else {
2961e876 3311 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3312
3313 msr->data = efer & ~EFER_LME;
3314 }
3315 setup_msrs(vmx);
3316}
3317
05b3e0c2 3318#ifdef CONFIG_X86_64
6aa8b732
AK		 3319
3320static void enter_lmode(struct kvm_vcpu *vcpu)
3321{
3322 u32 guest_tr_ar;
3323
2fb92db1
AK		 3324 vmx_segment_cache_clear(to_vmx(vcpu));
3325
6aa8b732
AK		 3326 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3327 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3328 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3329 __func__);
6aa8b732
AK		 3330 vmcs_write32(GUEST_TR_AR_BYTES,
3331 (guest_tr_ar & ~AR_TYPE_MASK)
3332 | AR_TYPE_BUSY_64_TSS);
3333 }
da38f438 3334 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3335}
3336
3337static void exit_lmode(struct kvm_vcpu *vcpu)
3338{
2961e876 3339 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3340 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3341}
3342
3343#endif
3344
2384d2b3
SY		 3345static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3346{
b9d762fa 3347 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3348 if (enable_ept) {
3349 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3350 return;
4e1096d2 3351 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3352 }
2384d2b3
SY		 3353}
3354
e8467fda
AK		 3355static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3356{
3357 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3358
3359 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3360 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3361}
3362
aff48baa
AK		 3363static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3364{
3365 if (enable_ept && is_paging(vcpu))
3366 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3367 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3368}
3369
25c4c276 3370static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3371{
fc78f519
AK		 3372 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3373
3374 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3375 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3376}
3377
1439442c
SY		 3378static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3379{
d0d538b9
GN		 3380 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3381
6de4f3ad
AK		 3382 if (!test_bit(VCPU_EXREG_PDPTR,
3383 (unsigned long *)&vcpu->arch.regs_dirty))
3384 return;
3385
1439442c 3386 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3387 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3388 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3389 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3390 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3391 }
3392}
3393
8f5d549f
AK		 3394static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3395{
d0d538b9
GN		 3396 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3397
8f5d549f 3398 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3399 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3400 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3401 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3402 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3403 }
6de4f3ad
AK		 3404
3405 __set_bit(VCPU_EXREG_PDPTR,
3406 (unsigned long *)&vcpu->arch.regs_avail);
3407 __set_bit(VCPU_EXREG_PDPTR,
3408 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3409}
3410
5e1746d6 3411static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3412
3413static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3414 unsigned long cr0,
3415 struct kvm_vcpu *vcpu)
3416{
5233dd51
MT		 3417 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3418 vmx_decache_cr3(vcpu);
1439442c
SY		 3419 if (!(cr0 & X86_CR0_PG)) {
3420 /* From paging/starting to nonpaging */
3421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3422 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3423 (CPU_BASED_CR3_LOAD_EXITING |
3424 CPU_BASED_CR3_STORE_EXITING));
3425 vcpu->arch.cr0 = cr0;
fc78f519 3426 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3427 } else if (!is_paging(vcpu)) {
3428 /* From nonpaging to paging */
3429 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3430 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3431 ~(CPU_BASED_CR3_LOAD_EXITING |
3432 CPU_BASED_CR3_STORE_EXITING));
3433 vcpu->arch.cr0 = cr0;
fc78f519 3434 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3435 }
95eb84a7
SY		 3436
3437 if (!(cr0 & X86_CR0_WP))
3438 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3439}
3440
6aa8b732
AK		 3441static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3442{
7ffd92c5 3443 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3444 unsigned long hw_cr0;
3445
5037878e 3446 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3447 if (enable_unrestricted_guest)
5037878e 3448 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3449 else {
5037878e 3450 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3451
218e763f
GN		 3452 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3453 enter_pmode(vcpu);
6aa8b732 3454
218e763f
GN		 3455 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3456 enter_rmode(vcpu);
3457 }
6aa8b732 3458
05b3e0c2 3459#ifdef CONFIG_X86_64
f6801dff 3460 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3461 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3462 enter_lmode(vcpu);
707d92fa 3463 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3464 exit_lmode(vcpu);
3465 }
3466#endif
3467
089d034e 3468 if (enable_ept)
1439442c
SY		 3469 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3470
02daab21 3471 if (!vcpu->fpu_active)
81231c69 3472 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3473
6aa8b732 3474 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3475 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3476 vcpu->arch.cr0 = cr0;
14168786
GN		 3477
3478 /* depends on vcpu->arch.cr0 to be set to a new value */
3479 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3480}
3481
1439442c
SY		 3482static u64 construct_eptp(unsigned long root_hpa)
3483{
3484 u64 eptp;
3485
3486 /* TODO write the value reading from MSR */
3487 eptp = VMX_EPT_DEFAULT_MT |
3488 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3489 if (enable_ept_ad_bits)
3490 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3491 eptp |= (root_hpa & PAGE_MASK);
3492
3493 return eptp;
3494}
3495
6aa8b732
AK		 3496static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3497{
1439442c
SY		 3498 unsigned long guest_cr3;
3499 u64 eptp;
3500
3501 guest_cr3 = cr3;
089d034e 3502 if (enable_ept) {
1439442c
SY		 3503 eptp = construct_eptp(cr3);
3504 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3505 if (is_paging(vcpu) || is_guest_mode(vcpu))
3506 guest_cr3 = kvm_read_cr3(vcpu);
3507 else
3508 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3509 ept_load_pdptrs(vcpu);
1439442c
SY		 3510 }
3511
2384d2b3 3512 vmx_flush_tlb(vcpu);
1439442c 3513 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3514}
3515
5e1746d6 3516static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3517{
7ffd92c5 3518 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3519 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3520
5e1746d6
NHE		 3521 if (cr4 & X86_CR4_VMXE) {
3522 /*
3523 * To use VMXON (and later other VMX instructions), a guest
3524 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3525 * So basically the check on whether to allow nested VMX
3526 * is here.
3527 */
3528 if (!nested_vmx_allowed(vcpu))
3529 return 1;
1a0d74e6
JK		 3530 }
3531 if (to_vmx(vcpu)->nested.vmxon &&
3532 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3533 return 1;
3534
ad312c7c 3535 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3536 if (enable_ept) {
3537 if (!is_paging(vcpu)) {
3538 hw_cr4 &= ~X86_CR4_PAE;
3539 hw_cr4 |= X86_CR4_PSE;
c08800a5 3540 /*
e1e746b3
FW		 3541 * SMEP/SMAP is disabled if CPU is in non-paging mode
3542 * in hardware. However KVM always uses paging mode to
c08800a5 3543 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3544 * To emulate this behavior, SMEP/SMAP needs to be
3545 * manually disabled when guest switches to non-paging
3546 * mode.
c08800a5 3547 */
e1e746b3 3548 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3549 } else if (!(cr4 & X86_CR4_PAE)) {
3550 hw_cr4 &= ~X86_CR4_PAE;
3551 }
3552 }
1439442c
SY		 3553
3554 vmcs_writel(CR4_READ_SHADOW, cr4);
3555 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3556 return 0;
6aa8b732
AK		 3557}
3558
6aa8b732
AK		 3559static void vmx_get_segment(struct kvm_vcpu *vcpu,
3560 struct kvm_segment *var, int seg)
3561{
a9179499 3562 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3563 u32 ar;
3564
c6ad1153 3565 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3566 *var = vmx->rmode.segs[seg];
a9179499 3567 if (seg == VCPU_SREG_TR
2fb92db1 3568 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3569 return;
1390a28b
AK		 3570 var->base = vmx_read_guest_seg_base(vmx, seg);
3571 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3572 return;
a9179499 3573 }
2fb92db1
AK		 3574 var->base = vmx_read_guest_seg_base(vmx, seg);
3575 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3576 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3577 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3578 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3579 var->type = ar & 15;
3580 var->s = (ar >> 4) & 1;
3581 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3582 /*
3583 * Some userspaces do not preserve unusable property. Since usable
3584 * segment has to be present according to VMX spec we can use present
3585 * property to amend userspace bug by making unusable segment always
3586 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3587 * segment as unusable.
3588 */
3589 var->present = !var->unusable;
6aa8b732
AK		 3590 var->avl = (ar >> 12) & 1;
3591 var->l = (ar >> 13) & 1;
3592 var->db = (ar >> 14) & 1;
3593 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3594}
3595
a9179499
AK		 3596static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3597{
a9179499
AK		 3598 struct kvm_segment s;
3599
3600 if (to_vmx(vcpu)->rmode.vm86_active) {
3601 vmx_get_segment(vcpu, &s, seg);
3602 return s.base;
3603 }
2fb92db1 3604 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3605}
3606
b09408d0 3607static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3608{
b09408d0
MT		 3609 struct vcpu_vmx *vmx = to_vmx(vcpu);
3610
ae9fedc7 3611 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3612 return 0;
ae9fedc7
PB		 3613 else {
3614 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3615 return AR_DPL(ar);
69c73028 3616 }
69c73028
AK		 3617}
3618
653e3108 3619static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3620{
6aa8b732
AK		 3621 u32 ar;
3622
f0495f9b 3623 if (var->unusable || !var->present)
6aa8b732
AK		 3624 ar = 1 << 16;
3625 else {
3626 ar = var->type & 15;
3627 ar |= (var->s & 1) << 4;
3628 ar |= (var->dpl & 3) << 5;
3629 ar |= (var->present & 1) << 7;
3630 ar |= (var->avl & 1) << 12;
3631 ar |= (var->l & 1) << 13;
3632 ar |= (var->db & 1) << 14;
3633 ar |= (var->g & 1) << 15;
3634 }
653e3108
AK		 3635
3636 return ar;
3637}
3638
3639static void vmx_set_segment(struct kvm_vcpu *vcpu,
3640 struct kvm_segment *var, int seg)
3641{
7ffd92c5 3642 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3643 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3644
2fb92db1
AK		 3645 vmx_segment_cache_clear(vmx);
3646
1ecd50a9
GN		 3647 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3648 vmx->rmode.segs[seg] = *var;
3649 if (seg == VCPU_SREG_TR)
3650 vmcs_write16(sf->selector, var->selector);
3651 else if (var->s)
3652 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3653 goto out;
653e3108 3654 }
1ecd50a9 3655
653e3108
AK		 3656 vmcs_writel(sf->base, var->base);
3657 vmcs_write32(sf->limit, var->limit);
3658 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3659
3660 /*
3661 * Fix the "Accessed" bit in AR field of segment registers for older
3662 * qemu binaries.
3663 * IA32 arch specifies that at the time of processor reset the
3664 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3665 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3666 * state vmexit when "unrestricted guest" mode is turned on.
3667 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3668 * tree. Newer qemu binaries with that qemu fix would not need this
3669 * kvm hack.
3670 */
3671 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3672 var->type |= 0x1; /* Accessed */
3a624e29 3673
f924d66d 3674 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3675
3676out:
98eb2f8b 3677 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3678}
3679
6aa8b732
AK		 3680static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3681{
2fb92db1 3682 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3683
3684 *db = (ar >> 14) & 1;
3685 *l = (ar >> 13) & 1;
3686}
3687
89a27f4d 3688static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3689{
89a27f4d
GN		 3690 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3691 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3692}
3693
89a27f4d 3694static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3695{
89a27f4d
GN		 3696 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3697 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3698}
3699
89a27f4d 3700static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3701{
89a27f4d
GN		 3702 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3703 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3704}
3705
89a27f4d 3706static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3707{
89a27f4d
GN		 3708 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3709 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3710}
3711
648dfaa7
MG		 3712static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3713{
3714 struct kvm_segment var;
3715 u32 ar;
3716
3717 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3718 var.dpl = 0x3;
0647f4aa
GN		 3719 if (seg == VCPU_SREG_CS)
3720 var.type = 0x3;
648dfaa7
MG		 3721 ar = vmx_segment_access_rights(&var);
3722
3723 if (var.base != (var.selector << 4))
3724 return false;
89efbed0 3725 if (var.limit != 0xffff)
648dfaa7 3726 return false;
07f42f5f 3727 if (ar != 0xf3)
648dfaa7
MG		 3728 return false;
3729
3730 return true;
3731}
3732
3733static bool code_segment_valid(struct kvm_vcpu *vcpu)
3734{
3735 struct kvm_segment cs;
3736 unsigned int cs_rpl;
3737
3738 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3739 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3740
1872a3f4
AK		 3741 if (cs.unusable)
3742 return false;
648dfaa7
MG		 3743 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3744 return false;
3745 if (!cs.s)
3746 return false;
1872a3f4 3747 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3748 if (cs.dpl > cs_rpl)
3749 return false;
1872a3f4 3750 } else {
648dfaa7
MG		 3751 if (cs.dpl != cs_rpl)
3752 return false;
3753 }
3754 if (!cs.present)
3755 return false;
3756
3757 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3758 return true;
3759}
3760
3761static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3762{
3763 struct kvm_segment ss;
3764 unsigned int ss_rpl;
3765
3766 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3767 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3768
1872a3f4
AK		 3769 if (ss.unusable)
3770 return true;
3771 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3772 return false;
3773 if (!ss.s)
3774 return false;
3775 if (ss.dpl != ss_rpl) /* DPL != RPL */
3776 return false;
3777 if (!ss.present)
3778 return false;
3779
3780 return true;
3781}
3782
3783static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3784{
3785 struct kvm_segment var;
3786 unsigned int rpl;
3787
3788 vmx_get_segment(vcpu, &var, seg);
3789 rpl = var.selector & SELECTOR_RPL_MASK;
3790
1872a3f4
AK		 3791 if (var.unusable)
3792 return true;
648dfaa7
MG		 3793 if (!var.s)
3794 return false;
3795 if (!var.present)
3796 return false;
3797 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3798 if (var.dpl < rpl) /* DPL < RPL */
3799 return false;
3800 }
3801
3802 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3803 * rights flags
3804 */
3805 return true;
3806}
3807
3808static bool tr_valid(struct kvm_vcpu *vcpu)
3809{
3810 struct kvm_segment tr;
3811
3812 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3813
1872a3f4
AK		 3814 if (tr.unusable)
3815 return false;
648dfaa7
MG		 3816 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3817 return false;
1872a3f4 3818 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3819 return false;
3820 if (!tr.present)
3821 return false;
3822
3823 return true;
3824}
3825
3826static bool ldtr_valid(struct kvm_vcpu *vcpu)
3827{
3828 struct kvm_segment ldtr;
3829
3830 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3831
1872a3f4
AK		 3832 if (ldtr.unusable)
3833 return true;
648dfaa7
MG		 3834 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3835 return false;
3836 if (ldtr.type != 2)
3837 return false;
3838 if (!ldtr.present)
3839 return false;
3840
3841 return true;
3842}
3843
3844static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3845{
3846 struct kvm_segment cs, ss;
3847
3848 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3849 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3850
3851 return ((cs.selector & SELECTOR_RPL_MASK) ==
3852 (ss.selector & SELECTOR_RPL_MASK));
3853}
3854
3855/*
3856 * Check if guest state is valid. Returns true if valid, false if
3857 * not.
3858 * We assume that registers are always usable
3859 */
3860static bool guest_state_valid(struct kvm_vcpu *vcpu)
3861{
c5e97c80
GN		 3862 if (enable_unrestricted_guest)
3863 return true;
3864
648dfaa7 3865 /* real mode guest state checks */
f13882d8 3866 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3867 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3868 return false;
3869 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3870 return false;
3871 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3872 return false;
3873 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3874 return false;
3875 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3876 return false;
3877 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3878 return false;
3879 } else {
3880 /* protected mode guest state checks */
3881 if (!cs_ss_rpl_check(vcpu))
3882 return false;
3883 if (!code_segment_valid(vcpu))
3884 return false;
3885 if (!stack_segment_valid(vcpu))
3886 return false;
3887 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3888 return false;
3889 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3890 return false;
3891 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3892 return false;
3893 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3894 return false;
3895 if (!tr_valid(vcpu))
3896 return false;
3897 if (!ldtr_valid(vcpu))
3898 return false;
3899 }
3900 /* TODO:
3901 * - Add checks on RIP
3902 * - Add checks on RFLAGS
3903 */
3904
3905 return true;
3906}
3907
d77c26fc 3908static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3909{
40dcaa9f 3910 gfn_t fn;
195aefde 3911 u16 data = 0;
40dcaa9f 3912 int r, idx, ret = 0;
6aa8b732 3913
40dcaa9f 3914 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3915 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3916 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3917 if (r < 0)
10589a46 3918 goto out;
195aefde 3919 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3920 r = kvm_write_guest_page(kvm, fn++, &data,
3921 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3922 if (r < 0)
10589a46 3923 goto out;
195aefde
IE		 3924 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3925 if (r < 0)
10589a46 3926 goto out;
195aefde
IE		 3927 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3928 if (r < 0)
10589a46 3929 goto out;
195aefde 3930 data = ~0;
10589a46
MT		 3931 r = kvm_write_guest_page(kvm, fn, &data,
3932 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3933 sizeof(u8));
195aefde 3934 if (r < 0)
10589a46
MT		 3935 goto out;
3936
3937 ret = 1;
3938out:
40dcaa9f 3939 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3940 return ret;
6aa8b732
AK		 3941}
3942
b7ebfb05
SY		 3943static int init_rmode_identity_map(struct kvm *kvm)
3944{
40dcaa9f 3945 int i, idx, r, ret;
b7ebfb05
SY		 3946 pfn_t identity_map_pfn;
3947 u32 tmp;
3948
089d034e 3949 if (!enable_ept)
b7ebfb05
SY		 3950 return 1;
3951 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3952 printk(KERN_ERR "EPT: identity-mapping pagetable "
3953 "haven't been allocated!\n");
3954 return 0;
3955 }
3956 if (likely(kvm->arch.ept_identity_pagetable_done))
3957 return 1;
3958 ret = 0;
b927a3ce 3959 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3960 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3961 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3962 if (r < 0)
3963 goto out;
3964 /* Set up identity-mapping pagetable for EPT in real mode */
3965 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3966 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3967 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3968 r = kvm_write_guest_page(kvm, identity_map_pfn,
3969 &tmp, i * sizeof(tmp), sizeof(tmp));
3970 if (r < 0)
3971 goto out;
3972 }
3973 kvm->arch.ept_identity_pagetable_done = true;
3974 ret = 1;
3975out:
40dcaa9f 3976 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3977 return ret;
3978}
3979
6aa8b732
AK		 3980static void seg_setup(int seg)
3981{
772e0318 3982 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3983 unsigned int ar;
6aa8b732
AK		 3984
3985 vmcs_write16(sf->selector, 0);
3986 vmcs_writel(sf->base, 0);
3987 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3988 ar = 0x93;
3989 if (seg == VCPU_SREG_CS)
3990 ar |= 0x08; /* code segment */
3a624e29
NK		 3991
3992 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3993}
3994
f78e0e2e
SY		 3995static int alloc_apic_access_page(struct kvm *kvm)
3996{
4484141a 3997 struct page *page;
f78e0e2e
SY		 3998 struct kvm_userspace_memory_region kvm_userspace_mem;
3999 int r = 0;
4000
79fac95e 4001 mutex_lock(&kvm->slots_lock);
bfc6d222 4002 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4003 goto out;
4004 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4005 kvm_userspace_mem.flags = 0;
4006 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4007 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4008 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4009 if (r)
4010 goto out;
72dc67a6 4011
4484141a
XG		 4012 page = gfn_to_page(kvm, 0xfee00);
4013 if (is_error_page(page)) {
4014 r = -EFAULT;
4015 goto out;
4016 }
4017
4018 kvm->arch.apic_access_page = page;
f78e0e2e 4019out:
79fac95e 4020 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4021 return r;
4022}
4023
b7ebfb05
SY		 4024static int alloc_identity_pagetable(struct kvm *kvm)
4025{
4484141a 4026 struct page *page;
b7ebfb05
SY		 4027 struct kvm_userspace_memory_region kvm_userspace_mem;
4028 int r = 0;
4029
79fac95e 4030 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4031 if (kvm->arch.ept_identity_pagetable)
4032 goto out;
4033 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4034 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4035 kvm_userspace_mem.guest_phys_addr =
4036 kvm->arch.ept_identity_map_addr;
b7ebfb05 4037 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4038 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4039 if (r)
4040 goto out;
4041
4484141a
XG		 4042 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4043 if (is_error_page(page)) {
4044 r = -EFAULT;
4045 goto out;
4046 }
4047
4048 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4049out:
79fac95e 4050 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4051 return r;
4052}
4053
2384d2b3
SY		 4054static void allocate_vpid(struct vcpu_vmx *vmx)
4055{
4056 int vpid;
4057
4058 vmx->vpid = 0;
919818ab 4059 if (!enable_vpid)
2384d2b3
SY		 4060 return;
4061 spin_lock(&vmx_vpid_lock);
4062 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4063 if (vpid < VMX_NR_VPIDS) {
4064 vmx->vpid = vpid;
4065 __set_bit(vpid, vmx_vpid_bitmap);
4066 }
4067 spin_unlock(&vmx_vpid_lock);
4068}
4069
cdbecfc3
LJ		 4070static void free_vpid(struct vcpu_vmx *vmx)
4071{
4072 if (!enable_vpid)
4073 return;
4074 spin_lock(&vmx_vpid_lock);
4075 if (vmx->vpid != 0)
4076 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4077 spin_unlock(&vmx_vpid_lock);
4078}
4079
8d14695f
YZ		 4080#define MSR_TYPE_R 1
4081#define MSR_TYPE_W 2
4082static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4083 u32 msr, int type)
25c5f225 4084{
3e7c73e9 4085 int f = sizeof(unsigned long);
25c5f225
SY		 4086
4087 if (!cpu_has_vmx_msr_bitmap())
4088 return;
4089
4090 /*
4091 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4092 * have the write-low and read-high bitmap offsets the wrong way round.
4093 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4094 */
25c5f225 4095 if (msr <= 0x1fff) {
8d14695f
YZ		 4096 if (type & MSR_TYPE_R)
4097 /* read-low */
4098 __clear_bit(msr, msr_bitmap + 0x000 / f);
4099
4100 if (type & MSR_TYPE_W)
4101 /* write-low */
4102 __clear_bit(msr, msr_bitmap + 0x800 / f);
4103
25c5f225
SY		 4104 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4105 msr &= 0x1fff;
8d14695f
YZ		 4106 if (type & MSR_TYPE_R)
4107 /* read-high */
4108 __clear_bit(msr, msr_bitmap + 0x400 / f);
4109
4110 if (type & MSR_TYPE_W)
4111 /* write-high */
4112 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4113
4114 }
4115}
4116
4117static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4118 u32 msr, int type)
4119{
4120 int f = sizeof(unsigned long);
4121
4122 if (!cpu_has_vmx_msr_bitmap())
4123 return;
4124
4125 /*
4126 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4127 * have the write-low and read-high bitmap offsets the wrong way round.
4128 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4129 */
4130 if (msr <= 0x1fff) {
4131 if (type & MSR_TYPE_R)
4132 /* read-low */
4133 __set_bit(msr, msr_bitmap + 0x000 / f);
4134
4135 if (type & MSR_TYPE_W)
4136 /* write-low */
4137 __set_bit(msr, msr_bitmap + 0x800 / f);
4138
4139 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4140 msr &= 0x1fff;
4141 if (type & MSR_TYPE_R)
4142 /* read-high */
4143 __set_bit(msr, msr_bitmap + 0x400 / f);
4144
4145 if (type & MSR_TYPE_W)
4146 /* write-high */
4147 __set_bit(msr, msr_bitmap + 0xc00 / f);
4148
25c5f225 4149 }
25c5f225
SY		 4150}
4151
5897297b
AK		 4152static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4153{
4154 if (!longmode_only)
8d14695f
YZ		 4155 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4156 msr, MSR_TYPE_R | MSR_TYPE_W);
4157 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4158 msr, MSR_TYPE_R | MSR_TYPE_W);
4159}
4160
4161static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4162{
4163 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4164 msr, MSR_TYPE_R);
4165 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4166 msr, MSR_TYPE_R);
4167}
4168
4169static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4170{
4171 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4172 msr, MSR_TYPE_R);
4173 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4174 msr, MSR_TYPE_R);
4175}
4176
4177static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4178{
4179 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4180 msr, MSR_TYPE_W);
4181 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4182 msr, MSR_TYPE_W);
5897297b
AK		 4183}
4184
01e439be
YZ		 4185static int vmx_vm_has_apicv(struct kvm *kvm)
4186{
4187 return enable_apicv && irqchip_in_kernel(kvm);
4188}
4189
a20ed54d
YZ		 4190/*
4191 * Send interrupt to vcpu via posted interrupt way.
4192 * 1. If target vcpu is running(non-root mode), send posted interrupt
4193 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4194 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4195 * interrupt from PIR in next vmentry.
4196 */
4197static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4198{
4199 struct vcpu_vmx *vmx = to_vmx(vcpu);
4200 int r;
4201
4202 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4203 return;
4204
4205 r = pi_test_and_set_on(&vmx->pi_desc);
4206 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4207#ifdef CONFIG_SMP
a20ed54d
YZ		 4208 if (!r && (vcpu->mode == IN_GUEST_MODE))
4209 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4210 POSTED_INTR_VECTOR);
4211 else
6ffbbbba 4212#endif
a20ed54d
YZ		 4213 kvm_vcpu_kick(vcpu);
4214}
4215
4216static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4217{
4218 struct vcpu_vmx *vmx = to_vmx(vcpu);
4219
4220 if (!pi_test_and_clear_on(&vmx->pi_desc))
4221 return;
4222
4223 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4224}
4225
4226static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4227{
4228 return;
4229}
4230
a3a8ff8e
NHE		 4231/*
4232 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4233 * will not change in the lifetime of the guest.
4234 * Note that host-state that does change is set elsewhere. E.g., host-state
4235 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4236 */
a547c6db 4237static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4238{
4239 u32 low32, high32;
4240 unsigned long tmpl;
4241 struct desc_ptr dt;
4242
b1a74bf8 4243 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4244 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4245 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4246
4247 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4248#ifdef CONFIG_X86_64
4249 /*
4250 * Load null selectors, so we can avoid reloading them in
4251 * __vmx_load_host_state(), in case userspace uses the null selectors
4252 * too (the expected case).
4253 */
4254 vmcs_write16(HOST_DS_SELECTOR, 0);
4255 vmcs_write16(HOST_ES_SELECTOR, 0);
4256#else
a3a8ff8e
NHE		 4257 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4258 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4259#endif
a3a8ff8e
NHE		 4260 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4261 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4262
4263 native_store_idt(&dt);
4264 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4265 vmx->host_idt_base = dt.address;
a3a8ff8e 4266
83287ea4 4267 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4268
4269 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4270 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4271 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4272 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4273
4274 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4275 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4276 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4277 }
4278}
4279
bf8179a0
NHE		 4280static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4281{
4282 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4283 if (enable_ept)
4284 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4285 if (is_guest_mode(&vmx->vcpu))
4286 vmx->vcpu.arch.cr4_guest_owned_bits &=
4287 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4288 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4289}
4290
01e439be
YZ		 4291static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4292{
4293 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4294
4295 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4296 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4297 return pin_based_exec_ctrl;
4298}
4299
bf8179a0
NHE		 4300static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4301{
4302 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4303
4304 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4305 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4306
bf8179a0
NHE		 4307 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4308 exec_control &= ~CPU_BASED_TPR_SHADOW;
4309#ifdef CONFIG_X86_64
4310 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4311 CPU_BASED_CR8_LOAD_EXITING;
4312#endif
4313 }
4314 if (!enable_ept)
4315 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4316 CPU_BASED_CR3_LOAD_EXITING |
4317 CPU_BASED_INVLPG_EXITING;
4318 return exec_control;
4319}
4320
4321static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4322{
4323 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4324 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4325 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4326 if (vmx->vpid == 0)
4327 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4328 if (!enable_ept) {
4329 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4330 enable_unrestricted_guest = 0;
ad756a16
MJ		 4331 /* Enable INVPCID for non-ept guests may cause performance regression. */
4332 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4333 }
4334 if (!enable_unrestricted_guest)
4335 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4336 if (!ple_gap)
4337 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4338 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4339 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4340 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4341 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4342 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4343 (handle_vmptrld).
4344 We can NOT enable shadow_vmcs here because we don't have yet
4345 a current VMCS12
4346 */
4347 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4348 return exec_control;
4349}
4350
ce88decf
XG		 4351static void ept_set_mmio_spte_mask(void)
4352{
4353 /*
4354 * EPT Misconfigurations can be generated if the value of bits 2:0
4355 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4356 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4357 * spte.
4358 */
885032b9 4359 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4360}
4361
6aa8b732
AK		 4362/*
4363 * Sets up the vmcs for emulated real mode.
4364 */
8b9cf98c 4365static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4366{
2e4ce7f5 4367#ifdef CONFIG_X86_64
6aa8b732 4368 unsigned long a;
2e4ce7f5 4369#endif
6aa8b732 4370 int i;
6aa8b732 4371
6aa8b732 4372 /* I/O */
3e7c73e9
AK		 4373 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4374 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4375
4607c2d7
AG		 4376 if (enable_shadow_vmcs) {
4377 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4378 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4379 }
25c5f225 4380 if (cpu_has_vmx_msr_bitmap())
5897297b 4381 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4382
6aa8b732
AK		 4383 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4384
6aa8b732 4385 /* Control */
01e439be 4386 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4387
bf8179a0 4388 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4389
83ff3b9d 4390 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4391 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4392 vmx_secondary_exec_control(vmx));
83ff3b9d 4393 }
f78e0e2e 4394
01e439be 4395 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4396 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4397 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4398 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4399 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4400
4401 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4402
4403 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4404 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4405 }
4406
4b8d54f9
ZE		 4407 if (ple_gap) {
4408 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 4409 vmx->ple_window = ple_window;
4410 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 4411 }
4412
c3707958
XG		 4413 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4414 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4415 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4416
9581d442
AK		 4417 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4418 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4419 vmx_set_constant_host_state(vmx);
05b3e0c2 4420#ifdef CONFIG_X86_64
6aa8b732
AK		 4421 rdmsrl(MSR_FS_BASE, a);
4422 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4423 rdmsrl(MSR_GS_BASE, a);
4424 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4425#else
4426 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4427 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4428#endif
4429
2cc51560
ED		 4430 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4431 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4432 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4433 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4434 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4435
468d472f 4436 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4437 u32 msr_low, msr_high;
4438 u64 host_pat;
468d472f
SY		 4439 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4440 host_pat = msr_low | ((u64) msr_high << 32);
4441 /* Write the default value follow host pat */
4442 vmcs_write64(GUEST_IA32_PAT, host_pat);
4443 /* Keep arch.pat sync with GUEST_IA32_PAT */
4444 vmx->vcpu.arch.pat = host_pat;
4445 }
4446
03916db9 4447 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 4448 u32 index = vmx_msr_index[i];
4449 u32 data_low, data_high;
a2fa3e9f 4450 int j = vmx->nmsrs;
6aa8b732
AK		 4451
4452 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4453 continue;
432bd6cb
AK		 4454 if (wrmsr_safe(index, data_low, data_high) < 0)
4455 continue;
26bb0981
AK		 4456 vmx->guest_msrs[j].index = i;
4457 vmx->guest_msrs[j].data = 0;
d5696725 4458 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4459 ++vmx->nmsrs;
6aa8b732 4460 }
6aa8b732 4461
2961e876
GN		 4462
4463 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4464
4465 /* 22.2.1, 20.8.1 */
2961e876 4466 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4467
e00c8cf2 4468 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4469 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4470
4471 return 0;
4472}
4473
57f252f2 4474static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4475{
4476 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4477 struct msr_data apic_base_msr;
e00c8cf2 4478
7ffd92c5 4479 vmx->rmode.vm86_active = 0;
e00c8cf2 4480
3b86cd99
JK		 4481 vmx->soft_vnmi_blocked = 0;
4482
ad312c7c 4483 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4484 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4485 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4486 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4487 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4488 apic_base_msr.host_initiated = true;
4489 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4490
2fb92db1
AK		 4491 vmx_segment_cache_clear(vmx);
4492
5706be0d 4493 seg_setup(VCPU_SREG_CS);
66450a21 4494 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4495 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4496
4497 seg_setup(VCPU_SREG_DS);
4498 seg_setup(VCPU_SREG_ES);
4499 seg_setup(VCPU_SREG_FS);
4500 seg_setup(VCPU_SREG_GS);
4501 seg_setup(VCPU_SREG_SS);
4502
4503 vmcs_write16(GUEST_TR_SELECTOR, 0);
4504 vmcs_writel(GUEST_TR_BASE, 0);
4505 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4506 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4507
4508 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4509 vmcs_writel(GUEST_LDTR_BASE, 0);
4510 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4511 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4512
4513 vmcs_write32(GUEST_SYSENTER_CS, 0);
4514 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4515 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4516
4517 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4518 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4519
e00c8cf2
AK		 4520 vmcs_writel(GUEST_GDTR_BASE, 0);
4521 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4522
4523 vmcs_writel(GUEST_IDTR_BASE, 0);
4524 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4525
443381a8 4526 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4527 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4528 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4529
e00c8cf2
AK		 4530 /* Special registers */
4531 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4532
4533 setup_msrs(vmx);
4534
6aa8b732
AK		 4535 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4536
f78e0e2e
SY		 4537 if (cpu_has_vmx_tpr_shadow()) {
4538 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4539 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4540 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4541 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4542 vmcs_write32(TPR_THRESHOLD, 0);
4543 }
4544
4545 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4546 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4547 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4548
01e439be
YZ		 4549 if (vmx_vm_has_apicv(vcpu->kvm))
4550 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4551
2384d2b3
SY		 4552 if (vmx->vpid != 0)
4553 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4554
fa40052c 4555 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4556 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4557 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4558 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4559 vmx_fpu_activate(&vmx->vcpu);
4560 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4561
b9d762fa 4562 vpid_sync_context(vmx);
6aa8b732
AK		 4563}
4564
b6f1250e
NHE		 4565/*
4566 * In nested virtualization, check if L1 asked to exit on external interrupts.
4567 * For most existing hypervisors, this will always return true.
4568 */
4569static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4570{
4571 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4572 PIN_BASED_EXT_INTR_MASK;
4573}
4574
77b0f5d6
BD		 4575/*
4576 * In nested virtualization, check if L1 has set
4577 * VM_EXIT_ACK_INTR_ON_EXIT
4578 */
4579static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4580{
4581 return get_vmcs12(vcpu)->vm_exit_controls &
4582 VM_EXIT_ACK_INTR_ON_EXIT;
4583}
4584
ea8ceb83
JK		 4585static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4586{
4587 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4588 PIN_BASED_NMI_EXITING;
4589}
4590
c9a7953f 4591static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4592{
4593 u32 cpu_based_vm_exec_control;
730dca42 4594
3b86cd99
JK		 4595 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4596 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4597 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4598}
4599
c9a7953f 4600static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4601{
4602 u32 cpu_based_vm_exec_control;
4603
c9a7953f
JK		 4604 if (!cpu_has_virtual_nmis() ||
4605 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4606 enable_irq_window(vcpu);
4607 return;
4608 }
3b86cd99
JK		 4609
4610 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4611 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4612 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4613}
4614
66fd3f7f 4615static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4616{
9c8cba37 4617 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4618 uint32_t intr;
4619 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4620
229456fc 4621 trace_kvm_inj_virq(irq);
2714d1d3 4622
fa89a817 4623 ++vcpu->stat.irq_injections;
7ffd92c5 4624 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4625 int inc_eip = 0;
4626 if (vcpu->arch.interrupt.soft)
4627 inc_eip = vcpu->arch.event_exit_inst_len;
4628 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4629 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4630 return;
4631 }
66fd3f7f
GN		 4632 intr = irq | INTR_INFO_VALID_MASK;
4633 if (vcpu->arch.interrupt.soft) {
4634 intr |= INTR_TYPE_SOFT_INTR;
4635 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4636 vmx->vcpu.arch.event_exit_inst_len);
4637 } else
4638 intr |= INTR_TYPE_EXT_INTR;
4639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4640}
4641
f08864b4
SY		 4642static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4643{
66a5a347
JK		 4644 struct vcpu_vmx *vmx = to_vmx(vcpu);
4645
0b6ac343
NHE		 4646 if (is_guest_mode(vcpu))
4647 return;
4648
3b86cd99
JK		 4649 if (!cpu_has_virtual_nmis()) {
4650 /*
4651 * Tracking the NMI-blocked state in software is built upon
4652 * finding the next open IRQ window. This, in turn, depends on
4653 * well-behaving guests: They have to keep IRQs disabled at
4654 * least as long as the NMI handler runs. Otherwise we may
4655 * cause NMI nesting, maybe breaking the guest. But as this is
4656 * highly unlikely, we can live with the residual risk.
4657 */
4658 vmx->soft_vnmi_blocked = 1;
4659 vmx->vnmi_blocked_time = 0;
4660 }
4661
487b391d 4662 ++vcpu->stat.nmi_injections;
9d58b931 4663 vmx->nmi_known_unmasked = false;
7ffd92c5 4664 if (vmx->rmode.vm86_active) {
71f9833b 4665 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4666 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4667 return;
4668 }
f08864b4
SY		 4669 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4670 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4671}
4672
3cfc3092
JK		 4673static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4674{
4675 if (!cpu_has_virtual_nmis())
4676 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4677 if (to_vmx(vcpu)->nmi_known_unmasked)
4678 return false;
c332c83a 4679 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4680}
4681
4682static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4683{
4684 struct vcpu_vmx *vmx = to_vmx(vcpu);
4685
4686 if (!cpu_has_virtual_nmis()) {
4687 if (vmx->soft_vnmi_blocked != masked) {
4688 vmx->soft_vnmi_blocked = masked;
4689 vmx->vnmi_blocked_time = 0;
4690 }
4691 } else {
9d58b931 4692 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4693 if (masked)
4694 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4695 GUEST_INTR_STATE_NMI);
4696 else
4697 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4698 GUEST_INTR_STATE_NMI);
4699 }
4700}
4701
2505dc9f
JK		 4702static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4703{
b6b8a145
JK		 4704 if (to_vmx(vcpu)->nested.nested_run_pending)
4705 return 0;
ea8ceb83 4706
2505dc9f
JK		 4707 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4708 return 0;
4709
4710 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4711 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4712 | GUEST_INTR_STATE_NMI));
4713}
4714
78646121
GN		 4715static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4716{
b6b8a145
JK		 4717 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4718 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4719 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4720 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4721}
4722
cbc94022
IE		 4723static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4724{
4725 int ret;
4726 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4727 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4728 .guest_phys_addr = addr,
4729 .memory_size = PAGE_SIZE * 3,
4730 .flags = 0,
4731 };
4732
47ae31e2 4733 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4734 if (ret)
4735 return ret;
bfc6d222 4736 kvm->arch.tss_addr = addr;
93ea5388
GN		 4737 if (!init_rmode_tss(kvm))
4738 return -ENOMEM;
4739
cbc94022
IE		 4740 return 0;
4741}
4742
0ca1b4f4 4743static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4744{
77ab6db0 4745 switch (vec) {
77ab6db0 4746 case BP_VECTOR:
c573cd22
JK		 4747 /*
4748 * Update instruction length as we may reinject the exception
4749 * from user space while in guest debugging mode.
4750 */
4751 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4752 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4753 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4754 return false;
4755 /* fall through */
4756 case DB_VECTOR:
4757 if (vcpu->guest_debug &
4758 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4759 return false;
d0bfb940
JK		 4760 /* fall through */
4761 case DE_VECTOR:
77ab6db0
JK		 4762 case OF_VECTOR:
4763 case BR_VECTOR:
4764 case UD_VECTOR:
4765 case DF_VECTOR:
4766 case SS_VECTOR:
4767 case GP_VECTOR:
4768 case MF_VECTOR:
0ca1b4f4
GN		 4769 return true;
4770 break;
77ab6db0 4771 }
0ca1b4f4
GN		 4772 return false;
4773}
4774
4775static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4776 int vec, u32 err_code)
4777{
4778 /*
4779 * Instruction with address size override prefix opcode 0x67
4780 * Cause the #SS fault with 0 error code in VM86 mode.
4781 */
4782 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4783 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4784 if (vcpu->arch.halt_request) {
4785 vcpu->arch.halt_request = 0;
4786 return kvm_emulate_halt(vcpu);
4787 }
4788 return 1;
4789 }
4790 return 0;
4791 }
4792
4793 /*
4794 * Forward all other exceptions that are valid in real mode.
4795 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4796 * the required debugging infrastructure rework.
4797 */
4798 kvm_queue_exception(vcpu, vec);
4799 return 1;
6aa8b732
AK		 4800}
4801
a0861c02
AK		 4802/*
4803 * Trigger machine check on the host. We assume all the MSRs are already set up
4804 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4805 * We pass a fake environment to the machine check handler because we want
4806 * the guest to be always treated like user space, no matter what context
4807 * it used internally.
4808 */
4809static void kvm_machine_check(void)
4810{
4811#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4812 struct pt_regs regs = {
4813 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4814 .flags = X86_EFLAGS_IF,
4815 };
4816
4817 do_machine_check(&regs, 0);
4818#endif
4819}
4820
851ba692 4821static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4822{
4823 /* already handled by vcpu_run */
4824 return 1;
4825}
4826
851ba692 4827static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4828{
1155f76a 4829 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4830 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4831 u32 intr_info, ex_no, error_code;
42dbaa5a 4832 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4833 u32 vect_info;
4834 enum emulation_result er;
4835
1155f76a 4836 vect_info = vmx->idt_vectoring_info;
88786475 4837 intr_info = vmx->exit_intr_info;
6aa8b732 4838
a0861c02 4839 if (is_machine_check(intr_info))
851ba692 4840 return handle_machine_check(vcpu);
a0861c02 4841
e4a41889 4842 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4843 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4844
4845 if (is_no_device(intr_info)) {
5fd86fcf 4846 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4847 return 1;
4848 }
4849
7aa81cc0 4850 if (is_invalid_opcode(intr_info)) {
51d8b661 4851 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4852 if (er != EMULATE_DONE)
7ee5d940 4853 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4854 return 1;
4855 }
4856
6aa8b732 4857 error_code = 0;
2e11384c 4858 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4859 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4860
4861 /*
4862 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4863 * MMIO, it is better to report an internal error.
4864 * See the comments in vmx_handle_exit.
4865 */
4866 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4867 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4868 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4869 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4870 vcpu->run->internal.ndata = 2;
4871 vcpu->run->internal.data[0] = vect_info;
4872 vcpu->run->internal.data[1] = intr_info;
4873 return 0;
4874 }
4875
6aa8b732 4876 if (is_page_fault(intr_info)) {
1439442c 4877 /* EPT won't cause page fault directly */
cf3ace79 4878 BUG_ON(enable_ept);
6aa8b732 4879 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4880 trace_kvm_page_fault(cr2, error_code);
4881
3298b75c 4882 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4883 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4884 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4885 }
4886
d0bfb940 4887 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4888
4889 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4890 return handle_rmode_exception(vcpu, ex_no, error_code);
4891
42dbaa5a
JK		 4892 switch (ex_no) {
4893 case DB_VECTOR:
4894 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4895 if (!(vcpu->guest_debug &
4896 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4897 vcpu->arch.dr6 &= ~15;
6f43ed01 4898 vcpu->arch.dr6 |= dr6 | DR6_RTM;
fd2a445a
HD		 4899 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4900 skip_emulated_instruction(vcpu);
4901
42dbaa5a
JK		 4902 kvm_queue_exception(vcpu, DB_VECTOR);
4903 return 1;
4904 }
4905 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4906 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4907 /* fall through */
4908 case BP_VECTOR:
c573cd22
JK		 4909 /*
4910 * Update instruction length as we may reinject #BP from
4911 * user space while in guest debugging mode. Reading it for
4912 * #DB as well causes no harm, it is not used in that case.
4913 */
4914 vmx->vcpu.arch.event_exit_inst_len =
4915 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4916 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4917 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4918 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4919 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4920 break;
4921 default:
d0bfb940
JK		 4922 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4923 kvm_run->ex.exception = ex_no;
4924 kvm_run->ex.error_code = error_code;
42dbaa5a 4925 break;
6aa8b732 4926 }
6aa8b732
AK		 4927 return 0;
4928}
4929
851ba692 4930static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4931{
1165f5fe 4932 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4933 return 1;
4934}
4935
851ba692 4936static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4937{
851ba692 4938 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4939 return 0;
4940}
6aa8b732 4941
851ba692 4942static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4943{
bfdaab09 4944 unsigned long exit_qualification;
34c33d16 4945 int size, in, string;
039576c0 4946 unsigned port;
6aa8b732 4947
bfdaab09 4948 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4949 string = (exit_qualification & 16) != 0;
cf8f70bf 4950 in = (exit_qualification & 8) != 0;
e70669ab 4951
cf8f70bf 4952 ++vcpu->stat.io_exits;
e70669ab 4953
cf8f70bf 4954 if (string || in)
51d8b661 4955 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4956
cf8f70bf
GN		 4957 port = exit_qualification >> 16;
4958 size = (exit_qualification & 7) + 1;
e93f36bc 4959 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4960
4961 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4962}
4963
102d8325
IM		 4964static void
4965vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4966{
4967 /*
4968 * Patch in the VMCALL instruction:
4969 */
4970 hypercall[0] = 0x0f;
4971 hypercall[1] = 0x01;
4972 hypercall[2] = 0xc1;
102d8325
IM		 4973}
4974
92fbc7b1
JK		 4975static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4976{
4977 unsigned long always_on = VMXON_CR0_ALWAYSON;
4978
4979 if (nested_vmx_secondary_ctls_high &
4980 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4981 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4982 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4983 return (val & always_on) == always_on;
4984}
4985
0fa06071 4986/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4987static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4988{
eeadf9e7 4989 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4991 unsigned long orig_val = val;
4992
eeadf9e7
NHE		 4993 /*
4994 * We get here when L2 changed cr0 in a way that did not change
4995 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4996 * but did change L0 shadowed bits. So we first calculate the
4997 * effective cr0 value that L1 would like to write into the
4998 * hardware. It consists of the L2-owned bits from the new
4999 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 5000 */
1a0d74e6
JK		 5001 val = (val & ~vmcs12->cr0_guest_host_mask) |
5002 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5003
92fbc7b1 5004 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5005 return 1;
1a0d74e6
JK		 5006
5007 if (kvm_set_cr0(vcpu, val))
5008 return 1;
5009 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5010 return 0;
1a0d74e6
JK		 5011 } else {
5012 if (to_vmx(vcpu)->nested.vmxon &&
5013 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5014 return 1;
eeadf9e7 5015 return kvm_set_cr0(vcpu, val);
1a0d74e6 5016 }
eeadf9e7
NHE		 5017}
5018
5019static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5020{
5021 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5022 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5023 unsigned long orig_val = val;
5024
5025 /* analogously to handle_set_cr0 */
5026 val = (val & ~vmcs12->cr4_guest_host_mask) |
5027 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5028 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5029 return 1;
1a0d74e6 5030 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5031 return 0;
5032 } else
5033 return kvm_set_cr4(vcpu, val);
5034}
5035
5036/* called to set cr0 as approriate for clts instruction exit. */
5037static void handle_clts(struct kvm_vcpu *vcpu)
5038{
5039 if (is_guest_mode(vcpu)) {
5040 /*
5041 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5042 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5043 * just pretend it's off (also in arch.cr0 for fpu_activate).
5044 */
5045 vmcs_writel(CR0_READ_SHADOW,
5046 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5047 vcpu->arch.cr0 &= ~X86_CR0_TS;
5048 } else
5049 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5050}
5051
851ba692 5052static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5053{
229456fc 5054 unsigned long exit_qualification, val;
6aa8b732
AK		 5055 int cr;
5056 int reg;
49a9b07e 5057 int err;
6aa8b732 5058
bfdaab09 5059 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5060 cr = exit_qualification & 15;
5061 reg = (exit_qualification >> 8) & 15;
5062 switch ((exit_qualification >> 4) & 3) {
5063 case 0: /* mov to cr */
1e32c079 5064 val = kvm_register_readl(vcpu, reg);
229456fc 5065 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5066 switch (cr) {
5067 case 0:
eeadf9e7 5068 err = handle_set_cr0(vcpu, val);
db8fcefa 5069 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5070 return 1;
5071 case 3:
2390218b 5072 err = kvm_set_cr3(vcpu, val);
db8fcefa 5073 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5074 return 1;
5075 case 4:
eeadf9e7 5076 err = handle_set_cr4(vcpu, val);
db8fcefa 5077 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5078 return 1;
0a5fff19
GN		 5079 case 8: {
5080 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 5081 u8 cr8 = (u8)val;
eea1cff9 5082 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5083 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5084 if (irqchip_in_kernel(vcpu->kvm))
5085 return 1;
5086 if (cr8_prev <= cr8)
5087 return 1;
851ba692 5088 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5089 return 0;
5090 }
4b8073e4 5091 }
6aa8b732 5092 break;
25c4c276 5093 case 2: /* clts */
eeadf9e7 5094 handle_clts(vcpu);
4d4ec087 5095 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5096 skip_emulated_instruction(vcpu);
6b52d186 5097 vmx_fpu_activate(vcpu);
25c4c276 5098 return 1;
6aa8b732
AK		 5099 case 1: /*mov from cr*/
5100 switch (cr) {
5101 case 3:
9f8fe504
AK		 5102 val = kvm_read_cr3(vcpu);
5103 kvm_register_write(vcpu, reg, val);
5104 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5105 skip_emulated_instruction(vcpu);
5106 return 1;
5107 case 8:
229456fc
MT		 5108 val = kvm_get_cr8(vcpu);
5109 kvm_register_write(vcpu, reg, val);
5110 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5111 skip_emulated_instruction(vcpu);
5112 return 1;
5113 }
5114 break;
5115 case 3: /* lmsw */
a1f83a74 5116 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5117 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5118 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5119
5120 skip_emulated_instruction(vcpu);
5121 return 1;
5122 default:
5123 break;
5124 }
851ba692 5125 vcpu->run->exit_reason = 0;
a737f256 5126 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5127 (int)(exit_qualification >> 4) & 3, cr);
5128 return 0;
5129}
5130
851ba692 5131static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5132{
bfdaab09 5133 unsigned long exit_qualification;
6aa8b732
AK		 5134 int dr, reg;
5135
f2483415 5136 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5137 if (!kvm_require_cpl(vcpu, 0))
5138 return 1;
42dbaa5a
JK		 5139 dr = vmcs_readl(GUEST_DR7);
5140 if (dr & DR7_GD) {
5141 /*
5142 * As the vm-exit takes precedence over the debug trap, we
5143 * need to emulate the latter, either for the host or the
5144 * guest debugging itself.
5145 */
5146 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5147 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5148 vcpu->run->debug.arch.dr7 = dr;
5149 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5150 vmcs_readl(GUEST_CS_BASE) +
5151 vmcs_readl(GUEST_RIP);
851ba692
AK		 5152 vcpu->run->debug.arch.exception = DB_VECTOR;
5153 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5154 return 0;
5155 } else {
5156 vcpu->arch.dr7 &= ~DR7_GD;
6f43ed01 5157 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 5158 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5159 kvm_queue_exception(vcpu, DB_VECTOR);
5160 return 1;
5161 }
5162 }
5163
81908bf4
PB		 5164 if (vcpu->guest_debug == 0) {
5165 u32 cpu_based_vm_exec_control;
5166
5167 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5168 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5170
5171 /*
5172 * No more DR vmexits; force a reload of the debug registers
5173 * and reenter on this instruction. The next vmexit will
5174 * retrieve the full state of the debug registers.
5175 */
5176 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5177 return 1;
5178 }
5179
bfdaab09 5180 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5181 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5182 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5183 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5184 unsigned long val;
4c4d563b
JK		 5185
5186 if (kvm_get_dr(vcpu, dr, &val))
5187 return 1;
5188 kvm_register_write(vcpu, reg, val);
020df079 5189 } else
5777392e 5190 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 5191 return 1;
5192
6aa8b732
AK		 5193 skip_emulated_instruction(vcpu);
5194 return 1;
5195}
5196
73aaf249
JK		 5197static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5198{
5199 return vcpu->arch.dr6;
5200}
5201
5202static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5203{
5204}
5205
81908bf4
PB		 5206static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5207{
5208 u32 cpu_based_vm_exec_control;
5209
5210 get_debugreg(vcpu->arch.db[0], 0);
5211 get_debugreg(vcpu->arch.db[1], 1);
5212 get_debugreg(vcpu->arch.db[2], 2);
5213 get_debugreg(vcpu->arch.db[3], 3);
5214 get_debugreg(vcpu->arch.dr6, 6);
5215 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5216
5217 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5218
5219 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5220 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5221 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5222}
5223
020df079
GN		 5224static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5225{
5226 vmcs_writel(GUEST_DR7, val);
5227}
5228
851ba692 5229static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5230{
06465c5a
AK		 5231 kvm_emulate_cpuid(vcpu);
5232 return 1;
6aa8b732
AK		 5233}
5234
851ba692 5235static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5236{
ad312c7c 5237 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5238 u64 data;
5239
5240 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5241 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5242 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5243 return 1;
5244 }
5245
229456fc 5246 trace_kvm_msr_read(ecx, data);
2714d1d3 5247
6aa8b732 5248 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5249 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5250 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5251 skip_emulated_instruction(vcpu);
5252 return 1;
5253}
5254
851ba692 5255static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5256{
8fe8ab46 5257 struct msr_data msr;
ad312c7c
ZX		 5258 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5259 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5260 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5261
8fe8ab46
WA		 5262 msr.data = data;
5263 msr.index = ecx;
5264 msr.host_initiated = false;
5265 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5266 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5267 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5268 return 1;
5269 }
5270
59200273 5271 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5272 skip_emulated_instruction(vcpu);
5273 return 1;
5274}
5275
851ba692 5276static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5277{
3842d135 5278 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5279 return 1;
5280}
5281
851ba692 5282static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5283{
85f455f7
ED		 5284 u32 cpu_based_vm_exec_control;
5285
5286 /* clear pending irq */
5287 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5288 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5289 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5290
3842d135
AK		 5291 kvm_make_request(KVM_REQ_EVENT, vcpu);
5292
a26bf12a 5293 ++vcpu->stat.irq_window_exits;
2714d1d3 5294
c1150d8c
DL		 5295 /*
5296 * If the user space waits to inject interrupts, exit as soon as
5297 * possible
5298 */
8061823a 5299 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5300 vcpu->run->request_interrupt_window &&
8061823a 5301 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5302 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5303 return 0;
5304 }
6aa8b732
AK		 5305 return 1;
5306}
5307
851ba692 5308static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5309{
5310 skip_emulated_instruction(vcpu);
d3bef15f 5311 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5312}
5313
851ba692 5314static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5315{
510043da 5316 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5317 kvm_emulate_hypercall(vcpu);
5318 return 1;
c21415e8
IM		 5319}
5320
ec25d5e6
GN		 5321static int handle_invd(struct kvm_vcpu *vcpu)
5322{
51d8b661 5323 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5324}
5325
851ba692 5326static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5327{
f9c617f6 5328 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5329
5330 kvm_mmu_invlpg(vcpu, exit_qualification);
5331 skip_emulated_instruction(vcpu);
5332 return 1;
5333}
5334
fee84b07
AK		 5335static int handle_rdpmc(struct kvm_vcpu *vcpu)
5336{
5337 int err;
5338
5339 err = kvm_rdpmc(vcpu);
5340 kvm_complete_insn_gp(vcpu, err);
5341
5342 return 1;
5343}
5344
851ba692 5345static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5346{
5347 skip_emulated_instruction(vcpu);
f5f48ee1 5348 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5349 return 1;
5350}
5351
2acf923e
DC		 5352static int handle_xsetbv(struct kvm_vcpu *vcpu)
5353{
5354 u64 new_bv = kvm_read_edx_eax(vcpu);
5355 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5356
5357 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5358 skip_emulated_instruction(vcpu);
5359 return 1;
5360}
5361
851ba692 5362static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5363{
58fbbf26
KT		 5364 if (likely(fasteoi)) {
5365 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5366 int access_type, offset;
5367
5368 access_type = exit_qualification & APIC_ACCESS_TYPE;
5369 offset = exit_qualification & APIC_ACCESS_OFFSET;
5370 /*
5371 * Sane guest uses MOV to write EOI, with written value
5372 * not cared. So make a short-circuit here by avoiding
5373 * heavy instruction emulation.
5374 */
5375 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5376 (offset == APIC_EOI)) {
5377 kvm_lapic_set_eoi(vcpu);
5378 skip_emulated_instruction(vcpu);
5379 return 1;
5380 }
5381 }
51d8b661 5382 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5383}
5384
c7c9c56c
YZ		 5385static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5386{
5387 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5388 int vector = exit_qualification & 0xff;
5389
5390 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5391 kvm_apic_set_eoi_accelerated(vcpu, vector);
5392 return 1;
5393}
5394
83d4c286
YZ		 5395static int handle_apic_write(struct kvm_vcpu *vcpu)
5396{
5397 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5398 u32 offset = exit_qualification & 0xfff;
5399
5400 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5401 kvm_apic_write_nodecode(vcpu, offset);
5402 return 1;
5403}
5404
851ba692 5405static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5406{
60637aac 5407 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5408 unsigned long exit_qualification;
e269fb21
JK		 5409 bool has_error_code = false;
5410 u32 error_code = 0;
37817f29 5411 u16 tss_selector;
7f3d35fd 5412 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5413
5414 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5415 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5416 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5417
5418 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5419
5420 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5421 if (reason == TASK_SWITCH_GATE && idt_v) {
5422 switch (type) {
5423 case INTR_TYPE_NMI_INTR:
5424 vcpu->arch.nmi_injected = false;
654f06fc 5425 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5426 break;
5427 case INTR_TYPE_EXT_INTR:
66fd3f7f 5428 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5429 kvm_clear_interrupt_queue(vcpu);
5430 break;
5431 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5432 if (vmx->idt_vectoring_info &
5433 VECTORING_INFO_DELIVER_CODE_MASK) {
5434 has_error_code = true;
5435 error_code =
5436 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5437 }
5438 /* fall through */
64a7ec06
GN		 5439 case INTR_TYPE_SOFT_EXCEPTION:
5440 kvm_clear_exception_queue(vcpu);
5441 break;
5442 default:
5443 break;
5444 }
60637aac 5445 }
37817f29
IE		 5446 tss_selector = exit_qualification;
5447
64a7ec06
GN		 5448 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5449 type != INTR_TYPE_EXT_INTR &&
5450 type != INTR_TYPE_NMI_INTR))
5451 skip_emulated_instruction(vcpu);
5452
7f3d35fd
KW		 5453 if (kvm_task_switch(vcpu, tss_selector,
5454 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5455 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5456 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5457 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5458 vcpu->run->internal.ndata = 0;
42dbaa5a 5459 return 0;
acb54517 5460 }
42dbaa5a
JK		 5461
5462 /* clear all local breakpoint enable flags */
1f854112 5463 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5464
5465 /*
5466 * TODO: What about debug traps on tss switch?
5467 * Are we supposed to inject them and update dr6?
5468 */
5469
5470 return 1;
37817f29
IE		 5471}
5472
851ba692 5473static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5474{
f9c617f6 5475 unsigned long exit_qualification;
1439442c 5476 gpa_t gpa;
4f5982a5 5477 u32 error_code;
1439442c 5478 int gla_validity;
1439442c 5479
f9c617f6 5480 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5481
1439442c
SY		 5482 gla_validity = (exit_qualification >> 7) & 0x3;
5483 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5484 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5485 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5486 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5487 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5488 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5489 (long unsigned int)exit_qualification);
851ba692
AK		 5490 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5491 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5492 return 0;
1439442c
SY		 5493 }
5494
0be9c7a8
GN		 5495 /*
5496 * EPT violation happened while executing iret from NMI,
5497 * "blocked by NMI" bit has to be set before next VM entry.
5498 * There are errata that may cause this bit to not be set:
5499 * AAK134, BY25.
5500 */
bcd1c294
GN		 5501 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5502 cpu_has_virtual_nmis() &&
5503 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5504 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5505
1439442c 5506 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5507 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5508
5509 /* It is a write fault? */
5510 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5511 /* It is a fetch fault? */
5512 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5513 /* ept page table is present? */
5514 error_code |= (exit_qualification >> 3) & 0x1;
5515
25d92081
YZ		 5516 vcpu->arch.exit_qualification = exit_qualification;
5517
4f5982a5 5518 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5519}
5520
68f89400
MT		 5521static u64 ept_rsvd_mask(u64 spte, int level)
5522{
5523 int i;
5524 u64 mask = 0;
5525
5526 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5527 mask |= (1ULL << i);
5528
a32e8459 5529 if (level == 4)
68f89400
MT		 5530 /* bits 7:3 reserved */
5531 mask |= 0xf8;
a32e8459
WL		 5532 else if (spte & (1ULL << 7))
5533 /*
5534 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5535 * level == 1 if the hypervisor is using the ignored bit 7.
5536 */
5537 mask |= (PAGE_SIZE << ((level - 1) * 9)) - PAGE_SIZE;
5538 else if (level > 1)
5539 /* bits 6:3 reserved */
5540 mask |= 0x78;
68f89400
MT		 5541
5542 return mask;
5543}
5544
5545static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5546 int level)
5547{
5548 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5549
5550 /* 010b (write-only) */
5551 WARN_ON((spte & 0x7) == 0x2);
5552
5553 /* 110b (write/execute) */
5554 WARN_ON((spte & 0x7) == 0x6);
5555
5556 /* 100b (execute-only) and value not supported by logical processor */
5557 if (!cpu_has_vmx_ept_execute_only())
5558 WARN_ON((spte & 0x7) == 0x4);
5559
5560 /* not 000b */
5561 if ((spte & 0x7)) {
5562 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5563
5564 if (rsvd_bits != 0) {
5565 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5566 __func__, rsvd_bits);
5567 WARN_ON(1);
5568 }
5569
a32e8459
WL		 5570 /* bits 5:3 are _not_ reserved for large page or leaf page */
5571 if ((rsvd_bits & 0x38) == 0) {
68f89400
MT		 5572 u64 ept_mem_type = (spte & 0x38) >> 3;
5573
5574 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5575 ept_mem_type == 7) {
5576 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5577 __func__, ept_mem_type);
5578 WARN_ON(1);
5579 }
5580 }
5581 }
5582}
5583
851ba692 5584static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5585{
5586 u64 sptes[4];
ce88decf 5587 int nr_sptes, i, ret;
68f89400
MT		 5588 gpa_t gpa;
5589
5590 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5591 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5592 skip_emulated_instruction(vcpu);
5593 return 1;
5594 }
68f89400 5595
ce88decf 5596 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5597 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5598 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5599 EMULATE_DONE;
f8f55942
XG		 5600
5601 if (unlikely(ret == RET_MMIO_PF_INVALID))
5602 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5603
b37fbea6 5604 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5605 return 1;
5606
5607 /* It is the real ept misconfig */
68f89400
MT		 5608 printk(KERN_ERR "EPT: Misconfiguration.\n");
5609 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5610
5611 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5612
5613 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5614 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5615
851ba692
AK		 5616 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5617 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5618
5619 return 0;
5620}
5621
851ba692 5622static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5623{
5624 u32 cpu_based_vm_exec_control;
5625
5626 /* clear pending NMI */
5627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5628 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5630 ++vcpu->stat.nmi_window_exits;
3842d135 5631 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5632
5633 return 1;
5634}
5635
80ced186 5636static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5637{
8b3079a5
AK		 5638 struct vcpu_vmx *vmx = to_vmx(vcpu);
5639 enum emulation_result err = EMULATE_DONE;
80ced186 5640 int ret = 1;
49e9d557
AK		 5641 u32 cpu_exec_ctrl;
5642 bool intr_window_requested;
b8405c18 5643 unsigned count = 130;
49e9d557
AK		 5644
5645 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5646 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5647
98eb2f8b 5648 while (vmx->emulation_required && count-- != 0) {
bdea48e3 5649 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5650 return handle_interrupt_window(&vmx->vcpu);
5651
de87dcdd
AK		 5652 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5653 return 1;
5654
991eebf9 5655 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5656
ac0a48c3 5657 if (err == EMULATE_USER_EXIT) {
94452b9e 5658 ++vcpu->stat.mmio_exits;
80ced186
MG		 5659 ret = 0;
5660 goto out;
5661 }
1d5a4d9b 5662
de5f70e0
AK		 5663 if (err != EMULATE_DONE) {
5664 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5665 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5666 vcpu->run->internal.ndata = 0;
6d77dbfc 5667 return 0;
de5f70e0 5668 }
ea953ef0 5669
8d76c49e
GN		 5670 if (vcpu->arch.halt_request) {
5671 vcpu->arch.halt_request = 0;
5672 ret = kvm_emulate_halt(vcpu);
5673 goto out;
5674 }
5675
ea953ef0 5676 if (signal_pending(current))
80ced186 5677 goto out;
ea953ef0
MG		 5678 if (need_resched())
5679 schedule();
5680 }
5681
80ced186
MG		 5682out:
5683 return ret;
ea953ef0
MG		 5684}
5685
4b8d54f9
ZE		 5686/*
5687 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5688 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5689 */
9fb41ba8 5690static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5691{
5692 skip_emulated_instruction(vcpu);
5693 kvm_vcpu_on_spin(vcpu);
5694
5695 return 1;
5696}
5697
87c00572 5698static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5699{
87c00572 5700 skip_emulated_instruction(vcpu);
59708670
SY		 5701 return 1;
5702}
5703
87c00572
GS		 5704static int handle_mwait(struct kvm_vcpu *vcpu)
5705{
5706 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5707 return handle_nop(vcpu);
5708}
5709
5710static int handle_monitor(struct kvm_vcpu *vcpu)
5711{
5712 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5713 return handle_nop(vcpu);
5714}
5715
ff2f6fe9
NHE		 5716/*
5717 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5718 * We could reuse a single VMCS for all the L2 guests, but we also want the
5719 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5720 * allows keeping them loaded on the processor, and in the future will allow
5721 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5722 * every entry if they never change.
5723 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5724 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5725 *
5726 * The following functions allocate and free a vmcs02 in this pool.
5727 */
5728
5729/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5730static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5731{
5732 struct vmcs02_list *item;
5733 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5734 if (item->vmptr == vmx->nested.current_vmptr) {
5735 list_move(&item->list, &vmx->nested.vmcs02_pool);
5736 return &item->vmcs02;
5737 }
5738
5739 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5740 /* Recycle the least recently used VMCS. */
5741 item = list_entry(vmx->nested.vmcs02_pool.prev,
5742 struct vmcs02_list, list);
5743 item->vmptr = vmx->nested.current_vmptr;
5744 list_move(&item->list, &vmx->nested.vmcs02_pool);
5745 return &item->vmcs02;
5746 }
5747
5748 /* Create a new VMCS */
0fa24ce3 5749 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5750 if (!item)
5751 return NULL;
5752 item->vmcs02.vmcs = alloc_vmcs();
5753 if (!item->vmcs02.vmcs) {
5754 kfree(item);
5755 return NULL;
5756 }
5757 loaded_vmcs_init(&item->vmcs02);
5758 item->vmptr = vmx->nested.current_vmptr;
5759 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5760 vmx->nested.vmcs02_num++;
5761 return &item->vmcs02;
5762}
5763
5764/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5765static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5766{
5767 struct vmcs02_list *item;
5768 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5769 if (item->vmptr == vmptr) {
5770 free_loaded_vmcs(&item->vmcs02);
5771 list_del(&item->list);
5772 kfree(item);
5773 vmx->nested.vmcs02_num--;
5774 return;
5775 }
5776}
5777
5778/*
5779 * Free all VMCSs saved for this vcpu, except the one pointed by
4fa7734c
PB		 5780 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
5781 * must be &vmx->vmcs01.
ff2f6fe9
NHE		 5782 */
5783static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5784{
5785 struct vmcs02_list *item, *n;
4fa7734c
PB		 5786
5787 WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
ff2f6fe9 5788 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4fa7734c
PB		 5789 /*
5790 * Something will leak if the above WARN triggers. Better than
5791 * a use-after-free.
5792 */
5793 if (vmx->loaded_vmcs == &item->vmcs02)
5794 continue;
5795
5796 free_loaded_vmcs(&item->vmcs02);
ff2f6fe9
NHE		 5797 list_del(&item->list);
5798 kfree(item);
4fa7734c 5799 vmx->nested.vmcs02_num--;
ff2f6fe9 5800 }
ff2f6fe9
NHE		 5801}
5802
0658fbaa
ACL		 5803/*
5804 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5805 * set the success or error code of an emulated VMX instruction, as specified
5806 * by Vol 2B, VMX Instruction Reference, "Conventions".
5807 */
5808static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5809{
5810 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5811 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5812 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5813}
5814
5815static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5816{
5817 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5818 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5819 X86_EFLAGS_SF | X86_EFLAGS_OF))
5820 | X86_EFLAGS_CF);
5821}
5822
145c28dd 5823static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5824 u32 vm_instruction_error)
5825{
5826 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5827 /*
5828 * failValid writes the error number to the current VMCS, which
5829 * can't be done there isn't a current VMCS.
5830 */
5831 nested_vmx_failInvalid(vcpu);
5832 return;
5833 }
5834 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5835 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5836 X86_EFLAGS_SF | X86_EFLAGS_OF))
5837 | X86_EFLAGS_ZF);
5838 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5839 /*
5840 * We don't need to force a shadow sync because
5841 * VM_INSTRUCTION_ERROR is not shadowed
5842 */
5843}
145c28dd 5844
f4124500
JK		 5845static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5846{
5847 struct vcpu_vmx *vmx =
5848 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5849
5850 vmx->nested.preemption_timer_expired = true;
5851 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5852 kvm_vcpu_kick(&vmx->vcpu);
5853
5854 return HRTIMER_NORESTART;
5855}
5856
19677e32
BD		 5857/*
5858 * Decode the memory-address operand of a vmx instruction, as recorded on an
5859 * exit caused by such an instruction (run by a guest hypervisor).
5860 * On success, returns 0. When the operand is invalid, returns 1 and throws
5861 * #UD or #GP.
5862 */
5863static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5864 unsigned long exit_qualification,
5865 u32 vmx_instruction_info, gva_t *ret)
5866{
5867 /*
5868 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5869 * Execution", on an exit, vmx_instruction_info holds most of the
5870 * addressing components of the operand. Only the displacement part
5871 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5872 * For how an actual address is calculated from all these components,
5873 * refer to Vol. 1, "Operand Addressing".
5874 */
5875 int scaling = vmx_instruction_info & 3;
5876 int addr_size = (vmx_instruction_info >> 7) & 7;
5877 bool is_reg = vmx_instruction_info & (1u << 10);
5878 int seg_reg = (vmx_instruction_info >> 15) & 7;
5879 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5880 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5881 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5882 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5883
5884 if (is_reg) {
5885 kvm_queue_exception(vcpu, UD_VECTOR);
5886 return 1;
5887 }
5888
5889 /* Addr = segment_base + offset */
5890 /* offset = base + [index * scale] + displacement */
5891 *ret = vmx_get_segment_base(vcpu, seg_reg);
5892 if (base_is_valid)
5893 *ret += kvm_register_read(vcpu, base_reg);
5894 if (index_is_valid)
5895 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5896 *ret += exit_qualification; /* holds the displacement */
5897
5898 if (addr_size == 1) /* 32 bit */
5899 *ret &= 0xffffffff;
5900
5901 /*
5902 * TODO: throw #GP (and return 1) in various cases that the VM*
5903 * instructions require it - e.g., offset beyond segment limit,
5904 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5905 * address, and so on. Currently these are not checked.
5906 */
5907 return 0;
5908}
5909
3573e22c
BD		 5910/*
5911 * This function performs the various checks including
5912 * - if it's 4KB aligned
5913 * - No bits beyond the physical address width are set
5914 * - Returns 0 on success or else 1
4291b588 5915 * (Intel SDM Section 30.3)
3573e22c 5916 */
4291b588
BD		 5917static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5918 gpa_t *vmpointer)
3573e22c
BD		 5919{
5920 gva_t gva;
5921 gpa_t vmptr;
5922 struct x86_exception e;
5923 struct page *page;
5924 struct vcpu_vmx *vmx = to_vmx(vcpu);
5925 int maxphyaddr = cpuid_maxphyaddr(vcpu);
5926
5927 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5928 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5929 return 1;
5930
5931 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5932 sizeof(vmptr), &e)) {
5933 kvm_inject_page_fault(vcpu, &e);
5934 return 1;
5935 }
5936
5937 switch (exit_reason) {
5938 case EXIT_REASON_VMON:
5939 /*
5940 * SDM 3: 24.11.5
5941 * The first 4 bytes of VMXON region contain the supported
5942 * VMCS revision identifier
5943 *
5944 * Note - IA32_VMX_BASIC[48] will never be 1
5945 * for the nested case;
5946 * which replaces physical address width with 32
5947 *
5948 */
bc39c4db 5949 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 5950 nested_vmx_failInvalid(vcpu);
5951 skip_emulated_instruction(vcpu);
5952 return 1;
5953 }
5954
5955 page = nested_get_page(vcpu, vmptr);
5956 if (page == NULL ||
5957 *(u32 *)kmap(page) != VMCS12_REVISION) {
5958 nested_vmx_failInvalid(vcpu);
5959 kunmap(page);
5960 skip_emulated_instruction(vcpu);
5961 return 1;
5962 }
5963 kunmap(page);
5964 vmx->nested.vmxon_ptr = vmptr;
5965 break;
4291b588 5966 case EXIT_REASON_VMCLEAR:
bc39c4db 5967 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5968 nested_vmx_failValid(vcpu,
5969 VMXERR_VMCLEAR_INVALID_ADDRESS);
5970 skip_emulated_instruction(vcpu);
5971 return 1;
5972 }
5973
5974 if (vmptr == vmx->nested.vmxon_ptr) {
5975 nested_vmx_failValid(vcpu,
5976 VMXERR_VMCLEAR_VMXON_POINTER);
5977 skip_emulated_instruction(vcpu);
5978 return 1;
5979 }
5980 break;
5981 case EXIT_REASON_VMPTRLD:
bc39c4db 5982 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5983 nested_vmx_failValid(vcpu,
5984 VMXERR_VMPTRLD_INVALID_ADDRESS);
5985 skip_emulated_instruction(vcpu);
5986 return 1;
5987 }
3573e22c 5988
4291b588
BD		 5989 if (vmptr == vmx->nested.vmxon_ptr) {
5990 nested_vmx_failValid(vcpu,
5991 VMXERR_VMCLEAR_VMXON_POINTER);
5992 skip_emulated_instruction(vcpu);
5993 return 1;
5994 }
5995 break;
3573e22c
BD		 5996 default:
5997 return 1; /* shouldn't happen */
5998 }
5999
4291b588
BD		 6000 if (vmpointer)
6001 *vmpointer = vmptr;
3573e22c
BD		 6002 return 0;
6003}
6004
ec378aee
NHE		 6005/*
6006 * Emulate the VMXON instruction.
6007 * Currently, we just remember that VMX is active, and do not save or even
6008 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6009 * do not currently need to store anything in that guest-allocated memory
6010 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6011 * argument is different from the VMXON pointer (which the spec says they do).
6012 */
6013static int handle_vmon(struct kvm_vcpu *vcpu)
6014{
6015 struct kvm_segment cs;
6016 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6017 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6018 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6019 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6020
6021 /* The Intel VMX Instruction Reference lists a bunch of bits that
6022 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6023 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6024 * Otherwise, we should fail with #UD. We test these now:
6025 */
6026 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6027 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6028 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6029 kvm_queue_exception(vcpu, UD_VECTOR);
6030 return 1;
6031 }
6032
6033 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6034 if (is_long_mode(vcpu) && !cs.l) {
6035 kvm_queue_exception(vcpu, UD_VECTOR);
6036 return 1;
6037 }
6038
6039 if (vmx_get_cpl(vcpu)) {
6040 kvm_inject_gp(vcpu, 0);
6041 return 1;
6042 }
3573e22c 6043
4291b588 6044 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6045 return 1;
6046
145c28dd
AG		 6047 if (vmx->nested.vmxon) {
6048 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6049 skip_emulated_instruction(vcpu);
6050 return 1;
6051 }
b3897a49
NHE		 6052
6053 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6054 != VMXON_NEEDED_FEATURES) {
6055 kvm_inject_gp(vcpu, 0);
6056 return 1;
6057 }
6058
8de48833
AG		 6059 if (enable_shadow_vmcs) {
6060 shadow_vmcs = alloc_vmcs();
6061 if (!shadow_vmcs)
6062 return -ENOMEM;
6063 /* mark vmcs as shadow */
6064 shadow_vmcs->revision_id |= (1u << 31);
6065 /* init shadow vmcs */
6066 vmcs_clear(shadow_vmcs);
6067 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6068 }
ec378aee 6069
ff2f6fe9
NHE		 6070 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6071 vmx->nested.vmcs02_num = 0;
6072
f4124500
JK		 6073 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6074 HRTIMER_MODE_REL);
6075 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6076
ec378aee
NHE		 6077 vmx->nested.vmxon = true;
6078
6079 skip_emulated_instruction(vcpu);
a25eb114 6080 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6081 return 1;
6082}
6083
6084/*
6085 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6086 * for running VMX instructions (except VMXON, whose prerequisites are
6087 * slightly different). It also specifies what exception to inject otherwise.
6088 */
6089static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6090{
6091 struct kvm_segment cs;
6092 struct vcpu_vmx *vmx = to_vmx(vcpu);
6093
6094 if (!vmx->nested.vmxon) {
6095 kvm_queue_exception(vcpu, UD_VECTOR);
6096 return 0;
6097 }
6098
6099 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6100 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6101 (is_long_mode(vcpu) && !cs.l)) {
6102 kvm_queue_exception(vcpu, UD_VECTOR);
6103 return 0;
6104 }
6105
6106 if (vmx_get_cpl(vcpu)) {
6107 kvm_inject_gp(vcpu, 0);
6108 return 0;
6109 }
6110
6111 return 1;
6112}
6113
e7953d7f
AG		 6114static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6115{
8a1b9dd0 6116 u32 exec_control;
9a2a05b9
PB		 6117 if (vmx->nested.current_vmptr == -1ull)
6118 return;
6119
6120 /* current_vmptr and current_vmcs12 are always set/reset together */
6121 if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6122 return;
6123
012f83cb 6124 if (enable_shadow_vmcs) {
9a2a05b9
PB		 6125 /* copy to memory all shadowed fields in case
6126 they were modified */
6127 copy_shadow_to_vmcs12(vmx);
6128 vmx->nested.sync_shadow_vmcs = false;
6129 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6130 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6131 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6132 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb 6133 }
e7953d7f
AG		 6134 kunmap(vmx->nested.current_vmcs12_page);
6135 nested_release_page(vmx->nested.current_vmcs12_page);
9a2a05b9
PB		 6136 vmx->nested.current_vmptr = -1ull;
6137 vmx->nested.current_vmcs12 = NULL;
e7953d7f
AG		 6138}
6139
ec378aee
NHE		 6140/*
6141 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6142 * just stops using VMX.
6143 */
6144static void free_nested(struct vcpu_vmx *vmx)
6145{
6146 if (!vmx->nested.vmxon)
6147 return;
9a2a05b9 6148
ec378aee 6149 vmx->nested.vmxon = false;
9a2a05b9 6150 nested_release_vmcs12(vmx);
e7953d7f
AG		 6151 if (enable_shadow_vmcs)
6152 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6153 /* Unpin physical memory we referred to in current vmcs02 */
6154 if (vmx->nested.apic_access_page) {
6155 nested_release_page(vmx->nested.apic_access_page);
6156 vmx->nested.apic_access_page = 0;
6157 }
ff2f6fe9
NHE		 6158
6159 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6160}
6161
6162/* Emulate the VMXOFF instruction */
6163static int handle_vmoff(struct kvm_vcpu *vcpu)
6164{
6165 if (!nested_vmx_check_permission(vcpu))
6166 return 1;
6167 free_nested(to_vmx(vcpu));
6168 skip_emulated_instruction(vcpu);
a25eb114 6169 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6170 return 1;
6171}
6172
27d6c865
NHE		 6173/* Emulate the VMCLEAR instruction */
6174static int handle_vmclear(struct kvm_vcpu *vcpu)
6175{
6176 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6177 gpa_t vmptr;
6178 struct vmcs12 *vmcs12;
6179 struct page *page;
27d6c865
NHE		 6180
6181 if (!nested_vmx_check_permission(vcpu))
6182 return 1;
6183
4291b588 6184 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6185 return 1;
27d6c865 6186
9a2a05b9 6187 if (vmptr == vmx->nested.current_vmptr)
e7953d7f 6188 nested_release_vmcs12(vmx);
27d6c865
NHE		 6189
6190 page = nested_get_page(vcpu, vmptr);
6191 if (page == NULL) {
6192 /*
6193 * For accurate processor emulation, VMCLEAR beyond available
6194 * physical memory should do nothing at all. However, it is
6195 * possible that a nested vmx bug, not a guest hypervisor bug,
6196 * resulted in this case, so let's shut down before doing any
6197 * more damage:
6198 */
6199 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6200 return 1;
6201 }
6202 vmcs12 = kmap(page);
6203 vmcs12->launch_state = 0;
6204 kunmap(page);
6205 nested_release_page(page);
6206
6207 nested_free_vmcs02(vmx, vmptr);
6208
6209 skip_emulated_instruction(vcpu);
6210 nested_vmx_succeed(vcpu);
6211 return 1;
6212}
6213
cd232ad0
NHE		 6214static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6215
6216/* Emulate the VMLAUNCH instruction */
6217static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6218{
6219 return nested_vmx_run(vcpu, true);
6220}
6221
6222/* Emulate the VMRESUME instruction */
6223static int handle_vmresume(struct kvm_vcpu *vcpu)
6224{
6225
6226 return nested_vmx_run(vcpu, false);
6227}
6228
49f705c5
NHE		 6229enum vmcs_field_type {
6230 VMCS_FIELD_TYPE_U16 = 0,
6231 VMCS_FIELD_TYPE_U64 = 1,
6232 VMCS_FIELD_TYPE_U32 = 2,
6233 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6234};
6235
6236static inline int vmcs_field_type(unsigned long field)
6237{
6238 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6239 return VMCS_FIELD_TYPE_U32;
6240 return (field >> 13) & 0x3 ;
6241}
6242
6243static inline int vmcs_field_readonly(unsigned long field)
6244{
6245 return (((field >> 10) & 0x3) == 1);
6246}
6247
6248/*
6249 * Read a vmcs12 field. Since these can have varying lengths and we return
6250 * one type, we chose the biggest type (u64) and zero-extend the return value
6251 * to that size. Note that the caller, handle_vmread, might need to use only
6252 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6253 * 64-bit fields are to be returned).
6254 */
6255static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6256 unsigned long field, u64 *ret)
6257{
6258 short offset = vmcs_field_to_offset(field);
6259 char *p;
6260
6261 if (offset < 0)
6262 return 0;
6263
6264 p = ((char *)(get_vmcs12(vcpu))) + offset;
6265
6266 switch (vmcs_field_type(field)) {
6267 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6268 *ret = *((natural_width *)p);
6269 return 1;
6270 case VMCS_FIELD_TYPE_U16:
6271 *ret = *((u16 *)p);
6272 return 1;
6273 case VMCS_FIELD_TYPE_U32:
6274 *ret = *((u32 *)p);
6275 return 1;
6276 case VMCS_FIELD_TYPE_U64:
6277 *ret = *((u64 *)p);
6278 return 1;
6279 default:
6280 return 0; /* can never happen. */
6281 }
6282}
6283
20b97fea
AG		 6284
6285static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6286 unsigned long field, u64 field_value){
6287 short offset = vmcs_field_to_offset(field);
6288 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6289 if (offset < 0)
6290 return false;
6291
6292 switch (vmcs_field_type(field)) {
6293 case VMCS_FIELD_TYPE_U16:
6294 *(u16 *)p = field_value;
6295 return true;
6296 case VMCS_FIELD_TYPE_U32:
6297 *(u32 *)p = field_value;
6298 return true;
6299 case VMCS_FIELD_TYPE_U64:
6300 *(u64 *)p = field_value;
6301 return true;
6302 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6303 *(natural_width *)p = field_value;
6304 return true;
6305 default:
6306 return false; /* can never happen. */
6307 }
6308
6309}
6310
16f5b903
AG		 6311static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6312{
6313 int i;
6314 unsigned long field;
6315 u64 field_value;
6316 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6317 const unsigned long *fields = shadow_read_write_fields;
6318 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6319
6320 vmcs_load(shadow_vmcs);
6321
6322 for (i = 0; i < num_fields; i++) {
6323 field = fields[i];
6324 switch (vmcs_field_type(field)) {
6325 case VMCS_FIELD_TYPE_U16:
6326 field_value = vmcs_read16(field);
6327 break;
6328 case VMCS_FIELD_TYPE_U32:
6329 field_value = vmcs_read32(field);
6330 break;
6331 case VMCS_FIELD_TYPE_U64:
6332 field_value = vmcs_read64(field);
6333 break;
6334 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6335 field_value = vmcs_readl(field);
6336 break;
6337 }
6338 vmcs12_write_any(&vmx->vcpu, field, field_value);
6339 }
6340
6341 vmcs_clear(shadow_vmcs);
6342 vmcs_load(vmx->loaded_vmcs->vmcs);
6343}
6344
c3114420
AG		 6345static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6346{
c2bae893
MK		 6347 const unsigned long *fields[] = {
6348 shadow_read_write_fields,
6349 shadow_read_only_fields
c3114420 6350 };
c2bae893 6351 const int max_fields[] = {
c3114420
AG		 6352 max_shadow_read_write_fields,
6353 max_shadow_read_only_fields
6354 };
6355 int i, q;
6356 unsigned long field;
6357 u64 field_value = 0;
6358 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6359
6360 vmcs_load(shadow_vmcs);
6361
c2bae893 6362 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6363 for (i = 0; i < max_fields[q]; i++) {
6364 field = fields[q][i];
6365 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6366
6367 switch (vmcs_field_type(field)) {
6368 case VMCS_FIELD_TYPE_U16:
6369 vmcs_write16(field, (u16)field_value);
6370 break;
6371 case VMCS_FIELD_TYPE_U32:
6372 vmcs_write32(field, (u32)field_value);
6373 break;
6374 case VMCS_FIELD_TYPE_U64:
6375 vmcs_write64(field, (u64)field_value);
6376 break;
6377 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6378 vmcs_writel(field, (long)field_value);
6379 break;
6380 }
6381 }
6382 }
6383
6384 vmcs_clear(shadow_vmcs);
6385 vmcs_load(vmx->loaded_vmcs->vmcs);
6386}
6387
49f705c5
NHE		 6388/*
6389 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6390 * used before) all generate the same failure when it is missing.
6391 */
6392static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6393{
6394 struct vcpu_vmx *vmx = to_vmx(vcpu);
6395 if (vmx->nested.current_vmptr == -1ull) {
6396 nested_vmx_failInvalid(vcpu);
6397 skip_emulated_instruction(vcpu);
6398 return 0;
6399 }
6400 return 1;
6401}
6402
6403static int handle_vmread(struct kvm_vcpu *vcpu)
6404{
6405 unsigned long field;
6406 u64 field_value;
6407 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6408 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6409 gva_t gva = 0;
6410
6411 if (!nested_vmx_check_permission(vcpu) ||
6412 !nested_vmx_check_vmcs12(vcpu))
6413 return 1;
6414
6415 /* Decode instruction info and find the field to read */
27e6fb5d 6416 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6417 /* Read the field, zero-extended to a u64 field_value */
6418 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6419 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6420 skip_emulated_instruction(vcpu);
6421 return 1;
6422 }
6423 /*
6424 * Now copy part of this value to register or memory, as requested.
6425 * Note that the number of bits actually copied is 32 or 64 depending
6426 * on the guest's mode (32 or 64 bit), not on the given field's length.
6427 */
6428 if (vmx_instruction_info & (1u << 10)) {
27e6fb5d 6429 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
49f705c5
NHE		 6430 field_value);
6431 } else {
6432 if (get_vmx_mem_address(vcpu, exit_qualification,
6433 vmx_instruction_info, &gva))
6434 return 1;
6435 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6436 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6437 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6438 }
6439
6440 nested_vmx_succeed(vcpu);
6441 skip_emulated_instruction(vcpu);
6442 return 1;
6443}
6444
6445
6446static int handle_vmwrite(struct kvm_vcpu *vcpu)
6447{
6448 unsigned long field;
6449 gva_t gva;
6450 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6451 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6452 /* The value to write might be 32 or 64 bits, depending on L1's long
6453 * mode, and eventually we need to write that into a field of several
6454 * possible lengths. The code below first zero-extends the value to 64
6455 * bit (field_value), and then copies only the approriate number of
6456 * bits into the vmcs12 field.
6457 */
6458 u64 field_value = 0;
6459 struct x86_exception e;
6460
6461 if (!nested_vmx_check_permission(vcpu) ||
6462 !nested_vmx_check_vmcs12(vcpu))
6463 return 1;
6464
6465 if (vmx_instruction_info & (1u << 10))
27e6fb5d 6466 field_value = kvm_register_readl(vcpu,
49f705c5
NHE		 6467 (((vmx_instruction_info) >> 3) & 0xf));
6468 else {
6469 if (get_vmx_mem_address(vcpu, exit_qualification,
6470 vmx_instruction_info, &gva))
6471 return 1;
6472 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
27e6fb5d 6473 &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
49f705c5
NHE		 6474 kvm_inject_page_fault(vcpu, &e);
6475 return 1;
6476 }
6477 }
6478
6479
27e6fb5d 6480 field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
49f705c5
NHE		 6481 if (vmcs_field_readonly(field)) {
6482 nested_vmx_failValid(vcpu,
6483 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6484 skip_emulated_instruction(vcpu);
6485 return 1;
6486 }
6487
20b97fea 6488 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6489 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6490 skip_emulated_instruction(vcpu);
6491 return 1;
6492 }
6493
6494 nested_vmx_succeed(vcpu);
6495 skip_emulated_instruction(vcpu);
6496 return 1;
6497}
6498
63846663
NHE		 6499/* Emulate the VMPTRLD instruction */
6500static int handle_vmptrld(struct kvm_vcpu *vcpu)
6501{
6502 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6503 gpa_t vmptr;
8a1b9dd0 6504 u32 exec_control;
63846663
NHE		 6505
6506 if (!nested_vmx_check_permission(vcpu))
6507 return 1;
6508
4291b588 6509 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6510 return 1;
63846663
NHE		 6511
6512 if (vmx->nested.current_vmptr != vmptr) {
6513 struct vmcs12 *new_vmcs12;
6514 struct page *page;
6515 page = nested_get_page(vcpu, vmptr);
6516 if (page == NULL) {
6517 nested_vmx_failInvalid(vcpu);
6518 skip_emulated_instruction(vcpu);
6519 return 1;
6520 }
6521 new_vmcs12 = kmap(page);
6522 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6523 kunmap(page);
6524 nested_release_page_clean(page);
6525 nested_vmx_failValid(vcpu,
6526 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6527 skip_emulated_instruction(vcpu);
6528 return 1;
6529 }
63846663 6530
9a2a05b9 6531 nested_release_vmcs12(vmx);
63846663
NHE		 6532 vmx->nested.current_vmptr = vmptr;
6533 vmx->nested.current_vmcs12 = new_vmcs12;
6534 vmx->nested.current_vmcs12_page = page;
012f83cb 6535 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6536 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6537 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6538 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6539 vmcs_write64(VMCS_LINK_POINTER,
6540 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6541 vmx->nested.sync_shadow_vmcs = true;
6542 }
63846663
NHE		 6543 }
6544
6545 nested_vmx_succeed(vcpu);
6546 skip_emulated_instruction(vcpu);
6547 return 1;
6548}
6549
6a4d7550
NHE		 6550/* Emulate the VMPTRST instruction */
6551static int handle_vmptrst(struct kvm_vcpu *vcpu)
6552{
6553 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6554 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6555 gva_t vmcs_gva;
6556 struct x86_exception e;
6557
6558 if (!nested_vmx_check_permission(vcpu))
6559 return 1;
6560
6561 if (get_vmx_mem_address(vcpu, exit_qualification,
6562 vmx_instruction_info, &vmcs_gva))
6563 return 1;
6564 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6565 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6566 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6567 sizeof(u64), &e)) {
6568 kvm_inject_page_fault(vcpu, &e);
6569 return 1;
6570 }
6571 nested_vmx_succeed(vcpu);
6572 skip_emulated_instruction(vcpu);
6573 return 1;
6574}
6575
bfd0a56b
NHE		 6576/* Emulate the INVEPT instruction */
6577static int handle_invept(struct kvm_vcpu *vcpu)
6578{
6579 u32 vmx_instruction_info, types;
6580 unsigned long type;
6581 gva_t gva;
6582 struct x86_exception e;
6583 struct {
6584 u64 eptp, gpa;
6585 } operand;
bfd0a56b
NHE		 6586
6587 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6588 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6589 kvm_queue_exception(vcpu, UD_VECTOR);
6590 return 1;
6591 }
6592
6593 if (!nested_vmx_check_permission(vcpu))
6594 return 1;
6595
6596 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6597 kvm_queue_exception(vcpu, UD_VECTOR);
6598 return 1;
6599 }
6600
6601 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
27e6fb5d 6602 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
bfd0a56b
NHE		 6603
6604 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6605
6606 if (!(types & (1UL << type))) {
6607 nested_vmx_failValid(vcpu,
6608 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6609 return 1;
6610 }
6611
6612 /* According to the Intel VMX instruction reference, the memory
6613 * operand is read even if it isn't needed (e.g., for type==global)
6614 */
6615 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6616 vmx_instruction_info, &gva))
6617 return 1;
6618 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6619 sizeof(operand), &e)) {
6620 kvm_inject_page_fault(vcpu, &e);
6621 return 1;
6622 }
6623
6624 switch (type) {
bfd0a56b
NHE		 6625 case VMX_EPT_EXTENT_GLOBAL:
6626 kvm_mmu_sync_roots(vcpu);
6627 kvm_mmu_flush_tlb(vcpu);
6628 nested_vmx_succeed(vcpu);
6629 break;
6630 default:
4b855078 6631 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6632 BUG_ON(1);
6633 break;
6634 }
6635
6636 skip_emulated_instruction(vcpu);
6637 return 1;
6638}
6639
6aa8b732
AK		 6640/*
6641 * The exit handlers return 1 if the exit was handled fully and guest execution
6642 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6643 * to be done to userspace and return 0.
6644 */
772e0318 6645static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6646 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6647 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6648 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6649 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6650 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6651 [EXIT_REASON_CR_ACCESS] = handle_cr,
6652 [EXIT_REASON_DR_ACCESS] = handle_dr,
6653 [EXIT_REASON_CPUID] = handle_cpuid,
6654 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6655 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6656 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6657 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6658 [EXIT_REASON_INVD] = handle_invd,
a7052897 6659 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6660 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6661 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6662 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6663 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6664 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6665 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6666 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6667 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6668 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6669 [EXIT_REASON_VMOFF] = handle_vmoff,
6670 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6671 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6672 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6673 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6674 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6675 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6676 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6677 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6678 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6679 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6680 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6681 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6682 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6683 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6684 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6685};
6686
6687static const int kvm_vmx_max_exit_handlers =
50a3485c 6688 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6689
908a7bdd
JK		 6690static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6691 struct vmcs12 *vmcs12)
6692{
6693 unsigned long exit_qualification;
6694 gpa_t bitmap, last_bitmap;
6695 unsigned int port;
6696 int size;
6697 u8 b;
6698
908a7bdd 6699 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6700 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6701
6702 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6703
6704 port = exit_qualification >> 16;
6705 size = (exit_qualification & 7) + 1;
6706
6707 last_bitmap = (gpa_t)-1;
6708 b = -1;
6709
6710 while (size > 0) {
6711 if (port < 0x8000)
6712 bitmap = vmcs12->io_bitmap_a;
6713 else if (port < 0x10000)
6714 bitmap = vmcs12->io_bitmap_b;
6715 else
6716 return 1;
6717 bitmap += (port & 0x7fff) / 8;
6718
6719 if (last_bitmap != bitmap)
6720 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6721 return 1;
6722 if (b & (1 << (port & 7)))
6723 return 1;
6724
6725 port++;
6726 size--;
6727 last_bitmap = bitmap;
6728 }
6729
6730 return 0;
6731}
6732
644d711a
NHE		 6733/*
6734 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6735 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6736 * disinterest in the current event (read or write a specific MSR) by using an
6737 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6738 */
6739static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6740 struct vmcs12 *vmcs12, u32 exit_reason)
6741{
6742 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6743 gpa_t bitmap;
6744
cbd29cb6 6745 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6746 return 1;
6747
6748 /*
6749 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6750 * for the four combinations of read/write and low/high MSR numbers.
6751 * First we need to figure out which of the four to use:
6752 */
6753 bitmap = vmcs12->msr_bitmap;
6754 if (exit_reason == EXIT_REASON_MSR_WRITE)
6755 bitmap += 2048;
6756 if (msr_index >= 0xc0000000) {
6757 msr_index -= 0xc0000000;
6758 bitmap += 1024;
6759 }
6760
6761 /* Then read the msr_index'th bit from this bitmap: */
6762 if (msr_index < 1024*8) {
6763 unsigned char b;
bd31a7f5
JK		 6764 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6765 return 1;
644d711a
NHE		 6766 return 1 & (b >> (msr_index & 7));
6767 } else
6768 return 1; /* let L1 handle the wrong parameter */
6769}
6770
6771/*
6772 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6773 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6774 * intercept (via guest_host_mask etc.) the current event.
6775 */
6776static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6777 struct vmcs12 *vmcs12)
6778{
6779 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6780 int cr = exit_qualification & 15;
6781 int reg = (exit_qualification >> 8) & 15;
1e32c079 6782 unsigned long val = kvm_register_readl(vcpu, reg);
644d711a
NHE		 6783
6784 switch ((exit_qualification >> 4) & 3) {
6785 case 0: /* mov to cr */
6786 switch (cr) {
6787 case 0:
6788 if (vmcs12->cr0_guest_host_mask &
6789 (val ^ vmcs12->cr0_read_shadow))
6790 return 1;
6791 break;
6792 case 3:
6793 if ((vmcs12->cr3_target_count >= 1 &&
6794 vmcs12->cr3_target_value0 == val) ||
6795 (vmcs12->cr3_target_count >= 2 &&
6796 vmcs12->cr3_target_value1 == val) ||
6797 (vmcs12->cr3_target_count >= 3 &&
6798 vmcs12->cr3_target_value2 == val) ||
6799 (vmcs12->cr3_target_count >= 4 &&
6800 vmcs12->cr3_target_value3 == val))
6801 return 0;
6802 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6803 return 1;
6804 break;
6805 case 4:
6806 if (vmcs12->cr4_guest_host_mask &
6807 (vmcs12->cr4_read_shadow ^ val))
6808 return 1;
6809 break;
6810 case 8:
6811 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6812 return 1;
6813 break;
6814 }
6815 break;
6816 case 2: /* clts */
6817 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6818 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6819 return 1;
6820 break;
6821 case 1: /* mov from cr */
6822 switch (cr) {
6823 case 3:
6824 if (vmcs12->cpu_based_vm_exec_control &
6825 CPU_BASED_CR3_STORE_EXITING)
6826 return 1;
6827 break;
6828 case 8:
6829 if (vmcs12->cpu_based_vm_exec_control &
6830 CPU_BASED_CR8_STORE_EXITING)
6831 return 1;
6832 break;
6833 }
6834 break;
6835 case 3: /* lmsw */
6836 /*
6837 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6838 * cr0. Other attempted changes are ignored, with no exit.
6839 */
6840 if (vmcs12->cr0_guest_host_mask & 0xe &
6841 (val ^ vmcs12->cr0_read_shadow))
6842 return 1;
6843 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6844 !(vmcs12->cr0_read_shadow & 0x1) &&
6845 (val & 0x1))
6846 return 1;
6847 break;
6848 }
6849 return 0;
6850}
6851
6852/*
6853 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6854 * should handle it ourselves in L0 (and then continue L2). Only call this
6855 * when in is_guest_mode (L2).
6856 */
6857static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6858{
644d711a
NHE		 6859 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6860 struct vcpu_vmx *vmx = to_vmx(vcpu);
6861 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6862 u32 exit_reason = vmx->exit_reason;
644d711a 6863
542060ea
JK		 6864 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6865 vmcs_readl(EXIT_QUALIFICATION),
6866 vmx->idt_vectoring_info,
6867 intr_info,
6868 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6869 KVM_ISA_VMX);
6870
644d711a
NHE		 6871 if (vmx->nested.nested_run_pending)
6872 return 0;
6873
6874 if (unlikely(vmx->fail)) {
bd80158a
JK		 6875 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6876 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6877 return 1;
6878 }
6879
6880 switch (exit_reason) {
6881 case EXIT_REASON_EXCEPTION_NMI:
6882 if (!is_exception(intr_info))
6883 return 0;
6884 else if (is_page_fault(intr_info))
6885 return enable_ept;
e504c909 6886 else if (is_no_device(intr_info) &&
ccf9844e 6887 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6888 return 0;
644d711a
NHE		 6889 return vmcs12->exception_bitmap &
6890 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6891 case EXIT_REASON_EXTERNAL_INTERRUPT:
6892 return 0;
6893 case EXIT_REASON_TRIPLE_FAULT:
6894 return 1;
6895 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6896 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6897 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6898 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6899 case EXIT_REASON_TASK_SWITCH:
6900 return 1;
6901 case EXIT_REASON_CPUID:
6902 return 1;
6903 case EXIT_REASON_HLT:
6904 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6905 case EXIT_REASON_INVD:
6906 return 1;
6907 case EXIT_REASON_INVLPG:
6908 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6909 case EXIT_REASON_RDPMC:
6910 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6911 case EXIT_REASON_RDTSC:
6912 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6913 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6914 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6915 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6916 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6917 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6918 case EXIT_REASON_INVEPT:
644d711a
NHE		 6919 /*
6920 * VMX instructions trap unconditionally. This allows L1 to
6921 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6922 */
6923 return 1;
6924 case EXIT_REASON_CR_ACCESS:
6925 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6926 case EXIT_REASON_DR_ACCESS:
6927 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6928 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6929 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6930 case EXIT_REASON_MSR_READ:
6931 case EXIT_REASON_MSR_WRITE:
6932 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6933 case EXIT_REASON_INVALID_STATE:
6934 return 1;
6935 case EXIT_REASON_MWAIT_INSTRUCTION:
6936 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6937 case EXIT_REASON_MONITOR_INSTRUCTION:
6938 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6939 case EXIT_REASON_PAUSE_INSTRUCTION:
6940 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6941 nested_cpu_has2(vmcs12,
6942 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6943 case EXIT_REASON_MCE_DURING_VMENTRY:
6944 return 0;
6945 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6946 return 1;
6947 case EXIT_REASON_APIC_ACCESS:
6948 return nested_cpu_has2(vmcs12,
6949 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6950 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6951 /*
6952 * L0 always deals with the EPT violation. If nested EPT is
6953 * used, and the nested mmu code discovers that the address is
6954 * missing in the guest EPT table (EPT12), the EPT violation
6955 * will be injected with nested_ept_inject_page_fault()
6956 */
6957 return 0;
644d711a 6958 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6959 /*
6960 * L2 never uses directly L1's EPT, but rather L0's own EPT
6961 * table (shadow on EPT) or a merged EPT table that L0 built
6962 * (EPT on EPT). So any problems with the structure of the
6963 * table is L0's fault.
6964 */
644d711a
NHE		 6965 return 0;
6966 case EXIT_REASON_WBINVD:
6967 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6968 case EXIT_REASON_XSETBV:
6969 return 1;
6970 default:
6971 return 1;
6972 }
6973}
6974
586f9607
AK		 6975static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6976{
6977 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6978 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6979}
6980
6aa8b732
AK		 6981/*
6982 * The guest has exited. See if we can fix it or if we need userspace
6983 * assistance.
6984 */
851ba692 6985static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6986{
29bd8a78 6987 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6988 u32 exit_reason = vmx->exit_reason;
1155f76a 6989 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6990
80ced186 6991 /* If guest state is invalid, start emulating */
14168786 6992 if (vmx->emulation_required)
80ced186 6993 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6994
644d711a 6995 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6996 nested_vmx_vmexit(vcpu, exit_reason,
6997 vmcs_read32(VM_EXIT_INTR_INFO),
6998 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6999 return 1;
7000 }
7001
5120702e
MG		 7002 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
7003 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7004 vcpu->run->fail_entry.hardware_entry_failure_reason
7005 = exit_reason;
7006 return 0;
7007 }
7008
29bd8a78 7009 if (unlikely(vmx->fail)) {
851ba692
AK		 7010 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7011 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7012 = vmcs_read32(VM_INSTRUCTION_ERROR);
7013 return 0;
7014 }
6aa8b732 7015
b9bf6882
XG		 7016 /*
7017 * Note:
7018 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7019 * delivery event since it indicates guest is accessing MMIO.
7020 * The vm-exit can be triggered again after return to guest that
7021 * will cause infinite loop.
7022 */
d77c26fc 7023 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7024 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7025 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7026 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7027 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7028 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7029 vcpu->run->internal.ndata = 2;
7030 vcpu->run->internal.data[0] = vectoring_info;
7031 vcpu->run->internal.data[1] = exit_reason;
7032 return 0;
7033 }
3b86cd99 7034
644d711a
NHE		 7035 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7036 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7037 get_vmcs12(vcpu))))) {
c4282df9 7038 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7039 vmx->soft_vnmi_blocked = 0;
3b86cd99 7040 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7041 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7042 /*
7043 * This CPU don't support us in finding the end of an
7044 * NMI-blocked window if the guest runs with IRQs
7045 * disabled. So we pull the trigger after 1 s of
7046 * futile waiting, but inform the user about this.
7047 */
7048 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7049 "state on VCPU %d after 1 s timeout\n",
7050 __func__, vcpu->vcpu_id);
7051 vmx->soft_vnmi_blocked = 0;
3b86cd99 7052 }
3b86cd99
JK		 7053 }
7054
6aa8b732
AK		 7055 if (exit_reason < kvm_vmx_max_exit_handlers
7056 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7057 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7058 else {
851ba692
AK		 7059 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7060 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7061 }
7062 return 0;
7063}
7064
95ba8273 7065static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7066{
95ba8273 7067 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7068 vmcs_write32(TPR_THRESHOLD, 0);
7069 return;
7070 }
7071
95ba8273 7072 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7073}
7074
8d14695f
YZ		 7075static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7076{
7077 u32 sec_exec_control;
7078
7079 /*
7080 * There is not point to enable virtualize x2apic without enable
7081 * apicv
7082 */
c7c9c56c
YZ		 7083 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7084 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7085 return;
7086
7087 if (!vm_need_tpr_shadow(vcpu->kvm))
7088 return;
7089
7090 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7091
7092 if (set) {
7093 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7094 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7095 } else {
7096 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7097 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7098 }
7099 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7100
7101 vmx_set_msr_bitmap(vcpu);
7102}
7103
c7c9c56c
YZ		 7104static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7105{
7106 u16 status;
7107 u8 old;
7108
7109 if (!vmx_vm_has_apicv(kvm))
7110 return;
7111
7112 if (isr == -1)
7113 isr = 0;
7114
7115 status = vmcs_read16(GUEST_INTR_STATUS);
7116 old = status >> 8;
7117 if (isr != old) {
7118 status &= 0xff;
7119 status |= isr << 8;
7120 vmcs_write16(GUEST_INTR_STATUS, status);
7121 }
7122}
7123
7124static void vmx_set_rvi(int vector)
7125{
7126 u16 status;
7127 u8 old;
7128
7129 status = vmcs_read16(GUEST_INTR_STATUS);
7130 old = (u8)status & 0xff;
7131 if ((u8)vector != old) {
7132 status &= ~0xff;
7133 status |= (u8)vector;
7134 vmcs_write16(GUEST_INTR_STATUS, status);
7135 }
7136}
7137
7138static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7139{
7140 if (max_irr == -1)
7141 return;
7142
963fee16
WL		 7143 /*
7144 * If a vmexit is needed, vmx_check_nested_events handles it.
7145 */
7146 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
7147 return;
7148
7149 if (!is_guest_mode(vcpu)) {
7150 vmx_set_rvi(max_irr);
7151 return;
7152 }
7153
7154 /*
7155 * Fall back to pre-APICv interrupt injection since L2
7156 * is run without virtual interrupt delivery.
7157 */
7158 if (!kvm_event_needs_reinjection(vcpu) &&
7159 vmx_interrupt_allowed(vcpu)) {
7160 kvm_queue_interrupt(vcpu, max_irr, false);
7161 vmx_inject_irq(vcpu);
7162 }
c7c9c56c
YZ		 7163}
7164
7165static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7166{
3d81bc7e
YZ		 7167 if (!vmx_vm_has_apicv(vcpu->kvm))
7168 return;
7169
c7c9c56c
YZ		 7170 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7171 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7172 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7173 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7174}
7175
51aa01d1 7176static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7177{
00eba012
AK		 7178 u32 exit_intr_info;
7179
7180 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7181 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7182 return;
7183
c5ca8e57 7184 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7185 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7186
7187 /* Handle machine checks before interrupts are enabled */
00eba012 7188 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7189 kvm_machine_check();
7190
20f65983 7191 /* We need to handle NMIs before interrupts are enabled */
00eba012 7192 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7193 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7194 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7195 asm("int $2");
ff9d07a0
ZY		 7196 kvm_after_handle_nmi(&vmx->vcpu);
7197 }
51aa01d1 7198}
20f65983 7199
a547c6db
YZ		 7200static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7201{
7202 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7203
7204 /*
7205 * If external interrupt exists, IF bit is set in rflags/eflags on the
7206 * interrupt stack frame, and interrupt will be enabled on a return
7207 * from interrupt handler.
7208 */
7209 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7210 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7211 unsigned int vector;
7212 unsigned long entry;
7213 gate_desc *desc;
7214 struct vcpu_vmx *vmx = to_vmx(vcpu);
7215#ifdef CONFIG_X86_64
7216 unsigned long tmp;
7217#endif
7218
7219 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7220 desc = (gate_desc *)vmx->host_idt_base + vector;
7221 entry = gate_offset(*desc);
7222 asm volatile(
7223#ifdef CONFIG_X86_64
7224 "mov %%" _ASM_SP ", %[sp]\n\t"
7225 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7226 "push $%c[ss]\n\t"
7227 "push %[sp]\n\t"
7228#endif
7229 "pushf\n\t"
7230 "orl $0x200, (%%" _ASM_SP ")\n\t"
7231 __ASM_SIZE(push) " $%c[cs]\n\t"
7232 "call *%[entry]\n\t"
7233 :
7234#ifdef CONFIG_X86_64
7235 [sp]"=&r"(tmp)
7236#endif
7237 :
7238 [entry]"r"(entry),
7239 [ss]"i"(__KERNEL_DS),
7240 [cs]"i"(__KERNEL_CS)
7241 );
7242 } else
7243 local_irq_enable();
7244}
7245
da8999d3
LJ		 7246static bool vmx_mpx_supported(void)
7247{
7248 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7249 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7250}
7251
51aa01d1
AK		 7252static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7253{
c5ca8e57 7254 u32 exit_intr_info;
51aa01d1
AK		 7255 bool unblock_nmi;
7256 u8 vector;
7257 bool idtv_info_valid;
7258
7259 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7260
cf393f75 7261 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7262 if (vmx->nmi_known_unmasked)
7263 return;
c5ca8e57
AK		 7264 /*
7265 * Can't use vmx->exit_intr_info since we're not sure what
7266 * the exit reason is.
7267 */
7268 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7269 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7270 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7271 /*
7b4a25cb 7272 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7273 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7274 * a guest IRET fault.
7b4a25cb
GN		 7275 * SDM 3: 23.2.2 (September 2008)
7276 * Bit 12 is undefined in any of the following cases:
7277 * If the VM exit sets the valid bit in the IDT-vectoring
7278 * information field.
7279 * If the VM exit is due to a double fault.
cf393f75 7280 */
7b4a25cb
GN		 7281 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7282 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7283 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7284 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7285 else
7286 vmx->nmi_known_unmasked =
7287 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7288 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7289 } else if (unlikely(vmx->soft_vnmi_blocked))
7290 vmx->vnmi_blocked_time +=
7291 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7292}
7293
3ab66e8a 7294static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7295 u32 idt_vectoring_info,
7296 int instr_len_field,
7297 int error_code_field)
51aa01d1 7298{
51aa01d1
AK		 7299 u8 vector;
7300 int type;
7301 bool idtv_info_valid;
7302
7303 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7304
3ab66e8a
JK		 7305 vcpu->arch.nmi_injected = false;
7306 kvm_clear_exception_queue(vcpu);
7307 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7308
7309 if (!idtv_info_valid)
7310 return;
7311
3ab66e8a 7312 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7313
668f612f
AK		 7314 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7315 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7316
64a7ec06 7317 switch (type) {
37b96e98 7318 case INTR_TYPE_NMI_INTR:
3ab66e8a 7319 vcpu->arch.nmi_injected = true;
668f612f 7320 /*
7b4a25cb 7321 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7322 * Clear bit "block by NMI" before VM entry if a NMI
7323 * delivery faulted.
668f612f 7324 */
3ab66e8a 7325 vmx_set_nmi_mask(vcpu, false);
37b96e98 7326 break;
37b96e98 7327 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7328 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7329 /* fall through */
7330 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7331 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7332 u32 err = vmcs_read32(error_code_field);
851eb667 7333 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7334 } else
851eb667 7335 kvm_requeue_exception(vcpu, vector);
37b96e98 7336 break;
66fd3f7f 7337 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7338 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7339 /* fall through */
37b96e98 7340 case INTR_TYPE_EXT_INTR:
3ab66e8a 7341 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7342 break;
7343 default:
7344 break;
f7d9238f 7345 }
cf393f75
AK		 7346}
7347
83422e17
AK		 7348static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7349{
3ab66e8a 7350 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7351 VM_EXIT_INSTRUCTION_LEN,
7352 IDT_VECTORING_ERROR_CODE);
7353}
7354
b463a6f7
AK		 7355static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7356{
3ab66e8a 7357 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7358 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7359 VM_ENTRY_INSTRUCTION_LEN,
7360 VM_ENTRY_EXCEPTION_ERROR_CODE);
7361
7362 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7363}
7364
d7cd9796
GN		 7365static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7366{
7367 int i, nr_msrs;
7368 struct perf_guest_switch_msr *msrs;
7369
7370 msrs = perf_guest_get_msrs(&nr_msrs);
7371
7372 if (!msrs)
7373 return;
7374
7375 for (i = 0; i < nr_msrs; i++)
7376 if (msrs[i].host == msrs[i].guest)
7377 clear_atomic_switch_msr(vmx, msrs[i].msr);
7378 else
7379 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7380 msrs[i].host);
7381}
7382
a3b5ba49 7383static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7384{
a2fa3e9f 7385 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7386 unsigned long debugctlmsr;
104f226b
AK		 7387
7388 /* Record the guest's net vcpu time for enforced NMI injections. */
7389 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7390 vmx->entry_time = ktime_get();
7391
7392 /* Don't enter VMX if guest state is invalid, let the exit handler
7393 start emulation until we arrive back to a valid state */
14168786 7394 if (vmx->emulation_required)
104f226b
AK		 7395 return;
7396
a7653ecd
RK		 7397 if (vmx->ple_window_dirty) {
7398 vmx->ple_window_dirty = false;
7399 vmcs_write32(PLE_WINDOW, vmx->ple_window);
7400 }
7401
012f83cb
AG		 7402 if (vmx->nested.sync_shadow_vmcs) {
7403 copy_vmcs12_to_shadow(vmx);
7404 vmx->nested.sync_shadow_vmcs = false;
7405 }
7406
104f226b
AK		 7407 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7408 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7409 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7410 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7411
7412 /* When single-stepping over STI and MOV SS, we must clear the
7413 * corresponding interruptibility bits in the guest state. Otherwise
7414 * vmentry fails as it then expects bit 14 (BS) in pending debug
7415 * exceptions being set, but that's not correct for the guest debugging
7416 * case. */
7417 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7418 vmx_set_interrupt_shadow(vcpu, 0);
7419
d7cd9796 7420 atomic_switch_perf_msrs(vmx);
2a7921b7 7421 debugctlmsr = get_debugctlmsr();
d7cd9796 7422
d462b819 7423 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7424 asm(
6aa8b732 7425 /* Store host registers */
b188c81f
AK		 7426 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7427 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7428 "push %%" _ASM_CX " \n\t"
7429 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7430 "je 1f \n\t"
b188c81f 7431 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7432 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7433 "1: \n\t"
d3edefc0 7434 /* Reload cr2 if changed */
b188c81f
AK		 7435 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7436 "mov %%cr2, %%" _ASM_DX " \n\t"
7437 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7438 "je 2f \n\t"
b188c81f 7439 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7440 "2: \n\t"
6aa8b732 7441 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7442 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7443 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7444 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7445 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7446 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7447 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7448 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7449 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7450#ifdef CONFIG_X86_64
e08aa78a
AK		 7451 "mov %c[r8](%0), %%r8 \n\t"
7452 "mov %c[r9](%0), %%r9 \n\t"
7453 "mov %c[r10](%0), %%r10 \n\t"
7454 "mov %c[r11](%0), %%r11 \n\t"
7455 "mov %c[r12](%0), %%r12 \n\t"
7456 "mov %c[r13](%0), %%r13 \n\t"
7457 "mov %c[r14](%0), %%r14 \n\t"
7458 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7459#endif
b188c81f 7460 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7461
6aa8b732 7462 /* Enter guest mode */
83287ea4 7463 "jne 1f \n\t"
4ecac3fd 7464 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7465 "jmp 2f \n\t"
7466 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7467 "2: "
6aa8b732 7468 /* Save guest registers, load host registers, keep flags */
b188c81f 7469 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7470 "pop %0 \n\t"
b188c81f
AK		 7471 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7472 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7473 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7474 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7475 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7476 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7477 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7478#ifdef CONFIG_X86_64
e08aa78a
AK		 7479 "mov %%r8, %c[r8](%0) \n\t"
7480 "mov %%r9, %c[r9](%0) \n\t"
7481 "mov %%r10, %c[r10](%0) \n\t"
7482 "mov %%r11, %c[r11](%0) \n\t"
7483 "mov %%r12, %c[r12](%0) \n\t"
7484 "mov %%r13, %c[r13](%0) \n\t"
7485 "mov %%r14, %c[r14](%0) \n\t"
7486 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7487#endif
b188c81f
AK		 7488 "mov %%cr2, %%" _ASM_AX " \n\t"
7489 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7490
b188c81f 7491 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7492 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7493 ".pushsection .rodata \n\t"
7494 ".global vmx_return \n\t"
7495 "vmx_return: " _ASM_PTR " 2b \n\t"
7496 ".popsection"
e08aa78a 7497 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7498 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7499 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7500 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7501 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7502 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7503 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7504 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7505 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7506 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7507 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7508#ifdef CONFIG_X86_64
ad312c7c
ZX		 7509 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7510 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7511 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7512 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7513 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7514 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7515 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7516 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7517#endif
40712fae
AK		 7518 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7519 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7520 : "cc", "memory"
7521#ifdef CONFIG_X86_64
b188c81f 7522 , "rax", "rbx", "rdi", "rsi"
c2036300 7523 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7524#else
7525 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7526#endif
7527 );
6aa8b732 7528
2a7921b7
GN		 7529 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7530 if (debugctlmsr)
7531 update_debugctlmsr(debugctlmsr);
7532
aa67f609
AK		 7533#ifndef CONFIG_X86_64
7534 /*
7535 * The sysexit path does not restore ds/es, so we must set them to
7536 * a reasonable value ourselves.
7537 *
7538 * We can't defer this to vmx_load_host_state() since that function
7539 * may be executed in interrupt context, which saves and restore segments
7540 * around it, nullifying its effect.
7541 */
7542 loadsegment(ds, __USER_DS);
7543 loadsegment(es, __USER_DS);
7544#endif
7545
6de4f3ad 7546 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7547 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7548 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7549 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7550 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7551 vcpu->arch.regs_dirty = 0;
7552
1155f76a
AK		 7553 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7554
d462b819 7555 vmx->loaded_vmcs->launched = 1;
1b6269db 7556
51aa01d1 7557 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7558 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7559
e0b890d3
GN		 7560 /*
7561 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7562 * we did not inject a still-pending event to L1 now because of
7563 * nested_run_pending, we need to re-enable this bit.
7564 */
7565 if (vmx->nested.nested_run_pending)
7566 kvm_make_request(KVM_REQ_EVENT, vcpu);
7567
7568 vmx->nested.nested_run_pending = 0;
7569
51aa01d1
AK		 7570 vmx_complete_atomic_exit(vmx);
7571 vmx_recover_nmi_blocking(vmx);
cf393f75 7572 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7573}
7574
4fa7734c
PB		 7575static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
7576{
7577 struct vcpu_vmx *vmx = to_vmx(vcpu);
7578 int cpu;
7579
7580 if (vmx->loaded_vmcs == &vmx->vmcs01)
7581 return;
7582
7583 cpu = get_cpu();
7584 vmx->loaded_vmcs = &vmx->vmcs01;
7585 vmx_vcpu_put(vcpu);
7586 vmx_vcpu_load(vcpu, cpu);
7587 vcpu->cpu = cpu;
7588 put_cpu();
7589}
7590
6aa8b732
AK		 7591static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7592{
fb3f0f51
RR		 7593 struct vcpu_vmx *vmx = to_vmx(vcpu);
7594
cdbecfc3 7595 free_vpid(vmx);
4fa7734c
PB		 7596 leave_guest_mode(vcpu);
7597 vmx_load_vmcs01(vcpu);
26a865f4 7598 free_nested(vmx);
4fa7734c 7599 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7600 kfree(vmx->guest_msrs);
7601 kvm_vcpu_uninit(vcpu);
a4770347 7602 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7603}
7604
fb3f0f51 7605static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7606{
fb3f0f51 7607 int err;
c16f862d 7608 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7609 int cpu;
6aa8b732 7610
a2fa3e9f 7611 if (!vmx)
fb3f0f51
RR		 7612 return ERR_PTR(-ENOMEM);
7613
2384d2b3
SY		 7614 allocate_vpid(vmx);
7615
fb3f0f51
RR		 7616 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7617 if (err)
7618 goto free_vcpu;
965b58a5 7619
a2fa3e9f 7620 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
03916db9
PB		 7621 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
7622 > PAGE_SIZE);
0123be42 7623
be6d05cf 7624 err = -ENOMEM;
fb3f0f51 7625 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7626 goto uninit_vcpu;
7627 }
965b58a5 7628
d462b819
NHE		 7629 vmx->loaded_vmcs = &vmx->vmcs01;
7630 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7631 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7632 goto free_msrs;
d462b819
NHE		 7633 if (!vmm_exclusive)
7634 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7635 loaded_vmcs_init(vmx->loaded_vmcs);
7636 if (!vmm_exclusive)
7637 kvm_cpu_vmxoff();
a2fa3e9f 7638
15ad7146
AK		 7639 cpu = get_cpu();
7640 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7641 vmx->vcpu.cpu = cpu;
8b9cf98c 7642 err = vmx_vcpu_setup(vmx);
fb3f0f51 7643 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7644 put_cpu();
fb3f0f51
RR		 7645 if (err)
7646 goto free_vmcs;
a63cb560 7647 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7648 err = alloc_apic_access_page(kvm);
7649 if (err)
5e4a0b3c 7650 goto free_vmcs;
a63cb560 7651 }
fb3f0f51 7652
b927a3ce
SY		 7653 if (enable_ept) {
7654 if (!kvm->arch.ept_identity_map_addr)
7655 kvm->arch.ept_identity_map_addr =
7656 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7657 err = -ENOMEM;
b7ebfb05
SY		 7658 if (alloc_identity_pagetable(kvm) != 0)
7659 goto free_vmcs;
93ea5388
GN		 7660 if (!init_rmode_identity_map(kvm))
7661 goto free_vmcs;
b927a3ce 7662 }
b7ebfb05 7663
a9d30f33
NHE		 7664 vmx->nested.current_vmptr = -1ull;
7665 vmx->nested.current_vmcs12 = NULL;
7666
fb3f0f51
RR		 7667 return &vmx->vcpu;
7668
7669free_vmcs:
5f3fbc34 7670 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7671free_msrs:
fb3f0f51
RR		 7672 kfree(vmx->guest_msrs);
7673uninit_vcpu:
7674 kvm_vcpu_uninit(&vmx->vcpu);
7675free_vcpu:
cdbecfc3 7676 free_vpid(vmx);
a4770347 7677 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7678 return ERR_PTR(err);
6aa8b732
AK		 7679}
7680
002c7f7c
YS		 7681static void __init vmx_check_processor_compat(void *rtn)
7682{
7683 struct vmcs_config vmcs_conf;
7684
7685 *(int *)rtn = 0;
7686 if (setup_vmcs_config(&vmcs_conf) < 0)
7687 *(int *)rtn = -EIO;
7688 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7689 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7690 smp_processor_id());
7691 *(int *)rtn = -EIO;
7692 }
7693}
7694
67253af5
SY		 7695static int get_ept_level(void)
7696{
7697 return VMX_EPT_DEFAULT_GAW + 1;
7698}
7699
4b12f0de 7700static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7701{
4b12f0de
SY		 7702 u64 ret;
7703
522c68c4
SY		 7704 /* For VT-d and EPT combination
7705 * 1. MMIO: always map as UC
7706 * 2. EPT with VT-d:
7707 * a. VT-d without snooping control feature: can't guarantee the
7708 * result, try to trust guest.
7709 * b. VT-d with snooping control feature: snooping control feature of
7710 * VT-d engine can guarantee the cache correctness. Just set it
7711 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7712 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7713 * consistent with host MTRR
7714 */
4b12f0de
SY		 7715 if (is_mmio)
7716 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7717 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7718 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7719 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7720 else
522c68c4 7721 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7722 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7723
7724 return ret;
64d4d521
SY		 7725}
7726
17cc3935 7727static int vmx_get_lpage_level(void)
344f414f 7728{
878403b7
SY		 7729 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7730 return PT_DIRECTORY_LEVEL;
7731 else
7732 /* For shadow and EPT supported 1GB page */
7733 return PT_PDPE_LEVEL;
344f414f
JR		 7734}
7735
0e851880
SY		 7736static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7737{
4e47c7a6
SY		 7738 struct kvm_cpuid_entry2 *best;
7739 struct vcpu_vmx *vmx = to_vmx(vcpu);
7740 u32 exec_control;
7741
7742 vmx->rdtscp_enabled = false;
7743 if (vmx_rdtscp_supported()) {
7744 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7745 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7746 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7747 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7748 vmx->rdtscp_enabled = true;
7749 else {
7750 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7751 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7752 exec_control);
7753 }
7754 }
7755 }
ad756a16 7756
ad756a16
MJ		 7757 /* Exposing INVPCID only when PCID is exposed */
7758 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7759 if (vmx_invpcid_supported() &&
4f977045 7760 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7761 guest_cpuid_has_pcid(vcpu)) {
29282fde 7762 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7763 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7764 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7765 exec_control);
7766 } else {
29282fde
TI		 7767 if (cpu_has_secondary_exec_ctrls()) {
7768 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7769 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7770 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7771 exec_control);
7772 }
ad756a16 7773 if (best)
4f977045 7774 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7775 }
0e851880
SY		 7776}
7777
d4330ef2
JR		 7778static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7779{
7b8050f5
NHE		 7780 if (func == 1 && nested)
7781 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7782}
7783
25d92081
YZ		 7784static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7785 struct x86_exception *fault)
7786{
533558bc
JK		 7787 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7788 u32 exit_reason;
25d92081
YZ		 7789
7790 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7791 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7792 else
533558bc
JK		 7793 exit_reason = EXIT_REASON_EPT_VIOLATION;
7794 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7795 vmcs12->guest_physical_address = fault->address;
7796}
7797
155a97a3
NHE		 7798/* Callbacks for nested_ept_init_mmu_context: */
7799
7800static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7801{
7802 /* return the page table to be shadowed - in our case, EPT12 */
7803 return get_vmcs12(vcpu)->ept_pointer;
7804}
7805
8a3c1a33 7806static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7807{
8a3c1a33 7808 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7809 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7810
7811 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7812 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7813 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7814
7815 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7816}
7817
7818static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7819{
7820 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7821}
7822
feaf0c7d
GN		 7823static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7824 struct x86_exception *fault)
7825{
7826 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7827
7828 WARN_ON(!is_guest_mode(vcpu));
7829
7830 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7831 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7832 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7833 vmcs_read32(VM_EXIT_INTR_INFO),
7834 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7835 else
7836 kvm_inject_page_fault(vcpu, fault);
7837}
7838
f4124500
JK		 7839static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7840{
7841 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7842 struct vcpu_vmx *vmx = to_vmx(vcpu);
7843
7844 if (vcpu->arch.virtual_tsc_khz == 0)
7845 return;
7846
7847 /* Make sure short timeouts reliably trigger an immediate vmexit.
7848 * hrtimer_start does not guarantee this. */
7849 if (preemption_timeout <= 1) {
7850 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7851 return;
7852 }
7853
7854 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7855 preemption_timeout *= 1000000;
7856 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7857 hrtimer_start(&vmx->nested.preemption_timer,
7858 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7859}
7860
fe3ef05c
NHE		 7861/*
7862 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7863 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7864 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7865 * guest in a way that will both be appropriate to L1's requests, and our
7866 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7867 * function also has additional necessary side-effects, like setting various
7868 * vcpu->arch fields.
7869 */
7870static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7871{
7872 struct vcpu_vmx *vmx = to_vmx(vcpu);
7873 u32 exec_control;
7874
7875 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7876 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7877 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7878 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7879 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7880 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7881 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7882 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7883 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7884 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7885 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7886 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7887 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7888 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7889 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7890 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7891 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7892 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7893 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7894 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7895 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7896 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7897 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7898 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7899 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7900 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7901 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7902 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7903 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7904 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7905 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7906 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7907 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7908 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7909 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7910 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7911
2996fca0
JK		 7912 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
7913 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7914 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7915 } else {
7916 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
7917 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
7918 }
fe3ef05c
NHE		 7919 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7920 vmcs12->vm_entry_intr_info_field);
7921 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7922 vmcs12->vm_entry_exception_error_code);
7923 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7924 vmcs12->vm_entry_instruction_len);
7925 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7926 vmcs12->guest_interruptibility_info);
fe3ef05c 7927 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 7928 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7929 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7930 vmcs12->guest_pending_dbg_exceptions);
7931 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7932 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7933
7934 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7935
f4124500
JK		 7936 exec_control = vmcs12->pin_based_vm_exec_control;
7937 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 7938 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
7939 PIN_BASED_POSTED_INTR);
f4124500 7940 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7941
f4124500
JK		 7942 vmx->nested.preemption_timer_expired = false;
7943 if (nested_cpu_has_preemption_timer(vmcs12))
7944 vmx_start_preemption_timer(vcpu);
0238ea91 7945
fe3ef05c
NHE		 7946 /*
7947 * Whether page-faults are trapped is determined by a combination of
7948 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7949 * If enable_ept, L0 doesn't care about page faults and we should
7950 * set all of these to L1's desires. However, if !enable_ept, L0 does
7951 * care about (at least some) page faults, and because it is not easy
7952 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7953 * to exit on each and every L2 page fault. This is done by setting
7954 * MASK=MATCH=0 and (see below) EB.PF=1.
7955 * Note that below we don't need special code to set EB.PF beyond the
7956 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7957 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7958 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7959 *
7960 * A problem with this approach (when !enable_ept) is that L1 may be
7961 * injected with more page faults than it asked for. This could have
7962 * caused problems, but in practice existing hypervisors don't care.
7963 * To fix this, we will need to emulate the PFEC checking (on the L1
7964 * page tables), using walk_addr(), when injecting PFs to L1.
7965 */
7966 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7967 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7968 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7969 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7970
7971 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7972 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7973 if (!vmx->rdtscp_enabled)
7974 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7975 /* Take the following fields only from vmcs12 */
696dfd95
PB		 7976 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7977 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
7978 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 7979 if (nested_cpu_has(vmcs12,
7980 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7981 exec_control |= vmcs12->secondary_vm_exec_control;
7982
7983 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7984 /*
7985 * Translate L1 physical address to host physical
7986 * address for vmcs02. Keep the page pinned, so this
7987 * physical address remains valid. We keep a reference
7988 * to it so we can release it later.
7989 */
7990 if (vmx->nested.apic_access_page) /* shouldn't happen */
7991 nested_release_page(vmx->nested.apic_access_page);
7992 vmx->nested.apic_access_page =
7993 nested_get_page(vcpu, vmcs12->apic_access_addr);
7994 /*
7995 * If translation failed, no matter: This feature asks
7996 * to exit when accessing the given address, and if it
7997 * can never be accessed, this feature won't do
7998 * anything anyway.
7999 */
8000 if (!vmx->nested.apic_access_page)
8001 exec_control &=
8002 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8003 else
8004 vmcs_write64(APIC_ACCESS_ADDR,
8005 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 8006 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
8007 exec_control |=
8008 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8009 vmcs_write64(APIC_ACCESS_ADDR,
8010 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 8011 }
8012
8013 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
8014 }
8015
8016
8017 /*
8018 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
8019 * Some constant fields are set here by vmx_set_constant_host_state().
8020 * Other fields are different per CPU, and will be set later when
8021 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
8022 */
a547c6db 8023 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 8024
8025 /*
8026 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
8027 * entry, but only if the current (host) sp changed from the value
8028 * we wrote last (vmx->host_rsp). This cache is no longer relevant
8029 * if we switch vmcs, and rather than hold a separate cache per vmcs,
8030 * here we just force the write to happen on entry.
8031 */
8032 vmx->host_rsp = 0;
8033
8034 exec_control = vmx_exec_control(vmx); /* L0's desires */
8035 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
8036 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
8037 exec_control &= ~CPU_BASED_TPR_SHADOW;
8038 exec_control |= vmcs12->cpu_based_vm_exec_control;
8039 /*
8040 * Merging of IO and MSR bitmaps not currently supported.
8041 * Rather, exit every time.
8042 */
8043 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
8044 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
8045 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
8046
8047 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
8048
8049 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
8050 * bitwise-or of what L1 wants to trap for L2, and what we want to
8051 * trap. Note that CR0.TS also needs updating - we do this later.
8052 */
8053 update_exception_bitmap(vcpu);
8054 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8055 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8056
8049d651
NHE		 8057 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8058 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8059 * bits are further modified by vmx_set_efer() below.
8060 */
f4124500 8061 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8062
8063 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8064 * emulated by vmx_set_efer(), below.
8065 */
2961e876 8066 vm_entry_controls_init(vmx,
8049d651
NHE		 8067 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8068 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8069 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8070
44811c02 8071 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8072 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8073 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8074 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8075 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8076
8077
8078 set_cr4_guest_host_mask(vmx);
8079
36be0b9d
PB		 8080 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8081 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8082
27fc51b2
NHE		 8083 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8084 vmcs_write64(TSC_OFFSET,
8085 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8086 else
8087 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8088
8089 if (enable_vpid) {
8090 /*
8091 * Trivially support vpid by letting L2s share their parent
8092 * L1's vpid. TODO: move to a more elaborate solution, giving
8093 * each L2 its own vpid and exposing the vpid feature to L1.
8094 */
8095 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8096 vmx_flush_tlb(vcpu);
8097 }
8098
155a97a3
NHE		 8099 if (nested_cpu_has_ept(vmcs12)) {
8100 kvm_mmu_unload(vcpu);
8101 nested_ept_init_mmu_context(vcpu);
8102 }
8103
fe3ef05c
NHE		 8104 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8105 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8106 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8107 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8108 else
8109 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8110 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8111 vmx_set_efer(vcpu, vcpu->arch.efer);
8112
8113 /*
8114 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8115 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8116 * The CR0_READ_SHADOW is what L2 should have expected to read given
8117 * the specifications by L1; It's not enough to take
8118 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8119 * have more bits than L1 expected.
8120 */
8121 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8122 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8123
8124 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8125 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8126
8127 /* shadow page tables on either EPT or shadow page tables */
8128 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8129 kvm_mmu_reset_context(vcpu);
8130
feaf0c7d
GN		 8131 if (!enable_ept)
8132 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8133
3633cfc3
NHE		 8134 /*
8135 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8136 */
8137 if (enable_ept) {
8138 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8139 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8140 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8141 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8142 }
8143
fe3ef05c
NHE		 8144 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8145 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8146}
8147
cd232ad0
NHE		 8148/*
8149 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8150 * for running an L2 nested guest.
8151 */
8152static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8153{
8154 struct vmcs12 *vmcs12;
8155 struct vcpu_vmx *vmx = to_vmx(vcpu);
8156 int cpu;
8157 struct loaded_vmcs *vmcs02;
384bb783 8158 bool ia32e;
cd232ad0
NHE		 8159
8160 if (!nested_vmx_check_permission(vcpu) ||
8161 !nested_vmx_check_vmcs12(vcpu))
8162 return 1;
8163
8164 skip_emulated_instruction(vcpu);
8165 vmcs12 = get_vmcs12(vcpu);
8166
012f83cb
AG		 8167 if (enable_shadow_vmcs)
8168 copy_shadow_to_vmcs12(vmx);
8169
7c177938
NHE		 8170 /*
8171 * The nested entry process starts with enforcing various prerequisites
8172 * on vmcs12 as required by the Intel SDM, and act appropriately when
8173 * they fail: As the SDM explains, some conditions should cause the
8174 * instruction to fail, while others will cause the instruction to seem
8175 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8176 * To speed up the normal (success) code path, we should avoid checking
8177 * for misconfigurations which will anyway be caught by the processor
8178 * when using the merged vmcs02.
8179 */
8180 if (vmcs12->launch_state == launch) {
8181 nested_vmx_failValid(vcpu,
8182 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8183 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8184 return 1;
8185 }
8186
6dfacadd
JK		 8187 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8188 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8189 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8190 return 1;
8191 }
8192
7c177938 8193 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8194 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8195 /*TODO: Also verify bits beyond physical address width are 0*/
8196 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8197 return 1;
8198 }
8199
8200 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
bc39c4db 8201 !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
7c177938
NHE		 8202 /*TODO: Also verify bits beyond physical address width are 0*/
8203 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8204 return 1;
8205 }
8206
8207 if (vmcs12->vm_entry_msr_load_count > 0 ||
8208 vmcs12->vm_exit_msr_load_count > 0 ||
8209 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8210 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8211 __func__);
7c177938
NHE		 8212 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8213 return 1;
8214 }
8215
8216 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8217 nested_vmx_true_procbased_ctls_low,
8218 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8219 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8220 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8221 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8222 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8223 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8224 nested_vmx_true_exit_ctls_low,
8225 nested_vmx_exit_ctls_high) ||
7c177938 8226 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8227 nested_vmx_true_entry_ctls_low,
8228 nested_vmx_entry_ctls_high))
7c177938
NHE		 8229 {
8230 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8231 return 1;
8232 }
8233
8234 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8235 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8236 nested_vmx_failValid(vcpu,
8237 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8238 return 1;
8239 }
8240
92fbc7b1 8241 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8242 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8243 nested_vmx_entry_failure(vcpu, vmcs12,
8244 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8245 return 1;
8246 }
8247 if (vmcs12->vmcs_link_pointer != -1ull) {
8248 nested_vmx_entry_failure(vcpu, vmcs12,
8249 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8250 return 1;
8251 }
8252
384bb783 8253 /*
cb0c8cda 8254 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8255 * are performed on the field for the IA32_EFER MSR:
8256 * - Bits reserved in the IA32_EFER MSR must be 0.
8257 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8258 * the IA-32e mode guest VM-exit control. It must also be identical
8259 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8260 * CR0.PG) is 1.
8261 */
8262 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8263 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8264 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8265 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8266 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8267 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8268 nested_vmx_entry_failure(vcpu, vmcs12,
8269 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8270 return 1;
8271 }
8272 }
8273
8274 /*
8275 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8276 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8277 * the values of the LMA and LME bits in the field must each be that of
8278 * the host address-space size VM-exit control.
8279 */
8280 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8281 ia32e = (vmcs12->vm_exit_controls &
8282 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8283 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8284 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8285 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8286 nested_vmx_entry_failure(vcpu, vmcs12,
8287 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8288 return 1;
8289 }
8290 }
8291
7c177938
NHE		 8292 /*
8293 * We're finally done with prerequisite checking, and can start with
8294 * the nested entry.
8295 */
8296
cd232ad0
NHE		 8297 vmcs02 = nested_get_current_vmcs02(vmx);
8298 if (!vmcs02)
8299 return -ENOMEM;
8300
8301 enter_guest_mode(vcpu);
8302
8303 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8304
2996fca0
JK		 8305 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8306 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8307
cd232ad0
NHE		 8308 cpu = get_cpu();
8309 vmx->loaded_vmcs = vmcs02;
8310 vmx_vcpu_put(vcpu);
8311 vmx_vcpu_load(vcpu, cpu);
8312 vcpu->cpu = cpu;
8313 put_cpu();
8314
36c3cc42
JK		 8315 vmx_segment_cache_clear(vmx);
8316
cd232ad0
NHE		 8317 vmcs12->launch_state = 1;
8318
8319 prepare_vmcs02(vcpu, vmcs12);
8320
6dfacadd
JK		 8321 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8322 return kvm_emulate_halt(vcpu);
8323
7af40ad3
JK		 8324 vmx->nested.nested_run_pending = 1;
8325
cd232ad0
NHE		 8326 /*
8327 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8328 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8329 * returned as far as L1 is concerned. It will only return (and set
8330 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8331 */
8332 return 1;
8333}
8334
4704d0be
NHE		 8335/*
8336 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8337 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8338 * This function returns the new value we should put in vmcs12.guest_cr0.
8339 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8340 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8341 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8342 * didn't trap the bit, because if L1 did, so would L0).
8343 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8344 * been modified by L2, and L1 knows it. So just leave the old value of
8345 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8346 * isn't relevant, because if L0 traps this bit it can set it to anything.
8347 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8348 * changed these bits, and therefore they need to be updated, but L0
8349 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8350 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8351 */
8352static inline unsigned long
8353vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8354{
8355 return
8356 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8357 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8358 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8359 vcpu->arch.cr0_guest_owned_bits));
8360}
8361
8362static inline unsigned long
8363vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8364{
8365 return
8366 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8367 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8368 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8369 vcpu->arch.cr4_guest_owned_bits));
8370}
8371
5f3d5799
JK		 8372static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8373 struct vmcs12 *vmcs12)
8374{
8375 u32 idt_vectoring;
8376 unsigned int nr;
8377
851eb667 8378 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8379 nr = vcpu->arch.exception.nr;
8380 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8381
8382 if (kvm_exception_is_soft(nr)) {
8383 vmcs12->vm_exit_instruction_len =
8384 vcpu->arch.event_exit_inst_len;
8385 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8386 } else
8387 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8388
8389 if (vcpu->arch.exception.has_error_code) {
8390 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8391 vmcs12->idt_vectoring_error_code =
8392 vcpu->arch.exception.error_code;
8393 }
8394
8395 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8396 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8397 vmcs12->idt_vectoring_info_field =
8398 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8399 } else if (vcpu->arch.interrupt.pending) {
8400 nr = vcpu->arch.interrupt.nr;
8401 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8402
8403 if (vcpu->arch.interrupt.soft) {
8404 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8405 vmcs12->vm_entry_instruction_len =
8406 vcpu->arch.event_exit_inst_len;
8407 } else
8408 idt_vectoring |= INTR_TYPE_EXT_INTR;
8409
8410 vmcs12->idt_vectoring_info_field = idt_vectoring;
8411 }
8412}
8413
b6b8a145
JK		 8414static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8415{
8416 struct vcpu_vmx *vmx = to_vmx(vcpu);
8417
f4124500
JK		 8418 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8419 vmx->nested.preemption_timer_expired) {
8420 if (vmx->nested.nested_run_pending)
8421 return -EBUSY;
8422 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8423 return 0;
8424 }
8425
b6b8a145 8426 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8427 if (vmx->nested.nested_run_pending ||
8428 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8429 return -EBUSY;
8430 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8431 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8432 INTR_INFO_VALID_MASK, 0);
8433 /*
8434 * The NMI-triggered VM exit counts as injection:
8435 * clear this one and block further NMIs.
8436 */
8437 vcpu->arch.nmi_pending = 0;
8438 vmx_set_nmi_mask(vcpu, true);
8439 return 0;
8440 }
8441
8442 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8443 nested_exit_on_intr(vcpu)) {
8444 if (vmx->nested.nested_run_pending)
8445 return -EBUSY;
8446 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8447 }
8448
8449 return 0;
8450}
8451
f4124500
JK		 8452static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8453{
8454 ktime_t remaining =
8455 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8456 u64 value;
8457
8458 if (ktime_to_ns(remaining) <= 0)
8459 return 0;
8460
8461 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8462 do_div(value, 1000000);
8463 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8464}
8465
4704d0be
NHE		 8466/*
8467 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8468 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8469 * and this function updates it to reflect the changes to the guest state while
8470 * L2 was running (and perhaps made some exits which were handled directly by L0
8471 * without going back to L1), and to reflect the exit reason.
8472 * Note that we do not have to copy here all VMCS fields, just those that
8473 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8474 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8475 * which already writes to vmcs12 directly.
8476 */
533558bc
JK		 8477static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8478 u32 exit_reason, u32 exit_intr_info,
8479 unsigned long exit_qualification)
4704d0be
NHE		 8480{
8481 /* update guest state fields: */
8482 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8483 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8484
4704d0be
NHE		 8485 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8486 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8487 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8488
8489 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8490 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8491 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8492 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8493 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8494 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8495 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8496 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8497 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8498 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8499 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8500 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8501 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8502 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8503 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8504 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8505 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8506 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8507 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8508 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8509 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8510 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8511 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8512 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8513 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8514 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8515 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8516 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8517 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8518 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8519 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8520 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8521 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8522 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8523 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8524 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8525
4704d0be
NHE		 8526 vmcs12->guest_interruptibility_info =
8527 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8528 vmcs12->guest_pending_dbg_exceptions =
8529 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8530 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8531 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8532 else
8533 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8534
f4124500
JK		 8535 if (nested_cpu_has_preemption_timer(vmcs12)) {
8536 if (vmcs12->vm_exit_controls &
8537 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8538 vmcs12->vmx_preemption_timer_value =
8539 vmx_get_preemption_timer_value(vcpu);
8540 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8541 }
7854cbca 8542
3633cfc3
NHE		 8543 /*
8544 * In some cases (usually, nested EPT), L2 is allowed to change its
8545 * own CR3 without exiting. If it has changed it, we must keep it.
8546 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8547 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8548 *
8549 * Additionally, restore L2's PDPTR to vmcs12.
8550 */
8551 if (enable_ept) {
8552 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8553 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8554 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8555 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8556 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8557 }
8558
c18911a2
JK		 8559 vmcs12->vm_entry_controls =
8560 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8561 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8562
2996fca0
JK		 8563 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8564 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8565 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8566 }
8567
4704d0be
NHE		 8568 /* TODO: These cannot have changed unless we have MSR bitmaps and
8569 * the relevant bit asks not to trap the change */
b8c07d55 8570 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8571 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8572 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8573 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8574 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8575 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8576 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8577 if (vmx_mpx_supported())
8578 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8579
8580 /* update exit information fields: */
8581
533558bc
JK		 8582 vmcs12->vm_exit_reason = exit_reason;
8583 vmcs12->exit_qualification = exit_qualification;
4704d0be 8584
533558bc 8585 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8586 if ((vmcs12->vm_exit_intr_info &
8587 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8588 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8589 vmcs12->vm_exit_intr_error_code =
8590 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8591 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8592 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8593 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8594
5f3d5799
JK		 8595 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8596 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8597 * instead of reading the real value. */
4704d0be 8598 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8599
8600 /*
8601 * Transfer the event that L0 or L1 may wanted to inject into
8602 * L2 to IDT_VECTORING_INFO_FIELD.
8603 */
8604 vmcs12_save_pending_event(vcpu, vmcs12);
8605 }
8606
8607 /*
8608 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8609 * preserved above and would only end up incorrectly in L1.
8610 */
8611 vcpu->arch.nmi_injected = false;
8612 kvm_clear_exception_queue(vcpu);
8613 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8614}
8615
8616/*
8617 * A part of what we need to when the nested L2 guest exits and we want to
8618 * run its L1 parent, is to reset L1's guest state to the host state specified
8619 * in vmcs12.
8620 * This function is to be called not only on normal nested exit, but also on
8621 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8622 * Failures During or After Loading Guest State").
8623 * This function should be called when the active VMCS is L1's (vmcs01).
8624 */
733568f9
JK		 8625static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8626 struct vmcs12 *vmcs12)
4704d0be 8627{
21feb4eb
ACL		 8628 struct kvm_segment seg;
8629
4704d0be
NHE		 8630 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8631 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8632 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8633 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8634 else
8635 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8636 vmx_set_efer(vcpu, vcpu->arch.efer);
8637
8638 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8639 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8640 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8641 /*
8642 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8643 * actually changed, because it depends on the current state of
8644 * fpu_active (which may have changed).
8645 * Note that vmx_set_cr0 refers to efer set above.
8646 */
9e3e4dbf 8647 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8648 /*
8649 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8650 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8651 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8652 */
8653 update_exception_bitmap(vcpu);
8654 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8655 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8656
8657 /*
8658 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8659 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8660 */
8661 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8662 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8663
29bf08f1 8664 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8665
4704d0be
NHE		 8666 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8667 kvm_mmu_reset_context(vcpu);
8668
feaf0c7d
GN		 8669 if (!enable_ept)
8670 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8671
4704d0be
NHE		 8672 if (enable_vpid) {
8673 /*
8674 * Trivially support vpid by letting L2s share their parent
8675 * L1's vpid. TODO: move to a more elaborate solution, giving
8676 * each L2 its own vpid and exposing the vpid feature to L1.
8677 */
8678 vmx_flush_tlb(vcpu);
8679 }
8680
8681
8682 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8683 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8684 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8685 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8686 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8687
36be0b9d
PB		 8688 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8689 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8690 vmcs_write64(GUEST_BNDCFGS, 0);
8691
44811c02 8692 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8693 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8694 vcpu->arch.pat = vmcs12->host_ia32_pat;
8695 }
4704d0be
NHE		 8696 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8697 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8698 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8699
21feb4eb
ACL		 8700 /* Set L1 segment info according to Intel SDM
8701 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8702 seg = (struct kvm_segment) {
8703 .base = 0,
8704 .limit = 0xFFFFFFFF,
8705 .selector = vmcs12->host_cs_selector,
8706 .type = 11,
8707 .present = 1,
8708 .s = 1,
8709 .g = 1
8710 };
8711 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8712 seg.l = 1;
8713 else
8714 seg.db = 1;
8715 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8716 seg = (struct kvm_segment) {
8717 .base = 0,
8718 .limit = 0xFFFFFFFF,
8719 .type = 3,
8720 .present = 1,
8721 .s = 1,
8722 .db = 1,
8723 .g = 1
8724 };
8725 seg.selector = vmcs12->host_ds_selector;
8726 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8727 seg.selector = vmcs12->host_es_selector;
8728 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8729 seg.selector = vmcs12->host_ss_selector;
8730 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8731 seg.selector = vmcs12->host_fs_selector;
8732 seg.base = vmcs12->host_fs_base;
8733 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8734 seg.selector = vmcs12->host_gs_selector;
8735 seg.base = vmcs12->host_gs_base;
8736 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8737 seg = (struct kvm_segment) {
205befd9 8738 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8739 .limit = 0x67,
8740 .selector = vmcs12->host_tr_selector,
8741 .type = 11,
8742 .present = 1
8743 };
8744 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8745
503cd0c5
JK		 8746 kvm_set_dr(vcpu, 7, 0x400);
8747 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8748}
8749
8750/*
8751 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8752 * and modify vmcs12 to make it see what it would expect to see there if
8753 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8754 */
533558bc
JK		 8755static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8756 u32 exit_intr_info,
8757 unsigned long exit_qualification)
4704d0be
NHE		 8758{
8759 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be
NHE		 8760 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8761
5f3d5799
JK		 8762 /* trying to cancel vmlaunch/vmresume is a bug */
8763 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8764
4704d0be 8765 leave_guest_mode(vcpu);
533558bc
JK		 8766 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8767 exit_qualification);
4704d0be 8768
f3380ca5
WL		 8769 vmx_load_vmcs01(vcpu);
8770
77b0f5d6
BD		 8771 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8772 && nested_exit_intr_ack_set(vcpu)) {
8773 int irq = kvm_cpu_get_interrupt(vcpu);
8774 WARN_ON(irq < 0);
8775 vmcs12->vm_exit_intr_info = irq |
8776 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8777 }
8778
542060ea
JK		 8779 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8780 vmcs12->exit_qualification,
8781 vmcs12->idt_vectoring_info_field,
8782 vmcs12->vm_exit_intr_info,
8783 vmcs12->vm_exit_intr_error_code,
8784 KVM_ISA_VMX);
4704d0be 8785
2961e876
GN		 8786 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8787 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8788 vmx_segment_cache_clear(vmx);
8789
4704d0be
NHE		 8790 /* if no vmcs02 cache requested, remove the one we used */
8791 if (VMCS02_POOL_SIZE == 0)
8792 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8793
8794 load_vmcs12_host_state(vcpu, vmcs12);
8795
27fc51b2 8796 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8797 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8798
8799 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8800 vmx->host_rsp = 0;
8801
8802 /* Unpin physical memory we referred to in vmcs02 */
8803 if (vmx->nested.apic_access_page) {
8804 nested_release_page(vmx->nested.apic_access_page);
8805 vmx->nested.apic_access_page = 0;
8806 }
8807
8808 /*
8809 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8810 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8811 * success or failure flag accordingly.
8812 */
8813 if (unlikely(vmx->fail)) {
8814 vmx->fail = 0;
8815 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8816 } else
8817 nested_vmx_succeed(vcpu);
012f83cb
AG		 8818 if (enable_shadow_vmcs)
8819 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8820
8821 /* in case we halted in L2 */
8822 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8823}
8824
42124925
JK		 8825/*
8826 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8827 */
8828static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8829{
8830 if (is_guest_mode(vcpu))
533558bc 8831 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8832 free_nested(to_vmx(vcpu));
8833}
8834
7c177938
NHE		 8835/*
8836 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8837 * 23.7 "VM-entry failures during or after loading guest state" (this also
8838 * lists the acceptable exit-reason and exit-qualification parameters).
8839 * It should only be called before L2 actually succeeded to run, and when
8840 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8841 */
8842static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8843 struct vmcs12 *vmcs12,
8844 u32 reason, unsigned long qualification)
8845{
8846 load_vmcs12_host_state(vcpu, vmcs12);
8847 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8848 vmcs12->exit_qualification = qualification;
8849 nested_vmx_succeed(vcpu);
012f83cb
AG		 8850 if (enable_shadow_vmcs)
8851 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8852}
8853
8a76d7f2
JR		 8854static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8855 struct x86_instruction_info *info,
8856 enum x86_intercept_stage stage)
8857{
8858 return X86EMUL_CONTINUE;
8859}
8860
ae97a3b8
RK		 8861void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
8862{
8863}
8864
cbdd1bea 8865static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8866 .cpu_has_kvm_support = cpu_has_kvm_support,
8867 .disabled_by_bios = vmx_disabled_by_bios,
8868 .hardware_setup = hardware_setup,
8869 .hardware_unsetup = hardware_unsetup,
002c7f7c 8870 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8871 .hardware_enable = hardware_enable,
8872 .hardware_disable = hardware_disable,
04547156 8873 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8874
8875 .vcpu_create = vmx_create_vcpu,
8876 .vcpu_free = vmx_free_vcpu,
04d2cc77 8877 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8878
04d2cc77 8879 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8880 .vcpu_load = vmx_vcpu_load,
8881 .vcpu_put = vmx_vcpu_put,
8882
c8639010 8883 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8884 .get_msr = vmx_get_msr,
8885 .set_msr = vmx_set_msr,
8886 .get_segment_base = vmx_get_segment_base,
8887 .get_segment = vmx_get_segment,
8888 .set_segment = vmx_set_segment,
2e4d2653 8889 .get_cpl = vmx_get_cpl,
6aa8b732 8890 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8891 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8892 .decache_cr3 = vmx_decache_cr3,
25c4c276 8893 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8894 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8895 .set_cr3 = vmx_set_cr3,
8896 .set_cr4 = vmx_set_cr4,
6aa8b732 8897 .set_efer = vmx_set_efer,
6aa8b732
AK		 8898 .get_idt = vmx_get_idt,
8899 .set_idt = vmx_set_idt,
8900 .get_gdt = vmx_get_gdt,
8901 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8902 .get_dr6 = vmx_get_dr6,
8903 .set_dr6 = vmx_set_dr6,
020df079 8904 .set_dr7 = vmx_set_dr7,
81908bf4 8905 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8906 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8907 .get_rflags = vmx_get_rflags,
8908 .set_rflags = vmx_set_rflags,
02daab21 8909 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8910
8911 .tlb_flush = vmx_flush_tlb,
6aa8b732 8912
6aa8b732 8913 .run = vmx_vcpu_run,
6062d012 8914 .handle_exit = vmx_handle_exit,
6aa8b732 8915 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8916 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8917 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8918 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8919 .set_irq = vmx_inject_irq,
95ba8273 8920 .set_nmi = vmx_inject_nmi,
298101da 8921 .queue_exception = vmx_queue_exception,
b463a6f7 8922 .cancel_injection = vmx_cancel_injection,
78646121 8923 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8924 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8925 .get_nmi_mask = vmx_get_nmi_mask,
8926 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8927 .enable_nmi_window = enable_nmi_window,
8928 .enable_irq_window = enable_irq_window,
8929 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8930 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8931 .vm_has_apicv = vmx_vm_has_apicv,
8932 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8933 .hwapic_irr_update = vmx_hwapic_irr_update,
8934 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8935 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8936 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8937
cbc94022 8938 .set_tss_addr = vmx_set_tss_addr,
67253af5 8939 .get_tdp_level = get_ept_level,
4b12f0de 8940 .get_mt_mask = vmx_get_mt_mask,
229456fc 8941
586f9607 8942 .get_exit_info = vmx_get_exit_info,
586f9607 8943
17cc3935 8944 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8945
8946 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8947
8948 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8949 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8950
8951 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8952
8953 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8954
4051b188 8955 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8956 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8957 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8958 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8959 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8960 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8961
8962 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8963
8964 .check_intercept = vmx_check_intercept,
a547c6db 8965 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8966 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8967
8968 .check_nested_events = vmx_check_nested_events,
ae97a3b8
RK		 8969
8970 .sched_in = vmx_sched_in,
6aa8b732
AK		 8971};
8972
8973static int __init vmx_init(void)
8974{
8d14695f 8975 int r, i, msr;
26bb0981
AK		 8976
8977 rdmsrl_safe(MSR_EFER, &host_efer);
8978
03916db9 8979 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
26bb0981 8980 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8981
3e7c73e9 8982 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8983 if (!vmx_io_bitmap_a)
8984 return -ENOMEM;
8985
2106a548
GC		 8986 r = -ENOMEM;
8987
3e7c73e9 8988 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8989 if (!vmx_io_bitmap_b)
fdef3ad1 8990 goto out;
fdef3ad1 8991
5897297b 8992 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8993 if (!vmx_msr_bitmap_legacy)
25c5f225 8994 goto out1;
2106a548 8995
8d14695f
YZ		 8996 vmx_msr_bitmap_legacy_x2apic =
8997 (unsigned long *)__get_free_page(GFP_KERNEL);
8998 if (!vmx_msr_bitmap_legacy_x2apic)
8999 goto out2;
25c5f225 9000
5897297b 9001 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 9002 if (!vmx_msr_bitmap_longmode)
8d14695f 9003 goto out3;
2106a548 9004
8d14695f
YZ		 9005 vmx_msr_bitmap_longmode_x2apic =
9006 (unsigned long *)__get_free_page(GFP_KERNEL);
9007 if (!vmx_msr_bitmap_longmode_x2apic)
9008 goto out4;
4607c2d7
AG		 9009 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9010 if (!vmx_vmread_bitmap)
9011 goto out5;
9012
9013 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
9014 if (!vmx_vmwrite_bitmap)
9015 goto out6;
9016
9017 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
9018 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 9019
fdef3ad1
HQ		 9020 /*
9021 * Allow direct access to the PC debug port (it is often used for I/O
9022 * delays, but the vmexits simply slow things down).
9023 */
3e7c73e9
AK		 9024 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
9025 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 9026
3e7c73e9 9027 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 9028
5897297b
AK		 9029 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
9030 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 9031
2384d2b3
SY		 9032 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
9033
0ee75bea
AK		 9034 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
9035 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 9036 if (r)
4607c2d7 9037 goto out7;
25c5f225 9038
8f536b76
ZY		 9039#ifdef CONFIG_KEXEC
9040 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
9041 crash_vmclear_local_loaded_vmcss);
9042#endif
9043
5897297b
AK		 9044 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
9045 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
9046 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
9047 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
9048 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
9049 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 9050 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
9051
8d14695f
YZ		 9052 memcpy(vmx_msr_bitmap_legacy_x2apic,
9053 vmx_msr_bitmap_legacy, PAGE_SIZE);
9054 memcpy(vmx_msr_bitmap_longmode_x2apic,
9055 vmx_msr_bitmap_longmode, PAGE_SIZE);
9056
01e439be 9057 if (enable_apicv) {
8d14695f
YZ		 9058 for (msr = 0x800; msr <= 0x8ff; msr++)
9059 vmx_disable_intercept_msr_read_x2apic(msr);
9060
9061 /* According SDM, in x2apic mode, the whole id reg is used.
9062 * But in KVM, it only use the highest eight bits. Need to
9063 * intercept it */
9064 vmx_enable_intercept_msr_read_x2apic(0x802);
9065 /* TMCCT */
9066 vmx_enable_intercept_msr_read_x2apic(0x839);
9067 /* TPR */
9068 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9069 /* EOI */
9070 vmx_disable_intercept_msr_write_x2apic(0x80b);
9071 /* SELF-IPI */
9072 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9073 }
fdef3ad1 9074
089d034e 9075 if (enable_ept) {
3f6d8c8a
XH		 9076 kvm_mmu_set_mask_ptes(0ull,
9077 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9078 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9079 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9080 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9081 kvm_enable_tdp();
9082 } else
9083 kvm_disable_tdp();
1439442c 9084
fdef3ad1
HQ		 9085 return 0;
9086
4607c2d7
AG		 9087out7:
9088 free_page((unsigned long)vmx_vmwrite_bitmap);
9089out6:
9090 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9091out5:
9092 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9093out4:
5897297b 9094 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9095out3:
9096 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9097out2:
5897297b 9098 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9099out1:
3e7c73e9 9100 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9101out:
3e7c73e9 9102 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9103 return r;
6aa8b732
AK		 9104}
9105
9106static void __exit vmx_exit(void)
9107{
8d14695f
YZ		 9108 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9109 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9110 free_page((unsigned long)vmx_msr_bitmap_legacy);
9111 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9112 free_page((unsigned long)vmx_io_bitmap_b);
9113 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9114 free_page((unsigned long)vmx_vmwrite_bitmap);
9115 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9116
8f536b76 9117#ifdef CONFIG_KEXEC
3b63a43f 9118 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
8f536b76
ZY		 9119 synchronize_rcu();
9120#endif
9121
cb498ea2 9122 kvm_exit();
6aa8b732
AK		 9123}
9124
9125module_init(vmx_init)
9126module_exit(vmx_exit)
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