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KVM: x86: Break kvm_for_each_vcpu loop after finding the VP_INDEX
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
da8999d3 444 u64 msr_host_bndcfgs;
d77c26fc 445 } host_state;
9c8cba37 446 struct {
7ffd92c5 447 int vm86_active;
78ac8b47 448 ulong save_rflags;
f5f7b2fe
AK		 449 struct kvm_segment segs[8];
450 } rmode;
451 struct {
452 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 453 struct kvm_save_segment {
454 u16 selector;
455 unsigned long base;
456 u32 limit;
457 u32 ar;
f5f7b2fe 458 } seg[8];
2fb92db1 459 } segment_cache;
2384d2b3 460 int vpid;
04fa4d32 461 bool emulation_required;
3b86cd99
JK		 462
463 /* Support for vnmi-less CPUs */
464 int soft_vnmi_blocked;
465 ktime_t entry_time;
466 s64 vnmi_blocked_time;
a0861c02 467 u32 exit_reason;
4e47c7a6
SY		 468
469 bool rdtscp_enabled;
ec378aee 470
01e439be
YZ		 471 /* Posted interrupt descriptor */
472 struct pi_desc pi_desc;
473
ec378aee
NHE		 474 /* Support for a guest hypervisor (nested VMX) */
475 struct nested_vmx nested;
a2fa3e9f
GH		 476};
477
2fb92db1
AK		 478enum segment_cache_field {
479 SEG_FIELD_SEL = 0,
480 SEG_FIELD_BASE = 1,
481 SEG_FIELD_LIMIT = 2,
482 SEG_FIELD_AR = 3,
483
484 SEG_FIELD_NR = 4
485};
486
a2fa3e9f
GH		 487static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
488{
fb3f0f51 489 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 490}
491
22bd0358
NHE		 492#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
493#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
494#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
495 [number##_HIGH] = VMCS12_OFFSET(name)+4
496
4607c2d7
AG		 497
498static const unsigned long shadow_read_only_fields[] = {
499 /*
500 * We do NOT shadow fields that are modified when L0
501 * traps and emulates any vmx instruction (e.g. VMPTRLD,
502 * VMXON...) executed by L1.
503 * For example, VM_INSTRUCTION_ERROR is read
504 * by L1 if a vmx instruction fails (part of the error path).
505 * Note the code assumes this logic. If for some reason
506 * we start shadowing these fields then we need to
507 * force a shadow sync when L0 emulates vmx instructions
508 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
509 * by nested_vmx_failValid)
510 */
511 VM_EXIT_REASON,
512 VM_EXIT_INTR_INFO,
513 VM_EXIT_INSTRUCTION_LEN,
514 IDT_VECTORING_INFO_FIELD,
515 IDT_VECTORING_ERROR_CODE,
516 VM_EXIT_INTR_ERROR_CODE,
517 EXIT_QUALIFICATION,
518 GUEST_LINEAR_ADDRESS,
519 GUEST_PHYSICAL_ADDRESS
520};
521static const int max_shadow_read_only_fields =
522 ARRAY_SIZE(shadow_read_only_fields);
523
524static const unsigned long shadow_read_write_fields[] = {
525 GUEST_RIP,
526 GUEST_RSP,
527 GUEST_CR0,
528 GUEST_CR3,
529 GUEST_CR4,
530 GUEST_INTERRUPTIBILITY_INFO,
531 GUEST_RFLAGS,
532 GUEST_CS_SELECTOR,
533 GUEST_CS_AR_BYTES,
534 GUEST_CS_LIMIT,
535 GUEST_CS_BASE,
536 GUEST_ES_BASE,
537 CR0_GUEST_HOST_MASK,
538 CR0_READ_SHADOW,
539 CR4_READ_SHADOW,
540 TSC_OFFSET,
541 EXCEPTION_BITMAP,
542 CPU_BASED_VM_EXEC_CONTROL,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 VM_ENTRY_INTR_INFO_FIELD,
545 VM_ENTRY_INSTRUCTION_LEN,
546 VM_ENTRY_EXCEPTION_ERROR_CODE,
547 HOST_FS_BASE,
548 HOST_GS_BASE,
549 HOST_FS_SELECTOR,
550 HOST_GS_SELECTOR
551};
552static const int max_shadow_read_write_fields =
553 ARRAY_SIZE(shadow_read_write_fields);
554
772e0318 555static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 556 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
557 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
558 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
559 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
560 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
561 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
562 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
563 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
564 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
565 FIELD(HOST_ES_SELECTOR, host_es_selector),
566 FIELD(HOST_CS_SELECTOR, host_cs_selector),
567 FIELD(HOST_SS_SELECTOR, host_ss_selector),
568 FIELD(HOST_DS_SELECTOR, host_ds_selector),
569 FIELD(HOST_FS_SELECTOR, host_fs_selector),
570 FIELD(HOST_GS_SELECTOR, host_gs_selector),
571 FIELD(HOST_TR_SELECTOR, host_tr_selector),
572 FIELD64(IO_BITMAP_A, io_bitmap_a),
573 FIELD64(IO_BITMAP_B, io_bitmap_b),
574 FIELD64(MSR_BITMAP, msr_bitmap),
575 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
576 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
577 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
578 FIELD64(TSC_OFFSET, tsc_offset),
579 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
580 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
581 FIELD64(EPT_POINTER, ept_pointer),
582 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
583 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
584 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
585 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
586 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
587 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
588 FIELD64(GUEST_PDPTR0, guest_pdptr0),
589 FIELD64(GUEST_PDPTR1, guest_pdptr1),
590 FIELD64(GUEST_PDPTR2, guest_pdptr2),
591 FIELD64(GUEST_PDPTR3, guest_pdptr3),
592 FIELD64(HOST_IA32_PAT, host_ia32_pat),
593 FIELD64(HOST_IA32_EFER, host_ia32_efer),
594 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
595 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
596 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
597 FIELD(EXCEPTION_BITMAP, exception_bitmap),
598 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
599 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
600 FIELD(CR3_TARGET_COUNT, cr3_target_count),
601 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
602 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
603 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
604 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
605 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
606 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
607 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
608 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
609 FIELD(TPR_THRESHOLD, tpr_threshold),
610 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
611 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
612 FIELD(VM_EXIT_REASON, vm_exit_reason),
613 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
614 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
615 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
616 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
617 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
618 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
619 FIELD(GUEST_ES_LIMIT, guest_es_limit),
620 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
621 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
622 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
623 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
624 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
625 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
626 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
627 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
628 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
629 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
630 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
631 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
632 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
633 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
634 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
635 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
636 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
637 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
638 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
639 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
640 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 641 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 642 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
643 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
644 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
645 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
646 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
647 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
648 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
649 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
650 FIELD(EXIT_QUALIFICATION, exit_qualification),
651 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
652 FIELD(GUEST_CR0, guest_cr0),
653 FIELD(GUEST_CR3, guest_cr3),
654 FIELD(GUEST_CR4, guest_cr4),
655 FIELD(GUEST_ES_BASE, guest_es_base),
656 FIELD(GUEST_CS_BASE, guest_cs_base),
657 FIELD(GUEST_SS_BASE, guest_ss_base),
658 FIELD(GUEST_DS_BASE, guest_ds_base),
659 FIELD(GUEST_FS_BASE, guest_fs_base),
660 FIELD(GUEST_GS_BASE, guest_gs_base),
661 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
662 FIELD(GUEST_TR_BASE, guest_tr_base),
663 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
664 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
665 FIELD(GUEST_DR7, guest_dr7),
666 FIELD(GUEST_RSP, guest_rsp),
667 FIELD(GUEST_RIP, guest_rip),
668 FIELD(GUEST_RFLAGS, guest_rflags),
669 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
670 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
671 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
672 FIELD(HOST_CR0, host_cr0),
673 FIELD(HOST_CR3, host_cr3),
674 FIELD(HOST_CR4, host_cr4),
675 FIELD(HOST_FS_BASE, host_fs_base),
676 FIELD(HOST_GS_BASE, host_gs_base),
677 FIELD(HOST_TR_BASE, host_tr_base),
678 FIELD(HOST_GDTR_BASE, host_gdtr_base),
679 FIELD(HOST_IDTR_BASE, host_idtr_base),
680 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
681 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
682 FIELD(HOST_RSP, host_rsp),
683 FIELD(HOST_RIP, host_rip),
684};
685static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
686
687static inline short vmcs_field_to_offset(unsigned long field)
688{
689 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
690 return -1;
691 return vmcs_field_to_offset_table[field];
692}
693
a9d30f33
NHE		 694static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
695{
696 return to_vmx(vcpu)->nested.current_vmcs12;
697}
698
699static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
700{
701 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 702 if (is_error_page(page))
a9d30f33 703 return NULL;
32cad84f 704
a9d30f33
NHE		 705 return page;
706}
707
708static void nested_release_page(struct page *page)
709{
710 kvm_release_page_dirty(page);
711}
712
713static void nested_release_page_clean(struct page *page)
714{
715 kvm_release_page_clean(page);
716}
717
bfd0a56b 718static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 719static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 720static void kvm_cpu_vmxon(u64 addr);
721static void kvm_cpu_vmxoff(void);
776e58ea 722static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 723static void vmx_set_segment(struct kvm_vcpu *vcpu,
724 struct kvm_segment *var, int seg);
725static void vmx_get_segment(struct kvm_vcpu *vcpu,
726 struct kvm_segment *var, int seg);
d99e4152
GN		 727static bool guest_state_valid(struct kvm_vcpu *vcpu);
728static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 729static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 730static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 731static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 732
6aa8b732
AK		 733static DEFINE_PER_CPU(struct vmcs *, vmxarea);
734static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 735/*
736 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
737 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
738 */
739static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 740static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 741
3e7c73e9
AK		 742static unsigned long *vmx_io_bitmap_a;
743static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 744static unsigned long *vmx_msr_bitmap_legacy;
745static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 746static unsigned long *vmx_msr_bitmap_legacy_x2apic;
747static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 748static unsigned long *vmx_vmread_bitmap;
749static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 750
110312c8 751static bool cpu_has_load_ia32_efer;
8bf00a52 752static bool cpu_has_load_perf_global_ctrl;
110312c8 753
2384d2b3
SY		 754static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
755static DEFINE_SPINLOCK(vmx_vpid_lock);
756
1c3d14fe 757static struct vmcs_config {
6aa8b732
AK		 758 int size;
759 int order;
760 u32 revision_id;
1c3d14fe
YS		 761 u32 pin_based_exec_ctrl;
762 u32 cpu_based_exec_ctrl;
f78e0e2e 763 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 764 u32 vmexit_ctrl;
765 u32 vmentry_ctrl;
766} vmcs_config;
6aa8b732 767
efff9e53 768static struct vmx_capability {
d56f546d
SY		 769 u32 ept;
770 u32 vpid;
771} vmx_capability;
772
6aa8b732
AK		 773#define VMX_SEGMENT_FIELD(seg) \
774 [VCPU_SREG_##seg] = { \
775 .selector = GUEST_##seg##_SELECTOR, \
776 .base = GUEST_##seg##_BASE, \
777 .limit = GUEST_##seg##_LIMIT, \
778 .ar_bytes = GUEST_##seg##_AR_BYTES, \
779 }
780
772e0318 781static const struct kvm_vmx_segment_field {
6aa8b732
AK		 782 unsigned selector;
783 unsigned base;
784 unsigned limit;
785 unsigned ar_bytes;
786} kvm_vmx_segment_fields[] = {
787 VMX_SEGMENT_FIELD(CS),
788 VMX_SEGMENT_FIELD(DS),
789 VMX_SEGMENT_FIELD(ES),
790 VMX_SEGMENT_FIELD(FS),
791 VMX_SEGMENT_FIELD(GS),
792 VMX_SEGMENT_FIELD(SS),
793 VMX_SEGMENT_FIELD(TR),
794 VMX_SEGMENT_FIELD(LDTR),
795};
796
26bb0981
AK		 797static u64 host_efer;
798
6de4f3ad
AK		 799static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
800
4d56c8a7 801/*
8c06585d 802 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 803 * away by decrementing the array size.
804 */
6aa8b732 805static const u32 vmx_msr_index[] = {
05b3e0c2 806#ifdef CONFIG_X86_64
44ea2b17 807 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 808#endif
8c06585d 809 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 810};
9d8f549d 811#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 812
31299944 813static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 814{
815 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
816 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 817 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 818}
819
31299944 820static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 821{
822 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
823 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 824 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 825}
826
31299944 827static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 828{
829 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
830 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 831 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 832}
833
31299944 834static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 835{
836 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
837 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
838}
839
31299944 840static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 841{
842 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
843 INTR_INFO_VALID_MASK)) ==
844 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
845}
846
31299944 847static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 848{
04547156 849 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 850}
851
31299944 852static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 853{
04547156 854 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 855}
856
31299944 857static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 858{
04547156 859 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 860}
861
31299944 862static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 863{
04547156
SY		 864 return vmcs_config.cpu_based_exec_ctrl &
865 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 866}
867
774ead3a 868static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 869{
04547156
SY		 870 return vmcs_config.cpu_based_2nd_exec_ctrl &
871 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
872}
873
8d14695f
YZ		 874static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
878}
879
83d4c286
YZ		 880static inline bool cpu_has_vmx_apic_register_virt(void)
881{
882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_APIC_REGISTER_VIRT;
884}
885
c7c9c56c
YZ		 886static inline bool cpu_has_vmx_virtual_intr_delivery(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
890}
891
01e439be
YZ		 892static inline bool cpu_has_vmx_posted_intr(void)
893{
894 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
895}
896
897static inline bool cpu_has_vmx_apicv(void)
898{
899 return cpu_has_vmx_apic_register_virt() &&
900 cpu_has_vmx_virtual_intr_delivery() &&
901 cpu_has_vmx_posted_intr();
902}
903
04547156
SY		 904static inline bool cpu_has_vmx_flexpriority(void)
905{
906 return cpu_has_vmx_tpr_shadow() &&
907 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 908}
909
e799794e
MT		 910static inline bool cpu_has_vmx_ept_execute_only(void)
911{
31299944 912 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 913}
914
915static inline bool cpu_has_vmx_eptp_uncacheable(void)
916{
31299944 917 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 918}
919
920static inline bool cpu_has_vmx_eptp_writeback(void)
921{
31299944 922 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 923}
924
925static inline bool cpu_has_vmx_ept_2m_page(void)
926{
31299944 927 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 928}
929
878403b7
SY		 930static inline bool cpu_has_vmx_ept_1g_page(void)
931{
31299944 932 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 933}
934
4bc9b982
SY		 935static inline bool cpu_has_vmx_ept_4levels(void)
936{
937 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
938}
939
83c3a331
XH		 940static inline bool cpu_has_vmx_ept_ad_bits(void)
941{
942 return vmx_capability.ept & VMX_EPT_AD_BIT;
943}
944
31299944 945static inline bool cpu_has_vmx_invept_context(void)
d56f546d 946{
31299944 947 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 948}
949
31299944 950static inline bool cpu_has_vmx_invept_global(void)
d56f546d 951{
31299944 952 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 953}
954
518c8aee
GJ		 955static inline bool cpu_has_vmx_invvpid_single(void)
956{
957 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
958}
959
b9d762fa
GJ		 960static inline bool cpu_has_vmx_invvpid_global(void)
961{
962 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
963}
964
31299944 965static inline bool cpu_has_vmx_ept(void)
d56f546d 966{
04547156
SY		 967 return vmcs_config.cpu_based_2nd_exec_ctrl &
968 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 969}
970
31299944 971static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 972{
973 return vmcs_config.cpu_based_2nd_exec_ctrl &
974 SECONDARY_EXEC_UNRESTRICTED_GUEST;
975}
976
31299944 977static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 978{
979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
981}
982
31299944 983static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 984{
6d3e435e 985 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 986}
987
31299944 988static inline bool cpu_has_vmx_vpid(void)
2384d2b3 989{
04547156
SY		 990 return vmcs_config.cpu_based_2nd_exec_ctrl &
991 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 992}
993
31299944 994static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 995{
996 return vmcs_config.cpu_based_2nd_exec_ctrl &
997 SECONDARY_EXEC_RDTSCP;
998}
999
ad756a16
MJ		 1000static inline bool cpu_has_vmx_invpcid(void)
1001{
1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_INVPCID;
1004}
1005
31299944 1006static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1007{
1008 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1009}
1010
f5f48ee1
SY		 1011static inline bool cpu_has_vmx_wbinvd_exit(void)
1012{
1013 return vmcs_config.cpu_based_2nd_exec_ctrl &
1014 SECONDARY_EXEC_WBINVD_EXITING;
1015}
1016
abc4fc58
AG		 1017static inline bool cpu_has_vmx_shadow_vmcs(void)
1018{
1019 u64 vmx_msr;
1020 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1021 /* check if the cpu supports writing r/o exit information fields */
1022 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1023 return false;
1024
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_SHADOW_VMCS;
1027}
1028
04547156
SY		 1029static inline bool report_flexpriority(void)
1030{
1031 return flexpriority_enabled;
1032}
1033
fe3ef05c
NHE		 1034static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1035{
1036 return vmcs12->cpu_based_vm_exec_control & bit;
1037}
1038
1039static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1040{
1041 return (vmcs12->cpu_based_vm_exec_control &
1042 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1043 (vmcs12->secondary_vm_exec_control & bit);
1044}
1045
f5c4368f 1046static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1047{
1048 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1049}
1050
155a97a3
NHE		 1051static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1052{
1053 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1054}
1055
644d711a
NHE		 1056static inline bool is_exception(u32 intr_info)
1057{
1058 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1059 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1060}
1061
533558bc
JK		 1062static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1063 u32 exit_intr_info,
1064 unsigned long exit_qualification);
7c177938
NHE		 1065static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1066 struct vmcs12 *vmcs12,
1067 u32 reason, unsigned long qualification);
1068
8b9cf98c 1069static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1070{
1071 int i;
1072
a2fa3e9f 1073 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1074 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1075 return i;
1076 return -1;
1077}
1078
2384d2b3
SY		 1079static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1080{
1081 struct {
1082 u64 vpid : 16;
1083 u64 rsvd : 48;
1084 u64 gva;
1085 } operand = { vpid, 0, gva };
1086
4ecac3fd 1087 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1088 /* CF==1 or ZF==1 --> rc = -1 */
1089 "; ja 1f ; ud2 ; 1:"
1090 : : "a"(&operand), "c"(ext) : "cc", "memory");
1091}
1092
1439442c
SY		 1093static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1094{
1095 struct {
1096 u64 eptp, gpa;
1097 } operand = {eptp, gpa};
1098
4ecac3fd 1099 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1100 /* CF==1 or ZF==1 --> rc = -1 */
1101 "; ja 1f ; ud2 ; 1:\n"
1102 : : "a" (&operand), "c" (ext) : "cc", "memory");
1103}
1104
26bb0981 1105static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1106{
1107 int i;
1108
8b9cf98c 1109 i = __find_msr_index(vmx, msr);
a75beee6 1110 if (i >= 0)
a2fa3e9f 1111 return &vmx->guest_msrs[i];
8b6d44c7 1112 return NULL;
7725f0ba
AK		 1113}
1114
6aa8b732
AK		 1115static void vmcs_clear(struct vmcs *vmcs)
1116{
1117 u64 phys_addr = __pa(vmcs);
1118 u8 error;
1119
4ecac3fd 1120 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1121 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1122 : "cc", "memory");
1123 if (error)
1124 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1125 vmcs, phys_addr);
1126}
1127
d462b819
NHE		 1128static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1129{
1130 vmcs_clear(loaded_vmcs->vmcs);
1131 loaded_vmcs->cpu = -1;
1132 loaded_vmcs->launched = 0;
1133}
1134
7725b894
DX		 1135static void vmcs_load(struct vmcs *vmcs)
1136{
1137 u64 phys_addr = __pa(vmcs);
1138 u8 error;
1139
1140 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1141 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1142 : "cc", "memory");
1143 if (error)
2844d849 1144 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1145 vmcs, phys_addr);
1146}
1147
8f536b76
ZY		 1148#ifdef CONFIG_KEXEC
1149/*
1150 * This bitmap is used to indicate whether the vmclear
1151 * operation is enabled on all cpus. All disabled by
1152 * default.
1153 */
1154static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1155
1156static inline void crash_enable_local_vmclear(int cpu)
1157{
1158 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline void crash_disable_local_vmclear(int cpu)
1162{
1163 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static inline int crash_local_vmclear_enabled(int cpu)
1167{
1168 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1169}
1170
1171static void crash_vmclear_local_loaded_vmcss(void)
1172{
1173 int cpu = raw_smp_processor_id();
1174 struct loaded_vmcs *v;
1175
1176 if (!crash_local_vmclear_enabled(cpu))
1177 return;
1178
1179 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1180 loaded_vmcss_on_cpu_link)
1181 vmcs_clear(v->vmcs);
1182}
1183#else
1184static inline void crash_enable_local_vmclear(int cpu) { }
1185static inline void crash_disable_local_vmclear(int cpu) { }
1186#endif /* CONFIG_KEXEC */
1187
d462b819 1188static void __loaded_vmcs_clear(void *arg)
6aa8b732 1189{
d462b819 1190 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1191 int cpu = raw_smp_processor_id();
6aa8b732 1192
d462b819
NHE		 1193 if (loaded_vmcs->cpu != cpu)
1194 return; /* vcpu migration can race with cpu offline */
1195 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1196 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1197 crash_disable_local_vmclear(cpu);
d462b819 1198 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1199
1200 /*
1201 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1202 * is before setting loaded_vmcs->vcpu to -1 which is done in
1203 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1204 * then adds the vmcs into percpu list before it is deleted.
1205 */
1206 smp_wmb();
1207
d462b819 1208 loaded_vmcs_init(loaded_vmcs);
8f536b76 1209 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1210}
1211
d462b819 1212static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1213{
e6c7d321
XG		 1214 int cpu = loaded_vmcs->cpu;
1215
1216 if (cpu != -1)
1217 smp_call_function_single(cpu,
1218 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1219}
1220
1760dd49 1221static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1222{
1223 if (vmx->vpid == 0)
1224 return;
1225
518c8aee
GJ		 1226 if (cpu_has_vmx_invvpid_single())
1227 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1228}
1229
b9d762fa
GJ		 1230static inline void vpid_sync_vcpu_global(void)
1231{
1232 if (cpu_has_vmx_invvpid_global())
1233 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1234}
1235
1236static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1237{
1238 if (cpu_has_vmx_invvpid_single())
1760dd49 1239 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1240 else
1241 vpid_sync_vcpu_global();
1242}
1243
1439442c
SY		 1244static inline void ept_sync_global(void)
1245{
1246 if (cpu_has_vmx_invept_global())
1247 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1248}
1249
1250static inline void ept_sync_context(u64 eptp)
1251{
089d034e 1252 if (enable_ept) {
1439442c
SY		 1253 if (cpu_has_vmx_invept_context())
1254 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1255 else
1256 ept_sync_global();
1257 }
1258}
1259
96304217 1260static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1261{
5e520e62 1262 unsigned long value;
6aa8b732 1263
5e520e62
AK		 1264 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1265 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1266 return value;
1267}
1268
96304217 1269static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1275{
1276 return vmcs_readl(field);
1277}
1278
96304217 1279static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1280{
05b3e0c2 1281#ifdef CONFIG_X86_64
6aa8b732
AK		 1282 return vmcs_readl(field);
1283#else
1284 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1285#endif
1286}
1287
e52de1b8
AK		 1288static noinline void vmwrite_error(unsigned long field, unsigned long value)
1289{
1290 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1291 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1292 dump_stack();
1293}
1294
6aa8b732
AK		 1295static void vmcs_writel(unsigned long field, unsigned long value)
1296{
1297 u8 error;
1298
4ecac3fd 1299 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1300 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1301 if (unlikely(error))
1302 vmwrite_error(field, value);
6aa8b732
AK		 1303}
1304
1305static void vmcs_write16(unsigned long field, u16 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write32(unsigned long field, u32 value)
1311{
1312 vmcs_writel(field, value);
1313}
1314
1315static void vmcs_write64(unsigned long field, u64 value)
1316{
6aa8b732 1317 vmcs_writel(field, value);
7682f2d0 1318#ifndef CONFIG_X86_64
6aa8b732
AK		 1319 asm volatile ("");
1320 vmcs_writel(field+1, value >> 32);
1321#endif
1322}
1323
2ab455cc
AL		 1324static void vmcs_clear_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) & ~mask);
1327}
1328
1329static void vmcs_set_bits(unsigned long field, u32 mask)
1330{
1331 vmcs_writel(field, vmcs_readl(field) | mask);
1332}
1333
2961e876
GN		 1334static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1335{
1336 vmcs_write32(VM_ENTRY_CONTROLS, val);
1337 vmx->vm_entry_controls_shadow = val;
1338}
1339
1340static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1341{
1342 if (vmx->vm_entry_controls_shadow != val)
1343 vm_entry_controls_init(vmx, val);
1344}
1345
1346static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1347{
1348 return vmx->vm_entry_controls_shadow;
1349}
1350
1351
1352static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1353{
1354 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1355}
1356
1357static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1358{
1359 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1360}
1361
1362static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1363{
1364 vmcs_write32(VM_EXIT_CONTROLS, val);
1365 vmx->vm_exit_controls_shadow = val;
1366}
1367
1368static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1369{
1370 if (vmx->vm_exit_controls_shadow != val)
1371 vm_exit_controls_init(vmx, val);
1372}
1373
1374static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1375{
1376 return vmx->vm_exit_controls_shadow;
1377}
1378
1379
1380static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1383}
1384
1385static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1386{
1387 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1388}
1389
2fb92db1
AK		 1390static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1391{
1392 vmx->segment_cache.bitmask = 0;
1393}
1394
1395static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1396 unsigned field)
1397{
1398 bool ret;
1399 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1400
1401 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1402 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1403 vmx->segment_cache.bitmask = 0;
1404 }
1405 ret = vmx->segment_cache.bitmask & mask;
1406 vmx->segment_cache.bitmask |= mask;
1407 return ret;
1408}
1409
1410static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1411{
1412 u16 *p = &vmx->segment_cache.seg[seg].selector;
1413
1414 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1415 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1416 return *p;
1417}
1418
1419static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1420{
1421 ulong *p = &vmx->segment_cache.seg[seg].base;
1422
1423 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1424 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1425 return *p;
1426}
1427
1428static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1429{
1430 u32 *p = &vmx->segment_cache.seg[seg].limit;
1431
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1433 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1434 return *p;
1435}
1436
1437static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1438{
1439 u32 *p = &vmx->segment_cache.seg[seg].ar;
1440
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1442 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1443 return *p;
1444}
1445
abd3f2d6
AK		 1446static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1447{
1448 u32 eb;
1449
fd7373cc
JK		 1450 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1451 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1452 if ((vcpu->guest_debug &
1453 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1454 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1455 eb |= 1u << BP_VECTOR;
7ffd92c5 1456 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1457 eb = ~0;
089d034e 1458 if (enable_ept)
1439442c 1459 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1460 if (vcpu->fpu_active)
1461 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1462
1463 /* When we are running a nested L2 guest and L1 specified for it a
1464 * certain exception bitmap, we must trap the same exceptions and pass
1465 * them to L1. When running L2, we will only handle the exceptions
1466 * specified above if L1 did not want them.
1467 */
1468 if (is_guest_mode(vcpu))
1469 eb |= get_vmcs12(vcpu)->exception_bitmap;
1470
abd3f2d6
AK		 1471 vmcs_write32(EXCEPTION_BITMAP, eb);
1472}
1473
2961e876
GN		 1474static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1475 unsigned long entry, unsigned long exit)
8bf00a52 1476{
2961e876
GN		 1477 vm_entry_controls_clearbit(vmx, entry);
1478 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1479}
1480
61d2ef2c
AK		 1481static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1482{
1483 unsigned i;
1484 struct msr_autoload *m = &vmx->msr_autoload;
1485
8bf00a52
GN		 1486 switch (msr) {
1487 case MSR_EFER:
1488 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1489 clear_atomic_switch_msr_special(vmx,
1490 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1491 VM_EXIT_LOAD_IA32_EFER);
1492 return;
1493 }
1494 break;
1495 case MSR_CORE_PERF_GLOBAL_CTRL:
1496 if (cpu_has_load_perf_global_ctrl) {
2961e876 1497 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1498 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1499 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1500 return;
1501 }
1502 break;
110312c8
AK		 1503 }
1504
61d2ef2c
AK		 1505 for (i = 0; i < m->nr; ++i)
1506 if (m->guest[i].index == msr)
1507 break;
1508
1509 if (i == m->nr)
1510 return;
1511 --m->nr;
1512 m->guest[i] = m->guest[m->nr];
1513 m->host[i] = m->host[m->nr];
1514 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1515 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1516}
1517
2961e876
GN		 1518static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1519 unsigned long entry, unsigned long exit,
1520 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1521 u64 guest_val, u64 host_val)
8bf00a52
GN		 1522{
1523 vmcs_write64(guest_val_vmcs, guest_val);
1524 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1525 vm_entry_controls_setbit(vmx, entry);
1526 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1527}
1528
61d2ef2c
AK		 1529static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1530 u64 guest_val, u64 host_val)
1531{
1532 unsigned i;
1533 struct msr_autoload *m = &vmx->msr_autoload;
1534
8bf00a52
GN		 1535 switch (msr) {
1536 case MSR_EFER:
1537 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1538 add_atomic_switch_msr_special(vmx,
1539 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1540 VM_EXIT_LOAD_IA32_EFER,
1541 GUEST_IA32_EFER,
1542 HOST_IA32_EFER,
1543 guest_val, host_val);
1544 return;
1545 }
1546 break;
1547 case MSR_CORE_PERF_GLOBAL_CTRL:
1548 if (cpu_has_load_perf_global_ctrl) {
2961e876 1549 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1550 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1551 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1552 GUEST_IA32_PERF_GLOBAL_CTRL,
1553 HOST_IA32_PERF_GLOBAL_CTRL,
1554 guest_val, host_val);
1555 return;
1556 }
1557 break;
110312c8
AK		 1558 }
1559
61d2ef2c
AK		 1560 for (i = 0; i < m->nr; ++i)
1561 if (m->guest[i].index == msr)
1562 break;
1563
e7fc6f93 1564 if (i == NR_AUTOLOAD_MSRS) {
60266204 1565 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1566 "Can't add msr %x\n", msr);
1567 return;
1568 } else if (i == m->nr) {
61d2ef2c
AK		 1569 ++m->nr;
1570 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1571 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1572 }
1573
1574 m->guest[i].index = msr;
1575 m->guest[i].value = guest_val;
1576 m->host[i].index = msr;
1577 m->host[i].value = host_val;
1578}
1579
33ed6329
AK		 1580static void reload_tss(void)
1581{
33ed6329
AK		 1582 /*
1583 * VT restores TR but not its size. Useless.
1584 */
d359192f 1585 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1586 struct desc_struct *descs;
33ed6329 1587
d359192f 1588 descs = (void *)gdt->address;
33ed6329
AK		 1589 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1590 load_TR_desc();
33ed6329
AK		 1591}
1592
92c0d900 1593static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1594{
3a34a881 1595 u64 guest_efer;
51c6cf66
AK		 1596 u64 ignore_bits;
1597
f6801dff 1598 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1599
51c6cf66 1600 /*
0fa06071 1601 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1602 * outside long mode
1603 */
1604 ignore_bits = EFER_NX | EFER_SCE;
1605#ifdef CONFIG_X86_64
1606 ignore_bits |= EFER_LMA | EFER_LME;
1607 /* SCE is meaningful only in long mode on Intel */
1608 if (guest_efer & EFER_LMA)
1609 ignore_bits &= ~(u64)EFER_SCE;
1610#endif
51c6cf66
AK		 1611 guest_efer &= ~ignore_bits;
1612 guest_efer |= host_efer & ignore_bits;
26bb0981 1613 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1614 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1615
1616 clear_atomic_switch_msr(vmx, MSR_EFER);
1617 /* On ept, can't emulate nx, and must switch nx atomically */
1618 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1619 guest_efer = vmx->vcpu.arch.efer;
1620 if (!(guest_efer & EFER_LMA))
1621 guest_efer &= ~EFER_LME;
1622 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1623 return false;
1624 }
1625
26bb0981 1626 return true;
51c6cf66
AK		 1627}
1628
2d49ec72
GN		 1629static unsigned long segment_base(u16 selector)
1630{
d359192f 1631 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1632 struct desc_struct *d;
1633 unsigned long table_base;
1634 unsigned long v;
1635
1636 if (!(selector & ~3))
1637 return 0;
1638
d359192f 1639 table_base = gdt->address;
2d49ec72
GN		 1640
1641 if (selector & 4) { /* from ldt */
1642 u16 ldt_selector = kvm_read_ldt();
1643
1644 if (!(ldt_selector & ~3))
1645 return 0;
1646
1647 table_base = segment_base(ldt_selector);
1648 }
1649 d = (struct desc_struct *)(table_base + (selector & ~7));
1650 v = get_desc_base(d);
1651#ifdef CONFIG_X86_64
1652 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1653 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1654#endif
1655 return v;
1656}
1657
1658static inline unsigned long kvm_read_tr_base(void)
1659{
1660 u16 tr;
1661 asm("str %0" : "=g"(tr));
1662 return segment_base(tr);
1663}
1664
04d2cc77 1665static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1666{
04d2cc77 1667 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1668 int i;
04d2cc77 1669
a2fa3e9f 1670 if (vmx->host_state.loaded)
33ed6329
AK		 1671 return;
1672
a2fa3e9f 1673 vmx->host_state.loaded = 1;
33ed6329
AK		 1674 /*
1675 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1676 * allow segment selectors with cpl > 0 or ti == 1.
1677 */
d6e88aec 1678 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1679 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1680 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1681 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1682 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1683 vmx->host_state.fs_reload_needed = 0;
1684 } else {
33ed6329 1685 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1686 vmx->host_state.fs_reload_needed = 1;
33ed6329 1687 }
9581d442 1688 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1689 if (!(vmx->host_state.gs_sel & 7))
1690 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1691 else {
1692 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1693 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1694 }
1695
b2da15ac
AK		 1696#ifdef CONFIG_X86_64
1697 savesegment(ds, vmx->host_state.ds_sel);
1698 savesegment(es, vmx->host_state.es_sel);
1699#endif
1700
33ed6329
AK		 1701#ifdef CONFIG_X86_64
1702 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1703 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1704#else
a2fa3e9f
GH		 1705 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1706 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1707#endif
707c0874
AK		 1708
1709#ifdef CONFIG_X86_64
c8770e7b
AK		 1710 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1711 if (is_long_mode(&vmx->vcpu))
44ea2b17 1712 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1713#endif
da8999d3
LJ		 1714 if (boot_cpu_has(X86_FEATURE_MPX))
1715 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1716 for (i = 0; i < vmx->save_nmsrs; ++i)
1717 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1718 vmx->guest_msrs[i].data,
1719 vmx->guest_msrs[i].mask);
33ed6329
AK		 1720}
1721
a9b21b62 1722static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1723{
a2fa3e9f 1724 if (!vmx->host_state.loaded)
33ed6329
AK		 1725 return;
1726
e1beb1d3 1727 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1728 vmx->host_state.loaded = 0;
c8770e7b
AK		 1729#ifdef CONFIG_X86_64
1730 if (is_long_mode(&vmx->vcpu))
1731 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1732#endif
152d3f2f 1733 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1734 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1735#ifdef CONFIG_X86_64
9581d442 1736 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1737#else
1738 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1739#endif
33ed6329 1740 }
0a77fe4c
AK		 1741 if (vmx->host_state.fs_reload_needed)
1742 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1743#ifdef CONFIG_X86_64
1744 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1745 loadsegment(ds, vmx->host_state.ds_sel);
1746 loadsegment(es, vmx->host_state.es_sel);
1747 }
b2da15ac 1748#endif
152d3f2f 1749 reload_tss();
44ea2b17 1750#ifdef CONFIG_X86_64
c8770e7b 1751 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1752#endif
da8999d3
LJ		 1753 if (vmx->host_state.msr_host_bndcfgs)
1754 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1755 /*
1756 * If the FPU is not active (through the host task or
1757 * the guest vcpu), then restore the cr0.TS bit.
1758 */
1759 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1760 stts();
3444d7da 1761 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1762}
1763
a9b21b62
AK		 1764static void vmx_load_host_state(struct vcpu_vmx *vmx)
1765{
1766 preempt_disable();
1767 __vmx_load_host_state(vmx);
1768 preempt_enable();
1769}
1770
6aa8b732
AK		 1771/*
1772 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1773 * vcpu mutex is already taken.
1774 */
15ad7146 1775static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1776{
a2fa3e9f 1777 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1778 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1779
4610c9cc
DX		 1780 if (!vmm_exclusive)
1781 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1782 else if (vmx->loaded_vmcs->cpu != cpu)
1783 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1784
d462b819
NHE		 1785 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1786 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1787 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1788 }
1789
d462b819 1790 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1791 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1792 unsigned long sysenter_esp;
1793
a8eeb04a 1794 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1795 local_irq_disable();
8f536b76 1796 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1797
1798 /*
1799 * Read loaded_vmcs->cpu should be before fetching
1800 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1801 * See the comments in __loaded_vmcs_clear().
1802 */
1803 smp_rmb();
1804
d462b819
NHE		 1805 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1806 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1807 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1808 local_irq_enable();
1809
6aa8b732
AK		 1810 /*
1811 * Linux uses per-cpu TSS and GDT, so set these when switching
1812 * processors.
1813 */
d6e88aec 1814 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1815 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1816
1817 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1818 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1819 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1820 }
6aa8b732
AK		 1821}
1822
1823static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1824{
a9b21b62 1825 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1826 if (!vmm_exclusive) {
d462b819
NHE		 1827 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1828 vcpu->cpu = -1;
4610c9cc
DX		 1829 kvm_cpu_vmxoff();
1830 }
6aa8b732
AK		 1831}
1832
5fd86fcf
AK		 1833static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1834{
81231c69
AK		 1835 ulong cr0;
1836
5fd86fcf
AK		 1837 if (vcpu->fpu_active)
1838 return;
1839 vcpu->fpu_active = 1;
81231c69
AK		 1840 cr0 = vmcs_readl(GUEST_CR0);
1841 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1842 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1843 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1844 update_exception_bitmap(vcpu);
edcafe3c 1845 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1846 if (is_guest_mode(vcpu))
1847 vcpu->arch.cr0_guest_owned_bits &=
1848 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1849 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1850}
1851
edcafe3c
AK		 1852static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1853
fe3ef05c
NHE		 1854/*
1855 * Return the cr0 value that a nested guest would read. This is a combination
1856 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1857 * its hypervisor (cr0_read_shadow).
1858 */
1859static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1860{
1861 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1862 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1863}
1864static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1865{
1866 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1867 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1868}
1869
5fd86fcf
AK		 1870static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1871{
36cf24e0
NHE		 1872 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1873 * set this *before* calling this function.
1874 */
edcafe3c 1875 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1876 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1877 update_exception_bitmap(vcpu);
edcafe3c
AK		 1878 vcpu->arch.cr0_guest_owned_bits = 0;
1879 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1880 if (is_guest_mode(vcpu)) {
1881 /*
1882 * L1's specified read shadow might not contain the TS bit,
1883 * so now that we turned on shadowing of this bit, we need to
1884 * set this bit of the shadow. Like in nested_vmx_run we need
1885 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1886 * up-to-date here because we just decached cr0.TS (and we'll
1887 * only update vmcs12->guest_cr0 on nested exit).
1888 */
1889 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1890 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1891 (vcpu->arch.cr0 & X86_CR0_TS);
1892 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1893 } else
1894 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1895}
1896
6aa8b732
AK		 1897static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1898{
78ac8b47 1899 unsigned long rflags, save_rflags;
345dcaa8 1900
6de12732
AK		 1901 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1902 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1903 rflags = vmcs_readl(GUEST_RFLAGS);
1904 if (to_vmx(vcpu)->rmode.vm86_active) {
1905 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1906 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1907 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1908 }
1909 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1910 }
6de12732 1911 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1912}
1913
1914static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1915{
6de12732
AK		 1916 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1917 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1918 if (to_vmx(vcpu)->rmode.vm86_active) {
1919 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1920 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1921 }
6aa8b732
AK		 1922 vmcs_writel(GUEST_RFLAGS, rflags);
1923}
1924
2809f5d2
GC		 1925static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1926{
1927 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1928 int ret = 0;
1929
1930 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1931 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1932 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1933 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1934
1935 return ret & mask;
1936}
1937
1938static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1939{
1940 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1941 u32 interruptibility = interruptibility_old;
1942
1943 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1944
48005f64 1945 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1946 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1947 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1948 interruptibility |= GUEST_INTR_STATE_STI;
1949
1950 if ((interruptibility != interruptibility_old))
1951 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1952}
1953
6aa8b732
AK		 1954static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1955{
1956 unsigned long rip;
6aa8b732 1957
5fdbf976 1958 rip = kvm_rip_read(vcpu);
6aa8b732 1959 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1960 kvm_rip_write(vcpu, rip);
6aa8b732 1961
2809f5d2
GC		 1962 /* skipping an emulated instruction also counts */
1963 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1964}
1965
0b6ac343
NHE		 1966/*
1967 * KVM wants to inject page-faults which it got to the guest. This function
1968 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1969 */
e011c663 1970static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1971{
1972 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1973
e011c663 1974 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1975 return 0;
1976
533558bc
JK		 1977 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1978 vmcs_read32(VM_EXIT_INTR_INFO),
1979 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1980 return 1;
1981}
1982
298101da 1983static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1984 bool has_error_code, u32 error_code,
1985 bool reinject)
298101da 1986{
77ab6db0 1987 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1988 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1989
e011c663
GN		 1990 if (!reinject && is_guest_mode(vcpu) &&
1991 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1992 return;
1993
8ab2d2e2 1994 if (has_error_code) {
77ab6db0 1995 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1996 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1997 }
77ab6db0 1998
7ffd92c5 1999 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2000 int inc_eip = 0;
2001 if (kvm_exception_is_soft(nr))
2002 inc_eip = vcpu->arch.event_exit_inst_len;
2003 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2004 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2005 return;
2006 }
2007
66fd3f7f
GN		 2008 if (kvm_exception_is_soft(nr)) {
2009 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2010 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2011 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2012 } else
2013 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2014
2015 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2016}
2017
4e47c7a6
SY		 2018static bool vmx_rdtscp_supported(void)
2019{
2020 return cpu_has_vmx_rdtscp();
2021}
2022
ad756a16
MJ		 2023static bool vmx_invpcid_supported(void)
2024{
2025 return cpu_has_vmx_invpcid() && enable_ept;
2026}
2027
a75beee6
ED		 2028/*
2029 * Swap MSR entry in host/guest MSR entry array.
2030 */
8b9cf98c 2031static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2032{
26bb0981 2033 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2034
2035 tmp = vmx->guest_msrs[to];
2036 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2037 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2038}
2039
8d14695f
YZ		 2040static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2041{
2042 unsigned long *msr_bitmap;
2043
2044 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2045 if (is_long_mode(vcpu))
2046 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2047 else
2048 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2049 } else {
2050 if (is_long_mode(vcpu))
2051 msr_bitmap = vmx_msr_bitmap_longmode;
2052 else
2053 msr_bitmap = vmx_msr_bitmap_legacy;
2054 }
2055
2056 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2057}
2058
e38aea3e
AK		 2059/*
2060 * Set up the vmcs to automatically save and restore system
2061 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2062 * mode, as fiddling with msrs is very expensive.
2063 */
8b9cf98c 2064static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2065{
26bb0981 2066 int save_nmsrs, index;
e38aea3e 2067
a75beee6
ED		 2068 save_nmsrs = 0;
2069#ifdef CONFIG_X86_64
8b9cf98c 2070 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2071 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2072 if (index >= 0)
8b9cf98c
RR		 2073 move_msr_up(vmx, index, save_nmsrs++);
2074 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2075 if (index >= 0)
8b9cf98c
RR		 2076 move_msr_up(vmx, index, save_nmsrs++);
2077 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2078 if (index >= 0)
8b9cf98c 2079 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2080 index = __find_msr_index(vmx, MSR_TSC_AUX);
2081 if (index >= 0 && vmx->rdtscp_enabled)
2082 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2083 /*
8c06585d 2084 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2085 * if efer.sce is enabled.
2086 */
8c06585d 2087 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2088 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2089 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2090 }
2091#endif
92c0d900
AK		 2092 index = __find_msr_index(vmx, MSR_EFER);
2093 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2094 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2095
26bb0981 2096 vmx->save_nmsrs = save_nmsrs;
5897297b 2097
8d14695f
YZ		 2098 if (cpu_has_vmx_msr_bitmap())
2099 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2100}
2101
6aa8b732
AK		 2102/*
2103 * reads and returns guest's timestamp counter "register"
2104 * guest_tsc = host_tsc + tsc_offset -- 21.3
2105 */
2106static u64 guest_read_tsc(void)
2107{
2108 u64 host_tsc, tsc_offset;
2109
2110 rdtscll(host_tsc);
2111 tsc_offset = vmcs_read64(TSC_OFFSET);
2112 return host_tsc + tsc_offset;
2113}
2114
d5c1785d
NHE		 2115/*
2116 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2117 * counter, even if a nested guest (L2) is currently running.
2118 */
886b470c 2119u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2120{
886b470c 2121 u64 tsc_offset;
d5c1785d 2122
d5c1785d
NHE		 2123 tsc_offset = is_guest_mode(vcpu) ?
2124 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2125 vmcs_read64(TSC_OFFSET);
2126 return host_tsc + tsc_offset;
2127}
2128
4051b188 2129/*
cc578287
ZA		 2130 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2131 * software catchup for faster rates on slower CPUs.
4051b188 2132 */
cc578287 2133static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2134{
cc578287
ZA		 2135 if (!scale)
2136 return;
2137
2138 if (user_tsc_khz > tsc_khz) {
2139 vcpu->arch.tsc_catchup = 1;
2140 vcpu->arch.tsc_always_catchup = 1;
2141 } else
2142 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2143}
2144
ba904635
WA		 2145static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2146{
2147 return vmcs_read64(TSC_OFFSET);
2148}
2149
6aa8b732 2150/*
99e3e30a 2151 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2152 */
99e3e30a 2153static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2154{
27fc51b2 2155 if (is_guest_mode(vcpu)) {
7991825b 2156 /*
27fc51b2
NHE		 2157 * We're here if L1 chose not to trap WRMSR to TSC. According
2158 * to the spec, this should set L1's TSC; The offset that L1
2159 * set for L2 remains unchanged, and still needs to be added
2160 * to the newly set TSC to get L2's TSC.
7991825b 2161 */
27fc51b2
NHE		 2162 struct vmcs12 *vmcs12;
2163 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2164 /* recalculate vmcs02.TSC_OFFSET: */
2165 vmcs12 = get_vmcs12(vcpu);
2166 vmcs_write64(TSC_OFFSET, offset +
2167 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2168 vmcs12->tsc_offset : 0));
2169 } else {
489223ed
YY		 2170 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2171 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2172 vmcs_write64(TSC_OFFSET, offset);
2173 }
6aa8b732
AK		 2174}
2175
f1e2b260 2176static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2177{
2178 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2179
e48672fa 2180 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2181 if (is_guest_mode(vcpu)) {
2182 /* Even when running L2, the adjustment needs to apply to L1 */
2183 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2184 } else
2185 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2186 offset + adjustment);
e48672fa
ZA		 2187}
2188
857e4099
JR		 2189static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2190{
2191 return target_tsc - native_read_tsc();
2192}
2193
801d3424
NHE		 2194static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2195{
2196 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2197 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2198}
2199
2200/*
2201 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2202 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2203 * all guests if the "nested" module option is off, and can also be disabled
2204 * for a single guest by disabling its VMX cpuid bit.
2205 */
2206static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2207{
2208 return nested && guest_cpuid_has_vmx(vcpu);
2209}
2210
b87a51ae
NHE		 2211/*
2212 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2213 * returned for the various VMX controls MSRs when nested VMX is enabled.
2214 * The same values should also be used to verify that vmcs12 control fields are
2215 * valid during nested entry from L1 to L2.
2216 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2217 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2218 * bit in the high half is on if the corresponding bit in the control field
2219 * may be on. See also vmx_control_verify().
2220 * TODO: allow these variables to be modified (downgraded) by module options
2221 * or other means.
2222 */
2223static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2224static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2225static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2226static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2227static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2228static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2229static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2230static __init void nested_vmx_setup_ctls_msrs(void)
2231{
2232 /*
2233 * Note that as a general rule, the high half of the MSRs (bits in
2234 * the control fields which may be 1) should be initialized by the
2235 * intersection of the underlying hardware's MSR (i.e., features which
2236 * can be supported) and the list of features we want to expose -
2237 * because they are known to be properly supported in our code.
2238 * Also, usually, the low half of the MSRs (bits which must be 1) can
2239 * be set to 0, meaning that L1 may turn off any of these bits. The
2240 * reason is that if one of these bits is necessary, it will appear
2241 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2242 * fields of vmcs01 and vmcs02, will turn these bits off - and
2243 * nested_vmx_exit_handled() will not pass related exits to L1.
2244 * These rules have exceptions below.
2245 */
2246
2247 /* pin-based controls */
eabeaacc
JK		 2248 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2249 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2250 /*
2251 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2252 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2253 */
eabeaacc
JK		 2254 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2255 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2256 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2257 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2258 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2259
33fb20c3
JK		 2260 /*
2261 * Exit controls
2262 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2263 * 17 must be 1.
2264 */
c0dfee58
ACL		 2265 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2266 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2267 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2268 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2269 nested_vmx_exit_ctls_high &=
b87a51ae 2270#ifdef CONFIG_X86_64
c0dfee58 2271 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2272#endif
7854cbca
ACL		 2273 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2274 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2275 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2276 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2277 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2278 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2279 }
8049d651 2280 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2281 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2282
2283 /* entry controls */
2284 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2285 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2286 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2287 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2288 nested_vmx_entry_ctls_high &=
57435349
JK		 2289#ifdef CONFIG_X86_64
2290 VM_ENTRY_IA32E_MODE |
2291#endif
2292 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2293 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2294 VM_ENTRY_LOAD_IA32_EFER);
57435349 2295
b87a51ae
NHE		 2296 /* cpu-based controls */
2297 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2298 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2299 nested_vmx_procbased_ctls_low = 0;
2300 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2301 CPU_BASED_VIRTUAL_INTR_PENDING |
2302 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2303 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2304 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2305 CPU_BASED_CR3_STORE_EXITING |
2306#ifdef CONFIG_X86_64
2307 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2308#endif
2309 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2310 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2311 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2312 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2313 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2314 /*
2315 * We can allow some features even when not supported by the
2316 * hardware. For example, L1 can specify an MSR bitmap - and we
2317 * can use it to avoid exits to L1 - even when L0 runs L2
2318 * without MSR bitmaps.
2319 */
2320 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2321
2322 /* secondary cpu-based controls */
2323 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2324 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2325 nested_vmx_secondary_ctls_low = 0;
2326 nested_vmx_secondary_ctls_high &=
d6851fbe 2327 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2328 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2329 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2330
afa61f75
NHE		 2331 if (enable_ept) {
2332 /* nested EPT: emulate EPT also to L1 */
2333 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2334 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2335 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2336 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2337 nested_vmx_ept_caps &= vmx_capability.ept;
2338 /*
2339 * Since invept is completely emulated we support both global
2340 * and context invalidation independent of what host cpu
2341 * supports
2342 */
2343 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2344 VMX_EPT_EXTENT_CONTEXT_BIT;
2345 } else
2346 nested_vmx_ept_caps = 0;
2347
c18911a2
JK		 2348 /* miscellaneous data */
2349 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2350 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2351 VMX_MISC_SAVE_EFER_LMA;
6dfacadd 2352 nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
c18911a2 2353 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2354}
2355
2356static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2357{
2358 /*
2359 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2360 */
2361 return ((control & high) | low) == control;
2362}
2363
2364static inline u64 vmx_control_msr(u32 low, u32 high)
2365{
2366 return low | ((u64)high << 32);
2367}
2368
cae50139 2369/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2370static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2371{
b87a51ae 2372 switch (msr_index) {
b87a51ae
NHE		 2373 case MSR_IA32_VMX_BASIC:
2374 /*
2375 * This MSR reports some information about VMX support. We
2376 * should return information about the VMX we emulate for the
2377 * guest, and the VMCS structure we give it - not about the
2378 * VMX support of the underlying hardware.
2379 */
2380 *pdata = VMCS12_REVISION |
2381 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2382 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2383 break;
2384 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2385 case MSR_IA32_VMX_PINBASED_CTLS:
2386 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2387 nested_vmx_pinbased_ctls_high);
2388 break;
2389 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2390 case MSR_IA32_VMX_PROCBASED_CTLS:
2391 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2392 nested_vmx_procbased_ctls_high);
2393 break;
2394 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2395 case MSR_IA32_VMX_EXIT_CTLS:
2396 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2397 nested_vmx_exit_ctls_high);
2398 break;
2399 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2400 case MSR_IA32_VMX_ENTRY_CTLS:
2401 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2402 nested_vmx_entry_ctls_high);
2403 break;
2404 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2405 *pdata = vmx_control_msr(nested_vmx_misc_low,
2406 nested_vmx_misc_high);
b87a51ae
NHE		 2407 break;
2408 /*
2409 * These MSRs specify bits which the guest must keep fixed (on or off)
2410 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2411 * We picked the standard core2 setting.
2412 */
2413#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2414#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2415 case MSR_IA32_VMX_CR0_FIXED0:
2416 *pdata = VMXON_CR0_ALWAYSON;
2417 break;
2418 case MSR_IA32_VMX_CR0_FIXED1:
2419 *pdata = -1ULL;
2420 break;
2421 case MSR_IA32_VMX_CR4_FIXED0:
2422 *pdata = VMXON_CR4_ALWAYSON;
2423 break;
2424 case MSR_IA32_VMX_CR4_FIXED1:
2425 *pdata = -1ULL;
2426 break;
2427 case MSR_IA32_VMX_VMCS_ENUM:
2428 *pdata = 0x1f;
2429 break;
2430 case MSR_IA32_VMX_PROCBASED_CTLS2:
2431 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2432 nested_vmx_secondary_ctls_high);
2433 break;
2434 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2435 /* Currently, no nested vpid support */
2436 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2437 break;
2438 default:
b87a51ae 2439 return 1;
b3897a49
NHE		 2440 }
2441
b87a51ae
NHE		 2442 return 0;
2443}
2444
6aa8b732
AK		 2445/*
2446 * Reads an msr value (of 'msr_index') into 'pdata'.
2447 * Returns 0 on success, non-0 otherwise.
2448 * Assumes vcpu_load() was already called.
2449 */
2450static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2451{
2452 u64 data;
26bb0981 2453 struct shared_msr_entry *msr;
6aa8b732
AK		 2454
2455 if (!pdata) {
2456 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2457 return -EINVAL;
2458 }
2459
2460 switch (msr_index) {
05b3e0c2 2461#ifdef CONFIG_X86_64
6aa8b732
AK		 2462 case MSR_FS_BASE:
2463 data = vmcs_readl(GUEST_FS_BASE);
2464 break;
2465 case MSR_GS_BASE:
2466 data = vmcs_readl(GUEST_GS_BASE);
2467 break;
44ea2b17
AK		 2468 case MSR_KERNEL_GS_BASE:
2469 vmx_load_host_state(to_vmx(vcpu));
2470 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2471 break;
26bb0981 2472#endif
6aa8b732 2473 case MSR_EFER:
3bab1f5d 2474 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2475 case MSR_IA32_TSC:
6aa8b732
AK		 2476 data = guest_read_tsc();
2477 break;
2478 case MSR_IA32_SYSENTER_CS:
2479 data = vmcs_read32(GUEST_SYSENTER_CS);
2480 break;
2481 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2482 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2483 break;
2484 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2485 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2486 break;
0dd376e7
LJ		 2487 case MSR_IA32_BNDCFGS:
2488 data = vmcs_read64(GUEST_BNDCFGS);
2489 break;
cae50139
JK		 2490 case MSR_IA32_FEATURE_CONTROL:
2491 if (!nested_vmx_allowed(vcpu))
2492 return 1;
2493 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2494 break;
2495 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2496 if (!nested_vmx_allowed(vcpu))
2497 return 1;
2498 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2499 case MSR_TSC_AUX:
2500 if (!to_vmx(vcpu)->rdtscp_enabled)
2501 return 1;
2502 /* Otherwise falls through */
6aa8b732 2503 default:
8b9cf98c 2504 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2505 if (msr) {
2506 data = msr->data;
2507 break;
6aa8b732 2508 }
3bab1f5d 2509 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2510 }
2511
2512 *pdata = data;
2513 return 0;
2514}
2515
cae50139
JK		 2516static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2517
6aa8b732
AK		 2518/*
2519 * Writes msr value into into the appropriate "register".
2520 * Returns 0 on success, non-0 otherwise.
2521 * Assumes vcpu_load() was already called.
2522 */
8fe8ab46 2523static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2524{
a2fa3e9f 2525 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2526 struct shared_msr_entry *msr;
2cc51560 2527 int ret = 0;
8fe8ab46
WA		 2528 u32 msr_index = msr_info->index;
2529 u64 data = msr_info->data;
2cc51560 2530
6aa8b732 2531 switch (msr_index) {
3bab1f5d 2532 case MSR_EFER:
8fe8ab46 2533 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2534 break;
16175a79 2535#ifdef CONFIG_X86_64
6aa8b732 2536 case MSR_FS_BASE:
2fb92db1 2537 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2538 vmcs_writel(GUEST_FS_BASE, data);
2539 break;
2540 case MSR_GS_BASE:
2fb92db1 2541 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2542 vmcs_writel(GUEST_GS_BASE, data);
2543 break;
44ea2b17
AK		 2544 case MSR_KERNEL_GS_BASE:
2545 vmx_load_host_state(vmx);
2546 vmx->msr_guest_kernel_gs_base = data;
2547 break;
6aa8b732
AK		 2548#endif
2549 case MSR_IA32_SYSENTER_CS:
2550 vmcs_write32(GUEST_SYSENTER_CS, data);
2551 break;
2552 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2553 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2554 break;
2555 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2556 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2557 break;
0dd376e7
LJ		 2558 case MSR_IA32_BNDCFGS:
2559 vmcs_write64(GUEST_BNDCFGS, data);
2560 break;
af24a4e4 2561 case MSR_IA32_TSC:
8fe8ab46 2562 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2563 break;
468d472f
SY		 2564 case MSR_IA32_CR_PAT:
2565 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2566 vmcs_write64(GUEST_IA32_PAT, data);
2567 vcpu->arch.pat = data;
2568 break;
2569 }
8fe8ab46 2570 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2571 break;
ba904635
WA		 2572 case MSR_IA32_TSC_ADJUST:
2573 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2574 break;
cae50139
JK		 2575 case MSR_IA32_FEATURE_CONTROL:
2576 if (!nested_vmx_allowed(vcpu) ||
2577 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2578 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2579 return 1;
2580 vmx->nested.msr_ia32_feature_control = data;
2581 if (msr_info->host_initiated && data == 0)
2582 vmx_leave_nested(vcpu);
2583 break;
2584 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2585 return 1; /* they are read-only */
4e47c7a6
SY		 2586 case MSR_TSC_AUX:
2587 if (!vmx->rdtscp_enabled)
2588 return 1;
2589 /* Check reserved bit, higher 32 bits should be zero */
2590 if ((data >> 32) != 0)
2591 return 1;
2592 /* Otherwise falls through */
6aa8b732 2593 default:
8b9cf98c 2594 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2595 if (msr) {
2596 msr->data = data;
2225fd56
AK		 2597 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2598 preempt_disable();
9ee73970
AK		 2599 kvm_set_shared_msr(msr->index, msr->data,
2600 msr->mask);
2225fd56
AK		 2601 preempt_enable();
2602 }
3bab1f5d 2603 break;
6aa8b732 2604 }
8fe8ab46 2605 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2606 }
2607
2cc51560 2608 return ret;
6aa8b732
AK		 2609}
2610
5fdbf976 2611static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2612{
5fdbf976
MT		 2613 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2614 switch (reg) {
2615 case VCPU_REGS_RSP:
2616 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2617 break;
2618 case VCPU_REGS_RIP:
2619 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2620 break;
6de4f3ad
AK		 2621 case VCPU_EXREG_PDPTR:
2622 if (enable_ept)
2623 ept_save_pdptrs(vcpu);
2624 break;
5fdbf976
MT		 2625 default:
2626 break;
2627 }
6aa8b732
AK		 2628}
2629
6aa8b732
AK		 2630static __init int cpu_has_kvm_support(void)
2631{
6210e37b 2632 return cpu_has_vmx();
6aa8b732
AK		 2633}
2634
2635static __init int vmx_disabled_by_bios(void)
2636{
2637 u64 msr;
2638
2639 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2640 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2641 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2642 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2643 && tboot_enabled())
2644 return 1;
23f3e991 2645 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2646 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2647 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2648 && !tboot_enabled()) {
2649 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2650 "activate TXT before enabling KVM\n");
cafd6659 2651 return 1;
f9335afe 2652 }
23f3e991
JC		 2653 /* launched w/o TXT and VMX disabled */
2654 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2655 && !tboot_enabled())
2656 return 1;
cafd6659
SW		 2657 }
2658
2659 return 0;
6aa8b732
AK		 2660}
2661
7725b894
DX		 2662static void kvm_cpu_vmxon(u64 addr)
2663{
2664 asm volatile (ASM_VMX_VMXON_RAX
2665 : : "a"(&addr), "m"(addr)
2666 : "memory", "cc");
2667}
2668
10474ae8 2669static int hardware_enable(void *garbage)
6aa8b732
AK		 2670{
2671 int cpu = raw_smp_processor_id();
2672 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2673 u64 old, test_bits;
6aa8b732 2674
10474ae8
AG		 2675 if (read_cr4() & X86_CR4_VMXE)
2676 return -EBUSY;
2677
d462b819 2678 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2679
2680 /*
2681 * Now we can enable the vmclear operation in kdump
2682 * since the loaded_vmcss_on_cpu list on this cpu
2683 * has been initialized.
2684 *
2685 * Though the cpu is not in VMX operation now, there
2686 * is no problem to enable the vmclear operation
2687 * for the loaded_vmcss_on_cpu list is empty!
2688 */
2689 crash_enable_local_vmclear(cpu);
2690
6aa8b732 2691 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2692
2693 test_bits = FEATURE_CONTROL_LOCKED;
2694 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2695 if (tboot_enabled())
2696 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2697
2698 if ((old & test_bits) != test_bits) {
6aa8b732 2699 /* enable and lock */
cafd6659
SW		 2700 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2701 }
66aee91a 2702 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2703
4610c9cc
DX		 2704 if (vmm_exclusive) {
2705 kvm_cpu_vmxon(phys_addr);
2706 ept_sync_global();
2707 }
10474ae8 2708
357d1226 2709 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2710
10474ae8 2711 return 0;
6aa8b732
AK		 2712}
2713
d462b819 2714static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2715{
2716 int cpu = raw_smp_processor_id();
d462b819 2717 struct loaded_vmcs *v, *n;
543e4243 2718
d462b819
NHE		 2719 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2720 loaded_vmcss_on_cpu_link)
2721 __loaded_vmcs_clear(v);
543e4243
AK		 2722}
2723
710ff4a8
EH		 2724
2725/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2726 * tricks.
2727 */
2728static void kvm_cpu_vmxoff(void)
6aa8b732 2729{
4ecac3fd 2730 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2731}
2732
710ff4a8
EH		 2733static void hardware_disable(void *garbage)
2734{
4610c9cc 2735 if (vmm_exclusive) {
d462b819 2736 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2737 kvm_cpu_vmxoff();
2738 }
7725b894 2739 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2740}
2741
1c3d14fe 2742static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2743 u32 msr, u32 *result)
1c3d14fe
YS		 2744{
2745 u32 vmx_msr_low, vmx_msr_high;
2746 u32 ctl = ctl_min | ctl_opt;
2747
2748 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2749
2750 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2751 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2752
2753 /* Ensure minimum (required) set of control bits are supported. */
2754 if (ctl_min & ~ctl)
002c7f7c 2755 return -EIO;
1c3d14fe
YS		 2756
2757 *result = ctl;
2758 return 0;
2759}
2760
110312c8
AK		 2761static __init bool allow_1_setting(u32 msr, u32 ctl)
2762{
2763 u32 vmx_msr_low, vmx_msr_high;
2764
2765 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2766 return vmx_msr_high & ctl;
2767}
2768
002c7f7c 2769static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2770{
2771 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2772 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2773 u32 _pin_based_exec_control = 0;
2774 u32 _cpu_based_exec_control = 0;
f78e0e2e 2775 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2776 u32 _vmexit_control = 0;
2777 u32 _vmentry_control = 0;
2778
10166744 2779 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2780#ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING |
2782 CPU_BASED_CR8_STORE_EXITING |
2783#endif
d56f546d
SY		 2784 CPU_BASED_CR3_LOAD_EXITING |
2785 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2786 CPU_BASED_USE_IO_BITMAPS |
2787 CPU_BASED_MOV_DR_EXITING |
a7052897 2788 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2789 CPU_BASED_MWAIT_EXITING |
2790 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2791 CPU_BASED_INVLPG_EXITING |
2792 CPU_BASED_RDPMC_EXITING;
443381a8 2793
f78e0e2e 2794 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2795 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2796 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2797 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2798 &_cpu_based_exec_control) < 0)
002c7f7c 2799 return -EIO;
6e5d865c
YS		 2800#ifdef CONFIG_X86_64
2801 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2802 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2803 ~CPU_BASED_CR8_STORE_EXITING;
2804#endif
f78e0e2e 2805 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2806 min2 = 0;
2807 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2808 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2809 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2810 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2811 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2812 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2813 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2814 SECONDARY_EXEC_RDTSCP |
83d4c286 2815 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2816 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2817 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2818 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2819 if (adjust_vmx_controls(min2, opt2,
2820 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2821 &_cpu_based_2nd_exec_control) < 0)
2822 return -EIO;
2823 }
2824#ifndef CONFIG_X86_64
2825 if (!(_cpu_based_2nd_exec_control &
2826 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2827 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2828#endif
83d4c286
YZ		 2829
2830 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2831 _cpu_based_2nd_exec_control &= ~(
8d14695f 2832 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2833 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2834 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2835
d56f546d 2836 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2837 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2838 enabled */
5fff7d27
GN		 2839 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2840 CPU_BASED_CR3_STORE_EXITING |
2841 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2842 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2843 vmx_capability.ept, vmx_capability.vpid);
2844 }
1c3d14fe
YS		 2845
2846 min = 0;
2847#ifdef CONFIG_X86_64
2848 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2849#endif
a547c6db 2850 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2851 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2852 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2853 &_vmexit_control) < 0)
002c7f7c 2854 return -EIO;
1c3d14fe 2855
01e439be
YZ		 2856 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2857 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2858 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2859 &_pin_based_exec_control) < 0)
2860 return -EIO;
2861
2862 if (!(_cpu_based_2nd_exec_control &
2863 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2864 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2865 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2866
468d472f 2867 min = 0;
da8999d3 2868 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2869 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2870 &_vmentry_control) < 0)
002c7f7c 2871 return -EIO;
6aa8b732 2872
c68876fd 2873 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2874
2875 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2876 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2877 return -EIO;
1c3d14fe
YS		 2878
2879#ifdef CONFIG_X86_64
2880 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2881 if (vmx_msr_high & (1u<<16))
002c7f7c 2882 return -EIO;
1c3d14fe
YS		 2883#endif
2884
2885 /* Require Write-Back (WB) memory type for VMCS accesses. */
2886 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2887 return -EIO;
1c3d14fe 2888
002c7f7c
YS		 2889 vmcs_conf->size = vmx_msr_high & 0x1fff;
2890 vmcs_conf->order = get_order(vmcs_config.size);
2891 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2892
002c7f7c
YS		 2893 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2894 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2895 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2896 vmcs_conf->vmexit_ctrl = _vmexit_control;
2897 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2898
110312c8
AK		 2899 cpu_has_load_ia32_efer =
2900 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2901 VM_ENTRY_LOAD_IA32_EFER)
2902 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2903 VM_EXIT_LOAD_IA32_EFER);
2904
8bf00a52
GN		 2905 cpu_has_load_perf_global_ctrl =
2906 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2907 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2908 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2909 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2910
2911 /*
2912 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2913 * but due to arrata below it can't be used. Workaround is to use
2914 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2915 *
2916 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2917 *
2918 * AAK155 (model 26)
2919 * AAP115 (model 30)
2920 * AAT100 (model 37)
2921 * BC86,AAY89,BD102 (model 44)
2922 * BA97 (model 46)
2923 *
2924 */
2925 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2926 switch (boot_cpu_data.x86_model) {
2927 case 26:
2928 case 30:
2929 case 37:
2930 case 44:
2931 case 46:
2932 cpu_has_load_perf_global_ctrl = false;
2933 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2934 "does not work properly. Using workaround\n");
2935 break;
2936 default:
2937 break;
2938 }
2939 }
2940
1c3d14fe 2941 return 0;
c68876fd 2942}
6aa8b732
AK		 2943
2944static struct vmcs *alloc_vmcs_cpu(int cpu)
2945{
2946 int node = cpu_to_node(cpu);
2947 struct page *pages;
2948 struct vmcs *vmcs;
2949
6484eb3e 2950 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2951 if (!pages)
2952 return NULL;
2953 vmcs = page_address(pages);
1c3d14fe
YS		 2954 memset(vmcs, 0, vmcs_config.size);
2955 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2956 return vmcs;
2957}
2958
2959static struct vmcs *alloc_vmcs(void)
2960{
d3b2c338 2961 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2962}
2963
2964static void free_vmcs(struct vmcs *vmcs)
2965{
1c3d14fe 2966 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2967}
2968
d462b819
NHE		 2969/*
2970 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2971 */
2972static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2973{
2974 if (!loaded_vmcs->vmcs)
2975 return;
2976 loaded_vmcs_clear(loaded_vmcs);
2977 free_vmcs(loaded_vmcs->vmcs);
2978 loaded_vmcs->vmcs = NULL;
2979}
2980
39959588 2981static void free_kvm_area(void)
6aa8b732
AK		 2982{
2983 int cpu;
2984
3230bb47 2985 for_each_possible_cpu(cpu) {
6aa8b732 2986 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2987 per_cpu(vmxarea, cpu) = NULL;
2988 }
6aa8b732
AK		 2989}
2990
6aa8b732
AK		 2991static __init int alloc_kvm_area(void)
2992{
2993 int cpu;
2994
3230bb47 2995 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2996 struct vmcs *vmcs;
2997
2998 vmcs = alloc_vmcs_cpu(cpu);
2999 if (!vmcs) {
3000 free_kvm_area();
3001 return -ENOMEM;
3002 }
3003
3004 per_cpu(vmxarea, cpu) = vmcs;
3005 }
3006 return 0;
3007}
3008
3009static __init int hardware_setup(void)
3010{
002c7f7c
YS		 3011 if (setup_vmcs_config(&vmcs_config) < 0)
3012 return -EIO;
50a37eb4
JR		 3013
3014 if (boot_cpu_has(X86_FEATURE_NX))
3015 kvm_enable_efer_bits(EFER_NX);
3016
93ba03c2
SY		 3017 if (!cpu_has_vmx_vpid())
3018 enable_vpid = 0;
abc4fc58
AG		 3019 if (!cpu_has_vmx_shadow_vmcs())
3020 enable_shadow_vmcs = 0;
93ba03c2 3021
4bc9b982
SY		 3022 if (!cpu_has_vmx_ept() ||
3023 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3024 enable_ept = 0;
3a624e29 3025 enable_unrestricted_guest = 0;
83c3a331 3026 enable_ept_ad_bits = 0;
3a624e29
NK		 3027 }
3028
83c3a331
XH		 3029 if (!cpu_has_vmx_ept_ad_bits())
3030 enable_ept_ad_bits = 0;
3031
3a624e29
NK		 3032 if (!cpu_has_vmx_unrestricted_guest())
3033 enable_unrestricted_guest = 0;
93ba03c2
SY		 3034
3035 if (!cpu_has_vmx_flexpriority())
3036 flexpriority_enabled = 0;
3037
95ba8273
GN		 3038 if (!cpu_has_vmx_tpr_shadow())
3039 kvm_x86_ops->update_cr8_intercept = NULL;
3040
54dee993
MT		 3041 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3042 kvm_disable_largepages();
3043
4b8d54f9
ZE		 3044 if (!cpu_has_vmx_ple())
3045 ple_gap = 0;
3046
01e439be
YZ		 3047 if (!cpu_has_vmx_apicv())
3048 enable_apicv = 0;
c7c9c56c 3049
01e439be 3050 if (enable_apicv)
c7c9c56c 3051 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3052 else {
c7c9c56c 3053 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3054 kvm_x86_ops->deliver_posted_interrupt = NULL;
3055 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3056 }
83d4c286 3057
b87a51ae
NHE		 3058 if (nested)
3059 nested_vmx_setup_ctls_msrs();
3060
6aa8b732
AK		 3061 return alloc_kvm_area();
3062}
3063
3064static __exit void hardware_unsetup(void)
3065{
3066 free_kvm_area();
3067}
3068
14168786
GN		 3069static bool emulation_required(struct kvm_vcpu *vcpu)
3070{
3071 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3072}
3073
91b0aa2c 3074static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3075 struct kvm_segment *save)
6aa8b732 3076{
d99e4152
GN		 3077 if (!emulate_invalid_guest_state) {
3078 /*
3079 * CS and SS RPL should be equal during guest entry according
3080 * to VMX spec, but in reality it is not always so. Since vcpu
3081 * is in the middle of the transition from real mode to
3082 * protected mode it is safe to assume that RPL 0 is a good
3083 * default value.
3084 */
3085 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3086 save->selector &= ~SELECTOR_RPL_MASK;
3087 save->dpl = save->selector & SELECTOR_RPL_MASK;
3088 save->s = 1;
6aa8b732 3089 }
d99e4152 3090 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3091}
3092
3093static void enter_pmode(struct kvm_vcpu *vcpu)
3094{
3095 unsigned long flags;
a89a8fb9 3096 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3097
d99e4152
GN		 3098 /*
3099 * Update real mode segment cache. It may be not up-to-date if sement
3100 * register was written while vcpu was in a guest mode.
3101 */
3102 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3103 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3104 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3105 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3106 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3107 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3108
7ffd92c5 3109 vmx->rmode.vm86_active = 0;
6aa8b732 3110
2fb92db1
AK		 3111 vmx_segment_cache_clear(vmx);
3112
f5f7b2fe 3113 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3114
3115 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3116 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3117 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3118 vmcs_writel(GUEST_RFLAGS, flags);
3119
66aee91a
RR		 3120 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3121 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3122
3123 update_exception_bitmap(vcpu);
3124
91b0aa2c
GN		 3125 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3126 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3127 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3128 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3129 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3130 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3131
3132 /* CPL is always 0 when CPU enters protected mode */
3133 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3134 vmx->cpl = 0;
6aa8b732
AK		 3135}
3136
f5f7b2fe 3137static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3138{
772e0318 3139 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3140 struct kvm_segment var = *save;
3141
3142 var.dpl = 0x3;
3143 if (seg == VCPU_SREG_CS)
3144 var.type = 0x3;
3145
3146 if (!emulate_invalid_guest_state) {
3147 var.selector = var.base >> 4;
3148 var.base = var.base & 0xffff0;
3149 var.limit = 0xffff;
3150 var.g = 0;
3151 var.db = 0;
3152 var.present = 1;
3153 var.s = 1;
3154 var.l = 0;
3155 var.unusable = 0;
3156 var.type = 0x3;
3157 var.avl = 0;
3158 if (save->base & 0xf)
3159 printk_once(KERN_WARNING "kvm: segment base is not "
3160 "paragraph aligned when entering "
3161 "protected mode (seg=%d)", seg);
3162 }
6aa8b732 3163
d99e4152
GN		 3164 vmcs_write16(sf->selector, var.selector);
3165 vmcs_write32(sf->base, var.base);
3166 vmcs_write32(sf->limit, var.limit);
3167 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3168}
3169
3170static void enter_rmode(struct kvm_vcpu *vcpu)
3171{
3172 unsigned long flags;
a89a8fb9 3173 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3174
f5f7b2fe
AK		 3175 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3176 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3177 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3178 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3179 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3180 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3181 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3182
7ffd92c5 3183 vmx->rmode.vm86_active = 1;
6aa8b732 3184
776e58ea
GN		 3185 /*
3186 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3187 * vcpu. Warn the user that an update is overdue.
776e58ea 3188 */
4918c6ca 3189 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3190 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3191 "called before entering vcpu\n");
776e58ea 3192
2fb92db1
AK		 3193 vmx_segment_cache_clear(vmx);
3194
4918c6ca 3195 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3196 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3197 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3198
3199 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3200 vmx->rmode.save_rflags = flags;
6aa8b732 3201
053de044 3202 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3203
3204 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3205 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3206 update_exception_bitmap(vcpu);
3207
d99e4152
GN		 3208 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3209 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3210 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3211 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3212 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3213 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3214
8668a3c4 3215 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3216}
3217
401d10de
AS		 3218static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3219{
3220 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3221 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3222
3223 if (!msr)
3224 return;
401d10de 3225
44ea2b17
AK		 3226 /*
3227 * Force kernel_gs_base reloading before EFER changes, as control
3228 * of this msr depends on is_long_mode().
3229 */
3230 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3231 vcpu->arch.efer = efer;
401d10de 3232 if (efer & EFER_LMA) {
2961e876 3233 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3234 msr->data = efer;
3235 } else {
2961e876 3236 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3237
3238 msr->data = efer & ~EFER_LME;
3239 }
3240 setup_msrs(vmx);
3241}
3242
05b3e0c2 3243#ifdef CONFIG_X86_64
6aa8b732
AK		 3244
3245static void enter_lmode(struct kvm_vcpu *vcpu)
3246{
3247 u32 guest_tr_ar;
3248
2fb92db1
AK		 3249 vmx_segment_cache_clear(to_vmx(vcpu));
3250
6aa8b732
AK		 3251 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3252 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3253 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3254 __func__);
6aa8b732
AK		 3255 vmcs_write32(GUEST_TR_AR_BYTES,
3256 (guest_tr_ar & ~AR_TYPE_MASK)
3257 | AR_TYPE_BUSY_64_TSS);
3258 }
da38f438 3259 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3260}
3261
3262static void exit_lmode(struct kvm_vcpu *vcpu)
3263{
2961e876 3264 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3265 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3266}
3267
3268#endif
3269
2384d2b3
SY		 3270static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3271{
b9d762fa 3272 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3273 if (enable_ept) {
3274 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3275 return;
4e1096d2 3276 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3277 }
2384d2b3
SY		 3278}
3279
e8467fda
AK		 3280static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3281{
3282 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3283
3284 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3285 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3286}
3287
aff48baa
AK		 3288static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3289{
3290 if (enable_ept && is_paging(vcpu))
3291 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3292 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3293}
3294
25c4c276 3295static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3296{
fc78f519
AK		 3297 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3298
3299 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3300 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3301}
3302
1439442c
SY		 3303static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3304{
d0d538b9
GN		 3305 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3306
6de4f3ad
AK		 3307 if (!test_bit(VCPU_EXREG_PDPTR,
3308 (unsigned long *)&vcpu->arch.regs_dirty))
3309 return;
3310
1439442c 3311 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3312 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3313 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3314 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3315 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3316 }
3317}
3318
8f5d549f
AK		 3319static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3320{
d0d538b9
GN		 3321 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3322
8f5d549f 3323 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3324 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3325 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3326 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3327 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3328 }
6de4f3ad
AK		 3329
3330 __set_bit(VCPU_EXREG_PDPTR,
3331 (unsigned long *)&vcpu->arch.regs_avail);
3332 __set_bit(VCPU_EXREG_PDPTR,
3333 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3334}
3335
5e1746d6 3336static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3337
3338static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3339 unsigned long cr0,
3340 struct kvm_vcpu *vcpu)
3341{
5233dd51
MT		 3342 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3343 vmx_decache_cr3(vcpu);
1439442c
SY		 3344 if (!(cr0 & X86_CR0_PG)) {
3345 /* From paging/starting to nonpaging */
3346 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3347 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3348 (CPU_BASED_CR3_LOAD_EXITING |
3349 CPU_BASED_CR3_STORE_EXITING));
3350 vcpu->arch.cr0 = cr0;
fc78f519 3351 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3352 } else if (!is_paging(vcpu)) {
3353 /* From nonpaging to paging */
3354 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3355 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3356 ~(CPU_BASED_CR3_LOAD_EXITING |
3357 CPU_BASED_CR3_STORE_EXITING));
3358 vcpu->arch.cr0 = cr0;
fc78f519 3359 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3360 }
95eb84a7
SY		 3361
3362 if (!(cr0 & X86_CR0_WP))
3363 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3364}
3365
6aa8b732
AK		 3366static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3367{
7ffd92c5 3368 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3369 unsigned long hw_cr0;
3370
5037878e 3371 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3372 if (enable_unrestricted_guest)
5037878e 3373 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3374 else {
5037878e 3375 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3376
218e763f
GN		 3377 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3378 enter_pmode(vcpu);
6aa8b732 3379
218e763f
GN		 3380 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3381 enter_rmode(vcpu);
3382 }
6aa8b732 3383
05b3e0c2 3384#ifdef CONFIG_X86_64
f6801dff 3385 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3386 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3387 enter_lmode(vcpu);
707d92fa 3388 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3389 exit_lmode(vcpu);
3390 }
3391#endif
3392
089d034e 3393 if (enable_ept)
1439442c
SY		 3394 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3395
02daab21 3396 if (!vcpu->fpu_active)
81231c69 3397 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3398
6aa8b732 3399 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3400 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3401 vcpu->arch.cr0 = cr0;
14168786
GN		 3402
3403 /* depends on vcpu->arch.cr0 to be set to a new value */
3404 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3405}
3406
1439442c
SY		 3407static u64 construct_eptp(unsigned long root_hpa)
3408{
3409 u64 eptp;
3410
3411 /* TODO write the value reading from MSR */
3412 eptp = VMX_EPT_DEFAULT_MT |
3413 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3414 if (enable_ept_ad_bits)
3415 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3416 eptp |= (root_hpa & PAGE_MASK);
3417
3418 return eptp;
3419}
3420
6aa8b732
AK		 3421static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3422{
1439442c
SY		 3423 unsigned long guest_cr3;
3424 u64 eptp;
3425
3426 guest_cr3 = cr3;
089d034e 3427 if (enable_ept) {
1439442c
SY		 3428 eptp = construct_eptp(cr3);
3429 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3430 if (is_paging(vcpu) || is_guest_mode(vcpu))
3431 guest_cr3 = kvm_read_cr3(vcpu);
3432 else
3433 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3434 ept_load_pdptrs(vcpu);
1439442c
SY		 3435 }
3436
2384d2b3 3437 vmx_flush_tlb(vcpu);
1439442c 3438 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3439}
3440
5e1746d6 3441static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3442{
7ffd92c5 3443 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3444 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3445
5e1746d6
NHE		 3446 if (cr4 & X86_CR4_VMXE) {
3447 /*
3448 * To use VMXON (and later other VMX instructions), a guest
3449 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3450 * So basically the check on whether to allow nested VMX
3451 * is here.
3452 */
3453 if (!nested_vmx_allowed(vcpu))
3454 return 1;
1a0d74e6
JK		 3455 }
3456 if (to_vmx(vcpu)->nested.vmxon &&
3457 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3458 return 1;
3459
ad312c7c 3460 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3461 if (enable_ept) {
3462 if (!is_paging(vcpu)) {
3463 hw_cr4 &= ~X86_CR4_PAE;
3464 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3465 /*
3466 * SMEP is disabled if CPU is in non-paging mode in
3467 * hardware. However KVM always uses paging mode to
3468 * emulate guest non-paging mode with TDP.
3469 * To emulate this behavior, SMEP needs to be manually
3470 * disabled when guest switches to non-paging mode.
3471 */
3472 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3473 } else if (!(cr4 & X86_CR4_PAE)) {
3474 hw_cr4 &= ~X86_CR4_PAE;
3475 }
3476 }
1439442c
SY		 3477
3478 vmcs_writel(CR4_READ_SHADOW, cr4);
3479 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3480 return 0;
6aa8b732
AK		 3481}
3482
6aa8b732
AK		 3483static void vmx_get_segment(struct kvm_vcpu *vcpu,
3484 struct kvm_segment *var, int seg)
3485{
a9179499 3486 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3487 u32 ar;
3488
c6ad1153 3489 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3490 *var = vmx->rmode.segs[seg];
a9179499 3491 if (seg == VCPU_SREG_TR
2fb92db1 3492 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3493 return;
1390a28b
AK		 3494 var->base = vmx_read_guest_seg_base(vmx, seg);
3495 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3496 return;
a9179499 3497 }
2fb92db1
AK		 3498 var->base = vmx_read_guest_seg_base(vmx, seg);
3499 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3500 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3501 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3502 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3503 var->type = ar & 15;
3504 var->s = (ar >> 4) & 1;
3505 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3506 /*
3507 * Some userspaces do not preserve unusable property. Since usable
3508 * segment has to be present according to VMX spec we can use present
3509 * property to amend userspace bug by making unusable segment always
3510 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3511 * segment as unusable.
3512 */
3513 var->present = !var->unusable;
6aa8b732
AK		 3514 var->avl = (ar >> 12) & 1;
3515 var->l = (ar >> 13) & 1;
3516 var->db = (ar >> 14) & 1;
3517 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3518}
3519
a9179499
AK		 3520static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3521{
a9179499
AK		 3522 struct kvm_segment s;
3523
3524 if (to_vmx(vcpu)->rmode.vm86_active) {
3525 vmx_get_segment(vcpu, &s, seg);
3526 return s.base;
3527 }
2fb92db1 3528 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3529}
3530
b09408d0 3531static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3532{
b09408d0
MT		 3533 struct vcpu_vmx *vmx = to_vmx(vcpu);
3534
3eeb3288 3535 if (!is_protmode(vcpu))
2e4d2653
IE		 3536 return 0;
3537
f4c63e5d
AK		 3538 if (!is_long_mode(vcpu)
3539 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3540 return 3;
3541
69c73028
AK		 3542 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3543 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3544 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3545 }
d881e6f6
AK		 3546
3547 return vmx->cpl;
69c73028
AK		 3548}
3549
3550
653e3108 3551static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3552{
6aa8b732
AK		 3553 u32 ar;
3554
f0495f9b 3555 if (var->unusable || !var->present)
6aa8b732
AK		 3556 ar = 1 << 16;
3557 else {
3558 ar = var->type & 15;
3559 ar |= (var->s & 1) << 4;
3560 ar |= (var->dpl & 3) << 5;
3561 ar |= (var->present & 1) << 7;
3562 ar |= (var->avl & 1) << 12;
3563 ar |= (var->l & 1) << 13;
3564 ar |= (var->db & 1) << 14;
3565 ar |= (var->g & 1) << 15;
3566 }
653e3108
AK		 3567
3568 return ar;
3569}
3570
3571static void vmx_set_segment(struct kvm_vcpu *vcpu,
3572 struct kvm_segment *var, int seg)
3573{
7ffd92c5 3574 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3575 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3576
2fb92db1 3577 vmx_segment_cache_clear(vmx);
2f143240
GN		 3578 if (seg == VCPU_SREG_CS)
3579 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3580
1ecd50a9
GN		 3581 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3582 vmx->rmode.segs[seg] = *var;
3583 if (seg == VCPU_SREG_TR)
3584 vmcs_write16(sf->selector, var->selector);
3585 else if (var->s)
3586 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3587 goto out;
653e3108 3588 }
1ecd50a9 3589
653e3108
AK		 3590 vmcs_writel(sf->base, var->base);
3591 vmcs_write32(sf->limit, var->limit);
3592 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3593
3594 /*
3595 * Fix the "Accessed" bit in AR field of segment registers for older
3596 * qemu binaries.
3597 * IA32 arch specifies that at the time of processor reset the
3598 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3599 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3600 * state vmexit when "unrestricted guest" mode is turned on.
3601 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3602 * tree. Newer qemu binaries with that qemu fix would not need this
3603 * kvm hack.
3604 */
3605 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3606 var->type |= 0x1; /* Accessed */
3a624e29 3607
f924d66d 3608 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3609
3610out:
14168786 3611 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3612}
3613
6aa8b732
AK		 3614static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3615{
2fb92db1 3616 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3617
3618 *db = (ar >> 14) & 1;
3619 *l = (ar >> 13) & 1;
3620}
3621
89a27f4d 3622static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3623{
89a27f4d
GN		 3624 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3625 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3626}
3627
89a27f4d 3628static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3629{
89a27f4d
GN		 3630 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3631 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3632}
3633
89a27f4d 3634static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3635{
89a27f4d
GN		 3636 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3637 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3638}
3639
89a27f4d 3640static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3641{
89a27f4d
GN		 3642 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3643 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3644}
3645
648dfaa7
MG		 3646static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3647{
3648 struct kvm_segment var;
3649 u32 ar;
3650
3651 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3652 var.dpl = 0x3;
0647f4aa
GN		 3653 if (seg == VCPU_SREG_CS)
3654 var.type = 0x3;
648dfaa7
MG		 3655 ar = vmx_segment_access_rights(&var);
3656
3657 if (var.base != (var.selector << 4))
3658 return false;
89efbed0 3659 if (var.limit != 0xffff)
648dfaa7 3660 return false;
07f42f5f 3661 if (ar != 0xf3)
648dfaa7
MG		 3662 return false;
3663
3664 return true;
3665}
3666
3667static bool code_segment_valid(struct kvm_vcpu *vcpu)
3668{
3669 struct kvm_segment cs;
3670 unsigned int cs_rpl;
3671
3672 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3673 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3674
1872a3f4
AK		 3675 if (cs.unusable)
3676 return false;
648dfaa7
MG		 3677 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3678 return false;
3679 if (!cs.s)
3680 return false;
1872a3f4 3681 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3682 if (cs.dpl > cs_rpl)
3683 return false;
1872a3f4 3684 } else {
648dfaa7
MG		 3685 if (cs.dpl != cs_rpl)
3686 return false;
3687 }
3688 if (!cs.present)
3689 return false;
3690
3691 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3692 return true;
3693}
3694
3695static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3696{
3697 struct kvm_segment ss;
3698 unsigned int ss_rpl;
3699
3700 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3701 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3702
1872a3f4
AK		 3703 if (ss.unusable)
3704 return true;
3705 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3706 return false;
3707 if (!ss.s)
3708 return false;
3709 if (ss.dpl != ss_rpl) /* DPL != RPL */
3710 return false;
3711 if (!ss.present)
3712 return false;
3713
3714 return true;
3715}
3716
3717static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3718{
3719 struct kvm_segment var;
3720 unsigned int rpl;
3721
3722 vmx_get_segment(vcpu, &var, seg);
3723 rpl = var.selector & SELECTOR_RPL_MASK;
3724
1872a3f4
AK		 3725 if (var.unusable)
3726 return true;
648dfaa7
MG		 3727 if (!var.s)
3728 return false;
3729 if (!var.present)
3730 return false;
3731 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3732 if (var.dpl < rpl) /* DPL < RPL */
3733 return false;
3734 }
3735
3736 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3737 * rights flags
3738 */
3739 return true;
3740}
3741
3742static bool tr_valid(struct kvm_vcpu *vcpu)
3743{
3744 struct kvm_segment tr;
3745
3746 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3747
1872a3f4
AK		 3748 if (tr.unusable)
3749 return false;
648dfaa7
MG		 3750 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3751 return false;
1872a3f4 3752 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3753 return false;
3754 if (!tr.present)
3755 return false;
3756
3757 return true;
3758}
3759
3760static bool ldtr_valid(struct kvm_vcpu *vcpu)
3761{
3762 struct kvm_segment ldtr;
3763
3764 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3765
1872a3f4
AK		 3766 if (ldtr.unusable)
3767 return true;
648dfaa7
MG		 3768 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3769 return false;
3770 if (ldtr.type != 2)
3771 return false;
3772 if (!ldtr.present)
3773 return false;
3774
3775 return true;
3776}
3777
3778static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3779{
3780 struct kvm_segment cs, ss;
3781
3782 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3783 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3784
3785 return ((cs.selector & SELECTOR_RPL_MASK) ==
3786 (ss.selector & SELECTOR_RPL_MASK));
3787}
3788
3789/*
3790 * Check if guest state is valid. Returns true if valid, false if
3791 * not.
3792 * We assume that registers are always usable
3793 */
3794static bool guest_state_valid(struct kvm_vcpu *vcpu)
3795{
c5e97c80
GN		 3796 if (enable_unrestricted_guest)
3797 return true;
3798
648dfaa7 3799 /* real mode guest state checks */
f13882d8 3800 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3801 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3802 return false;
3803 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3804 return false;
3805 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3806 return false;
3807 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3808 return false;
3809 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3810 return false;
3811 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3812 return false;
3813 } else {
3814 /* protected mode guest state checks */
3815 if (!cs_ss_rpl_check(vcpu))
3816 return false;
3817 if (!code_segment_valid(vcpu))
3818 return false;
3819 if (!stack_segment_valid(vcpu))
3820 return false;
3821 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3822 return false;
3823 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3824 return false;
3825 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3826 return false;
3827 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3828 return false;
3829 if (!tr_valid(vcpu))
3830 return false;
3831 if (!ldtr_valid(vcpu))
3832 return false;
3833 }
3834 /* TODO:
3835 * - Add checks on RIP
3836 * - Add checks on RFLAGS
3837 */
3838
3839 return true;
3840}
3841
d77c26fc 3842static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3843{
40dcaa9f 3844 gfn_t fn;
195aefde 3845 u16 data = 0;
40dcaa9f 3846 int r, idx, ret = 0;
6aa8b732 3847
40dcaa9f 3848 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3849 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3850 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3851 if (r < 0)
10589a46 3852 goto out;
195aefde 3853 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3854 r = kvm_write_guest_page(kvm, fn++, &data,
3855 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3856 if (r < 0)
10589a46 3857 goto out;
195aefde
IE		 3858 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3859 if (r < 0)
10589a46 3860 goto out;
195aefde
IE		 3861 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3862 if (r < 0)
10589a46 3863 goto out;
195aefde 3864 data = ~0;
10589a46
MT		 3865 r = kvm_write_guest_page(kvm, fn, &data,
3866 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3867 sizeof(u8));
195aefde 3868 if (r < 0)
10589a46
MT		 3869 goto out;
3870
3871 ret = 1;
3872out:
40dcaa9f 3873 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3874 return ret;
6aa8b732
AK		 3875}
3876
b7ebfb05
SY		 3877static int init_rmode_identity_map(struct kvm *kvm)
3878{
40dcaa9f 3879 int i, idx, r, ret;
b7ebfb05
SY		 3880 pfn_t identity_map_pfn;
3881 u32 tmp;
3882
089d034e 3883 if (!enable_ept)
b7ebfb05
SY		 3884 return 1;
3885 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3886 printk(KERN_ERR "EPT: identity-mapping pagetable "
3887 "haven't been allocated!\n");
3888 return 0;
3889 }
3890 if (likely(kvm->arch.ept_identity_pagetable_done))
3891 return 1;
3892 ret = 0;
b927a3ce 3893 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3894 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3895 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3896 if (r < 0)
3897 goto out;
3898 /* Set up identity-mapping pagetable for EPT in real mode */
3899 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3900 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3901 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3902 r = kvm_write_guest_page(kvm, identity_map_pfn,
3903 &tmp, i * sizeof(tmp), sizeof(tmp));
3904 if (r < 0)
3905 goto out;
3906 }
3907 kvm->arch.ept_identity_pagetable_done = true;
3908 ret = 1;
3909out:
40dcaa9f 3910 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3911 return ret;
3912}
3913
6aa8b732
AK		 3914static void seg_setup(int seg)
3915{
772e0318 3916 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3917 unsigned int ar;
6aa8b732
AK		 3918
3919 vmcs_write16(sf->selector, 0);
3920 vmcs_writel(sf->base, 0);
3921 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3922 ar = 0x93;
3923 if (seg == VCPU_SREG_CS)
3924 ar |= 0x08; /* code segment */
3a624e29
NK		 3925
3926 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3927}
3928
f78e0e2e
SY		 3929static int alloc_apic_access_page(struct kvm *kvm)
3930{
4484141a 3931 struct page *page;
f78e0e2e
SY		 3932 struct kvm_userspace_memory_region kvm_userspace_mem;
3933 int r = 0;
3934
79fac95e 3935 mutex_lock(&kvm->slots_lock);
bfc6d222 3936 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3937 goto out;
3938 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3939 kvm_userspace_mem.flags = 0;
3940 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3941 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3942 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3943 if (r)
3944 goto out;
72dc67a6 3945
4484141a
XG		 3946 page = gfn_to_page(kvm, 0xfee00);
3947 if (is_error_page(page)) {
3948 r = -EFAULT;
3949 goto out;
3950 }
3951
3952 kvm->arch.apic_access_page = page;
f78e0e2e 3953out:
79fac95e 3954 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3955 return r;
3956}
3957
b7ebfb05
SY		 3958static int alloc_identity_pagetable(struct kvm *kvm)
3959{
4484141a 3960 struct page *page;
b7ebfb05
SY		 3961 struct kvm_userspace_memory_region kvm_userspace_mem;
3962 int r = 0;
3963
79fac95e 3964 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3965 if (kvm->arch.ept_identity_pagetable)
3966 goto out;
3967 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3968 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3969 kvm_userspace_mem.guest_phys_addr =
3970 kvm->arch.ept_identity_map_addr;
b7ebfb05 3971 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3972 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3973 if (r)
3974 goto out;
3975
4484141a
XG		 3976 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3977 if (is_error_page(page)) {
3978 r = -EFAULT;
3979 goto out;
3980 }
3981
3982 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3983out:
79fac95e 3984 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3985 return r;
3986}
3987
2384d2b3
SY		 3988static void allocate_vpid(struct vcpu_vmx *vmx)
3989{
3990 int vpid;
3991
3992 vmx->vpid = 0;
919818ab 3993 if (!enable_vpid)
2384d2b3
SY		 3994 return;
3995 spin_lock(&vmx_vpid_lock);
3996 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3997 if (vpid < VMX_NR_VPIDS) {
3998 vmx->vpid = vpid;
3999 __set_bit(vpid, vmx_vpid_bitmap);
4000 }
4001 spin_unlock(&vmx_vpid_lock);
4002}
4003
cdbecfc3
LJ		 4004static void free_vpid(struct vcpu_vmx *vmx)
4005{
4006 if (!enable_vpid)
4007 return;
4008 spin_lock(&vmx_vpid_lock);
4009 if (vmx->vpid != 0)
4010 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4011 spin_unlock(&vmx_vpid_lock);
4012}
4013
8d14695f
YZ		 4014#define MSR_TYPE_R 1
4015#define MSR_TYPE_W 2
4016static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4017 u32 msr, int type)
25c5f225 4018{
3e7c73e9 4019 int f = sizeof(unsigned long);
25c5f225
SY		 4020
4021 if (!cpu_has_vmx_msr_bitmap())
4022 return;
4023
4024 /*
4025 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4026 * have the write-low and read-high bitmap offsets the wrong way round.
4027 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4028 */
25c5f225 4029 if (msr <= 0x1fff) {
8d14695f
YZ		 4030 if (type & MSR_TYPE_R)
4031 /* read-low */
4032 __clear_bit(msr, msr_bitmap + 0x000 / f);
4033
4034 if (type & MSR_TYPE_W)
4035 /* write-low */
4036 __clear_bit(msr, msr_bitmap + 0x800 / f);
4037
25c5f225
SY		 4038 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4039 msr &= 0x1fff;
8d14695f
YZ		 4040 if (type & MSR_TYPE_R)
4041 /* read-high */
4042 __clear_bit(msr, msr_bitmap + 0x400 / f);
4043
4044 if (type & MSR_TYPE_W)
4045 /* write-high */
4046 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4047
4048 }
4049}
4050
4051static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4052 u32 msr, int type)
4053{
4054 int f = sizeof(unsigned long);
4055
4056 if (!cpu_has_vmx_msr_bitmap())
4057 return;
4058
4059 /*
4060 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4061 * have the write-low and read-high bitmap offsets the wrong way round.
4062 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4063 */
4064 if (msr <= 0x1fff) {
4065 if (type & MSR_TYPE_R)
4066 /* read-low */
4067 __set_bit(msr, msr_bitmap + 0x000 / f);
4068
4069 if (type & MSR_TYPE_W)
4070 /* write-low */
4071 __set_bit(msr, msr_bitmap + 0x800 / f);
4072
4073 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4074 msr &= 0x1fff;
4075 if (type & MSR_TYPE_R)
4076 /* read-high */
4077 __set_bit(msr, msr_bitmap + 0x400 / f);
4078
4079 if (type & MSR_TYPE_W)
4080 /* write-high */
4081 __set_bit(msr, msr_bitmap + 0xc00 / f);
4082
25c5f225 4083 }
25c5f225
SY		 4084}
4085
5897297b
AK		 4086static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4087{
4088 if (!longmode_only)
8d14695f
YZ		 4089 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4090 msr, MSR_TYPE_R | MSR_TYPE_W);
4091 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4092 msr, MSR_TYPE_R | MSR_TYPE_W);
4093}
4094
4095static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4096{
4097 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4098 msr, MSR_TYPE_R);
4099 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4100 msr, MSR_TYPE_R);
4101}
4102
4103static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4104{
4105 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4106 msr, MSR_TYPE_R);
4107 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4108 msr, MSR_TYPE_R);
4109}
4110
4111static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4112{
4113 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4114 msr, MSR_TYPE_W);
4115 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4116 msr, MSR_TYPE_W);
5897297b
AK		 4117}
4118
01e439be
YZ		 4119static int vmx_vm_has_apicv(struct kvm *kvm)
4120{
4121 return enable_apicv && irqchip_in_kernel(kvm);
4122}
4123
a20ed54d
YZ		 4124/*
4125 * Send interrupt to vcpu via posted interrupt way.
4126 * 1. If target vcpu is running(non-root mode), send posted interrupt
4127 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4128 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4129 * interrupt from PIR in next vmentry.
4130 */
4131static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4132{
4133 struct vcpu_vmx *vmx = to_vmx(vcpu);
4134 int r;
4135
4136 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4137 return;
4138
4139 r = pi_test_and_set_on(&vmx->pi_desc);
4140 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4141#ifdef CONFIG_SMP
a20ed54d
YZ		 4142 if (!r && (vcpu->mode == IN_GUEST_MODE))
4143 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4144 POSTED_INTR_VECTOR);
4145 else
6ffbbbba 4146#endif
a20ed54d
YZ		 4147 kvm_vcpu_kick(vcpu);
4148}
4149
4150static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4151{
4152 struct vcpu_vmx *vmx = to_vmx(vcpu);
4153
4154 if (!pi_test_and_clear_on(&vmx->pi_desc))
4155 return;
4156
4157 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4158}
4159
4160static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4161{
4162 return;
4163}
4164
a3a8ff8e
NHE		 4165/*
4166 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4167 * will not change in the lifetime of the guest.
4168 * Note that host-state that does change is set elsewhere. E.g., host-state
4169 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4170 */
a547c6db 4171static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4172{
4173 u32 low32, high32;
4174 unsigned long tmpl;
4175 struct desc_ptr dt;
4176
b1a74bf8 4177 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4178 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4179 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4180
4181 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4182#ifdef CONFIG_X86_64
4183 /*
4184 * Load null selectors, so we can avoid reloading them in
4185 * __vmx_load_host_state(), in case userspace uses the null selectors
4186 * too (the expected case).
4187 */
4188 vmcs_write16(HOST_DS_SELECTOR, 0);
4189 vmcs_write16(HOST_ES_SELECTOR, 0);
4190#else
a3a8ff8e
NHE		 4191 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4192 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4193#endif
a3a8ff8e
NHE		 4194 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4195 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4196
4197 native_store_idt(&dt);
4198 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4199 vmx->host_idt_base = dt.address;
a3a8ff8e 4200
83287ea4 4201 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4202
4203 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4204 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4205 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4206 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4207
4208 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4209 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4210 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4211 }
4212}
4213
bf8179a0
NHE		 4214static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4215{
4216 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4217 if (enable_ept)
4218 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4219 if (is_guest_mode(&vmx->vcpu))
4220 vmx->vcpu.arch.cr4_guest_owned_bits &=
4221 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4222 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4223}
4224
01e439be
YZ		 4225static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4226{
4227 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4228
4229 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4230 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4231 return pin_based_exec_ctrl;
4232}
4233
bf8179a0
NHE		 4234static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4235{
4236 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4237 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4238 exec_control &= ~CPU_BASED_TPR_SHADOW;
4239#ifdef CONFIG_X86_64
4240 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4241 CPU_BASED_CR8_LOAD_EXITING;
4242#endif
4243 }
4244 if (!enable_ept)
4245 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4246 CPU_BASED_CR3_LOAD_EXITING |
4247 CPU_BASED_INVLPG_EXITING;
4248 return exec_control;
4249}
4250
4251static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4252{
4253 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4254 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4255 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4256 if (vmx->vpid == 0)
4257 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4258 if (!enable_ept) {
4259 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4260 enable_unrestricted_guest = 0;
ad756a16
MJ		 4261 /* Enable INVPCID for non-ept guests may cause performance regression. */
4262 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4263 }
4264 if (!enable_unrestricted_guest)
4265 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4266 if (!ple_gap)
4267 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4268 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4269 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4270 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4271 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4272 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4273 (handle_vmptrld).
4274 We can NOT enable shadow_vmcs here because we don't have yet
4275 a current VMCS12
4276 */
4277 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4278 return exec_control;
4279}
4280
ce88decf
XG		 4281static void ept_set_mmio_spte_mask(void)
4282{
4283 /*
4284 * EPT Misconfigurations can be generated if the value of bits 2:0
4285 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4286 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4287 * spte.
4288 */
885032b9 4289 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4290}
4291
6aa8b732
AK		 4292/*
4293 * Sets up the vmcs for emulated real mode.
4294 */
8b9cf98c 4295static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4296{
2e4ce7f5 4297#ifdef CONFIG_X86_64
6aa8b732 4298 unsigned long a;
2e4ce7f5 4299#endif
6aa8b732 4300 int i;
6aa8b732 4301
6aa8b732 4302 /* I/O */
3e7c73e9
AK		 4303 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4304 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4305
4607c2d7
AG		 4306 if (enable_shadow_vmcs) {
4307 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4308 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4309 }
25c5f225 4310 if (cpu_has_vmx_msr_bitmap())
5897297b 4311 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4312
6aa8b732
AK		 4313 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4314
6aa8b732 4315 /* Control */
01e439be 4316 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4317
bf8179a0 4318 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4319
83ff3b9d 4320 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4321 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4322 vmx_secondary_exec_control(vmx));
83ff3b9d 4323 }
f78e0e2e 4324
01e439be 4325 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4326 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4327 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4328 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4329 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4330
4331 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4332
4333 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4334 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4335 }
4336
4b8d54f9
ZE		 4337 if (ple_gap) {
4338 vmcs_write32(PLE_GAP, ple_gap);
4339 vmcs_write32(PLE_WINDOW, ple_window);
4340 }
4341
c3707958
XG		 4342 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4343 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4344 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4345
9581d442
AK		 4346 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4347 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4348 vmx_set_constant_host_state(vmx);
05b3e0c2 4349#ifdef CONFIG_X86_64
6aa8b732
AK		 4350 rdmsrl(MSR_FS_BASE, a);
4351 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4352 rdmsrl(MSR_GS_BASE, a);
4353 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4354#else
4355 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4356 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4357#endif
4358
2cc51560
ED		 4359 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4360 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4361 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4362 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4363 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4364
468d472f 4365 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4366 u32 msr_low, msr_high;
4367 u64 host_pat;
468d472f
SY		 4368 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4369 host_pat = msr_low | ((u64) msr_high << 32);
4370 /* Write the default value follow host pat */
4371 vmcs_write64(GUEST_IA32_PAT, host_pat);
4372 /* Keep arch.pat sync with GUEST_IA32_PAT */
4373 vmx->vcpu.arch.pat = host_pat;
4374 }
4375
6aa8b732
AK		 4376 for (i = 0; i < NR_VMX_MSR; ++i) {
4377 u32 index = vmx_msr_index[i];
4378 u32 data_low, data_high;
a2fa3e9f 4379 int j = vmx->nmsrs;
6aa8b732
AK		 4380
4381 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4382 continue;
432bd6cb
AK		 4383 if (wrmsr_safe(index, data_low, data_high) < 0)
4384 continue;
26bb0981
AK		 4385 vmx->guest_msrs[j].index = i;
4386 vmx->guest_msrs[j].data = 0;
d5696725 4387 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4388 ++vmx->nmsrs;
6aa8b732 4389 }
6aa8b732 4390
2961e876
GN		 4391
4392 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4393
4394 /* 22.2.1, 20.8.1 */
2961e876 4395 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4396
e00c8cf2 4397 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4398 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4399
4400 return 0;
4401}
4402
57f252f2 4403static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4404{
4405 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4406 struct msr_data apic_base_msr;
e00c8cf2 4407
7ffd92c5 4408 vmx->rmode.vm86_active = 0;
e00c8cf2 4409
3b86cd99
JK		 4410 vmx->soft_vnmi_blocked = 0;
4411
ad312c7c 4412 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4413 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4414 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4415 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4416 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4417 apic_base_msr.host_initiated = true;
4418 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4419
2fb92db1
AK		 4420 vmx_segment_cache_clear(vmx);
4421
5706be0d 4422 seg_setup(VCPU_SREG_CS);
66450a21 4423 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4424 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4425
4426 seg_setup(VCPU_SREG_DS);
4427 seg_setup(VCPU_SREG_ES);
4428 seg_setup(VCPU_SREG_FS);
4429 seg_setup(VCPU_SREG_GS);
4430 seg_setup(VCPU_SREG_SS);
4431
4432 vmcs_write16(GUEST_TR_SELECTOR, 0);
4433 vmcs_writel(GUEST_TR_BASE, 0);
4434 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4435 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4436
4437 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4438 vmcs_writel(GUEST_LDTR_BASE, 0);
4439 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4440 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4441
4442 vmcs_write32(GUEST_SYSENTER_CS, 0);
4443 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4444 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4445
4446 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4447 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4448
e00c8cf2
AK		 4449 vmcs_writel(GUEST_GDTR_BASE, 0);
4450 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4451
4452 vmcs_writel(GUEST_IDTR_BASE, 0);
4453 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4454
443381a8 4455 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4456 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4457 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4458
e00c8cf2
AK		 4459 /* Special registers */
4460 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4461
4462 setup_msrs(vmx);
4463
6aa8b732
AK		 4464 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4465
f78e0e2e
SY		 4466 if (cpu_has_vmx_tpr_shadow()) {
4467 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4468 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4469 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4470 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4471 vmcs_write32(TPR_THRESHOLD, 0);
4472 }
4473
4474 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4475 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4476 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4477
01e439be
YZ		 4478 if (vmx_vm_has_apicv(vcpu->kvm))
4479 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4480
2384d2b3
SY		 4481 if (vmx->vpid != 0)
4482 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4483
fa40052c 4484 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4485 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4486 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4487 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4488 vmx_fpu_activate(&vmx->vcpu);
4489 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4490
b9d762fa 4491 vpid_sync_context(vmx);
6aa8b732
AK		 4492}
4493
b6f1250e
NHE		 4494/*
4495 * In nested virtualization, check if L1 asked to exit on external interrupts.
4496 * For most existing hypervisors, this will always return true.
4497 */
4498static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4499{
4500 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4501 PIN_BASED_EXT_INTR_MASK;
4502}
4503
ea8ceb83
JK		 4504static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4505{
4506 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4507 PIN_BASED_NMI_EXITING;
4508}
4509
730dca42 4510static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4511{
4512 u32 cpu_based_vm_exec_control;
730dca42
JK		 4513
4514 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4515 /*
4516 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4517 * inject to L1 now because L2 must run. The caller will have
4518 * to make L2 exit right after entry, so we can inject to L1
4519 * more promptly.
b6f1250e 4520 */
730dca42 4521 return -EBUSY;
3b86cd99
JK		 4522
4523 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4524 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4525 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4526 return 0;
3b86cd99
JK		 4527}
4528
03b28f81 4529static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4530{
4531 u32 cpu_based_vm_exec_control;
4532
03b28f81
JK		 4533 if (!cpu_has_virtual_nmis())
4534 return enable_irq_window(vcpu);
4535
4536 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4537 return enable_irq_window(vcpu);
3b86cd99
JK		 4538
4539 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4540 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4542 return 0;
3b86cd99
JK		 4543}
4544
66fd3f7f 4545static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4546{
9c8cba37 4547 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4548 uint32_t intr;
4549 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4550
229456fc 4551 trace_kvm_inj_virq(irq);
2714d1d3 4552
fa89a817 4553 ++vcpu->stat.irq_injections;
7ffd92c5 4554 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4555 int inc_eip = 0;
4556 if (vcpu->arch.interrupt.soft)
4557 inc_eip = vcpu->arch.event_exit_inst_len;
4558 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4559 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4560 return;
4561 }
66fd3f7f
GN		 4562 intr = irq | INTR_INFO_VALID_MASK;
4563 if (vcpu->arch.interrupt.soft) {
4564 intr |= INTR_TYPE_SOFT_INTR;
4565 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4566 vmx->vcpu.arch.event_exit_inst_len);
4567 } else
4568 intr |= INTR_TYPE_EXT_INTR;
4569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4570}
4571
f08864b4
SY		 4572static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4573{
66a5a347
JK		 4574 struct vcpu_vmx *vmx = to_vmx(vcpu);
4575
0b6ac343
NHE		 4576 if (is_guest_mode(vcpu))
4577 return;
4578
3b86cd99
JK		 4579 if (!cpu_has_virtual_nmis()) {
4580 /*
4581 * Tracking the NMI-blocked state in software is built upon
4582 * finding the next open IRQ window. This, in turn, depends on
4583 * well-behaving guests: They have to keep IRQs disabled at
4584 * least as long as the NMI handler runs. Otherwise we may
4585 * cause NMI nesting, maybe breaking the guest. But as this is
4586 * highly unlikely, we can live with the residual risk.
4587 */
4588 vmx->soft_vnmi_blocked = 1;
4589 vmx->vnmi_blocked_time = 0;
4590 }
4591
487b391d 4592 ++vcpu->stat.nmi_injections;
9d58b931 4593 vmx->nmi_known_unmasked = false;
7ffd92c5 4594 if (vmx->rmode.vm86_active) {
71f9833b 4595 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4596 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4597 return;
4598 }
f08864b4
SY		 4599 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4600 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4601}
4602
3cfc3092
JK		 4603static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4604{
4605 if (!cpu_has_virtual_nmis())
4606 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4607 if (to_vmx(vcpu)->nmi_known_unmasked)
4608 return false;
c332c83a 4609 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4610}
4611
4612static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4613{
4614 struct vcpu_vmx *vmx = to_vmx(vcpu);
4615
4616 if (!cpu_has_virtual_nmis()) {
4617 if (vmx->soft_vnmi_blocked != masked) {
4618 vmx->soft_vnmi_blocked = masked;
4619 vmx->vnmi_blocked_time = 0;
4620 }
4621 } else {
9d58b931 4622 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4623 if (masked)
4624 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4625 GUEST_INTR_STATE_NMI);
4626 else
4627 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4628 GUEST_INTR_STATE_NMI);
4629 }
4630}
4631
2505dc9f
JK		 4632static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4633{
ea8ceb83 4634 if (is_guest_mode(vcpu)) {
ea8ceb83
JK		 4635 if (to_vmx(vcpu)->nested.nested_run_pending)
4636 return 0;
4637 if (nested_exit_on_nmi(vcpu)) {
533558bc
JK		 4638 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
4639 NMI_VECTOR | INTR_TYPE_NMI_INTR |
4640 INTR_INFO_VALID_MASK, 0);
ea8ceb83
JK		 4641 /*
4642 * The NMI-triggered VM exit counts as injection:
4643 * clear this one and block further NMIs.
4644 */
4645 vcpu->arch.nmi_pending = 0;
4646 vmx_set_nmi_mask(vcpu, true);
4647 return 0;
4648 }
4649 }
4650
2505dc9f
JK		 4651 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4652 return 0;
4653
4654 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4655 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4656 | GUEST_INTR_STATE_NMI));
4657}
4658
78646121
GN		 4659static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4660{
e8457c67 4661 if (is_guest_mode(vcpu)) {
e8457c67 4662 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4663 return 0;
e8457c67 4664 if (nested_exit_on_intr(vcpu)) {
533558bc
JK		 4665 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT,
4666 0, 0);
e8457c67
JK		 4667 /*
4668 * fall through to normal code, but now in L1, not L2
4669 */
4670 }
b6f1250e
NHE		 4671 }
4672
c4282df9
GN		 4673 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4674 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4675 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4676}
4677
cbc94022
IE		 4678static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4679{
4680 int ret;
4681 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4682 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4683 .guest_phys_addr = addr,
4684 .memory_size = PAGE_SIZE * 3,
4685 .flags = 0,
4686 };
4687
47ae31e2 4688 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4689 if (ret)
4690 return ret;
bfc6d222 4691 kvm->arch.tss_addr = addr;
93ea5388
GN		 4692 if (!init_rmode_tss(kvm))
4693 return -ENOMEM;
4694
cbc94022
IE		 4695 return 0;
4696}
4697
0ca1b4f4 4698static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4699{
77ab6db0 4700 switch (vec) {
77ab6db0 4701 case BP_VECTOR:
c573cd22
JK		 4702 /*
4703 * Update instruction length as we may reinject the exception
4704 * from user space while in guest debugging mode.
4705 */
4706 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4707 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4708 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4709 return false;
4710 /* fall through */
4711 case DB_VECTOR:
4712 if (vcpu->guest_debug &
4713 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4714 return false;
d0bfb940
JK		 4715 /* fall through */
4716 case DE_VECTOR:
77ab6db0
JK		 4717 case OF_VECTOR:
4718 case BR_VECTOR:
4719 case UD_VECTOR:
4720 case DF_VECTOR:
4721 case SS_VECTOR:
4722 case GP_VECTOR:
4723 case MF_VECTOR:
0ca1b4f4
GN		 4724 return true;
4725 break;
77ab6db0 4726 }
0ca1b4f4
GN		 4727 return false;
4728}
4729
4730static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4731 int vec, u32 err_code)
4732{
4733 /*
4734 * Instruction with address size override prefix opcode 0x67
4735 * Cause the #SS fault with 0 error code in VM86 mode.
4736 */
4737 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4738 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4739 if (vcpu->arch.halt_request) {
4740 vcpu->arch.halt_request = 0;
4741 return kvm_emulate_halt(vcpu);
4742 }
4743 return 1;
4744 }
4745 return 0;
4746 }
4747
4748 /*
4749 * Forward all other exceptions that are valid in real mode.
4750 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4751 * the required debugging infrastructure rework.
4752 */
4753 kvm_queue_exception(vcpu, vec);
4754 return 1;
6aa8b732
AK		 4755}
4756
a0861c02
AK		 4757/*
4758 * Trigger machine check on the host. We assume all the MSRs are already set up
4759 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4760 * We pass a fake environment to the machine check handler because we want
4761 * the guest to be always treated like user space, no matter what context
4762 * it used internally.
4763 */
4764static void kvm_machine_check(void)
4765{
4766#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4767 struct pt_regs regs = {
4768 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4769 .flags = X86_EFLAGS_IF,
4770 };
4771
4772 do_machine_check(&regs, 0);
4773#endif
4774}
4775
851ba692 4776static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4777{
4778 /* already handled by vcpu_run */
4779 return 1;
4780}
4781
851ba692 4782static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4783{
1155f76a 4784 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4785 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4786 u32 intr_info, ex_no, error_code;
42dbaa5a 4787 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4788 u32 vect_info;
4789 enum emulation_result er;
4790
1155f76a 4791 vect_info = vmx->idt_vectoring_info;
88786475 4792 intr_info = vmx->exit_intr_info;
6aa8b732 4793
a0861c02 4794 if (is_machine_check(intr_info))
851ba692 4795 return handle_machine_check(vcpu);
a0861c02 4796
e4a41889 4797 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4798 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4799
4800 if (is_no_device(intr_info)) {
5fd86fcf 4801 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4802 return 1;
4803 }
4804
7aa81cc0 4805 if (is_invalid_opcode(intr_info)) {
51d8b661 4806 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4807 if (er != EMULATE_DONE)
7ee5d940 4808 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4809 return 1;
4810 }
4811
6aa8b732 4812 error_code = 0;
2e11384c 4813 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4814 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4815
4816 /*
4817 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4818 * MMIO, it is better to report an internal error.
4819 * See the comments in vmx_handle_exit.
4820 */
4821 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4822 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4823 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4824 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4825 vcpu->run->internal.ndata = 2;
4826 vcpu->run->internal.data[0] = vect_info;
4827 vcpu->run->internal.data[1] = intr_info;
4828 return 0;
4829 }
4830
6aa8b732 4831 if (is_page_fault(intr_info)) {
1439442c 4832 /* EPT won't cause page fault directly */
cf3ace79 4833 BUG_ON(enable_ept);
6aa8b732 4834 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4835 trace_kvm_page_fault(cr2, error_code);
4836
3298b75c 4837 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4838 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4839 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4840 }
4841
d0bfb940 4842 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4843
4844 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4845 return handle_rmode_exception(vcpu, ex_no, error_code);
4846
42dbaa5a
JK		 4847 switch (ex_no) {
4848 case DB_VECTOR:
4849 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4850 if (!(vcpu->guest_debug &
4851 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4852 vcpu->arch.dr6 &= ~15;
4853 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4854 kvm_queue_exception(vcpu, DB_VECTOR);
4855 return 1;
4856 }
4857 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4858 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4859 /* fall through */
4860 case BP_VECTOR:
c573cd22
JK		 4861 /*
4862 * Update instruction length as we may reinject #BP from
4863 * user space while in guest debugging mode. Reading it for
4864 * #DB as well causes no harm, it is not used in that case.
4865 */
4866 vmx->vcpu.arch.event_exit_inst_len =
4867 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4868 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4869 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4870 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4871 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4872 break;
4873 default:
d0bfb940
JK		 4874 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4875 kvm_run->ex.exception = ex_no;
4876 kvm_run->ex.error_code = error_code;
42dbaa5a 4877 break;
6aa8b732 4878 }
6aa8b732
AK		 4879 return 0;
4880}
4881
851ba692 4882static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4883{
1165f5fe 4884 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4885 return 1;
4886}
4887
851ba692 4888static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4889{
851ba692 4890 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4891 return 0;
4892}
6aa8b732 4893
851ba692 4894static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4895{
bfdaab09 4896 unsigned long exit_qualification;
34c33d16 4897 int size, in, string;
039576c0 4898 unsigned port;
6aa8b732 4899
bfdaab09 4900 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4901 string = (exit_qualification & 16) != 0;
cf8f70bf 4902 in = (exit_qualification & 8) != 0;
e70669ab 4903
cf8f70bf 4904 ++vcpu->stat.io_exits;
e70669ab 4905
cf8f70bf 4906 if (string || in)
51d8b661 4907 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4908
cf8f70bf
GN		 4909 port = exit_qualification >> 16;
4910 size = (exit_qualification & 7) + 1;
e93f36bc 4911 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4912
4913 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4914}
4915
102d8325
IM		 4916static void
4917vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4918{
4919 /*
4920 * Patch in the VMCALL instruction:
4921 */
4922 hypercall[0] = 0x0f;
4923 hypercall[1] = 0x01;
4924 hypercall[2] = 0xc1;
102d8325
IM		 4925}
4926
92fbc7b1
JK		 4927static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4928{
4929 unsigned long always_on = VMXON_CR0_ALWAYSON;
4930
4931 if (nested_vmx_secondary_ctls_high &
4932 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4933 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4934 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4935 return (val & always_on) == always_on;
4936}
4937
0fa06071 4938/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4939static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4940{
eeadf9e7 4941 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4942 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4943 unsigned long orig_val = val;
4944
eeadf9e7
NHE		 4945 /*
4946 * We get here when L2 changed cr0 in a way that did not change
4947 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4948 * but did change L0 shadowed bits. So we first calculate the
4949 * effective cr0 value that L1 would like to write into the
4950 * hardware. It consists of the L2-owned bits from the new
4951 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4952 */
1a0d74e6
JK		 4953 val = (val & ~vmcs12->cr0_guest_host_mask) |
4954 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4955
92fbc7b1 4956 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4957 return 1;
1a0d74e6
JK		 4958
4959 if (kvm_set_cr0(vcpu, val))
4960 return 1;
4961 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4962 return 0;
1a0d74e6
JK		 4963 } else {
4964 if (to_vmx(vcpu)->nested.vmxon &&
4965 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4966 return 1;
eeadf9e7 4967 return kvm_set_cr0(vcpu, val);
1a0d74e6 4968 }
eeadf9e7
NHE		 4969}
4970
4971static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4972{
4973 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4974 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4975 unsigned long orig_val = val;
4976
4977 /* analogously to handle_set_cr0 */
4978 val = (val & ~vmcs12->cr4_guest_host_mask) |
4979 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4980 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4981 return 1;
1a0d74e6 4982 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4983 return 0;
4984 } else
4985 return kvm_set_cr4(vcpu, val);
4986}
4987
4988/* called to set cr0 as approriate for clts instruction exit. */
4989static void handle_clts(struct kvm_vcpu *vcpu)
4990{
4991 if (is_guest_mode(vcpu)) {
4992 /*
4993 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4994 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4995 * just pretend it's off (also in arch.cr0 for fpu_activate).
4996 */
4997 vmcs_writel(CR0_READ_SHADOW,
4998 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4999 vcpu->arch.cr0 &= ~X86_CR0_TS;
5000 } else
5001 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5002}
5003
851ba692 5004static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5005{
229456fc 5006 unsigned long exit_qualification, val;
6aa8b732
AK		 5007 int cr;
5008 int reg;
49a9b07e 5009 int err;
6aa8b732 5010
bfdaab09 5011 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5012 cr = exit_qualification & 15;
5013 reg = (exit_qualification >> 8) & 15;
5014 switch ((exit_qualification >> 4) & 3) {
5015 case 0: /* mov to cr */
229456fc
MT		 5016 val = kvm_register_read(vcpu, reg);
5017 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5018 switch (cr) {
5019 case 0:
eeadf9e7 5020 err = handle_set_cr0(vcpu, val);
db8fcefa 5021 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5022 return 1;
5023 case 3:
2390218b 5024 err = kvm_set_cr3(vcpu, val);
db8fcefa 5025 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5026 return 1;
5027 case 4:
eeadf9e7 5028 err = handle_set_cr4(vcpu, val);
db8fcefa 5029 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5030 return 1;
0a5fff19
GN		 5031 case 8: {
5032 u8 cr8_prev = kvm_get_cr8(vcpu);
5033 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5034 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5035 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5036 if (irqchip_in_kernel(vcpu->kvm))
5037 return 1;
5038 if (cr8_prev <= cr8)
5039 return 1;
851ba692 5040 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5041 return 0;
5042 }
4b8073e4 5043 }
6aa8b732 5044 break;
25c4c276 5045 case 2: /* clts */
eeadf9e7 5046 handle_clts(vcpu);
4d4ec087 5047 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5048 skip_emulated_instruction(vcpu);
6b52d186 5049 vmx_fpu_activate(vcpu);
25c4c276 5050 return 1;
6aa8b732
AK		 5051 case 1: /*mov from cr*/
5052 switch (cr) {
5053 case 3:
9f8fe504
AK		 5054 val = kvm_read_cr3(vcpu);
5055 kvm_register_write(vcpu, reg, val);
5056 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5057 skip_emulated_instruction(vcpu);
5058 return 1;
5059 case 8:
229456fc
MT		 5060 val = kvm_get_cr8(vcpu);
5061 kvm_register_write(vcpu, reg, val);
5062 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5063 skip_emulated_instruction(vcpu);
5064 return 1;
5065 }
5066 break;
5067 case 3: /* lmsw */
a1f83a74 5068 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5069 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5070 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5071
5072 skip_emulated_instruction(vcpu);
5073 return 1;
5074 default:
5075 break;
5076 }
851ba692 5077 vcpu->run->exit_reason = 0;
a737f256 5078 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5079 (int)(exit_qualification >> 4) & 3, cr);
5080 return 0;
5081}
5082
851ba692 5083static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5084{
bfdaab09 5085 unsigned long exit_qualification;
6aa8b732
AK		 5086 int dr, reg;
5087
f2483415 5088 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5089 if (!kvm_require_cpl(vcpu, 0))
5090 return 1;
42dbaa5a
JK		 5091 dr = vmcs_readl(GUEST_DR7);
5092 if (dr & DR7_GD) {
5093 /*
5094 * As the vm-exit takes precedence over the debug trap, we
5095 * need to emulate the latter, either for the host or the
5096 * guest debugging itself.
5097 */
5098 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5099 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5100 vcpu->run->debug.arch.dr7 = dr;
5101 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5102 vmcs_readl(GUEST_CS_BASE) +
5103 vmcs_readl(GUEST_RIP);
851ba692
AK		 5104 vcpu->run->debug.arch.exception = DB_VECTOR;
5105 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5106 return 0;
5107 } else {
5108 vcpu->arch.dr7 &= ~DR7_GD;
5109 vcpu->arch.dr6 |= DR6_BD;
5110 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5111 kvm_queue_exception(vcpu, DB_VECTOR);
5112 return 1;
5113 }
5114 }
5115
bfdaab09 5116 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5117 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5118 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5119 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5120 unsigned long val;
4c4d563b
JK		 5121
5122 if (kvm_get_dr(vcpu, dr, &val))
5123 return 1;
5124 kvm_register_write(vcpu, reg, val);
020df079 5125 } else
4c4d563b
JK		 5126 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5127 return 1;
5128
6aa8b732
AK		 5129 skip_emulated_instruction(vcpu);
5130 return 1;
5131}
5132
73aaf249
JK		 5133static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5134{
5135 return vcpu->arch.dr6;
5136}
5137
5138static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5139{
5140}
5141
020df079
GN		 5142static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5143{
5144 vmcs_writel(GUEST_DR7, val);
5145}
5146
851ba692 5147static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5148{
06465c5a
AK		 5149 kvm_emulate_cpuid(vcpu);
5150 return 1;
6aa8b732
AK		 5151}
5152
851ba692 5153static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5154{
ad312c7c 5155 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5156 u64 data;
5157
5158 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5159 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5160 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5161 return 1;
5162 }
5163
229456fc 5164 trace_kvm_msr_read(ecx, data);
2714d1d3 5165
6aa8b732 5166 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5167 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5168 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5169 skip_emulated_instruction(vcpu);
5170 return 1;
5171}
5172
851ba692 5173static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5174{
8fe8ab46 5175 struct msr_data msr;
ad312c7c
ZX		 5176 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5177 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5178 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5179
8fe8ab46
WA		 5180 msr.data = data;
5181 msr.index = ecx;
5182 msr.host_initiated = false;
5183 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5184 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5185 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5186 return 1;
5187 }
5188
59200273 5189 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5190 skip_emulated_instruction(vcpu);
5191 return 1;
5192}
5193
851ba692 5194static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5195{
3842d135 5196 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5197 return 1;
5198}
5199
851ba692 5200static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5201{
85f455f7
ED		 5202 u32 cpu_based_vm_exec_control;
5203
5204 /* clear pending irq */
5205 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5206 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5207 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5208
3842d135
AK		 5209 kvm_make_request(KVM_REQ_EVENT, vcpu);
5210
a26bf12a 5211 ++vcpu->stat.irq_window_exits;
2714d1d3 5212
c1150d8c
DL		 5213 /*
5214 * If the user space waits to inject interrupts, exit as soon as
5215 * possible
5216 */
8061823a 5217 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5218 vcpu->run->request_interrupt_window &&
8061823a 5219 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5220 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5221 return 0;
5222 }
6aa8b732
AK		 5223 return 1;
5224}
5225
851ba692 5226static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5227{
5228 skip_emulated_instruction(vcpu);
d3bef15f 5229 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5230}
5231
851ba692 5232static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5233{
510043da 5234 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5235 kvm_emulate_hypercall(vcpu);
5236 return 1;
c21415e8
IM		 5237}
5238
ec25d5e6
GN		 5239static int handle_invd(struct kvm_vcpu *vcpu)
5240{
51d8b661 5241 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5242}
5243
851ba692 5244static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5245{
f9c617f6 5246 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5247
5248 kvm_mmu_invlpg(vcpu, exit_qualification);
5249 skip_emulated_instruction(vcpu);
5250 return 1;
5251}
5252
fee84b07
AK		 5253static int handle_rdpmc(struct kvm_vcpu *vcpu)
5254{
5255 int err;
5256
5257 err = kvm_rdpmc(vcpu);
5258 kvm_complete_insn_gp(vcpu, err);
5259
5260 return 1;
5261}
5262
851ba692 5263static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5264{
5265 skip_emulated_instruction(vcpu);
f5f48ee1 5266 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5267 return 1;
5268}
5269
2acf923e
DC		 5270static int handle_xsetbv(struct kvm_vcpu *vcpu)
5271{
5272 u64 new_bv = kvm_read_edx_eax(vcpu);
5273 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5274
5275 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5276 skip_emulated_instruction(vcpu);
5277 return 1;
5278}
5279
851ba692 5280static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5281{
58fbbf26
KT		 5282 if (likely(fasteoi)) {
5283 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5284 int access_type, offset;
5285
5286 access_type = exit_qualification & APIC_ACCESS_TYPE;
5287 offset = exit_qualification & APIC_ACCESS_OFFSET;
5288 /*
5289 * Sane guest uses MOV to write EOI, with written value
5290 * not cared. So make a short-circuit here by avoiding
5291 * heavy instruction emulation.
5292 */
5293 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5294 (offset == APIC_EOI)) {
5295 kvm_lapic_set_eoi(vcpu);
5296 skip_emulated_instruction(vcpu);
5297 return 1;
5298 }
5299 }
51d8b661 5300 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5301}
5302
c7c9c56c
YZ		 5303static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5304{
5305 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5306 int vector = exit_qualification & 0xff;
5307
5308 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5309 kvm_apic_set_eoi_accelerated(vcpu, vector);
5310 return 1;
5311}
5312
83d4c286
YZ		 5313static int handle_apic_write(struct kvm_vcpu *vcpu)
5314{
5315 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5316 u32 offset = exit_qualification & 0xfff;
5317
5318 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5319 kvm_apic_write_nodecode(vcpu, offset);
5320 return 1;
5321}
5322
851ba692 5323static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5324{
60637aac 5325 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5326 unsigned long exit_qualification;
e269fb21
JK		 5327 bool has_error_code = false;
5328 u32 error_code = 0;
37817f29 5329 u16 tss_selector;
7f3d35fd 5330 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5331
5332 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5333 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5334 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5335
5336 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5337
5338 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5339 if (reason == TASK_SWITCH_GATE && idt_v) {
5340 switch (type) {
5341 case INTR_TYPE_NMI_INTR:
5342 vcpu->arch.nmi_injected = false;
654f06fc 5343 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5344 break;
5345 case INTR_TYPE_EXT_INTR:
66fd3f7f 5346 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5347 kvm_clear_interrupt_queue(vcpu);
5348 break;
5349 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5350 if (vmx->idt_vectoring_info &
5351 VECTORING_INFO_DELIVER_CODE_MASK) {
5352 has_error_code = true;
5353 error_code =
5354 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5355 }
5356 /* fall through */
64a7ec06
GN		 5357 case INTR_TYPE_SOFT_EXCEPTION:
5358 kvm_clear_exception_queue(vcpu);
5359 break;
5360 default:
5361 break;
5362 }
60637aac 5363 }
37817f29
IE		 5364 tss_selector = exit_qualification;
5365
64a7ec06
GN		 5366 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5367 type != INTR_TYPE_EXT_INTR &&
5368 type != INTR_TYPE_NMI_INTR))
5369 skip_emulated_instruction(vcpu);
5370
7f3d35fd
KW		 5371 if (kvm_task_switch(vcpu, tss_selector,
5372 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5373 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5374 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5375 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5376 vcpu->run->internal.ndata = 0;
42dbaa5a 5377 return 0;
acb54517 5378 }
42dbaa5a
JK		 5379
5380 /* clear all local breakpoint enable flags */
5381 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5382
5383 /*
5384 * TODO: What about debug traps on tss switch?
5385 * Are we supposed to inject them and update dr6?
5386 */
5387
5388 return 1;
37817f29
IE		 5389}
5390
851ba692 5391static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5392{
f9c617f6 5393 unsigned long exit_qualification;
1439442c 5394 gpa_t gpa;
4f5982a5 5395 u32 error_code;
1439442c 5396 int gla_validity;
1439442c 5397
f9c617f6 5398 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5399
1439442c
SY		 5400 gla_validity = (exit_qualification >> 7) & 0x3;
5401 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5402 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5403 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5404 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5405 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5406 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5407 (long unsigned int)exit_qualification);
851ba692
AK		 5408 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5409 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5410 return 0;
1439442c
SY		 5411 }
5412
0be9c7a8
GN		 5413 /*
5414 * EPT violation happened while executing iret from NMI,
5415 * "blocked by NMI" bit has to be set before next VM entry.
5416 * There are errata that may cause this bit to not be set:
5417 * AAK134, BY25.
5418 */
bcd1c294
GN		 5419 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5420 cpu_has_virtual_nmis() &&
5421 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5422 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5423
1439442c 5424 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5425 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5426
5427 /* It is a write fault? */
5428 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5429 /* It is a fetch fault? */
5430 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5431 /* ept page table is present? */
5432 error_code |= (exit_qualification >> 3) & 0x1;
5433
25d92081
YZ		 5434 vcpu->arch.exit_qualification = exit_qualification;
5435
4f5982a5 5436 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5437}
5438
68f89400
MT		 5439static u64 ept_rsvd_mask(u64 spte, int level)
5440{
5441 int i;
5442 u64 mask = 0;
5443
5444 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5445 mask |= (1ULL << i);
5446
5447 if (level > 2)
5448 /* bits 7:3 reserved */
5449 mask |= 0xf8;
5450 else if (level == 2) {
5451 if (spte & (1ULL << 7))
5452 /* 2MB ref, bits 20:12 reserved */
5453 mask |= 0x1ff000;
5454 else
5455 /* bits 6:3 reserved */
5456 mask |= 0x78;
5457 }
5458
5459 return mask;
5460}
5461
5462static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5463 int level)
5464{
5465 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5466
5467 /* 010b (write-only) */
5468 WARN_ON((spte & 0x7) == 0x2);
5469
5470 /* 110b (write/execute) */
5471 WARN_ON((spte & 0x7) == 0x6);
5472
5473 /* 100b (execute-only) and value not supported by logical processor */
5474 if (!cpu_has_vmx_ept_execute_only())
5475 WARN_ON((spte & 0x7) == 0x4);
5476
5477 /* not 000b */
5478 if ((spte & 0x7)) {
5479 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5480
5481 if (rsvd_bits != 0) {
5482 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5483 __func__, rsvd_bits);
5484 WARN_ON(1);
5485 }
5486
5487 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5488 u64 ept_mem_type = (spte & 0x38) >> 3;
5489
5490 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5491 ept_mem_type == 7) {
5492 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5493 __func__, ept_mem_type);
5494 WARN_ON(1);
5495 }
5496 }
5497 }
5498}
5499
851ba692 5500static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5501{
5502 u64 sptes[4];
ce88decf 5503 int nr_sptes, i, ret;
68f89400
MT		 5504 gpa_t gpa;
5505
5506 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5507
ce88decf 5508 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5509 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5510 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5511 EMULATE_DONE;
f8f55942
XG		 5512
5513 if (unlikely(ret == RET_MMIO_PF_INVALID))
5514 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5515
b37fbea6 5516 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5517 return 1;
5518
5519 /* It is the real ept misconfig */
68f89400
MT		 5520 printk(KERN_ERR "EPT: Misconfiguration.\n");
5521 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5522
5523 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5524
5525 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5526 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5527
851ba692
AK		 5528 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5529 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5530
5531 return 0;
5532}
5533
851ba692 5534static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5535{
5536 u32 cpu_based_vm_exec_control;
5537
5538 /* clear pending NMI */
5539 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5540 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5542 ++vcpu->stat.nmi_window_exits;
3842d135 5543 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5544
5545 return 1;
5546}
5547
80ced186 5548static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5549{
8b3079a5
AK		 5550 struct vcpu_vmx *vmx = to_vmx(vcpu);
5551 enum emulation_result err = EMULATE_DONE;
80ced186 5552 int ret = 1;
49e9d557
AK		 5553 u32 cpu_exec_ctrl;
5554 bool intr_window_requested;
b8405c18 5555 unsigned count = 130;
49e9d557
AK		 5556
5557 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5558 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5559
b8405c18 5560 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5561 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5562 return handle_interrupt_window(&vmx->vcpu);
5563
de87dcdd
AK		 5564 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5565 return 1;
5566
991eebf9 5567 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5568
ac0a48c3 5569 if (err == EMULATE_USER_EXIT) {
94452b9e 5570 ++vcpu->stat.mmio_exits;
80ced186
MG		 5571 ret = 0;
5572 goto out;
5573 }
1d5a4d9b 5574
de5f70e0
AK		 5575 if (err != EMULATE_DONE) {
5576 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5577 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5578 vcpu->run->internal.ndata = 0;
6d77dbfc 5579 return 0;
de5f70e0 5580 }
ea953ef0 5581
8d76c49e
GN		 5582 if (vcpu->arch.halt_request) {
5583 vcpu->arch.halt_request = 0;
5584 ret = kvm_emulate_halt(vcpu);
5585 goto out;
5586 }
5587
ea953ef0 5588 if (signal_pending(current))
80ced186 5589 goto out;
ea953ef0
MG		 5590 if (need_resched())
5591 schedule();
5592 }
5593
14168786 5594 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5595out:
5596 return ret;
ea953ef0
MG		 5597}
5598
4b8d54f9
ZE		 5599/*
5600 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5601 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5602 */
9fb41ba8 5603static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5604{
5605 skip_emulated_instruction(vcpu);
5606 kvm_vcpu_on_spin(vcpu);
5607
5608 return 1;
5609}
5610
59708670
SY		 5611static int handle_invalid_op(struct kvm_vcpu *vcpu)
5612{
5613 kvm_queue_exception(vcpu, UD_VECTOR);
5614 return 1;
5615}
5616
ff2f6fe9
NHE		 5617/*
5618 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5619 * We could reuse a single VMCS for all the L2 guests, but we also want the
5620 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5621 * allows keeping them loaded on the processor, and in the future will allow
5622 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5623 * every entry if they never change.
5624 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5625 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5626 *
5627 * The following functions allocate and free a vmcs02 in this pool.
5628 */
5629
5630/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5631static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5632{
5633 struct vmcs02_list *item;
5634 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5635 if (item->vmptr == vmx->nested.current_vmptr) {
5636 list_move(&item->list, &vmx->nested.vmcs02_pool);
5637 return &item->vmcs02;
5638 }
5639
5640 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5641 /* Recycle the least recently used VMCS. */
5642 item = list_entry(vmx->nested.vmcs02_pool.prev,
5643 struct vmcs02_list, list);
5644 item->vmptr = vmx->nested.current_vmptr;
5645 list_move(&item->list, &vmx->nested.vmcs02_pool);
5646 return &item->vmcs02;
5647 }
5648
5649 /* Create a new VMCS */
0fa24ce3 5650 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5651 if (!item)
5652 return NULL;
5653 item->vmcs02.vmcs = alloc_vmcs();
5654 if (!item->vmcs02.vmcs) {
5655 kfree(item);
5656 return NULL;
5657 }
5658 loaded_vmcs_init(&item->vmcs02);
5659 item->vmptr = vmx->nested.current_vmptr;
5660 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5661 vmx->nested.vmcs02_num++;
5662 return &item->vmcs02;
5663}
5664
5665/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5666static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5667{
5668 struct vmcs02_list *item;
5669 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5670 if (item->vmptr == vmptr) {
5671 free_loaded_vmcs(&item->vmcs02);
5672 list_del(&item->list);
5673 kfree(item);
5674 vmx->nested.vmcs02_num--;
5675 return;
5676 }
5677}
5678
5679/*
5680 * Free all VMCSs saved for this vcpu, except the one pointed by
5681 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5682 * currently used, if running L2), and vmcs01 when running L2.
5683 */
5684static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5685{
5686 struct vmcs02_list *item, *n;
5687 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5688 if (vmx->loaded_vmcs != &item->vmcs02)
5689 free_loaded_vmcs(&item->vmcs02);
5690 list_del(&item->list);
5691 kfree(item);
5692 }
5693 vmx->nested.vmcs02_num = 0;
5694
5695 if (vmx->loaded_vmcs != &vmx->vmcs01)
5696 free_loaded_vmcs(&vmx->vmcs01);
5697}
5698
0658fbaa
ACL		 5699/*
5700 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5701 * set the success or error code of an emulated VMX instruction, as specified
5702 * by Vol 2B, VMX Instruction Reference, "Conventions".
5703 */
5704static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5705{
5706 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5707 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5708 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5709}
5710
5711static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5712{
5713 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5714 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5715 X86_EFLAGS_SF | X86_EFLAGS_OF))
5716 | X86_EFLAGS_CF);
5717}
5718
145c28dd 5719static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5720 u32 vm_instruction_error)
5721{
5722 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5723 /*
5724 * failValid writes the error number to the current VMCS, which
5725 * can't be done there isn't a current VMCS.
5726 */
5727 nested_vmx_failInvalid(vcpu);
5728 return;
5729 }
5730 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5731 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5732 X86_EFLAGS_SF | X86_EFLAGS_OF))
5733 | X86_EFLAGS_ZF);
5734 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5735 /*
5736 * We don't need to force a shadow sync because
5737 * VM_INSTRUCTION_ERROR is not shadowed
5738 */
5739}
145c28dd 5740
ec378aee
NHE		 5741/*
5742 * Emulate the VMXON instruction.
5743 * Currently, we just remember that VMX is active, and do not save or even
5744 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5745 * do not currently need to store anything in that guest-allocated memory
5746 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5747 * argument is different from the VMXON pointer (which the spec says they do).
5748 */
5749static int handle_vmon(struct kvm_vcpu *vcpu)
5750{
5751 struct kvm_segment cs;
5752 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5753 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5754 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5755 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5756
5757 /* The Intel VMX Instruction Reference lists a bunch of bits that
5758 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5759 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5760 * Otherwise, we should fail with #UD. We test these now:
5761 */
5762 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5763 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5764 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5765 kvm_queue_exception(vcpu, UD_VECTOR);
5766 return 1;
5767 }
5768
5769 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5770 if (is_long_mode(vcpu) && !cs.l) {
5771 kvm_queue_exception(vcpu, UD_VECTOR);
5772 return 1;
5773 }
5774
5775 if (vmx_get_cpl(vcpu)) {
5776 kvm_inject_gp(vcpu, 0);
5777 return 1;
5778 }
145c28dd
AG		 5779 if (vmx->nested.vmxon) {
5780 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5781 skip_emulated_instruction(vcpu);
5782 return 1;
5783 }
b3897a49
NHE		 5784
5785 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5786 != VMXON_NEEDED_FEATURES) {
5787 kvm_inject_gp(vcpu, 0);
5788 return 1;
5789 }
5790
8de48833
AG		 5791 if (enable_shadow_vmcs) {
5792 shadow_vmcs = alloc_vmcs();
5793 if (!shadow_vmcs)
5794 return -ENOMEM;
5795 /* mark vmcs as shadow */
5796 shadow_vmcs->revision_id |= (1u << 31);
5797 /* init shadow vmcs */
5798 vmcs_clear(shadow_vmcs);
5799 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5800 }
ec378aee 5801
ff2f6fe9
NHE		 5802 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5803 vmx->nested.vmcs02_num = 0;
5804
ec378aee
NHE		 5805 vmx->nested.vmxon = true;
5806
5807 skip_emulated_instruction(vcpu);
a25eb114 5808 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5809 return 1;
5810}
5811
5812/*
5813 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5814 * for running VMX instructions (except VMXON, whose prerequisites are
5815 * slightly different). It also specifies what exception to inject otherwise.
5816 */
5817static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5818{
5819 struct kvm_segment cs;
5820 struct vcpu_vmx *vmx = to_vmx(vcpu);
5821
5822 if (!vmx->nested.vmxon) {
5823 kvm_queue_exception(vcpu, UD_VECTOR);
5824 return 0;
5825 }
5826
5827 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5828 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5829 (is_long_mode(vcpu) && !cs.l)) {
5830 kvm_queue_exception(vcpu, UD_VECTOR);
5831 return 0;
5832 }
5833
5834 if (vmx_get_cpl(vcpu)) {
5835 kvm_inject_gp(vcpu, 0);
5836 return 0;
5837 }
5838
5839 return 1;
5840}
5841
e7953d7f
AG		 5842static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5843{
8a1b9dd0 5844 u32 exec_control;
012f83cb
AG		 5845 if (enable_shadow_vmcs) {
5846 if (vmx->nested.current_vmcs12 != NULL) {
5847 /* copy to memory all shadowed fields in case
5848 they were modified */
5849 copy_shadow_to_vmcs12(vmx);
5850 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5851 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5852 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5853 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5854 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5855 }
5856 }
e7953d7f
AG		 5857 kunmap(vmx->nested.current_vmcs12_page);
5858 nested_release_page(vmx->nested.current_vmcs12_page);
5859}
5860
ec378aee
NHE		 5861/*
5862 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5863 * just stops using VMX.
5864 */
5865static void free_nested(struct vcpu_vmx *vmx)
5866{
5867 if (!vmx->nested.vmxon)
5868 return;
5869 vmx->nested.vmxon = false;
a9d30f33 5870 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5871 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5872 vmx->nested.current_vmptr = -1ull;
5873 vmx->nested.current_vmcs12 = NULL;
5874 }
e7953d7f
AG		 5875 if (enable_shadow_vmcs)
5876 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5877 /* Unpin physical memory we referred to in current vmcs02 */
5878 if (vmx->nested.apic_access_page) {
5879 nested_release_page(vmx->nested.apic_access_page);
5880 vmx->nested.apic_access_page = 0;
5881 }
ff2f6fe9
NHE		 5882
5883 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5884}
5885
5886/* Emulate the VMXOFF instruction */
5887static int handle_vmoff(struct kvm_vcpu *vcpu)
5888{
5889 if (!nested_vmx_check_permission(vcpu))
5890 return 1;
5891 free_nested(to_vmx(vcpu));
5892 skip_emulated_instruction(vcpu);
a25eb114 5893 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5894 return 1;
5895}
5896
064aea77
NHE		 5897/*
5898 * Decode the memory-address operand of a vmx instruction, as recorded on an
5899 * exit caused by such an instruction (run by a guest hypervisor).
5900 * On success, returns 0. When the operand is invalid, returns 1 and throws
5901 * #UD or #GP.
5902 */
5903static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5904 unsigned long exit_qualification,
5905 u32 vmx_instruction_info, gva_t *ret)
5906{
5907 /*
5908 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5909 * Execution", on an exit, vmx_instruction_info holds most of the
5910 * addressing components of the operand. Only the displacement part
5911 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5912 * For how an actual address is calculated from all these components,
5913 * refer to Vol. 1, "Operand Addressing".
5914 */
5915 int scaling = vmx_instruction_info & 3;
5916 int addr_size = (vmx_instruction_info >> 7) & 7;
5917 bool is_reg = vmx_instruction_info & (1u << 10);
5918 int seg_reg = (vmx_instruction_info >> 15) & 7;
5919 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5920 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5921 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5922 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5923
5924 if (is_reg) {
5925 kvm_queue_exception(vcpu, UD_VECTOR);
5926 return 1;
5927 }
5928
5929 /* Addr = segment_base + offset */
5930 /* offset = base + [index * scale] + displacement */
5931 *ret = vmx_get_segment_base(vcpu, seg_reg);
5932 if (base_is_valid)
5933 *ret += kvm_register_read(vcpu, base_reg);
5934 if (index_is_valid)
5935 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5936 *ret += exit_qualification; /* holds the displacement */
5937
5938 if (addr_size == 1) /* 32 bit */
5939 *ret &= 0xffffffff;
5940
5941 /*
5942 * TODO: throw #GP (and return 1) in various cases that the VM*
5943 * instructions require it - e.g., offset beyond segment limit,
5944 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5945 * address, and so on. Currently these are not checked.
5946 */
5947 return 0;
5948}
5949
27d6c865
NHE		 5950/* Emulate the VMCLEAR instruction */
5951static int handle_vmclear(struct kvm_vcpu *vcpu)
5952{
5953 struct vcpu_vmx *vmx = to_vmx(vcpu);
5954 gva_t gva;
5955 gpa_t vmptr;
5956 struct vmcs12 *vmcs12;
5957 struct page *page;
5958 struct x86_exception e;
5959
5960 if (!nested_vmx_check_permission(vcpu))
5961 return 1;
5962
5963 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5964 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5965 return 1;
5966
5967 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5968 sizeof(vmptr), &e)) {
5969 kvm_inject_page_fault(vcpu, &e);
5970 return 1;
5971 }
5972
5973 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5974 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5975 skip_emulated_instruction(vcpu);
5976 return 1;
5977 }
5978
5979 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5980 nested_release_vmcs12(vmx);
27d6c865
NHE		 5981 vmx->nested.current_vmptr = -1ull;
5982 vmx->nested.current_vmcs12 = NULL;
5983 }
5984
5985 page = nested_get_page(vcpu, vmptr);
5986 if (page == NULL) {
5987 /*
5988 * For accurate processor emulation, VMCLEAR beyond available
5989 * physical memory should do nothing at all. However, it is
5990 * possible that a nested vmx bug, not a guest hypervisor bug,
5991 * resulted in this case, so let's shut down before doing any
5992 * more damage:
5993 */
5994 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5995 return 1;
5996 }
5997 vmcs12 = kmap(page);
5998 vmcs12->launch_state = 0;
5999 kunmap(page);
6000 nested_release_page(page);
6001
6002 nested_free_vmcs02(vmx, vmptr);
6003
6004 skip_emulated_instruction(vcpu);
6005 nested_vmx_succeed(vcpu);
6006 return 1;
6007}
6008
cd232ad0
NHE		 6009static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6010
6011/* Emulate the VMLAUNCH instruction */
6012static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6013{
6014 return nested_vmx_run(vcpu, true);
6015}
6016
6017/* Emulate the VMRESUME instruction */
6018static int handle_vmresume(struct kvm_vcpu *vcpu)
6019{
6020
6021 return nested_vmx_run(vcpu, false);
6022}
6023
49f705c5
NHE		 6024enum vmcs_field_type {
6025 VMCS_FIELD_TYPE_U16 = 0,
6026 VMCS_FIELD_TYPE_U64 = 1,
6027 VMCS_FIELD_TYPE_U32 = 2,
6028 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6029};
6030
6031static inline int vmcs_field_type(unsigned long field)
6032{
6033 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6034 return VMCS_FIELD_TYPE_U32;
6035 return (field >> 13) & 0x3 ;
6036}
6037
6038static inline int vmcs_field_readonly(unsigned long field)
6039{
6040 return (((field >> 10) & 0x3) == 1);
6041}
6042
6043/*
6044 * Read a vmcs12 field. Since these can have varying lengths and we return
6045 * one type, we chose the biggest type (u64) and zero-extend the return value
6046 * to that size. Note that the caller, handle_vmread, might need to use only
6047 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6048 * 64-bit fields are to be returned).
6049 */
6050static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6051 unsigned long field, u64 *ret)
6052{
6053 short offset = vmcs_field_to_offset(field);
6054 char *p;
6055
6056 if (offset < 0)
6057 return 0;
6058
6059 p = ((char *)(get_vmcs12(vcpu))) + offset;
6060
6061 switch (vmcs_field_type(field)) {
6062 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6063 *ret = *((natural_width *)p);
6064 return 1;
6065 case VMCS_FIELD_TYPE_U16:
6066 *ret = *((u16 *)p);
6067 return 1;
6068 case VMCS_FIELD_TYPE_U32:
6069 *ret = *((u32 *)p);
6070 return 1;
6071 case VMCS_FIELD_TYPE_U64:
6072 *ret = *((u64 *)p);
6073 return 1;
6074 default:
6075 return 0; /* can never happen. */
6076 }
6077}
6078
20b97fea
AG		 6079
6080static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6081 unsigned long field, u64 field_value){
6082 short offset = vmcs_field_to_offset(field);
6083 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6084 if (offset < 0)
6085 return false;
6086
6087 switch (vmcs_field_type(field)) {
6088 case VMCS_FIELD_TYPE_U16:
6089 *(u16 *)p = field_value;
6090 return true;
6091 case VMCS_FIELD_TYPE_U32:
6092 *(u32 *)p = field_value;
6093 return true;
6094 case VMCS_FIELD_TYPE_U64:
6095 *(u64 *)p = field_value;
6096 return true;
6097 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6098 *(natural_width *)p = field_value;
6099 return true;
6100 default:
6101 return false; /* can never happen. */
6102 }
6103
6104}
6105
16f5b903
AG		 6106static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6107{
6108 int i;
6109 unsigned long field;
6110 u64 field_value;
6111 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6112 const unsigned long *fields = shadow_read_write_fields;
6113 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6114
6115 vmcs_load(shadow_vmcs);
6116
6117 for (i = 0; i < num_fields; i++) {
6118 field = fields[i];
6119 switch (vmcs_field_type(field)) {
6120 case VMCS_FIELD_TYPE_U16:
6121 field_value = vmcs_read16(field);
6122 break;
6123 case VMCS_FIELD_TYPE_U32:
6124 field_value = vmcs_read32(field);
6125 break;
6126 case VMCS_FIELD_TYPE_U64:
6127 field_value = vmcs_read64(field);
6128 break;
6129 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6130 field_value = vmcs_readl(field);
6131 break;
6132 }
6133 vmcs12_write_any(&vmx->vcpu, field, field_value);
6134 }
6135
6136 vmcs_clear(shadow_vmcs);
6137 vmcs_load(vmx->loaded_vmcs->vmcs);
6138}
6139
c3114420
AG		 6140static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6141{
c2bae893
MK		 6142 const unsigned long *fields[] = {
6143 shadow_read_write_fields,
6144 shadow_read_only_fields
c3114420 6145 };
c2bae893 6146 const int max_fields[] = {
c3114420
AG		 6147 max_shadow_read_write_fields,
6148 max_shadow_read_only_fields
6149 };
6150 int i, q;
6151 unsigned long field;
6152 u64 field_value = 0;
6153 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6154
6155 vmcs_load(shadow_vmcs);
6156
c2bae893 6157 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6158 for (i = 0; i < max_fields[q]; i++) {
6159 field = fields[q][i];
6160 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6161
6162 switch (vmcs_field_type(field)) {
6163 case VMCS_FIELD_TYPE_U16:
6164 vmcs_write16(field, (u16)field_value);
6165 break;
6166 case VMCS_FIELD_TYPE_U32:
6167 vmcs_write32(field, (u32)field_value);
6168 break;
6169 case VMCS_FIELD_TYPE_U64:
6170 vmcs_write64(field, (u64)field_value);
6171 break;
6172 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6173 vmcs_writel(field, (long)field_value);
6174 break;
6175 }
6176 }
6177 }
6178
6179 vmcs_clear(shadow_vmcs);
6180 vmcs_load(vmx->loaded_vmcs->vmcs);
6181}
6182
49f705c5
NHE		 6183/*
6184 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6185 * used before) all generate the same failure when it is missing.
6186 */
6187static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6188{
6189 struct vcpu_vmx *vmx = to_vmx(vcpu);
6190 if (vmx->nested.current_vmptr == -1ull) {
6191 nested_vmx_failInvalid(vcpu);
6192 skip_emulated_instruction(vcpu);
6193 return 0;
6194 }
6195 return 1;
6196}
6197
6198static int handle_vmread(struct kvm_vcpu *vcpu)
6199{
6200 unsigned long field;
6201 u64 field_value;
6202 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6203 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6204 gva_t gva = 0;
6205
6206 if (!nested_vmx_check_permission(vcpu) ||
6207 !nested_vmx_check_vmcs12(vcpu))
6208 return 1;
6209
6210 /* Decode instruction info and find the field to read */
6211 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6212 /* Read the field, zero-extended to a u64 field_value */
6213 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6214 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6215 skip_emulated_instruction(vcpu);
6216 return 1;
6217 }
6218 /*
6219 * Now copy part of this value to register or memory, as requested.
6220 * Note that the number of bits actually copied is 32 or 64 depending
6221 * on the guest's mode (32 or 64 bit), not on the given field's length.
6222 */
6223 if (vmx_instruction_info & (1u << 10)) {
6224 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6225 field_value);
6226 } else {
6227 if (get_vmx_mem_address(vcpu, exit_qualification,
6228 vmx_instruction_info, &gva))
6229 return 1;
6230 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6231 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6232 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6233 }
6234
6235 nested_vmx_succeed(vcpu);
6236 skip_emulated_instruction(vcpu);
6237 return 1;
6238}
6239
6240
6241static int handle_vmwrite(struct kvm_vcpu *vcpu)
6242{
6243 unsigned long field;
6244 gva_t gva;
6245 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6246 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6247 /* The value to write might be 32 or 64 bits, depending on L1's long
6248 * mode, and eventually we need to write that into a field of several
6249 * possible lengths. The code below first zero-extends the value to 64
6250 * bit (field_value), and then copies only the approriate number of
6251 * bits into the vmcs12 field.
6252 */
6253 u64 field_value = 0;
6254 struct x86_exception e;
6255
6256 if (!nested_vmx_check_permission(vcpu) ||
6257 !nested_vmx_check_vmcs12(vcpu))
6258 return 1;
6259
6260 if (vmx_instruction_info & (1u << 10))
6261 field_value = kvm_register_read(vcpu,
6262 (((vmx_instruction_info) >> 3) & 0xf));
6263 else {
6264 if (get_vmx_mem_address(vcpu, exit_qualification,
6265 vmx_instruction_info, &gva))
6266 return 1;
6267 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6268 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6269 kvm_inject_page_fault(vcpu, &e);
6270 return 1;
6271 }
6272 }
6273
6274
6275 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6276 if (vmcs_field_readonly(field)) {
6277 nested_vmx_failValid(vcpu,
6278 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6279 skip_emulated_instruction(vcpu);
6280 return 1;
6281 }
6282
20b97fea 6283 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6284 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6285 skip_emulated_instruction(vcpu);
6286 return 1;
6287 }
6288
6289 nested_vmx_succeed(vcpu);
6290 skip_emulated_instruction(vcpu);
6291 return 1;
6292}
6293
63846663
NHE		 6294/* Emulate the VMPTRLD instruction */
6295static int handle_vmptrld(struct kvm_vcpu *vcpu)
6296{
6297 struct vcpu_vmx *vmx = to_vmx(vcpu);
6298 gva_t gva;
6299 gpa_t vmptr;
6300 struct x86_exception e;
8a1b9dd0 6301 u32 exec_control;
63846663
NHE		 6302
6303 if (!nested_vmx_check_permission(vcpu))
6304 return 1;
6305
6306 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6307 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6308 return 1;
6309
6310 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6311 sizeof(vmptr), &e)) {
6312 kvm_inject_page_fault(vcpu, &e);
6313 return 1;
6314 }
6315
6316 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6317 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6318 skip_emulated_instruction(vcpu);
6319 return 1;
6320 }
6321
6322 if (vmx->nested.current_vmptr != vmptr) {
6323 struct vmcs12 *new_vmcs12;
6324 struct page *page;
6325 page = nested_get_page(vcpu, vmptr);
6326 if (page == NULL) {
6327 nested_vmx_failInvalid(vcpu);
6328 skip_emulated_instruction(vcpu);
6329 return 1;
6330 }
6331 new_vmcs12 = kmap(page);
6332 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6333 kunmap(page);
6334 nested_release_page_clean(page);
6335 nested_vmx_failValid(vcpu,
6336 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6337 skip_emulated_instruction(vcpu);
6338 return 1;
6339 }
e7953d7f
AG		 6340 if (vmx->nested.current_vmptr != -1ull)
6341 nested_release_vmcs12(vmx);
63846663
NHE		 6342
6343 vmx->nested.current_vmptr = vmptr;
6344 vmx->nested.current_vmcs12 = new_vmcs12;
6345 vmx->nested.current_vmcs12_page = page;
012f83cb 6346 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6347 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6348 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6349 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6350 vmcs_write64(VMCS_LINK_POINTER,
6351 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6352 vmx->nested.sync_shadow_vmcs = true;
6353 }
63846663
NHE		 6354 }
6355
6356 nested_vmx_succeed(vcpu);
6357 skip_emulated_instruction(vcpu);
6358 return 1;
6359}
6360
6a4d7550
NHE		 6361/* Emulate the VMPTRST instruction */
6362static int handle_vmptrst(struct kvm_vcpu *vcpu)
6363{
6364 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6365 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6366 gva_t vmcs_gva;
6367 struct x86_exception e;
6368
6369 if (!nested_vmx_check_permission(vcpu))
6370 return 1;
6371
6372 if (get_vmx_mem_address(vcpu, exit_qualification,
6373 vmx_instruction_info, &vmcs_gva))
6374 return 1;
6375 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6376 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6377 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6378 sizeof(u64), &e)) {
6379 kvm_inject_page_fault(vcpu, &e);
6380 return 1;
6381 }
6382 nested_vmx_succeed(vcpu);
6383 skip_emulated_instruction(vcpu);
6384 return 1;
6385}
6386
bfd0a56b
NHE		 6387/* Emulate the INVEPT instruction */
6388static int handle_invept(struct kvm_vcpu *vcpu)
6389{
6390 u32 vmx_instruction_info, types;
6391 unsigned long type;
6392 gva_t gva;
6393 struct x86_exception e;
6394 struct {
6395 u64 eptp, gpa;
6396 } operand;
6397 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6398
6399 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6400 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6401 kvm_queue_exception(vcpu, UD_VECTOR);
6402 return 1;
6403 }
6404
6405 if (!nested_vmx_check_permission(vcpu))
6406 return 1;
6407
6408 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6409 kvm_queue_exception(vcpu, UD_VECTOR);
6410 return 1;
6411 }
6412
6413 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6414 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6415
6416 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6417
6418 if (!(types & (1UL << type))) {
6419 nested_vmx_failValid(vcpu,
6420 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6421 return 1;
6422 }
6423
6424 /* According to the Intel VMX instruction reference, the memory
6425 * operand is read even if it isn't needed (e.g., for type==global)
6426 */
6427 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6428 vmx_instruction_info, &gva))
6429 return 1;
6430 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6431 sizeof(operand), &e)) {
6432 kvm_inject_page_fault(vcpu, &e);
6433 return 1;
6434 }
6435
6436 switch (type) {
6437 case VMX_EPT_EXTENT_CONTEXT:
6438 if ((operand.eptp & eptp_mask) !=
6439 (nested_ept_get_cr3(vcpu) & eptp_mask))
6440 break;
6441 case VMX_EPT_EXTENT_GLOBAL:
6442 kvm_mmu_sync_roots(vcpu);
6443 kvm_mmu_flush_tlb(vcpu);
6444 nested_vmx_succeed(vcpu);
6445 break;
6446 default:
6447 BUG_ON(1);
6448 break;
6449 }
6450
6451 skip_emulated_instruction(vcpu);
6452 return 1;
6453}
6454
6aa8b732
AK		 6455/*
6456 * The exit handlers return 1 if the exit was handled fully and guest execution
6457 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6458 * to be done to userspace and return 0.
6459 */
772e0318 6460static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6461 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6462 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6463 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6464 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6465 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6466 [EXIT_REASON_CR_ACCESS] = handle_cr,
6467 [EXIT_REASON_DR_ACCESS] = handle_dr,
6468 [EXIT_REASON_CPUID] = handle_cpuid,
6469 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6470 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6471 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6472 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6473 [EXIT_REASON_INVD] = handle_invd,
a7052897 6474 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6475 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6476 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6477 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6478 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6479 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6480 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6481 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6482 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6483 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6484 [EXIT_REASON_VMOFF] = handle_vmoff,
6485 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6486 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6487 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6488 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6489 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6490 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6491 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6492 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6493 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6494 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6495 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6496 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6497 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6498 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6499 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6500};
6501
6502static const int kvm_vmx_max_exit_handlers =
50a3485c 6503 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6504
908a7bdd
JK		 6505static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6506 struct vmcs12 *vmcs12)
6507{
6508 unsigned long exit_qualification;
6509 gpa_t bitmap, last_bitmap;
6510 unsigned int port;
6511 int size;
6512 u8 b;
6513
908a7bdd 6514 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6515 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6516
6517 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6518
6519 port = exit_qualification >> 16;
6520 size = (exit_qualification & 7) + 1;
6521
6522 last_bitmap = (gpa_t)-1;
6523 b = -1;
6524
6525 while (size > 0) {
6526 if (port < 0x8000)
6527 bitmap = vmcs12->io_bitmap_a;
6528 else if (port < 0x10000)
6529 bitmap = vmcs12->io_bitmap_b;
6530 else
6531 return 1;
6532 bitmap += (port & 0x7fff) / 8;
6533
6534 if (last_bitmap != bitmap)
6535 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6536 return 1;
6537 if (b & (1 << (port & 7)))
6538 return 1;
6539
6540 port++;
6541 size--;
6542 last_bitmap = bitmap;
6543 }
6544
6545 return 0;
6546}
6547
644d711a
NHE		 6548/*
6549 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6550 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6551 * disinterest in the current event (read or write a specific MSR) by using an
6552 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6553 */
6554static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6555 struct vmcs12 *vmcs12, u32 exit_reason)
6556{
6557 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6558 gpa_t bitmap;
6559
cbd29cb6 6560 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6561 return 1;
6562
6563 /*
6564 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6565 * for the four combinations of read/write and low/high MSR numbers.
6566 * First we need to figure out which of the four to use:
6567 */
6568 bitmap = vmcs12->msr_bitmap;
6569 if (exit_reason == EXIT_REASON_MSR_WRITE)
6570 bitmap += 2048;
6571 if (msr_index >= 0xc0000000) {
6572 msr_index -= 0xc0000000;
6573 bitmap += 1024;
6574 }
6575
6576 /* Then read the msr_index'th bit from this bitmap: */
6577 if (msr_index < 1024*8) {
6578 unsigned char b;
bd31a7f5
JK		 6579 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6580 return 1;
644d711a
NHE		 6581 return 1 & (b >> (msr_index & 7));
6582 } else
6583 return 1; /* let L1 handle the wrong parameter */
6584}
6585
6586/*
6587 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6588 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6589 * intercept (via guest_host_mask etc.) the current event.
6590 */
6591static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6592 struct vmcs12 *vmcs12)
6593{
6594 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6595 int cr = exit_qualification & 15;
6596 int reg = (exit_qualification >> 8) & 15;
6597 unsigned long val = kvm_register_read(vcpu, reg);
6598
6599 switch ((exit_qualification >> 4) & 3) {
6600 case 0: /* mov to cr */
6601 switch (cr) {
6602 case 0:
6603 if (vmcs12->cr0_guest_host_mask &
6604 (val ^ vmcs12->cr0_read_shadow))
6605 return 1;
6606 break;
6607 case 3:
6608 if ((vmcs12->cr3_target_count >= 1 &&
6609 vmcs12->cr3_target_value0 == val) ||
6610 (vmcs12->cr3_target_count >= 2 &&
6611 vmcs12->cr3_target_value1 == val) ||
6612 (vmcs12->cr3_target_count >= 3 &&
6613 vmcs12->cr3_target_value2 == val) ||
6614 (vmcs12->cr3_target_count >= 4 &&
6615 vmcs12->cr3_target_value3 == val))
6616 return 0;
6617 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6618 return 1;
6619 break;
6620 case 4:
6621 if (vmcs12->cr4_guest_host_mask &
6622 (vmcs12->cr4_read_shadow ^ val))
6623 return 1;
6624 break;
6625 case 8:
6626 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6627 return 1;
6628 break;
6629 }
6630 break;
6631 case 2: /* clts */
6632 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6633 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6634 return 1;
6635 break;
6636 case 1: /* mov from cr */
6637 switch (cr) {
6638 case 3:
6639 if (vmcs12->cpu_based_vm_exec_control &
6640 CPU_BASED_CR3_STORE_EXITING)
6641 return 1;
6642 break;
6643 case 8:
6644 if (vmcs12->cpu_based_vm_exec_control &
6645 CPU_BASED_CR8_STORE_EXITING)
6646 return 1;
6647 break;
6648 }
6649 break;
6650 case 3: /* lmsw */
6651 /*
6652 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6653 * cr0. Other attempted changes are ignored, with no exit.
6654 */
6655 if (vmcs12->cr0_guest_host_mask & 0xe &
6656 (val ^ vmcs12->cr0_read_shadow))
6657 return 1;
6658 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6659 !(vmcs12->cr0_read_shadow & 0x1) &&
6660 (val & 0x1))
6661 return 1;
6662 break;
6663 }
6664 return 0;
6665}
6666
6667/*
6668 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6669 * should handle it ourselves in L0 (and then continue L2). Only call this
6670 * when in is_guest_mode (L2).
6671 */
6672static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6673{
644d711a
NHE		 6674 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6675 struct vcpu_vmx *vmx = to_vmx(vcpu);
6676 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6677 u32 exit_reason = vmx->exit_reason;
644d711a 6678
542060ea
JK		 6679 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6680 vmcs_readl(EXIT_QUALIFICATION),
6681 vmx->idt_vectoring_info,
6682 intr_info,
6683 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6684 KVM_ISA_VMX);
6685
644d711a
NHE		 6686 if (vmx->nested.nested_run_pending)
6687 return 0;
6688
6689 if (unlikely(vmx->fail)) {
bd80158a
JK		 6690 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6691 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6692 return 1;
6693 }
6694
6695 switch (exit_reason) {
6696 case EXIT_REASON_EXCEPTION_NMI:
6697 if (!is_exception(intr_info))
6698 return 0;
6699 else if (is_page_fault(intr_info))
6700 return enable_ept;
e504c909
AB		 6701 else if (is_no_device(intr_info) &&
6702 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6703 return 0;
644d711a
NHE		 6704 return vmcs12->exception_bitmap &
6705 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6706 case EXIT_REASON_EXTERNAL_INTERRUPT:
6707 return 0;
6708 case EXIT_REASON_TRIPLE_FAULT:
6709 return 1;
6710 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6711 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6712 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6713 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6714 case EXIT_REASON_TASK_SWITCH:
6715 return 1;
6716 case EXIT_REASON_CPUID:
6717 return 1;
6718 case EXIT_REASON_HLT:
6719 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6720 case EXIT_REASON_INVD:
6721 return 1;
6722 case EXIT_REASON_INVLPG:
6723 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6724 case EXIT_REASON_RDPMC:
6725 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6726 case EXIT_REASON_RDTSC:
6727 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6728 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6729 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6730 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6731 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6732 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6733 case EXIT_REASON_INVEPT:
644d711a
NHE		 6734 /*
6735 * VMX instructions trap unconditionally. This allows L1 to
6736 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6737 */
6738 return 1;
6739 case EXIT_REASON_CR_ACCESS:
6740 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6741 case EXIT_REASON_DR_ACCESS:
6742 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6743 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6744 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6745 case EXIT_REASON_MSR_READ:
6746 case EXIT_REASON_MSR_WRITE:
6747 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6748 case EXIT_REASON_INVALID_STATE:
6749 return 1;
6750 case EXIT_REASON_MWAIT_INSTRUCTION:
6751 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6752 case EXIT_REASON_MONITOR_INSTRUCTION:
6753 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6754 case EXIT_REASON_PAUSE_INSTRUCTION:
6755 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6756 nested_cpu_has2(vmcs12,
6757 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6758 case EXIT_REASON_MCE_DURING_VMENTRY:
6759 return 0;
6760 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6761 return 1;
6762 case EXIT_REASON_APIC_ACCESS:
6763 return nested_cpu_has2(vmcs12,
6764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6765 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6766 /*
6767 * L0 always deals with the EPT violation. If nested EPT is
6768 * used, and the nested mmu code discovers that the address is
6769 * missing in the guest EPT table (EPT12), the EPT violation
6770 * will be injected with nested_ept_inject_page_fault()
6771 */
6772 return 0;
644d711a 6773 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6774 /*
6775 * L2 never uses directly L1's EPT, but rather L0's own EPT
6776 * table (shadow on EPT) or a merged EPT table that L0 built
6777 * (EPT on EPT). So any problems with the structure of the
6778 * table is L0's fault.
6779 */
644d711a 6780 return 0;
0238ea91
JK		 6781 case EXIT_REASON_PREEMPTION_TIMER:
6782 return vmcs12->pin_based_vm_exec_control &
6783 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6784 case EXIT_REASON_WBINVD:
6785 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6786 case EXIT_REASON_XSETBV:
6787 return 1;
6788 default:
6789 return 1;
6790 }
6791}
6792
586f9607
AK		 6793static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6794{
6795 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6796 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6797}
6798
7854cbca
ACL		 6799static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6800{
6801 u64 delta_tsc_l1;
6802 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6803
6804 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6805 PIN_BASED_VMX_PREEMPTION_TIMER))
6806 return;
6807 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6808 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6809 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6810 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6811 - vcpu->arch.last_guest_tsc;
6812 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6813 if (preempt_val_l2 <= preempt_val_l1)
6814 preempt_val_l2 = 0;
6815 else
6816 preempt_val_l2 -= preempt_val_l1;
6817 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6818}
6819
6aa8b732
AK		 6820/*
6821 * The guest has exited. See if we can fix it or if we need userspace
6822 * assistance.
6823 */
851ba692 6824static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6825{
29bd8a78 6826 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6827 u32 exit_reason = vmx->exit_reason;
1155f76a 6828 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6829
80ced186 6830 /* If guest state is invalid, start emulating */
14168786 6831 if (vmx->emulation_required)
80ced186 6832 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6833
644d711a 6834 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6835 nested_vmx_vmexit(vcpu, exit_reason,
6836 vmcs_read32(VM_EXIT_INTR_INFO),
6837 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6838 return 1;
6839 }
6840
5120702e
MG		 6841 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6842 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6843 vcpu->run->fail_entry.hardware_entry_failure_reason
6844 = exit_reason;
6845 return 0;
6846 }
6847
29bd8a78 6848 if (unlikely(vmx->fail)) {
851ba692
AK		 6849 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6850 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6851 = vmcs_read32(VM_INSTRUCTION_ERROR);
6852 return 0;
6853 }
6aa8b732 6854
b9bf6882
XG		 6855 /*
6856 * Note:
6857 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6858 * delivery event since it indicates guest is accessing MMIO.
6859 * The vm-exit can be triggered again after return to guest that
6860 * will cause infinite loop.
6861 */
d77c26fc 6862 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6863 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6864 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6865 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6866 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6867 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6868 vcpu->run->internal.ndata = 2;
6869 vcpu->run->internal.data[0] = vectoring_info;
6870 vcpu->run->internal.data[1] = exit_reason;
6871 return 0;
6872 }
3b86cd99 6873
644d711a
NHE		 6874 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6875 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6876 get_vmcs12(vcpu))))) {
c4282df9 6877 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6878 vmx->soft_vnmi_blocked = 0;
3b86cd99 6879 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6880 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6881 /*
6882 * This CPU don't support us in finding the end of an
6883 * NMI-blocked window if the guest runs with IRQs
6884 * disabled. So we pull the trigger after 1 s of
6885 * futile waiting, but inform the user about this.
6886 */
6887 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6888 "state on VCPU %d after 1 s timeout\n",
6889 __func__, vcpu->vcpu_id);
6890 vmx->soft_vnmi_blocked = 0;
3b86cd99 6891 }
3b86cd99
JK		 6892 }
6893
6aa8b732
AK		 6894 if (exit_reason < kvm_vmx_max_exit_handlers
6895 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6896 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6897 else {
851ba692
AK		 6898 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6899 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6900 }
6901 return 0;
6902}
6903
95ba8273 6904static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6905{
95ba8273 6906 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6907 vmcs_write32(TPR_THRESHOLD, 0);
6908 return;
6909 }
6910
95ba8273 6911 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6912}
6913
8d14695f
YZ		 6914static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6915{
6916 u32 sec_exec_control;
6917
6918 /*
6919 * There is not point to enable virtualize x2apic without enable
6920 * apicv
6921 */
c7c9c56c
YZ		 6922 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6923 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6924 return;
6925
6926 if (!vm_need_tpr_shadow(vcpu->kvm))
6927 return;
6928
6929 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6930
6931 if (set) {
6932 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6933 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6934 } else {
6935 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6936 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6937 }
6938 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6939
6940 vmx_set_msr_bitmap(vcpu);
6941}
6942
c7c9c56c
YZ		 6943static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6944{
6945 u16 status;
6946 u8 old;
6947
6948 if (!vmx_vm_has_apicv(kvm))
6949 return;
6950
6951 if (isr == -1)
6952 isr = 0;
6953
6954 status = vmcs_read16(GUEST_INTR_STATUS);
6955 old = status >> 8;
6956 if (isr != old) {
6957 status &= 0xff;
6958 status |= isr << 8;
6959 vmcs_write16(GUEST_INTR_STATUS, status);
6960 }
6961}
6962
6963static void vmx_set_rvi(int vector)
6964{
6965 u16 status;
6966 u8 old;
6967
6968 status = vmcs_read16(GUEST_INTR_STATUS);
6969 old = (u8)status & 0xff;
6970 if ((u8)vector != old) {
6971 status &= ~0xff;
6972 status |= (u8)vector;
6973 vmcs_write16(GUEST_INTR_STATUS, status);
6974 }
6975}
6976
6977static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6978{
6979 if (max_irr == -1)
6980 return;
6981
6982 vmx_set_rvi(max_irr);
6983}
6984
6985static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6986{
3d81bc7e
YZ		 6987 if (!vmx_vm_has_apicv(vcpu->kvm))
6988 return;
6989
c7c9c56c
YZ		 6990 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6991 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6992 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6993 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6994}
6995
51aa01d1 6996static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6997{
00eba012
AK		 6998 u32 exit_intr_info;
6999
7000 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7001 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7002 return;
7003
c5ca8e57 7004 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7005 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7006
7007 /* Handle machine checks before interrupts are enabled */
00eba012 7008 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7009 kvm_machine_check();
7010
20f65983 7011 /* We need to handle NMIs before interrupts are enabled */
00eba012 7012 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7013 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7014 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7015 asm("int $2");
ff9d07a0
ZY		 7016 kvm_after_handle_nmi(&vmx->vcpu);
7017 }
51aa01d1 7018}
20f65983 7019
a547c6db
YZ		 7020static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7021{
7022 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7023
7024 /*
7025 * If external interrupt exists, IF bit is set in rflags/eflags on the
7026 * interrupt stack frame, and interrupt will be enabled on a return
7027 * from interrupt handler.
7028 */
7029 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7030 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7031 unsigned int vector;
7032 unsigned long entry;
7033 gate_desc *desc;
7034 struct vcpu_vmx *vmx = to_vmx(vcpu);
7035#ifdef CONFIG_X86_64
7036 unsigned long tmp;
7037#endif
7038
7039 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7040 desc = (gate_desc *)vmx->host_idt_base + vector;
7041 entry = gate_offset(*desc);
7042 asm volatile(
7043#ifdef CONFIG_X86_64
7044 "mov %%" _ASM_SP ", %[sp]\n\t"
7045 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7046 "push $%c[ss]\n\t"
7047 "push %[sp]\n\t"
7048#endif
7049 "pushf\n\t"
7050 "orl $0x200, (%%" _ASM_SP ")\n\t"
7051 __ASM_SIZE(push) " $%c[cs]\n\t"
7052 "call *%[entry]\n\t"
7053 :
7054#ifdef CONFIG_X86_64
7055 [sp]"=&r"(tmp)
7056#endif
7057 :
7058 [entry]"r"(entry),
7059 [ss]"i"(__KERNEL_DS),
7060 [cs]"i"(__KERNEL_CS)
7061 );
7062 } else
7063 local_irq_enable();
7064}
7065
da8999d3
LJ		 7066static bool vmx_mpx_supported(void)
7067{
7068 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7069 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7070}
7071
51aa01d1
AK		 7072static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7073{
c5ca8e57 7074 u32 exit_intr_info;
51aa01d1
AK		 7075 bool unblock_nmi;
7076 u8 vector;
7077 bool idtv_info_valid;
7078
7079 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7080
cf393f75 7081 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7082 if (vmx->nmi_known_unmasked)
7083 return;
c5ca8e57
AK		 7084 /*
7085 * Can't use vmx->exit_intr_info since we're not sure what
7086 * the exit reason is.
7087 */
7088 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7089 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7090 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7091 /*
7b4a25cb 7092 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7093 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7094 * a guest IRET fault.
7b4a25cb
GN		 7095 * SDM 3: 23.2.2 (September 2008)
7096 * Bit 12 is undefined in any of the following cases:
7097 * If the VM exit sets the valid bit in the IDT-vectoring
7098 * information field.
7099 * If the VM exit is due to a double fault.
cf393f75 7100 */
7b4a25cb
GN		 7101 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7102 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7103 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7104 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7105 else
7106 vmx->nmi_known_unmasked =
7107 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7108 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7109 } else if (unlikely(vmx->soft_vnmi_blocked))
7110 vmx->vnmi_blocked_time +=
7111 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7112}
7113
3ab66e8a 7114static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7115 u32 idt_vectoring_info,
7116 int instr_len_field,
7117 int error_code_field)
51aa01d1 7118{
51aa01d1
AK		 7119 u8 vector;
7120 int type;
7121 bool idtv_info_valid;
7122
7123 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7124
3ab66e8a
JK		 7125 vcpu->arch.nmi_injected = false;
7126 kvm_clear_exception_queue(vcpu);
7127 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7128
7129 if (!idtv_info_valid)
7130 return;
7131
3ab66e8a 7132 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7133
668f612f
AK		 7134 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7135 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7136
64a7ec06 7137 switch (type) {
37b96e98 7138 case INTR_TYPE_NMI_INTR:
3ab66e8a 7139 vcpu->arch.nmi_injected = true;
668f612f 7140 /*
7b4a25cb 7141 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7142 * Clear bit "block by NMI" before VM entry if a NMI
7143 * delivery faulted.
668f612f 7144 */
3ab66e8a 7145 vmx_set_nmi_mask(vcpu, false);
37b96e98 7146 break;
37b96e98 7147 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7148 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7149 /* fall through */
7150 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7151 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7152 u32 err = vmcs_read32(error_code_field);
851eb667 7153 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7154 } else
851eb667 7155 kvm_requeue_exception(vcpu, vector);
37b96e98 7156 break;
66fd3f7f 7157 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7158 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7159 /* fall through */
37b96e98 7160 case INTR_TYPE_EXT_INTR:
3ab66e8a 7161 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7162 break;
7163 default:
7164 break;
f7d9238f 7165 }
cf393f75
AK		 7166}
7167
83422e17
AK		 7168static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7169{
3ab66e8a 7170 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7171 VM_EXIT_INSTRUCTION_LEN,
7172 IDT_VECTORING_ERROR_CODE);
7173}
7174
b463a6f7
AK		 7175static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7176{
3ab66e8a 7177 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7178 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7179 VM_ENTRY_INSTRUCTION_LEN,
7180 VM_ENTRY_EXCEPTION_ERROR_CODE);
7181
7182 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7183}
7184
d7cd9796
GN		 7185static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7186{
7187 int i, nr_msrs;
7188 struct perf_guest_switch_msr *msrs;
7189
7190 msrs = perf_guest_get_msrs(&nr_msrs);
7191
7192 if (!msrs)
7193 return;
7194
7195 for (i = 0; i < nr_msrs; i++)
7196 if (msrs[i].host == msrs[i].guest)
7197 clear_atomic_switch_msr(vmx, msrs[i].msr);
7198 else
7199 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7200 msrs[i].host);
7201}
7202
a3b5ba49 7203static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7204{
a2fa3e9f 7205 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7206 unsigned long debugctlmsr;
104f226b
AK		 7207
7208 /* Record the guest's net vcpu time for enforced NMI injections. */
7209 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7210 vmx->entry_time = ktime_get();
7211
7212 /* Don't enter VMX if guest state is invalid, let the exit handler
7213 start emulation until we arrive back to a valid state */
14168786 7214 if (vmx->emulation_required)
104f226b
AK		 7215 return;
7216
012f83cb
AG		 7217 if (vmx->nested.sync_shadow_vmcs) {
7218 copy_vmcs12_to_shadow(vmx);
7219 vmx->nested.sync_shadow_vmcs = false;
7220 }
7221
104f226b
AK		 7222 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7223 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7224 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7225 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7226
7227 /* When single-stepping over STI and MOV SS, we must clear the
7228 * corresponding interruptibility bits in the guest state. Otherwise
7229 * vmentry fails as it then expects bit 14 (BS) in pending debug
7230 * exceptions being set, but that's not correct for the guest debugging
7231 * case. */
7232 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7233 vmx_set_interrupt_shadow(vcpu, 0);
7234
d7cd9796 7235 atomic_switch_perf_msrs(vmx);
2a7921b7 7236 debugctlmsr = get_debugctlmsr();
d7cd9796 7237
7854cbca
ACL		 7238 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7239 nested_adjust_preemption_timer(vcpu);
d462b819 7240 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7241 asm(
6aa8b732 7242 /* Store host registers */
b188c81f
AK		 7243 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7244 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7245 "push %%" _ASM_CX " \n\t"
7246 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7247 "je 1f \n\t"
b188c81f 7248 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7249 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7250 "1: \n\t"
d3edefc0 7251 /* Reload cr2 if changed */
b188c81f
AK		 7252 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7253 "mov %%cr2, %%" _ASM_DX " \n\t"
7254 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7255 "je 2f \n\t"
b188c81f 7256 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7257 "2: \n\t"
6aa8b732 7258 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7259 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7260 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7261 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7262 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7263 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7264 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7265 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7266 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7267#ifdef CONFIG_X86_64
e08aa78a
AK		 7268 "mov %c[r8](%0), %%r8 \n\t"
7269 "mov %c[r9](%0), %%r9 \n\t"
7270 "mov %c[r10](%0), %%r10 \n\t"
7271 "mov %c[r11](%0), %%r11 \n\t"
7272 "mov %c[r12](%0), %%r12 \n\t"
7273 "mov %c[r13](%0), %%r13 \n\t"
7274 "mov %c[r14](%0), %%r14 \n\t"
7275 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7276#endif
b188c81f 7277 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7278
6aa8b732 7279 /* Enter guest mode */
83287ea4 7280 "jne 1f \n\t"
4ecac3fd 7281 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7282 "jmp 2f \n\t"
7283 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7284 "2: "
6aa8b732 7285 /* Save guest registers, load host registers, keep flags */
b188c81f 7286 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7287 "pop %0 \n\t"
b188c81f
AK		 7288 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7289 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7290 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7291 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7292 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7293 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7294 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7295#ifdef CONFIG_X86_64
e08aa78a
AK		 7296 "mov %%r8, %c[r8](%0) \n\t"
7297 "mov %%r9, %c[r9](%0) \n\t"
7298 "mov %%r10, %c[r10](%0) \n\t"
7299 "mov %%r11, %c[r11](%0) \n\t"
7300 "mov %%r12, %c[r12](%0) \n\t"
7301 "mov %%r13, %c[r13](%0) \n\t"
7302 "mov %%r14, %c[r14](%0) \n\t"
7303 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7304#endif
b188c81f
AK		 7305 "mov %%cr2, %%" _ASM_AX " \n\t"
7306 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7307
b188c81f 7308 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7309 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7310 ".pushsection .rodata \n\t"
7311 ".global vmx_return \n\t"
7312 "vmx_return: " _ASM_PTR " 2b \n\t"
7313 ".popsection"
e08aa78a 7314 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7315 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7316 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7317 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7318 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7319 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7320 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7321 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7322 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7323 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7324 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7325#ifdef CONFIG_X86_64
ad312c7c
ZX		 7326 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7327 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7328 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7329 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7330 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7331 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7332 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7333 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7334#endif
40712fae
AK		 7335 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7336 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7337 : "cc", "memory"
7338#ifdef CONFIG_X86_64
b188c81f 7339 , "rax", "rbx", "rdi", "rsi"
c2036300 7340 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7341#else
7342 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7343#endif
7344 );
6aa8b732 7345
2a7921b7
GN		 7346 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7347 if (debugctlmsr)
7348 update_debugctlmsr(debugctlmsr);
7349
aa67f609
AK		 7350#ifndef CONFIG_X86_64
7351 /*
7352 * The sysexit path does not restore ds/es, so we must set them to
7353 * a reasonable value ourselves.
7354 *
7355 * We can't defer this to vmx_load_host_state() since that function
7356 * may be executed in interrupt context, which saves and restore segments
7357 * around it, nullifying its effect.
7358 */
7359 loadsegment(ds, __USER_DS);
7360 loadsegment(es, __USER_DS);
7361#endif
7362
6de4f3ad 7363 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7364 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7365 | (1 << VCPU_EXREG_CPL)
aff48baa 7366 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7367 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7368 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7369 vcpu->arch.regs_dirty = 0;
7370
1155f76a
AK		 7371 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7372
d462b819 7373 vmx->loaded_vmcs->launched = 1;
1b6269db 7374
51aa01d1 7375 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7376 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7377
e0b890d3
GN		 7378 /*
7379 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7380 * we did not inject a still-pending event to L1 now because of
7381 * nested_run_pending, we need to re-enable this bit.
7382 */
7383 if (vmx->nested.nested_run_pending)
7384 kvm_make_request(KVM_REQ_EVENT, vcpu);
7385
7386 vmx->nested.nested_run_pending = 0;
7387
51aa01d1
AK		 7388 vmx_complete_atomic_exit(vmx);
7389 vmx_recover_nmi_blocking(vmx);
cf393f75 7390 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7391}
7392
6aa8b732
AK		 7393static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7394{
fb3f0f51
RR		 7395 struct vcpu_vmx *vmx = to_vmx(vcpu);
7396
cdbecfc3 7397 free_vpid(vmx);
d462b819 7398 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7399 free_nested(vmx);
fb3f0f51
RR		 7400 kfree(vmx->guest_msrs);
7401 kvm_vcpu_uninit(vcpu);
a4770347 7402 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7403}
7404
fb3f0f51 7405static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7406{
fb3f0f51 7407 int err;
c16f862d 7408 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7409 int cpu;
6aa8b732 7410
a2fa3e9f 7411 if (!vmx)
fb3f0f51
RR		 7412 return ERR_PTR(-ENOMEM);
7413
2384d2b3
SY		 7414 allocate_vpid(vmx);
7415
fb3f0f51
RR		 7416 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7417 if (err)
7418 goto free_vcpu;
965b58a5 7419
a2fa3e9f 7420 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7421 err = -ENOMEM;
fb3f0f51 7422 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7423 goto uninit_vcpu;
7424 }
965b58a5 7425
d462b819
NHE		 7426 vmx->loaded_vmcs = &vmx->vmcs01;
7427 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7428 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7429 goto free_msrs;
d462b819
NHE		 7430 if (!vmm_exclusive)
7431 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7432 loaded_vmcs_init(vmx->loaded_vmcs);
7433 if (!vmm_exclusive)
7434 kvm_cpu_vmxoff();
a2fa3e9f 7435
15ad7146
AK		 7436 cpu = get_cpu();
7437 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7438 vmx->vcpu.cpu = cpu;
8b9cf98c 7439 err = vmx_vcpu_setup(vmx);
fb3f0f51 7440 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7441 put_cpu();
fb3f0f51
RR		 7442 if (err)
7443 goto free_vmcs;
a63cb560 7444 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7445 err = alloc_apic_access_page(kvm);
7446 if (err)
5e4a0b3c 7447 goto free_vmcs;
a63cb560 7448 }
fb3f0f51 7449
b927a3ce
SY		 7450 if (enable_ept) {
7451 if (!kvm->arch.ept_identity_map_addr)
7452 kvm->arch.ept_identity_map_addr =
7453 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7454 err = -ENOMEM;
b7ebfb05
SY		 7455 if (alloc_identity_pagetable(kvm) != 0)
7456 goto free_vmcs;
93ea5388
GN		 7457 if (!init_rmode_identity_map(kvm))
7458 goto free_vmcs;
b927a3ce 7459 }
b7ebfb05 7460
a9d30f33
NHE		 7461 vmx->nested.current_vmptr = -1ull;
7462 vmx->nested.current_vmcs12 = NULL;
7463
fb3f0f51
RR		 7464 return &vmx->vcpu;
7465
7466free_vmcs:
5f3fbc34 7467 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7468free_msrs:
fb3f0f51
RR		 7469 kfree(vmx->guest_msrs);
7470uninit_vcpu:
7471 kvm_vcpu_uninit(&vmx->vcpu);
7472free_vcpu:
cdbecfc3 7473 free_vpid(vmx);
a4770347 7474 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7475 return ERR_PTR(err);
6aa8b732
AK		 7476}
7477
002c7f7c
YS		 7478static void __init vmx_check_processor_compat(void *rtn)
7479{
7480 struct vmcs_config vmcs_conf;
7481
7482 *(int *)rtn = 0;
7483 if (setup_vmcs_config(&vmcs_conf) < 0)
7484 *(int *)rtn = -EIO;
7485 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7486 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7487 smp_processor_id());
7488 *(int *)rtn = -EIO;
7489 }
7490}
7491
67253af5
SY		 7492static int get_ept_level(void)
7493{
7494 return VMX_EPT_DEFAULT_GAW + 1;
7495}
7496
4b12f0de 7497static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7498{
4b12f0de
SY		 7499 u64 ret;
7500
522c68c4
SY		 7501 /* For VT-d and EPT combination
7502 * 1. MMIO: always map as UC
7503 * 2. EPT with VT-d:
7504 * a. VT-d without snooping control feature: can't guarantee the
7505 * result, try to trust guest.
7506 * b. VT-d with snooping control feature: snooping control feature of
7507 * VT-d engine can guarantee the cache correctness. Just set it
7508 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7509 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7510 * consistent with host MTRR
7511 */
4b12f0de
SY		 7512 if (is_mmio)
7513 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7514 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7515 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7516 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7517 else
522c68c4 7518 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7519 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7520
7521 return ret;
64d4d521
SY		 7522}
7523
17cc3935 7524static int vmx_get_lpage_level(void)
344f414f 7525{
878403b7
SY		 7526 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7527 return PT_DIRECTORY_LEVEL;
7528 else
7529 /* For shadow and EPT supported 1GB page */
7530 return PT_PDPE_LEVEL;
344f414f
JR		 7531}
7532
0e851880
SY		 7533static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7534{
4e47c7a6
SY		 7535 struct kvm_cpuid_entry2 *best;
7536 struct vcpu_vmx *vmx = to_vmx(vcpu);
7537 u32 exec_control;
7538
7539 vmx->rdtscp_enabled = false;
7540 if (vmx_rdtscp_supported()) {
7541 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7542 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7543 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7544 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7545 vmx->rdtscp_enabled = true;
7546 else {
7547 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7548 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7549 exec_control);
7550 }
7551 }
7552 }
ad756a16 7553
ad756a16
MJ		 7554 /* Exposing INVPCID only when PCID is exposed */
7555 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7556 if (vmx_invpcid_supported() &&
4f977045 7557 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7558 guest_cpuid_has_pcid(vcpu)) {
29282fde 7559 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7560 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7561 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7562 exec_control);
7563 } else {
29282fde
TI		 7564 if (cpu_has_secondary_exec_ctrls()) {
7565 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7566 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7568 exec_control);
7569 }
ad756a16 7570 if (best)
4f977045 7571 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7572 }
0e851880
SY		 7573}
7574
d4330ef2
JR		 7575static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7576{
7b8050f5
NHE		 7577 if (func == 1 && nested)
7578 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7579}
7580
25d92081
YZ		 7581static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7582 struct x86_exception *fault)
7583{
533558bc
JK		 7584 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7585 u32 exit_reason;
25d92081
YZ		 7586
7587 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7588 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7589 else
533558bc
JK		 7590 exit_reason = EXIT_REASON_EPT_VIOLATION;
7591 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7592 vmcs12->guest_physical_address = fault->address;
7593}
7594
155a97a3
NHE		 7595/* Callbacks for nested_ept_init_mmu_context: */
7596
7597static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7598{
7599 /* return the page table to be shadowed - in our case, EPT12 */
7600 return get_vmcs12(vcpu)->ept_pointer;
7601}
7602
8a3c1a33 7603static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7604{
8a3c1a33 7605 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7606 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7607
7608 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7609 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7610 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7611
7612 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7613}
7614
7615static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7616{
7617 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7618}
7619
feaf0c7d
GN		 7620static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7621 struct x86_exception *fault)
7622{
7623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7624
7625 WARN_ON(!is_guest_mode(vcpu));
7626
7627 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7628 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7629 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7630 vmcs_read32(VM_EXIT_INTR_INFO),
7631 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7632 else
7633 kvm_inject_page_fault(vcpu, fault);
7634}
7635
fe3ef05c
NHE		 7636/*
7637 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7638 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7639 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7640 * guest in a way that will both be appropriate to L1's requests, and our
7641 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7642 * function also has additional necessary side-effects, like setting various
7643 * vcpu->arch fields.
7644 */
7645static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7646{
7647 struct vcpu_vmx *vmx = to_vmx(vcpu);
7648 u32 exec_control;
7854cbca 7649 u32 exit_control;
fe3ef05c
NHE		 7650
7651 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7652 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7653 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7654 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7655 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7656 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7657 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7658 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7659 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7660 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7661 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7662 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7663 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7664 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7665 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7666 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7667 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7668 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7669 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7670 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7671 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7672 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7673 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7674 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7675 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7676 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7677 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7678 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7679 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7680 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7681 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7682 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7683 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7684 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7685 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7686 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7687
7688 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7690 vmcs12->vm_entry_intr_info_field);
7691 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7692 vmcs12->vm_entry_exception_error_code);
7693 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7694 vmcs12->vm_entry_instruction_len);
7695 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7696 vmcs12->guest_interruptibility_info);
fe3ef05c 7697 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7698 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7699 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7700 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7701 vmcs12->guest_pending_dbg_exceptions);
7702 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7703 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7704
7705 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7706
7707 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7708 (vmcs_config.pin_based_exec_ctrl |
7709 vmcs12->pin_based_vm_exec_control));
7710
0238ea91
JK		 7711 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7712 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7713 vmcs12->vmx_preemption_timer_value);
7714
fe3ef05c
NHE		 7715 /*
7716 * Whether page-faults are trapped is determined by a combination of
7717 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7718 * If enable_ept, L0 doesn't care about page faults and we should
7719 * set all of these to L1's desires. However, if !enable_ept, L0 does
7720 * care about (at least some) page faults, and because it is not easy
7721 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7722 * to exit on each and every L2 page fault. This is done by setting
7723 * MASK=MATCH=0 and (see below) EB.PF=1.
7724 * Note that below we don't need special code to set EB.PF beyond the
7725 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7726 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7727 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7728 *
7729 * A problem with this approach (when !enable_ept) is that L1 may be
7730 * injected with more page faults than it asked for. This could have
7731 * caused problems, but in practice existing hypervisors don't care.
7732 * To fix this, we will need to emulate the PFEC checking (on the L1
7733 * page tables), using walk_addr(), when injecting PFs to L1.
7734 */
7735 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7736 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7737 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7738 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7739
7740 if (cpu_has_secondary_exec_ctrls()) {
7741 u32 exec_control = vmx_secondary_exec_control(vmx);
7742 if (!vmx->rdtscp_enabled)
7743 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7744 /* Take the following fields only from vmcs12 */
7745 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7746 if (nested_cpu_has(vmcs12,
7747 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7748 exec_control |= vmcs12->secondary_vm_exec_control;
7749
7750 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7751 /*
7752 * Translate L1 physical address to host physical
7753 * address for vmcs02. Keep the page pinned, so this
7754 * physical address remains valid. We keep a reference
7755 * to it so we can release it later.
7756 */
7757 if (vmx->nested.apic_access_page) /* shouldn't happen */
7758 nested_release_page(vmx->nested.apic_access_page);
7759 vmx->nested.apic_access_page =
7760 nested_get_page(vcpu, vmcs12->apic_access_addr);
7761 /*
7762 * If translation failed, no matter: This feature asks
7763 * to exit when accessing the given address, and if it
7764 * can never be accessed, this feature won't do
7765 * anything anyway.
7766 */
7767 if (!vmx->nested.apic_access_page)
7768 exec_control &=
7769 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7770 else
7771 vmcs_write64(APIC_ACCESS_ADDR,
7772 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7773 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7774 exec_control |=
7775 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7776 vmcs_write64(APIC_ACCESS_ADDR,
7777 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7778 }
7779
7780 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7781 }
7782
7783
7784 /*
7785 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7786 * Some constant fields are set here by vmx_set_constant_host_state().
7787 * Other fields are different per CPU, and will be set later when
7788 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7789 */
a547c6db 7790 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7791
7792 /*
7793 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7794 * entry, but only if the current (host) sp changed from the value
7795 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7796 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7797 * here we just force the write to happen on entry.
7798 */
7799 vmx->host_rsp = 0;
7800
7801 exec_control = vmx_exec_control(vmx); /* L0's desires */
7802 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7803 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7804 exec_control &= ~CPU_BASED_TPR_SHADOW;
7805 exec_control |= vmcs12->cpu_based_vm_exec_control;
7806 /*
7807 * Merging of IO and MSR bitmaps not currently supported.
7808 * Rather, exit every time.
7809 */
7810 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7811 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7812 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7813
7814 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7815
7816 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7817 * bitwise-or of what L1 wants to trap for L2, and what we want to
7818 * trap. Note that CR0.TS also needs updating - we do this later.
7819 */
7820 update_exception_bitmap(vcpu);
7821 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7822 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7823
8049d651
NHE		 7824 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7825 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7826 * bits are further modified by vmx_set_efer() below.
7827 */
7854cbca
ACL		 7828 exit_control = vmcs_config.vmexit_ctrl;
7829 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7830 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7831 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7832
7833 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7834 * emulated by vmx_set_efer(), below.
7835 */
2961e876 7836 vm_entry_controls_init(vmx,
8049d651
NHE		 7837 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7838 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7839 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7840
44811c02 7841 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7842 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7843 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7844 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7845 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7846
7847
7848 set_cr4_guest_host_mask(vmx);
7849
27fc51b2
NHE		 7850 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7851 vmcs_write64(TSC_OFFSET,
7852 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7853 else
7854 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7855
7856 if (enable_vpid) {
7857 /*
7858 * Trivially support vpid by letting L2s share their parent
7859 * L1's vpid. TODO: move to a more elaborate solution, giving
7860 * each L2 its own vpid and exposing the vpid feature to L1.
7861 */
7862 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7863 vmx_flush_tlb(vcpu);
7864 }
7865
155a97a3
NHE		 7866 if (nested_cpu_has_ept(vmcs12)) {
7867 kvm_mmu_unload(vcpu);
7868 nested_ept_init_mmu_context(vcpu);
7869 }
7870
fe3ef05c
NHE		 7871 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7872 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7873 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7874 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7875 else
7876 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7877 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7878 vmx_set_efer(vcpu, vcpu->arch.efer);
7879
7880 /*
7881 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7882 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7883 * The CR0_READ_SHADOW is what L2 should have expected to read given
7884 * the specifications by L1; It's not enough to take
7885 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7886 * have more bits than L1 expected.
7887 */
7888 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7889 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7890
7891 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7892 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7893
7894 /* shadow page tables on either EPT or shadow page tables */
7895 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7896 kvm_mmu_reset_context(vcpu);
7897
feaf0c7d
GN		 7898 if (!enable_ept)
7899 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7900
3633cfc3
NHE		 7901 /*
7902 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7903 */
7904 if (enable_ept) {
7905 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7906 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7907 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7908 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7909 }
7910
fe3ef05c
NHE		 7911 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7912 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7913}
7914
cd232ad0
NHE		 7915/*
7916 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7917 * for running an L2 nested guest.
7918 */
7919static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7920{
7921 struct vmcs12 *vmcs12;
7922 struct vcpu_vmx *vmx = to_vmx(vcpu);
7923 int cpu;
7924 struct loaded_vmcs *vmcs02;
384bb783 7925 bool ia32e;
cd232ad0
NHE		 7926
7927 if (!nested_vmx_check_permission(vcpu) ||
7928 !nested_vmx_check_vmcs12(vcpu))
7929 return 1;
7930
7931 skip_emulated_instruction(vcpu);
7932 vmcs12 = get_vmcs12(vcpu);
7933
012f83cb
AG		 7934 if (enable_shadow_vmcs)
7935 copy_shadow_to_vmcs12(vmx);
7936
7c177938
NHE		 7937 /*
7938 * The nested entry process starts with enforcing various prerequisites
7939 * on vmcs12 as required by the Intel SDM, and act appropriately when
7940 * they fail: As the SDM explains, some conditions should cause the
7941 * instruction to fail, while others will cause the instruction to seem
7942 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7943 * To speed up the normal (success) code path, we should avoid checking
7944 * for misconfigurations which will anyway be caught by the processor
7945 * when using the merged vmcs02.
7946 */
7947 if (vmcs12->launch_state == launch) {
7948 nested_vmx_failValid(vcpu,
7949 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7950 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7951 return 1;
7952 }
7953
6dfacadd
JK		 7954 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7955 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7956 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7957 return 1;
7958 }
7959
7c177938
NHE		 7960 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7961 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7962 /*TODO: Also verify bits beyond physical address width are 0*/
7963 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7964 return 1;
7965 }
7966
7967 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7968 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7969 /*TODO: Also verify bits beyond physical address width are 0*/
7970 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7971 return 1;
7972 }
7973
7974 if (vmcs12->vm_entry_msr_load_count > 0 ||
7975 vmcs12->vm_exit_msr_load_count > 0 ||
7976 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7977 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7978 __func__);
7c177938
NHE		 7979 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7980 return 1;
7981 }
7982
7983 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7984 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7985 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7986 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7987 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7988 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7989 !vmx_control_verify(vmcs12->vm_exit_controls,
7990 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7991 !vmx_control_verify(vmcs12->vm_entry_controls,
7992 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7993 {
7994 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7995 return 1;
7996 }
7997
7998 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7999 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8000 nested_vmx_failValid(vcpu,
8001 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8002 return 1;
8003 }
8004
92fbc7b1 8005 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8006 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8007 nested_vmx_entry_failure(vcpu, vmcs12,
8008 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8009 return 1;
8010 }
8011 if (vmcs12->vmcs_link_pointer != -1ull) {
8012 nested_vmx_entry_failure(vcpu, vmcs12,
8013 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8014 return 1;
8015 }
8016
384bb783 8017 /*
cb0c8cda 8018 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8019 * are performed on the field for the IA32_EFER MSR:
8020 * - Bits reserved in the IA32_EFER MSR must be 0.
8021 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8022 * the IA-32e mode guest VM-exit control. It must also be identical
8023 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8024 * CR0.PG) is 1.
8025 */
8026 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8027 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8028 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8029 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8030 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8031 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8032 nested_vmx_entry_failure(vcpu, vmcs12,
8033 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8034 return 1;
8035 }
8036 }
8037
8038 /*
8039 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8040 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8041 * the values of the LMA and LME bits in the field must each be that of
8042 * the host address-space size VM-exit control.
8043 */
8044 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8045 ia32e = (vmcs12->vm_exit_controls &
8046 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8047 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8048 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8049 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8050 nested_vmx_entry_failure(vcpu, vmcs12,
8051 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8052 return 1;
8053 }
8054 }
8055
7c177938
NHE		 8056 /*
8057 * We're finally done with prerequisite checking, and can start with
8058 * the nested entry.
8059 */
8060
cd232ad0
NHE		 8061 vmcs02 = nested_get_current_vmcs02(vmx);
8062 if (!vmcs02)
8063 return -ENOMEM;
8064
8065 enter_guest_mode(vcpu);
8066
8067 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8068
8069 cpu = get_cpu();
8070 vmx->loaded_vmcs = vmcs02;
8071 vmx_vcpu_put(vcpu);
8072 vmx_vcpu_load(vcpu, cpu);
8073 vcpu->cpu = cpu;
8074 put_cpu();
8075
36c3cc42
JK		 8076 vmx_segment_cache_clear(vmx);
8077
cd232ad0
NHE		 8078 vmcs12->launch_state = 1;
8079
8080 prepare_vmcs02(vcpu, vmcs12);
8081
6dfacadd
JK		 8082 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8083 return kvm_emulate_halt(vcpu);
8084
7af40ad3
JK		 8085 vmx->nested.nested_run_pending = 1;
8086
cd232ad0
NHE		 8087 /*
8088 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8089 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8090 * returned as far as L1 is concerned. It will only return (and set
8091 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8092 */
8093 return 1;
8094}
8095
4704d0be
NHE		 8096/*
8097 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8098 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8099 * This function returns the new value we should put in vmcs12.guest_cr0.
8100 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8101 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8102 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8103 * didn't trap the bit, because if L1 did, so would L0).
8104 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8105 * been modified by L2, and L1 knows it. So just leave the old value of
8106 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8107 * isn't relevant, because if L0 traps this bit it can set it to anything.
8108 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8109 * changed these bits, and therefore they need to be updated, but L0
8110 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8111 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8112 */
8113static inline unsigned long
8114vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8115{
8116 return
8117 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8118 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8119 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8120 vcpu->arch.cr0_guest_owned_bits));
8121}
8122
8123static inline unsigned long
8124vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8125{
8126 return
8127 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8128 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8129 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8130 vcpu->arch.cr4_guest_owned_bits));
8131}
8132
5f3d5799
JK		 8133static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8134 struct vmcs12 *vmcs12)
8135{
8136 u32 idt_vectoring;
8137 unsigned int nr;
8138
851eb667 8139 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8140 nr = vcpu->arch.exception.nr;
8141 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8142
8143 if (kvm_exception_is_soft(nr)) {
8144 vmcs12->vm_exit_instruction_len =
8145 vcpu->arch.event_exit_inst_len;
8146 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8147 } else
8148 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8149
8150 if (vcpu->arch.exception.has_error_code) {
8151 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8152 vmcs12->idt_vectoring_error_code =
8153 vcpu->arch.exception.error_code;
8154 }
8155
8156 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8157 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8158 vmcs12->idt_vectoring_info_field =
8159 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8160 } else if (vcpu->arch.interrupt.pending) {
8161 nr = vcpu->arch.interrupt.nr;
8162 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8163
8164 if (vcpu->arch.interrupt.soft) {
8165 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8166 vmcs12->vm_entry_instruction_len =
8167 vcpu->arch.event_exit_inst_len;
8168 } else
8169 idt_vectoring |= INTR_TYPE_EXT_INTR;
8170
8171 vmcs12->idt_vectoring_info_field = idt_vectoring;
8172 }
8173}
8174
4704d0be
NHE		 8175/*
8176 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8177 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8178 * and this function updates it to reflect the changes to the guest state while
8179 * L2 was running (and perhaps made some exits which were handled directly by L0
8180 * without going back to L1), and to reflect the exit reason.
8181 * Note that we do not have to copy here all VMCS fields, just those that
8182 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8183 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8184 * which already writes to vmcs12 directly.
8185 */
533558bc
JK		 8186static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8187 u32 exit_reason, u32 exit_intr_info,
8188 unsigned long exit_qualification)
4704d0be
NHE		 8189{
8190 /* update guest state fields: */
8191 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8192 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8193
8194 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8195 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8196 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8197 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8198
8199 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8200 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8201 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8202 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8203 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8204 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8205 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8206 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8207 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8208 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8209 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8210 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8211 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8212 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8213 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8214 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8215 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8216 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8217 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8218 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8219 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8220 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8221 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8222 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8223 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8224 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8225 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8226 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8227 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8228 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8229 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8230 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8231 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8232 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8233 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8234 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8235
4704d0be
NHE		 8236 vmcs12->guest_interruptibility_info =
8237 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8238 vmcs12->guest_pending_dbg_exceptions =
8239 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8240 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8241 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8242 else
8243 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8244
7854cbca
ACL		 8245 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8246 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8247 vmcs12->vmx_preemption_timer_value =
8248 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8249
3633cfc3
NHE		 8250 /*
8251 * In some cases (usually, nested EPT), L2 is allowed to change its
8252 * own CR3 without exiting. If it has changed it, we must keep it.
8253 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8254 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8255 *
8256 * Additionally, restore L2's PDPTR to vmcs12.
8257 */
8258 if (enable_ept) {
8259 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8260 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8261 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8262 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8263 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8264 }
8265
c18911a2
JK		 8266 vmcs12->vm_entry_controls =
8267 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8268 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8269
4704d0be
NHE		 8270 /* TODO: These cannot have changed unless we have MSR bitmaps and
8271 * the relevant bit asks not to trap the change */
8272 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8273 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8274 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8275 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8276 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8277 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8278 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8279 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8280
8281 /* update exit information fields: */
8282
533558bc
JK		 8283 vmcs12->vm_exit_reason = exit_reason;
8284 vmcs12->exit_qualification = exit_qualification;
4704d0be 8285
533558bc 8286 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8287 if ((vmcs12->vm_exit_intr_info &
8288 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8289 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8290 vmcs12->vm_exit_intr_error_code =
8291 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8292 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8293 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8294 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8295
5f3d5799
JK		 8296 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8297 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8298 * instead of reading the real value. */
4704d0be 8299 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8300
8301 /*
8302 * Transfer the event that L0 or L1 may wanted to inject into
8303 * L2 to IDT_VECTORING_INFO_FIELD.
8304 */
8305 vmcs12_save_pending_event(vcpu, vmcs12);
8306 }
8307
8308 /*
8309 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8310 * preserved above and would only end up incorrectly in L1.
8311 */
8312 vcpu->arch.nmi_injected = false;
8313 kvm_clear_exception_queue(vcpu);
8314 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8315}
8316
8317/*
8318 * A part of what we need to when the nested L2 guest exits and we want to
8319 * run its L1 parent, is to reset L1's guest state to the host state specified
8320 * in vmcs12.
8321 * This function is to be called not only on normal nested exit, but also on
8322 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8323 * Failures During or After Loading Guest State").
8324 * This function should be called when the active VMCS is L1's (vmcs01).
8325 */
733568f9
JK		 8326static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8327 struct vmcs12 *vmcs12)
4704d0be 8328{
21feb4eb
ACL		 8329 struct kvm_segment seg;
8330
4704d0be
NHE		 8331 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8332 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8333 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8334 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8335 else
8336 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8337 vmx_set_efer(vcpu, vcpu->arch.efer);
8338
8339 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8340 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8341 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8342 /*
8343 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8344 * actually changed, because it depends on the current state of
8345 * fpu_active (which may have changed).
8346 * Note that vmx_set_cr0 refers to efer set above.
8347 */
9e3e4dbf 8348 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8349 /*
8350 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8351 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8352 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8353 */
8354 update_exception_bitmap(vcpu);
8355 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8356 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8357
8358 /*
8359 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8360 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8361 */
8362 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8363 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8364
29bf08f1 8365 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8366
4704d0be
NHE		 8367 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8368 kvm_mmu_reset_context(vcpu);
8369
feaf0c7d
GN		 8370 if (!enable_ept)
8371 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8372
4704d0be
NHE		 8373 if (enable_vpid) {
8374 /*
8375 * Trivially support vpid by letting L2s share their parent
8376 * L1's vpid. TODO: move to a more elaborate solution, giving
8377 * each L2 its own vpid and exposing the vpid feature to L1.
8378 */
8379 vmx_flush_tlb(vcpu);
8380 }
8381
8382
8383 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8384 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8385 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8386 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8387 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8388
44811c02 8389 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8390 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8391 vcpu->arch.pat = vmcs12->host_ia32_pat;
8392 }
4704d0be
NHE		 8393 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8394 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8395 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8396
21feb4eb
ACL		 8397 /* Set L1 segment info according to Intel SDM
8398 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8399 seg = (struct kvm_segment) {
8400 .base = 0,
8401 .limit = 0xFFFFFFFF,
8402 .selector = vmcs12->host_cs_selector,
8403 .type = 11,
8404 .present = 1,
8405 .s = 1,
8406 .g = 1
8407 };
8408 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8409 seg.l = 1;
8410 else
8411 seg.db = 1;
8412 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8413 seg = (struct kvm_segment) {
8414 .base = 0,
8415 .limit = 0xFFFFFFFF,
8416 .type = 3,
8417 .present = 1,
8418 .s = 1,
8419 .db = 1,
8420 .g = 1
8421 };
8422 seg.selector = vmcs12->host_ds_selector;
8423 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8424 seg.selector = vmcs12->host_es_selector;
8425 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8426 seg.selector = vmcs12->host_ss_selector;
8427 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8428 seg.selector = vmcs12->host_fs_selector;
8429 seg.base = vmcs12->host_fs_base;
8430 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8431 seg.selector = vmcs12->host_gs_selector;
8432 seg.base = vmcs12->host_gs_base;
8433 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8434 seg = (struct kvm_segment) {
205befd9 8435 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8436 .limit = 0x67,
8437 .selector = vmcs12->host_tr_selector,
8438 .type = 11,
8439 .present = 1
8440 };
8441 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8442
503cd0c5
JK		 8443 kvm_set_dr(vcpu, 7, 0x400);
8444 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8445}
8446
8447/*
8448 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8449 * and modify vmcs12 to make it see what it would expect to see there if
8450 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8451 */
533558bc
JK		 8452static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8453 u32 exit_intr_info,
8454 unsigned long exit_qualification)
4704d0be
NHE		 8455{
8456 struct vcpu_vmx *vmx = to_vmx(vcpu);
8457 int cpu;
8458 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8459
5f3d5799
JK		 8460 /* trying to cancel vmlaunch/vmresume is a bug */
8461 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8462
4704d0be 8463 leave_guest_mode(vcpu);
533558bc
JK		 8464 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8465 exit_qualification);
4704d0be 8466
542060ea
JK		 8467 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8468 vmcs12->exit_qualification,
8469 vmcs12->idt_vectoring_info_field,
8470 vmcs12->vm_exit_intr_info,
8471 vmcs12->vm_exit_intr_error_code,
8472 KVM_ISA_VMX);
4704d0be
NHE		 8473
8474 cpu = get_cpu();
8475 vmx->loaded_vmcs = &vmx->vmcs01;
8476 vmx_vcpu_put(vcpu);
8477 vmx_vcpu_load(vcpu, cpu);
8478 vcpu->cpu = cpu;
8479 put_cpu();
8480
2961e876
GN		 8481 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8482 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8483 vmx_segment_cache_clear(vmx);
8484
4704d0be
NHE		 8485 /* if no vmcs02 cache requested, remove the one we used */
8486 if (VMCS02_POOL_SIZE == 0)
8487 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8488
8489 load_vmcs12_host_state(vcpu, vmcs12);
8490
27fc51b2 8491 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8492 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8493
8494 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8495 vmx->host_rsp = 0;
8496
8497 /* Unpin physical memory we referred to in vmcs02 */
8498 if (vmx->nested.apic_access_page) {
8499 nested_release_page(vmx->nested.apic_access_page);
8500 vmx->nested.apic_access_page = 0;
8501 }
8502
8503 /*
8504 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8505 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8506 * success or failure flag accordingly.
8507 */
8508 if (unlikely(vmx->fail)) {
8509 vmx->fail = 0;
8510 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8511 } else
8512 nested_vmx_succeed(vcpu);
012f83cb
AG		 8513 if (enable_shadow_vmcs)
8514 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8515}
8516
42124925
JK		 8517/*
8518 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8519 */
8520static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8521{
8522 if (is_guest_mode(vcpu))
533558bc 8523 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8524 free_nested(to_vmx(vcpu));
8525}
8526
7c177938
NHE		 8527/*
8528 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8529 * 23.7 "VM-entry failures during or after loading guest state" (this also
8530 * lists the acceptable exit-reason and exit-qualification parameters).
8531 * It should only be called before L2 actually succeeded to run, and when
8532 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8533 */
8534static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8535 struct vmcs12 *vmcs12,
8536 u32 reason, unsigned long qualification)
8537{
8538 load_vmcs12_host_state(vcpu, vmcs12);
8539 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8540 vmcs12->exit_qualification = qualification;
8541 nested_vmx_succeed(vcpu);
012f83cb
AG		 8542 if (enable_shadow_vmcs)
8543 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8544}
8545
8a76d7f2
JR		 8546static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8547 struct x86_instruction_info *info,
8548 enum x86_intercept_stage stage)
8549{
8550 return X86EMUL_CONTINUE;
8551}
8552
cbdd1bea 8553static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8554 .cpu_has_kvm_support = cpu_has_kvm_support,
8555 .disabled_by_bios = vmx_disabled_by_bios,
8556 .hardware_setup = hardware_setup,
8557 .hardware_unsetup = hardware_unsetup,
002c7f7c 8558 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8559 .hardware_enable = hardware_enable,
8560 .hardware_disable = hardware_disable,
04547156 8561 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8562
8563 .vcpu_create = vmx_create_vcpu,
8564 .vcpu_free = vmx_free_vcpu,
04d2cc77 8565 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8566
04d2cc77 8567 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8568 .vcpu_load = vmx_vcpu_load,
8569 .vcpu_put = vmx_vcpu_put,
8570
c8639010 8571 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8572 .get_msr = vmx_get_msr,
8573 .set_msr = vmx_set_msr,
8574 .get_segment_base = vmx_get_segment_base,
8575 .get_segment = vmx_get_segment,
8576 .set_segment = vmx_set_segment,
2e4d2653 8577 .get_cpl = vmx_get_cpl,
6aa8b732 8578 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8579 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8580 .decache_cr3 = vmx_decache_cr3,
25c4c276 8581 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8582 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8583 .set_cr3 = vmx_set_cr3,
8584 .set_cr4 = vmx_set_cr4,
6aa8b732 8585 .set_efer = vmx_set_efer,
6aa8b732
AK		 8586 .get_idt = vmx_get_idt,
8587 .set_idt = vmx_set_idt,
8588 .get_gdt = vmx_get_gdt,
8589 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8590 .get_dr6 = vmx_get_dr6,
8591 .set_dr6 = vmx_set_dr6,
020df079 8592 .set_dr7 = vmx_set_dr7,
5fdbf976 8593 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8594 .get_rflags = vmx_get_rflags,
8595 .set_rflags = vmx_set_rflags,
ebcbab4c 8596 .fpu_activate = vmx_fpu_activate,
02daab21 8597 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8598
8599 .tlb_flush = vmx_flush_tlb,
6aa8b732 8600
6aa8b732 8601 .run = vmx_vcpu_run,
6062d012 8602 .handle_exit = vmx_handle_exit,
6aa8b732 8603 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8604 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8605 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8606 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8607 .set_irq = vmx_inject_irq,
95ba8273 8608 .set_nmi = vmx_inject_nmi,
298101da 8609 .queue_exception = vmx_queue_exception,
b463a6f7 8610 .cancel_injection = vmx_cancel_injection,
78646121 8611 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8612 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8613 .get_nmi_mask = vmx_get_nmi_mask,
8614 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8615 .enable_nmi_window = enable_nmi_window,
8616 .enable_irq_window = enable_irq_window,
8617 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8618 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8619 .vm_has_apicv = vmx_vm_has_apicv,
8620 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8621 .hwapic_irr_update = vmx_hwapic_irr_update,
8622 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8623 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8624 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8625
cbc94022 8626 .set_tss_addr = vmx_set_tss_addr,
67253af5 8627 .get_tdp_level = get_ept_level,
4b12f0de 8628 .get_mt_mask = vmx_get_mt_mask,
229456fc 8629
586f9607 8630 .get_exit_info = vmx_get_exit_info,
586f9607 8631
17cc3935 8632 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8633
8634 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8635
8636 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8637 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8638
8639 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8640
8641 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8642
4051b188 8643 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8644 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8645 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8646 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8647 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8648 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8649
8650 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8651
8652 .check_intercept = vmx_check_intercept,
a547c6db 8653 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8654 .mpx_supported = vmx_mpx_supported,
6aa8b732
AK		 8655};
8656
8657static int __init vmx_init(void)
8658{
8d14695f 8659 int r, i, msr;
26bb0981
AK		 8660
8661 rdmsrl_safe(MSR_EFER, &host_efer);
8662
8663 for (i = 0; i < NR_VMX_MSR; ++i)
8664 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8665
3e7c73e9 8666 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8667 if (!vmx_io_bitmap_a)
8668 return -ENOMEM;
8669
2106a548
GC		 8670 r = -ENOMEM;
8671
3e7c73e9 8672 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8673 if (!vmx_io_bitmap_b)
fdef3ad1 8674 goto out;
fdef3ad1 8675
5897297b 8676 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8677 if (!vmx_msr_bitmap_legacy)
25c5f225 8678 goto out1;
2106a548 8679
8d14695f
YZ		 8680 vmx_msr_bitmap_legacy_x2apic =
8681 (unsigned long *)__get_free_page(GFP_KERNEL);
8682 if (!vmx_msr_bitmap_legacy_x2apic)
8683 goto out2;
25c5f225 8684
5897297b 8685 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8686 if (!vmx_msr_bitmap_longmode)
8d14695f 8687 goto out3;
2106a548 8688
8d14695f
YZ		 8689 vmx_msr_bitmap_longmode_x2apic =
8690 (unsigned long *)__get_free_page(GFP_KERNEL);
8691 if (!vmx_msr_bitmap_longmode_x2apic)
8692 goto out4;
4607c2d7
AG		 8693 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8694 if (!vmx_vmread_bitmap)
8695 goto out5;
8696
8697 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8698 if (!vmx_vmwrite_bitmap)
8699 goto out6;
8700
8701 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8702 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8703 /* shadowed read/write fields */
8704 for (i = 0; i < max_shadow_read_write_fields; i++) {
8705 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8706 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8707 }
8708 /* shadowed read only fields */
8709 for (i = 0; i < max_shadow_read_only_fields; i++)
8710 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8711
fdef3ad1
HQ		 8712 /*
8713 * Allow direct access to the PC debug port (it is often used for I/O
8714 * delays, but the vmexits simply slow things down).
8715 */
3e7c73e9
AK		 8716 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8717 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8718
3e7c73e9 8719 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8720
5897297b
AK		 8721 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8722 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8723
2384d2b3
SY		 8724 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8725
0ee75bea
AK		 8726 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8727 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8728 if (r)
4607c2d7 8729 goto out7;
25c5f225 8730
8f536b76
ZY		 8731#ifdef CONFIG_KEXEC
8732 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8733 crash_vmclear_local_loaded_vmcss);
8734#endif
8735
5897297b
AK		 8736 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8737 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8738 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8739 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8740 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8741 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8742 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8743
8d14695f
YZ		 8744 memcpy(vmx_msr_bitmap_legacy_x2apic,
8745 vmx_msr_bitmap_legacy, PAGE_SIZE);
8746 memcpy(vmx_msr_bitmap_longmode_x2apic,
8747 vmx_msr_bitmap_longmode, PAGE_SIZE);
8748
01e439be 8749 if (enable_apicv) {
8d14695f
YZ		 8750 for (msr = 0x800; msr <= 0x8ff; msr++)
8751 vmx_disable_intercept_msr_read_x2apic(msr);
8752
8753 /* According SDM, in x2apic mode, the whole id reg is used.
8754 * But in KVM, it only use the highest eight bits. Need to
8755 * intercept it */
8756 vmx_enable_intercept_msr_read_x2apic(0x802);
8757 /* TMCCT */
8758 vmx_enable_intercept_msr_read_x2apic(0x839);
8759 /* TPR */
8760 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8761 /* EOI */
8762 vmx_disable_intercept_msr_write_x2apic(0x80b);
8763 /* SELF-IPI */
8764 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8765 }
fdef3ad1 8766
089d034e 8767 if (enable_ept) {
3f6d8c8a
XH		 8768 kvm_mmu_set_mask_ptes(0ull,
8769 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8770 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8771 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8772 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8773 kvm_enable_tdp();
8774 } else
8775 kvm_disable_tdp();
1439442c 8776
fdef3ad1
HQ		 8777 return 0;
8778
4607c2d7
AG		 8779out7:
8780 free_page((unsigned long)vmx_vmwrite_bitmap);
8781out6:
8782 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8783out5:
8784 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8785out4:
5897297b 8786 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8787out3:
8788 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8789out2:
5897297b 8790 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8791out1:
3e7c73e9 8792 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8793out:
3e7c73e9 8794 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8795 return r;
6aa8b732
AK		 8796}
8797
8798static void __exit vmx_exit(void)
8799{
8d14695f
YZ		 8800 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8801 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8802 free_page((unsigned long)vmx_msr_bitmap_legacy);
8803 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8804 free_page((unsigned long)vmx_io_bitmap_b);
8805 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8806 free_page((unsigned long)vmx_vmwrite_bitmap);
8807 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8808
8f536b76
ZY		 8809#ifdef CONFIG_KEXEC
8810 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8811 synchronize_rcu();
8812#endif
8813
cb498ea2 8814 kvm_exit();
6aa8b732
AK		 8815}
8816
8817module_init(vmx_init)
8818module_exit(vmx_exit)
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