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KVM: nVMX: Further fixes for lazy FPU loading
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
61d2ef2c 121#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
fe3ef05c 348 u64 vmcs01_tsc_offset;
644d711a
NHE		 349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
fe3ef05c
NHE		 351 /*
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
354 */
355 struct page *apic_access_page;
ec378aee
NHE		 356};
357
a2fa3e9f 358struct vcpu_vmx {
fb3f0f51 359 struct kvm_vcpu vcpu;
313dbd49 360 unsigned long host_rsp;
29bd8a78 361 u8 fail;
69c73028 362 u8 cpl;
9d58b931 363 bool nmi_known_unmasked;
51aa01d1 364 u32 exit_intr_info;
1155f76a 365 u32 idt_vectoring_info;
6de12732 366 ulong rflags;
26bb0981 367 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 368 int nmsrs;
369 int save_nmsrs;
a2fa3e9f 370#ifdef CONFIG_X86_64
44ea2b17
AK		 371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
a2fa3e9f 373#endif
d462b819
NHE		 374 /*
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
378 */
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 382 struct msr_autoload {
383 unsigned nr;
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386 } msr_autoload;
a2fa3e9f
GH		 387 struct {
388 int loaded;
389 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
d77c26fc 392 } host_state;
9c8cba37 393 struct {
7ffd92c5 394 int vm86_active;
78ac8b47 395 ulong save_rflags;
7ffd92c5
AK		 396 struct kvm_save_segment {
397 u16 selector;
398 unsigned long base;
399 u32 limit;
400 u32 ar;
401 } tr, es, ds, fs, gs;
9c8cba37 402 } rmode;
2fb92db1
AK		 403 struct {
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
406 } segment_cache;
2384d2b3 407 int vpid;
04fa4d32 408 bool emulation_required;
3b86cd99
JK		 409
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
412 ktime_t entry_time;
413 s64 vnmi_blocked_time;
a0861c02 414 u32 exit_reason;
4e47c7a6
SY		 415
416 bool rdtscp_enabled;
ec378aee
NHE		 417
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
a2fa3e9f
GH		 420};
421
2fb92db1
AK		 422enum segment_cache_field {
423 SEG_FIELD_SEL = 0,
424 SEG_FIELD_BASE = 1,
425 SEG_FIELD_LIMIT = 2,
426 SEG_FIELD_AR = 3,
427
428 SEG_FIELD_NR = 4
429};
430
a2fa3e9f
GH		 431static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432{
fb3f0f51 433 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 434}
435
22bd0358
NHE		 436#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
569};
570static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572static inline short vmcs_field_to_offset(unsigned long field)
573{
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return -1;
576 return vmcs_field_to_offset_table[field];
577}
578
a9d30f33
NHE		 579static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580{
581 return to_vmx(vcpu)->nested.current_vmcs12;
582}
583
584static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585{
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
589 return NULL;
590 }
591 return page;
592}
593
594static void nested_release_page(struct page *page)
595{
596 kvm_release_page_dirty(page);
597}
598
599static void nested_release_page_clean(struct page *page)
600{
601 kvm_release_page_clean(page);
602}
603
4e1096d2 604static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 605static void kvm_cpu_vmxon(u64 addr);
606static void kvm_cpu_vmxoff(void);
aff48baa 607static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 609
6aa8b732
AK		 610static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 612/*
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 */
616static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 617static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 618
3e7c73e9
AK		 619static unsigned long *vmx_io_bitmap_a;
620static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 621static unsigned long *vmx_msr_bitmap_legacy;
622static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 623
110312c8
AK		 624static bool cpu_has_load_ia32_efer;
625
2384d2b3
SY		 626static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627static DEFINE_SPINLOCK(vmx_vpid_lock);
628
1c3d14fe 629static struct vmcs_config {
6aa8b732
AK		 630 int size;
631 int order;
632 u32 revision_id;
1c3d14fe
YS		 633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
f78e0e2e 635 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 636 u32 vmexit_ctrl;
637 u32 vmentry_ctrl;
638} vmcs_config;
6aa8b732 639
efff9e53 640static struct vmx_capability {
d56f546d
SY		 641 u32 ept;
642 u32 vpid;
643} vmx_capability;
644
6aa8b732
AK		 645#define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
651 }
652
653static struct kvm_vmx_segment_field {
654 unsigned selector;
655 unsigned base;
656 unsigned limit;
657 unsigned ar_bytes;
658} kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
667};
668
26bb0981
AK		 669static u64 host_efer;
670
6de4f3ad
AK		 671static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
4d56c8a7 673/*
8c06585d 674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 675 * away by decrementing the array size.
676 */
6aa8b732 677static const u32 vmx_msr_index[] = {
05b3e0c2 678#ifdef CONFIG_X86_64
44ea2b17 679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 680#endif
8c06585d 681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 682};
9d8f549d 683#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 684
31299944 685static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 686{
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 690}
691
31299944 692static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 693{
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 697}
698
31299944 699static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 700{
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 704}
705
31299944 706static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710}
711
31299944 712static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 713{
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717}
718
31299944 719static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 720{
04547156 721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 722}
723
31299944 724static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 725{
04547156 726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 727}
728
31299944 729static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 730{
04547156 731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 732}
733
31299944 734static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 735{
04547156
SY		 736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 738}
739
774ead3a 740static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 741{
04547156
SY		 742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744}
745
746static inline bool cpu_has_vmx_flexpriority(void)
747{
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 750}
751
e799794e
MT		 752static inline bool cpu_has_vmx_ept_execute_only(void)
753{
31299944 754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 755}
756
757static inline bool cpu_has_vmx_eptp_uncacheable(void)
758{
31299944 759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 760}
761
762static inline bool cpu_has_vmx_eptp_writeback(void)
763{
31299944 764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 765}
766
767static inline bool cpu_has_vmx_ept_2m_page(void)
768{
31299944 769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 770}
771
878403b7
SY		 772static inline bool cpu_has_vmx_ept_1g_page(void)
773{
31299944 774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 775}
776
4bc9b982
SY		 777static inline bool cpu_has_vmx_ept_4levels(void)
778{
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780}
781
31299944 782static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 783{
31299944 784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 785}
786
31299944 787static inline bool cpu_has_vmx_invept_context(void)
d56f546d 788{
31299944 789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 790}
791
31299944 792static inline bool cpu_has_vmx_invept_global(void)
d56f546d 793{
31299944 794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 795}
796
518c8aee
GJ		 797static inline bool cpu_has_vmx_invvpid_single(void)
798{
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800}
801
b9d762fa
GJ		 802static inline bool cpu_has_vmx_invvpid_global(void)
803{
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805}
806
31299944 807static inline bool cpu_has_vmx_ept(void)
d56f546d 808{
04547156
SY		 809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 814{
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817}
818
31299944 819static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 820{
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823}
824
31299944 825static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 826{
6d3e435e 827 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 828}
829
31299944 830static inline bool cpu_has_vmx_vpid(void)
2384d2b3 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
840}
841
31299944 842static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 843{
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845}
846
f5f48ee1
SY		 847static inline bool cpu_has_vmx_wbinvd_exit(void)
848{
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
851}
852
04547156
SY		 853static inline bool report_flexpriority(void)
854{
855 return flexpriority_enabled;
856}
857
fe3ef05c
NHE		 858static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859{
860 return vmcs12->cpu_based_vm_exec_control & bit;
861}
862
863static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864{
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
868}
869
644d711a
NHE		 870static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
872{
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874}
875
876static inline bool is_exception(u32 intr_info)
877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880}
881
882static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 883static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
886
8b9cf98c 887static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 888{
889 int i;
890
a2fa3e9f 891 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 893 return i;
894 return -1;
895}
896
2384d2b3
SY		 897static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898{
899 struct {
900 u64 vpid : 16;
901 u64 rsvd : 48;
902 u64 gva;
903 } operand = { vpid, 0, gva };
904
4ecac3fd 905 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 906 /* CF==1 or ZF==1 --> rc = -1 */
907 "; ja 1f ; ud2 ; 1:"
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
909}
910
1439442c
SY		 911static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912{
913 struct {
914 u64 eptp, gpa;
915 } operand = {eptp, gpa};
916
4ecac3fd 917 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
921}
922
26bb0981 923static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 924{
925 int i;
926
8b9cf98c 927 i = __find_msr_index(vmx, msr);
a75beee6 928 if (i >= 0)
a2fa3e9f 929 return &vmx->guest_msrs[i];
8b6d44c7 930 return NULL;
7725f0ba
AK		 931}
932
6aa8b732
AK		 933static void vmcs_clear(struct vmcs *vmcs)
934{
935 u64 phys_addr = __pa(vmcs);
936 u8 error;
937
4ecac3fd 938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 940 : "cc", "memory");
941 if (error)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943 vmcs, phys_addr);
944}
945
d462b819
NHE		 946static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947{
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
951}
952
7725b894
DX		 953static void vmcs_load(struct vmcs *vmcs)
954{
955 u64 phys_addr = __pa(vmcs);
956 u8 error;
957
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 960 : "cc", "memory");
961 if (error)
962 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
963 vmcs, phys_addr);
964}
965
d462b819 966static void __loaded_vmcs_clear(void *arg)
6aa8b732 967{
d462b819 968 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 969 int cpu = raw_smp_processor_id();
6aa8b732 970
d462b819
NHE		 971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 974 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 977}
978
d462b819 979static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 980{
d462b819
NHE		 981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 984}
985
1760dd49 986static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 987{
988 if (vmx->vpid == 0)
989 return;
990
518c8aee
GJ		 991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 993}
994
b9d762fa
GJ		 995static inline void vpid_sync_vcpu_global(void)
996{
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999}
1000
1001static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002{
1003 if (cpu_has_vmx_invvpid_single())
1760dd49 1004 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1005 else
1006 vpid_sync_vcpu_global();
1007}
1008
1439442c
SY		 1009static inline void ept_sync_global(void)
1010{
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013}
1014
1015static inline void ept_sync_context(u64 eptp)
1016{
089d034e 1017 if (enable_ept) {
1439442c
SY		 1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020 else
1021 ept_sync_global();
1022 }
1023}
1024
1025static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026{
089d034e 1027 if (enable_ept) {
1439442c
SY		 1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030 eptp, gpa);
1031 else
1032 ept_sync_context(eptp);
1033 }
1034}
1035
96304217 1036static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1037{
5e520e62 1038 unsigned long value;
6aa8b732 1039
5e520e62
AK		 1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1042 return value;
1043}
1044
96304217 1045static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1046{
1047 return vmcs_readl(field);
1048}
1049
96304217 1050static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1051{
1052 return vmcs_readl(field);
1053}
1054
96304217 1055static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1056{
05b3e0c2 1057#ifdef CONFIG_X86_64
6aa8b732
AK		 1058 return vmcs_readl(field);
1059#else
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061#endif
1062}
1063
e52de1b8
AK		 1064static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065{
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068 dump_stack();
1069}
1070
6aa8b732
AK		 1071static void vmcs_writel(unsigned long field, unsigned long value)
1072{
1073 u8 error;
1074
4ecac3fd 1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1077 if (unlikely(error))
1078 vmwrite_error(field, value);
6aa8b732
AK		 1079}
1080
1081static void vmcs_write16(unsigned long field, u16 value)
1082{
1083 vmcs_writel(field, value);
1084}
1085
1086static void vmcs_write32(unsigned long field, u32 value)
1087{
1088 vmcs_writel(field, value);
1089}
1090
1091static void vmcs_write64(unsigned long field, u64 value)
1092{
6aa8b732 1093 vmcs_writel(field, value);
7682f2d0 1094#ifndef CONFIG_X86_64
6aa8b732
AK		 1095 asm volatile ("");
1096 vmcs_writel(field+1, value >> 32);
1097#endif
1098}
1099
2ab455cc
AL		 1100static void vmcs_clear_bits(unsigned long field, u32 mask)
1101{
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1103}
1104
1105static void vmcs_set_bits(unsigned long field, u32 mask)
1106{
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1108}
1109
2fb92db1
AK		 1110static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111{
1112 vmx->segment_cache.bitmask = 0;
1113}
1114
1115static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116 unsigned field)
1117{
1118 bool ret;
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1124 }
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1127 return ret;
1128}
1129
1130static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131{
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136 return *p;
1137}
1138
1139static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140{
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145 return *p;
1146}
1147
1148static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149{
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154 return *p;
1155}
1156
1157static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163 return *p;
1164}
1165
abd3f2d6
AK		 1166static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167{
1168 u32 eb;
1169
fd7373cc
JK		 1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
7ffd92c5 1176 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1177 eb = ~0;
089d034e 1178 if (enable_ept)
1439442c 1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1182
1183 /* When we are running a nested L2 guest and L1 specified for it a
1184 * certain exception bitmap, we must trap the same exceptions and pass
1185 * them to L1. When running L2, we will only handle the exceptions
1186 * specified above if L1 did not want them.
1187 */
1188 if (is_guest_mode(vcpu))
1189 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
abd3f2d6
AK		 1191 vmcs_write32(EXCEPTION_BITMAP, eb);
1192}
1193
61d2ef2c
AK		 1194static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1195{
1196 unsigned i;
1197 struct msr_autoload *m = &vmx->msr_autoload;
1198
110312c8
AK		 1199 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1202 return;
1203 }
1204
61d2ef2c
AK		 1205 for (i = 0; i < m->nr; ++i)
1206 if (m->guest[i].index == msr)
1207 break;
1208
1209 if (i == m->nr)
1210 return;
1211 --m->nr;
1212 m->guest[i] = m->guest[m->nr];
1213 m->host[i] = m->host[m->nr];
1214 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1216}
1217
1218static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1219 u64 guest_val, u64 host_val)
1220{
1221 unsigned i;
1222 struct msr_autoload *m = &vmx->msr_autoload;
1223
110312c8
AK		 1224 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1225 vmcs_write64(GUEST_IA32_EFER, guest_val);
1226 vmcs_write64(HOST_IA32_EFER, host_val);
1227 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1228 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1229 return;
1230 }
1231
61d2ef2c
AK		 1232 for (i = 0; i < m->nr; ++i)
1233 if (m->guest[i].index == msr)
1234 break;
1235
1236 if (i == m->nr) {
1237 ++m->nr;
1238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1239 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1240 }
1241
1242 m->guest[i].index = msr;
1243 m->guest[i].value = guest_val;
1244 m->host[i].index = msr;
1245 m->host[i].value = host_val;
1246}
1247
33ed6329
AK		 1248static void reload_tss(void)
1249{
33ed6329
AK		 1250 /*
1251 * VT restores TR but not its size. Useless.
1252 */
d359192f 1253 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1254 struct desc_struct *descs;
33ed6329 1255
d359192f 1256 descs = (void *)gdt->address;
33ed6329
AK		 1257 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1258 load_TR_desc();
33ed6329
AK		 1259}
1260
92c0d900 1261static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1262{
3a34a881 1263 u64 guest_efer;
51c6cf66
AK		 1264 u64 ignore_bits;
1265
f6801dff 1266 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1267
51c6cf66
AK		 1268 /*
1269 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1270 * outside long mode
1271 */
1272 ignore_bits = EFER_NX | EFER_SCE;
1273#ifdef CONFIG_X86_64
1274 ignore_bits |= EFER_LMA | EFER_LME;
1275 /* SCE is meaningful only in long mode on Intel */
1276 if (guest_efer & EFER_LMA)
1277 ignore_bits &= ~(u64)EFER_SCE;
1278#endif
51c6cf66
AK		 1279 guest_efer &= ~ignore_bits;
1280 guest_efer |= host_efer & ignore_bits;
26bb0981 1281 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1282 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1283
1284 clear_atomic_switch_msr(vmx, MSR_EFER);
1285 /* On ept, can't emulate nx, and must switch nx atomically */
1286 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1287 guest_efer = vmx->vcpu.arch.efer;
1288 if (!(guest_efer & EFER_LMA))
1289 guest_efer &= ~EFER_LME;
1290 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1291 return false;
1292 }
1293
26bb0981 1294 return true;
51c6cf66
AK		 1295}
1296
2d49ec72
GN		 1297static unsigned long segment_base(u16 selector)
1298{
d359192f 1299 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1300 struct desc_struct *d;
1301 unsigned long table_base;
1302 unsigned long v;
1303
1304 if (!(selector & ~3))
1305 return 0;
1306
d359192f 1307 table_base = gdt->address;
2d49ec72
GN		 1308
1309 if (selector & 4) { /* from ldt */
1310 u16 ldt_selector = kvm_read_ldt();
1311
1312 if (!(ldt_selector & ~3))
1313 return 0;
1314
1315 table_base = segment_base(ldt_selector);
1316 }
1317 d = (struct desc_struct *)(table_base + (selector & ~7));
1318 v = get_desc_base(d);
1319#ifdef CONFIG_X86_64
1320 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1321 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1322#endif
1323 return v;
1324}
1325
1326static inline unsigned long kvm_read_tr_base(void)
1327{
1328 u16 tr;
1329 asm("str %0" : "=g"(tr));
1330 return segment_base(tr);
1331}
1332
04d2cc77 1333static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1334{
04d2cc77 1335 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1336 int i;
04d2cc77 1337
a2fa3e9f 1338 if (vmx->host_state.loaded)
33ed6329
AK		 1339 return;
1340
a2fa3e9f 1341 vmx->host_state.loaded = 1;
33ed6329
AK		 1342 /*
1343 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1344 * allow segment selectors with cpl > 0 or ti == 1.
1345 */
d6e88aec 1346 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1347 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1348 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1349 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1350 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1351 vmx->host_state.fs_reload_needed = 0;
1352 } else {
33ed6329 1353 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1354 vmx->host_state.fs_reload_needed = 1;
33ed6329 1355 }
9581d442 1356 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1357 if (!(vmx->host_state.gs_sel & 7))
1358 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1359 else {
1360 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1361 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1362 }
1363
1364#ifdef CONFIG_X86_64
1365 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1366 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1367#else
a2fa3e9f
GH		 1368 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1369 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1370#endif
707c0874
AK		 1371
1372#ifdef CONFIG_X86_64
c8770e7b
AK		 1373 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1374 if (is_long_mode(&vmx->vcpu))
44ea2b17 1375 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1376#endif
26bb0981
AK		 1377 for (i = 0; i < vmx->save_nmsrs; ++i)
1378 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1379 vmx->guest_msrs[i].data,
1380 vmx->guest_msrs[i].mask);
33ed6329
AK		 1381}
1382
a9b21b62 1383static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1384{
a2fa3e9f 1385 if (!vmx->host_state.loaded)
33ed6329
AK		 1386 return;
1387
e1beb1d3 1388 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1389 vmx->host_state.loaded = 0;
c8770e7b
AK		 1390#ifdef CONFIG_X86_64
1391 if (is_long_mode(&vmx->vcpu))
1392 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1393#endif
152d3f2f 1394 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1395 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1396#ifdef CONFIG_X86_64
9581d442 1397 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1398#else
1399 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1400#endif
33ed6329 1401 }
0a77fe4c
AK		 1402 if (vmx->host_state.fs_reload_needed)
1403 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1404 reload_tss();
44ea2b17 1405#ifdef CONFIG_X86_64
c8770e7b 1406 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1407#endif
1c11e713
AK		 1408 if (current_thread_info()->status & TS_USEDFPU)
1409 clts();
3444d7da 1410 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1411}
1412
a9b21b62
AK		 1413static void vmx_load_host_state(struct vcpu_vmx *vmx)
1414{
1415 preempt_disable();
1416 __vmx_load_host_state(vmx);
1417 preempt_enable();
1418}
1419
6aa8b732
AK		 1420/*
1421 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422 * vcpu mutex is already taken.
1423 */
15ad7146 1424static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1425{
a2fa3e9f 1426 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1427 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1428
4610c9cc
DX		 1429 if (!vmm_exclusive)
1430 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1431 else if (vmx->loaded_vmcs->cpu != cpu)
1432 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1433
d462b819
NHE		 1434 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1435 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1436 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1437 }
1438
d462b819 1439 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1440 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1441 unsigned long sysenter_esp;
1442
a8eeb04a 1443 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1444 local_irq_disable();
d462b819
NHE		 1445 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1446 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1447 local_irq_enable();
1448
6aa8b732
AK		 1449 /*
1450 * Linux uses per-cpu TSS and GDT, so set these when switching
1451 * processors.
1452 */
d6e88aec 1453 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1454 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1455
1456 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1457 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1458 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1459 }
6aa8b732
AK		 1460}
1461
1462static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1463{
a9b21b62 1464 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1465 if (!vmm_exclusive) {
d462b819
NHE		 1466 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1467 vcpu->cpu = -1;
4610c9cc
DX		 1468 kvm_cpu_vmxoff();
1469 }
6aa8b732
AK		 1470}
1471
5fd86fcf
AK		 1472static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1473{
81231c69
AK		 1474 ulong cr0;
1475
5fd86fcf
AK		 1476 if (vcpu->fpu_active)
1477 return;
1478 vcpu->fpu_active = 1;
81231c69
AK		 1479 cr0 = vmcs_readl(GUEST_CR0);
1480 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1481 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1482 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1483 update_exception_bitmap(vcpu);
edcafe3c 1484 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1485 if (is_guest_mode(vcpu))
1486 vcpu->arch.cr0_guest_owned_bits &=
1487 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1488 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1489}
1490
edcafe3c
AK		 1491static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1492
fe3ef05c
NHE		 1493/*
1494 * Return the cr0 value that a nested guest would read. This is a combination
1495 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496 * its hypervisor (cr0_read_shadow).
1497 */
1498static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1499{
1500 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1501 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1502}
1503static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1504{
1505 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1506 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1507}
1508
5fd86fcf
AK		 1509static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1510{
36cf24e0
NHE		 1511 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512 * set this *before* calling this function.
1513 */
edcafe3c 1514 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1515 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1516 update_exception_bitmap(vcpu);
edcafe3c
AK		 1517 vcpu->arch.cr0_guest_owned_bits = 0;
1518 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1519 if (is_guest_mode(vcpu)) {
1520 /*
1521 * L1's specified read shadow might not contain the TS bit,
1522 * so now that we turned on shadowing of this bit, we need to
1523 * set this bit of the shadow. Like in nested_vmx_run we need
1524 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525 * up-to-date here because we just decached cr0.TS (and we'll
1526 * only update vmcs12->guest_cr0 on nested exit).
1527 */
1528 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1529 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1530 (vcpu->arch.cr0 & X86_CR0_TS);
1531 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1532 } else
1533 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1534}
1535
6aa8b732
AK		 1536static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1537{
78ac8b47 1538 unsigned long rflags, save_rflags;
345dcaa8 1539
6de12732
AK		 1540 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1541 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1542 rflags = vmcs_readl(GUEST_RFLAGS);
1543 if (to_vmx(vcpu)->rmode.vm86_active) {
1544 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1545 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1546 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1547 }
1548 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1549 }
6de12732 1550 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1551}
1552
1553static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1554{
6de12732 1555 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1556 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1557 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1558 if (to_vmx(vcpu)->rmode.vm86_active) {
1559 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1560 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1561 }
6aa8b732
AK		 1562 vmcs_writel(GUEST_RFLAGS, rflags);
1563}
1564
2809f5d2
GC		 1565static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1566{
1567 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1568 int ret = 0;
1569
1570 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1571 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1572 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1573 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1574
1575 return ret & mask;
1576}
1577
1578static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1579{
1580 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1581 u32 interruptibility = interruptibility_old;
1582
1583 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1584
48005f64 1585 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1586 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1587 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1588 interruptibility |= GUEST_INTR_STATE_STI;
1589
1590 if ((interruptibility != interruptibility_old))
1591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1592}
1593
6aa8b732
AK		 1594static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1595{
1596 unsigned long rip;
6aa8b732 1597
5fdbf976 1598 rip = kvm_rip_read(vcpu);
6aa8b732 1599 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1600 kvm_rip_write(vcpu, rip);
6aa8b732 1601
2809f5d2
GC		 1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1604}
1605
443381a8
AL		 1606static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607{
1608 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1609 * explicitly skip the instruction because if the HLT state is set, then
1610 * the instruction is already executing and RIP has already been
1611 * advanced. */
1612 if (!yield_on_hlt &&
1613 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1614 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1615}
1616
0b6ac343
NHE		 1617/*
1618 * KVM wants to inject page-faults which it got to the guest. This function
1619 * checks whether in a nested guest, we need to inject them to L1 or L2.
1620 * This function assumes it is called with the exit reason in vmcs02 being
1621 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1622 * is running).
1623 */
1624static int nested_pf_handled(struct kvm_vcpu *vcpu)
1625{
1626 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1627
1628 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1630 return 0;
1631
1632 nested_vmx_vmexit(vcpu);
1633 return 1;
1634}
1635
298101da 1636static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1637 bool has_error_code, u32 error_code,
1638 bool reinject)
298101da 1639{
77ab6db0 1640 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1641 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1642
0b6ac343
NHE		 1643 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1644 nested_pf_handled(vcpu))
1645 return;
1646
8ab2d2e2 1647 if (has_error_code) {
77ab6db0 1648 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1649 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1650 }
77ab6db0 1651
7ffd92c5 1652 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1653 int inc_eip = 0;
1654 if (kvm_exception_is_soft(nr))
1655 inc_eip = vcpu->arch.event_exit_inst_len;
1656 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1657 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1658 return;
1659 }
1660
66fd3f7f
GN		 1661 if (kvm_exception_is_soft(nr)) {
1662 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1663 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1664 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1665 } else
1666 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1667
1668 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1669 vmx_clear_hlt(vcpu);
298101da
AK		 1670}
1671
4e47c7a6
SY		 1672static bool vmx_rdtscp_supported(void)
1673{
1674 return cpu_has_vmx_rdtscp();
1675}
1676
a75beee6
ED		 1677/*
1678 * Swap MSR entry in host/guest MSR entry array.
1679 */
8b9cf98c 1680static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1681{
26bb0981 1682 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1683
1684 tmp = vmx->guest_msrs[to];
1685 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1686 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1687}
1688
e38aea3e
AK		 1689/*
1690 * Set up the vmcs to automatically save and restore system
1691 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1692 * mode, as fiddling with msrs is very expensive.
1693 */
8b9cf98c 1694static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1695{
26bb0981 1696 int save_nmsrs, index;
5897297b 1697 unsigned long *msr_bitmap;
e38aea3e 1698
33f9c505 1699 vmx_load_host_state(vmx);
a75beee6
ED		 1700 save_nmsrs = 0;
1701#ifdef CONFIG_X86_64
8b9cf98c 1702 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1703 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1704 if (index >= 0)
8b9cf98c
RR		 1705 move_msr_up(vmx, index, save_nmsrs++);
1706 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1707 if (index >= 0)
8b9cf98c
RR		 1708 move_msr_up(vmx, index, save_nmsrs++);
1709 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1710 if (index >= 0)
8b9cf98c 1711 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1712 index = __find_msr_index(vmx, MSR_TSC_AUX);
1713 if (index >= 0 && vmx->rdtscp_enabled)
1714 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1715 /*
8c06585d 1716 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1717 * if efer.sce is enabled.
1718 */
8c06585d 1719 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1720 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1721 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1722 }
1723#endif
92c0d900
AK		 1724 index = __find_msr_index(vmx, MSR_EFER);
1725 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1726 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1727
26bb0981 1728 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1729
1730 if (cpu_has_vmx_msr_bitmap()) {
1731 if (is_long_mode(&vmx->vcpu))
1732 msr_bitmap = vmx_msr_bitmap_longmode;
1733 else
1734 msr_bitmap = vmx_msr_bitmap_legacy;
1735
1736 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1737 }
e38aea3e
AK		 1738}
1739
6aa8b732
AK		 1740/*
1741 * reads and returns guest's timestamp counter "register"
1742 * guest_tsc = host_tsc + tsc_offset -- 21.3
1743 */
1744static u64 guest_read_tsc(void)
1745{
1746 u64 host_tsc, tsc_offset;
1747
1748 rdtscll(host_tsc);
1749 tsc_offset = vmcs_read64(TSC_OFFSET);
1750 return host_tsc + tsc_offset;
1751}
1752
4051b188
JR		 1753/*
1754 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1755 * ioctl. In this case the call-back should update internal vmx state to make
1756 * the changes effective.
1757 */
1758static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1759{
1760 /* Nothing to do here */
1761}
1762
6aa8b732 1763/*
99e3e30a 1764 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1765 */
99e3e30a 1766static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1767{
f4e1b3c8 1768 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1769}
1770
e48672fa
ZA		 1771static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1772{
1773 u64 offset = vmcs_read64(TSC_OFFSET);
1774 vmcs_write64(TSC_OFFSET, offset + adjustment);
1775}
1776
857e4099
JR		 1777static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1778{
1779 return target_tsc - native_read_tsc();
1780}
1781
801d3424
NHE		 1782static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1783{
1784 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1785 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1786}
1787
1788/*
1789 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1790 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1791 * all guests if the "nested" module option is off, and can also be disabled
1792 * for a single guest by disabling its VMX cpuid bit.
1793 */
1794static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1795{
1796 return nested && guest_cpuid_has_vmx(vcpu);
1797}
1798
b87a51ae
NHE		 1799/*
1800 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1801 * returned for the various VMX controls MSRs when nested VMX is enabled.
1802 * The same values should also be used to verify that vmcs12 control fields are
1803 * valid during nested entry from L1 to L2.
1804 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1805 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1806 * bit in the high half is on if the corresponding bit in the control field
1807 * may be on. See also vmx_control_verify().
1808 * TODO: allow these variables to be modified (downgraded) by module options
1809 * or other means.
1810 */
1811static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1812static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1813static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1814static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1815static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1816static __init void nested_vmx_setup_ctls_msrs(void)
1817{
1818 /*
1819 * Note that as a general rule, the high half of the MSRs (bits in
1820 * the control fields which may be 1) should be initialized by the
1821 * intersection of the underlying hardware's MSR (i.e., features which
1822 * can be supported) and the list of features we want to expose -
1823 * because they are known to be properly supported in our code.
1824 * Also, usually, the low half of the MSRs (bits which must be 1) can
1825 * be set to 0, meaning that L1 may turn off any of these bits. The
1826 * reason is that if one of these bits is necessary, it will appear
1827 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1828 * fields of vmcs01 and vmcs02, will turn these bits off - and
1829 * nested_vmx_exit_handled() will not pass related exits to L1.
1830 * These rules have exceptions below.
1831 */
1832
1833 /* pin-based controls */
1834 /*
1835 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1836 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1837 */
1838 nested_vmx_pinbased_ctls_low = 0x16 ;
1839 nested_vmx_pinbased_ctls_high = 0x16 |
1840 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1841 PIN_BASED_VIRTUAL_NMIS;
1842
1843 /* exit controls */
1844 nested_vmx_exit_ctls_low = 0;
b6f1250e 1845 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1846#ifdef CONFIG_X86_64
1847 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1848#else
1849 nested_vmx_exit_ctls_high = 0;
1850#endif
1851
1852 /* entry controls */
1853 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1854 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1855 nested_vmx_entry_ctls_low = 0;
1856 nested_vmx_entry_ctls_high &=
1857 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1858
1859 /* cpu-based controls */
1860 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1861 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1862 nested_vmx_procbased_ctls_low = 0;
1863 nested_vmx_procbased_ctls_high &=
1864 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1865 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1866 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1867 CPU_BASED_CR3_STORE_EXITING |
1868#ifdef CONFIG_X86_64
1869 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1870#endif
1871 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1872 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1873 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1874 /*
1875 * We can allow some features even when not supported by the
1876 * hardware. For example, L1 can specify an MSR bitmap - and we
1877 * can use it to avoid exits to L1 - even when L0 runs L2
1878 * without MSR bitmaps.
1879 */
1880 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1881
1882 /* secondary cpu-based controls */
1883 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1884 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1885 nested_vmx_secondary_ctls_low = 0;
1886 nested_vmx_secondary_ctls_high &=
1887 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1888}
1889
1890static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1891{
1892 /*
1893 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1894 */
1895 return ((control & high) | low) == control;
1896}
1897
1898static inline u64 vmx_control_msr(u32 low, u32 high)
1899{
1900 return low | ((u64)high << 32);
1901}
1902
1903/*
1904 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1905 * also let it use VMX-specific MSRs.
1906 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1907 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1908 * like all other MSRs).
1909 */
1910static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1911{
1912 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1913 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1914 /*
1915 * According to the spec, processors which do not support VMX
1916 * should throw a #GP(0) when VMX capability MSRs are read.
1917 */
1918 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1919 return 1;
1920 }
1921
1922 switch (msr_index) {
1923 case MSR_IA32_FEATURE_CONTROL:
1924 *pdata = 0;
1925 break;
1926 case MSR_IA32_VMX_BASIC:
1927 /*
1928 * This MSR reports some information about VMX support. We
1929 * should return information about the VMX we emulate for the
1930 * guest, and the VMCS structure we give it - not about the
1931 * VMX support of the underlying hardware.
1932 */
1933 *pdata = VMCS12_REVISION |
1934 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1935 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1936 break;
1937 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1938 case MSR_IA32_VMX_PINBASED_CTLS:
1939 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1940 nested_vmx_pinbased_ctls_high);
1941 break;
1942 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1943 case MSR_IA32_VMX_PROCBASED_CTLS:
1944 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1945 nested_vmx_procbased_ctls_high);
1946 break;
1947 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1948 case MSR_IA32_VMX_EXIT_CTLS:
1949 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1950 nested_vmx_exit_ctls_high);
1951 break;
1952 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1953 case MSR_IA32_VMX_ENTRY_CTLS:
1954 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1955 nested_vmx_entry_ctls_high);
1956 break;
1957 case MSR_IA32_VMX_MISC:
1958 *pdata = 0;
1959 break;
1960 /*
1961 * These MSRs specify bits which the guest must keep fixed (on or off)
1962 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1963 * We picked the standard core2 setting.
1964 */
1965#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1966#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1967 case MSR_IA32_VMX_CR0_FIXED0:
1968 *pdata = VMXON_CR0_ALWAYSON;
1969 break;
1970 case MSR_IA32_VMX_CR0_FIXED1:
1971 *pdata = -1ULL;
1972 break;
1973 case MSR_IA32_VMX_CR4_FIXED0:
1974 *pdata = VMXON_CR4_ALWAYSON;
1975 break;
1976 case MSR_IA32_VMX_CR4_FIXED1:
1977 *pdata = -1ULL;
1978 break;
1979 case MSR_IA32_VMX_VMCS_ENUM:
1980 *pdata = 0x1f;
1981 break;
1982 case MSR_IA32_VMX_PROCBASED_CTLS2:
1983 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1984 nested_vmx_secondary_ctls_high);
1985 break;
1986 case MSR_IA32_VMX_EPT_VPID_CAP:
1987 /* Currently, no nested ept or nested vpid */
1988 *pdata = 0;
1989 break;
1990 default:
1991 return 0;
1992 }
1993
1994 return 1;
1995}
1996
1997static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1998{
1999 if (!nested_vmx_allowed(vcpu))
2000 return 0;
2001
2002 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2003 /* TODO: the right thing. */
2004 return 1;
2005 /*
2006 * No need to treat VMX capability MSRs specially: If we don't handle
2007 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2008 */
2009 return 0;
2010}
2011
6aa8b732
AK		 2012/*
2013 * Reads an msr value (of 'msr_index') into 'pdata'.
2014 * Returns 0 on success, non-0 otherwise.
2015 * Assumes vcpu_load() was already called.
2016 */
2017static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2018{
2019 u64 data;
26bb0981 2020 struct shared_msr_entry *msr;
6aa8b732
AK		 2021
2022 if (!pdata) {
2023 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2024 return -EINVAL;
2025 }
2026
2027 switch (msr_index) {
05b3e0c2 2028#ifdef CONFIG_X86_64
6aa8b732
AK		 2029 case MSR_FS_BASE:
2030 data = vmcs_readl(GUEST_FS_BASE);
2031 break;
2032 case MSR_GS_BASE:
2033 data = vmcs_readl(GUEST_GS_BASE);
2034 break;
44ea2b17
AK		 2035 case MSR_KERNEL_GS_BASE:
2036 vmx_load_host_state(to_vmx(vcpu));
2037 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2038 break;
26bb0981 2039#endif
6aa8b732 2040 case MSR_EFER:
3bab1f5d 2041 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2042 case MSR_IA32_TSC:
6aa8b732
AK		 2043 data = guest_read_tsc();
2044 break;
2045 case MSR_IA32_SYSENTER_CS:
2046 data = vmcs_read32(GUEST_SYSENTER_CS);
2047 break;
2048 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2049 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2050 break;
2051 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2052 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2053 break;
4e47c7a6
SY		 2054 case MSR_TSC_AUX:
2055 if (!to_vmx(vcpu)->rdtscp_enabled)
2056 return 1;
2057 /* Otherwise falls through */
6aa8b732 2058 default:
26bb0981 2059 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2060 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2061 return 0;
8b9cf98c 2062 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2063 if (msr) {
542423b0 2064 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2065 data = msr->data;
2066 break;
6aa8b732 2067 }
3bab1f5d 2068 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2069 }
2070
2071 *pdata = data;
2072 return 0;
2073}
2074
2075/*
2076 * Writes msr value into into the appropriate "register".
2077 * Returns 0 on success, non-0 otherwise.
2078 * Assumes vcpu_load() was already called.
2079 */
2080static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2081{
a2fa3e9f 2082 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2083 struct shared_msr_entry *msr;
2cc51560
ED		 2084 int ret = 0;
2085
6aa8b732 2086 switch (msr_index) {
3bab1f5d 2087 case MSR_EFER:
a9b21b62 2088 vmx_load_host_state(vmx);
2cc51560 2089 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2090 break;
16175a79 2091#ifdef CONFIG_X86_64
6aa8b732 2092 case MSR_FS_BASE:
2fb92db1 2093 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2094 vmcs_writel(GUEST_FS_BASE, data);
2095 break;
2096 case MSR_GS_BASE:
2fb92db1 2097 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2098 vmcs_writel(GUEST_GS_BASE, data);
2099 break;
44ea2b17
AK		 2100 case MSR_KERNEL_GS_BASE:
2101 vmx_load_host_state(vmx);
2102 vmx->msr_guest_kernel_gs_base = data;
2103 break;
6aa8b732
AK		 2104#endif
2105 case MSR_IA32_SYSENTER_CS:
2106 vmcs_write32(GUEST_SYSENTER_CS, data);
2107 break;
2108 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2109 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2110 break;
2111 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2112 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2113 break;
af24a4e4 2114 case MSR_IA32_TSC:
99e3e30a 2115 kvm_write_tsc(vcpu, data);
6aa8b732 2116 break;
468d472f
SY		 2117 case MSR_IA32_CR_PAT:
2118 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2119 vmcs_write64(GUEST_IA32_PAT, data);
2120 vcpu->arch.pat = data;
2121 break;
2122 }
4e47c7a6
SY		 2123 ret = kvm_set_msr_common(vcpu, msr_index, data);
2124 break;
2125 case MSR_TSC_AUX:
2126 if (!vmx->rdtscp_enabled)
2127 return 1;
2128 /* Check reserved bit, higher 32 bits should be zero */
2129 if ((data >> 32) != 0)
2130 return 1;
2131 /* Otherwise falls through */
6aa8b732 2132 default:
b87a51ae
NHE		 2133 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2134 break;
8b9cf98c 2135 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2136 if (msr) {
542423b0 2137 vmx_load_host_state(vmx);
3bab1f5d
AK		 2138 msr->data = data;
2139 break;
6aa8b732 2140 }
2cc51560 2141 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2142 }
2143
2cc51560 2144 return ret;
6aa8b732
AK		 2145}
2146
5fdbf976 2147static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2148{
5fdbf976
MT		 2149 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2150 switch (reg) {
2151 case VCPU_REGS_RSP:
2152 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2153 break;
2154 case VCPU_REGS_RIP:
2155 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2156 break;
6de4f3ad
AK		 2157 case VCPU_EXREG_PDPTR:
2158 if (enable_ept)
2159 ept_save_pdptrs(vcpu);
2160 break;
5fdbf976
MT		 2161 default:
2162 break;
2163 }
6aa8b732
AK		 2164}
2165
355be0b9 2166static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2167{
ae675ef0
JK		 2168 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2169 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2170 else
2171 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2172
abd3f2d6 2173 update_exception_bitmap(vcpu);
6aa8b732
AK		 2174}
2175
2176static __init int cpu_has_kvm_support(void)
2177{
6210e37b 2178 return cpu_has_vmx();
6aa8b732
AK		 2179}
2180
2181static __init int vmx_disabled_by_bios(void)
2182{
2183 u64 msr;
2184
2185 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2186 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2187 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2188 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2189 && tboot_enabled())
2190 return 1;
23f3e991 2191 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2192 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2193 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2194 && !tboot_enabled()) {
2195 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2196 "activate TXT before enabling KVM\n");
cafd6659 2197 return 1;
f9335afe 2198 }
23f3e991
JC		 2199 /* launched w/o TXT and VMX disabled */
2200 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2201 && !tboot_enabled())
2202 return 1;
cafd6659
SW		 2203 }
2204
2205 return 0;
6aa8b732
AK		 2206}
2207
7725b894
DX		 2208static void kvm_cpu_vmxon(u64 addr)
2209{
2210 asm volatile (ASM_VMX_VMXON_RAX
2211 : : "a"(&addr), "m"(addr)
2212 : "memory", "cc");
2213}
2214
10474ae8 2215static int hardware_enable(void *garbage)
6aa8b732
AK		 2216{
2217 int cpu = raw_smp_processor_id();
2218 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2219 u64 old, test_bits;
6aa8b732 2220
10474ae8
AG		 2221 if (read_cr4() & X86_CR4_VMXE)
2222 return -EBUSY;
2223
d462b819 2224 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2225 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2226
2227 test_bits = FEATURE_CONTROL_LOCKED;
2228 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2229 if (tboot_enabled())
2230 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2231
2232 if ((old & test_bits) != test_bits) {
6aa8b732 2233 /* enable and lock */
cafd6659
SW		 2234 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2235 }
66aee91a 2236 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2237
4610c9cc
DX		 2238 if (vmm_exclusive) {
2239 kvm_cpu_vmxon(phys_addr);
2240 ept_sync_global();
2241 }
10474ae8 2242
3444d7da
AK		 2243 store_gdt(&__get_cpu_var(host_gdt));
2244
10474ae8 2245 return 0;
6aa8b732
AK		 2246}
2247
d462b819 2248static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2249{
2250 int cpu = raw_smp_processor_id();
d462b819 2251 struct loaded_vmcs *v, *n;
543e4243 2252
d462b819
NHE		 2253 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2254 loaded_vmcss_on_cpu_link)
2255 __loaded_vmcs_clear(v);
543e4243
AK		 2256}
2257
710ff4a8
EH		 2258
2259/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2260 * tricks.
2261 */
2262static void kvm_cpu_vmxoff(void)
6aa8b732 2263{
4ecac3fd 2264 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2265}
2266
710ff4a8
EH		 2267static void hardware_disable(void *garbage)
2268{
4610c9cc 2269 if (vmm_exclusive) {
d462b819 2270 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2271 kvm_cpu_vmxoff();
2272 }
7725b894 2273 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2274}
2275
1c3d14fe 2276static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2277 u32 msr, u32 *result)
1c3d14fe
YS		 2278{
2279 u32 vmx_msr_low, vmx_msr_high;
2280 u32 ctl = ctl_min | ctl_opt;
2281
2282 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2283
2284 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2285 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2286
2287 /* Ensure minimum (required) set of control bits are supported. */
2288 if (ctl_min & ~ctl)
002c7f7c 2289 return -EIO;
1c3d14fe
YS		 2290
2291 *result = ctl;
2292 return 0;
2293}
2294
110312c8
AK		 2295static __init bool allow_1_setting(u32 msr, u32 ctl)
2296{
2297 u32 vmx_msr_low, vmx_msr_high;
2298
2299 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2300 return vmx_msr_high & ctl;
2301}
2302
002c7f7c 2303static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2304{
2305 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2306 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2307 u32 _pin_based_exec_control = 0;
2308 u32 _cpu_based_exec_control = 0;
f78e0e2e 2309 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2310 u32 _vmexit_control = 0;
2311 u32 _vmentry_control = 0;
2312
2313 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2314 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2315 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2316 &_pin_based_exec_control) < 0)
002c7f7c 2317 return -EIO;
1c3d14fe 2318
443381a8 2319 min =
1c3d14fe
YS		 2320#ifdef CONFIG_X86_64
2321 CPU_BASED_CR8_LOAD_EXITING |
2322 CPU_BASED_CR8_STORE_EXITING |
2323#endif
d56f546d
SY		 2324 CPU_BASED_CR3_LOAD_EXITING |
2325 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2326 CPU_BASED_USE_IO_BITMAPS |
2327 CPU_BASED_MOV_DR_EXITING |
a7052897 2328 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2329 CPU_BASED_MWAIT_EXITING |
2330 CPU_BASED_MONITOR_EXITING |
a7052897 2331 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2332
2333 if (yield_on_hlt)
2334 min |= CPU_BASED_HLT_EXITING;
2335
f78e0e2e 2336 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2337 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2338 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2339 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2340 &_cpu_based_exec_control) < 0)
002c7f7c 2341 return -EIO;
6e5d865c
YS		 2342#ifdef CONFIG_X86_64
2343 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2344 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2345 ~CPU_BASED_CR8_STORE_EXITING;
2346#endif
f78e0e2e 2347 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2348 min2 = 0;
2349 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2350 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2351 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2352 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2353 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2354 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2355 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2356 if (adjust_vmx_controls(min2, opt2,
2357 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2358 &_cpu_based_2nd_exec_control) < 0)
2359 return -EIO;
2360 }
2361#ifndef CONFIG_X86_64
2362 if (!(_cpu_based_2nd_exec_control &
2363 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2364 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2365#endif
d56f546d 2366 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2367 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2368 enabled */
5fff7d27
GN		 2369 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2370 CPU_BASED_CR3_STORE_EXITING |
2371 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2372 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2373 vmx_capability.ept, vmx_capability.vpid);
2374 }
1c3d14fe
YS		 2375
2376 min = 0;
2377#ifdef CONFIG_X86_64
2378 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2379#endif
468d472f 2380 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2381 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2382 &_vmexit_control) < 0)
002c7f7c 2383 return -EIO;
1c3d14fe 2384
468d472f
SY		 2385 min = 0;
2386 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2387 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2388 &_vmentry_control) < 0)
002c7f7c 2389 return -EIO;
6aa8b732 2390
c68876fd 2391 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2392
2393 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2394 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2395 return -EIO;
1c3d14fe
YS		 2396
2397#ifdef CONFIG_X86_64
2398 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2399 if (vmx_msr_high & (1u<<16))
002c7f7c 2400 return -EIO;
1c3d14fe
YS		 2401#endif
2402
2403 /* Require Write-Back (WB) memory type for VMCS accesses. */
2404 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2405 return -EIO;
1c3d14fe 2406
002c7f7c
YS		 2407 vmcs_conf->size = vmx_msr_high & 0x1fff;
2408 vmcs_conf->order = get_order(vmcs_config.size);
2409 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2410
002c7f7c
YS		 2411 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2412 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2413 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2414 vmcs_conf->vmexit_ctrl = _vmexit_control;
2415 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2416
110312c8
AK		 2417 cpu_has_load_ia32_efer =
2418 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2419 VM_ENTRY_LOAD_IA32_EFER)
2420 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2421 VM_EXIT_LOAD_IA32_EFER);
2422
1c3d14fe 2423 return 0;
c68876fd 2424}
6aa8b732
AK		 2425
2426static struct vmcs *alloc_vmcs_cpu(int cpu)
2427{
2428 int node = cpu_to_node(cpu);
2429 struct page *pages;
2430 struct vmcs *vmcs;
2431
6484eb3e 2432 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2433 if (!pages)
2434 return NULL;
2435 vmcs = page_address(pages);
1c3d14fe
YS		 2436 memset(vmcs, 0, vmcs_config.size);
2437 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2438 return vmcs;
2439}
2440
2441static struct vmcs *alloc_vmcs(void)
2442{
d3b2c338 2443 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2444}
2445
2446static void free_vmcs(struct vmcs *vmcs)
2447{
1c3d14fe 2448 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2449}
2450
d462b819
NHE		 2451/*
2452 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2453 */
2454static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2455{
2456 if (!loaded_vmcs->vmcs)
2457 return;
2458 loaded_vmcs_clear(loaded_vmcs);
2459 free_vmcs(loaded_vmcs->vmcs);
2460 loaded_vmcs->vmcs = NULL;
2461}
2462
39959588 2463static void free_kvm_area(void)
6aa8b732
AK		 2464{
2465 int cpu;
2466
3230bb47 2467 for_each_possible_cpu(cpu) {
6aa8b732 2468 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2469 per_cpu(vmxarea, cpu) = NULL;
2470 }
6aa8b732
AK		 2471}
2472
6aa8b732
AK		 2473static __init int alloc_kvm_area(void)
2474{
2475 int cpu;
2476
3230bb47 2477 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2478 struct vmcs *vmcs;
2479
2480 vmcs = alloc_vmcs_cpu(cpu);
2481 if (!vmcs) {
2482 free_kvm_area();
2483 return -ENOMEM;
2484 }
2485
2486 per_cpu(vmxarea, cpu) = vmcs;
2487 }
2488 return 0;
2489}
2490
2491static __init int hardware_setup(void)
2492{
002c7f7c
YS		 2493 if (setup_vmcs_config(&vmcs_config) < 0)
2494 return -EIO;
50a37eb4
JR		 2495
2496 if (boot_cpu_has(X86_FEATURE_NX))
2497 kvm_enable_efer_bits(EFER_NX);
2498
93ba03c2
SY		 2499 if (!cpu_has_vmx_vpid())
2500 enable_vpid = 0;
2501
4bc9b982
SY		 2502 if (!cpu_has_vmx_ept() ||
2503 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2504 enable_ept = 0;
3a624e29
NK		 2505 enable_unrestricted_guest = 0;
2506 }
2507
2508 if (!cpu_has_vmx_unrestricted_guest())
2509 enable_unrestricted_guest = 0;
93ba03c2
SY		 2510
2511 if (!cpu_has_vmx_flexpriority())
2512 flexpriority_enabled = 0;
2513
95ba8273
GN		 2514 if (!cpu_has_vmx_tpr_shadow())
2515 kvm_x86_ops->update_cr8_intercept = NULL;
2516
54dee993
MT		 2517 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2518 kvm_disable_largepages();
2519
4b8d54f9
ZE		 2520 if (!cpu_has_vmx_ple())
2521 ple_gap = 0;
2522
b87a51ae
NHE		 2523 if (nested)
2524 nested_vmx_setup_ctls_msrs();
2525
6aa8b732
AK		 2526 return alloc_kvm_area();
2527}
2528
2529static __exit void hardware_unsetup(void)
2530{
2531 free_kvm_area();
2532}
2533
6aa8b732
AK		 2534static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2535{
2536 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2537
6af11b9e 2538 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2539 vmcs_write16(sf->selector, save->selector);
2540 vmcs_writel(sf->base, save->base);
2541 vmcs_write32(sf->limit, save->limit);
2542 vmcs_write32(sf->ar_bytes, save->ar);
2543 } else {
2544 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2545 << AR_DPL_SHIFT;
2546 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2547 }
2548}
2549
2550static void enter_pmode(struct kvm_vcpu *vcpu)
2551{
2552 unsigned long flags;
a89a8fb9 2553 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2554
a89a8fb9 2555 vmx->emulation_required = 1;
7ffd92c5 2556 vmx->rmode.vm86_active = 0;
6aa8b732 2557
2fb92db1
AK		 2558 vmx_segment_cache_clear(vmx);
2559
d0ba64f9 2560 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2561 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2562 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2563 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2564
2565 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2566 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2567 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2568 vmcs_writel(GUEST_RFLAGS, flags);
2569
66aee91a
RR		 2570 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2571 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2572
2573 update_exception_bitmap(vcpu);
2574
a89a8fb9
MG		 2575 if (emulate_invalid_guest_state)
2576 return;
2577
7ffd92c5
AK		 2578 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2579 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2580 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2581 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2582
2fb92db1
AK		 2583 vmx_segment_cache_clear(vmx);
2584
6aa8b732
AK		 2585 vmcs_write16(GUEST_SS_SELECTOR, 0);
2586 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2587
2588 vmcs_write16(GUEST_CS_SELECTOR,
2589 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2590 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2591}
2592
d77c26fc 2593static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2594{
bfc6d222 2595 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2596 struct kvm_memslots *slots;
2597 gfn_t base_gfn;
2598
90d83dc3 2599 slots = kvm_memslots(kvm);
f495c6e5 2600 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2601 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2602 return base_gfn << PAGE_SHIFT;
2603 }
bfc6d222 2604 return kvm->arch.tss_addr;
6aa8b732
AK		 2605}
2606
2607static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2608{
2609 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2610
2611 save->selector = vmcs_read16(sf->selector);
2612 save->base = vmcs_readl(sf->base);
2613 save->limit = vmcs_read32(sf->limit);
2614 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2615 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2616 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2617 vmcs_write32(sf->limit, 0xffff);
2618 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2619 if (save->base & 0xf)
2620 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2621 " aligned when entering protected mode (seg=%d)",
2622 seg);
6aa8b732
AK		 2623}
2624
2625static void enter_rmode(struct kvm_vcpu *vcpu)
2626{
2627 unsigned long flags;
a89a8fb9 2628 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2629
3a624e29
NK		 2630 if (enable_unrestricted_guest)
2631 return;
2632
a89a8fb9 2633 vmx->emulation_required = 1;
7ffd92c5 2634 vmx->rmode.vm86_active = 1;
6aa8b732 2635
776e58ea
GN		 2636 /*
2637 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2638 * vcpu. Call it here with phys address pointing 16M below 4G.
2639 */
2640 if (!vcpu->kvm->arch.tss_addr) {
2641 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2642 "called before entering vcpu\n");
2643 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2644 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2645 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2646 }
2647
2fb92db1
AK		 2648 vmx_segment_cache_clear(vmx);
2649
d0ba64f9 2650 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2651 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2652 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2653
7ffd92c5 2654 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2655 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2656
7ffd92c5 2657 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2658 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2659
2660 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2661 vmx->rmode.save_rflags = flags;
6aa8b732 2662
053de044 2663 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2664
2665 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2666 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2667 update_exception_bitmap(vcpu);
2668
a89a8fb9
MG		 2669 if (emulate_invalid_guest_state)
2670 goto continue_rmode;
2671
6aa8b732
AK		 2672 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2673 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2674 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2675
2676 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2677 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2678 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2679 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2680 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2681
7ffd92c5
AK		 2682 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2683 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2684 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2685 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2686
a89a8fb9 2687continue_rmode:
8668a3c4 2688 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2689}
2690
401d10de
AS		 2691static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2692{
2693 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2694 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2695
2696 if (!msr)
2697 return;
401d10de 2698
44ea2b17
AK		 2699 /*
2700 * Force kernel_gs_base reloading before EFER changes, as control
2701 * of this msr depends on is_long_mode().
2702 */
2703 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2704 vcpu->arch.efer = efer;
401d10de
AS		 2705 if (efer & EFER_LMA) {
2706 vmcs_write32(VM_ENTRY_CONTROLS,
2707 vmcs_read32(VM_ENTRY_CONTROLS) |
2708 VM_ENTRY_IA32E_MODE);
2709 msr->data = efer;
2710 } else {
2711 vmcs_write32(VM_ENTRY_CONTROLS,
2712 vmcs_read32(VM_ENTRY_CONTROLS) &
2713 ~VM_ENTRY_IA32E_MODE);
2714
2715 msr->data = efer & ~EFER_LME;
2716 }
2717 setup_msrs(vmx);
2718}
2719
05b3e0c2 2720#ifdef CONFIG_X86_64
6aa8b732
AK		 2721
2722static void enter_lmode(struct kvm_vcpu *vcpu)
2723{
2724 u32 guest_tr_ar;
2725
2fb92db1
AK		 2726 vmx_segment_cache_clear(to_vmx(vcpu));
2727
6aa8b732
AK		 2728 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2729 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2730 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2731 __func__);
6aa8b732
AK		 2732 vmcs_write32(GUEST_TR_AR_BYTES,
2733 (guest_tr_ar & ~AR_TYPE_MASK)
2734 | AR_TYPE_BUSY_64_TSS);
2735 }
da38f438 2736 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2737}
2738
2739static void exit_lmode(struct kvm_vcpu *vcpu)
2740{
6aa8b732
AK		 2741 vmcs_write32(VM_ENTRY_CONTROLS,
2742 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2743 & ~VM_ENTRY_IA32E_MODE);
da38f438 2744 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2745}
2746
2747#endif
2748
2384d2b3
SY		 2749static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2750{
b9d762fa 2751 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2752 if (enable_ept) {
2753 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2754 return;
4e1096d2 2755 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2756 }
2384d2b3
SY		 2757}
2758
e8467fda
AK		 2759static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2760{
2761 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2762
2763 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2764 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2765}
2766
aff48baa
AK		 2767static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2768{
2769 if (enable_ept && is_paging(vcpu))
2770 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2771 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2772}
2773
25c4c276 2774static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2775{
fc78f519
AK		 2776 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2777
2778 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2779 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2780}
2781
1439442c
SY		 2782static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2783{
6de4f3ad
AK		 2784 if (!test_bit(VCPU_EXREG_PDPTR,
2785 (unsigned long *)&vcpu->arch.regs_dirty))
2786 return;
2787
1439442c 2788 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2789 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2790 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2791 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2792 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2793 }
2794}
2795
8f5d549f
AK		 2796static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2797{
2798 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2799 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2800 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2801 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2802 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2803 }
6de4f3ad
AK		 2804
2805 __set_bit(VCPU_EXREG_PDPTR,
2806 (unsigned long *)&vcpu->arch.regs_avail);
2807 __set_bit(VCPU_EXREG_PDPTR,
2808 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2809}
2810
5e1746d6 2811static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2812
2813static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2814 unsigned long cr0,
2815 struct kvm_vcpu *vcpu)
2816{
5233dd51
MT		 2817 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2818 vmx_decache_cr3(vcpu);
1439442c
SY		 2819 if (!(cr0 & X86_CR0_PG)) {
2820 /* From paging/starting to nonpaging */
2821 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2822 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2823 (CPU_BASED_CR3_LOAD_EXITING |
2824 CPU_BASED_CR3_STORE_EXITING));
2825 vcpu->arch.cr0 = cr0;
fc78f519 2826 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2827 } else if (!is_paging(vcpu)) {
2828 /* From nonpaging to paging */
2829 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2830 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2831 ~(CPU_BASED_CR3_LOAD_EXITING |
2832 CPU_BASED_CR3_STORE_EXITING));
2833 vcpu->arch.cr0 = cr0;
fc78f519 2834 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2835 }
95eb84a7
SY		 2836
2837 if (!(cr0 & X86_CR0_WP))
2838 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2839}
2840
6aa8b732
AK		 2841static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2842{
7ffd92c5 2843 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2844 unsigned long hw_cr0;
2845
2846 if (enable_unrestricted_guest)
2847 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2848 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2849 else
2850 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2851
7ffd92c5 2852 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2853 enter_pmode(vcpu);
2854
7ffd92c5 2855 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2856 enter_rmode(vcpu);
2857
05b3e0c2 2858#ifdef CONFIG_X86_64
f6801dff 2859 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2860 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2861 enter_lmode(vcpu);
707d92fa 2862 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2863 exit_lmode(vcpu);
2864 }
2865#endif
2866
089d034e 2867 if (enable_ept)
1439442c
SY		 2868 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2869
02daab21 2870 if (!vcpu->fpu_active)
81231c69 2871 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2872
6aa8b732 2873 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2874 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2875 vcpu->arch.cr0 = cr0;
69c73028 2876 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2877}
2878
1439442c
SY		 2879static u64 construct_eptp(unsigned long root_hpa)
2880{
2881 u64 eptp;
2882
2883 /* TODO write the value reading from MSR */
2884 eptp = VMX_EPT_DEFAULT_MT |
2885 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2886 eptp |= (root_hpa & PAGE_MASK);
2887
2888 return eptp;
2889}
2890
6aa8b732
AK		 2891static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2892{
1439442c
SY		 2893 unsigned long guest_cr3;
2894 u64 eptp;
2895
2896 guest_cr3 = cr3;
089d034e 2897 if (enable_ept) {
1439442c
SY		 2898 eptp = construct_eptp(cr3);
2899 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2900 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2901 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2902 ept_load_pdptrs(vcpu);
1439442c
SY		 2903 }
2904
2384d2b3 2905 vmx_flush_tlb(vcpu);
1439442c 2906 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2907}
2908
5e1746d6 2909static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2910{
7ffd92c5 2911 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2912 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2913
5e1746d6
NHE		 2914 if (cr4 & X86_CR4_VMXE) {
2915 /*
2916 * To use VMXON (and later other VMX instructions), a guest
2917 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2918 * So basically the check on whether to allow nested VMX
2919 * is here.
2920 */
2921 if (!nested_vmx_allowed(vcpu))
2922 return 1;
2923 } else if (to_vmx(vcpu)->nested.vmxon)
2924 return 1;
2925
ad312c7c 2926 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2927 if (enable_ept) {
2928 if (!is_paging(vcpu)) {
2929 hw_cr4 &= ~X86_CR4_PAE;
2930 hw_cr4 |= X86_CR4_PSE;
2931 } else if (!(cr4 & X86_CR4_PAE)) {
2932 hw_cr4 &= ~X86_CR4_PAE;
2933 }
2934 }
1439442c
SY		 2935
2936 vmcs_writel(CR4_READ_SHADOW, cr4);
2937 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2938 return 0;
6aa8b732
AK		 2939}
2940
6aa8b732
AK		 2941static void vmx_get_segment(struct kvm_vcpu *vcpu,
2942 struct kvm_segment *var, int seg)
2943{
a9179499 2944 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2945 struct kvm_save_segment *save;
6aa8b732
AK		 2946 u32 ar;
2947
a9179499
AK		 2948 if (vmx->rmode.vm86_active
2949 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2950 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2951 || seg == VCPU_SREG_GS)
2952 && !emulate_invalid_guest_state) {
2953 switch (seg) {
2954 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2955 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2956 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2957 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2958 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2959 default: BUG();
2960 }
2961 var->selector = save->selector;
2962 var->base = save->base;
2963 var->limit = save->limit;
2964 ar = save->ar;
2965 if (seg == VCPU_SREG_TR
2fb92db1 2966 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2967 goto use_saved_rmode_seg;
2968 }
2fb92db1
AK		 2969 var->base = vmx_read_guest_seg_base(vmx, seg);
2970 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2971 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2972 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2973use_saved_rmode_seg:
9fd4a3b7 2974 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2975 ar = 0;
2976 var->type = ar & 15;
2977 var->s = (ar >> 4) & 1;
2978 var->dpl = (ar >> 5) & 3;
2979 var->present = (ar >> 7) & 1;
2980 var->avl = (ar >> 12) & 1;
2981 var->l = (ar >> 13) & 1;
2982 var->db = (ar >> 14) & 1;
2983 var->g = (ar >> 15) & 1;
2984 var->unusable = (ar >> 16) & 1;
2985}
2986
a9179499
AK		 2987static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2988{
a9179499
AK		 2989 struct kvm_segment s;
2990
2991 if (to_vmx(vcpu)->rmode.vm86_active) {
2992 vmx_get_segment(vcpu, &s, seg);
2993 return s.base;
2994 }
2fb92db1 2995 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2996}
2997
69c73028 2998static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2999{
3eeb3288 3000 if (!is_protmode(vcpu))
2e4d2653
IE		 3001 return 0;
3002
f4c63e5d
AK		 3003 if (!is_long_mode(vcpu)
3004 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3005 return 3;
3006
2fb92db1 3007 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3008}
3009
69c73028
AK		 3010static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3011{
3012 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3013 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3014 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3015 }
3016 return to_vmx(vcpu)->cpl;
3017}
3018
3019
653e3108 3020static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3021{
6aa8b732
AK		 3022 u32 ar;
3023
653e3108 3024 if (var->unusable)
6aa8b732
AK		 3025 ar = 1 << 16;
3026 else {
3027 ar = var->type & 15;
3028 ar |= (var->s & 1) << 4;
3029 ar |= (var->dpl & 3) << 5;
3030 ar |= (var->present & 1) << 7;
3031 ar |= (var->avl & 1) << 12;
3032 ar |= (var->l & 1) << 13;
3033 ar |= (var->db & 1) << 14;
3034 ar |= (var->g & 1) << 15;
3035 }
f7fbf1fd
UL		 3036 if (ar == 0) /* a 0 value means unusable */
3037 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3038
3039 return ar;
3040}
3041
3042static void vmx_set_segment(struct kvm_vcpu *vcpu,
3043 struct kvm_segment *var, int seg)
3044{
7ffd92c5 3045 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3046 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3047 u32 ar;
3048
2fb92db1
AK		 3049 vmx_segment_cache_clear(vmx);
3050
7ffd92c5 3051 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3052 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3053 vmx->rmode.tr.selector = var->selector;
3054 vmx->rmode.tr.base = var->base;
3055 vmx->rmode.tr.limit = var->limit;
3056 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3057 return;
3058 }
3059 vmcs_writel(sf->base, var->base);
3060 vmcs_write32(sf->limit, var->limit);
3061 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3062 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3063 /*
3064 * Hack real-mode segments into vm86 compatibility.
3065 */
3066 if (var->base == 0xffff0000 && var->selector == 0xf000)
3067 vmcs_writel(sf->base, 0xf0000);
3068 ar = 0xf3;
3069 } else
3070 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3071
3072 /*
3073 * Fix the "Accessed" bit in AR field of segment registers for older
3074 * qemu binaries.
3075 * IA32 arch specifies that at the time of processor reset the
3076 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3077 * is setting it to 0 in the usedland code. This causes invalid guest
3078 * state vmexit when "unrestricted guest" mode is turned on.
3079 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3080 * tree. Newer qemu binaries with that qemu fix would not need this
3081 * kvm hack.
3082 */
3083 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3084 ar |= 0x1; /* Accessed */
3085
6aa8b732 3086 vmcs_write32(sf->ar_bytes, ar);
69c73028 3087 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3088}
3089
6aa8b732
AK		 3090static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3091{
2fb92db1 3092 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3093
3094 *db = (ar >> 14) & 1;
3095 *l = (ar >> 13) & 1;
3096}
3097
89a27f4d 3098static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3099{
89a27f4d
GN		 3100 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3101 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3102}
3103
89a27f4d 3104static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3105{
89a27f4d
GN		 3106 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3107 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3108}
3109
89a27f4d 3110static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3111{
89a27f4d
GN		 3112 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3113 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3114}
3115
89a27f4d 3116static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3117{
89a27f4d
GN		 3118 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3119 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3120}
3121
648dfaa7
MG		 3122static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3123{
3124 struct kvm_segment var;
3125 u32 ar;
3126
3127 vmx_get_segment(vcpu, &var, seg);
3128 ar = vmx_segment_access_rights(&var);
3129
3130 if (var.base != (var.selector << 4))
3131 return false;
3132 if (var.limit != 0xffff)
3133 return false;
3134 if (ar != 0xf3)
3135 return false;
3136
3137 return true;
3138}
3139
3140static bool code_segment_valid(struct kvm_vcpu *vcpu)
3141{
3142 struct kvm_segment cs;
3143 unsigned int cs_rpl;
3144
3145 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3146 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3147
1872a3f4
AK		 3148 if (cs.unusable)
3149 return false;
648dfaa7
MG		 3150 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3151 return false;
3152 if (!cs.s)
3153 return false;
1872a3f4 3154 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3155 if (cs.dpl > cs_rpl)
3156 return false;
1872a3f4 3157 } else {
648dfaa7
MG		 3158 if (cs.dpl != cs_rpl)
3159 return false;
3160 }
3161 if (!cs.present)
3162 return false;
3163
3164 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3165 return true;
3166}
3167
3168static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3169{
3170 struct kvm_segment ss;
3171 unsigned int ss_rpl;
3172
3173 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3174 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3175
1872a3f4
AK		 3176 if (ss.unusable)
3177 return true;
3178 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3179 return false;
3180 if (!ss.s)
3181 return false;
3182 if (ss.dpl != ss_rpl) /* DPL != RPL */
3183 return false;
3184 if (!ss.present)
3185 return false;
3186
3187 return true;
3188}
3189
3190static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3191{
3192 struct kvm_segment var;
3193 unsigned int rpl;
3194
3195 vmx_get_segment(vcpu, &var, seg);
3196 rpl = var.selector & SELECTOR_RPL_MASK;
3197
1872a3f4
AK		 3198 if (var.unusable)
3199 return true;
648dfaa7
MG		 3200 if (!var.s)
3201 return false;
3202 if (!var.present)
3203 return false;
3204 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3205 if (var.dpl < rpl) /* DPL < RPL */
3206 return false;
3207 }
3208
3209 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3210 * rights flags
3211 */
3212 return true;
3213}
3214
3215static bool tr_valid(struct kvm_vcpu *vcpu)
3216{
3217 struct kvm_segment tr;
3218
3219 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3220
1872a3f4
AK		 3221 if (tr.unusable)
3222 return false;
648dfaa7
MG		 3223 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3224 return false;
1872a3f4 3225 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3226 return false;
3227 if (!tr.present)
3228 return false;
3229
3230 return true;
3231}
3232
3233static bool ldtr_valid(struct kvm_vcpu *vcpu)
3234{
3235 struct kvm_segment ldtr;
3236
3237 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3238
1872a3f4
AK		 3239 if (ldtr.unusable)
3240 return true;
648dfaa7
MG		 3241 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3242 return false;
3243 if (ldtr.type != 2)
3244 return false;
3245 if (!ldtr.present)
3246 return false;
3247
3248 return true;
3249}
3250
3251static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3252{
3253 struct kvm_segment cs, ss;
3254
3255 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3256 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3257
3258 return ((cs.selector & SELECTOR_RPL_MASK) ==
3259 (ss.selector & SELECTOR_RPL_MASK));
3260}
3261
3262/*
3263 * Check if guest state is valid. Returns true if valid, false if
3264 * not.
3265 * We assume that registers are always usable
3266 */
3267static bool guest_state_valid(struct kvm_vcpu *vcpu)
3268{
3269 /* real mode guest state checks */
3eeb3288 3270 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3271 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3272 return false;
3273 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3274 return false;
3275 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3276 return false;
3277 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3278 return false;
3279 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3280 return false;
3281 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3282 return false;
3283 } else {
3284 /* protected mode guest state checks */
3285 if (!cs_ss_rpl_check(vcpu))
3286 return false;
3287 if (!code_segment_valid(vcpu))
3288 return false;
3289 if (!stack_segment_valid(vcpu))
3290 return false;
3291 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3292 return false;
3293 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3294 return false;
3295 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3296 return false;
3297 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3298 return false;
3299 if (!tr_valid(vcpu))
3300 return false;
3301 if (!ldtr_valid(vcpu))
3302 return false;
3303 }
3304 /* TODO:
3305 * - Add checks on RIP
3306 * - Add checks on RFLAGS
3307 */
3308
3309 return true;
3310}
3311
d77c26fc 3312static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3313{
40dcaa9f 3314 gfn_t fn;
195aefde 3315 u16 data = 0;
40dcaa9f 3316 int r, idx, ret = 0;
6aa8b732 3317
40dcaa9f
XG		 3318 idx = srcu_read_lock(&kvm->srcu);
3319 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3320 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3321 if (r < 0)
10589a46 3322 goto out;
195aefde 3323 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3324 r = kvm_write_guest_page(kvm, fn++, &data,
3325 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3326 if (r < 0)
10589a46 3327 goto out;
195aefde
IE		 3328 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3329 if (r < 0)
10589a46 3330 goto out;
195aefde
IE		 3331 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3332 if (r < 0)
10589a46 3333 goto out;
195aefde 3334 data = ~0;
10589a46
MT		 3335 r = kvm_write_guest_page(kvm, fn, &data,
3336 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3337 sizeof(u8));
195aefde 3338 if (r < 0)
10589a46
MT		 3339 goto out;
3340
3341 ret = 1;
3342out:
40dcaa9f 3343 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3344 return ret;
6aa8b732
AK		 3345}
3346
b7ebfb05
SY		 3347static int init_rmode_identity_map(struct kvm *kvm)
3348{
40dcaa9f 3349 int i, idx, r, ret;
b7ebfb05
SY		 3350 pfn_t identity_map_pfn;
3351 u32 tmp;
3352
089d034e 3353 if (!enable_ept)
b7ebfb05
SY		 3354 return 1;
3355 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3356 printk(KERN_ERR "EPT: identity-mapping pagetable "
3357 "haven't been allocated!\n");
3358 return 0;
3359 }
3360 if (likely(kvm->arch.ept_identity_pagetable_done))
3361 return 1;
3362 ret = 0;
b927a3ce 3363 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3364 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3365 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3366 if (r < 0)
3367 goto out;
3368 /* Set up identity-mapping pagetable for EPT in real mode */
3369 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3370 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3371 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3372 r = kvm_write_guest_page(kvm, identity_map_pfn,
3373 &tmp, i * sizeof(tmp), sizeof(tmp));
3374 if (r < 0)
3375 goto out;
3376 }
3377 kvm->arch.ept_identity_pagetable_done = true;
3378 ret = 1;
3379out:
40dcaa9f 3380 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3381 return ret;
3382}
3383
6aa8b732
AK		 3384static void seg_setup(int seg)
3385{
3386 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3387 unsigned int ar;
6aa8b732
AK		 3388
3389 vmcs_write16(sf->selector, 0);
3390 vmcs_writel(sf->base, 0);
3391 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3392 if (enable_unrestricted_guest) {
3393 ar = 0x93;
3394 if (seg == VCPU_SREG_CS)
3395 ar |= 0x08; /* code segment */
3396 } else
3397 ar = 0xf3;
3398
3399 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3400}
3401
f78e0e2e
SY		 3402static int alloc_apic_access_page(struct kvm *kvm)
3403{
3404 struct kvm_userspace_memory_region kvm_userspace_mem;
3405 int r = 0;
3406
79fac95e 3407 mutex_lock(&kvm->slots_lock);
bfc6d222 3408 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3409 goto out;
3410 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3411 kvm_userspace_mem.flags = 0;
3412 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3413 kvm_userspace_mem.memory_size = PAGE_SIZE;
3414 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3415 if (r)
3416 goto out;
72dc67a6 3417
bfc6d222 3418 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3419out:
79fac95e 3420 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3421 return r;
3422}
3423
b7ebfb05
SY		 3424static int alloc_identity_pagetable(struct kvm *kvm)
3425{
3426 struct kvm_userspace_memory_region kvm_userspace_mem;
3427 int r = 0;
3428
79fac95e 3429 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3430 if (kvm->arch.ept_identity_pagetable)
3431 goto out;
3432 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3433 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3434 kvm_userspace_mem.guest_phys_addr =
3435 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3436 kvm_userspace_mem.memory_size = PAGE_SIZE;
3437 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3438 if (r)
3439 goto out;
3440
b7ebfb05 3441 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3442 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3443out:
79fac95e 3444 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3445 return r;
3446}
3447
2384d2b3
SY		 3448static void allocate_vpid(struct vcpu_vmx *vmx)
3449{
3450 int vpid;
3451
3452 vmx->vpid = 0;
919818ab 3453 if (!enable_vpid)
2384d2b3
SY		 3454 return;
3455 spin_lock(&vmx_vpid_lock);
3456 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3457 if (vpid < VMX_NR_VPIDS) {
3458 vmx->vpid = vpid;
3459 __set_bit(vpid, vmx_vpid_bitmap);
3460 }
3461 spin_unlock(&vmx_vpid_lock);
3462}
3463
cdbecfc3
LJ		 3464static void free_vpid(struct vcpu_vmx *vmx)
3465{
3466 if (!enable_vpid)
3467 return;
3468 spin_lock(&vmx_vpid_lock);
3469 if (vmx->vpid != 0)
3470 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3471 spin_unlock(&vmx_vpid_lock);
3472}
3473
5897297b 3474static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3475{
3e7c73e9 3476 int f = sizeof(unsigned long);
25c5f225
SY		 3477
3478 if (!cpu_has_vmx_msr_bitmap())
3479 return;
3480
3481 /*
3482 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3483 * have the write-low and read-high bitmap offsets the wrong way round.
3484 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3485 */
25c5f225 3486 if (msr <= 0x1fff) {
3e7c73e9
AK		 3487 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3488 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3489 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3490 msr &= 0x1fff;
3e7c73e9
AK		 3491 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3492 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3493 }
25c5f225
SY		 3494}
3495
5897297b
AK		 3496static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3497{
3498 if (!longmode_only)
3499 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3500 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3501}
3502
a3a8ff8e
NHE		 3503/*
3504 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3505 * will not change in the lifetime of the guest.
3506 * Note that host-state that does change is set elsewhere. E.g., host-state
3507 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3508 */
3509static void vmx_set_constant_host_state(void)
3510{
3511 u32 low32, high32;
3512 unsigned long tmpl;
3513 struct desc_ptr dt;
3514
3515 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3516 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3517 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3518
3519 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3520 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3521 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3522 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3523 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3524
3525 native_store_idt(&dt);
3526 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3527
3528 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3529 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3530
3531 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3532 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3533 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3534 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3535
3536 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3537 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3538 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3539 }
3540}
3541
bf8179a0
NHE		 3542static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3543{
3544 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3545 if (enable_ept)
3546 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3547 if (is_guest_mode(&vmx->vcpu))
3548 vmx->vcpu.arch.cr4_guest_owned_bits &=
3549 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3550 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3551}
3552
3553static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3554{
3555 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3556 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3557 exec_control &= ~CPU_BASED_TPR_SHADOW;
3558#ifdef CONFIG_X86_64
3559 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3560 CPU_BASED_CR8_LOAD_EXITING;
3561#endif
3562 }
3563 if (!enable_ept)
3564 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3565 CPU_BASED_CR3_LOAD_EXITING |
3566 CPU_BASED_INVLPG_EXITING;
3567 return exec_control;
3568}
3569
3570static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3571{
3572 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3573 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3574 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3575 if (vmx->vpid == 0)
3576 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3577 if (!enable_ept) {
3578 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3579 enable_unrestricted_guest = 0;
3580 }
3581 if (!enable_unrestricted_guest)
3582 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3583 if (!ple_gap)
3584 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3585 return exec_control;
3586}
3587
6aa8b732
AK		 3588/*
3589 * Sets up the vmcs for emulated real mode.
3590 */
8b9cf98c 3591static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3592{
6aa8b732 3593 unsigned long a;
6aa8b732 3594 int i;
6aa8b732 3595
6aa8b732 3596 /* I/O */
3e7c73e9
AK		 3597 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3598 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3599
25c5f225 3600 if (cpu_has_vmx_msr_bitmap())
5897297b 3601 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3602
6aa8b732
AK		 3603 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3604
6aa8b732 3605 /* Control */
1c3d14fe
YS		 3606 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3607 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3608
bf8179a0 3609 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3610
83ff3b9d 3611 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3612 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3613 vmx_secondary_exec_control(vmx));
83ff3b9d 3614 }
f78e0e2e 3615
4b8d54f9
ZE		 3616 if (ple_gap) {
3617 vmcs_write32(PLE_GAP, ple_gap);
3618 vmcs_write32(PLE_WINDOW, ple_window);
3619 }
3620
c7addb90
AK		 3621 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3622 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 3623 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3624
9581d442
AK		 3625 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3626 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3627 vmx_set_constant_host_state();
05b3e0c2 3628#ifdef CONFIG_X86_64
6aa8b732
AK		 3629 rdmsrl(MSR_FS_BASE, a);
3630 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3631 rdmsrl(MSR_GS_BASE, a);
3632 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3633#else
3634 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3635 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3636#endif
3637
2cc51560
ED		 3638 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3639 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3640 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3641 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3642 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3643
468d472f 3644 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3645 u32 msr_low, msr_high;
3646 u64 host_pat;
468d472f
SY		 3647 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3648 host_pat = msr_low | ((u64) msr_high << 32);
3649 /* Write the default value follow host pat */
3650 vmcs_write64(GUEST_IA32_PAT, host_pat);
3651 /* Keep arch.pat sync with GUEST_IA32_PAT */
3652 vmx->vcpu.arch.pat = host_pat;
3653 }
3654
6aa8b732
AK		 3655 for (i = 0; i < NR_VMX_MSR; ++i) {
3656 u32 index = vmx_msr_index[i];
3657 u32 data_low, data_high;
a2fa3e9f 3658 int j = vmx->nmsrs;
6aa8b732
AK		 3659
3660 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3661 continue;
432bd6cb
AK		 3662 if (wrmsr_safe(index, data_low, data_high) < 0)
3663 continue;
26bb0981
AK		 3664 vmx->guest_msrs[j].index = i;
3665 vmx->guest_msrs[j].data = 0;
d5696725 3666 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3667 ++vmx->nmsrs;
6aa8b732 3668 }
6aa8b732 3669
1c3d14fe 3670 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3671
3672 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3673 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3674
e00c8cf2 3675 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3676 set_cr4_guest_host_mask(vmx);
e00c8cf2 3677
99e3e30a 3678 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3679
e00c8cf2
AK		 3680 return 0;
3681}
3682
3683static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3684{
3685 struct vcpu_vmx *vmx = to_vmx(vcpu);
3686 u64 msr;
4b9d3a04 3687 int ret;
e00c8cf2 3688
5fdbf976 3689 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3690
7ffd92c5 3691 vmx->rmode.vm86_active = 0;
e00c8cf2 3692
3b86cd99
JK		 3693 vmx->soft_vnmi_blocked = 0;
3694
ad312c7c 3695 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3696 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3697 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3698 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3699 msr |= MSR_IA32_APICBASE_BSP;
3700 kvm_set_apic_base(&vmx->vcpu, msr);
3701
10ab25cd
JK		 3702 ret = fx_init(&vmx->vcpu);
3703 if (ret != 0)
3704 goto out;
e00c8cf2 3705
2fb92db1
AK		 3706 vmx_segment_cache_clear(vmx);
3707
5706be0d 3708 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3709 /*
3710 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3711 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3712 */
c5af89b6 3713 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3714 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3715 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3716 } else {
ad312c7c
ZX		 3717 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3718 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3719 }
e00c8cf2
AK		 3720
3721 seg_setup(VCPU_SREG_DS);
3722 seg_setup(VCPU_SREG_ES);
3723 seg_setup(VCPU_SREG_FS);
3724 seg_setup(VCPU_SREG_GS);
3725 seg_setup(VCPU_SREG_SS);
3726
3727 vmcs_write16(GUEST_TR_SELECTOR, 0);
3728 vmcs_writel(GUEST_TR_BASE, 0);
3729 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3730 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3731
3732 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3733 vmcs_writel(GUEST_LDTR_BASE, 0);
3734 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3735 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3736
3737 vmcs_write32(GUEST_SYSENTER_CS, 0);
3738 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3739 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3740
3741 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3742 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3743 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3744 else
5fdbf976
MT		 3745 kvm_rip_write(vcpu, 0);
3746 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3747
e00c8cf2
AK		 3748 vmcs_writel(GUEST_DR7, 0x400);
3749
3750 vmcs_writel(GUEST_GDTR_BASE, 0);
3751 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3752
3753 vmcs_writel(GUEST_IDTR_BASE, 0);
3754 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3755
443381a8 3756 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3757 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3758 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3759
e00c8cf2
AK		 3760 /* Special registers */
3761 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3762
3763 setup_msrs(vmx);
3764
6aa8b732
AK		 3765 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3766
f78e0e2e
SY		 3767 if (cpu_has_vmx_tpr_shadow()) {
3768 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3769 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3770 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3771 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3772 vmcs_write32(TPR_THRESHOLD, 0);
3773 }
3774
3775 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3776 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3777 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3778
2384d2b3
SY		 3779 if (vmx->vpid != 0)
3780 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3781
fa40052c 3782 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3783 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3784 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3785 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3786 vmx_fpu_activate(&vmx->vcpu);
3787 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3788
b9d762fa 3789 vpid_sync_context(vmx);
2384d2b3 3790
3200f405 3791 ret = 0;
6aa8b732 3792
a89a8fb9
MG		 3793 /* HACK: Don't enable emulation on guest boot/reset */
3794 vmx->emulation_required = 0;
3795
6aa8b732
AK		 3796out:
3797 return ret;
3798}
3799
b6f1250e
NHE		 3800/*
3801 * In nested virtualization, check if L1 asked to exit on external interrupts.
3802 * For most existing hypervisors, this will always return true.
3803 */
3804static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3805{
3806 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3807 PIN_BASED_EXT_INTR_MASK;
3808}
3809
3b86cd99
JK		 3810static void enable_irq_window(struct kvm_vcpu *vcpu)
3811{
3812 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3813 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3814 /* We can get here when nested_run_pending caused
3815 * vmx_interrupt_allowed() to return false. In this case, do
3816 * nothing - the interrupt will be injected later.
3817 */
3818 return;
3b86cd99
JK		 3819
3820 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3821 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3822 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3823}
3824
3825static void enable_nmi_window(struct kvm_vcpu *vcpu)
3826{
3827 u32 cpu_based_vm_exec_control;
3828
3829 if (!cpu_has_virtual_nmis()) {
3830 enable_irq_window(vcpu);
3831 return;
3832 }
3833
30bd0c4c
AK		 3834 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3835 enable_irq_window(vcpu);
3836 return;
3837 }
3b86cd99
JK		 3838 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3839 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3840 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3841}
3842
66fd3f7f 3843static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3844{
9c8cba37 3845 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3846 uint32_t intr;
3847 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3848
229456fc 3849 trace_kvm_inj_virq(irq);
2714d1d3 3850
fa89a817 3851 ++vcpu->stat.irq_injections;
7ffd92c5 3852 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3853 int inc_eip = 0;
3854 if (vcpu->arch.interrupt.soft)
3855 inc_eip = vcpu->arch.event_exit_inst_len;
3856 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3857 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3858 return;
3859 }
66fd3f7f
GN		 3860 intr = irq | INTR_INFO_VALID_MASK;
3861 if (vcpu->arch.interrupt.soft) {
3862 intr |= INTR_TYPE_SOFT_INTR;
3863 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3864 vmx->vcpu.arch.event_exit_inst_len);
3865 } else
3866 intr |= INTR_TYPE_EXT_INTR;
3867 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3868 vmx_clear_hlt(vcpu);
85f455f7
ED		 3869}
3870
f08864b4
SY		 3871static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3872{
66a5a347
JK		 3873 struct vcpu_vmx *vmx = to_vmx(vcpu);
3874
0b6ac343
NHE		 3875 if (is_guest_mode(vcpu))
3876 return;
3877
3b86cd99
JK		 3878 if (!cpu_has_virtual_nmis()) {
3879 /*
3880 * Tracking the NMI-blocked state in software is built upon
3881 * finding the next open IRQ window. This, in turn, depends on
3882 * well-behaving guests: They have to keep IRQs disabled at
3883 * least as long as the NMI handler runs. Otherwise we may
3884 * cause NMI nesting, maybe breaking the guest. But as this is
3885 * highly unlikely, we can live with the residual risk.
3886 */
3887 vmx->soft_vnmi_blocked = 1;
3888 vmx->vnmi_blocked_time = 0;
3889 }
3890
487b391d 3891 ++vcpu->stat.nmi_injections;
9d58b931 3892 vmx->nmi_known_unmasked = false;
7ffd92c5 3893 if (vmx->rmode.vm86_active) {
71f9833b 3894 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3895 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3896 return;
3897 }
f08864b4
SY		 3898 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3899 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3900 vmx_clear_hlt(vcpu);
f08864b4
SY		 3901}
3902
c4282df9 3903static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3904{
3b86cd99 3905 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3906 return 0;
33f089ca 3907
c4282df9 3908 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3909 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3910 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3911}
3912
3cfc3092
JK		 3913static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3914{
3915 if (!cpu_has_virtual_nmis())
3916 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3917 if (to_vmx(vcpu)->nmi_known_unmasked)
3918 return false;
c332c83a 3919 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3920}
3921
3922static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3923{
3924 struct vcpu_vmx *vmx = to_vmx(vcpu);
3925
3926 if (!cpu_has_virtual_nmis()) {
3927 if (vmx->soft_vnmi_blocked != masked) {
3928 vmx->soft_vnmi_blocked = masked;
3929 vmx->vnmi_blocked_time = 0;
3930 }
3931 } else {
9d58b931 3932 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3933 if (masked)
3934 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3935 GUEST_INTR_STATE_NMI);
3936 else
3937 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3938 GUEST_INTR_STATE_NMI);
3939 }
3940}
3941
78646121
GN		 3942static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3943{
b6f1250e
NHE		 3944 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3945 struct vmcs12 *vmcs12;
3946 if (to_vmx(vcpu)->nested.nested_run_pending)
3947 return 0;
3948 nested_vmx_vmexit(vcpu);
3949 vmcs12 = get_vmcs12(vcpu);
3950 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3951 vmcs12->vm_exit_intr_info = 0;
3952 /* fall through to normal code, but now in L1, not L2 */
3953 }
3954
c4282df9
GN		 3955 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3956 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3957 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3958}
3959
cbc94022
IE		 3960static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3961{
3962 int ret;
3963 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3964 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3965 .guest_phys_addr = addr,
3966 .memory_size = PAGE_SIZE * 3,
3967 .flags = 0,
3968 };
3969
3970 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3971 if (ret)
3972 return ret;
bfc6d222 3973 kvm->arch.tss_addr = addr;
93ea5388
GN		 3974 if (!init_rmode_tss(kvm))
3975 return -ENOMEM;
3976
cbc94022
IE		 3977 return 0;
3978}
3979
6aa8b732
AK		 3980static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3981 int vec, u32 err_code)
3982{
b3f37707
NK		 3983 /*
3984 * Instruction with address size override prefix opcode 0x67
3985 * Cause the #SS fault with 0 error code in VM86 mode.
3986 */
3987 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3988 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3989 return 1;
77ab6db0
JK		 3990 /*
3991 * Forward all other exceptions that are valid in real mode.
3992 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3993 * the required debugging infrastructure rework.
3994 */
3995 switch (vec) {
77ab6db0 3996 case DB_VECTOR:
d0bfb940
JK		 3997 if (vcpu->guest_debug &
3998 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3999 return 0;
4000 kvm_queue_exception(vcpu, vec);
4001 return 1;
77ab6db0 4002 case BP_VECTOR:
c573cd22
JK		 4003 /*
4004 * Update instruction length as we may reinject the exception
4005 * from user space while in guest debugging mode.
4006 */
4007 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4008 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4009 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4010 return 0;
4011 /* fall through */
4012 case DE_VECTOR:
77ab6db0
JK		 4013 case OF_VECTOR:
4014 case BR_VECTOR:
4015 case UD_VECTOR:
4016 case DF_VECTOR:
4017 case SS_VECTOR:
4018 case GP_VECTOR:
4019 case MF_VECTOR:
4020 kvm_queue_exception(vcpu, vec);
4021 return 1;
4022 }
6aa8b732
AK		 4023 return 0;
4024}
4025
a0861c02
AK		 4026/*
4027 * Trigger machine check on the host. We assume all the MSRs are already set up
4028 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4029 * We pass a fake environment to the machine check handler because we want
4030 * the guest to be always treated like user space, no matter what context
4031 * it used internally.
4032 */
4033static void kvm_machine_check(void)
4034{
4035#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4036 struct pt_regs regs = {
4037 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4038 .flags = X86_EFLAGS_IF,
4039 };
4040
4041 do_machine_check(&regs, 0);
4042#endif
4043}
4044
851ba692 4045static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4046{
4047 /* already handled by vcpu_run */
4048 return 1;
4049}
4050
851ba692 4051static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4052{
1155f76a 4053 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4054 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4055 u32 intr_info, ex_no, error_code;
42dbaa5a 4056 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4057 u32 vect_info;
4058 enum emulation_result er;
4059
1155f76a 4060 vect_info = vmx->idt_vectoring_info;
88786475 4061 intr_info = vmx->exit_intr_info;
6aa8b732 4062
a0861c02 4063 if (is_machine_check(intr_info))
851ba692 4064 return handle_machine_check(vcpu);
a0861c02 4065
6aa8b732 4066 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4067 !is_page_fault(intr_info)) {
4068 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4069 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4070 vcpu->run->internal.ndata = 2;
4071 vcpu->run->internal.data[0] = vect_info;
4072 vcpu->run->internal.data[1] = intr_info;
4073 return 0;
4074 }
6aa8b732 4075
e4a41889 4076 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4077 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4078
4079 if (is_no_device(intr_info)) {
5fd86fcf 4080 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4081 return 1;
4082 }
4083
7aa81cc0 4084 if (is_invalid_opcode(intr_info)) {
51d8b661 4085 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4086 if (er != EMULATE_DONE)
7ee5d940 4087 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4088 return 1;
4089 }
4090
6aa8b732 4091 error_code = 0;
2e11384c 4092 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4093 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4094 if (is_page_fault(intr_info)) {
1439442c 4095 /* EPT won't cause page fault directly */
089d034e 4096 if (enable_ept)
1439442c 4097 BUG();
6aa8b732 4098 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4099 trace_kvm_page_fault(cr2, error_code);
4100
3298b75c 4101 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4102 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4103 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4104 }
4105
7ffd92c5 4106 if (vmx->rmode.vm86_active &&
6aa8b732 4107 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4108 error_code)) {
ad312c7c
ZX		 4109 if (vcpu->arch.halt_request) {
4110 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4111 return kvm_emulate_halt(vcpu);
4112 }
6aa8b732 4113 return 1;
72d6e5a0 4114 }
6aa8b732 4115
d0bfb940 4116 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4117 switch (ex_no) {
4118 case DB_VECTOR:
4119 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4120 if (!(vcpu->guest_debug &
4121 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4122 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4123 kvm_queue_exception(vcpu, DB_VECTOR);
4124 return 1;
4125 }
4126 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4127 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4128 /* fall through */
4129 case BP_VECTOR:
c573cd22
JK		 4130 /*
4131 * Update instruction length as we may reinject #BP from
4132 * user space while in guest debugging mode. Reading it for
4133 * #DB as well causes no harm, it is not used in that case.
4134 */
4135 vmx->vcpu.arch.event_exit_inst_len =
4136 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4137 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4138 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4139 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4140 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4141 break;
4142 default:
d0bfb940
JK		 4143 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4144 kvm_run->ex.exception = ex_no;
4145 kvm_run->ex.error_code = error_code;
42dbaa5a 4146 break;
6aa8b732 4147 }
6aa8b732
AK		 4148 return 0;
4149}
4150
851ba692 4151static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4152{
1165f5fe 4153 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4154 return 1;
4155}
4156
851ba692 4157static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4158{
851ba692 4159 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4160 return 0;
4161}
6aa8b732 4162
851ba692 4163static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4164{
bfdaab09 4165 unsigned long exit_qualification;
34c33d16 4166 int size, in, string;
039576c0 4167 unsigned port;
6aa8b732 4168
bfdaab09 4169 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4170 string = (exit_qualification & 16) != 0;
cf8f70bf 4171 in = (exit_qualification & 8) != 0;
e70669ab 4172
cf8f70bf 4173 ++vcpu->stat.io_exits;
e70669ab 4174
cf8f70bf 4175 if (string || in)
51d8b661 4176 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4177
cf8f70bf
GN		 4178 port = exit_qualification >> 16;
4179 size = (exit_qualification & 7) + 1;
e93f36bc 4180 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4181
4182 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4183}
4184
102d8325
IM		 4185static void
4186vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4187{
4188 /*
4189 * Patch in the VMCALL instruction:
4190 */
4191 hypercall[0] = 0x0f;
4192 hypercall[1] = 0x01;
4193 hypercall[2] = 0xc1;
102d8325
IM		 4194}
4195
eeadf9e7
NHE		 4196/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4197static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4198{
4199 if (to_vmx(vcpu)->nested.vmxon &&
4200 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4201 return 1;
4202
4203 if (is_guest_mode(vcpu)) {
4204 /*
4205 * We get here when L2 changed cr0 in a way that did not change
4206 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4207 * but did change L0 shadowed bits. This can currently happen
4208 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4209 * loading) while pretending to allow the guest to change it.
4210 */
4211 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4212 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4213 return 1;
4214 vmcs_writel(CR0_READ_SHADOW, val);
4215 return 0;
4216 } else
4217 return kvm_set_cr0(vcpu, val);
4218}
4219
4220static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4221{
4222 if (is_guest_mode(vcpu)) {
4223 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4224 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4225 return 1;
4226 vmcs_writel(CR4_READ_SHADOW, val);
4227 return 0;
4228 } else
4229 return kvm_set_cr4(vcpu, val);
4230}
4231
4232/* called to set cr0 as approriate for clts instruction exit. */
4233static void handle_clts(struct kvm_vcpu *vcpu)
4234{
4235 if (is_guest_mode(vcpu)) {
4236 /*
4237 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4238 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4239 * just pretend it's off (also in arch.cr0 for fpu_activate).
4240 */
4241 vmcs_writel(CR0_READ_SHADOW,
4242 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4243 vcpu->arch.cr0 &= ~X86_CR0_TS;
4244 } else
4245 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4246}
4247
851ba692 4248static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4249{
229456fc 4250 unsigned long exit_qualification, val;
6aa8b732
AK		 4251 int cr;
4252 int reg;
49a9b07e 4253 int err;
6aa8b732 4254
bfdaab09 4255 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4256 cr = exit_qualification & 15;
4257 reg = (exit_qualification >> 8) & 15;
4258 switch ((exit_qualification >> 4) & 3) {
4259 case 0: /* mov to cr */
229456fc
MT		 4260 val = kvm_register_read(vcpu, reg);
4261 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4262 switch (cr) {
4263 case 0:
eeadf9e7 4264 err = handle_set_cr0(vcpu, val);
db8fcefa 4265 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4266 return 1;
4267 case 3:
2390218b 4268 err = kvm_set_cr3(vcpu, val);
db8fcefa 4269 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4270 return 1;
4271 case 4:
eeadf9e7 4272 err = handle_set_cr4(vcpu, val);
db8fcefa 4273 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4274 return 1;
0a5fff19
GN		 4275 case 8: {
4276 u8 cr8_prev = kvm_get_cr8(vcpu);
4277 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4278 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4279 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4280 if (irqchip_in_kernel(vcpu->kvm))
4281 return 1;
4282 if (cr8_prev <= cr8)
4283 return 1;
851ba692 4284 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4285 return 0;
4286 }
6aa8b732
AK		 4287 };
4288 break;
25c4c276 4289 case 2: /* clts */
eeadf9e7 4290 handle_clts(vcpu);
4d4ec087 4291 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4292 skip_emulated_instruction(vcpu);
6b52d186 4293 vmx_fpu_activate(vcpu);
25c4c276 4294 return 1;
6aa8b732
AK		 4295 case 1: /*mov from cr*/
4296 switch (cr) {
4297 case 3:
9f8fe504
AK		 4298 val = kvm_read_cr3(vcpu);
4299 kvm_register_write(vcpu, reg, val);
4300 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4301 skip_emulated_instruction(vcpu);
4302 return 1;
4303 case 8:
229456fc
MT		 4304 val = kvm_get_cr8(vcpu);
4305 kvm_register_write(vcpu, reg, val);
4306 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4307 skip_emulated_instruction(vcpu);
4308 return 1;
4309 }
4310 break;
4311 case 3: /* lmsw */
a1f83a74 4312 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4313 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4314 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4315
4316 skip_emulated_instruction(vcpu);
4317 return 1;
4318 default:
4319 break;
4320 }
851ba692 4321 vcpu->run->exit_reason = 0;
f0242478 4322 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4323 (int)(exit_qualification >> 4) & 3, cr);
4324 return 0;
4325}
4326
851ba692 4327static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4328{
bfdaab09 4329 unsigned long exit_qualification;
6aa8b732
AK		 4330 int dr, reg;
4331
f2483415 4332 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4333 if (!kvm_require_cpl(vcpu, 0))
4334 return 1;
42dbaa5a
JK		 4335 dr = vmcs_readl(GUEST_DR7);
4336 if (dr & DR7_GD) {
4337 /*
4338 * As the vm-exit takes precedence over the debug trap, we
4339 * need to emulate the latter, either for the host or the
4340 * guest debugging itself.
4341 */
4342 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4343 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4344 vcpu->run->debug.arch.dr7 = dr;
4345 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4346 vmcs_readl(GUEST_CS_BASE) +
4347 vmcs_readl(GUEST_RIP);
851ba692
AK		 4348 vcpu->run->debug.arch.exception = DB_VECTOR;
4349 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4350 return 0;
4351 } else {
4352 vcpu->arch.dr7 &= ~DR7_GD;
4353 vcpu->arch.dr6 |= DR6_BD;
4354 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4355 kvm_queue_exception(vcpu, DB_VECTOR);
4356 return 1;
4357 }
4358 }
4359
bfdaab09 4360 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4361 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4362 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4363 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4364 unsigned long val;
4365 if (!kvm_get_dr(vcpu, dr, &val))
4366 kvm_register_write(vcpu, reg, val);
4367 } else
4368 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4369 skip_emulated_instruction(vcpu);
4370 return 1;
4371}
4372
020df079
GN		 4373static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4374{
4375 vmcs_writel(GUEST_DR7, val);
4376}
4377
851ba692 4378static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4379{
06465c5a
AK		 4380 kvm_emulate_cpuid(vcpu);
4381 return 1;
6aa8b732
AK		 4382}
4383
851ba692 4384static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4385{
ad312c7c 4386 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4387 u64 data;
4388
4389 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4390 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4391 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4392 return 1;
4393 }
4394
229456fc 4395 trace_kvm_msr_read(ecx, data);
2714d1d3 4396
6aa8b732 4397 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4398 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4399 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4400 skip_emulated_instruction(vcpu);
4401 return 1;
4402}
4403
851ba692 4404static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4405{
ad312c7c
ZX		 4406 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4407 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4408 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4409
4410 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4411 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4412 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4413 return 1;
4414 }
4415
59200273 4416 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4417 skip_emulated_instruction(vcpu);
4418 return 1;
4419}
4420
851ba692 4421static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4422{
3842d135 4423 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4424 return 1;
4425}
4426
851ba692 4427static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4428{
85f455f7
ED		 4429 u32 cpu_based_vm_exec_control;
4430
4431 /* clear pending irq */
4432 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4433 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4434 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4435
3842d135
AK		 4436 kvm_make_request(KVM_REQ_EVENT, vcpu);
4437
a26bf12a 4438 ++vcpu->stat.irq_window_exits;
2714d1d3 4439
c1150d8c
DL		 4440 /*
4441 * If the user space waits to inject interrupts, exit as soon as
4442 * possible
4443 */
8061823a 4444 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4445 vcpu->run->request_interrupt_window &&
8061823a 4446 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4447 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4448 return 0;
4449 }
6aa8b732
AK		 4450 return 1;
4451}
4452
851ba692 4453static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4454{
4455 skip_emulated_instruction(vcpu);
d3bef15f 4456 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4457}
4458
851ba692 4459static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4460{
510043da 4461 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4462 kvm_emulate_hypercall(vcpu);
4463 return 1;
c21415e8
IM		 4464}
4465
ec25d5e6
GN		 4466static int handle_invd(struct kvm_vcpu *vcpu)
4467{
51d8b661 4468 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4469}
4470
851ba692 4471static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4472{
f9c617f6 4473 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4474
4475 kvm_mmu_invlpg(vcpu, exit_qualification);
4476 skip_emulated_instruction(vcpu);
4477 return 1;
4478}
4479
851ba692 4480static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4481{
4482 skip_emulated_instruction(vcpu);
f5f48ee1 4483 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4484 return 1;
4485}
4486
2acf923e
DC		 4487static int handle_xsetbv(struct kvm_vcpu *vcpu)
4488{
4489 u64 new_bv = kvm_read_edx_eax(vcpu);
4490 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4491
4492 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4493 skip_emulated_instruction(vcpu);
4494 return 1;
4495}
4496
851ba692 4497static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4498{
51d8b661 4499 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4500}
4501
851ba692 4502static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4503{
60637aac 4504 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4505 unsigned long exit_qualification;
e269fb21
JK		 4506 bool has_error_code = false;
4507 u32 error_code = 0;
37817f29 4508 u16 tss_selector;
64a7ec06
GN		 4509 int reason, type, idt_v;
4510
4511 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4512 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4513
4514 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4515
4516 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4517 if (reason == TASK_SWITCH_GATE && idt_v) {
4518 switch (type) {
4519 case INTR_TYPE_NMI_INTR:
4520 vcpu->arch.nmi_injected = false;
654f06fc 4521 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4522 break;
4523 case INTR_TYPE_EXT_INTR:
66fd3f7f 4524 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4525 kvm_clear_interrupt_queue(vcpu);
4526 break;
4527 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4528 if (vmx->idt_vectoring_info &
4529 VECTORING_INFO_DELIVER_CODE_MASK) {
4530 has_error_code = true;
4531 error_code =
4532 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4533 }
4534 /* fall through */
64a7ec06
GN		 4535 case INTR_TYPE_SOFT_EXCEPTION:
4536 kvm_clear_exception_queue(vcpu);
4537 break;
4538 default:
4539 break;
4540 }
60637aac 4541 }
37817f29
IE		 4542 tss_selector = exit_qualification;
4543
64a7ec06
GN		 4544 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4545 type != INTR_TYPE_EXT_INTR &&
4546 type != INTR_TYPE_NMI_INTR))
4547 skip_emulated_instruction(vcpu);
4548
acb54517
GN		 4549 if (kvm_task_switch(vcpu, tss_selector, reason,
4550 has_error_code, error_code) == EMULATE_FAIL) {
4551 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4552 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4553 vcpu->run->internal.ndata = 0;
42dbaa5a 4554 return 0;
acb54517 4555 }
42dbaa5a
JK		 4556
4557 /* clear all local breakpoint enable flags */
4558 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4559
4560 /*
4561 * TODO: What about debug traps on tss switch?
4562 * Are we supposed to inject them and update dr6?
4563 */
4564
4565 return 1;
37817f29
IE		 4566}
4567
851ba692 4568static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4569{
f9c617f6 4570 unsigned long exit_qualification;
1439442c 4571 gpa_t gpa;
1439442c 4572 int gla_validity;
1439442c 4573
f9c617f6 4574 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4575
4576 if (exit_qualification & (1 << 6)) {
4577 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4578 return -EINVAL;
1439442c
SY		 4579 }
4580
4581 gla_validity = (exit_qualification >> 7) & 0x3;
4582 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4583 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4584 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4585 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4586 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4587 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4588 (long unsigned int)exit_qualification);
851ba692
AK		 4589 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4590 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4591 return 0;
1439442c
SY		 4592 }
4593
4594 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4595 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4596 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4597}
4598
68f89400
MT		 4599static u64 ept_rsvd_mask(u64 spte, int level)
4600{
4601 int i;
4602 u64 mask = 0;
4603
4604 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4605 mask |= (1ULL << i);
4606
4607 if (level > 2)
4608 /* bits 7:3 reserved */
4609 mask |= 0xf8;
4610 else if (level == 2) {
4611 if (spte & (1ULL << 7))
4612 /* 2MB ref, bits 20:12 reserved */
4613 mask |= 0x1ff000;
4614 else
4615 /* bits 6:3 reserved */
4616 mask |= 0x78;
4617 }
4618
4619 return mask;
4620}
4621
4622static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4623 int level)
4624{
4625 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4626
4627 /* 010b (write-only) */
4628 WARN_ON((spte & 0x7) == 0x2);
4629
4630 /* 110b (write/execute) */
4631 WARN_ON((spte & 0x7) == 0x6);
4632
4633 /* 100b (execute-only) and value not supported by logical processor */
4634 if (!cpu_has_vmx_ept_execute_only())
4635 WARN_ON((spte & 0x7) == 0x4);
4636
4637 /* not 000b */
4638 if ((spte & 0x7)) {
4639 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4640
4641 if (rsvd_bits != 0) {
4642 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4643 __func__, rsvd_bits);
4644 WARN_ON(1);
4645 }
4646
4647 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4648 u64 ept_mem_type = (spte & 0x38) >> 3;
4649
4650 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4651 ept_mem_type == 7) {
4652 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4653 __func__, ept_mem_type);
4654 WARN_ON(1);
4655 }
4656 }
4657 }
4658}
4659
851ba692 4660static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4661{
4662 u64 sptes[4];
4663 int nr_sptes, i;
4664 gpa_t gpa;
4665
4666 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4667
4668 printk(KERN_ERR "EPT: Misconfiguration.\n");
4669 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4670
4671 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4672
4673 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4674 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4675
851ba692
AK		 4676 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4677 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4678
4679 return 0;
4680}
4681
851ba692 4682static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4683{
4684 u32 cpu_based_vm_exec_control;
4685
4686 /* clear pending NMI */
4687 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4688 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4689 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4690 ++vcpu->stat.nmi_window_exits;
3842d135 4691 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4692
4693 return 1;
4694}
4695
80ced186 4696static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4697{
8b3079a5
AK		 4698 struct vcpu_vmx *vmx = to_vmx(vcpu);
4699 enum emulation_result err = EMULATE_DONE;
80ced186 4700 int ret = 1;
49e9d557
AK		 4701 u32 cpu_exec_ctrl;
4702 bool intr_window_requested;
4703
4704 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4705 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4706
4707 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4708 if (intr_window_requested
4709 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4710 return handle_interrupt_window(&vmx->vcpu);
4711
51d8b661 4712 err = emulate_instruction(vcpu, 0);
ea953ef0 4713
80ced186
MG		 4714 if (err == EMULATE_DO_MMIO) {
4715 ret = 0;
4716 goto out;
4717 }
1d5a4d9b 4718
6d77dbfc
GN		 4719 if (err != EMULATE_DONE)
4720 return 0;
ea953ef0
MG		 4721
4722 if (signal_pending(current))
80ced186 4723 goto out;
ea953ef0
MG		 4724 if (need_resched())
4725 schedule();
4726 }
4727
80ced186
MG		 4728 vmx->emulation_required = 0;
4729out:
4730 return ret;
ea953ef0
MG		 4731}
4732
4b8d54f9
ZE		 4733/*
4734 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4735 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4736 */
9fb41ba8 4737static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4738{
4739 skip_emulated_instruction(vcpu);
4740 kvm_vcpu_on_spin(vcpu);
4741
4742 return 1;
4743}
4744
59708670
SY		 4745static int handle_invalid_op(struct kvm_vcpu *vcpu)
4746{
4747 kvm_queue_exception(vcpu, UD_VECTOR);
4748 return 1;
4749}
4750
ff2f6fe9
NHE		 4751/*
4752 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4753 * We could reuse a single VMCS for all the L2 guests, but we also want the
4754 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4755 * allows keeping them loaded on the processor, and in the future will allow
4756 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4757 * every entry if they never change.
4758 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4759 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4760 *
4761 * The following functions allocate and free a vmcs02 in this pool.
4762 */
4763
4764/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4765static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4766{
4767 struct vmcs02_list *item;
4768 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4769 if (item->vmptr == vmx->nested.current_vmptr) {
4770 list_move(&item->list, &vmx->nested.vmcs02_pool);
4771 return &item->vmcs02;
4772 }
4773
4774 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4775 /* Recycle the least recently used VMCS. */
4776 item = list_entry(vmx->nested.vmcs02_pool.prev,
4777 struct vmcs02_list, list);
4778 item->vmptr = vmx->nested.current_vmptr;
4779 list_move(&item->list, &vmx->nested.vmcs02_pool);
4780 return &item->vmcs02;
4781 }
4782
4783 /* Create a new VMCS */
4784 item = (struct vmcs02_list *)
4785 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4786 if (!item)
4787 return NULL;
4788 item->vmcs02.vmcs = alloc_vmcs();
4789 if (!item->vmcs02.vmcs) {
4790 kfree(item);
4791 return NULL;
4792 }
4793 loaded_vmcs_init(&item->vmcs02);
4794 item->vmptr = vmx->nested.current_vmptr;
4795 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4796 vmx->nested.vmcs02_num++;
4797 return &item->vmcs02;
4798}
4799
4800/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4801static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4802{
4803 struct vmcs02_list *item;
4804 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4805 if (item->vmptr == vmptr) {
4806 free_loaded_vmcs(&item->vmcs02);
4807 list_del(&item->list);
4808 kfree(item);
4809 vmx->nested.vmcs02_num--;
4810 return;
4811 }
4812}
4813
4814/*
4815 * Free all VMCSs saved for this vcpu, except the one pointed by
4816 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4817 * currently used, if running L2), and vmcs01 when running L2.
4818 */
4819static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4820{
4821 struct vmcs02_list *item, *n;
4822 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4823 if (vmx->loaded_vmcs != &item->vmcs02)
4824 free_loaded_vmcs(&item->vmcs02);
4825 list_del(&item->list);
4826 kfree(item);
4827 }
4828 vmx->nested.vmcs02_num = 0;
4829
4830 if (vmx->loaded_vmcs != &vmx->vmcs01)
4831 free_loaded_vmcs(&vmx->vmcs01);
4832}
4833
ec378aee
NHE		 4834/*
4835 * Emulate the VMXON instruction.
4836 * Currently, we just remember that VMX is active, and do not save or even
4837 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4838 * do not currently need to store anything in that guest-allocated memory
4839 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4840 * argument is different from the VMXON pointer (which the spec says they do).
4841 */
4842static int handle_vmon(struct kvm_vcpu *vcpu)
4843{
4844 struct kvm_segment cs;
4845 struct vcpu_vmx *vmx = to_vmx(vcpu);
4846
4847 /* The Intel VMX Instruction Reference lists a bunch of bits that
4848 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4849 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4850 * Otherwise, we should fail with #UD. We test these now:
4851 */
4852 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4853 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4854 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4855 kvm_queue_exception(vcpu, UD_VECTOR);
4856 return 1;
4857 }
4858
4859 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4860 if (is_long_mode(vcpu) && !cs.l) {
4861 kvm_queue_exception(vcpu, UD_VECTOR);
4862 return 1;
4863 }
4864
4865 if (vmx_get_cpl(vcpu)) {
4866 kvm_inject_gp(vcpu, 0);
4867 return 1;
4868 }
4869
ff2f6fe9
NHE		 4870 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4871 vmx->nested.vmcs02_num = 0;
4872
ec378aee
NHE		 4873 vmx->nested.vmxon = true;
4874
4875 skip_emulated_instruction(vcpu);
4876 return 1;
4877}
4878
4879/*
4880 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4881 * for running VMX instructions (except VMXON, whose prerequisites are
4882 * slightly different). It also specifies what exception to inject otherwise.
4883 */
4884static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4885{
4886 struct kvm_segment cs;
4887 struct vcpu_vmx *vmx = to_vmx(vcpu);
4888
4889 if (!vmx->nested.vmxon) {
4890 kvm_queue_exception(vcpu, UD_VECTOR);
4891 return 0;
4892 }
4893
4894 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4895 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4896 (is_long_mode(vcpu) && !cs.l)) {
4897 kvm_queue_exception(vcpu, UD_VECTOR);
4898 return 0;
4899 }
4900
4901 if (vmx_get_cpl(vcpu)) {
4902 kvm_inject_gp(vcpu, 0);
4903 return 0;
4904 }
4905
4906 return 1;
4907}
4908
4909/*
4910 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4911 * just stops using VMX.
4912 */
4913static void free_nested(struct vcpu_vmx *vmx)
4914{
4915 if (!vmx->nested.vmxon)
4916 return;
4917 vmx->nested.vmxon = false;
a9d30f33
NHE		 4918 if (vmx->nested.current_vmptr != -1ull) {
4919 kunmap(vmx->nested.current_vmcs12_page);
4920 nested_release_page(vmx->nested.current_vmcs12_page);
4921 vmx->nested.current_vmptr = -1ull;
4922 vmx->nested.current_vmcs12 = NULL;
4923 }
fe3ef05c
NHE		 4924 /* Unpin physical memory we referred to in current vmcs02 */
4925 if (vmx->nested.apic_access_page) {
4926 nested_release_page(vmx->nested.apic_access_page);
4927 vmx->nested.apic_access_page = 0;
4928 }
ff2f6fe9
NHE		 4929
4930 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4931}
4932
4933/* Emulate the VMXOFF instruction */
4934static int handle_vmoff(struct kvm_vcpu *vcpu)
4935{
4936 if (!nested_vmx_check_permission(vcpu))
4937 return 1;
4938 free_nested(to_vmx(vcpu));
4939 skip_emulated_instruction(vcpu);
4940 return 1;
4941}
4942
064aea77
NHE		 4943/*
4944 * Decode the memory-address operand of a vmx instruction, as recorded on an
4945 * exit caused by such an instruction (run by a guest hypervisor).
4946 * On success, returns 0. When the operand is invalid, returns 1 and throws
4947 * #UD or #GP.
4948 */
4949static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4950 unsigned long exit_qualification,
4951 u32 vmx_instruction_info, gva_t *ret)
4952{
4953 /*
4954 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4955 * Execution", on an exit, vmx_instruction_info holds most of the
4956 * addressing components of the operand. Only the displacement part
4957 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4958 * For how an actual address is calculated from all these components,
4959 * refer to Vol. 1, "Operand Addressing".
4960 */
4961 int scaling = vmx_instruction_info & 3;
4962 int addr_size = (vmx_instruction_info >> 7) & 7;
4963 bool is_reg = vmx_instruction_info & (1u << 10);
4964 int seg_reg = (vmx_instruction_info >> 15) & 7;
4965 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4966 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4967 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4968 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4969
4970 if (is_reg) {
4971 kvm_queue_exception(vcpu, UD_VECTOR);
4972 return 1;
4973 }
4974
4975 /* Addr = segment_base + offset */
4976 /* offset = base + [index * scale] + displacement */
4977 *ret = vmx_get_segment_base(vcpu, seg_reg);
4978 if (base_is_valid)
4979 *ret += kvm_register_read(vcpu, base_reg);
4980 if (index_is_valid)
4981 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4982 *ret += exit_qualification; /* holds the displacement */
4983
4984 if (addr_size == 1) /* 32 bit */
4985 *ret &= 0xffffffff;
4986
4987 /*
4988 * TODO: throw #GP (and return 1) in various cases that the VM*
4989 * instructions require it - e.g., offset beyond segment limit,
4990 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4991 * address, and so on. Currently these are not checked.
4992 */
4993 return 0;
4994}
4995
0140caea
NHE		 4996/*
4997 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4998 * set the success or error code of an emulated VMX instruction, as specified
4999 * by Vol 2B, VMX Instruction Reference, "Conventions".
5000 */
5001static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5002{
5003 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5004 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5005 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5006}
5007
5008static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5009{
5010 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5011 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5012 X86_EFLAGS_SF | X86_EFLAGS_OF))
5013 | X86_EFLAGS_CF);
5014}
5015
5016static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5017 u32 vm_instruction_error)
5018{
5019 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5020 /*
5021 * failValid writes the error number to the current VMCS, which
5022 * can't be done there isn't a current VMCS.
5023 */
5024 nested_vmx_failInvalid(vcpu);
5025 return;
5026 }
5027 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5028 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5029 X86_EFLAGS_SF | X86_EFLAGS_OF))
5030 | X86_EFLAGS_ZF);
5031 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5032}
5033
27d6c865
NHE		 5034/* Emulate the VMCLEAR instruction */
5035static int handle_vmclear(struct kvm_vcpu *vcpu)
5036{
5037 struct vcpu_vmx *vmx = to_vmx(vcpu);
5038 gva_t gva;
5039 gpa_t vmptr;
5040 struct vmcs12 *vmcs12;
5041 struct page *page;
5042 struct x86_exception e;
5043
5044 if (!nested_vmx_check_permission(vcpu))
5045 return 1;
5046
5047 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5048 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5049 return 1;
5050
5051 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5052 sizeof(vmptr), &e)) {
5053 kvm_inject_page_fault(vcpu, &e);
5054 return 1;
5055 }
5056
5057 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5058 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5059 skip_emulated_instruction(vcpu);
5060 return 1;
5061 }
5062
5063 if (vmptr == vmx->nested.current_vmptr) {
5064 kunmap(vmx->nested.current_vmcs12_page);
5065 nested_release_page(vmx->nested.current_vmcs12_page);
5066 vmx->nested.current_vmptr = -1ull;
5067 vmx->nested.current_vmcs12 = NULL;
5068 }
5069
5070 page = nested_get_page(vcpu, vmptr);
5071 if (page == NULL) {
5072 /*
5073 * For accurate processor emulation, VMCLEAR beyond available
5074 * physical memory should do nothing at all. However, it is
5075 * possible that a nested vmx bug, not a guest hypervisor bug,
5076 * resulted in this case, so let's shut down before doing any
5077 * more damage:
5078 */
5079 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5080 return 1;
5081 }
5082 vmcs12 = kmap(page);
5083 vmcs12->launch_state = 0;
5084 kunmap(page);
5085 nested_release_page(page);
5086
5087 nested_free_vmcs02(vmx, vmptr);
5088
5089 skip_emulated_instruction(vcpu);
5090 nested_vmx_succeed(vcpu);
5091 return 1;
5092}
5093
cd232ad0
NHE		 5094static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5095
5096/* Emulate the VMLAUNCH instruction */
5097static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5098{
5099 return nested_vmx_run(vcpu, true);
5100}
5101
5102/* Emulate the VMRESUME instruction */
5103static int handle_vmresume(struct kvm_vcpu *vcpu)
5104{
5105
5106 return nested_vmx_run(vcpu, false);
5107}
5108
49f705c5
NHE		 5109enum vmcs_field_type {
5110 VMCS_FIELD_TYPE_U16 = 0,
5111 VMCS_FIELD_TYPE_U64 = 1,
5112 VMCS_FIELD_TYPE_U32 = 2,
5113 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5114};
5115
5116static inline int vmcs_field_type(unsigned long field)
5117{
5118 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5119 return VMCS_FIELD_TYPE_U32;
5120 return (field >> 13) & 0x3 ;
5121}
5122
5123static inline int vmcs_field_readonly(unsigned long field)
5124{
5125 return (((field >> 10) & 0x3) == 1);
5126}
5127
5128/*
5129 * Read a vmcs12 field. Since these can have varying lengths and we return
5130 * one type, we chose the biggest type (u64) and zero-extend the return value
5131 * to that size. Note that the caller, handle_vmread, might need to use only
5132 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5133 * 64-bit fields are to be returned).
5134 */
5135static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5136 unsigned long field, u64 *ret)
5137{
5138 short offset = vmcs_field_to_offset(field);
5139 char *p;
5140
5141 if (offset < 0)
5142 return 0;
5143
5144 p = ((char *)(get_vmcs12(vcpu))) + offset;
5145
5146 switch (vmcs_field_type(field)) {
5147 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5148 *ret = *((natural_width *)p);
5149 return 1;
5150 case VMCS_FIELD_TYPE_U16:
5151 *ret = *((u16 *)p);
5152 return 1;
5153 case VMCS_FIELD_TYPE_U32:
5154 *ret = *((u32 *)p);
5155 return 1;
5156 case VMCS_FIELD_TYPE_U64:
5157 *ret = *((u64 *)p);
5158 return 1;
5159 default:
5160 return 0; /* can never happen. */
5161 }
5162}
5163
5164/*
5165 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5166 * used before) all generate the same failure when it is missing.
5167 */
5168static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5169{
5170 struct vcpu_vmx *vmx = to_vmx(vcpu);
5171 if (vmx->nested.current_vmptr == -1ull) {
5172 nested_vmx_failInvalid(vcpu);
5173 skip_emulated_instruction(vcpu);
5174 return 0;
5175 }
5176 return 1;
5177}
5178
5179static int handle_vmread(struct kvm_vcpu *vcpu)
5180{
5181 unsigned long field;
5182 u64 field_value;
5183 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5184 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5185 gva_t gva = 0;
5186
5187 if (!nested_vmx_check_permission(vcpu) ||
5188 !nested_vmx_check_vmcs12(vcpu))
5189 return 1;
5190
5191 /* Decode instruction info and find the field to read */
5192 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5193 /* Read the field, zero-extended to a u64 field_value */
5194 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5195 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5196 skip_emulated_instruction(vcpu);
5197 return 1;
5198 }
5199 /*
5200 * Now copy part of this value to register or memory, as requested.
5201 * Note that the number of bits actually copied is 32 or 64 depending
5202 * on the guest's mode (32 or 64 bit), not on the given field's length.
5203 */
5204 if (vmx_instruction_info & (1u << 10)) {
5205 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5206 field_value);
5207 } else {
5208 if (get_vmx_mem_address(vcpu, exit_qualification,
5209 vmx_instruction_info, &gva))
5210 return 1;
5211 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5212 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5213 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5214 }
5215
5216 nested_vmx_succeed(vcpu);
5217 skip_emulated_instruction(vcpu);
5218 return 1;
5219}
5220
5221
5222static int handle_vmwrite(struct kvm_vcpu *vcpu)
5223{
5224 unsigned long field;
5225 gva_t gva;
5226 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5227 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5228 char *p;
5229 short offset;
5230 /* The value to write might be 32 or 64 bits, depending on L1's long
5231 * mode, and eventually we need to write that into a field of several
5232 * possible lengths. The code below first zero-extends the value to 64
5233 * bit (field_value), and then copies only the approriate number of
5234 * bits into the vmcs12 field.
5235 */
5236 u64 field_value = 0;
5237 struct x86_exception e;
5238
5239 if (!nested_vmx_check_permission(vcpu) ||
5240 !nested_vmx_check_vmcs12(vcpu))
5241 return 1;
5242
5243 if (vmx_instruction_info & (1u << 10))
5244 field_value = kvm_register_read(vcpu,
5245 (((vmx_instruction_info) >> 3) & 0xf));
5246 else {
5247 if (get_vmx_mem_address(vcpu, exit_qualification,
5248 vmx_instruction_info, &gva))
5249 return 1;
5250 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5251 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5252 kvm_inject_page_fault(vcpu, &e);
5253 return 1;
5254 }
5255 }
5256
5257
5258 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5259 if (vmcs_field_readonly(field)) {
5260 nested_vmx_failValid(vcpu,
5261 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5262 skip_emulated_instruction(vcpu);
5263 return 1;
5264 }
5265
5266 offset = vmcs_field_to_offset(field);
5267 if (offset < 0) {
5268 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5269 skip_emulated_instruction(vcpu);
5270 return 1;
5271 }
5272 p = ((char *) get_vmcs12(vcpu)) + offset;
5273
5274 switch (vmcs_field_type(field)) {
5275 case VMCS_FIELD_TYPE_U16:
5276 *(u16 *)p = field_value;
5277 break;
5278 case VMCS_FIELD_TYPE_U32:
5279 *(u32 *)p = field_value;
5280 break;
5281 case VMCS_FIELD_TYPE_U64:
5282 *(u64 *)p = field_value;
5283 break;
5284 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5285 *(natural_width *)p = field_value;
5286 break;
5287 default:
5288 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5289 skip_emulated_instruction(vcpu);
5290 return 1;
5291 }
5292
5293 nested_vmx_succeed(vcpu);
5294 skip_emulated_instruction(vcpu);
5295 return 1;
5296}
5297
63846663
NHE		 5298/* Emulate the VMPTRLD instruction */
5299static int handle_vmptrld(struct kvm_vcpu *vcpu)
5300{
5301 struct vcpu_vmx *vmx = to_vmx(vcpu);
5302 gva_t gva;
5303 gpa_t vmptr;
5304 struct x86_exception e;
5305
5306 if (!nested_vmx_check_permission(vcpu))
5307 return 1;
5308
5309 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5310 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5311 return 1;
5312
5313 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5314 sizeof(vmptr), &e)) {
5315 kvm_inject_page_fault(vcpu, &e);
5316 return 1;
5317 }
5318
5319 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5320 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5321 skip_emulated_instruction(vcpu);
5322 return 1;
5323 }
5324
5325 if (vmx->nested.current_vmptr != vmptr) {
5326 struct vmcs12 *new_vmcs12;
5327 struct page *page;
5328 page = nested_get_page(vcpu, vmptr);
5329 if (page == NULL) {
5330 nested_vmx_failInvalid(vcpu);
5331 skip_emulated_instruction(vcpu);
5332 return 1;
5333 }
5334 new_vmcs12 = kmap(page);
5335 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5336 kunmap(page);
5337 nested_release_page_clean(page);
5338 nested_vmx_failValid(vcpu,
5339 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5340 skip_emulated_instruction(vcpu);
5341 return 1;
5342 }
5343 if (vmx->nested.current_vmptr != -1ull) {
5344 kunmap(vmx->nested.current_vmcs12_page);
5345 nested_release_page(vmx->nested.current_vmcs12_page);
5346 }
5347
5348 vmx->nested.current_vmptr = vmptr;
5349 vmx->nested.current_vmcs12 = new_vmcs12;
5350 vmx->nested.current_vmcs12_page = page;
5351 }
5352
5353 nested_vmx_succeed(vcpu);
5354 skip_emulated_instruction(vcpu);
5355 return 1;
5356}
5357
6a4d7550
NHE		 5358/* Emulate the VMPTRST instruction */
5359static int handle_vmptrst(struct kvm_vcpu *vcpu)
5360{
5361 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5362 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5363 gva_t vmcs_gva;
5364 struct x86_exception e;
5365
5366 if (!nested_vmx_check_permission(vcpu))
5367 return 1;
5368
5369 if (get_vmx_mem_address(vcpu, exit_qualification,
5370 vmx_instruction_info, &vmcs_gva))
5371 return 1;
5372 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5373 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5374 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5375 sizeof(u64), &e)) {
5376 kvm_inject_page_fault(vcpu, &e);
5377 return 1;
5378 }
5379 nested_vmx_succeed(vcpu);
5380 skip_emulated_instruction(vcpu);
5381 return 1;
5382}
5383
6aa8b732
AK		 5384/*
5385 * The exit handlers return 1 if the exit was handled fully and guest execution
5386 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5387 * to be done to userspace and return 0.
5388 */
851ba692 5389static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5390 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5391 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5392 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5393 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5394 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5395 [EXIT_REASON_CR_ACCESS] = handle_cr,
5396 [EXIT_REASON_DR_ACCESS] = handle_dr,
5397 [EXIT_REASON_CPUID] = handle_cpuid,
5398 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5399 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5400 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5401 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5402 [EXIT_REASON_INVD] = handle_invd,
a7052897 5403 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5404 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5405 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5406 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5407 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5408 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5409 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5410 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5411 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5412 [EXIT_REASON_VMOFF] = handle_vmoff,
5413 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5414 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5415 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5416 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5417 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5418 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5419 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5420 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5421 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5422 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5423 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5424 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5425};
5426
5427static const int kvm_vmx_max_exit_handlers =
50a3485c 5428 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5429
644d711a
NHE		 5430/*
5431 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5432 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5433 * disinterest in the current event (read or write a specific MSR) by using an
5434 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5435 */
5436static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5437 struct vmcs12 *vmcs12, u32 exit_reason)
5438{
5439 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5440 gpa_t bitmap;
5441
5442 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5443 return 1;
5444
5445 /*
5446 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5447 * for the four combinations of read/write and low/high MSR numbers.
5448 * First we need to figure out which of the four to use:
5449 */
5450 bitmap = vmcs12->msr_bitmap;
5451 if (exit_reason == EXIT_REASON_MSR_WRITE)
5452 bitmap += 2048;
5453 if (msr_index >= 0xc0000000) {
5454 msr_index -= 0xc0000000;
5455 bitmap += 1024;
5456 }
5457
5458 /* Then read the msr_index'th bit from this bitmap: */
5459 if (msr_index < 1024*8) {
5460 unsigned char b;
5461 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5462 return 1 & (b >> (msr_index & 7));
5463 } else
5464 return 1; /* let L1 handle the wrong parameter */
5465}
5466
5467/*
5468 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5469 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5470 * intercept (via guest_host_mask etc.) the current event.
5471 */
5472static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5473 struct vmcs12 *vmcs12)
5474{
5475 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5476 int cr = exit_qualification & 15;
5477 int reg = (exit_qualification >> 8) & 15;
5478 unsigned long val = kvm_register_read(vcpu, reg);
5479
5480 switch ((exit_qualification >> 4) & 3) {
5481 case 0: /* mov to cr */
5482 switch (cr) {
5483 case 0:
5484 if (vmcs12->cr0_guest_host_mask &
5485 (val ^ vmcs12->cr0_read_shadow))
5486 return 1;
5487 break;
5488 case 3:
5489 if ((vmcs12->cr3_target_count >= 1 &&
5490 vmcs12->cr3_target_value0 == val) ||
5491 (vmcs12->cr3_target_count >= 2 &&
5492 vmcs12->cr3_target_value1 == val) ||
5493 (vmcs12->cr3_target_count >= 3 &&
5494 vmcs12->cr3_target_value2 == val) ||
5495 (vmcs12->cr3_target_count >= 4 &&
5496 vmcs12->cr3_target_value3 == val))
5497 return 0;
5498 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5499 return 1;
5500 break;
5501 case 4:
5502 if (vmcs12->cr4_guest_host_mask &
5503 (vmcs12->cr4_read_shadow ^ val))
5504 return 1;
5505 break;
5506 case 8:
5507 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5508 return 1;
5509 break;
5510 }
5511 break;
5512 case 2: /* clts */
5513 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5514 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5515 return 1;
5516 break;
5517 case 1: /* mov from cr */
5518 switch (cr) {
5519 case 3:
5520 if (vmcs12->cpu_based_vm_exec_control &
5521 CPU_BASED_CR3_STORE_EXITING)
5522 return 1;
5523 break;
5524 case 8:
5525 if (vmcs12->cpu_based_vm_exec_control &
5526 CPU_BASED_CR8_STORE_EXITING)
5527 return 1;
5528 break;
5529 }
5530 break;
5531 case 3: /* lmsw */
5532 /*
5533 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5534 * cr0. Other attempted changes are ignored, with no exit.
5535 */
5536 if (vmcs12->cr0_guest_host_mask & 0xe &
5537 (val ^ vmcs12->cr0_read_shadow))
5538 return 1;
5539 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5540 !(vmcs12->cr0_read_shadow & 0x1) &&
5541 (val & 0x1))
5542 return 1;
5543 break;
5544 }
5545 return 0;
5546}
5547
5548/*
5549 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5550 * should handle it ourselves in L0 (and then continue L2). Only call this
5551 * when in is_guest_mode (L2).
5552 */
5553static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5554{
5555 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5556 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5557 struct vcpu_vmx *vmx = to_vmx(vcpu);
5558 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5559
5560 if (vmx->nested.nested_run_pending)
5561 return 0;
5562
5563 if (unlikely(vmx->fail)) {
5564 printk(KERN_INFO "%s failed vm entry %x\n",
5565 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5566 return 1;
5567 }
5568
5569 switch (exit_reason) {
5570 case EXIT_REASON_EXCEPTION_NMI:
5571 if (!is_exception(intr_info))
5572 return 0;
5573 else if (is_page_fault(intr_info))
5574 return enable_ept;
5575 return vmcs12->exception_bitmap &
5576 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5577 case EXIT_REASON_EXTERNAL_INTERRUPT:
5578 return 0;
5579 case EXIT_REASON_TRIPLE_FAULT:
5580 return 1;
5581 case EXIT_REASON_PENDING_INTERRUPT:
5582 case EXIT_REASON_NMI_WINDOW:
5583 /*
5584 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5585 * (aka Interrupt Window Exiting) only when L1 turned it on,
5586 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5587 * Same for NMI Window Exiting.
5588 */
5589 return 1;
5590 case EXIT_REASON_TASK_SWITCH:
5591 return 1;
5592 case EXIT_REASON_CPUID:
5593 return 1;
5594 case EXIT_REASON_HLT:
5595 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5596 case EXIT_REASON_INVD:
5597 return 1;
5598 case EXIT_REASON_INVLPG:
5599 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5600 case EXIT_REASON_RDPMC:
5601 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5602 case EXIT_REASON_RDTSC:
5603 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5604 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5605 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5606 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5607 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5608 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5609 /*
5610 * VMX instructions trap unconditionally. This allows L1 to
5611 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5612 */
5613 return 1;
5614 case EXIT_REASON_CR_ACCESS:
5615 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5616 case EXIT_REASON_DR_ACCESS:
5617 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5618 case EXIT_REASON_IO_INSTRUCTION:
5619 /* TODO: support IO bitmaps */
5620 return 1;
5621 case EXIT_REASON_MSR_READ:
5622 case EXIT_REASON_MSR_WRITE:
5623 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5624 case EXIT_REASON_INVALID_STATE:
5625 return 1;
5626 case EXIT_REASON_MWAIT_INSTRUCTION:
5627 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5628 case EXIT_REASON_MONITOR_INSTRUCTION:
5629 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5630 case EXIT_REASON_PAUSE_INSTRUCTION:
5631 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5632 nested_cpu_has2(vmcs12,
5633 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5634 case EXIT_REASON_MCE_DURING_VMENTRY:
5635 return 0;
5636 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5637 return 1;
5638 case EXIT_REASON_APIC_ACCESS:
5639 return nested_cpu_has2(vmcs12,
5640 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5641 case EXIT_REASON_EPT_VIOLATION:
5642 case EXIT_REASON_EPT_MISCONFIG:
5643 return 0;
5644 case EXIT_REASON_WBINVD:
5645 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5646 case EXIT_REASON_XSETBV:
5647 return 1;
5648 default:
5649 return 1;
5650 }
5651}
5652
586f9607
AK		 5653static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5654{
5655 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5656 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5657}
5658
6aa8b732
AK		 5659/*
5660 * The guest has exited. See if we can fix it or if we need userspace
5661 * assistance.
5662 */
851ba692 5663static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5664{
29bd8a78 5665 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5666 u32 exit_reason = vmx->exit_reason;
1155f76a 5667 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5668
aa17911e 5669 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5670
80ced186
MG		 5671 /* If guest state is invalid, start emulating */
5672 if (vmx->emulation_required && emulate_invalid_guest_state)
5673 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5674
b6f1250e
NHE		 5675 /*
5676 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5677 * we did not inject a still-pending event to L1 now because of
5678 * nested_run_pending, we need to re-enable this bit.
5679 */
5680 if (vmx->nested.nested_run_pending)
5681 kvm_make_request(KVM_REQ_EVENT, vcpu);
5682
644d711a
NHE		 5683 if (exit_reason == EXIT_REASON_VMLAUNCH ||
5684 exit_reason == EXIT_REASON_VMRESUME)
5685 vmx->nested.nested_run_pending = 1;
5686 else
5687 vmx->nested.nested_run_pending = 0;
5688
5689 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5690 nested_vmx_vmexit(vcpu);
5691 return 1;
5692 }
5693
5120702e
MG		 5694 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5695 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5696 vcpu->run->fail_entry.hardware_entry_failure_reason
5697 = exit_reason;
5698 return 0;
5699 }
5700
29bd8a78 5701 if (unlikely(vmx->fail)) {
851ba692
AK		 5702 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5703 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5704 = vmcs_read32(VM_INSTRUCTION_ERROR);
5705 return 0;
5706 }
6aa8b732 5707
d77c26fc 5708 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5709 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5710 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5711 exit_reason != EXIT_REASON_TASK_SWITCH))
5712 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5713 "(0x%x) and exit reason is 0x%x\n",
5714 __func__, vectoring_info, exit_reason);
3b86cd99 5715
644d711a
NHE		 5716 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5717 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5718 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5719 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5720 vmx->soft_vnmi_blocked = 0;
3b86cd99 5721 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5722 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5723 /*
5724 * This CPU don't support us in finding the end of an
5725 * NMI-blocked window if the guest runs with IRQs
5726 * disabled. So we pull the trigger after 1 s of
5727 * futile waiting, but inform the user about this.
5728 */
5729 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5730 "state on VCPU %d after 1 s timeout\n",
5731 __func__, vcpu->vcpu_id);
5732 vmx->soft_vnmi_blocked = 0;
3b86cd99 5733 }
3b86cd99
JK		 5734 }
5735
6aa8b732
AK		 5736 if (exit_reason < kvm_vmx_max_exit_handlers
5737 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5738 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5739 else {
851ba692
AK		 5740 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5741 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5742 }
5743 return 0;
5744}
5745
95ba8273 5746static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5747{
95ba8273 5748 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5749 vmcs_write32(TPR_THRESHOLD, 0);
5750 return;
5751 }
5752
95ba8273 5753 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5754}
5755
51aa01d1 5756static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5757{
00eba012
AK		 5758 u32 exit_intr_info;
5759
5760 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5761 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5762 return;
5763
c5ca8e57 5764 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5765 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5766
5767 /* Handle machine checks before interrupts are enabled */
00eba012 5768 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5769 kvm_machine_check();
5770
20f65983 5771 /* We need to handle NMIs before interrupts are enabled */
00eba012 5772 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5773 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5774 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5775 asm("int $2");
ff9d07a0
ZY		 5776 kvm_after_handle_nmi(&vmx->vcpu);
5777 }
51aa01d1 5778}
20f65983 5779
51aa01d1
AK		 5780static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5781{
c5ca8e57 5782 u32 exit_intr_info;
51aa01d1
AK		 5783 bool unblock_nmi;
5784 u8 vector;
5785 bool idtv_info_valid;
5786
5787 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5788
cf393f75 5789 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5790 if (vmx->nmi_known_unmasked)
5791 return;
c5ca8e57
AK		 5792 /*
5793 * Can't use vmx->exit_intr_info since we're not sure what
5794 * the exit reason is.
5795 */
5796 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5797 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5798 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5799 /*
7b4a25cb 5800 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5801 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5802 * a guest IRET fault.
7b4a25cb
GN		 5803 * SDM 3: 23.2.2 (September 2008)
5804 * Bit 12 is undefined in any of the following cases:
5805 * If the VM exit sets the valid bit in the IDT-vectoring
5806 * information field.
5807 * If the VM exit is due to a double fault.
cf393f75 5808 */
7b4a25cb
GN		 5809 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5810 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5811 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5812 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5813 else
5814 vmx->nmi_known_unmasked =
5815 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5816 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5817 } else if (unlikely(vmx->soft_vnmi_blocked))
5818 vmx->vnmi_blocked_time +=
5819 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5820}
5821
83422e17
AK		 5822static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5823 u32 idt_vectoring_info,
5824 int instr_len_field,
5825 int error_code_field)
51aa01d1 5826{
51aa01d1
AK		 5827 u8 vector;
5828 int type;
5829 bool idtv_info_valid;
5830
5831 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5832
37b96e98
GN		 5833 vmx->vcpu.arch.nmi_injected = false;
5834 kvm_clear_exception_queue(&vmx->vcpu);
5835 kvm_clear_interrupt_queue(&vmx->vcpu);
5836
5837 if (!idtv_info_valid)
5838 return;
5839
3842d135
AK		 5840 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5841
668f612f
AK		 5842 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5843 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5844
64a7ec06 5845 switch (type) {
37b96e98
GN		 5846 case INTR_TYPE_NMI_INTR:
5847 vmx->vcpu.arch.nmi_injected = true;
668f612f 5848 /*
7b4a25cb 5849 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5850 * Clear bit "block by NMI" before VM entry if a NMI
5851 * delivery faulted.
668f612f 5852 */
654f06fc 5853 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5854 break;
37b96e98 5855 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5856 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5857 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5858 /* fall through */
5859 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5860 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5861 u32 err = vmcs_read32(error_code_field);
37b96e98 5862 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5863 } else
5864 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5865 break;
66fd3f7f
GN		 5866 case INTR_TYPE_SOFT_INTR:
5867 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5868 vmcs_read32(instr_len_field);
66fd3f7f 5869 /* fall through */
37b96e98 5870 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5871 kvm_queue_interrupt(&vmx->vcpu, vector,
5872 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5873 break;
5874 default:
5875 break;
f7d9238f 5876 }
cf393f75
AK		 5877}
5878
83422e17
AK		 5879static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5880{
66c78ae4
NHE		 5881 if (is_guest_mode(&vmx->vcpu))
5882 return;
83422e17
AK		 5883 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5884 VM_EXIT_INSTRUCTION_LEN,
5885 IDT_VECTORING_ERROR_CODE);
5886}
5887
b463a6f7
AK		 5888static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5889{
66c78ae4
NHE		 5890 if (is_guest_mode(vcpu))
5891 return;
b463a6f7
AK		 5892 __vmx_complete_interrupts(to_vmx(vcpu),
5893 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5894 VM_ENTRY_INSTRUCTION_LEN,
5895 VM_ENTRY_EXCEPTION_ERROR_CODE);
5896
5897 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5898}
5899
c801949d
AK		 5900#ifdef CONFIG_X86_64
5901#define R "r"
5902#define Q "q"
5903#else
5904#define R "e"
5905#define Q "l"
5906#endif
5907
a3b5ba49 5908static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5909{
a2fa3e9f 5910 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 5911
66c78ae4
NHE		 5912 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5913 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5914 if (vmcs12->idt_vectoring_info_field &
5915 VECTORING_INFO_VALID_MASK) {
5916 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5917 vmcs12->idt_vectoring_info_field);
5918 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5919 vmcs12->vm_exit_instruction_len);
5920 if (vmcs12->idt_vectoring_info_field &
5921 VECTORING_INFO_DELIVER_CODE_MASK)
5922 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5923 vmcs12->idt_vectoring_error_code);
5924 }
5925 }
5926
104f226b
AK		 5927 /* Record the guest's net vcpu time for enforced NMI injections. */
5928 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5929 vmx->entry_time = ktime_get();
5930
5931 /* Don't enter VMX if guest state is invalid, let the exit handler
5932 start emulation until we arrive back to a valid state */
5933 if (vmx->emulation_required && emulate_invalid_guest_state)
5934 return;
5935
5936 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5937 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5938 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5939 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5940
5941 /* When single-stepping over STI and MOV SS, we must clear the
5942 * corresponding interruptibility bits in the guest state. Otherwise
5943 * vmentry fails as it then expects bit 14 (BS) in pending debug
5944 * exceptions being set, but that's not correct for the guest debugging
5945 * case. */
5946 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5947 vmx_set_interrupt_shadow(vcpu, 0);
5948
d462b819 5949 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5950 asm(
6aa8b732 5951 /* Store host registers */
c801949d 5952 "push %%"R"dx; push %%"R"bp;"
40712fae 5953 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5954 "push %%"R"cx \n\t"
313dbd49
AK		 5955 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5956 "je 1f \n\t"
5957 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5958 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5959 "1: \n\t"
d3edefc0
AK		 5960 /* Reload cr2 if changed */
5961 "mov %c[cr2](%0), %%"R"ax \n\t"
5962 "mov %%cr2, %%"R"dx \n\t"
5963 "cmp %%"R"ax, %%"R"dx \n\t"
5964 "je 2f \n\t"
5965 "mov %%"R"ax, %%cr2 \n\t"
5966 "2: \n\t"
6aa8b732 5967 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5968 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5969 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5970 "mov %c[rax](%0), %%"R"ax \n\t"
5971 "mov %c[rbx](%0), %%"R"bx \n\t"
5972 "mov %c[rdx](%0), %%"R"dx \n\t"
5973 "mov %c[rsi](%0), %%"R"si \n\t"
5974 "mov %c[rdi](%0), %%"R"di \n\t"
5975 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 5976#ifdef CONFIG_X86_64
e08aa78a
AK		 5977 "mov %c[r8](%0), %%r8 \n\t"
5978 "mov %c[r9](%0), %%r9 \n\t"
5979 "mov %c[r10](%0), %%r10 \n\t"
5980 "mov %c[r11](%0), %%r11 \n\t"
5981 "mov %c[r12](%0), %%r12 \n\t"
5982 "mov %c[r13](%0), %%r13 \n\t"
5983 "mov %c[r14](%0), %%r14 \n\t"
5984 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 5985#endif
c801949d
AK		 5986 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5987
6aa8b732 5988 /* Enter guest mode */
cd2276a7 5989 "jne .Llaunched \n\t"
4ecac3fd 5990 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 5991 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 5992 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 5993 ".Lkvm_vmx_return: "
6aa8b732 5994 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 5995 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5996 "pop %0 \n\t"
c801949d
AK		 5997 "mov %%"R"ax, %c[rax](%0) \n\t"
5998 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 5999 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6000 "mov %%"R"dx, %c[rdx](%0) \n\t"
6001 "mov %%"R"si, %c[rsi](%0) \n\t"
6002 "mov %%"R"di, %c[rdi](%0) \n\t"
6003 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6004#ifdef CONFIG_X86_64
e08aa78a
AK		 6005 "mov %%r8, %c[r8](%0) \n\t"
6006 "mov %%r9, %c[r9](%0) \n\t"
6007 "mov %%r10, %c[r10](%0) \n\t"
6008 "mov %%r11, %c[r11](%0) \n\t"
6009 "mov %%r12, %c[r12](%0) \n\t"
6010 "mov %%r13, %c[r13](%0) \n\t"
6011 "mov %%r14, %c[r14](%0) \n\t"
6012 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6013#endif
c801949d
AK		 6014 "mov %%cr2, %%"R"ax \n\t"
6015 "mov %%"R"ax, %c[cr2](%0) \n\t"
6016
1c696d0e 6017 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6018 "setbe %c[fail](%0) \n\t"
6019 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6020 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6021 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6022 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6023 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6024 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6025 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6026 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6027 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6028 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6029 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6030#ifdef CONFIG_X86_64
ad312c7c
ZX		 6031 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6032 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6033 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6034 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6035 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6036 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6037 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6038 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6039#endif
40712fae
AK		 6040 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6041 [wordsize]"i"(sizeof(ulong))
c2036300 6042 : "cc", "memory"
07d6f555 6043 , R"ax", R"bx", R"di", R"si"
c2036300 6044#ifdef CONFIG_X86_64
c2036300
LV		 6045 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6046#endif
6047 );
6aa8b732 6048
6de4f3ad 6049 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6050 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6051 | (1 << VCPU_EXREG_CPL)
aff48baa 6052 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6053 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6054 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6055 vcpu->arch.regs_dirty = 0;
6056
1155f76a
AK		 6057 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6058
66c78ae4
NHE		 6059 if (is_guest_mode(vcpu)) {
6060 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6061 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6062 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6063 vmcs12->idt_vectoring_error_code =
6064 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6065 vmcs12->vm_exit_instruction_len =
6066 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6067 }
6068 }
6069
d77c26fc 6070 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6071 vmx->loaded_vmcs->launched = 1;
1b6269db 6072
51aa01d1 6073 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 6074
6075 vmx_complete_atomic_exit(vmx);
6076 vmx_recover_nmi_blocking(vmx);
cf393f75 6077 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6078}
6079
c801949d
AK		 6080#undef R
6081#undef Q
6082
6aa8b732
AK		 6083static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6084{
fb3f0f51
RR		 6085 struct vcpu_vmx *vmx = to_vmx(vcpu);
6086
cdbecfc3 6087 free_vpid(vmx);
ec378aee 6088 free_nested(vmx);
d462b819 6089 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6090 kfree(vmx->guest_msrs);
6091 kvm_vcpu_uninit(vcpu);
a4770347 6092 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6093}
6094
fb3f0f51 6095static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6096{
fb3f0f51 6097 int err;
c16f862d 6098 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6099 int cpu;
6aa8b732 6100
a2fa3e9f 6101 if (!vmx)
fb3f0f51
RR		 6102 return ERR_PTR(-ENOMEM);
6103
2384d2b3
SY		 6104 allocate_vpid(vmx);
6105
fb3f0f51
RR		 6106 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6107 if (err)
6108 goto free_vcpu;
965b58a5 6109
a2fa3e9f 6110 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6111 err = -ENOMEM;
fb3f0f51 6112 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6113 goto uninit_vcpu;
6114 }
965b58a5 6115
d462b819
NHE		 6116 vmx->loaded_vmcs = &vmx->vmcs01;
6117 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6118 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6119 goto free_msrs;
d462b819
NHE		 6120 if (!vmm_exclusive)
6121 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6122 loaded_vmcs_init(vmx->loaded_vmcs);
6123 if (!vmm_exclusive)
6124 kvm_cpu_vmxoff();
a2fa3e9f 6125
15ad7146
AK		 6126 cpu = get_cpu();
6127 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6128 vmx->vcpu.cpu = cpu;
8b9cf98c 6129 err = vmx_vcpu_setup(vmx);
fb3f0f51 6130 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6131 put_cpu();
fb3f0f51
RR		 6132 if (err)
6133 goto free_vmcs;
5e4a0b3c 6134 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6135 err = alloc_apic_access_page(kvm);
6136 if (err)
5e4a0b3c 6137 goto free_vmcs;
fb3f0f51 6138
b927a3ce
SY		 6139 if (enable_ept) {
6140 if (!kvm->arch.ept_identity_map_addr)
6141 kvm->arch.ept_identity_map_addr =
6142 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6143 err = -ENOMEM;
b7ebfb05
SY		 6144 if (alloc_identity_pagetable(kvm) != 0)
6145 goto free_vmcs;
93ea5388
GN		 6146 if (!init_rmode_identity_map(kvm))
6147 goto free_vmcs;
b927a3ce 6148 }
b7ebfb05 6149
a9d30f33
NHE		 6150 vmx->nested.current_vmptr = -1ull;
6151 vmx->nested.current_vmcs12 = NULL;
6152
fb3f0f51
RR		 6153 return &vmx->vcpu;
6154
6155free_vmcs:
d462b819 6156 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6157free_msrs:
fb3f0f51
RR		 6158 kfree(vmx->guest_msrs);
6159uninit_vcpu:
6160 kvm_vcpu_uninit(&vmx->vcpu);
6161free_vcpu:
cdbecfc3 6162 free_vpid(vmx);
a4770347 6163 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6164 return ERR_PTR(err);
6aa8b732
AK		 6165}
6166
002c7f7c
YS		 6167static void __init vmx_check_processor_compat(void *rtn)
6168{
6169 struct vmcs_config vmcs_conf;
6170
6171 *(int *)rtn = 0;
6172 if (setup_vmcs_config(&vmcs_conf) < 0)
6173 *(int *)rtn = -EIO;
6174 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6175 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6176 smp_processor_id());
6177 *(int *)rtn = -EIO;
6178 }
6179}
6180
67253af5
SY		 6181static int get_ept_level(void)
6182{
6183 return VMX_EPT_DEFAULT_GAW + 1;
6184}
6185
4b12f0de 6186static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6187{
4b12f0de
SY		 6188 u64 ret;
6189
522c68c4
SY		 6190 /* For VT-d and EPT combination
6191 * 1. MMIO: always map as UC
6192 * 2. EPT with VT-d:
6193 * a. VT-d without snooping control feature: can't guarantee the
6194 * result, try to trust guest.
6195 * b. VT-d with snooping control feature: snooping control feature of
6196 * VT-d engine can guarantee the cache correctness. Just set it
6197 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6198 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6199 * consistent with host MTRR
6200 */
4b12f0de
SY		 6201 if (is_mmio)
6202 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6203 else if (vcpu->kvm->arch.iommu_domain &&
6204 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6205 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6206 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6207 else
522c68c4 6208 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6209 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6210
6211 return ret;
64d4d521
SY		 6212}
6213
f4c9e87c
AK		 6214#define _ER(x) { EXIT_REASON_##x, #x }
6215
229456fc 6216static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 6217 _ER(EXCEPTION_NMI),
6218 _ER(EXTERNAL_INTERRUPT),
6219 _ER(TRIPLE_FAULT),
6220 _ER(PENDING_INTERRUPT),
6221 _ER(NMI_WINDOW),
6222 _ER(TASK_SWITCH),
6223 _ER(CPUID),
6224 _ER(HLT),
6225 _ER(INVLPG),
6226 _ER(RDPMC),
6227 _ER(RDTSC),
6228 _ER(VMCALL),
6229 _ER(VMCLEAR),
6230 _ER(VMLAUNCH),
6231 _ER(VMPTRLD),
6232 _ER(VMPTRST),
6233 _ER(VMREAD),
6234 _ER(VMRESUME),
6235 _ER(VMWRITE),
6236 _ER(VMOFF),
6237 _ER(VMON),
6238 _ER(CR_ACCESS),
6239 _ER(DR_ACCESS),
6240 _ER(IO_INSTRUCTION),
6241 _ER(MSR_READ),
6242 _ER(MSR_WRITE),
6243 _ER(MWAIT_INSTRUCTION),
6244 _ER(MONITOR_INSTRUCTION),
6245 _ER(PAUSE_INSTRUCTION),
6246 _ER(MCE_DURING_VMENTRY),
6247 _ER(TPR_BELOW_THRESHOLD),
6248 _ER(APIC_ACCESS),
6249 _ER(EPT_VIOLATION),
6250 _ER(EPT_MISCONFIG),
6251 _ER(WBINVD),
229456fc
MT		 6252 { -1, NULL }
6253};
6254
f4c9e87c
AK		 6255#undef _ER
6256
17cc3935 6257static int vmx_get_lpage_level(void)
344f414f 6258{
878403b7
SY		 6259 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6260 return PT_DIRECTORY_LEVEL;
6261 else
6262 /* For shadow and EPT supported 1GB page */
6263 return PT_PDPE_LEVEL;
344f414f
JR		 6264}
6265
0e851880
SY		 6266static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6267{
4e47c7a6
SY		 6268 struct kvm_cpuid_entry2 *best;
6269 struct vcpu_vmx *vmx = to_vmx(vcpu);
6270 u32 exec_control;
6271
6272 vmx->rdtscp_enabled = false;
6273 if (vmx_rdtscp_supported()) {
6274 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6275 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6276 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6277 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6278 vmx->rdtscp_enabled = true;
6279 else {
6280 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6281 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6282 exec_control);
6283 }
6284 }
6285 }
0e851880
SY		 6286}
6287
d4330ef2
JR		 6288static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6289{
6290}
6291
fe3ef05c
NHE		 6292/*
6293 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6294 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6295 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6296 * guest in a way that will both be appropriate to L1's requests, and our
6297 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6298 * function also has additional necessary side-effects, like setting various
6299 * vcpu->arch fields.
6300 */
6301static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6302{
6303 struct vcpu_vmx *vmx = to_vmx(vcpu);
6304 u32 exec_control;
6305
6306 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6307 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6308 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6309 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6310 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6311 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6312 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6313 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6314 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6315 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6316 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6317 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6318 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6319 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6320 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6321 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6322 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6323 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6324 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6325 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6326 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6327 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6328 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6329 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6330 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6331 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6332 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6333 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6334 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6335 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6336 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6337 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6338 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6339 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6340 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6341 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6342
6343 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6344 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6345 vmcs12->vm_entry_intr_info_field);
6346 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6347 vmcs12->vm_entry_exception_error_code);
6348 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6349 vmcs12->vm_entry_instruction_len);
6350 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6351 vmcs12->guest_interruptibility_info);
6352 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6353 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6354 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6355 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6356 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6357 vmcs12->guest_pending_dbg_exceptions);
6358 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6359 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6360
6361 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6362
6363 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6364 (vmcs_config.pin_based_exec_ctrl |
6365 vmcs12->pin_based_vm_exec_control));
6366
6367 /*
6368 * Whether page-faults are trapped is determined by a combination of
6369 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6370 * If enable_ept, L0 doesn't care about page faults and we should
6371 * set all of these to L1's desires. However, if !enable_ept, L0 does
6372 * care about (at least some) page faults, and because it is not easy
6373 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6374 * to exit on each and every L2 page fault. This is done by setting
6375 * MASK=MATCH=0 and (see below) EB.PF=1.
6376 * Note that below we don't need special code to set EB.PF beyond the
6377 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6378 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6379 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6380 *
6381 * A problem with this approach (when !enable_ept) is that L1 may be
6382 * injected with more page faults than it asked for. This could have
6383 * caused problems, but in practice existing hypervisors don't care.
6384 * To fix this, we will need to emulate the PFEC checking (on the L1
6385 * page tables), using walk_addr(), when injecting PFs to L1.
6386 */
6387 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6388 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6389 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6390 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6391
6392 if (cpu_has_secondary_exec_ctrls()) {
6393 u32 exec_control = vmx_secondary_exec_control(vmx);
6394 if (!vmx->rdtscp_enabled)
6395 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6396 /* Take the following fields only from vmcs12 */
6397 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6398 if (nested_cpu_has(vmcs12,
6399 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6400 exec_control |= vmcs12->secondary_vm_exec_control;
6401
6402 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6403 /*
6404 * Translate L1 physical address to host physical
6405 * address for vmcs02. Keep the page pinned, so this
6406 * physical address remains valid. We keep a reference
6407 * to it so we can release it later.
6408 */
6409 if (vmx->nested.apic_access_page) /* shouldn't happen */
6410 nested_release_page(vmx->nested.apic_access_page);
6411 vmx->nested.apic_access_page =
6412 nested_get_page(vcpu, vmcs12->apic_access_addr);
6413 /*
6414 * If translation failed, no matter: This feature asks
6415 * to exit when accessing the given address, and if it
6416 * can never be accessed, this feature won't do
6417 * anything anyway.
6418 */
6419 if (!vmx->nested.apic_access_page)
6420 exec_control &=
6421 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6422 else
6423 vmcs_write64(APIC_ACCESS_ADDR,
6424 page_to_phys(vmx->nested.apic_access_page));
6425 }
6426
6427 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6428 }
6429
6430
6431 /*
6432 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6433 * Some constant fields are set here by vmx_set_constant_host_state().
6434 * Other fields are different per CPU, and will be set later when
6435 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6436 */
6437 vmx_set_constant_host_state();
6438
6439 /*
6440 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6441 * entry, but only if the current (host) sp changed from the value
6442 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6443 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6444 * here we just force the write to happen on entry.
6445 */
6446 vmx->host_rsp = 0;
6447
6448 exec_control = vmx_exec_control(vmx); /* L0's desires */
6449 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6450 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6451 exec_control &= ~CPU_BASED_TPR_SHADOW;
6452 exec_control |= vmcs12->cpu_based_vm_exec_control;
6453 /*
6454 * Merging of IO and MSR bitmaps not currently supported.
6455 * Rather, exit every time.
6456 */
6457 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6458 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6459 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6460
6461 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6462
6463 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6464 * bitwise-or of what L1 wants to trap for L2, and what we want to
6465 * trap. Note that CR0.TS also needs updating - we do this later.
6466 */
6467 update_exception_bitmap(vcpu);
6468 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6469 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6470
6471 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6472 vmcs_write32(VM_EXIT_CONTROLS,
6473 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6474 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6475 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6476
6477 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6478 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6479 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6480 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6481
6482
6483 set_cr4_guest_host_mask(vmx);
6484
6485 vmcs_write64(TSC_OFFSET,
6486 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6487
6488 if (enable_vpid) {
6489 /*
6490 * Trivially support vpid by letting L2s share their parent
6491 * L1's vpid. TODO: move to a more elaborate solution, giving
6492 * each L2 its own vpid and exposing the vpid feature to L1.
6493 */
6494 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6495 vmx_flush_tlb(vcpu);
6496 }
6497
6498 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6499 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6500 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6501 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6502 else
6503 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6504 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6505 vmx_set_efer(vcpu, vcpu->arch.efer);
6506
6507 /*
6508 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6509 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6510 * The CR0_READ_SHADOW is what L2 should have expected to read given
6511 * the specifications by L1; It's not enough to take
6512 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6513 * have more bits than L1 expected.
6514 */
6515 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6516 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6517
6518 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6519 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6520
6521 /* shadow page tables on either EPT or shadow page tables */
6522 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6523 kvm_mmu_reset_context(vcpu);
6524
6525 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6526 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6527}
6528
cd232ad0
NHE		 6529/*
6530 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6531 * for running an L2 nested guest.
6532 */
6533static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6534{
6535 struct vmcs12 *vmcs12;
6536 struct vcpu_vmx *vmx = to_vmx(vcpu);
6537 int cpu;
6538 struct loaded_vmcs *vmcs02;
6539
6540 if (!nested_vmx_check_permission(vcpu) ||
6541 !nested_vmx_check_vmcs12(vcpu))
6542 return 1;
6543
6544 skip_emulated_instruction(vcpu);
6545 vmcs12 = get_vmcs12(vcpu);
6546
7c177938
NHE		 6547 /*
6548 * The nested entry process starts with enforcing various prerequisites
6549 * on vmcs12 as required by the Intel SDM, and act appropriately when
6550 * they fail: As the SDM explains, some conditions should cause the
6551 * instruction to fail, while others will cause the instruction to seem
6552 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6553 * To speed up the normal (success) code path, we should avoid checking
6554 * for misconfigurations which will anyway be caught by the processor
6555 * when using the merged vmcs02.
6556 */
6557 if (vmcs12->launch_state == launch) {
6558 nested_vmx_failValid(vcpu,
6559 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6560 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6561 return 1;
6562 }
6563
6564 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6565 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6566 /*TODO: Also verify bits beyond physical address width are 0*/
6567 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6568 return 1;
6569 }
6570
6571 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6572 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6573 /*TODO: Also verify bits beyond physical address width are 0*/
6574 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6575 return 1;
6576 }
6577
6578 if (vmcs12->vm_entry_msr_load_count > 0 ||
6579 vmcs12->vm_exit_msr_load_count > 0 ||
6580 vmcs12->vm_exit_msr_store_count > 0) {
6581 if (printk_ratelimit())
6582 printk(KERN_WARNING
6583 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6584 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6585 return 1;
6586 }
6587
6588 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6589 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6590 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6591 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6592 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6593 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6594 !vmx_control_verify(vmcs12->vm_exit_controls,
6595 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6596 !vmx_control_verify(vmcs12->vm_entry_controls,
6597 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6598 {
6599 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6600 return 1;
6601 }
6602
6603 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6604 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6605 nested_vmx_failValid(vcpu,
6606 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6607 return 1;
6608 }
6609
6610 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6611 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6612 nested_vmx_entry_failure(vcpu, vmcs12,
6613 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6614 return 1;
6615 }
6616 if (vmcs12->vmcs_link_pointer != -1ull) {
6617 nested_vmx_entry_failure(vcpu, vmcs12,
6618 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6619 return 1;
6620 }
6621
6622 /*
6623 * We're finally done with prerequisite checking, and can start with
6624 * the nested entry.
6625 */
6626
cd232ad0
NHE		 6627 vmcs02 = nested_get_current_vmcs02(vmx);
6628 if (!vmcs02)
6629 return -ENOMEM;
6630
6631 enter_guest_mode(vcpu);
6632
6633 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6634
6635 cpu = get_cpu();
6636 vmx->loaded_vmcs = vmcs02;
6637 vmx_vcpu_put(vcpu);
6638 vmx_vcpu_load(vcpu, cpu);
6639 vcpu->cpu = cpu;
6640 put_cpu();
6641
6642 vmcs12->launch_state = 1;
6643
6644 prepare_vmcs02(vcpu, vmcs12);
6645
6646 /*
6647 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6648 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6649 * returned as far as L1 is concerned. It will only return (and set
6650 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6651 */
6652 return 1;
6653}
6654
4704d0be
NHE		 6655/*
6656 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6657 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6658 * This function returns the new value we should put in vmcs12.guest_cr0.
6659 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6660 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6661 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6662 * didn't trap the bit, because if L1 did, so would L0).
6663 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6664 * been modified by L2, and L1 knows it. So just leave the old value of
6665 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6666 * isn't relevant, because if L0 traps this bit it can set it to anything.
6667 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6668 * changed these bits, and therefore they need to be updated, but L0
6669 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6670 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6671 */
6672static inline unsigned long
6673vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6674{
6675 return
6676 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6677 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6678 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6679 vcpu->arch.cr0_guest_owned_bits));
6680}
6681
6682static inline unsigned long
6683vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6684{
6685 return
6686 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6687 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6688 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6689 vcpu->arch.cr4_guest_owned_bits));
6690}
6691
6692/*
6693 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6694 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6695 * and this function updates it to reflect the changes to the guest state while
6696 * L2 was running (and perhaps made some exits which were handled directly by L0
6697 * without going back to L1), and to reflect the exit reason.
6698 * Note that we do not have to copy here all VMCS fields, just those that
6699 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6700 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6701 * which already writes to vmcs12 directly.
6702 */
6703void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6704{
6705 /* update guest state fields: */
6706 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6707 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6708
6709 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6710 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6711 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6712 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6713
6714 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6715 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6716 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6717 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6718 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6719 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6720 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6721 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6722 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6723 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6724 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6725 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6726 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6727 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6728 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6729 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6730 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6731 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6732 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6733 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6734 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6735 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6736 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6737 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6738 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6739 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6740 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6741 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6742 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6743 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6744 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6745 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6746 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6747 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6748 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6749 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6750
6751 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6752 vmcs12->guest_interruptibility_info =
6753 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6754 vmcs12->guest_pending_dbg_exceptions =
6755 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6756
6757 /* TODO: These cannot have changed unless we have MSR bitmaps and
6758 * the relevant bit asks not to trap the change */
6759 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6760 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6761 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6762 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6763 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6764 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6765
6766 /* update exit information fields: */
6767
6768 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6769 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6770
6771 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6772 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6773 vmcs12->idt_vectoring_info_field =
6774 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6775 vmcs12->idt_vectoring_error_code =
6776 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6777 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6778 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6779
6780 /* clear vm-entry fields which are to be cleared on exit */
6781 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6782 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6783}
6784
6785/*
6786 * A part of what we need to when the nested L2 guest exits and we want to
6787 * run its L1 parent, is to reset L1's guest state to the host state specified
6788 * in vmcs12.
6789 * This function is to be called not only on normal nested exit, but also on
6790 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6791 * Failures During or After Loading Guest State").
6792 * This function should be called when the active VMCS is L1's (vmcs01).
6793 */
6794void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6795{
6796 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6797 vcpu->arch.efer = vmcs12->host_ia32_efer;
6798 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6799 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6800 else
6801 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6802 vmx_set_efer(vcpu, vcpu->arch.efer);
6803
6804 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6805 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6806 /*
6807 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6808 * actually changed, because it depends on the current state of
6809 * fpu_active (which may have changed).
6810 * Note that vmx_set_cr0 refers to efer set above.
6811 */
6812 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6813 /*
6814 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6815 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6816 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6817 */
6818 update_exception_bitmap(vcpu);
6819 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6820 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6821
6822 /*
6823 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6824 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6825 */
6826 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6827 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6828
6829 /* shadow page tables on either EPT or shadow page tables */
6830 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6831 kvm_mmu_reset_context(vcpu);
6832
6833 if (enable_vpid) {
6834 /*
6835 * Trivially support vpid by letting L2s share their parent
6836 * L1's vpid. TODO: move to a more elaborate solution, giving
6837 * each L2 its own vpid and exposing the vpid feature to L1.
6838 */
6839 vmx_flush_tlb(vcpu);
6840 }
6841
6842
6843 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6844 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6845 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6846 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6847 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6848 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6849 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6850 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6851 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6852 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6853 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6854 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6855 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6856 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6857 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6858
6859 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6860 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6861 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6862 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6863 vmcs12->host_ia32_perf_global_ctrl);
6864}
6865
6866/*
6867 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6868 * and modify vmcs12 to make it see what it would expect to see there if
6869 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6870 */
6871static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6872{
6873 struct vcpu_vmx *vmx = to_vmx(vcpu);
6874 int cpu;
6875 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6876
6877 leave_guest_mode(vcpu);
6878 prepare_vmcs12(vcpu, vmcs12);
6879
6880 cpu = get_cpu();
6881 vmx->loaded_vmcs = &vmx->vmcs01;
6882 vmx_vcpu_put(vcpu);
6883 vmx_vcpu_load(vcpu, cpu);
6884 vcpu->cpu = cpu;
6885 put_cpu();
6886
6887 /* if no vmcs02 cache requested, remove the one we used */
6888 if (VMCS02_POOL_SIZE == 0)
6889 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6890
6891 load_vmcs12_host_state(vcpu, vmcs12);
6892
6893 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6894 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6895
6896 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6897 vmx->host_rsp = 0;
6898
6899 /* Unpin physical memory we referred to in vmcs02 */
6900 if (vmx->nested.apic_access_page) {
6901 nested_release_page(vmx->nested.apic_access_page);
6902 vmx->nested.apic_access_page = 0;
6903 }
6904
6905 /*
6906 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6907 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6908 * success or failure flag accordingly.
6909 */
6910 if (unlikely(vmx->fail)) {
6911 vmx->fail = 0;
6912 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6913 } else
6914 nested_vmx_succeed(vcpu);
6915}
6916
7c177938
NHE		 6917/*
6918 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6919 * 23.7 "VM-entry failures during or after loading guest state" (this also
6920 * lists the acceptable exit-reason and exit-qualification parameters).
6921 * It should only be called before L2 actually succeeded to run, and when
6922 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6923 */
6924static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6925 struct vmcs12 *vmcs12,
6926 u32 reason, unsigned long qualification)
6927{
6928 load_vmcs12_host_state(vcpu, vmcs12);
6929 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6930 vmcs12->exit_qualification = qualification;
6931 nested_vmx_succeed(vcpu);
6932}
6933
8a76d7f2
JR		 6934static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6935 struct x86_instruction_info *info,
6936 enum x86_intercept_stage stage)
6937{
6938 return X86EMUL_CONTINUE;
6939}
6940
cbdd1bea 6941static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 6942 .cpu_has_kvm_support = cpu_has_kvm_support,
6943 .disabled_by_bios = vmx_disabled_by_bios,
6944 .hardware_setup = hardware_setup,
6945 .hardware_unsetup = hardware_unsetup,
002c7f7c 6946 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 6947 .hardware_enable = hardware_enable,
6948 .hardware_disable = hardware_disable,
04547156 6949 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 6950
6951 .vcpu_create = vmx_create_vcpu,
6952 .vcpu_free = vmx_free_vcpu,
04d2cc77 6953 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 6954
04d2cc77 6955 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 6956 .vcpu_load = vmx_vcpu_load,
6957 .vcpu_put = vmx_vcpu_put,
6958
6959 .set_guest_debug = set_guest_debug,
6960 .get_msr = vmx_get_msr,
6961 .set_msr = vmx_set_msr,
6962 .get_segment_base = vmx_get_segment_base,
6963 .get_segment = vmx_get_segment,
6964 .set_segment = vmx_set_segment,
2e4d2653 6965 .get_cpl = vmx_get_cpl,
6aa8b732 6966 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 6967 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 6968 .decache_cr3 = vmx_decache_cr3,
25c4c276 6969 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 6970 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 6971 .set_cr3 = vmx_set_cr3,
6972 .set_cr4 = vmx_set_cr4,
6aa8b732 6973 .set_efer = vmx_set_efer,
6aa8b732
AK		 6974 .get_idt = vmx_get_idt,
6975 .set_idt = vmx_set_idt,
6976 .get_gdt = vmx_get_gdt,
6977 .set_gdt = vmx_set_gdt,
020df079 6978 .set_dr7 = vmx_set_dr7,
5fdbf976 6979 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 6980 .get_rflags = vmx_get_rflags,
6981 .set_rflags = vmx_set_rflags,
ebcbab4c 6982 .fpu_activate = vmx_fpu_activate,
02daab21 6983 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 6984
6985 .tlb_flush = vmx_flush_tlb,
6aa8b732 6986
6aa8b732 6987 .run = vmx_vcpu_run,
6062d012 6988 .handle_exit = vmx_handle_exit,
6aa8b732 6989 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 6990 .set_interrupt_shadow = vmx_set_interrupt_shadow,
6991 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 6992 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 6993 .set_irq = vmx_inject_irq,
95ba8273 6994 .set_nmi = vmx_inject_nmi,
298101da 6995 .queue_exception = vmx_queue_exception,
b463a6f7 6996 .cancel_injection = vmx_cancel_injection,
78646121 6997 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 6998 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 6999 .get_nmi_mask = vmx_get_nmi_mask,
7000 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7001 .enable_nmi_window = enable_nmi_window,
7002 .enable_irq_window = enable_irq_window,
7003 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7004
cbc94022 7005 .set_tss_addr = vmx_set_tss_addr,
67253af5 7006 .get_tdp_level = get_ept_level,
4b12f0de 7007 .get_mt_mask = vmx_get_mt_mask,
229456fc 7008
586f9607 7009 .get_exit_info = vmx_get_exit_info,
229456fc 7010 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 7011
17cc3935 7012 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7013
7014 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7015
7016 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7017
7018 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7019
7020 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7021
4051b188 7022 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7023 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7024 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7025 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 7026
7027 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7028
7029 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7030};
7031
7032static int __init vmx_init(void)
7033{
26bb0981
AK		 7034 int r, i;
7035
7036 rdmsrl_safe(MSR_EFER, &host_efer);
7037
7038 for (i = 0; i < NR_VMX_MSR; ++i)
7039 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7040
3e7c73e9 7041 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7042 if (!vmx_io_bitmap_a)
7043 return -ENOMEM;
7044
3e7c73e9 7045 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7046 if (!vmx_io_bitmap_b) {
7047 r = -ENOMEM;
7048 goto out;
7049 }
7050
5897297b
AK		 7051 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7052 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7053 r = -ENOMEM;
7054 goto out1;
7055 }
7056
5897297b
AK		 7057 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7058 if (!vmx_msr_bitmap_longmode) {
7059 r = -ENOMEM;
7060 goto out2;
7061 }
7062
fdef3ad1
HQ		 7063 /*
7064 * Allow direct access to the PC debug port (it is often used for I/O
7065 * delays, but the vmexits simply slow things down).
7066 */
3e7c73e9
AK		 7067 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7068 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7069
3e7c73e9 7070 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7071
5897297b
AK		 7072 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7073 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7074
2384d2b3
SY		 7075 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7076
0ee75bea
AK		 7077 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7078 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7079 if (r)
5897297b 7080 goto out3;
25c5f225 7081
5897297b
AK		 7082 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7083 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7084 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7085 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7086 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7087 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7088
089d034e 7089 if (enable_ept) {
1439442c 7090 bypass_guest_pf = 0;
534e38b4 7091 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7092 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 7093 kvm_enable_tdp();
7094 } else
7095 kvm_disable_tdp();
1439442c 7096
c7addb90
AK		 7097 if (bypass_guest_pf)
7098 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
7099
fdef3ad1
HQ		 7100 return 0;
7101
5897297b
AK		 7102out3:
7103 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7104out2:
5897297b 7105 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7106out1:
3e7c73e9 7107 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7108out:
3e7c73e9 7109 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7110 return r;
6aa8b732
AK		 7111}
7112
7113static void __exit vmx_exit(void)
7114{
5897297b
AK		 7115 free_page((unsigned long)vmx_msr_bitmap_legacy);
7116 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7117 free_page((unsigned long)vmx_io_bitmap_b);
7118 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7119
cb498ea2 7120 kvm_exit();
6aa8b732
AK		 7121}
7122
7123module_init(vmx_init)
7124module_exit(vmx_exit)
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