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KVM: VMX: Trap and invalid MWAIT/MONITOR instruction
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
4b8d54f9
ZE		 64/*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75#define KVM_VMX_DEFAULT_PLE_GAP 41
76#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78module_param(ple_gap, int, S_IRUGO);
79
80static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81module_param(ple_window, int, S_IRUGO);
82
a2fa3e9f
GH		 83struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87};
88
26bb0981
AK		 89struct shared_msr_entry {
90 unsigned index;
91 u64 data;
d5696725 92 u64 mask;
26bb0981
AK		 93};
94
a2fa3e9f 95struct vcpu_vmx {
fb3f0f51 96 struct kvm_vcpu vcpu;
543e4243 97 struct list_head local_vcpus_link;
313dbd49 98 unsigned long host_rsp;
a2fa3e9f 99 int launched;
29bd8a78 100 u8 fail;
1155f76a 101 u32 idt_vectoring_info;
26bb0981 102 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 103 int nmsrs;
104 int save_nmsrs;
a2fa3e9f 105#ifdef CONFIG_X86_64
44ea2b17
AK		 106 u64 msr_host_kernel_gs_base;
107 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 108#endif
109 struct vmcs *vmcs;
110 struct {
111 int loaded;
112 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 113 int gs_ldt_reload_needed;
114 int fs_reload_needed;
d77c26fc 115 } host_state;
9c8cba37 116 struct {
7ffd92c5
AK		 117 int vm86_active;
118 u8 save_iopl;
119 struct kvm_save_segment {
120 u16 selector;
121 unsigned long base;
122 u32 limit;
123 u32 ar;
124 } tr, es, ds, fs, gs;
9c8cba37
AK		 125 struct {
126 bool pending;
127 u8 vector;
128 unsigned rip;
129 } irq;
130 } rmode;
2384d2b3 131 int vpid;
04fa4d32 132 bool emulation_required;
3b86cd99
JK		 133
134 /* Support for vnmi-less CPUs */
135 int soft_vnmi_blocked;
136 ktime_t entry_time;
137 s64 vnmi_blocked_time;
a0861c02 138 u32 exit_reason;
a2fa3e9f
GH		 139};
140
141static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
142{
fb3f0f51 143 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 144}
145
b7ebfb05 146static int init_rmode(struct kvm *kvm);
4e1096d2 147static u64 construct_eptp(unsigned long root_hpa);
75880a01 148
6aa8b732
AK		 149static DEFINE_PER_CPU(struct vmcs *, vmxarea);
150static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 151static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 152
3e7c73e9
AK		 153static unsigned long *vmx_io_bitmap_a;
154static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 155static unsigned long *vmx_msr_bitmap_legacy;
156static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 157
2384d2b3
SY		 158static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
159static DEFINE_SPINLOCK(vmx_vpid_lock);
160
1c3d14fe 161static struct vmcs_config {
6aa8b732
AK		 162 int size;
163 int order;
164 u32 revision_id;
1c3d14fe
YS		 165 u32 pin_based_exec_ctrl;
166 u32 cpu_based_exec_ctrl;
f78e0e2e 167 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 168 u32 vmexit_ctrl;
169 u32 vmentry_ctrl;
170} vmcs_config;
6aa8b732 171
efff9e53 172static struct vmx_capability {
d56f546d
SY		 173 u32 ept;
174 u32 vpid;
175} vmx_capability;
176
6aa8b732
AK		 177#define VMX_SEGMENT_FIELD(seg) \
178 [VCPU_SREG_##seg] = { \
179 .selector = GUEST_##seg##_SELECTOR, \
180 .base = GUEST_##seg##_BASE, \
181 .limit = GUEST_##seg##_LIMIT, \
182 .ar_bytes = GUEST_##seg##_AR_BYTES, \
183 }
184
185static struct kvm_vmx_segment_field {
186 unsigned selector;
187 unsigned base;
188 unsigned limit;
189 unsigned ar_bytes;
190} kvm_vmx_segment_fields[] = {
191 VMX_SEGMENT_FIELD(CS),
192 VMX_SEGMENT_FIELD(DS),
193 VMX_SEGMENT_FIELD(ES),
194 VMX_SEGMENT_FIELD(FS),
195 VMX_SEGMENT_FIELD(GS),
196 VMX_SEGMENT_FIELD(SS),
197 VMX_SEGMENT_FIELD(TR),
198 VMX_SEGMENT_FIELD(LDTR),
199};
200
26bb0981
AK		 201static u64 host_efer;
202
6de4f3ad
AK		 203static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
204
4d56c8a7
AK		 205/*
206 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
207 * away by decrementing the array size.
208 */
6aa8b732 209static const u32 vmx_msr_index[] = {
05b3e0c2 210#ifdef CONFIG_X86_64
44ea2b17 211 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 212#endif
213 MSR_EFER, MSR_K6_STAR,
214};
9d8f549d 215#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 216
6aa8b732
AK		 217static inline int is_page_fault(u32 intr_info)
218{
219 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
220 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 221 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 222}
223
2ab455cc
AL		 224static inline int is_no_device(u32 intr_info)
225{
226 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
227 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 228 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 229}
230
7aa81cc0
AL		 231static inline int is_invalid_opcode(u32 intr_info)
232{
233 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
234 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 235 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 236}
237
6aa8b732
AK		 238static inline int is_external_interrupt(u32 intr_info)
239{
240 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
241 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
242}
243
a0861c02
AK		 244static inline int is_machine_check(u32 intr_info)
245{
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
248 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
249}
250
25c5f225
SY		 251static inline int cpu_has_vmx_msr_bitmap(void)
252{
04547156 253 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 254}
255
6e5d865c
YS		 256static inline int cpu_has_vmx_tpr_shadow(void)
257{
04547156 258 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 259}
260
261static inline int vm_need_tpr_shadow(struct kvm *kvm)
262{
04547156 263 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 264}
265
f78e0e2e
SY		 266static inline int cpu_has_secondary_exec_ctrls(void)
267{
04547156
SY		 268 return vmcs_config.cpu_based_exec_ctrl &
269 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 270}
271
774ead3a 272static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 273{
04547156
SY		 274 return vmcs_config.cpu_based_2nd_exec_ctrl &
275 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
276}
277
278static inline bool cpu_has_vmx_flexpriority(void)
279{
280 return cpu_has_vmx_tpr_shadow() &&
281 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 282}
283
e799794e
MT		 284static inline bool cpu_has_vmx_ept_execute_only(void)
285{
286 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
287}
288
289static inline bool cpu_has_vmx_eptp_uncacheable(void)
290{
291 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
292}
293
294static inline bool cpu_has_vmx_eptp_writeback(void)
295{
296 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
297}
298
299static inline bool cpu_has_vmx_ept_2m_page(void)
300{
301 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
302}
303
d56f546d
SY		 304static inline int cpu_has_vmx_invept_individual_addr(void)
305{
04547156 306 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 307}
308
309static inline int cpu_has_vmx_invept_context(void)
310{
04547156 311 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 312}
313
314static inline int cpu_has_vmx_invept_global(void)
315{
04547156 316 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 317}
318
319static inline int cpu_has_vmx_ept(void)
320{
04547156
SY		 321 return vmcs_config.cpu_based_2nd_exec_ctrl &
322 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 323}
324
3a624e29
NK		 325static inline int cpu_has_vmx_unrestricted_guest(void)
326{
327 return vmcs_config.cpu_based_2nd_exec_ctrl &
328 SECONDARY_EXEC_UNRESTRICTED_GUEST;
329}
330
4b8d54f9
ZE		 331static inline int cpu_has_vmx_ple(void)
332{
333 return vmcs_config.cpu_based_2nd_exec_ctrl &
334 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
335}
336
f78e0e2e
SY		 337static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
338{
04547156
SY		 339 return flexpriority_enabled &&
340 (cpu_has_vmx_virtualize_apic_accesses()) &&
341 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 342}
343
2384d2b3
SY		 344static inline int cpu_has_vmx_vpid(void)
345{
04547156
SY		 346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 348}
349
f08864b4
SY		 350static inline int cpu_has_virtual_nmis(void)
351{
352 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
353}
354
04547156
SY		 355static inline bool report_flexpriority(void)
356{
357 return flexpriority_enabled;
358}
359
8b9cf98c 360static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 361{
362 int i;
363
a2fa3e9f 364 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 365 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 366 return i;
367 return -1;
368}
369
2384d2b3
SY		 370static inline void __invvpid(int ext, u16 vpid, gva_t gva)
371{
372 struct {
373 u64 vpid : 16;
374 u64 rsvd : 48;
375 u64 gva;
376 } operand = { vpid, 0, gva };
377
4ecac3fd 378 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 379 /* CF==1 or ZF==1 --> rc = -1 */
380 "; ja 1f ; ud2 ; 1:"
381 : : "a"(&operand), "c"(ext) : "cc", "memory");
382}
383
1439442c
SY		 384static inline void __invept(int ext, u64 eptp, gpa_t gpa)
385{
386 struct {
387 u64 eptp, gpa;
388 } operand = {eptp, gpa};
389
4ecac3fd 390 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 391 /* CF==1 or ZF==1 --> rc = -1 */
392 "; ja 1f ; ud2 ; 1:\n"
393 : : "a" (&operand), "c" (ext) : "cc", "memory");
394}
395
26bb0981 396static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 397{
398 int i;
399
8b9cf98c 400 i = __find_msr_index(vmx, msr);
a75beee6 401 if (i >= 0)
a2fa3e9f 402 return &vmx->guest_msrs[i];
8b6d44c7 403 return NULL;
7725f0ba
AK		 404}
405
6aa8b732
AK		 406static void vmcs_clear(struct vmcs *vmcs)
407{
408 u64 phys_addr = __pa(vmcs);
409 u8 error;
410
4ecac3fd 411 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 412 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
413 : "cc", "memory");
414 if (error)
415 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
416 vmcs, phys_addr);
417}
418
419static void __vcpu_clear(void *arg)
420{
8b9cf98c 421 struct vcpu_vmx *vmx = arg;
d3b2c338 422 int cpu = raw_smp_processor_id();
6aa8b732 423
8b9cf98c 424 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 425 vmcs_clear(vmx->vmcs);
426 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 427 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 428 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 429 list_del(&vmx->local_vcpus_link);
430 vmx->vcpu.cpu = -1;
431 vmx->launched = 0;
6aa8b732
AK		 432}
433
8b9cf98c 434static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 435{
eae5ecb5
AK		 436 if (vmx->vcpu.cpu == -1)
437 return;
8691e5a8 438 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 439}
440
2384d2b3
SY		 441static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
442{
443 if (vmx->vpid == 0)
444 return;
445
446 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
447}
448
1439442c
SY		 449static inline void ept_sync_global(void)
450{
451 if (cpu_has_vmx_invept_global())
452 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
453}
454
455static inline void ept_sync_context(u64 eptp)
456{
089d034e 457 if (enable_ept) {
1439442c
SY		 458 if (cpu_has_vmx_invept_context())
459 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
460 else
461 ept_sync_global();
462 }
463}
464
465static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
466{
089d034e 467 if (enable_ept) {
1439442c
SY		 468 if (cpu_has_vmx_invept_individual_addr())
469 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
470 eptp, gpa);
471 else
472 ept_sync_context(eptp);
473 }
474}
475
6aa8b732
AK		 476static unsigned long vmcs_readl(unsigned long field)
477{
478 unsigned long value;
479
4ecac3fd 480 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 481 : "=a"(value) : "d"(field) : "cc");
482 return value;
483}
484
485static u16 vmcs_read16(unsigned long field)
486{
487 return vmcs_readl(field);
488}
489
490static u32 vmcs_read32(unsigned long field)
491{
492 return vmcs_readl(field);
493}
494
495static u64 vmcs_read64(unsigned long field)
496{
05b3e0c2 497#ifdef CONFIG_X86_64
6aa8b732
AK		 498 return vmcs_readl(field);
499#else
500 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
501#endif
502}
503
e52de1b8
AK		 504static noinline void vmwrite_error(unsigned long field, unsigned long value)
505{
506 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
507 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
508 dump_stack();
509}
510
6aa8b732
AK		 511static void vmcs_writel(unsigned long field, unsigned long value)
512{
513 u8 error;
514
4ecac3fd 515 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 516 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 517 if (unlikely(error))
518 vmwrite_error(field, value);
6aa8b732
AK		 519}
520
521static void vmcs_write16(unsigned long field, u16 value)
522{
523 vmcs_writel(field, value);
524}
525
526static void vmcs_write32(unsigned long field, u32 value)
527{
528 vmcs_writel(field, value);
529}
530
531static void vmcs_write64(unsigned long field, u64 value)
532{
6aa8b732 533 vmcs_writel(field, value);
7682f2d0 534#ifndef CONFIG_X86_64
6aa8b732
AK		 535 asm volatile ("");
536 vmcs_writel(field+1, value >> 32);
537#endif
538}
539
2ab455cc
AL		 540static void vmcs_clear_bits(unsigned long field, u32 mask)
541{
542 vmcs_writel(field, vmcs_readl(field) & ~mask);
543}
544
545static void vmcs_set_bits(unsigned long field, u32 mask)
546{
547 vmcs_writel(field, vmcs_readl(field) | mask);
548}
549
abd3f2d6
AK		 550static void update_exception_bitmap(struct kvm_vcpu *vcpu)
551{
552 u32 eb;
553
a0861c02 554 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 555 if (!vcpu->fpu_active)
556 eb |= 1u << NM_VECTOR;
e8a48342
AK		 557 /*
558 * Unconditionally intercept #DB so we can maintain dr6 without
559 * reading it every exit.
560 */
561 eb |= 1u << DB_VECTOR;
d0bfb940 562 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 563 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
564 eb |= 1u << BP_VECTOR;
565 }
7ffd92c5 566 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 567 eb = ~0;
089d034e 568 if (enable_ept)
1439442c 569 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 570 vmcs_write32(EXCEPTION_BITMAP, eb);
571}
572
33ed6329
AK		 573static void reload_tss(void)
574{
33ed6329
AK		 575 /*
576 * VT restores TR but not its size. Useless.
577 */
578 struct descriptor_table gdt;
a5f61300 579 struct desc_struct *descs;
33ed6329 580
d6e88aec 581 kvm_get_gdt(&gdt);
33ed6329
AK		 582 descs = (void *)gdt.base;
583 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
584 load_TR_desc();
33ed6329
AK		 585}
586
92c0d900 587static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 588{
3a34a881 589 u64 guest_efer;
51c6cf66
AK		 590 u64 ignore_bits;
591
26bb0981 592 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 593
51c6cf66
AK		 594 /*
595 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
596 * outside long mode
597 */
598 ignore_bits = EFER_NX | EFER_SCE;
599#ifdef CONFIG_X86_64
600 ignore_bits |= EFER_LMA | EFER_LME;
601 /* SCE is meaningful only in long mode on Intel */
602 if (guest_efer & EFER_LMA)
603 ignore_bits &= ~(u64)EFER_SCE;
604#endif
51c6cf66
AK		 605 guest_efer &= ~ignore_bits;
606 guest_efer |= host_efer & ignore_bits;
26bb0981 607 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 608 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 609 return true;
51c6cf66
AK		 610}
611
04d2cc77 612static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 613{
04d2cc77 614 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 615 int i;
04d2cc77 616
a2fa3e9f 617 if (vmx->host_state.loaded)
33ed6329
AK		 618 return;
619
a2fa3e9f 620 vmx->host_state.loaded = 1;
33ed6329
AK		 621 /*
622 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
623 * allow segment selectors with cpl > 0 or ti == 1.
624 */
d6e88aec 625 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 626 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 627 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 628 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 629 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 630 vmx->host_state.fs_reload_needed = 0;
631 } else {
33ed6329 632 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 633 vmx->host_state.fs_reload_needed = 1;
33ed6329 634 }
d6e88aec 635 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 636 if (!(vmx->host_state.gs_sel & 7))
637 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 638 else {
639 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 640 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 641 }
642
643#ifdef CONFIG_X86_64
644 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
645 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
646#else
a2fa3e9f
GH		 647 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
648 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 649#endif
707c0874
AK		 650
651#ifdef CONFIG_X86_64
44ea2b17
AK		 652 if (is_long_mode(&vmx->vcpu)) {
653 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
654 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
655 }
707c0874 656#endif
26bb0981
AK		 657 for (i = 0; i < vmx->save_nmsrs; ++i)
658 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 659 vmx->guest_msrs[i].data,
660 vmx->guest_msrs[i].mask);
33ed6329
AK		 661}
662
a9b21b62 663static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 664{
15ad7146 665 unsigned long flags;
33ed6329 666
a2fa3e9f 667 if (!vmx->host_state.loaded)
33ed6329
AK		 668 return;
669
e1beb1d3 670 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 671 vmx->host_state.loaded = 0;
152d3f2f 672 if (vmx->host_state.fs_reload_needed)
d6e88aec 673 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 674 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 675 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 676 /*
677 * If we have to reload gs, we must take care to
678 * preserve our gs base.
679 */
15ad7146 680 local_irq_save(flags);
d6e88aec 681 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 682#ifdef CONFIG_X86_64
683 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
684#endif
15ad7146 685 local_irq_restore(flags);
33ed6329 686 }
152d3f2f 687 reload_tss();
44ea2b17
AK		 688#ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
691 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
692 }
693#endif
33ed6329
AK		 694}
695
a9b21b62
AK		 696static void vmx_load_host_state(struct vcpu_vmx *vmx)
697{
698 preempt_disable();
699 __vmx_load_host_state(vmx);
700 preempt_enable();
701}
702
6aa8b732
AK		 703/*
704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
705 * vcpu mutex is already taken.
706 */
15ad7146 707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 708{
a2fa3e9f
GH		 709 struct vcpu_vmx *vmx = to_vmx(vcpu);
710 u64 phys_addr = __pa(vmx->vmcs);
019960ae 711 u64 tsc_this, delta, new_offset;
6aa8b732 712
a3d7f85f 713 if (vcpu->cpu != cpu) {
8b9cf98c 714 vcpu_clear(vmx);
2f599714 715 kvm_migrate_timers(vcpu);
eb5109e3 716 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 717 local_irq_disable();
718 list_add(&vmx->local_vcpus_link,
719 &per_cpu(vcpus_on_cpu, cpu));
720 local_irq_enable();
a3d7f85f 721 }
6aa8b732 722
a2fa3e9f 723 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 724 u8 error;
725
a2fa3e9f 726 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 727 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 728 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
729 : "cc");
730 if (error)
731 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 732 vmx->vmcs, phys_addr);
6aa8b732
AK		 733 }
734
735 if (vcpu->cpu != cpu) {
736 struct descriptor_table dt;
737 unsigned long sysenter_esp;
738
739 vcpu->cpu = cpu;
740 /*
741 * Linux uses per-cpu TSS and GDT, so set these when switching
742 * processors.
743 */
d6e88aec
AK		 744 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
745 kvm_get_gdt(&dt);
6aa8b732
AK		 746 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
747
748 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
749 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 750
751 /*
752 * Make sure the time stamp counter is monotonous.
753 */
754 rdtscll(tsc_this);
019960ae
AK		 755 if (tsc_this < vcpu->arch.host_tsc) {
756 delta = vcpu->arch.host_tsc - tsc_this;
757 new_offset = vmcs_read64(TSC_OFFSET) + delta;
758 vmcs_write64(TSC_OFFSET, new_offset);
759 }
6aa8b732 760 }
6aa8b732
AK		 761}
762
763static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
764{
a9b21b62 765 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 766}
767
5fd86fcf
AK		 768static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
769{
770 if (vcpu->fpu_active)
771 return;
772 vcpu->fpu_active = 1;
707d92fa 773 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 774 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 775 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 776 update_exception_bitmap(vcpu);
777}
778
779static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
780{
781 if (!vcpu->fpu_active)
782 return;
783 vcpu->fpu_active = 0;
707d92fa 784 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 785 update_exception_bitmap(vcpu);
786}
787
6aa8b732
AK		 788static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
789{
345dcaa8
AK		 790 unsigned long rflags;
791
792 rflags = vmcs_readl(GUEST_RFLAGS);
793 if (to_vmx(vcpu)->rmode.vm86_active)
794 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
795 return rflags;
6aa8b732
AK		 796}
797
798static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799{
7ffd92c5 800 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 801 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 802 vmcs_writel(GUEST_RFLAGS, rflags);
803}
804
2809f5d2
GC		 805static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
806{
807 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
808 int ret = 0;
809
810 if (interruptibility & GUEST_INTR_STATE_STI)
811 ret |= X86_SHADOW_INT_STI;
812 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
813 ret |= X86_SHADOW_INT_MOV_SS;
814
815 return ret & mask;
816}
817
818static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819{
820 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 u32 interruptibility = interruptibility_old;
822
823 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
824
825 if (mask & X86_SHADOW_INT_MOV_SS)
826 interruptibility |= GUEST_INTR_STATE_MOV_SS;
827 if (mask & X86_SHADOW_INT_STI)
828 interruptibility |= GUEST_INTR_STATE_STI;
829
830 if ((interruptibility != interruptibility_old))
831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
832}
833
6aa8b732
AK		 834static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
835{
836 unsigned long rip;
6aa8b732 837
5fdbf976 838 rip = kvm_rip_read(vcpu);
6aa8b732 839 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 840 kvm_rip_write(vcpu, rip);
6aa8b732 841
2809f5d2
GC		 842 /* skipping an emulated instruction also counts */
843 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 844}
845
298101da
AK		 846static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
847 bool has_error_code, u32 error_code)
848{
77ab6db0 849 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 850 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 851
8ab2d2e2 852 if (has_error_code) {
77ab6db0 853 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 854 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
855 }
77ab6db0 856
7ffd92c5 857 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 858 vmx->rmode.irq.pending = true;
859 vmx->rmode.irq.vector = nr;
860 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 861 if (kvm_exception_is_soft(nr))
862 vmx->rmode.irq.rip +=
863 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 864 intr_info |= INTR_TYPE_SOFT_INTR;
865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
868 return;
869 }
870
66fd3f7f
GN		 871 if (kvm_exception_is_soft(nr)) {
872 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
873 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 874 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
875 } else
876 intr_info |= INTR_TYPE_HARD_EXCEPTION;
877
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 879}
880
a75beee6
ED		 881/*
882 * Swap MSR entry in host/guest MSR entry array.
883 */
8b9cf98c 884static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 885{
26bb0981 886 struct shared_msr_entry tmp;
a2fa3e9f
GH		 887
888 tmp = vmx->guest_msrs[to];
889 vmx->guest_msrs[to] = vmx->guest_msrs[from];
890 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 891}
892
e38aea3e
AK		 893/*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
8b9cf98c 898static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 899{
26bb0981 900 int save_nmsrs, index;
5897297b 901 unsigned long *msr_bitmap;
e38aea3e 902
33f9c505 903 vmx_load_host_state(vmx);
a75beee6
ED		 904 save_nmsrs = 0;
905#ifdef CONFIG_X86_64
8b9cf98c 906 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 907 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 908 if (index >= 0)
8b9cf98c
RR		 909 move_msr_up(vmx, index, save_nmsrs++);
910 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 911 if (index >= 0)
8b9cf98c
RR		 912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 914 if (index >= 0)
8b9cf98c 915 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 916 /*
917 * MSR_K6_STAR is only needed on long mode guests, and only
918 * if efer.sce is enabled.
919 */
8b9cf98c 920 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 921 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 922 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 923 }
924#endif
92c0d900
AK		 925 index = __find_msr_index(vmx, MSR_EFER);
926 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 927 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 928
26bb0981 929 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 930
931 if (cpu_has_vmx_msr_bitmap()) {
932 if (is_long_mode(&vmx->vcpu))
933 msr_bitmap = vmx_msr_bitmap_longmode;
934 else
935 msr_bitmap = vmx_msr_bitmap_legacy;
936
937 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
938 }
e38aea3e
AK		 939}
940
6aa8b732
AK		 941/*
942 * reads and returns guest's timestamp counter "register"
943 * guest_tsc = host_tsc + tsc_offset -- 21.3
944 */
945static u64 guest_read_tsc(void)
946{
947 u64 host_tsc, tsc_offset;
948
949 rdtscll(host_tsc);
950 tsc_offset = vmcs_read64(TSC_OFFSET);
951 return host_tsc + tsc_offset;
952}
953
954/*
955 * writes 'guest_tsc' into guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
957 */
53f658b3 958static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 959{
6aa8b732
AK		 960 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
961}
962
6aa8b732
AK		 963/*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969{
970 u64 data;
26bb0981 971 struct shared_msr_entry *msr;
6aa8b732
AK		 972
973 if (!pdata) {
974 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
975 return -EINVAL;
976 }
977
978 switch (msr_index) {
05b3e0c2 979#ifdef CONFIG_X86_64
6aa8b732
AK		 980 case MSR_FS_BASE:
981 data = vmcs_readl(GUEST_FS_BASE);
982 break;
983 case MSR_GS_BASE:
984 data = vmcs_readl(GUEST_GS_BASE);
985 break;
44ea2b17
AK		 986 case MSR_KERNEL_GS_BASE:
987 vmx_load_host_state(to_vmx(vcpu));
988 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
989 break;
26bb0981 990#endif
6aa8b732 991 case MSR_EFER:
3bab1f5d 992 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 993 case MSR_IA32_TSC:
6aa8b732
AK		 994 data = guest_read_tsc();
995 break;
996 case MSR_IA32_SYSENTER_CS:
997 data = vmcs_read32(GUEST_SYSENTER_CS);
998 break;
999 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1000 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1001 break;
1002 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1003 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1004 break;
6aa8b732 1005 default:
26bb0981 1006 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1007 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1008 if (msr) {
542423b0 1009 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1010 data = msr->data;
1011 break;
6aa8b732 1012 }
3bab1f5d 1013 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1014 }
1015
1016 *pdata = data;
1017 return 0;
1018}
1019
1020/*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
1025static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026{
a2fa3e9f 1027 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1028 struct shared_msr_entry *msr;
53f658b3 1029 u64 host_tsc;
2cc51560
ED		 1030 int ret = 0;
1031
6aa8b732 1032 switch (msr_index) {
3bab1f5d 1033 case MSR_EFER:
a9b21b62 1034 vmx_load_host_state(vmx);
2cc51560 1035 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1036 break;
16175a79 1037#ifdef CONFIG_X86_64
6aa8b732
AK		 1038 case MSR_FS_BASE:
1039 vmcs_writel(GUEST_FS_BASE, data);
1040 break;
1041 case MSR_GS_BASE:
1042 vmcs_writel(GUEST_GS_BASE, data);
1043 break;
44ea2b17
AK		 1044 case MSR_KERNEL_GS_BASE:
1045 vmx_load_host_state(vmx);
1046 vmx->msr_guest_kernel_gs_base = data;
1047 break;
6aa8b732
AK		 1048#endif
1049 case MSR_IA32_SYSENTER_CS:
1050 vmcs_write32(GUEST_SYSENTER_CS, data);
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1053 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1054 break;
1055 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1056 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1057 break;
af24a4e4 1058 case MSR_IA32_TSC:
53f658b3
MT		 1059 rdtscll(host_tsc);
1060 guest_write_tsc(data, host_tsc);
6aa8b732 1061 break;
468d472f
SY		 1062 case MSR_IA32_CR_PAT:
1063 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064 vmcs_write64(GUEST_IA32_PAT, data);
1065 vcpu->arch.pat = data;
1066 break;
1067 }
1068 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1069 default:
8b9cf98c 1070 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1071 if (msr) {
542423b0 1072 vmx_load_host_state(vmx);
3bab1f5d
AK		 1073 msr->data = data;
1074 break;
6aa8b732 1075 }
2cc51560 1076 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1077 }
1078
2cc51560 1079 return ret;
6aa8b732
AK		 1080}
1081
5fdbf976 1082static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1083{
5fdbf976
MT		 1084 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085 switch (reg) {
1086 case VCPU_REGS_RSP:
1087 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088 break;
1089 case VCPU_REGS_RIP:
1090 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091 break;
6de4f3ad
AK		 1092 case VCPU_EXREG_PDPTR:
1093 if (enable_ept)
1094 ept_save_pdptrs(vcpu);
1095 break;
5fdbf976
MT		 1096 default:
1097 break;
1098 }
6aa8b732
AK		 1099}
1100
355be0b9 1101static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1102{
ae675ef0
JK		 1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105 else
1106 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
abd3f2d6 1108 update_exception_bitmap(vcpu);
6aa8b732
AK		 1109}
1110
1111static __init int cpu_has_kvm_support(void)
1112{
6210e37b 1113 return cpu_has_vmx();
6aa8b732
AK		 1114}
1115
1116static __init int vmx_disabled_by_bios(void)
1117{
1118 u64 msr;
1119
1120 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1121 return (msr & (FEATURE_CONTROL_LOCKED |
1122 FEATURE_CONTROL_VMXON_ENABLED))
1123 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1124 /* locked but not enabled */
6aa8b732
AK		 1125}
1126
10474ae8 1127static int hardware_enable(void *garbage)
6aa8b732
AK		 1128{
1129 int cpu = raw_smp_processor_id();
1130 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131 u64 old;
1132
10474ae8
AG		 1133 if (read_cr4() & X86_CR4_VMXE)
1134 return -EBUSY;
1135
543e4243 1136 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1138 if ((old & (FEATURE_CONTROL_LOCKED |
1139 FEATURE_CONTROL_VMXON_ENABLED))
1140 != (FEATURE_CONTROL_LOCKED |
1141 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1142 /* enable and lock */
62b3ffb8 1143 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1144 FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1146 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1147 asm volatile (ASM_VMX_VMXON_RAX
1148 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1149 : "memory", "cc");
10474ae8
AG		 1150
1151 ept_sync_global();
1152
1153 return 0;
6aa8b732
AK		 1154}
1155
543e4243
AK		 1156static void vmclear_local_vcpus(void)
1157{
1158 int cpu = raw_smp_processor_id();
1159 struct vcpu_vmx *vmx, *n;
1160
1161 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162 local_vcpus_link)
1163 __vcpu_clear(vmx);
1164}
1165
710ff4a8
EH		 1166
1167/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168 * tricks.
1169 */
1170static void kvm_cpu_vmxoff(void)
6aa8b732 1171{
4ecac3fd 1172 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1173 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1174}
1175
710ff4a8
EH		 1176static void hardware_disable(void *garbage)
1177{
1178 vmclear_local_vcpus();
1179 kvm_cpu_vmxoff();
1180}
1181
1c3d14fe 1182static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1183 u32 msr, u32 *result)
1c3d14fe
YS		 1184{
1185 u32 vmx_msr_low, vmx_msr_high;
1186 u32 ctl = ctl_min | ctl_opt;
1187
1188 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1192
1193 /* Ensure minimum (required) set of control bits are supported. */
1194 if (ctl_min & ~ctl)
002c7f7c 1195 return -EIO;
1c3d14fe
YS		 1196
1197 *result = ctl;
1198 return 0;
1199}
1200
002c7f7c 1201static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1202{
1203 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1204 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1205 u32 _pin_based_exec_control = 0;
1206 u32 _cpu_based_exec_control = 0;
f78e0e2e 1207 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1208 u32 _vmexit_control = 0;
1209 u32 _vmentry_control = 0;
1210
1211 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1212 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214 &_pin_based_exec_control) < 0)
002c7f7c 1215 return -EIO;
1c3d14fe
YS		 1216
1217 min = CPU_BASED_HLT_EXITING |
1218#ifdef CONFIG_X86_64
1219 CPU_BASED_CR8_LOAD_EXITING |
1220 CPU_BASED_CR8_STORE_EXITING |
1221#endif
d56f546d
SY		 1222 CPU_BASED_CR3_LOAD_EXITING |
1223 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1224 CPU_BASED_USE_IO_BITMAPS |
1225 CPU_BASED_MOV_DR_EXITING |
a7052897 1226 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1227 CPU_BASED_MWAIT_EXITING |
1228 CPU_BASED_MONITOR_EXITING |
a7052897 1229 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1230 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1231 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1232 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1233 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1234 &_cpu_based_exec_control) < 0)
002c7f7c 1235 return -EIO;
6e5d865c
YS		 1236#ifdef CONFIG_X86_64
1237 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1238 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1239 ~CPU_BASED_CR8_STORE_EXITING;
1240#endif
f78e0e2e 1241 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1242 min2 = 0;
1243 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1244 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1245 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1246 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1247 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1248 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1249 if (adjust_vmx_controls(min2, opt2,
1250 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1251 &_cpu_based_2nd_exec_control) < 0)
1252 return -EIO;
1253 }
1254#ifndef CONFIG_X86_64
1255 if (!(_cpu_based_2nd_exec_control &
1256 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1257 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1258#endif
d56f546d 1259 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1260 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1261 enabled */
5fff7d27
GN		 1262 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1263 CPU_BASED_CR3_STORE_EXITING |
1264 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1265 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1266 vmx_capability.ept, vmx_capability.vpid);
1267 }
1c3d14fe
YS		 1268
1269 min = 0;
1270#ifdef CONFIG_X86_64
1271 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1272#endif
468d472f 1273 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1274 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1275 &_vmexit_control) < 0)
002c7f7c 1276 return -EIO;
1c3d14fe 1277
468d472f
SY		 1278 min = 0;
1279 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1280 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1281 &_vmentry_control) < 0)
002c7f7c 1282 return -EIO;
6aa8b732 1283
c68876fd 1284 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1285
1286 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1287 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1288 return -EIO;
1c3d14fe
YS		 1289
1290#ifdef CONFIG_X86_64
1291 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1292 if (vmx_msr_high & (1u<<16))
002c7f7c 1293 return -EIO;
1c3d14fe
YS		 1294#endif
1295
1296 /* Require Write-Back (WB) memory type for VMCS accesses. */
1297 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1298 return -EIO;
1c3d14fe 1299
002c7f7c
YS		 1300 vmcs_conf->size = vmx_msr_high & 0x1fff;
1301 vmcs_conf->order = get_order(vmcs_config.size);
1302 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1303
002c7f7c
YS		 1304 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1305 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1306 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1307 vmcs_conf->vmexit_ctrl = _vmexit_control;
1308 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1309
1310 return 0;
c68876fd 1311}
6aa8b732
AK		 1312
1313static struct vmcs *alloc_vmcs_cpu(int cpu)
1314{
1315 int node = cpu_to_node(cpu);
1316 struct page *pages;
1317 struct vmcs *vmcs;
1318
6484eb3e 1319 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1320 if (!pages)
1321 return NULL;
1322 vmcs = page_address(pages);
1c3d14fe
YS		 1323 memset(vmcs, 0, vmcs_config.size);
1324 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1325 return vmcs;
1326}
1327
1328static struct vmcs *alloc_vmcs(void)
1329{
d3b2c338 1330 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1331}
1332
1333static void free_vmcs(struct vmcs *vmcs)
1334{
1c3d14fe 1335 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1336}
1337
39959588 1338static void free_kvm_area(void)
6aa8b732
AK		 1339{
1340 int cpu;
1341
3230bb47 1342 for_each_possible_cpu(cpu) {
6aa8b732 1343 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1344 per_cpu(vmxarea, cpu) = NULL;
1345 }
6aa8b732
AK		 1346}
1347
6aa8b732
AK		 1348static __init int alloc_kvm_area(void)
1349{
1350 int cpu;
1351
3230bb47 1352 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1353 struct vmcs *vmcs;
1354
1355 vmcs = alloc_vmcs_cpu(cpu);
1356 if (!vmcs) {
1357 free_kvm_area();
1358 return -ENOMEM;
1359 }
1360
1361 per_cpu(vmxarea, cpu) = vmcs;
1362 }
1363 return 0;
1364}
1365
1366static __init int hardware_setup(void)
1367{
002c7f7c
YS		 1368 if (setup_vmcs_config(&vmcs_config) < 0)
1369 return -EIO;
50a37eb4
JR		 1370
1371 if (boot_cpu_has(X86_FEATURE_NX))
1372 kvm_enable_efer_bits(EFER_NX);
1373
93ba03c2
SY		 1374 if (!cpu_has_vmx_vpid())
1375 enable_vpid = 0;
1376
3a624e29 1377 if (!cpu_has_vmx_ept()) {
93ba03c2 1378 enable_ept = 0;
3a624e29
NK		 1379 enable_unrestricted_guest = 0;
1380 }
1381
1382 if (!cpu_has_vmx_unrestricted_guest())
1383 enable_unrestricted_guest = 0;
93ba03c2
SY		 1384
1385 if (!cpu_has_vmx_flexpriority())
1386 flexpriority_enabled = 0;
1387
95ba8273
GN		 1388 if (!cpu_has_vmx_tpr_shadow())
1389 kvm_x86_ops->update_cr8_intercept = NULL;
1390
54dee993
MT		 1391 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1392 kvm_disable_largepages();
1393
4b8d54f9
ZE		 1394 if (!cpu_has_vmx_ple())
1395 ple_gap = 0;
1396
6aa8b732
AK		 1397 return alloc_kvm_area();
1398}
1399
1400static __exit void hardware_unsetup(void)
1401{
1402 free_kvm_area();
1403}
1404
6aa8b732
AK		 1405static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1406{
1407 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1408
6af11b9e 1409 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1410 vmcs_write16(sf->selector, save->selector);
1411 vmcs_writel(sf->base, save->base);
1412 vmcs_write32(sf->limit, save->limit);
1413 vmcs_write32(sf->ar_bytes, save->ar);
1414 } else {
1415 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1416 << AR_DPL_SHIFT;
1417 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1418 }
1419}
1420
1421static void enter_pmode(struct kvm_vcpu *vcpu)
1422{
1423 unsigned long flags;
a89a8fb9 1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1425
a89a8fb9 1426 vmx->emulation_required = 1;
7ffd92c5 1427 vmx->rmode.vm86_active = 0;
6aa8b732 1428
7ffd92c5
AK		 1429 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1430 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1431 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1432
1433 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1434 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1435 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1436 vmcs_writel(GUEST_RFLAGS, flags);
1437
66aee91a
RR		 1438 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1439 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1440
1441 update_exception_bitmap(vcpu);
1442
a89a8fb9
MG		 1443 if (emulate_invalid_guest_state)
1444 return;
1445
7ffd92c5
AK		 1446 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1447 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1448 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1449 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1450
1451 vmcs_write16(GUEST_SS_SELECTOR, 0);
1452 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1453
1454 vmcs_write16(GUEST_CS_SELECTOR,
1455 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1456 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1457}
1458
d77c26fc 1459static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1460{
bfc6d222 1461 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1462 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1463 kvm->memslots[0].npages - 3;
1464 return base_gfn << PAGE_SHIFT;
1465 }
bfc6d222 1466 return kvm->arch.tss_addr;
6aa8b732
AK		 1467}
1468
1469static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1470{
1471 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1472
1473 save->selector = vmcs_read16(sf->selector);
1474 save->base = vmcs_readl(sf->base);
1475 save->limit = vmcs_read32(sf->limit);
1476 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1477 vmcs_write16(sf->selector, save->base >> 4);
1478 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1479 vmcs_write32(sf->limit, 0xffff);
1480 vmcs_write32(sf->ar_bytes, 0xf3);
1481}
1482
1483static void enter_rmode(struct kvm_vcpu *vcpu)
1484{
1485 unsigned long flags;
a89a8fb9 1486 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1487
3a624e29
NK		 1488 if (enable_unrestricted_guest)
1489 return;
1490
a89a8fb9 1491 vmx->emulation_required = 1;
7ffd92c5 1492 vmx->rmode.vm86_active = 1;
6aa8b732 1493
7ffd92c5 1494 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1495 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1496
7ffd92c5 1497 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1498 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1499
7ffd92c5 1500 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1501 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1502
1503 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1504 vmx->rmode.save_iopl
ad312c7c 1505 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1506
053de044 1507 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1508
1509 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1510 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1511 update_exception_bitmap(vcpu);
1512
a89a8fb9
MG		 1513 if (emulate_invalid_guest_state)
1514 goto continue_rmode;
1515
6aa8b732
AK		 1516 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1517 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1518 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1519
1520 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1521 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1522 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1523 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1524 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1525
7ffd92c5
AK		 1526 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1527 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1528 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1529 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1530
a89a8fb9 1531continue_rmode:
8668a3c4 1532 kvm_mmu_reset_context(vcpu);
b7ebfb05 1533 init_rmode(vcpu->kvm);
6aa8b732
AK		 1534}
1535
401d10de
AS		 1536static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1537{
1538 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1539 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1540
1541 if (!msr)
1542 return;
401d10de 1543
44ea2b17
AK		 1544 /*
1545 * Force kernel_gs_base reloading before EFER changes, as control
1546 * of this msr depends on is_long_mode().
1547 */
1548 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1549 vcpu->arch.shadow_efer = efer;
1550 if (!msr)
1551 return;
1552 if (efer & EFER_LMA) {
1553 vmcs_write32(VM_ENTRY_CONTROLS,
1554 vmcs_read32(VM_ENTRY_CONTROLS) |
1555 VM_ENTRY_IA32E_MODE);
1556 msr->data = efer;
1557 } else {
1558 vmcs_write32(VM_ENTRY_CONTROLS,
1559 vmcs_read32(VM_ENTRY_CONTROLS) &
1560 ~VM_ENTRY_IA32E_MODE);
1561
1562 msr->data = efer & ~EFER_LME;
1563 }
1564 setup_msrs(vmx);
1565}
1566
05b3e0c2 1567#ifdef CONFIG_X86_64
6aa8b732
AK		 1568
1569static void enter_lmode(struct kvm_vcpu *vcpu)
1570{
1571 u32 guest_tr_ar;
1572
1573 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1574 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1575 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1576 __func__);
6aa8b732
AK		 1577 vmcs_write32(GUEST_TR_AR_BYTES,
1578 (guest_tr_ar & ~AR_TYPE_MASK)
1579 | AR_TYPE_BUSY_64_TSS);
1580 }
ad312c7c 1581 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1582 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1583}
1584
1585static void exit_lmode(struct kvm_vcpu *vcpu)
1586{
ad312c7c 1587 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1588
1589 vmcs_write32(VM_ENTRY_CONTROLS,
1590 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1591 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1592}
1593
1594#endif
1595
2384d2b3
SY		 1596static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1597{
1598 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1599 if (enable_ept)
4e1096d2 1600 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1601}
1602
25c4c276 1603static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1604{
ad312c7c
ZX		 1605 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1606 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1607}
1608
1439442c
SY		 1609static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1610{
6de4f3ad
AK		 1611 if (!test_bit(VCPU_EXREG_PDPTR,
1612 (unsigned long *)&vcpu->arch.regs_dirty))
1613 return;
1614
1439442c 1615 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1616 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1617 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1618 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1619 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1620 }
1621}
1622
8f5d549f
AK		 1623static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1624{
1625 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1626 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1627 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1628 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1629 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1630 }
6de4f3ad
AK		 1631
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_avail);
1634 __set_bit(VCPU_EXREG_PDPTR,
1635 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1636}
1637
1439442c
SY		 1638static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1639
1640static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1641 unsigned long cr0,
1642 struct kvm_vcpu *vcpu)
1643{
1644 if (!(cr0 & X86_CR0_PG)) {
1645 /* From paging/starting to nonpaging */
1646 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1647 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1648 (CPU_BASED_CR3_LOAD_EXITING |
1649 CPU_BASED_CR3_STORE_EXITING));
1650 vcpu->arch.cr0 = cr0;
1651 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c
SY		 1652 } else if (!is_paging(vcpu)) {
1653 /* From nonpaging to paging */
1654 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1655 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1656 ~(CPU_BASED_CR3_LOAD_EXITING |
1657 CPU_BASED_CR3_STORE_EXITING));
1658 vcpu->arch.cr0 = cr0;
1659 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1439442c 1660 }
95eb84a7
SY		 1661
1662 if (!(cr0 & X86_CR0_WP))
1663 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1664}
1665
1666static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1667 struct kvm_vcpu *vcpu)
1668{
1669 if (!is_paging(vcpu)) {
1670 *hw_cr4 &= ~X86_CR4_PAE;
1671 *hw_cr4 |= X86_CR4_PSE;
1672 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1673 *hw_cr4 &= ~X86_CR4_PAE;
1674}
1675
6aa8b732
AK		 1676static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1677{
7ffd92c5 1678 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1679 unsigned long hw_cr0;
1680
1681 if (enable_unrestricted_guest)
1682 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1683 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1684 else
1685 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1686
5fd86fcf
AK		 1687 vmx_fpu_deactivate(vcpu);
1688
7ffd92c5 1689 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1690 enter_pmode(vcpu);
1691
7ffd92c5 1692 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1693 enter_rmode(vcpu);
1694
05b3e0c2 1695#ifdef CONFIG_X86_64
ad312c7c 1696 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1697 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1698 enter_lmode(vcpu);
707d92fa 1699 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1700 exit_lmode(vcpu);
1701 }
1702#endif
1703
089d034e 1704 if (enable_ept)
1439442c
SY		 1705 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1706
6aa8b732 1707 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1708 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1709 vcpu->arch.cr0 = cr0;
5fd86fcf 1710
707d92fa 1711 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1712 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1713}
1714
1439442c
SY		 1715static u64 construct_eptp(unsigned long root_hpa)
1716{
1717 u64 eptp;
1718
1719 /* TODO write the value reading from MSR */
1720 eptp = VMX_EPT_DEFAULT_MT |
1721 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1722 eptp |= (root_hpa & PAGE_MASK);
1723
1724 return eptp;
1725}
1726
6aa8b732
AK		 1727static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1728{
1439442c
SY		 1729 unsigned long guest_cr3;
1730 u64 eptp;
1731
1732 guest_cr3 = cr3;
089d034e 1733 if (enable_ept) {
1439442c
SY		 1734 eptp = construct_eptp(cr3);
1735 vmcs_write64(EPT_POINTER, eptp);
1439442c 1736 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1737 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1738 ept_load_pdptrs(vcpu);
1439442c
SY		 1739 }
1740
2384d2b3 1741 vmx_flush_tlb(vcpu);
1439442c 1742 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1743 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1744 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1745}
1746
1747static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1748{
7ffd92c5 1749 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1750 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1751
ad312c7c 1752 vcpu->arch.cr4 = cr4;
089d034e 1753 if (enable_ept)
1439442c
SY		 1754 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1755
1756 vmcs_writel(CR4_READ_SHADOW, cr4);
1757 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1758}
1759
6aa8b732
AK		 1760static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1761{
1762 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1763
1764 return vmcs_readl(sf->base);
1765}
1766
1767static void vmx_get_segment(struct kvm_vcpu *vcpu,
1768 struct kvm_segment *var, int seg)
1769{
1770 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1771 u32 ar;
1772
1773 var->base = vmcs_readl(sf->base);
1774 var->limit = vmcs_read32(sf->limit);
1775 var->selector = vmcs_read16(sf->selector);
1776 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1777 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1778 ar = 0;
1779 var->type = ar & 15;
1780 var->s = (ar >> 4) & 1;
1781 var->dpl = (ar >> 5) & 3;
1782 var->present = (ar >> 7) & 1;
1783 var->avl = (ar >> 12) & 1;
1784 var->l = (ar >> 13) & 1;
1785 var->db = (ar >> 14) & 1;
1786 var->g = (ar >> 15) & 1;
1787 var->unusable = (ar >> 16) & 1;
1788}
1789
2e4d2653
IE		 1790static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1791{
2e4d2653
IE		 1792 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1793 return 0;
1794
1795 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1796 return 3;
1797
eab4b8aa 1798 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1799}
1800
653e3108 1801static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1802{
6aa8b732
AK		 1803 u32 ar;
1804
653e3108 1805 if (var->unusable)
6aa8b732
AK		 1806 ar = 1 << 16;
1807 else {
1808 ar = var->type & 15;
1809 ar |= (var->s & 1) << 4;
1810 ar |= (var->dpl & 3) << 5;
1811 ar |= (var->present & 1) << 7;
1812 ar |= (var->avl & 1) << 12;
1813 ar |= (var->l & 1) << 13;
1814 ar |= (var->db & 1) << 14;
1815 ar |= (var->g & 1) << 15;
1816 }
f7fbf1fd
UL		 1817 if (ar == 0) /* a 0 value means unusable */
1818 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1819
1820 return ar;
1821}
1822
1823static void vmx_set_segment(struct kvm_vcpu *vcpu,
1824 struct kvm_segment *var, int seg)
1825{
7ffd92c5 1826 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1827 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1828 u32 ar;
1829
7ffd92c5
AK		 1830 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1831 vmx->rmode.tr.selector = var->selector;
1832 vmx->rmode.tr.base = var->base;
1833 vmx->rmode.tr.limit = var->limit;
1834 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1835 return;
1836 }
1837 vmcs_writel(sf->base, var->base);
1838 vmcs_write32(sf->limit, var->limit);
1839 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1840 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1841 /*
1842 * Hack real-mode segments into vm86 compatibility.
1843 */
1844 if (var->base == 0xffff0000 && var->selector == 0xf000)
1845 vmcs_writel(sf->base, 0xf0000);
1846 ar = 0xf3;
1847 } else
1848 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1849
1850 /*
1851 * Fix the "Accessed" bit in AR field of segment registers for older
1852 * qemu binaries.
1853 * IA32 arch specifies that at the time of processor reset the
1854 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1855 * is setting it to 0 in the usedland code. This causes invalid guest
1856 * state vmexit when "unrestricted guest" mode is turned on.
1857 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1858 * tree. Newer qemu binaries with that qemu fix would not need this
1859 * kvm hack.
1860 */
1861 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1862 ar |= 0x1; /* Accessed */
1863
6aa8b732
AK		 1864 vmcs_write32(sf->ar_bytes, ar);
1865}
1866
6aa8b732
AK		 1867static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1868{
1869 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1870
1871 *db = (ar >> 14) & 1;
1872 *l = (ar >> 13) & 1;
1873}
1874
1875static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1876{
1877 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1878 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1879}
1880
1881static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1882{
1883 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1884 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1885}
1886
1887static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1888{
1889 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1890 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1891}
1892
1893static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1894{
1895 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1896 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1897}
1898
648dfaa7
MG		 1899static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1900{
1901 struct kvm_segment var;
1902 u32 ar;
1903
1904 vmx_get_segment(vcpu, &var, seg);
1905 ar = vmx_segment_access_rights(&var);
1906
1907 if (var.base != (var.selector << 4))
1908 return false;
1909 if (var.limit != 0xffff)
1910 return false;
1911 if (ar != 0xf3)
1912 return false;
1913
1914 return true;
1915}
1916
1917static bool code_segment_valid(struct kvm_vcpu *vcpu)
1918{
1919 struct kvm_segment cs;
1920 unsigned int cs_rpl;
1921
1922 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1923 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1924
1872a3f4
AK		 1925 if (cs.unusable)
1926 return false;
648dfaa7
MG		 1927 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1928 return false;
1929 if (!cs.s)
1930 return false;
1872a3f4 1931 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1932 if (cs.dpl > cs_rpl)
1933 return false;
1872a3f4 1934 } else {
648dfaa7
MG		 1935 if (cs.dpl != cs_rpl)
1936 return false;
1937 }
1938 if (!cs.present)
1939 return false;
1940
1941 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1942 return true;
1943}
1944
1945static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1946{
1947 struct kvm_segment ss;
1948 unsigned int ss_rpl;
1949
1950 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1951 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1952
1872a3f4
AK		 1953 if (ss.unusable)
1954 return true;
1955 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1956 return false;
1957 if (!ss.s)
1958 return false;
1959 if (ss.dpl != ss_rpl) /* DPL != RPL */
1960 return false;
1961 if (!ss.present)
1962 return false;
1963
1964 return true;
1965}
1966
1967static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1968{
1969 struct kvm_segment var;
1970 unsigned int rpl;
1971
1972 vmx_get_segment(vcpu, &var, seg);
1973 rpl = var.selector & SELECTOR_RPL_MASK;
1974
1872a3f4
AK		 1975 if (var.unusable)
1976 return true;
648dfaa7
MG		 1977 if (!var.s)
1978 return false;
1979 if (!var.present)
1980 return false;
1981 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1982 if (var.dpl < rpl) /* DPL < RPL */
1983 return false;
1984 }
1985
1986 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1987 * rights flags
1988 */
1989 return true;
1990}
1991
1992static bool tr_valid(struct kvm_vcpu *vcpu)
1993{
1994 struct kvm_segment tr;
1995
1996 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1997
1872a3f4
AK		 1998 if (tr.unusable)
1999 return false;
648dfaa7
MG		 2000 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2001 return false;
1872a3f4 2002 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2003 return false;
2004 if (!tr.present)
2005 return false;
2006
2007 return true;
2008}
2009
2010static bool ldtr_valid(struct kvm_vcpu *vcpu)
2011{
2012 struct kvm_segment ldtr;
2013
2014 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2015
1872a3f4
AK		 2016 if (ldtr.unusable)
2017 return true;
648dfaa7
MG		 2018 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2019 return false;
2020 if (ldtr.type != 2)
2021 return false;
2022 if (!ldtr.present)
2023 return false;
2024
2025 return true;
2026}
2027
2028static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2029{
2030 struct kvm_segment cs, ss;
2031
2032 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2033 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2034
2035 return ((cs.selector & SELECTOR_RPL_MASK) ==
2036 (ss.selector & SELECTOR_RPL_MASK));
2037}
2038
2039/*
2040 * Check if guest state is valid. Returns true if valid, false if
2041 * not.
2042 * We assume that registers are always usable
2043 */
2044static bool guest_state_valid(struct kvm_vcpu *vcpu)
2045{
2046 /* real mode guest state checks */
2047 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2048 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2049 return false;
2050 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2051 return false;
2052 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2053 return false;
2054 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2055 return false;
2056 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2057 return false;
2058 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2059 return false;
2060 } else {
2061 /* protected mode guest state checks */
2062 if (!cs_ss_rpl_check(vcpu))
2063 return false;
2064 if (!code_segment_valid(vcpu))
2065 return false;
2066 if (!stack_segment_valid(vcpu))
2067 return false;
2068 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2069 return false;
2070 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2071 return false;
2072 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2073 return false;
2074 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2075 return false;
2076 if (!tr_valid(vcpu))
2077 return false;
2078 if (!ldtr_valid(vcpu))
2079 return false;
2080 }
2081 /* TODO:
2082 * - Add checks on RIP
2083 * - Add checks on RFLAGS
2084 */
2085
2086 return true;
2087}
2088
d77c26fc 2089static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2090{
6aa8b732 2091 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2092 u16 data = 0;
10589a46 2093 int ret = 0;
195aefde 2094 int r;
6aa8b732 2095
195aefde
IE		 2096 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2097 if (r < 0)
10589a46 2098 goto out;
195aefde 2099 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2100 r = kvm_write_guest_page(kvm, fn++, &data,
2101 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2102 if (r < 0)
10589a46 2103 goto out;
195aefde
IE		 2104 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2105 if (r < 0)
10589a46 2106 goto out;
195aefde
IE		 2107 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2108 if (r < 0)
10589a46 2109 goto out;
195aefde 2110 data = ~0;
10589a46
MT		 2111 r = kvm_write_guest_page(kvm, fn, &data,
2112 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2113 sizeof(u8));
195aefde 2114 if (r < 0)
10589a46
MT		 2115 goto out;
2116
2117 ret = 1;
2118out:
10589a46 2119 return ret;
6aa8b732
AK		 2120}
2121
b7ebfb05
SY		 2122static int init_rmode_identity_map(struct kvm *kvm)
2123{
2124 int i, r, ret;
2125 pfn_t identity_map_pfn;
2126 u32 tmp;
2127
089d034e 2128 if (!enable_ept)
b7ebfb05
SY		 2129 return 1;
2130 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2131 printk(KERN_ERR "EPT: identity-mapping pagetable "
2132 "haven't been allocated!\n");
2133 return 0;
2134 }
2135 if (likely(kvm->arch.ept_identity_pagetable_done))
2136 return 1;
2137 ret = 0;
b927a3ce 2138 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2139 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2140 if (r < 0)
2141 goto out;
2142 /* Set up identity-mapping pagetable for EPT in real mode */
2143 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2144 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2145 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2146 r = kvm_write_guest_page(kvm, identity_map_pfn,
2147 &tmp, i * sizeof(tmp), sizeof(tmp));
2148 if (r < 0)
2149 goto out;
2150 }
2151 kvm->arch.ept_identity_pagetable_done = true;
2152 ret = 1;
2153out:
2154 return ret;
2155}
2156
6aa8b732
AK		 2157static void seg_setup(int seg)
2158{
2159 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2160 unsigned int ar;
6aa8b732
AK		 2161
2162 vmcs_write16(sf->selector, 0);
2163 vmcs_writel(sf->base, 0);
2164 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2165 if (enable_unrestricted_guest) {
2166 ar = 0x93;
2167 if (seg == VCPU_SREG_CS)
2168 ar |= 0x08; /* code segment */
2169 } else
2170 ar = 0xf3;
2171
2172 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2173}
2174
f78e0e2e
SY		 2175static int alloc_apic_access_page(struct kvm *kvm)
2176{
2177 struct kvm_userspace_memory_region kvm_userspace_mem;
2178 int r = 0;
2179
72dc67a6 2180 down_write(&kvm->slots_lock);
bfc6d222 2181 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2182 goto out;
2183 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2184 kvm_userspace_mem.flags = 0;
2185 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2186 kvm_userspace_mem.memory_size = PAGE_SIZE;
2187 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2188 if (r)
2189 goto out;
72dc67a6 2190
bfc6d222 2191 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2192out:
72dc67a6 2193 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2194 return r;
2195}
2196
b7ebfb05
SY		 2197static int alloc_identity_pagetable(struct kvm *kvm)
2198{
2199 struct kvm_userspace_memory_region kvm_userspace_mem;
2200 int r = 0;
2201
2202 down_write(&kvm->slots_lock);
2203 if (kvm->arch.ept_identity_pagetable)
2204 goto out;
2205 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2206 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2207 kvm_userspace_mem.guest_phys_addr =
2208 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2209 kvm_userspace_mem.memory_size = PAGE_SIZE;
2210 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2211 if (r)
2212 goto out;
2213
b7ebfb05 2214 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2215 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2216out:
2217 up_write(&kvm->slots_lock);
2218 return r;
2219}
2220
2384d2b3
SY		 2221static void allocate_vpid(struct vcpu_vmx *vmx)
2222{
2223 int vpid;
2224
2225 vmx->vpid = 0;
919818ab 2226 if (!enable_vpid)
2384d2b3
SY		 2227 return;
2228 spin_lock(&vmx_vpid_lock);
2229 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2230 if (vpid < VMX_NR_VPIDS) {
2231 vmx->vpid = vpid;
2232 __set_bit(vpid, vmx_vpid_bitmap);
2233 }
2234 spin_unlock(&vmx_vpid_lock);
2235}
2236
5897297b 2237static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2238{
3e7c73e9 2239 int f = sizeof(unsigned long);
25c5f225
SY		 2240
2241 if (!cpu_has_vmx_msr_bitmap())
2242 return;
2243
2244 /*
2245 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2246 * have the write-low and read-high bitmap offsets the wrong way round.
2247 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2248 */
25c5f225 2249 if (msr <= 0x1fff) {
3e7c73e9
AK		 2250 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2251 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2252 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2253 msr &= 0x1fff;
3e7c73e9
AK		 2254 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2255 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2256 }
25c5f225
SY		 2257}
2258
5897297b
AK		 2259static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2260{
2261 if (!longmode_only)
2262 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2263 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2264}
2265
6aa8b732
AK		 2266/*
2267 * Sets up the vmcs for emulated real mode.
2268 */
8b9cf98c 2269static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2270{
468d472f 2271 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2272 u32 junk;
53f658b3 2273 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2274 unsigned long a;
2275 struct descriptor_table dt;
2276 int i;
cd2276a7 2277 unsigned long kvm_vmx_return;
6e5d865c 2278 u32 exec_control;
6aa8b732 2279
6aa8b732 2280 /* I/O */
3e7c73e9
AK		 2281 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2282 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2283
25c5f225 2284 if (cpu_has_vmx_msr_bitmap())
5897297b 2285 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2286
6aa8b732
AK		 2287 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2288
6aa8b732 2289 /* Control */
1c3d14fe
YS		 2290 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2291 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2292
2293 exec_control = vmcs_config.cpu_based_exec_ctrl;
2294 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2295 exec_control &= ~CPU_BASED_TPR_SHADOW;
2296#ifdef CONFIG_X86_64
2297 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2298 CPU_BASED_CR8_LOAD_EXITING;
2299#endif
2300 }
089d034e 2301 if (!enable_ept)
d56f546d 2302 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2303 CPU_BASED_CR3_LOAD_EXITING |
2304 CPU_BASED_INVLPG_EXITING;
6e5d865c 2305 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2306
83ff3b9d
SY		 2307 if (cpu_has_secondary_exec_ctrls()) {
2308 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2309 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2310 exec_control &=
2311 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2312 if (vmx->vpid == 0)
2313 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2314 if (!enable_ept) {
d56f546d 2315 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2316 enable_unrestricted_guest = 0;
2317 }
3a624e29
NK		 2318 if (!enable_unrestricted_guest)
2319 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2320 if (!ple_gap)
2321 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2322 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2323 }
f78e0e2e 2324
4b8d54f9
ZE		 2325 if (ple_gap) {
2326 vmcs_write32(PLE_GAP, ple_gap);
2327 vmcs_write32(PLE_WINDOW, ple_window);
2328 }
2329
c7addb90
AK		 2330 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2331 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2332 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2333
2334 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2335 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2336 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2337
2338 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2339 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2340 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2341 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2342 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2343 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2344#ifdef CONFIG_X86_64
6aa8b732
AK		 2345 rdmsrl(MSR_FS_BASE, a);
2346 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2347 rdmsrl(MSR_GS_BASE, a);
2348 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2349#else
2350 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2351 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2352#endif
2353
2354 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2355
d6e88aec 2356 kvm_get_idt(&dt);
6aa8b732
AK		 2357 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2358
d77c26fc 2359 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2360 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2361 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2362 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2363 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2364
2365 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2366 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2367 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2368 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2369 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2370 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2371
468d472f
SY		 2372 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2373 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2374 host_pat = msr_low | ((u64) msr_high << 32);
2375 vmcs_write64(HOST_IA32_PAT, host_pat);
2376 }
2377 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2378 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2379 host_pat = msr_low | ((u64) msr_high << 32);
2380 /* Write the default value follow host pat */
2381 vmcs_write64(GUEST_IA32_PAT, host_pat);
2382 /* Keep arch.pat sync with GUEST_IA32_PAT */
2383 vmx->vcpu.arch.pat = host_pat;
2384 }
2385
6aa8b732
AK		 2386 for (i = 0; i < NR_VMX_MSR; ++i) {
2387 u32 index = vmx_msr_index[i];
2388 u32 data_low, data_high;
2389 u64 data;
a2fa3e9f 2390 int j = vmx->nmsrs;
6aa8b732
AK		 2391
2392 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2393 continue;
432bd6cb
AK		 2394 if (wrmsr_safe(index, data_low, data_high) < 0)
2395 continue;
6aa8b732 2396 data = data_low | ((u64)data_high << 32);
26bb0981
AK		 2397 vmx->guest_msrs[j].index = i;
2398 vmx->guest_msrs[j].data = 0;
d5696725 2399 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2400 ++vmx->nmsrs;
6aa8b732 2401 }
6aa8b732 2402
1c3d14fe 2403 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2404
2405 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2406 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2407
e00c8cf2
AK		 2408 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2409 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2410
53f658b3
MT		 2411 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2412 rdtscll(tsc_this);
2413 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2414 tsc_base = tsc_this;
2415
2416 guest_write_tsc(0, tsc_base);
f78e0e2e 2417
e00c8cf2
AK		 2418 return 0;
2419}
2420
b7ebfb05
SY		 2421static int init_rmode(struct kvm *kvm)
2422{
2423 if (!init_rmode_tss(kvm))
2424 return 0;
2425 if (!init_rmode_identity_map(kvm))
2426 return 0;
2427 return 1;
2428}
2429
e00c8cf2
AK		 2430static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2431{
2432 struct vcpu_vmx *vmx = to_vmx(vcpu);
2433 u64 msr;
2434 int ret;
2435
5fdbf976 2436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2437 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2438 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2439 ret = -ENOMEM;
2440 goto out;
2441 }
2442
7ffd92c5 2443 vmx->rmode.vm86_active = 0;
e00c8cf2 2444
3b86cd99
JK		 2445 vmx->soft_vnmi_blocked = 0;
2446
ad312c7c 2447 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2448 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2449 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2450 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2451 msr |= MSR_IA32_APICBASE_BSP;
2452 kvm_set_apic_base(&vmx->vcpu, msr);
2453
2454 fx_init(&vmx->vcpu);
2455
5706be0d 2456 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2457 /*
2458 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2459 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2460 */
c5af89b6 2461 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2462 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2463 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2464 } else {
ad312c7c
ZX		 2465 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2466 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2467 }
e00c8cf2
AK		 2468
2469 seg_setup(VCPU_SREG_DS);
2470 seg_setup(VCPU_SREG_ES);
2471 seg_setup(VCPU_SREG_FS);
2472 seg_setup(VCPU_SREG_GS);
2473 seg_setup(VCPU_SREG_SS);
2474
2475 vmcs_write16(GUEST_TR_SELECTOR, 0);
2476 vmcs_writel(GUEST_TR_BASE, 0);
2477 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2478 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2479
2480 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2481 vmcs_writel(GUEST_LDTR_BASE, 0);
2482 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2483 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2484
2485 vmcs_write32(GUEST_SYSENTER_CS, 0);
2486 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2487 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2488
2489 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2490 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2491 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2492 else
5fdbf976
MT		 2493 kvm_rip_write(vcpu, 0);
2494 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2495
e00c8cf2
AK		 2496 vmcs_writel(GUEST_DR7, 0x400);
2497
2498 vmcs_writel(GUEST_GDTR_BASE, 0);
2499 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2500
2501 vmcs_writel(GUEST_IDTR_BASE, 0);
2502 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2503
2504 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2506 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2507
e00c8cf2
AK		 2508 /* Special registers */
2509 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2510
2511 setup_msrs(vmx);
2512
6aa8b732
AK		 2513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2514
f78e0e2e
SY		 2515 if (cpu_has_vmx_tpr_shadow()) {
2516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2517 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2518 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2519 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2520 vmcs_write32(TPR_THRESHOLD, 0);
2521 }
2522
2523 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2524 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2525 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2526
2384d2b3
SY		 2527 if (vmx->vpid != 0)
2528 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2529
fa40052c 2530 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2531 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2532 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2533 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2534 vmx_fpu_activate(&vmx->vcpu);
2535 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2536
2384d2b3
SY		 2537 vpid_sync_vcpu_all(vmx);
2538
3200f405 2539 ret = 0;
6aa8b732 2540
a89a8fb9
MG		 2541 /* HACK: Don't enable emulation on guest boot/reset */
2542 vmx->emulation_required = 0;
2543
6aa8b732 2544out:
3200f405 2545 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2546 return ret;
2547}
2548
3b86cd99
JK		 2549static void enable_irq_window(struct kvm_vcpu *vcpu)
2550{
2551 u32 cpu_based_vm_exec_control;
2552
2553 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2554 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2555 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2556}
2557
2558static void enable_nmi_window(struct kvm_vcpu *vcpu)
2559{
2560 u32 cpu_based_vm_exec_control;
2561
2562 if (!cpu_has_virtual_nmis()) {
2563 enable_irq_window(vcpu);
2564 return;
2565 }
2566
2567 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2568 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2570}
2571
66fd3f7f 2572static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2573{
9c8cba37 2574 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2575 uint32_t intr;
2576 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2577
229456fc 2578 trace_kvm_inj_virq(irq);
2714d1d3 2579
fa89a817 2580 ++vcpu->stat.irq_injections;
7ffd92c5 2581 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2582 vmx->rmode.irq.pending = true;
2583 vmx->rmode.irq.vector = irq;
5fdbf976 2584 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2585 if (vcpu->arch.interrupt.soft)
2586 vmx->rmode.irq.rip +=
2587 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2588 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2589 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2590 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2591 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2592 return;
2593 }
66fd3f7f
GN		 2594 intr = irq | INTR_INFO_VALID_MASK;
2595 if (vcpu->arch.interrupt.soft) {
2596 intr |= INTR_TYPE_SOFT_INTR;
2597 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2598 vmx->vcpu.arch.event_exit_inst_len);
2599 } else
2600 intr |= INTR_TYPE_EXT_INTR;
2601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2602}
2603
f08864b4
SY		 2604static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2605{
66a5a347
JK		 2606 struct vcpu_vmx *vmx = to_vmx(vcpu);
2607
3b86cd99
JK		 2608 if (!cpu_has_virtual_nmis()) {
2609 /*
2610 * Tracking the NMI-blocked state in software is built upon
2611 * finding the next open IRQ window. This, in turn, depends on
2612 * well-behaving guests: They have to keep IRQs disabled at
2613 * least as long as the NMI handler runs. Otherwise we may
2614 * cause NMI nesting, maybe breaking the guest. But as this is
2615 * highly unlikely, we can live with the residual risk.
2616 */
2617 vmx->soft_vnmi_blocked = 1;
2618 vmx->vnmi_blocked_time = 0;
2619 }
2620
487b391d 2621 ++vcpu->stat.nmi_injections;
7ffd92c5 2622 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2623 vmx->rmode.irq.pending = true;
2624 vmx->rmode.irq.vector = NMI_VECTOR;
2625 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2626 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2627 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2628 INTR_INFO_VALID_MASK);
2629 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2630 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2631 return;
2632 }
f08864b4
SY		 2633 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2634 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2635}
2636
c4282df9 2637static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2638{
3b86cd99 2639 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2640 return 0;
33f089ca 2641
c4282df9
GN		 2642 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2643 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2644 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2645}
2646
3cfc3092
JK		 2647static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2648{
2649 if (!cpu_has_virtual_nmis())
2650 return to_vmx(vcpu)->soft_vnmi_blocked;
2651 else
2652 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2653 GUEST_INTR_STATE_NMI);
2654}
2655
2656static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2657{
2658 struct vcpu_vmx *vmx = to_vmx(vcpu);
2659
2660 if (!cpu_has_virtual_nmis()) {
2661 if (vmx->soft_vnmi_blocked != masked) {
2662 vmx->soft_vnmi_blocked = masked;
2663 vmx->vnmi_blocked_time = 0;
2664 }
2665 } else {
2666 if (masked)
2667 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2668 GUEST_INTR_STATE_NMI);
2669 else
2670 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2671 GUEST_INTR_STATE_NMI);
2672 }
2673}
2674
78646121
GN		 2675static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2676{
c4282df9
GN		 2677 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2678 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2679 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2680}
2681
cbc94022
IE		 2682static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2683{
2684 int ret;
2685 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2686 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2687 .guest_phys_addr = addr,
2688 .memory_size = PAGE_SIZE * 3,
2689 .flags = 0,
2690 };
2691
2692 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2693 if (ret)
2694 return ret;
bfc6d222 2695 kvm->arch.tss_addr = addr;
cbc94022
IE		 2696 return 0;
2697}
2698
6aa8b732
AK		 2699static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2700 int vec, u32 err_code)
2701{
b3f37707
NK		 2702 /*
2703 * Instruction with address size override prefix opcode 0x67
2704 * Cause the #SS fault with 0 error code in VM86 mode.
2705 */
2706 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2707 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2708 return 1;
77ab6db0
JK		 2709 /*
2710 * Forward all other exceptions that are valid in real mode.
2711 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2712 * the required debugging infrastructure rework.
2713 */
2714 switch (vec) {
77ab6db0 2715 case DB_VECTOR:
d0bfb940
JK		 2716 if (vcpu->guest_debug &
2717 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2718 return 0;
2719 kvm_queue_exception(vcpu, vec);
2720 return 1;
77ab6db0 2721 case BP_VECTOR:
d0bfb940
JK		 2722 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2723 return 0;
2724 /* fall through */
2725 case DE_VECTOR:
77ab6db0
JK		 2726 case OF_VECTOR:
2727 case BR_VECTOR:
2728 case UD_VECTOR:
2729 case DF_VECTOR:
2730 case SS_VECTOR:
2731 case GP_VECTOR:
2732 case MF_VECTOR:
2733 kvm_queue_exception(vcpu, vec);
2734 return 1;
2735 }
6aa8b732
AK		 2736 return 0;
2737}
2738
a0861c02
AK		 2739/*
2740 * Trigger machine check on the host. We assume all the MSRs are already set up
2741 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2742 * We pass a fake environment to the machine check handler because we want
2743 * the guest to be always treated like user space, no matter what context
2744 * it used internally.
2745 */
2746static void kvm_machine_check(void)
2747{
2748#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2749 struct pt_regs regs = {
2750 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2751 .flags = X86_EFLAGS_IF,
2752 };
2753
2754 do_machine_check(&regs, 0);
2755#endif
2756}
2757
851ba692 2758static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2759{
2760 /* already handled by vcpu_run */
2761 return 1;
2762}
2763
851ba692 2764static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2765{
1155f76a 2766 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2767 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2768 u32 intr_info, ex_no, error_code;
42dbaa5a 2769 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2770 u32 vect_info;
2771 enum emulation_result er;
2772
1155f76a 2773 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2774 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2775
a0861c02 2776 if (is_machine_check(intr_info))
851ba692 2777 return handle_machine_check(vcpu);
a0861c02 2778
6aa8b732 2779 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2780 !is_page_fault(intr_info)) {
2781 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2782 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2783 vcpu->run->internal.ndata = 2;
2784 vcpu->run->internal.data[0] = vect_info;
2785 vcpu->run->internal.data[1] = intr_info;
2786 return 0;
2787 }
6aa8b732 2788
e4a41889 2789 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2790 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2791
2792 if (is_no_device(intr_info)) {
5fd86fcf 2793 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2794 return 1;
2795 }
2796
7aa81cc0 2797 if (is_invalid_opcode(intr_info)) {
851ba692 2798 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2799 if (er != EMULATE_DONE)
7ee5d940 2800 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2801 return 1;
2802 }
2803
6aa8b732 2804 error_code = 0;
5fdbf976 2805 rip = kvm_rip_read(vcpu);
2e11384c 2806 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2807 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2808 if (is_page_fault(intr_info)) {
1439442c 2809 /* EPT won't cause page fault directly */
089d034e 2810 if (enable_ept)
1439442c 2811 BUG();
6aa8b732 2812 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2813 trace_kvm_page_fault(cr2, error_code);
2814
3298b75c 2815 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2816 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2817 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2818 }
2819
7ffd92c5 2820 if (vmx->rmode.vm86_active &&
6aa8b732 2821 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2822 error_code)) {
ad312c7c
ZX		 2823 if (vcpu->arch.halt_request) {
2824 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2825 return kvm_emulate_halt(vcpu);
2826 }
6aa8b732 2827 return 1;
72d6e5a0 2828 }
6aa8b732 2829
d0bfb940 2830 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2831 switch (ex_no) {
2832 case DB_VECTOR:
2833 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2834 if (!(vcpu->guest_debug &
2835 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2836 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2837 kvm_queue_exception(vcpu, DB_VECTOR);
2838 return 1;
2839 }
2840 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2841 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2842 /* fall through */
2843 case BP_VECTOR:
6aa8b732 2844 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2845 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2846 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2847 break;
2848 default:
d0bfb940
JK		 2849 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2850 kvm_run->ex.exception = ex_no;
2851 kvm_run->ex.error_code = error_code;
42dbaa5a 2852 break;
6aa8b732 2853 }
6aa8b732
AK		 2854 return 0;
2855}
2856
851ba692 2857static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2858{
1165f5fe 2859 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2860 return 1;
2861}
2862
851ba692 2863static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2864{
851ba692 2865 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2866 return 0;
2867}
6aa8b732 2868
851ba692 2869static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2870{
bfdaab09 2871 unsigned long exit_qualification;
34c33d16 2872 int size, in, string;
039576c0 2873 unsigned port;
6aa8b732 2874
1165f5fe 2875 ++vcpu->stat.io_exits;
bfdaab09 2876 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2877 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2878
2879 if (string) {
851ba692 2880 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2881 return 0;
2882 return 1;
2883 }
2884
2885 size = (exit_qualification & 7) + 1;
2886 in = (exit_qualification & 8) != 0;
039576c0 2887 port = exit_qualification >> 16;
e70669ab 2888
e93f36bc 2889 skip_emulated_instruction(vcpu);
851ba692 2890 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2891}
2892
102d8325
IM		 2893static void
2894vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2895{
2896 /*
2897 * Patch in the VMCALL instruction:
2898 */
2899 hypercall[0] = 0x0f;
2900 hypercall[1] = 0x01;
2901 hypercall[2] = 0xc1;
102d8325
IM		 2902}
2903
851ba692 2904static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2905{
229456fc 2906 unsigned long exit_qualification, val;
6aa8b732
AK		 2907 int cr;
2908 int reg;
2909
bfdaab09 2910 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2911 cr = exit_qualification & 15;
2912 reg = (exit_qualification >> 8) & 15;
2913 switch ((exit_qualification >> 4) & 3) {
2914 case 0: /* mov to cr */
229456fc
MT		 2915 val = kvm_register_read(vcpu, reg);
2916 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2917 switch (cr) {
2918 case 0:
229456fc 2919 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2920 skip_emulated_instruction(vcpu);
2921 return 1;
2922 case 3:
229456fc 2923 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2924 skip_emulated_instruction(vcpu);
2925 return 1;
2926 case 4:
229456fc 2927 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2928 skip_emulated_instruction(vcpu);
2929 return 1;
0a5fff19
GN		 2930 case 8: {
2931 u8 cr8_prev = kvm_get_cr8(vcpu);
2932 u8 cr8 = kvm_register_read(vcpu, reg);
2933 kvm_set_cr8(vcpu, cr8);
2934 skip_emulated_instruction(vcpu);
2935 if (irqchip_in_kernel(vcpu->kvm))
2936 return 1;
2937 if (cr8_prev <= cr8)
2938 return 1;
851ba692 2939 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2940 return 0;
2941 }
6aa8b732
AK		 2942 };
2943 break;
25c4c276 2944 case 2: /* clts */
5fd86fcf 2945 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2946 vcpu->arch.cr0 &= ~X86_CR0_TS;
2947 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2948 vmx_fpu_activate(vcpu);
25c4c276
AL		 2949 skip_emulated_instruction(vcpu);
2950 return 1;
6aa8b732
AK		 2951 case 1: /*mov from cr*/
2952 switch (cr) {
2953 case 3:
5fdbf976 2954 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2955 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2956 skip_emulated_instruction(vcpu);
2957 return 1;
2958 case 8:
229456fc
MT		 2959 val = kvm_get_cr8(vcpu);
2960 kvm_register_write(vcpu, reg, val);
2961 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2962 skip_emulated_instruction(vcpu);
2963 return 1;
2964 }
2965 break;
2966 case 3: /* lmsw */
2d3ad1f4 2967 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2968
2969 skip_emulated_instruction(vcpu);
2970 return 1;
2971 default:
2972 break;
2973 }
851ba692 2974 vcpu->run->exit_reason = 0;
f0242478 2975 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2976 (int)(exit_qualification >> 4) & 3, cr);
2977 return 0;
2978}
2979
851ba692 2980static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2981{
bfdaab09 2982 unsigned long exit_qualification;
6aa8b732
AK		 2983 unsigned long val;
2984 int dr, reg;
2985
0a79b009
AK		 2986 if (!kvm_require_cpl(vcpu, 0))
2987 return 1;
42dbaa5a
JK		 2988 dr = vmcs_readl(GUEST_DR7);
2989 if (dr & DR7_GD) {
2990 /*
2991 * As the vm-exit takes precedence over the debug trap, we
2992 * need to emulate the latter, either for the host or the
2993 * guest debugging itself.
2994 */
2995 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 2996 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2997 vcpu->run->debug.arch.dr7 = dr;
2998 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 2999 vmcs_readl(GUEST_CS_BASE) +
3000 vmcs_readl(GUEST_RIP);
851ba692
AK		 3001 vcpu->run->debug.arch.exception = DB_VECTOR;
3002 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3003 return 0;
3004 } else {
3005 vcpu->arch.dr7 &= ~DR7_GD;
3006 vcpu->arch.dr6 |= DR6_BD;
3007 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3008 kvm_queue_exception(vcpu, DB_VECTOR);
3009 return 1;
3010 }
3011 }
3012
bfdaab09 3013 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3014 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3015 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3016 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3017 switch (dr) {
42dbaa5a
JK		 3018 case 0 ... 3:
3019 val = vcpu->arch.db[dr];
3020 break;
6aa8b732 3021 case 6:
42dbaa5a 3022 val = vcpu->arch.dr6;
6aa8b732
AK		 3023 break;
3024 case 7:
42dbaa5a 3025 val = vcpu->arch.dr7;
6aa8b732
AK		 3026 break;
3027 default:
3028 val = 0;
3029 }
5fdbf976 3030 kvm_register_write(vcpu, reg, val);
6aa8b732 3031 } else {
42dbaa5a
JK		 3032 val = vcpu->arch.regs[reg];
3033 switch (dr) {
3034 case 0 ... 3:
3035 vcpu->arch.db[dr] = val;
3036 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3037 vcpu->arch.eff_db[dr] = val;
3038 break;
3039 case 4 ... 5:
3040 if (vcpu->arch.cr4 & X86_CR4_DE)
3041 kvm_queue_exception(vcpu, UD_VECTOR);
3042 break;
3043 case 6:
3044 if (val & 0xffffffff00000000ULL) {
3045 kvm_queue_exception(vcpu, GP_VECTOR);
3046 break;
3047 }
3048 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3049 break;
3050 case 7:
3051 if (val & 0xffffffff00000000ULL) {
3052 kvm_queue_exception(vcpu, GP_VECTOR);
3053 break;
3054 }
3055 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3056 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3057 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3058 vcpu->arch.switch_db_regs =
3059 (val & DR7_BP_EN_MASK);
3060 }
3061 break;
3062 }
6aa8b732 3063 }
6aa8b732
AK		 3064 skip_emulated_instruction(vcpu);
3065 return 1;
3066}
3067
851ba692 3068static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3069{
06465c5a
AK		 3070 kvm_emulate_cpuid(vcpu);
3071 return 1;
6aa8b732
AK		 3072}
3073
851ba692 3074static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3075{
ad312c7c 3076 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3077 u64 data;
3078
3079 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3080 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3081 return 1;
3082 }
3083
229456fc 3084 trace_kvm_msr_read(ecx, data);
2714d1d3 3085
6aa8b732 3086 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3087 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3088 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3089 skip_emulated_instruction(vcpu);
3090 return 1;
3091}
3092
851ba692 3093static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3094{
ad312c7c
ZX		 3095 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3096 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3097 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3098
229456fc 3099 trace_kvm_msr_write(ecx, data);
2714d1d3 3100
6aa8b732 3101 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3102 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3103 return 1;
3104 }
3105
3106 skip_emulated_instruction(vcpu);
3107 return 1;
3108}
3109
851ba692 3110static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3111{
3112 return 1;
3113}
3114
851ba692 3115static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3116{
85f455f7
ED		 3117 u32 cpu_based_vm_exec_control;
3118
3119 /* clear pending irq */
3120 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3121 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3122 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3123
a26bf12a 3124 ++vcpu->stat.irq_window_exits;
2714d1d3 3125
c1150d8c
DL		 3126 /*
3127 * If the user space waits to inject interrupts, exit as soon as
3128 * possible
3129 */
8061823a 3130 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3131 vcpu->run->request_interrupt_window &&
8061823a 3132 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3133 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3134 return 0;
3135 }
6aa8b732
AK		 3136 return 1;
3137}
3138
851ba692 3139static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3140{
3141 skip_emulated_instruction(vcpu);
d3bef15f 3142 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3143}
3144
851ba692 3145static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3146{
510043da 3147 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3148 kvm_emulate_hypercall(vcpu);
3149 return 1;
c21415e8
IM		 3150}
3151
851ba692 3152static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3153{
3154 kvm_queue_exception(vcpu, UD_VECTOR);
3155 return 1;
3156}
3157
851ba692 3158static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3159{
f9c617f6 3160 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3161
3162 kvm_mmu_invlpg(vcpu, exit_qualification);
3163 skip_emulated_instruction(vcpu);
3164 return 1;
3165}
3166
851ba692 3167static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3168{
3169 skip_emulated_instruction(vcpu);
3170 /* TODO: Add support for VT-d/pass-through device */
3171 return 1;
3172}
3173
851ba692 3174static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3175{
f9c617f6 3176 unsigned long exit_qualification;
f78e0e2e
SY		 3177 enum emulation_result er;
3178 unsigned long offset;
3179
f9c617f6 3180 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3181 offset = exit_qualification & 0xffful;
3182
851ba692 3183 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3184
3185 if (er != EMULATE_DONE) {
3186 printk(KERN_ERR
3187 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3188 offset);
7f582ab6 3189 return -ENOEXEC;
f78e0e2e
SY		 3190 }
3191 return 1;
3192}
3193
851ba692 3194static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3195{
60637aac 3196 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3197 unsigned long exit_qualification;
3198 u16 tss_selector;
64a7ec06
GN		 3199 int reason, type, idt_v;
3200
3201 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3202 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3203
3204 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3205
3206 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3207 if (reason == TASK_SWITCH_GATE && idt_v) {
3208 switch (type) {
3209 case INTR_TYPE_NMI_INTR:
3210 vcpu->arch.nmi_injected = false;
3211 if (cpu_has_virtual_nmis())
3212 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3213 GUEST_INTR_STATE_NMI);
3214 break;
3215 case INTR_TYPE_EXT_INTR:
66fd3f7f 3216 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3217 kvm_clear_interrupt_queue(vcpu);
3218 break;
3219 case INTR_TYPE_HARD_EXCEPTION:
3220 case INTR_TYPE_SOFT_EXCEPTION:
3221 kvm_clear_exception_queue(vcpu);
3222 break;
3223 default:
3224 break;
3225 }
60637aac 3226 }
37817f29
IE		 3227 tss_selector = exit_qualification;
3228
64a7ec06
GN		 3229 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3230 type != INTR_TYPE_EXT_INTR &&
3231 type != INTR_TYPE_NMI_INTR))
3232 skip_emulated_instruction(vcpu);
3233
42dbaa5a
JK		 3234 if (!kvm_task_switch(vcpu, tss_selector, reason))
3235 return 0;
3236
3237 /* clear all local breakpoint enable flags */
3238 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3239
3240 /*
3241 * TODO: What about debug traps on tss switch?
3242 * Are we supposed to inject them and update dr6?
3243 */
3244
3245 return 1;
37817f29
IE		 3246}
3247
851ba692 3248static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3249{
f9c617f6 3250 unsigned long exit_qualification;
1439442c 3251 gpa_t gpa;
1439442c 3252 int gla_validity;
1439442c 3253
f9c617f6 3254 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3255
3256 if (exit_qualification & (1 << 6)) {
3257 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3258 return -EINVAL;
1439442c
SY		 3259 }
3260
3261 gla_validity = (exit_qualification >> 7) & 0x3;
3262 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3263 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3264 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3265 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3266 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3267 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3268 (long unsigned int)exit_qualification);
851ba692
AK		 3269 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3270 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3271 return 0;
1439442c
SY		 3272 }
3273
3274 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3275 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3276 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3277}
3278
68f89400
MT		 3279static u64 ept_rsvd_mask(u64 spte, int level)
3280{
3281 int i;
3282 u64 mask = 0;
3283
3284 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3285 mask |= (1ULL << i);
3286
3287 if (level > 2)
3288 /* bits 7:3 reserved */
3289 mask |= 0xf8;
3290 else if (level == 2) {
3291 if (spte & (1ULL << 7))
3292 /* 2MB ref, bits 20:12 reserved */
3293 mask |= 0x1ff000;
3294 else
3295 /* bits 6:3 reserved */
3296 mask |= 0x78;
3297 }
3298
3299 return mask;
3300}
3301
3302static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3303 int level)
3304{
3305 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3306
3307 /* 010b (write-only) */
3308 WARN_ON((spte & 0x7) == 0x2);
3309
3310 /* 110b (write/execute) */
3311 WARN_ON((spte & 0x7) == 0x6);
3312
3313 /* 100b (execute-only) and value not supported by logical processor */
3314 if (!cpu_has_vmx_ept_execute_only())
3315 WARN_ON((spte & 0x7) == 0x4);
3316
3317 /* not 000b */
3318 if ((spte & 0x7)) {
3319 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3320
3321 if (rsvd_bits != 0) {
3322 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3323 __func__, rsvd_bits);
3324 WARN_ON(1);
3325 }
3326
3327 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3328 u64 ept_mem_type = (spte & 0x38) >> 3;
3329
3330 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3331 ept_mem_type == 7) {
3332 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3333 __func__, ept_mem_type);
3334 WARN_ON(1);
3335 }
3336 }
3337 }
3338}
3339
851ba692 3340static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3341{
3342 u64 sptes[4];
3343 int nr_sptes, i;
3344 gpa_t gpa;
3345
3346 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3347
3348 printk(KERN_ERR "EPT: Misconfiguration.\n");
3349 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3350
3351 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3352
3353 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3354 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3355
851ba692
AK		 3356 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3357 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3358
3359 return 0;
3360}
3361
851ba692 3362static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3363{
3364 u32 cpu_based_vm_exec_control;
3365
3366 /* clear pending NMI */
3367 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3368 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3369 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3370 ++vcpu->stat.nmi_window_exits;
3371
3372 return 1;
3373}
3374
80ced186 3375static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3376{
8b3079a5
AK		 3377 struct vcpu_vmx *vmx = to_vmx(vcpu);
3378 enum emulation_result err = EMULATE_DONE;
80ced186 3379 int ret = 1;
ea953ef0
MG		 3380
3381 while (!guest_state_valid(vcpu)) {
851ba692 3382 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3383
80ced186
MG		 3384 if (err == EMULATE_DO_MMIO) {
3385 ret = 0;
3386 goto out;
3387 }
1d5a4d9b
GT		 3388
3389 if (err != EMULATE_DONE) {
3390 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3391 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3392 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3393 vcpu->run->internal.ndata = 0;
80ced186
MG		 3394 ret = 0;
3395 goto out;
ea953ef0
MG		 3396 }
3397
3398 if (signal_pending(current))
80ced186 3399 goto out;
ea953ef0
MG		 3400 if (need_resched())
3401 schedule();
3402 }
3403
80ced186
MG		 3404 vmx->emulation_required = 0;
3405out:
3406 return ret;
ea953ef0
MG		 3407}
3408
4b8d54f9
ZE		 3409/*
3410 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3411 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3412 */
9fb41ba8 3413static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3414{
3415 skip_emulated_instruction(vcpu);
3416 kvm_vcpu_on_spin(vcpu);
3417
3418 return 1;
3419}
3420
59708670
SY		 3421static int handle_invalid_op(struct kvm_vcpu *vcpu)
3422{
3423 kvm_queue_exception(vcpu, UD_VECTOR);
3424 return 1;
3425}
3426
6aa8b732
AK		 3427/*
3428 * The exit handlers return 1 if the exit was handled fully and guest execution
3429 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3430 * to be done to userspace and return 0.
3431 */
851ba692 3432static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3433 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3434 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3435 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3436 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3437 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3438 [EXIT_REASON_CR_ACCESS] = handle_cr,
3439 [EXIT_REASON_DR_ACCESS] = handle_dr,
3440 [EXIT_REASON_CPUID] = handle_cpuid,
3441 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3442 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3443 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3444 [EXIT_REASON_HLT] = handle_halt,
a7052897 3445 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3446 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3447 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3448 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3449 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3450 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3451 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3452 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3453 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3454 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3455 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3456 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3457 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3458 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3459 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3460 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3461 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3462 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3463 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3464 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3465 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3466};
3467
3468static const int kvm_vmx_max_exit_handlers =
50a3485c 3469 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3470
3471/*
3472 * The guest has exited. See if we can fix it or if we need userspace
3473 * assistance.
3474 */
851ba692 3475static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3476{
29bd8a78 3477 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3478 u32 exit_reason = vmx->exit_reason;
1155f76a 3479 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3480
229456fc 3481 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3482
80ced186
MG		 3483 /* If guest state is invalid, start emulating */
3484 if (vmx->emulation_required && emulate_invalid_guest_state)
3485 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3486
1439442c
SY		 3487 /* Access CR3 don't cause VMExit in paging mode, so we need
3488 * to sync with guest real CR3. */
6de4f3ad 3489 if (enable_ept && is_paging(vcpu))
1439442c 3490 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3491
29bd8a78 3492 if (unlikely(vmx->fail)) {
851ba692
AK		 3493 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3494 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3495 = vmcs_read32(VM_INSTRUCTION_ERROR);
3496 return 0;
3497 }
6aa8b732 3498
d77c26fc 3499 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3500 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3501 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3502 exit_reason != EXIT_REASON_TASK_SWITCH))
3503 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3504 "(0x%x) and exit reason is 0x%x\n",
3505 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3506
3507 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3508 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3509 vmx->soft_vnmi_blocked = 0;
3b86cd99 3510 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3511 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3512 /*
3513 * This CPU don't support us in finding the end of an
3514 * NMI-blocked window if the guest runs with IRQs
3515 * disabled. So we pull the trigger after 1 s of
3516 * futile waiting, but inform the user about this.
3517 */
3518 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3519 "state on VCPU %d after 1 s timeout\n",
3520 __func__, vcpu->vcpu_id);
3521 vmx->soft_vnmi_blocked = 0;
3b86cd99 3522 }
3b86cd99
JK		 3523 }
3524
6aa8b732
AK		 3525 if (exit_reason < kvm_vmx_max_exit_handlers
3526 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3527 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3528 else {
851ba692
AK		 3529 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3530 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3531 }
3532 return 0;
3533}
3534
95ba8273 3535static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3536{
95ba8273 3537 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3538 vmcs_write32(TPR_THRESHOLD, 0);
3539 return;
3540 }
3541
95ba8273 3542 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3543}
3544
cf393f75
AK		 3545static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3546{
3547 u32 exit_intr_info;
7b4a25cb 3548 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3549 bool unblock_nmi;
3550 u8 vector;
668f612f
AK		 3551 int type;
3552 bool idtv_info_valid;
cf393f75
AK		 3553
3554 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3555
a0861c02
AK		 3556 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3557
3558 /* Handle machine checks before interrupts are enabled */
3559 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3560 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3561 && is_machine_check(exit_intr_info)))
3562 kvm_machine_check();
3563
20f65983
GN		 3564 /* We need to handle NMIs before interrupts are enabled */
3565 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3566 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3567 asm("int $2");
20f65983
GN		 3568
3569 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3570
cf393f75
AK		 3571 if (cpu_has_virtual_nmis()) {
3572 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3573 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3574 /*
7b4a25cb 3575 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3576 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3577 * a guest IRET fault.
7b4a25cb
GN		 3578 * SDM 3: 23.2.2 (September 2008)
3579 * Bit 12 is undefined in any of the following cases:
3580 * If the VM exit sets the valid bit in the IDT-vectoring
3581 * information field.
3582 * If the VM exit is due to a double fault.
cf393f75 3583 */
7b4a25cb
GN		 3584 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3585 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3586 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3587 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3588 } else if (unlikely(vmx->soft_vnmi_blocked))
3589 vmx->vnmi_blocked_time +=
3590 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3591
37b96e98
GN		 3592 vmx->vcpu.arch.nmi_injected = false;
3593 kvm_clear_exception_queue(&vmx->vcpu);
3594 kvm_clear_interrupt_queue(&vmx->vcpu);
3595
3596 if (!idtv_info_valid)
3597 return;
3598
668f612f
AK		 3599 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3600 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3601
64a7ec06 3602 switch (type) {
37b96e98
GN		 3603 case INTR_TYPE_NMI_INTR:
3604 vmx->vcpu.arch.nmi_injected = true;
668f612f 3605 /*
7b4a25cb 3606 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3607 * Clear bit "block by NMI" before VM entry if a NMI
3608 * delivery faulted.
668f612f 3609 */
37b96e98
GN		 3610 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3611 GUEST_INTR_STATE_NMI);
3612 break;
37b96e98 3613 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3614 vmx->vcpu.arch.event_exit_inst_len =
3615 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3616 /* fall through */
3617 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3618 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3619 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3620 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3621 } else
3622 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3623 break;
66fd3f7f
GN		 3624 case INTR_TYPE_SOFT_INTR:
3625 vmx->vcpu.arch.event_exit_inst_len =
3626 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3627 /* fall through */
37b96e98 3628 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3629 kvm_queue_interrupt(&vmx->vcpu, vector,
3630 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3631 break;
3632 default:
3633 break;
f7d9238f 3634 }
cf393f75
AK		 3635}
3636
9c8cba37
AK		 3637/*
3638 * Failure to inject an interrupt should give us the information
3639 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3640 * when fetching the interrupt redirection bitmap in the real-mode
3641 * tss, this doesn't happen. So we do it ourselves.
3642 */
3643static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3644{
3645 vmx->rmode.irq.pending = 0;
5fdbf976 3646 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3647 return;
5fdbf976 3648 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3649 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3650 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3651 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3652 return;
3653 }
3654 vmx->idt_vectoring_info =
3655 VECTORING_INFO_VALID_MASK
3656 | INTR_TYPE_EXT_INTR
3657 | vmx->rmode.irq.vector;
3658}
3659
c801949d
AK		 3660#ifdef CONFIG_X86_64
3661#define R "r"
3662#define Q "q"
3663#else
3664#define R "e"
3665#define Q "l"
3666#endif
3667
851ba692 3668static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3669{
a2fa3e9f 3670 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3671
3b86cd99
JK		 3672 /* Record the guest's net vcpu time for enforced NMI injections. */
3673 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3674 vmx->entry_time = ktime_get();
3675
80ced186
MG		 3676 /* Don't enter VMX if guest state is invalid, let the exit handler
3677 start emulation until we arrive back to a valid state */
3678 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3679 return;
a89a8fb9 3680
5fdbf976
MT		 3681 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3682 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3683 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3684 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3685
787ff736
GN		 3686 /* When single-stepping over STI and MOV SS, we must clear the
3687 * corresponding interruptibility bits in the guest state. Otherwise
3688 * vmentry fails as it then expects bit 14 (BS) in pending debug
3689 * exceptions being set, but that's not correct for the guest debugging
3690 * case. */
3691 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3692 vmx_set_interrupt_shadow(vcpu, 0);
3693
e6adf283
AK		 3694 /*
3695 * Loading guest fpu may have cleared host cr0.ts
3696 */
3697 vmcs_writel(HOST_CR0, read_cr0());
3698
e8a48342
AK		 3699 if (vcpu->arch.switch_db_regs)
3700 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3701
d77c26fc 3702 asm(
6aa8b732 3703 /* Store host registers */
c801949d
AK		 3704 "push %%"R"dx; push %%"R"bp;"
3705 "push %%"R"cx \n\t"
313dbd49
AK		 3706 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3707 "je 1f \n\t"
3708 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3709 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3710 "1: \n\t"
d3edefc0
AK		 3711 /* Reload cr2 if changed */
3712 "mov %c[cr2](%0), %%"R"ax \n\t"
3713 "mov %%cr2, %%"R"dx \n\t"
3714 "cmp %%"R"ax, %%"R"dx \n\t"
3715 "je 2f \n\t"
3716 "mov %%"R"ax, %%cr2 \n\t"
3717 "2: \n\t"
6aa8b732 3718 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3719 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3720 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3721 "mov %c[rax](%0), %%"R"ax \n\t"
3722 "mov %c[rbx](%0), %%"R"bx \n\t"
3723 "mov %c[rdx](%0), %%"R"dx \n\t"
3724 "mov %c[rsi](%0), %%"R"si \n\t"
3725 "mov %c[rdi](%0), %%"R"di \n\t"
3726 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3727#ifdef CONFIG_X86_64
e08aa78a
AK		 3728 "mov %c[r8](%0), %%r8 \n\t"
3729 "mov %c[r9](%0), %%r9 \n\t"
3730 "mov %c[r10](%0), %%r10 \n\t"
3731 "mov %c[r11](%0), %%r11 \n\t"
3732 "mov %c[r12](%0), %%r12 \n\t"
3733 "mov %c[r13](%0), %%r13 \n\t"
3734 "mov %c[r14](%0), %%r14 \n\t"
3735 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3736#endif
c801949d
AK		 3737 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3738
6aa8b732 3739 /* Enter guest mode */
cd2276a7 3740 "jne .Llaunched \n\t"
4ecac3fd 3741 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3742 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3743 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3744 ".Lkvm_vmx_return: "
6aa8b732 3745 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3746 "xchg %0, (%%"R"sp) \n\t"
3747 "mov %%"R"ax, %c[rax](%0) \n\t"
3748 "mov %%"R"bx, %c[rbx](%0) \n\t"
3749 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3750 "mov %%"R"dx, %c[rdx](%0) \n\t"
3751 "mov %%"R"si, %c[rsi](%0) \n\t"
3752 "mov %%"R"di, %c[rdi](%0) \n\t"
3753 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3754#ifdef CONFIG_X86_64
e08aa78a
AK		 3755 "mov %%r8, %c[r8](%0) \n\t"
3756 "mov %%r9, %c[r9](%0) \n\t"
3757 "mov %%r10, %c[r10](%0) \n\t"
3758 "mov %%r11, %c[r11](%0) \n\t"
3759 "mov %%r12, %c[r12](%0) \n\t"
3760 "mov %%r13, %c[r13](%0) \n\t"
3761 "mov %%r14, %c[r14](%0) \n\t"
3762 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3763#endif
c801949d
AK		 3764 "mov %%cr2, %%"R"ax \n\t"
3765 "mov %%"R"ax, %c[cr2](%0) \n\t"
3766
3767 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3768 "setbe %c[fail](%0) \n\t"
3769 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3770 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3771 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3772 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3773 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3774 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3775 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3776 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3777 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3778 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3779 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3780#ifdef CONFIG_X86_64
ad312c7c
ZX		 3781 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3782 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3783 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3784 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3785 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3786 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3787 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3788 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3789#endif
ad312c7c 3790 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3791 : "cc", "memory"
c801949d 3792 , R"bx", R"di", R"si"
c2036300 3793#ifdef CONFIG_X86_64
c2036300
LV		 3794 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3795#endif
3796 );
6aa8b732 3797
6de4f3ad
AK		 3798 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3799 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3800 vcpu->arch.regs_dirty = 0;
3801
e8a48342
AK		 3802 if (vcpu->arch.switch_db_regs)
3803 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3804
1155f76a 3805 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3806 if (vmx->rmode.irq.pending)
3807 fixup_rmode_irq(vmx);
1155f76a 3808
d77c26fc 3809 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3810 vmx->launched = 1;
1b6269db 3811
cf393f75 3812 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3813}
3814
c801949d
AK		 3815#undef R
3816#undef Q
3817
6aa8b732
AK		 3818static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3819{
a2fa3e9f
GH		 3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821
3822 if (vmx->vmcs) {
543e4243 3823 vcpu_clear(vmx);
a2fa3e9f
GH		 3824 free_vmcs(vmx->vmcs);
3825 vmx->vmcs = NULL;
6aa8b732
AK		 3826 }
3827}
3828
3829static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3830{
fb3f0f51
RR		 3831 struct vcpu_vmx *vmx = to_vmx(vcpu);
3832
2384d2b3
SY		 3833 spin_lock(&vmx_vpid_lock);
3834 if (vmx->vpid != 0)
3835 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3836 spin_unlock(&vmx_vpid_lock);
6aa8b732 3837 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3838 kfree(vmx->guest_msrs);
3839 kvm_vcpu_uninit(vcpu);
a4770347 3840 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3841}
3842
fb3f0f51 3843static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3844{
fb3f0f51 3845 int err;
c16f862d 3846 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3847 int cpu;
6aa8b732 3848
a2fa3e9f 3849 if (!vmx)
fb3f0f51
RR		 3850 return ERR_PTR(-ENOMEM);
3851
2384d2b3
SY		 3852 allocate_vpid(vmx);
3853
fb3f0f51
RR		 3854 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3855 if (err)
3856 goto free_vcpu;
965b58a5 3857
a2fa3e9f 3858 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3859 if (!vmx->guest_msrs) {
3860 err = -ENOMEM;
3861 goto uninit_vcpu;
3862 }
965b58a5 3863
a2fa3e9f
GH		 3864 vmx->vmcs = alloc_vmcs();
3865 if (!vmx->vmcs)
fb3f0f51 3866 goto free_msrs;
a2fa3e9f
GH		 3867
3868 vmcs_clear(vmx->vmcs);
3869
15ad7146
AK		 3870 cpu = get_cpu();
3871 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3872 err = vmx_vcpu_setup(vmx);
fb3f0f51 3873 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3874 put_cpu();
fb3f0f51
RR		 3875 if (err)
3876 goto free_vmcs;
5e4a0b3c
MT		 3877 if (vm_need_virtualize_apic_accesses(kvm))
3878 if (alloc_apic_access_page(kvm) != 0)
3879 goto free_vmcs;
fb3f0f51 3880
b927a3ce
SY		 3881 if (enable_ept) {
3882 if (!kvm->arch.ept_identity_map_addr)
3883 kvm->arch.ept_identity_map_addr =
3884 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3885 if (alloc_identity_pagetable(kvm) != 0)
3886 goto free_vmcs;
b927a3ce 3887 }
b7ebfb05 3888
fb3f0f51
RR		 3889 return &vmx->vcpu;
3890
3891free_vmcs:
3892 free_vmcs(vmx->vmcs);
3893free_msrs:
fb3f0f51
RR		 3894 kfree(vmx->guest_msrs);
3895uninit_vcpu:
3896 kvm_vcpu_uninit(&vmx->vcpu);
3897free_vcpu:
a4770347 3898 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3899 return ERR_PTR(err);
6aa8b732
AK		 3900}
3901
002c7f7c
YS		 3902static void __init vmx_check_processor_compat(void *rtn)
3903{
3904 struct vmcs_config vmcs_conf;
3905
3906 *(int *)rtn = 0;
3907 if (setup_vmcs_config(&vmcs_conf) < 0)
3908 *(int *)rtn = -EIO;
3909 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3910 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3911 smp_processor_id());
3912 *(int *)rtn = -EIO;
3913 }
3914}
3915
67253af5
SY		 3916static int get_ept_level(void)
3917{
3918 return VMX_EPT_DEFAULT_GAW + 1;
3919}
3920
4b12f0de 3921static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3922{
4b12f0de
SY		 3923 u64 ret;
3924
522c68c4
SY		 3925 /* For VT-d and EPT combination
3926 * 1. MMIO: always map as UC
3927 * 2. EPT with VT-d:
3928 * a. VT-d without snooping control feature: can't guarantee the
3929 * result, try to trust guest.
3930 * b. VT-d with snooping control feature: snooping control feature of
3931 * VT-d engine can guarantee the cache correctness. Just set it
3932 * to WB to keep consistent with host. So the same as item 3.
3933 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3934 * consistent with host MTRR
3935 */
4b12f0de
SY		 3936 if (is_mmio)
3937 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3938 else if (vcpu->kvm->arch.iommu_domain &&
3939 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3940 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3941 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3942 else
522c68c4
SY		 3943 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3944 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3945
3946 return ret;
64d4d521
SY		 3947}
3948
229456fc
MT		 3949static const struct trace_print_flags vmx_exit_reasons_str[] = {
3950 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3951 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3952 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3953 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3954 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3955 { EXIT_REASON_CR_ACCESS, "cr_access" },
3956 { EXIT_REASON_DR_ACCESS, "dr_access" },
3957 { EXIT_REASON_CPUID, "cpuid" },
3958 { EXIT_REASON_MSR_READ, "rdmsr" },
3959 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3960 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3961 { EXIT_REASON_HLT, "halt" },
3962 { EXIT_REASON_INVLPG, "invlpg" },
3963 { EXIT_REASON_VMCALL, "hypercall" },
3964 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3965 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3966 { EXIT_REASON_WBINVD, "wbinvd" },
3967 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3968 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3969 { -1, NULL }
3970};
3971
344f414f
JR		 3972static bool vmx_gb_page_enable(void)
3973{
3974 return false;
3975}
3976
cbdd1bea 3977static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3978 .cpu_has_kvm_support = cpu_has_kvm_support,
3979 .disabled_by_bios = vmx_disabled_by_bios,
3980 .hardware_setup = hardware_setup,
3981 .hardware_unsetup = hardware_unsetup,
002c7f7c 3982 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3983 .hardware_enable = hardware_enable,
3984 .hardware_disable = hardware_disable,
04547156 3985 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 3986
3987 .vcpu_create = vmx_create_vcpu,
3988 .vcpu_free = vmx_free_vcpu,
04d2cc77 3989 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3990
04d2cc77 3991 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3992 .vcpu_load = vmx_vcpu_load,
3993 .vcpu_put = vmx_vcpu_put,
3994
3995 .set_guest_debug = set_guest_debug,
3996 .get_msr = vmx_get_msr,
3997 .set_msr = vmx_set_msr,
3998 .get_segment_base = vmx_get_segment_base,
3999 .get_segment = vmx_get_segment,
4000 .set_segment = vmx_set_segment,
2e4d2653 4001 .get_cpl = vmx_get_cpl,
6aa8b732 4002 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 4003 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4004 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4005 .set_cr3 = vmx_set_cr3,
4006 .set_cr4 = vmx_set_cr4,
6aa8b732 4007 .set_efer = vmx_set_efer,
6aa8b732
AK		 4008 .get_idt = vmx_get_idt,
4009 .set_idt = vmx_set_idt,
4010 .get_gdt = vmx_get_gdt,
4011 .set_gdt = vmx_set_gdt,
5fdbf976 4012 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4013 .get_rflags = vmx_get_rflags,
4014 .set_rflags = vmx_set_rflags,
4015
4016 .tlb_flush = vmx_flush_tlb,
6aa8b732 4017
6aa8b732 4018 .run = vmx_vcpu_run,
6062d012 4019 .handle_exit = vmx_handle_exit,
6aa8b732 4020 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4021 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4022 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4023 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4024 .set_irq = vmx_inject_irq,
95ba8273 4025 .set_nmi = vmx_inject_nmi,
298101da 4026 .queue_exception = vmx_queue_exception,
78646121 4027 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4028 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4029 .get_nmi_mask = vmx_get_nmi_mask,
4030 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4031 .enable_nmi_window = enable_nmi_window,
4032 .enable_irq_window = enable_irq_window,
4033 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4034
cbc94022 4035 .set_tss_addr = vmx_set_tss_addr,
67253af5 4036 .get_tdp_level = get_ept_level,
4b12f0de 4037 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4038
4039 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 4040 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 4041};
4042
4043static int __init vmx_init(void)
4044{
26bb0981
AK		 4045 int r, i;
4046
4047 rdmsrl_safe(MSR_EFER, &host_efer);
4048
4049 for (i = 0; i < NR_VMX_MSR; ++i)
4050 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4051
3e7c73e9 4052 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4053 if (!vmx_io_bitmap_a)
4054 return -ENOMEM;
4055
3e7c73e9 4056 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4057 if (!vmx_io_bitmap_b) {
4058 r = -ENOMEM;
4059 goto out;
4060 }
4061
5897297b
AK		 4062 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4063 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4064 r = -ENOMEM;
4065 goto out1;
4066 }
4067
5897297b
AK		 4068 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4069 if (!vmx_msr_bitmap_longmode) {
4070 r = -ENOMEM;
4071 goto out2;
4072 }
4073
fdef3ad1
HQ		 4074 /*
4075 * Allow direct access to the PC debug port (it is often used for I/O
4076 * delays, but the vmexits simply slow things down).
4077 */
3e7c73e9
AK		 4078 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4079 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4080
3e7c73e9 4081 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4082
5897297b
AK		 4083 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4084 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4085
2384d2b3
SY		 4086 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4087
cb498ea2 4088 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4089 if (r)
5897297b 4090 goto out3;
25c5f225 4091
5897297b
AK		 4092 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4093 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4094 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4095 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4096 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4097 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4098
089d034e 4099 if (enable_ept) {
1439442c 4100 bypass_guest_pf = 0;
5fdbcb9d 4101 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4102 VMX_EPT_WRITABLE_MASK);
534e38b4 4103 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4104 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4105 kvm_enable_tdp();
4106 } else
4107 kvm_disable_tdp();
1439442c 4108
c7addb90
AK		 4109 if (bypass_guest_pf)
4110 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4111
fdef3ad1
HQ		 4112 return 0;
4113
5897297b
AK		 4114out3:
4115 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4116out2:
5897297b 4117 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4118out1:
3e7c73e9 4119 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4120out:
3e7c73e9 4121 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4122 return r;
6aa8b732
AK		 4123}
4124
4125static void __exit vmx_exit(void)
4126{
5897297b
AK		 4127 free_page((unsigned long)vmx_msr_bitmap_legacy);
4128 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4129 free_page((unsigned long)vmx_io_bitmap_b);
4130 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4131
cb498ea2 4132 kvm_exit();
6aa8b732
AK		 4133}
4134
4135module_init(vmx_init)
4136module_exit(vmx_exit)
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