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KVM: VMX: Add module parameter and emulation flag.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
6aa8b732 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
c7addb90
AK		 40static int bypass_guest_pf = 1;
41module_param(bypass_guest_pf, bool, 0);
42
2384d2b3
SY		 43static int enable_vpid = 1;
44module_param(enable_vpid, bool, 0);
45
4c9fc8ef
AK		 46static int flexpriority_enabled = 1;
47module_param(flexpriority_enabled, bool, 0);
48
1439442c 49static int enable_ept = 1;
d56f546d
SY		 50module_param(enable_ept, bool, 0);
51
04fa4d32
MG		 52static int emulate_invalid_guest_state = 0;
53module_param(emulate_invalid_guest_state, bool, 0);
54
a2fa3e9f
GH		 55struct vmcs {
56 u32 revision_id;
57 u32 abort;
58 char data[0];
59};
60
61struct vcpu_vmx {
fb3f0f51 62 struct kvm_vcpu vcpu;
543e4243 63 struct list_head local_vcpus_link;
313dbd49 64 unsigned long host_rsp;
a2fa3e9f 65 int launched;
29bd8a78 66 u8 fail;
1155f76a 67 u32 idt_vectoring_info;
a2fa3e9f
GH		 68 struct kvm_msr_entry *guest_msrs;
69 struct kvm_msr_entry *host_msrs;
70 int nmsrs;
71 int save_nmsrs;
72 int msr_offset_efer;
73#ifdef CONFIG_X86_64
74 int msr_offset_kernel_gs_base;
75#endif
76 struct vmcs *vmcs;
77 struct {
78 int loaded;
79 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 80 int gs_ldt_reload_needed;
81 int fs_reload_needed;
51c6cf66 82 int guest_efer_loaded;
d77c26fc 83 } host_state;
9c8cba37
AK		 84 struct {
85 struct {
86 bool pending;
87 u8 vector;
88 unsigned rip;
89 } irq;
90 } rmode;
2384d2b3 91 int vpid;
04fa4d32 92 bool emulation_required;
a2fa3e9f
GH		 93};
94
95static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
96{
fb3f0f51 97 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 98}
99
b7ebfb05 100static int init_rmode(struct kvm *kvm);
4e1096d2 101static u64 construct_eptp(unsigned long root_hpa);
75880a01 102
6aa8b732
AK		 103static DEFINE_PER_CPU(struct vmcs *, vmxarea);
104static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 105static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 106
fdef3ad1
HQ		 107static struct page *vmx_io_bitmap_a;
108static struct page *vmx_io_bitmap_b;
25c5f225 109static struct page *vmx_msr_bitmap;
fdef3ad1 110
2384d2b3
SY		 111static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
112static DEFINE_SPINLOCK(vmx_vpid_lock);
113
1c3d14fe 114static struct vmcs_config {
6aa8b732
AK		 115 int size;
116 int order;
117 u32 revision_id;
1c3d14fe
YS		 118 u32 pin_based_exec_ctrl;
119 u32 cpu_based_exec_ctrl;
f78e0e2e 120 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 121 u32 vmexit_ctrl;
122 u32 vmentry_ctrl;
123} vmcs_config;
6aa8b732 124
d56f546d
SY		 125struct vmx_capability {
126 u32 ept;
127 u32 vpid;
128} vmx_capability;
129
6aa8b732
AK		 130#define VMX_SEGMENT_FIELD(seg) \
131 [VCPU_SREG_##seg] = { \
132 .selector = GUEST_##seg##_SELECTOR, \
133 .base = GUEST_##seg##_BASE, \
134 .limit = GUEST_##seg##_LIMIT, \
135 .ar_bytes = GUEST_##seg##_AR_BYTES, \
136 }
137
138static struct kvm_vmx_segment_field {
139 unsigned selector;
140 unsigned base;
141 unsigned limit;
142 unsigned ar_bytes;
143} kvm_vmx_segment_fields[] = {
144 VMX_SEGMENT_FIELD(CS),
145 VMX_SEGMENT_FIELD(DS),
146 VMX_SEGMENT_FIELD(ES),
147 VMX_SEGMENT_FIELD(FS),
148 VMX_SEGMENT_FIELD(GS),
149 VMX_SEGMENT_FIELD(SS),
150 VMX_SEGMENT_FIELD(TR),
151 VMX_SEGMENT_FIELD(LDTR),
152};
153
4d56c8a7
AK		 154/*
155 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
156 * away by decrementing the array size.
157 */
6aa8b732 158static const u32 vmx_msr_index[] = {
05b3e0c2 159#ifdef CONFIG_X86_64
6aa8b732
AK		 160 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
161#endif
162 MSR_EFER, MSR_K6_STAR,
163};
9d8f549d 164#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 165
a2fa3e9f
GH		 166static void load_msrs(struct kvm_msr_entry *e, int n)
167{
168 int i;
169
170 for (i = 0; i < n; ++i)
171 wrmsrl(e[i].index, e[i].data);
172}
173
174static void save_msrs(struct kvm_msr_entry *e, int n)
175{
176 int i;
177
178 for (i = 0; i < n; ++i)
179 rdmsrl(e[i].index, e[i].data);
180}
181
6aa8b732
AK		 182static inline int is_page_fault(u32 intr_info)
183{
184 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
185 INTR_INFO_VALID_MASK)) ==
186 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
187}
188
2ab455cc
AL		 189static inline int is_no_device(u32 intr_info)
190{
191 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
192 INTR_INFO_VALID_MASK)) ==
193 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
194}
195
7aa81cc0
AL		 196static inline int is_invalid_opcode(u32 intr_info)
197{
198 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
199 INTR_INFO_VALID_MASK)) ==
200 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
201}
202
6aa8b732
AK		 203static inline int is_external_interrupt(u32 intr_info)
204{
205 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
206 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
207}
208
25c5f225
SY		 209static inline int cpu_has_vmx_msr_bitmap(void)
210{
211 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
212}
213
6e5d865c
YS		 214static inline int cpu_has_vmx_tpr_shadow(void)
215{
216 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
217}
218
219static inline int vm_need_tpr_shadow(struct kvm *kvm)
220{
221 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
222}
223
f78e0e2e
SY		 224static inline int cpu_has_secondary_exec_ctrls(void)
225{
226 return (vmcs_config.cpu_based_exec_ctrl &
227 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
228}
229
774ead3a 230static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 231{
4c9fc8ef
AK		 232 return flexpriority_enabled
233 && (vmcs_config.cpu_based_2nd_exec_ctrl &
234 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 235}
236
d56f546d
SY		 237static inline int cpu_has_vmx_invept_individual_addr(void)
238{
239 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
240}
241
242static inline int cpu_has_vmx_invept_context(void)
243{
244 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
245}
246
247static inline int cpu_has_vmx_invept_global(void)
248{
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
250}
251
252static inline int cpu_has_vmx_ept(void)
253{
254 return (vmcs_config.cpu_based_2nd_exec_ctrl &
255 SECONDARY_EXEC_ENABLE_EPT);
256}
257
258static inline int vm_need_ept(void)
259{
260 return (cpu_has_vmx_ept() && enable_ept);
261}
262
f78e0e2e
SY		 263static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
264{
265 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
266 (irqchip_in_kernel(kvm)));
267}
268
2384d2b3
SY		 269static inline int cpu_has_vmx_vpid(void)
270{
271 return (vmcs_config.cpu_based_2nd_exec_ctrl &
272 SECONDARY_EXEC_ENABLE_VPID);
273}
274
f08864b4
SY		 275static inline int cpu_has_virtual_nmis(void)
276{
277 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
278}
279
8b9cf98c 280static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 281{
282 int i;
283
a2fa3e9f
GH		 284 for (i = 0; i < vmx->nmsrs; ++i)
285 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 286 return i;
287 return -1;
288}
289
2384d2b3
SY		 290static inline void __invvpid(int ext, u16 vpid, gva_t gva)
291{
292 struct {
293 u64 vpid : 16;
294 u64 rsvd : 48;
295 u64 gva;
296 } operand = { vpid, 0, gva };
297
4ecac3fd 298 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 299 /* CF==1 or ZF==1 --> rc = -1 */
300 "; ja 1f ; ud2 ; 1:"
301 : : "a"(&operand), "c"(ext) : "cc", "memory");
302}
303
1439442c
SY		 304static inline void __invept(int ext, u64 eptp, gpa_t gpa)
305{
306 struct {
307 u64 eptp, gpa;
308 } operand = {eptp, gpa};
309
4ecac3fd 310 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 311 /* CF==1 or ZF==1 --> rc = -1 */
312 "; ja 1f ; ud2 ; 1:\n"
313 : : "a" (&operand), "c" (ext) : "cc", "memory");
314}
315
8b9cf98c 316static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 317{
318 int i;
319
8b9cf98c 320 i = __find_msr_index(vmx, msr);
a75beee6 321 if (i >= 0)
a2fa3e9f 322 return &vmx->guest_msrs[i];
8b6d44c7 323 return NULL;
7725f0ba
AK		 324}
325
6aa8b732
AK		 326static void vmcs_clear(struct vmcs *vmcs)
327{
328 u64 phys_addr = __pa(vmcs);
329 u8 error;
330
4ecac3fd 331 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 332 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
333 : "cc", "memory");
334 if (error)
335 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
336 vmcs, phys_addr);
337}
338
339static void __vcpu_clear(void *arg)
340{
8b9cf98c 341 struct vcpu_vmx *vmx = arg;
d3b2c338 342 int cpu = raw_smp_processor_id();
6aa8b732 343
8b9cf98c 344 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 345 vmcs_clear(vmx->vmcs);
346 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 347 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 348 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 349 list_del(&vmx->local_vcpus_link);
350 vmx->vcpu.cpu = -1;
351 vmx->launched = 0;
6aa8b732
AK		 352}
353
8b9cf98c 354static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 355{
eae5ecb5
AK		 356 if (vmx->vcpu.cpu == -1)
357 return;
8691e5a8 358 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 359}
360
2384d2b3
SY		 361static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
362{
363 if (vmx->vpid == 0)
364 return;
365
366 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
367}
368
1439442c
SY		 369static inline void ept_sync_global(void)
370{
371 if (cpu_has_vmx_invept_global())
372 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
373}
374
375static inline void ept_sync_context(u64 eptp)
376{
377 if (vm_need_ept()) {
378 if (cpu_has_vmx_invept_context())
379 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
380 else
381 ept_sync_global();
382 }
383}
384
385static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
386{
387 if (vm_need_ept()) {
388 if (cpu_has_vmx_invept_individual_addr())
389 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
390 eptp, gpa);
391 else
392 ept_sync_context(eptp);
393 }
394}
395
6aa8b732
AK		 396static unsigned long vmcs_readl(unsigned long field)
397{
398 unsigned long value;
399
4ecac3fd 400 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 401 : "=a"(value) : "d"(field) : "cc");
402 return value;
403}
404
405static u16 vmcs_read16(unsigned long field)
406{
407 return vmcs_readl(field);
408}
409
410static u32 vmcs_read32(unsigned long field)
411{
412 return vmcs_readl(field);
413}
414
415static u64 vmcs_read64(unsigned long field)
416{
05b3e0c2 417#ifdef CONFIG_X86_64
6aa8b732
AK		 418 return vmcs_readl(field);
419#else
420 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
421#endif
422}
423
e52de1b8
AK		 424static noinline void vmwrite_error(unsigned long field, unsigned long value)
425{
426 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
427 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
428 dump_stack();
429}
430
6aa8b732
AK		 431static void vmcs_writel(unsigned long field, unsigned long value)
432{
433 u8 error;
434
4ecac3fd 435 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 436 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 437 if (unlikely(error))
438 vmwrite_error(field, value);
6aa8b732
AK		 439}
440
441static void vmcs_write16(unsigned long field, u16 value)
442{
443 vmcs_writel(field, value);
444}
445
446static void vmcs_write32(unsigned long field, u32 value)
447{
448 vmcs_writel(field, value);
449}
450
451static void vmcs_write64(unsigned long field, u64 value)
452{
6aa8b732 453 vmcs_writel(field, value);
7682f2d0 454#ifndef CONFIG_X86_64
6aa8b732
AK		 455 asm volatile ("");
456 vmcs_writel(field+1, value >> 32);
457#endif
458}
459
2ab455cc
AL		 460static void vmcs_clear_bits(unsigned long field, u32 mask)
461{
462 vmcs_writel(field, vmcs_readl(field) & ~mask);
463}
464
465static void vmcs_set_bits(unsigned long field, u32 mask)
466{
467 vmcs_writel(field, vmcs_readl(field) | mask);
468}
469
abd3f2d6
AK		 470static void update_exception_bitmap(struct kvm_vcpu *vcpu)
471{
472 u32 eb;
473
7aa81cc0 474 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 475 if (!vcpu->fpu_active)
476 eb |= 1u << NM_VECTOR;
477 if (vcpu->guest_debug.enabled)
19bd8afd 478 eb |= 1u << DB_VECTOR;
ad312c7c 479 if (vcpu->arch.rmode.active)
abd3f2d6 480 eb = ~0;
1439442c
SY		 481 if (vm_need_ept())
482 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 483 vmcs_write32(EXCEPTION_BITMAP, eb);
484}
485
33ed6329
AK		 486static void reload_tss(void)
487{
33ed6329
AK		 488 /*
489 * VT restores TR but not its size. Useless.
490 */
491 struct descriptor_table gdt;
a5f61300 492 struct desc_struct *descs;
33ed6329 493
d6e88aec 494 kvm_get_gdt(&gdt);
33ed6329
AK		 495 descs = (void *)gdt.base;
496 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
497 load_TR_desc();
33ed6329
AK		 498}
499
8b9cf98c 500static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 501{
a2fa3e9f 502 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 503 u64 host_efer = vmx->host_msrs[efer_offset].data;
504 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
505 u64 ignore_bits;
506
507 if (efer_offset < 0)
508 return;
509 /*
510 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
511 * outside long mode
512 */
513 ignore_bits = EFER_NX | EFER_SCE;
514#ifdef CONFIG_X86_64
515 ignore_bits |= EFER_LMA | EFER_LME;
516 /* SCE is meaningful only in long mode on Intel */
517 if (guest_efer & EFER_LMA)
518 ignore_bits &= ~(u64)EFER_SCE;
519#endif
520 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
521 return;
2cc51560 522
51c6cf66
AK		 523 vmx->host_state.guest_efer_loaded = 1;
524 guest_efer &= ~ignore_bits;
525 guest_efer |= host_efer & ignore_bits;
526 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 527 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 528}
529
51c6cf66
AK		 530static void reload_host_efer(struct vcpu_vmx *vmx)
531{
532 if (vmx->host_state.guest_efer_loaded) {
533 vmx->host_state.guest_efer_loaded = 0;
534 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
535 }
536}
537
04d2cc77 538static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 539{
04d2cc77
AK		 540 struct vcpu_vmx *vmx = to_vmx(vcpu);
541
a2fa3e9f 542 if (vmx->host_state.loaded)
33ed6329
AK		 543 return;
544
a2fa3e9f 545 vmx->host_state.loaded = 1;
33ed6329
AK		 546 /*
547 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
548 * allow segment selectors with cpl > 0 or ti == 1.
549 */
d6e88aec 550 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 551 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 552 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 553 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 554 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 555 vmx->host_state.fs_reload_needed = 0;
556 } else {
33ed6329 557 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 558 vmx->host_state.fs_reload_needed = 1;
33ed6329 559 }
d6e88aec 560 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 561 if (!(vmx->host_state.gs_sel & 7))
562 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 563 else {
564 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 565 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 566 }
567
568#ifdef CONFIG_X86_64
569 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
570 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
571#else
a2fa3e9f
GH		 572 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
573 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 574#endif
707c0874
AK		 575
576#ifdef CONFIG_X86_64
d77c26fc 577 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 578 save_msrs(vmx->host_msrs +
579 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 580
707c0874 581#endif
a2fa3e9f 582 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 583 load_transition_efer(vmx);
33ed6329
AK		 584}
585
a9b21b62 586static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 587{
15ad7146 588 unsigned long flags;
33ed6329 589
a2fa3e9f 590 if (!vmx->host_state.loaded)
33ed6329
AK		 591 return;
592
e1beb1d3 593 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 594 vmx->host_state.loaded = 0;
152d3f2f 595 if (vmx->host_state.fs_reload_needed)
d6e88aec 596 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 597 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 598 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 599 /*
600 * If we have to reload gs, we must take care to
601 * preserve our gs base.
602 */
15ad7146 603 local_irq_save(flags);
d6e88aec 604 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 605#ifdef CONFIG_X86_64
606 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
607#endif
15ad7146 608 local_irq_restore(flags);
33ed6329 609 }
152d3f2f 610 reload_tss();
a2fa3e9f
GH		 611 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
612 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 613 reload_host_efer(vmx);
33ed6329
AK		 614}
615
a9b21b62
AK		 616static void vmx_load_host_state(struct vcpu_vmx *vmx)
617{
618 preempt_disable();
619 __vmx_load_host_state(vmx);
620 preempt_enable();
621}
622
6aa8b732
AK		 623/*
624 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
625 * vcpu mutex is already taken.
626 */
15ad7146 627static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 628{
a2fa3e9f
GH		 629 struct vcpu_vmx *vmx = to_vmx(vcpu);
630 u64 phys_addr = __pa(vmx->vmcs);
019960ae 631 u64 tsc_this, delta, new_offset;
6aa8b732 632
a3d7f85f 633 if (vcpu->cpu != cpu) {
8b9cf98c 634 vcpu_clear(vmx);
2f599714 635 kvm_migrate_timers(vcpu);
2384d2b3 636 vpid_sync_vcpu_all(vmx);
543e4243
AK		 637 local_irq_disable();
638 list_add(&vmx->local_vcpus_link,
639 &per_cpu(vcpus_on_cpu, cpu));
640 local_irq_enable();
a3d7f85f 641 }
6aa8b732 642
a2fa3e9f 643 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 644 u8 error;
645
a2fa3e9f 646 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 647 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 648 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
649 : "cc");
650 if (error)
651 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 652 vmx->vmcs, phys_addr);
6aa8b732
AK		 653 }
654
655 if (vcpu->cpu != cpu) {
656 struct descriptor_table dt;
657 unsigned long sysenter_esp;
658
659 vcpu->cpu = cpu;
660 /*
661 * Linux uses per-cpu TSS and GDT, so set these when switching
662 * processors.
663 */
d6e88aec
AK		 664 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
665 kvm_get_gdt(&dt);
6aa8b732
AK		 666 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
667
668 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
669 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 670
671 /*
672 * Make sure the time stamp counter is monotonous.
673 */
674 rdtscll(tsc_this);
019960ae
AK		 675 if (tsc_this < vcpu->arch.host_tsc) {
676 delta = vcpu->arch.host_tsc - tsc_this;
677 new_offset = vmcs_read64(TSC_OFFSET) + delta;
678 vmcs_write64(TSC_OFFSET, new_offset);
679 }
6aa8b732 680 }
6aa8b732
AK		 681}
682
683static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
684{
a9b21b62 685 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 686}
687
5fd86fcf
AK		 688static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
689{
690 if (vcpu->fpu_active)
691 return;
692 vcpu->fpu_active = 1;
707d92fa 693 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 694 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 695 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 696 update_exception_bitmap(vcpu);
697}
698
699static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
700{
701 if (!vcpu->fpu_active)
702 return;
703 vcpu->fpu_active = 0;
707d92fa 704 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 705 update_exception_bitmap(vcpu);
706}
707
6aa8b732
AK		 708static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
709{
710 return vmcs_readl(GUEST_RFLAGS);
711}
712
713static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
714{
ad312c7c 715 if (vcpu->arch.rmode.active)
053de044 716 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 717 vmcs_writel(GUEST_RFLAGS, rflags);
718}
719
720static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
721{
722 unsigned long rip;
723 u32 interruptibility;
724
5fdbf976 725 rip = kvm_rip_read(vcpu);
6aa8b732 726 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 727 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 728
729 /*
730 * We emulated an instruction, so temporary interrupt blocking
731 * should be removed, if set.
732 */
733 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
734 if (interruptibility & 3)
735 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
736 interruptibility & ~3);
ad312c7c 737 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 738}
739
298101da
AK		 740static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
741 bool has_error_code, u32 error_code)
742{
77ab6db0
JK		 743 struct vcpu_vmx *vmx = to_vmx(vcpu);
744
745 if (has_error_code)
746 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
747
748 if (vcpu->arch.rmode.active) {
749 vmx->rmode.irq.pending = true;
750 vmx->rmode.irq.vector = nr;
751 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
752 if (nr == BP_VECTOR)
753 vmx->rmode.irq.rip++;
754 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
755 nr | INTR_TYPE_SOFT_INTR
756 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
757 | INTR_INFO_VALID_MASK);
758 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
759 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
760 return;
761 }
762
298101da
AK		 763 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
764 nr | INTR_TYPE_EXCEPTION
2e11384c 765 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da 766 | INTR_INFO_VALID_MASK);
298101da
AK		 767}
768
769static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
770{
35920a35 771 return false;
298101da
AK		 772}
773
a75beee6
ED		 774/*
775 * Swap MSR entry in host/guest MSR entry array.
776 */
54e11fa1 777#ifdef CONFIG_X86_64
8b9cf98c 778static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 779{
a2fa3e9f
GH		 780 struct kvm_msr_entry tmp;
781
782 tmp = vmx->guest_msrs[to];
783 vmx->guest_msrs[to] = vmx->guest_msrs[from];
784 vmx->guest_msrs[from] = tmp;
785 tmp = vmx->host_msrs[to];
786 vmx->host_msrs[to] = vmx->host_msrs[from];
787 vmx->host_msrs[from] = tmp;
a75beee6 788}
54e11fa1 789#endif
a75beee6 790
e38aea3e
AK		 791/*
792 * Set up the vmcs to automatically save and restore system
793 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
794 * mode, as fiddling with msrs is very expensive.
795 */
8b9cf98c 796static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 797{
2cc51560 798 int save_nmsrs;
e38aea3e 799
33f9c505 800 vmx_load_host_state(vmx);
a75beee6
ED		 801 save_nmsrs = 0;
802#ifdef CONFIG_X86_64
8b9cf98c 803 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 804 int index;
805
8b9cf98c 806 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 807 if (index >= 0)
8b9cf98c
RR		 808 move_msr_up(vmx, index, save_nmsrs++);
809 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 810 if (index >= 0)
8b9cf98c
RR		 811 move_msr_up(vmx, index, save_nmsrs++);
812 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 813 if (index >= 0)
8b9cf98c
RR		 814 move_msr_up(vmx, index, save_nmsrs++);
815 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 816 if (index >= 0)
8b9cf98c 817 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 818 /*
819 * MSR_K6_STAR is only needed on long mode guests, and only
820 * if efer.sce is enabled.
821 */
8b9cf98c 822 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 823 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 824 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 825 }
826#endif
a2fa3e9f 827 vmx->save_nmsrs = save_nmsrs;
e38aea3e 828
4d56c8a7 829#ifdef CONFIG_X86_64
a2fa3e9f 830 vmx->msr_offset_kernel_gs_base =
8b9cf98c 831 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 832#endif
8b9cf98c 833 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 834}
835
6aa8b732
AK		 836/*
837 * reads and returns guest's timestamp counter "register"
838 * guest_tsc = host_tsc + tsc_offset -- 21.3
839 */
840static u64 guest_read_tsc(void)
841{
842 u64 host_tsc, tsc_offset;
843
844 rdtscll(host_tsc);
845 tsc_offset = vmcs_read64(TSC_OFFSET);
846 return host_tsc + tsc_offset;
847}
848
849/*
850 * writes 'guest_tsc' into guest's timestamp counter "register"
851 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
852 */
853static void guest_write_tsc(u64 guest_tsc)
854{
855 u64 host_tsc;
856
857 rdtscll(host_tsc);
858 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
859}
860
6aa8b732
AK		 861/*
862 * Reads an msr value (of 'msr_index') into 'pdata'.
863 * Returns 0 on success, non-0 otherwise.
864 * Assumes vcpu_load() was already called.
865 */
866static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
867{
868 u64 data;
a2fa3e9f 869 struct kvm_msr_entry *msr;
6aa8b732
AK		 870
871 if (!pdata) {
872 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
873 return -EINVAL;
874 }
875
876 switch (msr_index) {
05b3e0c2 877#ifdef CONFIG_X86_64
6aa8b732
AK		 878 case MSR_FS_BASE:
879 data = vmcs_readl(GUEST_FS_BASE);
880 break;
881 case MSR_GS_BASE:
882 data = vmcs_readl(GUEST_GS_BASE);
883 break;
884 case MSR_EFER:
3bab1f5d 885 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 886#endif
887 case MSR_IA32_TIME_STAMP_COUNTER:
888 data = guest_read_tsc();
889 break;
890 case MSR_IA32_SYSENTER_CS:
891 data = vmcs_read32(GUEST_SYSENTER_CS);
892 break;
893 case MSR_IA32_SYSENTER_EIP:
f5b42c33 894 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 895 break;
896 case MSR_IA32_SYSENTER_ESP:
f5b42c33 897 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 898 break;
6aa8b732 899 default:
8b9cf98c 900 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 901 if (msr) {
902 data = msr->data;
903 break;
6aa8b732 904 }
3bab1f5d 905 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 906 }
907
908 *pdata = data;
909 return 0;
910}
911
912/*
913 * Writes msr value into into the appropriate "register".
914 * Returns 0 on success, non-0 otherwise.
915 * Assumes vcpu_load() was already called.
916 */
917static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
918{
a2fa3e9f
GH		 919 struct vcpu_vmx *vmx = to_vmx(vcpu);
920 struct kvm_msr_entry *msr;
2cc51560
ED		 921 int ret = 0;
922
6aa8b732 923 switch (msr_index) {
05b3e0c2 924#ifdef CONFIG_X86_64
3bab1f5d 925 case MSR_EFER:
a9b21b62 926 vmx_load_host_state(vmx);
2cc51560 927 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 928 break;
6aa8b732
AK		 929 case MSR_FS_BASE:
930 vmcs_writel(GUEST_FS_BASE, data);
931 break;
932 case MSR_GS_BASE:
933 vmcs_writel(GUEST_GS_BASE, data);
934 break;
935#endif
936 case MSR_IA32_SYSENTER_CS:
937 vmcs_write32(GUEST_SYSENTER_CS, data);
938 break;
939 case MSR_IA32_SYSENTER_EIP:
f5b42c33 940 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 941 break;
942 case MSR_IA32_SYSENTER_ESP:
f5b42c33 943 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 944 break;
d27d4aca 945 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732 946 guest_write_tsc(data);
efa67e0d
CL		 947 break;
948 case MSR_P6_PERFCTR0:
949 case MSR_P6_PERFCTR1:
950 case MSR_P6_EVNTSEL0:
951 case MSR_P6_EVNTSEL1:
952 /*
953 * Just discard all writes to the performance counters; this
954 * should keep both older linux and windows 64-bit guests
955 * happy
956 */
957 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
958
6aa8b732 959 break;
6aa8b732 960 default:
a9b21b62 961 vmx_load_host_state(vmx);
8b9cf98c 962 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 963 if (msr) {
964 msr->data = data;
965 break;
6aa8b732 966 }
2cc51560 967 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 968 }
969
2cc51560 970 return ret;
6aa8b732
AK		 971}
972
5fdbf976 973static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 974{
5fdbf976
MT		 975 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
976 switch (reg) {
977 case VCPU_REGS_RSP:
978 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
979 break;
980 case VCPU_REGS_RIP:
981 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
982 break;
983 default:
984 break;
985 }
6aa8b732
AK		 986}
987
988static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
989{
990 unsigned long dr7 = 0x400;
6aa8b732
AK		 991 int old_singlestep;
992
6aa8b732
AK		 993 old_singlestep = vcpu->guest_debug.singlestep;
994
995 vcpu->guest_debug.enabled = dbg->enabled;
996 if (vcpu->guest_debug.enabled) {
997 int i;
998
999 dr7 |= 0x200; /* exact */
1000 for (i = 0; i < 4; ++i) {
1001 if (!dbg->breakpoints[i].enabled)
1002 continue;
1003 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
1004 dr7 |= 2 << (i*2); /* global enable */
1005 dr7 |= 0 << (i*4+16); /* execution breakpoint */
1006 }
1007
6aa8b732 1008 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 1009 } else
6aa8b732 1010 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 1011
1012 if (old_singlestep && !vcpu->guest_debug.singlestep) {
1013 unsigned long flags;
1014
1015 flags = vmcs_readl(GUEST_RFLAGS);
1016 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1017 vmcs_writel(GUEST_RFLAGS, flags);
1018 }
1019
abd3f2d6 1020 update_exception_bitmap(vcpu);
6aa8b732
AK		 1021 vmcs_writel(GUEST_DR7, dr7);
1022
1023 return 0;
1024}
1025
2a8067f1
ED		 1026static int vmx_get_irq(struct kvm_vcpu *vcpu)
1027{
f7d9238f
AK		 1028 if (!vcpu->arch.interrupt.pending)
1029 return -1;
1030 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1031}
1032
6aa8b732
AK		 1033static __init int cpu_has_kvm_support(void)
1034{
1035 unsigned long ecx = cpuid_ecx(1);
1036 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1037}
1038
1039static __init int vmx_disabled_by_bios(void)
1040{
1041 u64 msr;
1042
1043 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
ca60dfbb
SY		 1044 return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1045 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1046 == IA32_FEATURE_CONTROL_LOCKED_BIT;
62b3ffb8 1047 /* locked but not enabled */
6aa8b732
AK		 1048}
1049
774c47f1 1050static void hardware_enable(void *garbage)
6aa8b732
AK		 1051{
1052 int cpu = raw_smp_processor_id();
1053 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1054 u64 old;
1055
543e4243 1056 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1057 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
ca60dfbb
SY		 1058 if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1059 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1060 != (IA32_FEATURE_CONTROL_LOCKED_BIT |
1061 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
6aa8b732 1062 /* enable and lock */
62b3ffb8 1063 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
ca60dfbb
SY		 1064 IA32_FEATURE_CONTROL_LOCKED_BIT |
1065 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT);
66aee91a 1066 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1067 asm volatile (ASM_VMX_VMXON_RAX
1068 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1069 : "memory", "cc");
1070}
1071
543e4243
AK		 1072static void vmclear_local_vcpus(void)
1073{
1074 int cpu = raw_smp_processor_id();
1075 struct vcpu_vmx *vmx, *n;
1076
1077 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1078 local_vcpus_link)
1079 __vcpu_clear(vmx);
1080}
1081
6aa8b732
AK		 1082static void hardware_disable(void *garbage)
1083{
543e4243 1084 vmclear_local_vcpus();
4ecac3fd 1085 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1086 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1087}
1088
1c3d14fe 1089static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1090 u32 msr, u32 *result)
1c3d14fe
YS		 1091{
1092 u32 vmx_msr_low, vmx_msr_high;
1093 u32 ctl = ctl_min | ctl_opt;
1094
1095 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1096
1097 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1098 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1099
1100 /* Ensure minimum (required) set of control bits are supported. */
1101 if (ctl_min & ~ctl)
002c7f7c 1102 return -EIO;
1c3d14fe
YS		 1103
1104 *result = ctl;
1105 return 0;
1106}
1107
002c7f7c 1108static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1109{
1110 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1111 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1112 u32 _pin_based_exec_control = 0;
1113 u32 _cpu_based_exec_control = 0;
f78e0e2e 1114 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1115 u32 _vmexit_control = 0;
1116 u32 _vmentry_control = 0;
1117
1118 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1119 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1120 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1121 &_pin_based_exec_control) < 0)
002c7f7c 1122 return -EIO;
1c3d14fe
YS		 1123
1124 min = CPU_BASED_HLT_EXITING |
1125#ifdef CONFIG_X86_64
1126 CPU_BASED_CR8_LOAD_EXITING |
1127 CPU_BASED_CR8_STORE_EXITING |
1128#endif
d56f546d
SY		 1129 CPU_BASED_CR3_LOAD_EXITING |
1130 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1131 CPU_BASED_USE_IO_BITMAPS |
1132 CPU_BASED_MOV_DR_EXITING |
1133 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e 1134 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1135 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1136 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1137 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1138 &_cpu_based_exec_control) < 0)
002c7f7c 1139 return -EIO;
6e5d865c
YS		 1140#ifdef CONFIG_X86_64
1141 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1142 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1143 ~CPU_BASED_CR8_STORE_EXITING;
1144#endif
f78e0e2e 1145 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1146 min2 = 0;
1147 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1148 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1149 SECONDARY_EXEC_ENABLE_VPID |
1150 SECONDARY_EXEC_ENABLE_EPT;
1151 if (adjust_vmx_controls(min2, opt2,
1152 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1153 &_cpu_based_2nd_exec_control) < 0)
1154 return -EIO;
1155 }
1156#ifndef CONFIG_X86_64
1157 if (!(_cpu_based_2nd_exec_control &
1158 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1159 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1160#endif
d56f546d
SY		 1161 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1162 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1163 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1164 CPU_BASED_CR3_STORE_EXITING);
1165 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1166 &_cpu_based_exec_control) < 0)
1167 return -EIO;
1168 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1169 vmx_capability.ept, vmx_capability.vpid);
1170 }
1c3d14fe
YS		 1171
1172 min = 0;
1173#ifdef CONFIG_X86_64
1174 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1175#endif
1176 opt = 0;
1177 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1178 &_vmexit_control) < 0)
002c7f7c 1179 return -EIO;
1c3d14fe
YS		 1180
1181 min = opt = 0;
1182 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1183 &_vmentry_control) < 0)
002c7f7c 1184 return -EIO;
6aa8b732 1185
c68876fd 1186 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1187
1188 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1189 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1190 return -EIO;
1c3d14fe
YS		 1191
1192#ifdef CONFIG_X86_64
1193 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1194 if (vmx_msr_high & (1u<<16))
002c7f7c 1195 return -EIO;
1c3d14fe
YS		 1196#endif
1197
1198 /* Require Write-Back (WB) memory type for VMCS accesses. */
1199 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1200 return -EIO;
1c3d14fe 1201
002c7f7c
YS		 1202 vmcs_conf->size = vmx_msr_high & 0x1fff;
1203 vmcs_conf->order = get_order(vmcs_config.size);
1204 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1205
002c7f7c
YS		 1206 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1207 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1208 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1209 vmcs_conf->vmexit_ctrl = _vmexit_control;
1210 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1211
1212 return 0;
c68876fd 1213}
6aa8b732
AK		 1214
1215static struct vmcs *alloc_vmcs_cpu(int cpu)
1216{
1217 int node = cpu_to_node(cpu);
1218 struct page *pages;
1219 struct vmcs *vmcs;
1220
1c3d14fe 1221 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1222 if (!pages)
1223 return NULL;
1224 vmcs = page_address(pages);
1c3d14fe
YS		 1225 memset(vmcs, 0, vmcs_config.size);
1226 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1227 return vmcs;
1228}
1229
1230static struct vmcs *alloc_vmcs(void)
1231{
d3b2c338 1232 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1233}
1234
1235static void free_vmcs(struct vmcs *vmcs)
1236{
1c3d14fe 1237 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1238}
1239
39959588 1240static void free_kvm_area(void)
6aa8b732
AK		 1241{
1242 int cpu;
1243
1244 for_each_online_cpu(cpu)
1245 free_vmcs(per_cpu(vmxarea, cpu));
1246}
1247
6aa8b732
AK		 1248static __init int alloc_kvm_area(void)
1249{
1250 int cpu;
1251
1252 for_each_online_cpu(cpu) {
1253 struct vmcs *vmcs;
1254
1255 vmcs = alloc_vmcs_cpu(cpu);
1256 if (!vmcs) {
1257 free_kvm_area();
1258 return -ENOMEM;
1259 }
1260
1261 per_cpu(vmxarea, cpu) = vmcs;
1262 }
1263 return 0;
1264}
1265
1266static __init int hardware_setup(void)
1267{
002c7f7c
YS		 1268 if (setup_vmcs_config(&vmcs_config) < 0)
1269 return -EIO;
50a37eb4
JR		 1270
1271 if (boot_cpu_has(X86_FEATURE_NX))
1272 kvm_enable_efer_bits(EFER_NX);
1273
6aa8b732
AK		 1274 return alloc_kvm_area();
1275}
1276
1277static __exit void hardware_unsetup(void)
1278{
1279 free_kvm_area();
1280}
1281
6aa8b732
AK		 1282static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1283{
1284 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1285
6af11b9e 1286 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1287 vmcs_write16(sf->selector, save->selector);
1288 vmcs_writel(sf->base, save->base);
1289 vmcs_write32(sf->limit, save->limit);
1290 vmcs_write32(sf->ar_bytes, save->ar);
1291 } else {
1292 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1293 << AR_DPL_SHIFT;
1294 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1295 }
1296}
1297
1298static void enter_pmode(struct kvm_vcpu *vcpu)
1299{
1300 unsigned long flags;
1301
ad312c7c 1302 vcpu->arch.rmode.active = 0;
6aa8b732 1303
ad312c7c
ZX		 1304 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1305 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1306 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1307
1308 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1309 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1310 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1311 vmcs_writel(GUEST_RFLAGS, flags);
1312
66aee91a
RR		 1313 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1314 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1315
1316 update_exception_bitmap(vcpu);
1317
ad312c7c
ZX		 1318 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1319 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1320 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1321 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1322
1323 vmcs_write16(GUEST_SS_SELECTOR, 0);
1324 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1325
1326 vmcs_write16(GUEST_CS_SELECTOR,
1327 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1328 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1329}
1330
d77c26fc 1331static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1332{
bfc6d222 1333 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1334 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1335 kvm->memslots[0].npages - 3;
1336 return base_gfn << PAGE_SHIFT;
1337 }
bfc6d222 1338 return kvm->arch.tss_addr;
6aa8b732
AK		 1339}
1340
1341static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1342{
1343 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1344
1345 save->selector = vmcs_read16(sf->selector);
1346 save->base = vmcs_readl(sf->base);
1347 save->limit = vmcs_read32(sf->limit);
1348 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1349 vmcs_write16(sf->selector, save->base >> 4);
1350 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1351 vmcs_write32(sf->limit, 0xffff);
1352 vmcs_write32(sf->ar_bytes, 0xf3);
1353}
1354
1355static void enter_rmode(struct kvm_vcpu *vcpu)
1356{
1357 unsigned long flags;
1358
ad312c7c 1359 vcpu->arch.rmode.active = 1;
6aa8b732 1360
ad312c7c 1361 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1362 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1363
ad312c7c 1364 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1365 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1366
ad312c7c 1367 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1368 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1369
1370 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1371 vcpu->arch.rmode.save_iopl
1372 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1373
053de044 1374 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1375
1376 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1377 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1378 update_exception_bitmap(vcpu);
1379
1380 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1381 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1382 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1383
1384 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1385 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1386 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1387 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1388 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1389
ad312c7c
ZX		 1390 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1391 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1392 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1393 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1394
8668a3c4 1395 kvm_mmu_reset_context(vcpu);
b7ebfb05 1396 init_rmode(vcpu->kvm);
6aa8b732
AK		 1397}
1398
05b3e0c2 1399#ifdef CONFIG_X86_64
6aa8b732
AK		 1400
1401static void enter_lmode(struct kvm_vcpu *vcpu)
1402{
1403 u32 guest_tr_ar;
1404
1405 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1406 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1407 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1408 __func__);
6aa8b732
AK		 1409 vmcs_write32(GUEST_TR_AR_BYTES,
1410 (guest_tr_ar & ~AR_TYPE_MASK)
1411 | AR_TYPE_BUSY_64_TSS);
1412 }
1413
ad312c7c 1414 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1415
8b9cf98c 1416 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1417 vmcs_write32(VM_ENTRY_CONTROLS,
1418 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1419 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1420}
1421
1422static void exit_lmode(struct kvm_vcpu *vcpu)
1423{
ad312c7c 1424 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1425
1426 vmcs_write32(VM_ENTRY_CONTROLS,
1427 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1428 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1429}
1430
1431#endif
1432
2384d2b3
SY		 1433static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1434{
1435 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1436 if (vm_need_ept())
1437 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1438}
1439
25c4c276 1440static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1441{
ad312c7c
ZX		 1442 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1443 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1444}
1445
1439442c
SY		 1446static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1447{
1448 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1449 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1450 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1451 return;
1452 }
1453 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1454 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1455 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1456 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1457 }
1458}
1459
1460static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1461
1462static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1463 unsigned long cr0,
1464 struct kvm_vcpu *vcpu)
1465{
1466 if (!(cr0 & X86_CR0_PG)) {
1467 /* From paging/starting to nonpaging */
1468 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1469 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1470 (CPU_BASED_CR3_LOAD_EXITING |
1471 CPU_BASED_CR3_STORE_EXITING));
1472 vcpu->arch.cr0 = cr0;
1473 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1474 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1475 *hw_cr0 &= ~X86_CR0_WP;
1476 } else if (!is_paging(vcpu)) {
1477 /* From nonpaging to paging */
1478 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1479 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1480 ~(CPU_BASED_CR3_LOAD_EXITING |
1481 CPU_BASED_CR3_STORE_EXITING));
1482 vcpu->arch.cr0 = cr0;
1483 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1484 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1485 *hw_cr0 &= ~X86_CR0_WP;
1486 }
1487}
1488
1489static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1490 struct kvm_vcpu *vcpu)
1491{
1492 if (!is_paging(vcpu)) {
1493 *hw_cr4 &= ~X86_CR4_PAE;
1494 *hw_cr4 |= X86_CR4_PSE;
1495 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1496 *hw_cr4 &= ~X86_CR4_PAE;
1497}
1498
6aa8b732
AK		 1499static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1500{
1439442c
SY		 1501 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1502 KVM_VM_CR0_ALWAYS_ON;
1503
5fd86fcf
AK		 1504 vmx_fpu_deactivate(vcpu);
1505
ad312c7c 1506 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1507 enter_pmode(vcpu);
1508
ad312c7c 1509 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1510 enter_rmode(vcpu);
1511
05b3e0c2 1512#ifdef CONFIG_X86_64
ad312c7c 1513 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1515 enter_lmode(vcpu);
707d92fa 1516 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1517 exit_lmode(vcpu);
1518 }
1519#endif
1520
1439442c
SY		 1521 if (vm_need_ept())
1522 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1523
6aa8b732 1524 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1525 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1526 vcpu->arch.cr0 = cr0;
5fd86fcf 1527
707d92fa 1528 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1529 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1530}
1531
1439442c
SY		 1532static u64 construct_eptp(unsigned long root_hpa)
1533{
1534 u64 eptp;
1535
1536 /* TODO write the value reading from MSR */
1537 eptp = VMX_EPT_DEFAULT_MT |
1538 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1539 eptp |= (root_hpa & PAGE_MASK);
1540
1541 return eptp;
1542}
1543
6aa8b732
AK		 1544static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1545{
1439442c
SY		 1546 unsigned long guest_cr3;
1547 u64 eptp;
1548
1549 guest_cr3 = cr3;
1550 if (vm_need_ept()) {
1551 eptp = construct_eptp(cr3);
1552 vmcs_write64(EPT_POINTER, eptp);
1553 ept_sync_context(eptp);
1554 ept_load_pdptrs(vcpu);
1555 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1556 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1557 }
1558
2384d2b3 1559 vmx_flush_tlb(vcpu);
1439442c 1560 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1561 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1562 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1563}
1564
1565static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1566{
1439442c
SY		 1567 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1568 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1569
ad312c7c 1570 vcpu->arch.cr4 = cr4;
1439442c
SY		 1571 if (vm_need_ept())
1572 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1573
1574 vmcs_writel(CR4_READ_SHADOW, cr4);
1575 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1576}
1577
6aa8b732
AK		 1578static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1579{
8b9cf98c
RR		 1580 struct vcpu_vmx *vmx = to_vmx(vcpu);
1581 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1582
ad312c7c 1583 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1584 if (!msr)
1585 return;
6aa8b732
AK		 1586 if (efer & EFER_LMA) {
1587 vmcs_write32(VM_ENTRY_CONTROLS,
1588 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1589 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1590 msr->data = efer;
1591
1592 } else {
1593 vmcs_write32(VM_ENTRY_CONTROLS,
1594 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1595 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1596
1597 msr->data = efer & ~EFER_LME;
1598 }
8b9cf98c 1599 setup_msrs(vmx);
6aa8b732
AK		 1600}
1601
6aa8b732
AK		 1602static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1603{
1604 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1605
1606 return vmcs_readl(sf->base);
1607}
1608
1609static void vmx_get_segment(struct kvm_vcpu *vcpu,
1610 struct kvm_segment *var, int seg)
1611{
1612 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1613 u32 ar;
1614
1615 var->base = vmcs_readl(sf->base);
1616 var->limit = vmcs_read32(sf->limit);
1617 var->selector = vmcs_read16(sf->selector);
1618 ar = vmcs_read32(sf->ar_bytes);
1619 if (ar & AR_UNUSABLE_MASK)
1620 ar = 0;
1621 var->type = ar & 15;
1622 var->s = (ar >> 4) & 1;
1623 var->dpl = (ar >> 5) & 3;
1624 var->present = (ar >> 7) & 1;
1625 var->avl = (ar >> 12) & 1;
1626 var->l = (ar >> 13) & 1;
1627 var->db = (ar >> 14) & 1;
1628 var->g = (ar >> 15) & 1;
1629 var->unusable = (ar >> 16) & 1;
1630}
1631
2e4d2653
IE		 1632static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1633{
1634 struct kvm_segment kvm_seg;
1635
1636 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1637 return 0;
1638
1639 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1640 return 3;
1641
1642 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1643 return kvm_seg.selector & 3;
1644}
1645
653e3108 1646static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1647{
6aa8b732
AK		 1648 u32 ar;
1649
653e3108 1650 if (var->unusable)
6aa8b732
AK		 1651 ar = 1 << 16;
1652 else {
1653 ar = var->type & 15;
1654 ar |= (var->s & 1) << 4;
1655 ar |= (var->dpl & 3) << 5;
1656 ar |= (var->present & 1) << 7;
1657 ar |= (var->avl & 1) << 12;
1658 ar |= (var->l & 1) << 13;
1659 ar |= (var->db & 1) << 14;
1660 ar |= (var->g & 1) << 15;
1661 }
f7fbf1fd
UL		 1662 if (ar == 0) /* a 0 value means unusable */
1663 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1664
1665 return ar;
1666}
1667
1668static void vmx_set_segment(struct kvm_vcpu *vcpu,
1669 struct kvm_segment *var, int seg)
1670{
1671 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1672 u32 ar;
1673
ad312c7c
ZX		 1674 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1675 vcpu->arch.rmode.tr.selector = var->selector;
1676 vcpu->arch.rmode.tr.base = var->base;
1677 vcpu->arch.rmode.tr.limit = var->limit;
1678 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1679 return;
1680 }
1681 vmcs_writel(sf->base, var->base);
1682 vmcs_write32(sf->limit, var->limit);
1683 vmcs_write16(sf->selector, var->selector);
ad312c7c 1684 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1685 /*
1686 * Hack real-mode segments into vm86 compatibility.
1687 */
1688 if (var->base == 0xffff0000 && var->selector == 0xf000)
1689 vmcs_writel(sf->base, 0xf0000);
1690 ar = 0xf3;
1691 } else
1692 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1693 vmcs_write32(sf->ar_bytes, ar);
1694}
1695
6aa8b732
AK		 1696static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1697{
1698 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1699
1700 *db = (ar >> 14) & 1;
1701 *l = (ar >> 13) & 1;
1702}
1703
1704static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1705{
1706 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1707 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1708}
1709
1710static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1711{
1712 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1713 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1714}
1715
1716static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1717{
1718 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1719 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1720}
1721
1722static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1723{
1724 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1725 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1726}
1727
648dfaa7
MG		 1728static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1729{
1730 struct kvm_segment var;
1731 u32 ar;
1732
1733 vmx_get_segment(vcpu, &var, seg);
1734 ar = vmx_segment_access_rights(&var);
1735
1736 if (var.base != (var.selector << 4))
1737 return false;
1738 if (var.limit != 0xffff)
1739 return false;
1740 if (ar != 0xf3)
1741 return false;
1742
1743 return true;
1744}
1745
1746static bool code_segment_valid(struct kvm_vcpu *vcpu)
1747{
1748 struct kvm_segment cs;
1749 unsigned int cs_rpl;
1750
1751 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1752 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1753
1754 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1755 return false;
1756 if (!cs.s)
1757 return false;
1758 if (!(~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK))) {
1759 if (cs.dpl > cs_rpl)
1760 return false;
1761 } else if (cs.type & AR_TYPE_CODE_MASK) {
1762 if (cs.dpl != cs_rpl)
1763 return false;
1764 }
1765 if (!cs.present)
1766 return false;
1767
1768 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1769 return true;
1770}
1771
1772static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1773{
1774 struct kvm_segment ss;
1775 unsigned int ss_rpl;
1776
1777 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1778 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1779
1780 if ((ss.type != 3) || (ss.type != 7))
1781 return false;
1782 if (!ss.s)
1783 return false;
1784 if (ss.dpl != ss_rpl) /* DPL != RPL */
1785 return false;
1786 if (!ss.present)
1787 return false;
1788
1789 return true;
1790}
1791
1792static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1793{
1794 struct kvm_segment var;
1795 unsigned int rpl;
1796
1797 vmx_get_segment(vcpu, &var, seg);
1798 rpl = var.selector & SELECTOR_RPL_MASK;
1799
1800 if (!var.s)
1801 return false;
1802 if (!var.present)
1803 return false;
1804 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1805 if (var.dpl < rpl) /* DPL < RPL */
1806 return false;
1807 }
1808
1809 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1810 * rights flags
1811 */
1812 return true;
1813}
1814
1815static bool tr_valid(struct kvm_vcpu *vcpu)
1816{
1817 struct kvm_segment tr;
1818
1819 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1820
1821 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1822 return false;
1823 if ((tr.type != 3) || (tr.type != 11)) /* TODO: Check if guest is in IA32e mode */
1824 return false;
1825 if (!tr.present)
1826 return false;
1827
1828 return true;
1829}
1830
1831static bool ldtr_valid(struct kvm_vcpu *vcpu)
1832{
1833 struct kvm_segment ldtr;
1834
1835 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1836
1837 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1838 return false;
1839 if (ldtr.type != 2)
1840 return false;
1841 if (!ldtr.present)
1842 return false;
1843
1844 return true;
1845}
1846
1847static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1848{
1849 struct kvm_segment cs, ss;
1850
1851 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1852 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1853
1854 return ((cs.selector & SELECTOR_RPL_MASK) ==
1855 (ss.selector & SELECTOR_RPL_MASK));
1856}
1857
1858/*
1859 * Check if guest state is valid. Returns true if valid, false if
1860 * not.
1861 * We assume that registers are always usable
1862 */
1863static bool guest_state_valid(struct kvm_vcpu *vcpu)
1864{
1865 /* real mode guest state checks */
1866 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1867 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1868 return false;
1869 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1870 return false;
1871 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1872 return false;
1873 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1874 return false;
1875 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1876 return false;
1877 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1878 return false;
1879 } else {
1880 /* protected mode guest state checks */
1881 if (!cs_ss_rpl_check(vcpu))
1882 return false;
1883 if (!code_segment_valid(vcpu))
1884 return false;
1885 if (!stack_segment_valid(vcpu))
1886 return false;
1887 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1888 return false;
1889 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1890 return false;
1891 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1892 return false;
1893 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1894 return false;
1895 if (!tr_valid(vcpu))
1896 return false;
1897 if (!ldtr_valid(vcpu))
1898 return false;
1899 }
1900 /* TODO:
1901 * - Add checks on RIP
1902 * - Add checks on RFLAGS
1903 */
1904
1905 return true;
1906}
1907
d77c26fc 1908static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1909{
6aa8b732 1910 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1911 u16 data = 0;
10589a46 1912 int ret = 0;
195aefde 1913 int r;
6aa8b732 1914
195aefde
IE		 1915 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1916 if (r < 0)
10589a46 1917 goto out;
195aefde 1918 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 1919 r = kvm_write_guest_page(kvm, fn++, &data,
1920 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 1921 if (r < 0)
10589a46 1922 goto out;
195aefde
IE		 1923 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1924 if (r < 0)
10589a46 1925 goto out;
195aefde
IE		 1926 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1927 if (r < 0)
10589a46 1928 goto out;
195aefde 1929 data = ~0;
10589a46
MT		 1930 r = kvm_write_guest_page(kvm, fn, &data,
1931 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1932 sizeof(u8));
195aefde 1933 if (r < 0)
10589a46
MT		 1934 goto out;
1935
1936 ret = 1;
1937out:
10589a46 1938 return ret;
6aa8b732
AK		 1939}
1940
b7ebfb05
SY		 1941static int init_rmode_identity_map(struct kvm *kvm)
1942{
1943 int i, r, ret;
1944 pfn_t identity_map_pfn;
1945 u32 tmp;
1946
1947 if (!vm_need_ept())
1948 return 1;
1949 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1950 printk(KERN_ERR "EPT: identity-mapping pagetable "
1951 "haven't been allocated!\n");
1952 return 0;
1953 }
1954 if (likely(kvm->arch.ept_identity_pagetable_done))
1955 return 1;
1956 ret = 0;
1957 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1958 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1959 if (r < 0)
1960 goto out;
1961 /* Set up identity-mapping pagetable for EPT in real mode */
1962 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1963 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1964 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1965 r = kvm_write_guest_page(kvm, identity_map_pfn,
1966 &tmp, i * sizeof(tmp), sizeof(tmp));
1967 if (r < 0)
1968 goto out;
1969 }
1970 kvm->arch.ept_identity_pagetable_done = true;
1971 ret = 1;
1972out:
1973 return ret;
1974}
1975
6aa8b732
AK		 1976static void seg_setup(int seg)
1977{
1978 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1979
1980 vmcs_write16(sf->selector, 0);
1981 vmcs_writel(sf->base, 0);
1982 vmcs_write32(sf->limit, 0xffff);
1983 vmcs_write32(sf->ar_bytes, 0x93);
1984}
1985
f78e0e2e
SY		 1986static int alloc_apic_access_page(struct kvm *kvm)
1987{
1988 struct kvm_userspace_memory_region kvm_userspace_mem;
1989 int r = 0;
1990
72dc67a6 1991 down_write(&kvm->slots_lock);
bfc6d222 1992 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1993 goto out;
1994 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1995 kvm_userspace_mem.flags = 0;
1996 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1997 kvm_userspace_mem.memory_size = PAGE_SIZE;
1998 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1999 if (r)
2000 goto out;
72dc67a6
IE		 2001
2002 down_read(&current->mm->mmap_sem);
bfc6d222 2003 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 2004 up_read(&current->mm->mmap_sem);
f78e0e2e 2005out:
72dc67a6 2006 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2007 return r;
2008}
2009
b7ebfb05
SY		 2010static int alloc_identity_pagetable(struct kvm *kvm)
2011{
2012 struct kvm_userspace_memory_region kvm_userspace_mem;
2013 int r = 0;
2014
2015 down_write(&kvm->slots_lock);
2016 if (kvm->arch.ept_identity_pagetable)
2017 goto out;
2018 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2019 kvm_userspace_mem.flags = 0;
2020 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2021 kvm_userspace_mem.memory_size = PAGE_SIZE;
2022 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2023 if (r)
2024 goto out;
2025
2026 down_read(&current->mm->mmap_sem);
2027 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2028 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2029 up_read(&current->mm->mmap_sem);
2030out:
2031 up_write(&kvm->slots_lock);
2032 return r;
2033}
2034
2384d2b3
SY		 2035static void allocate_vpid(struct vcpu_vmx *vmx)
2036{
2037 int vpid;
2038
2039 vmx->vpid = 0;
2040 if (!enable_vpid || !cpu_has_vmx_vpid())
2041 return;
2042 spin_lock(&vmx_vpid_lock);
2043 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2044 if (vpid < VMX_NR_VPIDS) {
2045 vmx->vpid = vpid;
2046 __set_bit(vpid, vmx_vpid_bitmap);
2047 }
2048 spin_unlock(&vmx_vpid_lock);
2049}
2050
8b2cf73c 2051static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 2052{
2053 void *va;
2054
2055 if (!cpu_has_vmx_msr_bitmap())
2056 return;
2057
2058 /*
2059 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2060 * have the write-low and read-high bitmap offsets the wrong way round.
2061 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2062 */
2063 va = kmap(msr_bitmap);
2064 if (msr <= 0x1fff) {
2065 __clear_bit(msr, va + 0x000); /* read-low */
2066 __clear_bit(msr, va + 0x800); /* write-low */
2067 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2068 msr &= 0x1fff;
2069 __clear_bit(msr, va + 0x400); /* read-high */
2070 __clear_bit(msr, va + 0xc00); /* write-high */
2071 }
2072 kunmap(msr_bitmap);
2073}
2074
6aa8b732
AK		 2075/*
2076 * Sets up the vmcs for emulated real mode.
2077 */
8b9cf98c 2078static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 2079{
2080 u32 host_sysenter_cs;
2081 u32 junk;
2082 unsigned long a;
2083 struct descriptor_table dt;
2084 int i;
cd2276a7 2085 unsigned long kvm_vmx_return;
6e5d865c 2086 u32 exec_control;
6aa8b732 2087
6aa8b732 2088 /* I/O */
fdef3ad1
HQ		 2089 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2090 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 2091
25c5f225
SY		 2092 if (cpu_has_vmx_msr_bitmap())
2093 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2094
6aa8b732
AK		 2095 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2096
6aa8b732 2097 /* Control */
1c3d14fe
YS		 2098 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2099 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2100
2101 exec_control = vmcs_config.cpu_based_exec_ctrl;
2102 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2103 exec_control &= ~CPU_BASED_TPR_SHADOW;
2104#ifdef CONFIG_X86_64
2105 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2106 CPU_BASED_CR8_LOAD_EXITING;
2107#endif
2108 }
d56f546d
SY		 2109 if (!vm_need_ept())
2110 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2111 CPU_BASED_CR3_LOAD_EXITING;
6e5d865c 2112 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2113
83ff3b9d
SY		 2114 if (cpu_has_secondary_exec_ctrls()) {
2115 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2116 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2117 exec_control &=
2118 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2119 if (vmx->vpid == 0)
2120 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 2121 if (!vm_need_ept())
2122 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 2123 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2124 }
f78e0e2e 2125
c7addb90
AK		 2126 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2127 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2128 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2129
2130 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2131 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2132 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2133
2134 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2135 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2136 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2137 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2138 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2139 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2140#ifdef CONFIG_X86_64
6aa8b732
AK		 2141 rdmsrl(MSR_FS_BASE, a);
2142 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2143 rdmsrl(MSR_GS_BASE, a);
2144 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2145#else
2146 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2147 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2148#endif
2149
2150 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2151
d6e88aec 2152 kvm_get_idt(&dt);
6aa8b732
AK		 2153 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2154
d77c26fc 2155 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2156 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2157 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2158 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2159 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2160
2161 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2162 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2163 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2164 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2165 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2166 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2167
6aa8b732
AK		 2168 for (i = 0; i < NR_VMX_MSR; ++i) {
2169 u32 index = vmx_msr_index[i];
2170 u32 data_low, data_high;
2171 u64 data;
a2fa3e9f 2172 int j = vmx->nmsrs;
6aa8b732
AK		 2173
2174 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2175 continue;
432bd6cb
AK		 2176 if (wrmsr_safe(index, data_low, data_high) < 0)
2177 continue;
6aa8b732 2178 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 2179 vmx->host_msrs[j].index = index;
2180 vmx->host_msrs[j].reserved = 0;
2181 vmx->host_msrs[j].data = data;
2182 vmx->guest_msrs[j] = vmx->host_msrs[j];
2183 ++vmx->nmsrs;
6aa8b732 2184 }
6aa8b732 2185
1c3d14fe 2186 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2187
2188 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2189 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2190
e00c8cf2
AK		 2191 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2192 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2193
f78e0e2e 2194
e00c8cf2
AK		 2195 return 0;
2196}
2197
b7ebfb05
SY		 2198static int init_rmode(struct kvm *kvm)
2199{
2200 if (!init_rmode_tss(kvm))
2201 return 0;
2202 if (!init_rmode_identity_map(kvm))
2203 return 0;
2204 return 1;
2205}
2206
e00c8cf2
AK		 2207static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2208{
2209 struct vcpu_vmx *vmx = to_vmx(vcpu);
2210 u64 msr;
2211 int ret;
2212
5fdbf976 2213 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2214 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2215 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2216 ret = -ENOMEM;
2217 goto out;
2218 }
2219
ad312c7c 2220 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2221
ad312c7c 2222 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2223 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2224 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2225 if (vmx->vcpu.vcpu_id == 0)
2226 msr |= MSR_IA32_APICBASE_BSP;
2227 kvm_set_apic_base(&vmx->vcpu, msr);
2228
2229 fx_init(&vmx->vcpu);
2230
2231 /*
2232 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2233 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2234 */
2235 if (vmx->vcpu.vcpu_id == 0) {
2236 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2237 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2238 } else {
ad312c7c
ZX		 2239 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2240 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 2241 }
2242 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2243 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2244
2245 seg_setup(VCPU_SREG_DS);
2246 seg_setup(VCPU_SREG_ES);
2247 seg_setup(VCPU_SREG_FS);
2248 seg_setup(VCPU_SREG_GS);
2249 seg_setup(VCPU_SREG_SS);
2250
2251 vmcs_write16(GUEST_TR_SELECTOR, 0);
2252 vmcs_writel(GUEST_TR_BASE, 0);
2253 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2254 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2255
2256 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2257 vmcs_writel(GUEST_LDTR_BASE, 0);
2258 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2259 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2260
2261 vmcs_write32(GUEST_SYSENTER_CS, 0);
2262 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2263 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2264
2265 vmcs_writel(GUEST_RFLAGS, 0x02);
2266 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2267 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2268 else
5fdbf976
MT		 2269 kvm_rip_write(vcpu, 0);
2270 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2
AK		 2271
2272 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2273 vmcs_writel(GUEST_DR7, 0x400);
2274
2275 vmcs_writel(GUEST_GDTR_BASE, 0);
2276 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2277
2278 vmcs_writel(GUEST_IDTR_BASE, 0);
2279 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2280
2281 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2282 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2283 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2284
2285 guest_write_tsc(0);
2286
2287 /* Special registers */
2288 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2289
2290 setup_msrs(vmx);
2291
6aa8b732
AK		 2292 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2293
f78e0e2e
SY		 2294 if (cpu_has_vmx_tpr_shadow()) {
2295 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2296 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2297 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2298 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2299 vmcs_write32(TPR_THRESHOLD, 0);
2300 }
2301
2302 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2303 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2304 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2305
2384d2b3
SY		 2306 if (vmx->vpid != 0)
2307 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2308
ad312c7c
ZX		 2309 vmx->vcpu.arch.cr0 = 0x60000010;
2310 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2311 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2312 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2313 vmx_fpu_activate(&vmx->vcpu);
2314 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2315
2384d2b3
SY		 2316 vpid_sync_vcpu_all(vmx);
2317
3200f405 2318 ret = 0;
6aa8b732 2319
6aa8b732 2320out:
3200f405 2321 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2322 return ret;
2323}
2324
85f455f7
ED		 2325static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2326{
9c8cba37
AK		 2327 struct vcpu_vmx *vmx = to_vmx(vcpu);
2328
2714d1d3
FEL		 2329 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2330
ad312c7c 2331 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2332 vmx->rmode.irq.pending = true;
2333 vmx->rmode.irq.vector = irq;
5fdbf976 2334 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2335 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2336 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2337 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2338 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2339 return;
2340 }
2341 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2342 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2343}
2344
f08864b4
SY		 2345static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2346{
2347 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2348 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2349}
2350
6aa8b732
AK		 2351static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2352{
ad312c7c
ZX		 2353 int word_index = __ffs(vcpu->arch.irq_summary);
2354 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2355 int irq = word_index * BITS_PER_LONG + bit_index;
2356
ad312c7c
ZX		 2357 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2358 if (!vcpu->arch.irq_pending[word_index])
2359 clear_bit(word_index, &vcpu->arch.irq_summary);
ecfc79c7 2360 kvm_queue_interrupt(vcpu, irq);
6aa8b732
AK		 2361}
2362
c1150d8c
DL		 2363
2364static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2365 struct kvm_run *kvm_run)
6aa8b732 2366{
c1150d8c
DL		 2367 u32 cpu_based_vm_exec_control;
2368
ad312c7c 2369 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 2370 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2371 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2372
ad312c7c 2373 if (vcpu->arch.interrupt_window_open &&
ecfc79c7 2374 vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
6aa8b732 2375 kvm_do_inject_irq(vcpu);
c1150d8c 2376
ecfc79c7
AK		 2377 if (vcpu->arch.interrupt_window_open && vcpu->arch.interrupt.pending)
2378 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2379
c1150d8c 2380 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 2381 if (!vcpu->arch.interrupt_window_open &&
2382 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 2383 /*
2384 * Interrupts blocked. Wait for unblock.
2385 */
c1150d8c
DL		 2386 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2387 else
2388 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2389 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 2390}
2391
cbc94022
IE		 2392static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2393{
2394 int ret;
2395 struct kvm_userspace_memory_region tss_mem = {
2396 .slot = 8,
2397 .guest_phys_addr = addr,
2398 .memory_size = PAGE_SIZE * 3,
2399 .flags = 0,
2400 };
2401
2402 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2403 if (ret)
2404 return ret;
bfc6d222 2405 kvm->arch.tss_addr = addr;
cbc94022
IE		 2406 return 0;
2407}
2408
6aa8b732
AK		 2409static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2410{
2411 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2412
2413 set_debugreg(dbg->bp[0], 0);
2414 set_debugreg(dbg->bp[1], 1);
2415 set_debugreg(dbg->bp[2], 2);
2416 set_debugreg(dbg->bp[3], 3);
2417
2418 if (dbg->singlestep) {
2419 unsigned long flags;
2420
2421 flags = vmcs_readl(GUEST_RFLAGS);
2422 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2423 vmcs_writel(GUEST_RFLAGS, flags);
2424 }
2425}
2426
2427static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2428 int vec, u32 err_code)
2429{
b3f37707
NK		 2430 /*
2431 * Instruction with address size override prefix opcode 0x67
2432 * Cause the #SS fault with 0 error code in VM86 mode.
2433 */
2434 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2435 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2436 return 1;
77ab6db0
JK		 2437 /*
2438 * Forward all other exceptions that are valid in real mode.
2439 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2440 * the required debugging infrastructure rework.
2441 */
2442 switch (vec) {
2443 case DE_VECTOR:
2444 case DB_VECTOR:
2445 case BP_VECTOR:
2446 case OF_VECTOR:
2447 case BR_VECTOR:
2448 case UD_VECTOR:
2449 case DF_VECTOR:
2450 case SS_VECTOR:
2451 case GP_VECTOR:
2452 case MF_VECTOR:
2453 kvm_queue_exception(vcpu, vec);
2454 return 1;
2455 }
6aa8b732
AK		 2456 return 0;
2457}
2458
2459static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2460{
1155f76a 2461 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2462 u32 intr_info, error_code;
2463 unsigned long cr2, rip;
2464 u32 vect_info;
2465 enum emulation_result er;
2466
1155f76a 2467 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2468 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2469
2470 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2471 !is_page_fault(intr_info))
6aa8b732 2472 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2473 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2474
85f455f7 2475 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2476 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2477 set_bit(irq, vcpu->arch.irq_pending);
2478 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2479 }
2480
1b6269db
AK		 2481 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2482 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2483
2484 if (is_no_device(intr_info)) {
5fd86fcf 2485 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2486 return 1;
2487 }
2488
7aa81cc0 2489 if (is_invalid_opcode(intr_info)) {
571008da 2490 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2491 if (er != EMULATE_DONE)
7ee5d940 2492 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2493 return 1;
2494 }
2495
6aa8b732 2496 error_code = 0;
5fdbf976 2497 rip = kvm_rip_read(vcpu);
2e11384c 2498 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2499 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2500 if (is_page_fault(intr_info)) {
1439442c
SY		 2501 /* EPT won't cause page fault directly */
2502 if (vm_need_ept())
2503 BUG();
6aa8b732 2504 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2505 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2506 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2507 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2508 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2509 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2510 }
2511
ad312c7c 2512 if (vcpu->arch.rmode.active &&
6aa8b732 2513 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2514 error_code)) {
ad312c7c
ZX		 2515 if (vcpu->arch.halt_request) {
2516 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2517 return kvm_emulate_halt(vcpu);
2518 }
6aa8b732 2519 return 1;
72d6e5a0 2520 }
6aa8b732 2521
d77c26fc
MD		 2522 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2523 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2524 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2525 return 0;
2526 }
2527 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2528 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2529 kvm_run->ex.error_code = error_code;
2530 return 0;
2531}
2532
2533static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2534 struct kvm_run *kvm_run)
2535{
1165f5fe 2536 ++vcpu->stat.irq_exits;
2714d1d3 2537 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2538 return 1;
2539}
2540
988ad74f
AK		 2541static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2542{
2543 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2544 return 0;
2545}
6aa8b732 2546
6aa8b732
AK		 2547static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2548{
bfdaab09 2549 unsigned long exit_qualification;
039576c0
AK		 2550 int size, down, in, string, rep;
2551 unsigned port;
6aa8b732 2552
1165f5fe 2553 ++vcpu->stat.io_exits;
bfdaab09 2554 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2555 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2556
2557 if (string) {
3427318f
LV		 2558 if (emulate_instruction(vcpu,
2559 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2560 return 0;
2561 return 1;
2562 }
2563
2564 size = (exit_qualification & 7) + 1;
2565 in = (exit_qualification & 8) != 0;
039576c0 2566 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2567 rep = (exit_qualification & 32) != 0;
2568 port = exit_qualification >> 16;
e70669ab 2569
3090dd73 2570 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2571}
2572
102d8325
IM		 2573static void
2574vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2575{
2576 /*
2577 * Patch in the VMCALL instruction:
2578 */
2579 hypercall[0] = 0x0f;
2580 hypercall[1] = 0x01;
2581 hypercall[2] = 0xc1;
102d8325
IM		 2582}
2583
6aa8b732
AK		 2584static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2585{
bfdaab09 2586 unsigned long exit_qualification;
6aa8b732
AK		 2587 int cr;
2588 int reg;
2589
bfdaab09 2590 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2591 cr = exit_qualification & 15;
2592 reg = (exit_qualification >> 8) & 15;
2593 switch ((exit_qualification >> 4) & 3) {
2594 case 0: /* mov to cr */
5fdbf976
MT		 2595 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2596 (u32)kvm_register_read(vcpu, reg),
2597 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2598 handler);
6aa8b732
AK		 2599 switch (cr) {
2600 case 0:
5fdbf976 2601 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2602 skip_emulated_instruction(vcpu);
2603 return 1;
2604 case 3:
5fdbf976 2605 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2606 skip_emulated_instruction(vcpu);
2607 return 1;
2608 case 4:
5fdbf976 2609 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2610 skip_emulated_instruction(vcpu);
2611 return 1;
2612 case 8:
5fdbf976 2613 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2614 skip_emulated_instruction(vcpu);
e5314067
AK		 2615 if (irqchip_in_kernel(vcpu->kvm))
2616 return 1;
253abdee
YS		 2617 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2618 return 0;
6aa8b732
AK		 2619 };
2620 break;
25c4c276 2621 case 2: /* clts */
5fd86fcf 2622 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2623 vcpu->arch.cr0 &= ~X86_CR0_TS;
2624 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2625 vmx_fpu_activate(vcpu);
2714d1d3 2626 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2627 skip_emulated_instruction(vcpu);
2628 return 1;
6aa8b732
AK		 2629 case 1: /*mov from cr*/
2630 switch (cr) {
2631 case 3:
5fdbf976 2632 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2633 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2634 (u32)kvm_register_read(vcpu, reg),
2635 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2636 handler);
6aa8b732
AK		 2637 skip_emulated_instruction(vcpu);
2638 return 1;
2639 case 8:
5fdbf976 2640 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2641 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2642 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2643 skip_emulated_instruction(vcpu);
2644 return 1;
2645 }
2646 break;
2647 case 3: /* lmsw */
2d3ad1f4 2648 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2649
2650 skip_emulated_instruction(vcpu);
2651 return 1;
2652 default:
2653 break;
2654 }
2655 kvm_run->exit_reason = 0;
f0242478 2656 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2657 (int)(exit_qualification >> 4) & 3, cr);
2658 return 0;
2659}
2660
2661static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2662{
bfdaab09 2663 unsigned long exit_qualification;
6aa8b732
AK		 2664 unsigned long val;
2665 int dr, reg;
2666
2667 /*
2668 * FIXME: this code assumes the host is debugging the guest.
2669 * need to deal with guest debugging itself too.
2670 */
bfdaab09 2671 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2672 dr = exit_qualification & 7;
2673 reg = (exit_qualification >> 8) & 15;
6aa8b732
AK		 2674 if (exit_qualification & 16) {
2675 /* mov from dr */
2676 switch (dr) {
2677 case 6:
2678 val = 0xffff0ff0;
2679 break;
2680 case 7:
2681 val = 0x400;
2682 break;
2683 default:
2684 val = 0;
2685 }
5fdbf976 2686 kvm_register_write(vcpu, reg, val);
2714d1d3 2687 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2688 } else {
2689 /* mov to dr */
2690 }
6aa8b732
AK		 2691 skip_emulated_instruction(vcpu);
2692 return 1;
2693}
2694
2695static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2696{
06465c5a
AK		 2697 kvm_emulate_cpuid(vcpu);
2698 return 1;
6aa8b732
AK		 2699}
2700
2701static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2702{
ad312c7c 2703 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2704 u64 data;
2705
2706 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2707 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2708 return 1;
2709 }
2710
2714d1d3
FEL		 2711 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2712 handler);
2713
6aa8b732 2714 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2715 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2716 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2717 skip_emulated_instruction(vcpu);
2718 return 1;
2719}
2720
2721static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2722{
ad312c7c
ZX		 2723 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2724 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2725 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2726
2714d1d3
FEL		 2727 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2728 handler);
2729
6aa8b732 2730 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2731 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2732 return 1;
2733 }
2734
2735 skip_emulated_instruction(vcpu);
2736 return 1;
2737}
2738
6e5d865c
YS		 2739static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2740 struct kvm_run *kvm_run)
2741{
2742 return 1;
2743}
2744
6aa8b732
AK		 2745static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2746 struct kvm_run *kvm_run)
2747{
85f455f7
ED		 2748 u32 cpu_based_vm_exec_control;
2749
2750 /* clear pending irq */
2751 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2752 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2753 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2754
2755 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2756
c1150d8c
DL		 2757 /*
2758 * If the user space waits to inject interrupts, exit as soon as
2759 * possible
2760 */
2761 if (kvm_run->request_interrupt_window &&
ad312c7c 2762 !vcpu->arch.irq_summary) {
c1150d8c 2763 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2764 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2765 return 0;
2766 }
6aa8b732
AK		 2767 return 1;
2768}
2769
2770static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2771{
2772 skip_emulated_instruction(vcpu);
d3bef15f 2773 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2774}
2775
c21415e8
IM		 2776static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2777{
510043da 2778 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2779 kvm_emulate_hypercall(vcpu);
2780 return 1;
c21415e8
IM		 2781}
2782
e5edaa01
ED		 2783static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2784{
2785 skip_emulated_instruction(vcpu);
2786 /* TODO: Add support for VT-d/pass-through device */
2787 return 1;
2788}
2789
f78e0e2e
SY		 2790static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2791{
2792 u64 exit_qualification;
2793 enum emulation_result er;
2794 unsigned long offset;
2795
2796 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2797 offset = exit_qualification & 0xffful;
2798
2799 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2800
2801 if (er != EMULATE_DONE) {
2802 printk(KERN_ERR
2803 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2804 offset);
2805 return -ENOTSUPP;
2806 }
2807 return 1;
2808}
2809
37817f29
IE		 2810static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2811{
2812 unsigned long exit_qualification;
2813 u16 tss_selector;
2814 int reason;
2815
2816 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2817
2818 reason = (u32)exit_qualification >> 30;
2819 tss_selector = exit_qualification;
2820
2821 return kvm_task_switch(vcpu, tss_selector, reason);
2822}
2823
1439442c
SY		 2824static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2825{
2826 u64 exit_qualification;
2827 enum emulation_result er;
2828 gpa_t gpa;
2829 unsigned long hva;
2830 int gla_validity;
2831 int r;
2832
2833 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2834
2835 if (exit_qualification & (1 << 6)) {
2836 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2837 return -ENOTSUPP;
2838 }
2839
2840 gla_validity = (exit_qualification >> 7) & 0x3;
2841 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2842 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2843 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2844 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2845 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2846 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2847 (long unsigned int)exit_qualification);
2848 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2849 kvm_run->hw.hardware_exit_reason = 0;
2850 return -ENOTSUPP;
2851 }
2852
2853 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2854 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2855 if (!kvm_is_error_hva(hva)) {
2856 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2857 if (r < 0) {
2858 printk(KERN_ERR "EPT: Not enough memory!\n");
2859 return -ENOMEM;
2860 }
2861 return 1;
2862 } else {
2863 /* must be MMIO */
2864 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2865
2866 if (er == EMULATE_FAIL) {
2867 printk(KERN_ERR
2868 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2869 er);
2870 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2871 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2872 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2873 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2874 (long unsigned int)exit_qualification);
2875 return -ENOTSUPP;
2876 } else if (er == EMULATE_DO_MMIO)
2877 return 0;
2878 }
2879 return 1;
2880}
2881
f08864b4
SY		 2882static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2883{
2884 u32 cpu_based_vm_exec_control;
2885
2886 /* clear pending NMI */
2887 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2888 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2889 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2890 ++vcpu->stat.nmi_window_exits;
2891
2892 return 1;
2893}
2894
6aa8b732
AK		 2895/*
2896 * The exit handlers return 1 if the exit was handled fully and guest execution
2897 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2898 * to be done to userspace and return 0.
2899 */
2900static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2901 struct kvm_run *kvm_run) = {
2902 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2903 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2904 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 2905 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 2906 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2907 [EXIT_REASON_CR_ACCESS] = handle_cr,
2908 [EXIT_REASON_DR_ACCESS] = handle_dr,
2909 [EXIT_REASON_CPUID] = handle_cpuid,
2910 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2911 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2912 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2913 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2914 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2915 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2916 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2917 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 2918 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 2919 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 2920};
2921
2922static const int kvm_vmx_max_exit_handlers =
50a3485c 2923 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2924
2925/*
2926 * The guest has exited. See if we can fix it or if we need userspace
2927 * assistance.
2928 */
2929static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2930{
6aa8b732 2931 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2932 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2933 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 2934
5fdbf976
MT		 2935 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2936 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 2937
1439442c
SY		 2938 /* Access CR3 don't cause VMExit in paging mode, so we need
2939 * to sync with guest real CR3. */
2940 if (vm_need_ept() && is_paging(vcpu)) {
2941 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2942 ept_load_pdptrs(vcpu);
2943 }
2944
29bd8a78
AK		 2945 if (unlikely(vmx->fail)) {
2946 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2947 kvm_run->fail_entry.hardware_entry_failure_reason
2948 = vmcs_read32(VM_INSTRUCTION_ERROR);
2949 return 0;
2950 }
6aa8b732 2951
d77c26fc 2952 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c
SY		 2953 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2954 exit_reason != EXIT_REASON_EPT_VIOLATION))
6aa8b732 2955 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2956 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2957 if (exit_reason < kvm_vmx_max_exit_handlers
2958 && kvm_vmx_exit_handlers[exit_reason])
2959 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2960 else {
2961 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2962 kvm_run->hw.hardware_exit_reason = exit_reason;
2963 }
2964 return 0;
2965}
2966
6e5d865c
YS		 2967static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2968{
2969 int max_irr, tpr;
2970
2971 if (!vm_need_tpr_shadow(vcpu->kvm))
2972 return;
2973
2974 if (!kvm_lapic_enabled(vcpu) ||
2975 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2976 vmcs_write32(TPR_THRESHOLD, 0);
2977 return;
2978 }
2979
2980 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2981 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2982}
2983
85f455f7
ED		 2984static void enable_irq_window(struct kvm_vcpu *vcpu)
2985{
2986 u32 cpu_based_vm_exec_control;
2987
2988 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2989 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2990 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2991}
2992
f08864b4
SY		 2993static void enable_nmi_window(struct kvm_vcpu *vcpu)
2994{
2995 u32 cpu_based_vm_exec_control;
2996
2997 if (!cpu_has_virtual_nmis())
2998 return;
2999
3000 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3001 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3002 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3003}
3004
3005static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
3006{
3007 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3008 return !(guest_intr & (GUEST_INTR_STATE_NMI |
3009 GUEST_INTR_STATE_MOV_SS |
3010 GUEST_INTR_STATE_STI));
3011}
3012
3013static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
3014{
3015 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
3016 return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
3017 GUEST_INTR_STATE_STI)) &&
3018 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
3019}
3020
3021static void enable_intr_window(struct kvm_vcpu *vcpu)
3022{
3023 if (vcpu->arch.nmi_pending)
3024 enable_nmi_window(vcpu);
3025 else if (kvm_cpu_has_interrupt(vcpu))
3026 enable_irq_window(vcpu);
3027}
3028
cf393f75
AK		 3029static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3030{
3031 u32 exit_intr_info;
668f612f 3032 u32 idt_vectoring_info;
cf393f75
AK		 3033 bool unblock_nmi;
3034 u8 vector;
668f612f
AK		 3035 int type;
3036 bool idtv_info_valid;
35920a35 3037 u32 error;
cf393f75
AK		 3038
3039 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3040 if (cpu_has_virtual_nmis()) {
3041 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3042 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3043 /*
3044 * SDM 3: 25.7.1.2
3045 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3046 * a guest IRET fault.
3047 */
3048 if (unblock_nmi && vector != DF_VECTOR)
3049 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3050 GUEST_INTR_STATE_NMI);
3051 }
668f612f
AK		 3052
3053 idt_vectoring_info = vmx->idt_vectoring_info;
3054 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3055 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3056 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3057 if (vmx->vcpu.arch.nmi_injected) {
3058 /*
3059 * SDM 3: 25.7.1.2
3060 * Clear bit "block by NMI" before VM entry if a NMI delivery
3061 * faulted.
3062 */
3063 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3064 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3065 GUEST_INTR_STATE_NMI);
3066 else
3067 vmx->vcpu.arch.nmi_injected = false;
3068 }
35920a35
AK		 3069 kvm_clear_exception_queue(&vmx->vcpu);
3070 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
3071 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3072 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3073 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3074 } else
3075 kvm_queue_exception(&vmx->vcpu, vector);
3076 vmx->idt_vectoring_info = 0;
3077 }
f7d9238f
AK		 3078 kvm_clear_interrupt_queue(&vmx->vcpu);
3079 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3080 kvm_queue_interrupt(&vmx->vcpu, vector);
3081 vmx->idt_vectoring_info = 0;
3082 }
cf393f75
AK		 3083}
3084
85f455f7
ED		 3085static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3086{
f7d9238f 3087 u32 intr_info_field;
85f455f7 3088
6e5d865c
YS		 3089 update_tpr_threshold(vcpu);
3090
85f455f7 3091 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
f08864b4 3092 if (cpu_has_virtual_nmis()) {
668f612f
AK		 3093 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3094 if (vmx_nmi_enabled(vcpu)) {
3095 vcpu->arch.nmi_pending = false;
3096 vcpu->arch.nmi_injected = true;
3097 } else {
3098 enable_intr_window(vcpu);
3099 return;
3100 }
3101 }
3102 if (vcpu->arch.nmi_injected) {
3103 vmx_inject_nmi(vcpu);
f08864b4
SY		 3104 enable_intr_window(vcpu);
3105 return;
3106 }
f08864b4 3107 }
f7d9238f
AK		 3108 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3109 if (vmx_irq_enabled(vcpu))
3110 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3111 else
3112 enable_irq_window(vcpu);
3113 }
3114 if (vcpu->arch.interrupt.pending) {
3115 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3116 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3117 }
85f455f7
ED		 3118}
3119
9c8cba37
AK		 3120/*
3121 * Failure to inject an interrupt should give us the information
3122 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3123 * when fetching the interrupt redirection bitmap in the real-mode
3124 * tss, this doesn't happen. So we do it ourselves.
3125 */
3126static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3127{
3128 vmx->rmode.irq.pending = 0;
5fdbf976 3129 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3130 return;
5fdbf976 3131 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3132 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3133 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3134 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3135 return;
3136 }
3137 vmx->idt_vectoring_info =
3138 VECTORING_INFO_VALID_MASK
3139 | INTR_TYPE_EXT_INTR
3140 | vmx->rmode.irq.vector;
3141}
3142
c801949d
AK		 3143#ifdef CONFIG_X86_64
3144#define R "r"
3145#define Q "q"
3146#else
3147#define R "e"
3148#define Q "l"
3149#endif
3150
04d2cc77 3151static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 3152{
a2fa3e9f 3153 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 3154 u32 intr_info;
e6adf283 3155
5fdbf976
MT		 3156 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3157 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3158 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3159 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3160
e6adf283
AK		 3161 /*
3162 * Loading guest fpu may have cleared host cr0.ts
3163 */
3164 vmcs_writel(HOST_CR0, read_cr0());
3165
d77c26fc 3166 asm(
6aa8b732 3167 /* Store host registers */
c801949d
AK		 3168 "push %%"R"dx; push %%"R"bp;"
3169 "push %%"R"cx \n\t"
313dbd49
AK		 3170 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3171 "je 1f \n\t"
3172 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3173 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3174 "1: \n\t"
6aa8b732 3175 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3176 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3177 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3178 "mov %c[cr2](%0), %%"R"ax \n\t"
3179 "mov %%"R"ax, %%cr2 \n\t"
3180 "mov %c[rax](%0), %%"R"ax \n\t"
3181 "mov %c[rbx](%0), %%"R"bx \n\t"
3182 "mov %c[rdx](%0), %%"R"dx \n\t"
3183 "mov %c[rsi](%0), %%"R"si \n\t"
3184 "mov %c[rdi](%0), %%"R"di \n\t"
3185 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3186#ifdef CONFIG_X86_64
e08aa78a
AK		 3187 "mov %c[r8](%0), %%r8 \n\t"
3188 "mov %c[r9](%0), %%r9 \n\t"
3189 "mov %c[r10](%0), %%r10 \n\t"
3190 "mov %c[r11](%0), %%r11 \n\t"
3191 "mov %c[r12](%0), %%r12 \n\t"
3192 "mov %c[r13](%0), %%r13 \n\t"
3193 "mov %c[r14](%0), %%r14 \n\t"
3194 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3195#endif
c801949d
AK		 3196 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3197
6aa8b732 3198 /* Enter guest mode */
cd2276a7 3199 "jne .Llaunched \n\t"
4ecac3fd 3200 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3201 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3202 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3203 ".Lkvm_vmx_return: "
6aa8b732 3204 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3205 "xchg %0, (%%"R"sp) \n\t"
3206 "mov %%"R"ax, %c[rax](%0) \n\t"
3207 "mov %%"R"bx, %c[rbx](%0) \n\t"
3208 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3209 "mov %%"R"dx, %c[rdx](%0) \n\t"
3210 "mov %%"R"si, %c[rsi](%0) \n\t"
3211 "mov %%"R"di, %c[rdi](%0) \n\t"
3212 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3213#ifdef CONFIG_X86_64
e08aa78a
AK		 3214 "mov %%r8, %c[r8](%0) \n\t"
3215 "mov %%r9, %c[r9](%0) \n\t"
3216 "mov %%r10, %c[r10](%0) \n\t"
3217 "mov %%r11, %c[r11](%0) \n\t"
3218 "mov %%r12, %c[r12](%0) \n\t"
3219 "mov %%r13, %c[r13](%0) \n\t"
3220 "mov %%r14, %c[r14](%0) \n\t"
3221 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3222#endif
c801949d
AK		 3223 "mov %%cr2, %%"R"ax \n\t"
3224 "mov %%"R"ax, %c[cr2](%0) \n\t"
3225
3226 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3227 "setbe %c[fail](%0) \n\t"
3228 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3229 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3230 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3231 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3232 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3233 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3234 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3235 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3236 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3237 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3238 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3239#ifdef CONFIG_X86_64
ad312c7c
ZX		 3240 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3241 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3242 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3243 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3244 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3245 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3246 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3247 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3248#endif
ad312c7c 3249 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3250 : "cc", "memory"
c801949d 3251 , R"bx", R"di", R"si"
c2036300 3252#ifdef CONFIG_X86_64
c2036300
LV		 3253 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3254#endif
3255 );
6aa8b732 3256
5fdbf976
MT		 3257 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3258 vcpu->arch.regs_dirty = 0;
3259
1155f76a 3260 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3261 if (vmx->rmode.irq.pending)
3262 fixup_rmode_irq(vmx);
1155f76a 3263
ad312c7c 3264 vcpu->arch.interrupt_window_open =
f08864b4
SY		 3265 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3266 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
6aa8b732 3267
d77c26fc 3268 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3269 vmx->launched = 1;
1b6269db
AK		 3270
3271 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3272
3273 /* We need to handle NMIs before interrupts are enabled */
f08864b4
SY		 3274 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3275 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3276 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3277 asm("int $2");
2714d1d3 3278 }
cf393f75
AK		 3279
3280 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3281}
3282
c801949d
AK		 3283#undef R
3284#undef Q
3285
6aa8b732
AK		 3286static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3287{
a2fa3e9f
GH		 3288 struct vcpu_vmx *vmx = to_vmx(vcpu);
3289
3290 if (vmx->vmcs) {
543e4243 3291 vcpu_clear(vmx);
a2fa3e9f
GH		 3292 free_vmcs(vmx->vmcs);
3293 vmx->vmcs = NULL;
6aa8b732
AK		 3294 }
3295}
3296
3297static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3298{
fb3f0f51
RR		 3299 struct vcpu_vmx *vmx = to_vmx(vcpu);
3300
2384d2b3
SY		 3301 spin_lock(&vmx_vpid_lock);
3302 if (vmx->vpid != 0)
3303 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3304 spin_unlock(&vmx_vpid_lock);
6aa8b732 3305 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3306 kfree(vmx->host_msrs);
3307 kfree(vmx->guest_msrs);
3308 kvm_vcpu_uninit(vcpu);
a4770347 3309 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3310}
3311
fb3f0f51 3312static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3313{
fb3f0f51 3314 int err;
c16f862d 3315 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3316 int cpu;
6aa8b732 3317
a2fa3e9f 3318 if (!vmx)
fb3f0f51
RR		 3319 return ERR_PTR(-ENOMEM);
3320
2384d2b3
SY		 3321 allocate_vpid(vmx);
3322
fb3f0f51
RR		 3323 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3324 if (err)
3325 goto free_vcpu;
965b58a5 3326
a2fa3e9f 3327 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3328 if (!vmx->guest_msrs) {
3329 err = -ENOMEM;
3330 goto uninit_vcpu;
3331 }
965b58a5 3332
a2fa3e9f
GH		 3333 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3334 if (!vmx->host_msrs)
fb3f0f51 3335 goto free_guest_msrs;
965b58a5 3336
a2fa3e9f
GH		 3337 vmx->vmcs = alloc_vmcs();
3338 if (!vmx->vmcs)
fb3f0f51 3339 goto free_msrs;
a2fa3e9f
GH		 3340
3341 vmcs_clear(vmx->vmcs);
3342
15ad7146
AK		 3343 cpu = get_cpu();
3344 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3345 err = vmx_vcpu_setup(vmx);
fb3f0f51 3346 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3347 put_cpu();
fb3f0f51
RR		 3348 if (err)
3349 goto free_vmcs;
5e4a0b3c
MT		 3350 if (vm_need_virtualize_apic_accesses(kvm))
3351 if (alloc_apic_access_page(kvm) != 0)
3352 goto free_vmcs;
fb3f0f51 3353
b7ebfb05
SY		 3354 if (vm_need_ept())
3355 if (alloc_identity_pagetable(kvm) != 0)
3356 goto free_vmcs;
3357
fb3f0f51
RR		 3358 return &vmx->vcpu;
3359
3360free_vmcs:
3361 free_vmcs(vmx->vmcs);
3362free_msrs:
3363 kfree(vmx->host_msrs);
3364free_guest_msrs:
3365 kfree(vmx->guest_msrs);
3366uninit_vcpu:
3367 kvm_vcpu_uninit(&vmx->vcpu);
3368free_vcpu:
a4770347 3369 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3370 return ERR_PTR(err);
6aa8b732
AK		 3371}
3372
002c7f7c
YS		 3373static void __init vmx_check_processor_compat(void *rtn)
3374{
3375 struct vmcs_config vmcs_conf;
3376
3377 *(int *)rtn = 0;
3378 if (setup_vmcs_config(&vmcs_conf) < 0)
3379 *(int *)rtn = -EIO;
3380 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3381 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3382 smp_processor_id());
3383 *(int *)rtn = -EIO;
3384 }
3385}
3386
67253af5
SY		 3387static int get_ept_level(void)
3388{
3389 return VMX_EPT_DEFAULT_GAW + 1;
3390}
3391
cbdd1bea 3392static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3393 .cpu_has_kvm_support = cpu_has_kvm_support,
3394 .disabled_by_bios = vmx_disabled_by_bios,
3395 .hardware_setup = hardware_setup,
3396 .hardware_unsetup = hardware_unsetup,
002c7f7c 3397 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3398 .hardware_enable = hardware_enable,
3399 .hardware_disable = hardware_disable,
774ead3a 3400 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3401
3402 .vcpu_create = vmx_create_vcpu,
3403 .vcpu_free = vmx_free_vcpu,
04d2cc77 3404 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3405
04d2cc77 3406 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3407 .vcpu_load = vmx_vcpu_load,
3408 .vcpu_put = vmx_vcpu_put,
3409
3410 .set_guest_debug = set_guest_debug,
04d2cc77 3411 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3412 .get_msr = vmx_get_msr,
3413 .set_msr = vmx_set_msr,
3414 .get_segment_base = vmx_get_segment_base,
3415 .get_segment = vmx_get_segment,
3416 .set_segment = vmx_set_segment,
2e4d2653 3417 .get_cpl = vmx_get_cpl,
6aa8b732 3418 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3419 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3420 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3421 .set_cr3 = vmx_set_cr3,
3422 .set_cr4 = vmx_set_cr4,
6aa8b732 3423 .set_efer = vmx_set_efer,
6aa8b732
AK		 3424 .get_idt = vmx_get_idt,
3425 .set_idt = vmx_set_idt,
3426 .get_gdt = vmx_get_gdt,
3427 .set_gdt = vmx_set_gdt,
5fdbf976 3428 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3429 .get_rflags = vmx_get_rflags,
3430 .set_rflags = vmx_set_rflags,
3431
3432 .tlb_flush = vmx_flush_tlb,
6aa8b732 3433
6aa8b732 3434 .run = vmx_vcpu_run,
04d2cc77 3435 .handle_exit = kvm_handle_exit,
6aa8b732 3436 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3437 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3438 .get_irq = vmx_get_irq,
3439 .set_irq = vmx_inject_irq,
298101da
AK		 3440 .queue_exception = vmx_queue_exception,
3441 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3442 .inject_pending_irq = vmx_intr_assist,
3443 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3444
3445 .set_tss_addr = vmx_set_tss_addr,
67253af5 3446 .get_tdp_level = get_ept_level,
6aa8b732
AK		 3447};
3448
3449static int __init vmx_init(void)
3450{
25c5f225 3451 void *va;
fdef3ad1
HQ		 3452 int r;
3453
3454 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3455 if (!vmx_io_bitmap_a)
3456 return -ENOMEM;
3457
3458 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3459 if (!vmx_io_bitmap_b) {
3460 r = -ENOMEM;
3461 goto out;
3462 }
3463
25c5f225
SY		 3464 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3465 if (!vmx_msr_bitmap) {
3466 r = -ENOMEM;
3467 goto out1;
3468 }
3469
fdef3ad1
HQ		 3470 /*
3471 * Allow direct access to the PC debug port (it is often used for I/O
3472 * delays, but the vmexits simply slow things down).
3473 */
25c5f225
SY		 3474 va = kmap(vmx_io_bitmap_a);
3475 memset(va, 0xff, PAGE_SIZE);
3476 clear_bit(0x80, va);
cd0536d7 3477 kunmap(vmx_io_bitmap_a);
fdef3ad1 3478
25c5f225
SY		 3479 va = kmap(vmx_io_bitmap_b);
3480 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3481 kunmap(vmx_io_bitmap_b);
fdef3ad1 3482
25c5f225
SY		 3483 va = kmap(vmx_msr_bitmap);
3484 memset(va, 0xff, PAGE_SIZE);
3485 kunmap(vmx_msr_bitmap);
3486
2384d2b3
SY		 3487 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3488
cb498ea2 3489 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3490 if (r)
25c5f225
SY		 3491 goto out2;
3492
3493 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3494 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3495 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3496 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3497 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3498
5fdbcb9d 3499 if (vm_need_ept()) {
1439442c 3500 bypass_guest_pf = 0;
5fdbcb9d
SY		 3501 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3502 VMX_EPT_WRITABLE_MASK |
3503 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
534e38b4 3504 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5fdbcb9d
SY		 3505 VMX_EPT_EXECUTABLE_MASK);
3506 kvm_enable_tdp();
3507 } else
3508 kvm_disable_tdp();
1439442c 3509
c7addb90
AK		 3510 if (bypass_guest_pf)
3511 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3512
1439442c
SY		 3513 ept_sync_global();
3514
fdef3ad1
HQ		 3515 return 0;
3516
25c5f225
SY		 3517out2:
3518 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3519out1:
3520 __free_page(vmx_io_bitmap_b);
3521out:
3522 __free_page(vmx_io_bitmap_a);
3523 return r;
6aa8b732
AK		 3524}
3525
3526static void __exit vmx_exit(void)
3527{
25c5f225 3528 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3529 __free_page(vmx_io_bitmap_b);
3530 __free_page(vmx_io_bitmap_a);
3531
cb498ea2 3532 kvm_exit();
6aa8b732
AK		 3533}
3534
3535module_init(vmx_init)
3536module_exit(vmx_exit)
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