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KVM: Fix potential guest state leak into host
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
6aa8b732 20#include <linux/module.h>
9d8f549d 21#include <linux/kernel.h>
6aa8b732
AK		 22#include <linux/mm.h>
23#include <linux/highmem.h>
07031e14 24#include <linux/profile.h>
e8edc6e0 25#include <linux/sched.h>
6aa8b732 26#include <asm/io.h>
3b3be0d1 27#include <asm/desc.h>
6aa8b732
AK		 28
29#include "segment_descriptor.h"
30
6aa8b732
AK		 31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
fdef3ad1
HQ		 37static struct page *vmx_io_bitmap_a;
38static struct page *vmx_io_bitmap_b;
39
05b3e0c2 40#ifdef CONFIG_X86_64
6aa8b732
AK		 41#define HOST_IS_64 1
42#else
43#define HOST_IS_64 0
44#endif
45
46static struct vmcs_descriptor {
47 int size;
48 int order;
49 u32 revision_id;
50} vmcs_descriptor;
51
52#define VMX_SEGMENT_FIELD(seg) \
53 [VCPU_SREG_##seg] = { \
54 .selector = GUEST_##seg##_SELECTOR, \
55 .base = GUEST_##seg##_BASE, \
56 .limit = GUEST_##seg##_LIMIT, \
57 .ar_bytes = GUEST_##seg##_AR_BYTES, \
58 }
59
60static struct kvm_vmx_segment_field {
61 unsigned selector;
62 unsigned base;
63 unsigned limit;
64 unsigned ar_bytes;
65} kvm_vmx_segment_fields[] = {
66 VMX_SEGMENT_FIELD(CS),
67 VMX_SEGMENT_FIELD(DS),
68 VMX_SEGMENT_FIELD(ES),
69 VMX_SEGMENT_FIELD(FS),
70 VMX_SEGMENT_FIELD(GS),
71 VMX_SEGMENT_FIELD(SS),
72 VMX_SEGMENT_FIELD(TR),
73 VMX_SEGMENT_FIELD(LDTR),
74};
75
4d56c8a7
AK		 76/*
77 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
78 * away by decrementing the array size.
79 */
6aa8b732 80static const u32 vmx_msr_index[] = {
05b3e0c2 81#ifdef CONFIG_X86_64
6aa8b732
AK		 82 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
83#endif
84 MSR_EFER, MSR_K6_STAR,
85};
9d8f549d 86#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 87
2345df8c
AK		 88#ifdef CONFIG_X86_64
89static unsigned msr_offset_kernel_gs_base;
e38aea3e 90#define NR_64BIT_MSRS 4
35cc7f97
AK		 91/*
92 * avoid save/load MSR_SYSCALL_MASK and MSR_LSTAR by std vt
93 * mechanism (cpu bug AA24)
94 */
95#define NR_BAD_MSRS 2
e38aea3e
AK		 96#else
97#define NR_64BIT_MSRS 0
35cc7f97 98#define NR_BAD_MSRS 0
2345df8c
AK		 99#endif
100
6aa8b732
AK		 101static inline int is_page_fault(u32 intr_info)
102{
103 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
104 INTR_INFO_VALID_MASK)) ==
105 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
106}
107
2ab455cc
AL		 108static inline int is_no_device(u32 intr_info)
109{
110 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
111 INTR_INFO_VALID_MASK)) ==
112 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
113}
114
6aa8b732
AK		 115static inline int is_external_interrupt(u32 intr_info)
116{
117 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
118 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
119}
120
7725f0ba
AK		 121static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
122{
123 int i;
124
125 for (i = 0; i < vcpu->nmsrs; ++i)
126 if (vcpu->guest_msrs[i].index == msr)
127 return &vcpu->guest_msrs[i];
8b6d44c7 128 return NULL;
7725f0ba
AK		 129}
130
6aa8b732
AK		 131static void vmcs_clear(struct vmcs *vmcs)
132{
133 u64 phys_addr = __pa(vmcs);
134 u8 error;
135
136 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
137 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
138 : "cc", "memory");
139 if (error)
140 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
141 vmcs, phys_addr);
142}
143
144static void __vcpu_clear(void *arg)
145{
146 struct kvm_vcpu *vcpu = arg;
d3b2c338 147 int cpu = raw_smp_processor_id();
6aa8b732
AK		 148
149 if (vcpu->cpu == cpu)
150 vmcs_clear(vcpu->vmcs);
151 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
152 per_cpu(current_vmcs, cpu) = NULL;
153}
154
8d0be2b3
AK		 155static void vcpu_clear(struct kvm_vcpu *vcpu)
156{
157 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
158 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
159 else
160 __vcpu_clear(vcpu);
161 vcpu->launched = 0;
162}
163
6aa8b732
AK		 164static unsigned long vmcs_readl(unsigned long field)
165{
166 unsigned long value;
167
168 asm volatile (ASM_VMX_VMREAD_RDX_RAX
169 : "=a"(value) : "d"(field) : "cc");
170 return value;
171}
172
173static u16 vmcs_read16(unsigned long field)
174{
175 return vmcs_readl(field);
176}
177
178static u32 vmcs_read32(unsigned long field)
179{
180 return vmcs_readl(field);
181}
182
183static u64 vmcs_read64(unsigned long field)
184{
05b3e0c2 185#ifdef CONFIG_X86_64
6aa8b732
AK		 186 return vmcs_readl(field);
187#else
188 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
189#endif
190}
191
e52de1b8
AK		 192static noinline void vmwrite_error(unsigned long field, unsigned long value)
193{
194 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
195 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
196 dump_stack();
197}
198
6aa8b732
AK		 199static void vmcs_writel(unsigned long field, unsigned long value)
200{
201 u8 error;
202
203 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
204 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 205 if (unlikely(error))
206 vmwrite_error(field, value);
6aa8b732
AK		 207}
208
209static void vmcs_write16(unsigned long field, u16 value)
210{
211 vmcs_writel(field, value);
212}
213
214static void vmcs_write32(unsigned long field, u32 value)
215{
216 vmcs_writel(field, value);
217}
218
219static void vmcs_write64(unsigned long field, u64 value)
220{
05b3e0c2 221#ifdef CONFIG_X86_64
6aa8b732
AK		 222 vmcs_writel(field, value);
223#else
224 vmcs_writel(field, value);
225 asm volatile ("");
226 vmcs_writel(field+1, value >> 32);
227#endif
228}
229
2ab455cc
AL		 230static void vmcs_clear_bits(unsigned long field, u32 mask)
231{
232 vmcs_writel(field, vmcs_readl(field) & ~mask);
233}
234
235static void vmcs_set_bits(unsigned long field, u32 mask)
236{
237 vmcs_writel(field, vmcs_readl(field) | mask);
238}
239
33ed6329
AK		 240static void reload_tss(void)
241{
242#ifndef CONFIG_X86_64
243
244 /*
245 * VT restores TR but not its size. Useless.
246 */
247 struct descriptor_table gdt;
248 struct segment_descriptor *descs;
249
250 get_gdt(&gdt);
251 descs = (void *)gdt.base;
252 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
253 load_TR_desc();
254#endif
255}
256
257static void vmx_save_host_state(struct kvm_vcpu *vcpu)
258{
259 struct vmx_host_state *hs = &vcpu->vmx_host_state;
260
261 if (hs->loaded)
262 return;
263
264 hs->loaded = 1;
265 /*
266 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
267 * allow segment selectors with cpl > 0 or ti == 1.
268 */
269 hs->ldt_sel = read_ldt();
270 hs->fs_gs_ldt_reload_needed = hs->ldt_sel;
271 hs->fs_sel = read_fs();
272 if (!(hs->fs_sel & 7))
273 vmcs_write16(HOST_FS_SELECTOR, hs->fs_sel);
274 else {
275 vmcs_write16(HOST_FS_SELECTOR, 0);
276 hs->fs_gs_ldt_reload_needed = 1;
277 }
278 hs->gs_sel = read_gs();
279 if (!(hs->gs_sel & 7))
280 vmcs_write16(HOST_GS_SELECTOR, hs->gs_sel);
281 else {
282 vmcs_write16(HOST_GS_SELECTOR, 0);
283 hs->fs_gs_ldt_reload_needed = 1;
284 }
285
286#ifdef CONFIG_X86_64
287 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
288 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
289#else
290 vmcs_writel(HOST_FS_BASE, segment_base(hs->fs_sel));
291 vmcs_writel(HOST_GS_BASE, segment_base(hs->gs_sel));
292#endif
293}
294
295static void vmx_load_host_state(struct kvm_vcpu *vcpu)
296{
297 struct vmx_host_state *hs = &vcpu->vmx_host_state;
298
299 if (!hs->loaded)
300 return;
301
302 hs->loaded = 0;
303 if (hs->fs_gs_ldt_reload_needed) {
304 load_ldt(hs->ldt_sel);
305 load_fs(hs->fs_sel);
306 /*
307 * If we have to reload gs, we must take care to
308 * preserve our gs base.
309 */
310 local_irq_disable();
311 load_gs(hs->gs_sel);
312#ifdef CONFIG_X86_64
313 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
314#endif
315 local_irq_enable();
316
317 reload_tss();
318 }
319#ifdef CONFIG_X86_64
320 if (is_long_mode(vcpu)) {
321 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
322 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
323 }
324#endif
325}
326
6aa8b732
AK		 327/*
328 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
329 * vcpu mutex is already taken.
330 */
bccf2150 331static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732
AK		 332{
333 u64 phys_addr = __pa(vcpu->vmcs);
334 int cpu;
335
336 cpu = get_cpu();
337
8d0be2b3
AK		 338 if (vcpu->cpu != cpu)
339 vcpu_clear(vcpu);
6aa8b732
AK		 340
341 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
342 u8 error;
343
344 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
345 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
346 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
347 : "cc");
348 if (error)
349 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
350 vcpu->vmcs, phys_addr);
351 }
352
353 if (vcpu->cpu != cpu) {
354 struct descriptor_table dt;
355 unsigned long sysenter_esp;
356
357 vcpu->cpu = cpu;
358 /*
359 * Linux uses per-cpu TSS and GDT, so set these when switching
360 * processors.
361 */
362 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
363 get_gdt(&dt);
364 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
365
366 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
367 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
368 }
6aa8b732
AK		 369}
370
371static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
372{
33ed6329 373 vmx_load_host_state(vcpu);
7702fd1f 374 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 375 put_cpu();
376}
377
774c47f1
AK		 378static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
379{
380 vcpu_clear(vcpu);
381}
382
6aa8b732
AK		 383static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
384{
385 return vmcs_readl(GUEST_RFLAGS);
386}
387
388static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
389{
390 vmcs_writel(GUEST_RFLAGS, rflags);
391}
392
393static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
394{
395 unsigned long rip;
396 u32 interruptibility;
397
398 rip = vmcs_readl(GUEST_RIP);
399 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
400 vmcs_writel(GUEST_RIP, rip);
401
402 /*
403 * We emulated an instruction, so temporary interrupt blocking
404 * should be removed, if set.
405 */
406 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
407 if (interruptibility & 3)
408 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
409 interruptibility & ~3);
c1150d8c 410 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 411}
412
413static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
414{
415 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
416 vmcs_readl(GUEST_RIP));
417 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
418 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
419 GP_VECTOR |
420 INTR_TYPE_EXCEPTION |
421 INTR_INFO_DELIEVER_CODE_MASK |
422 INTR_INFO_VALID_MASK);
423}
424
e38aea3e
AK		 425/*
426 * Set up the vmcs to automatically save and restore system
427 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
428 * mode, as fiddling with msrs is very expensive.
429 */
430static void setup_msrs(struct kvm_vcpu *vcpu)
431{
432 int nr_skip, nr_good_msrs;
433
434 if (is_long_mode(vcpu))
435 nr_skip = NR_BAD_MSRS;
436 else
437 nr_skip = NR_64BIT_MSRS;
438 nr_good_msrs = vcpu->nmsrs - nr_skip;
439
4d56c8a7
AK		 440 /*
441 * MSR_K6_STAR is only needed on long mode guests, and only
442 * if efer.sce is enabled.
443 */
444 if (find_msr_entry(vcpu, MSR_K6_STAR)) {
445 --nr_good_msrs;
446#ifdef CONFIG_X86_64
447 if (is_long_mode(vcpu) && (vcpu->shadow_efer & EFER_SCE))
448 ++nr_good_msrs;
449#endif
450 }
451
e38aea3e
AK		 452 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
453 virt_to_phys(vcpu->guest_msrs + nr_skip));
454 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
455 virt_to_phys(vcpu->guest_msrs + nr_skip));
456 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
457 virt_to_phys(vcpu->host_msrs + nr_skip));
458 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
459 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
460 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
461}
462
6aa8b732
AK		 463/*
464 * reads and returns guest's timestamp counter "register"
465 * guest_tsc = host_tsc + tsc_offset -- 21.3
466 */
467static u64 guest_read_tsc(void)
468{
469 u64 host_tsc, tsc_offset;
470
471 rdtscll(host_tsc);
472 tsc_offset = vmcs_read64(TSC_OFFSET);
473 return host_tsc + tsc_offset;
474}
475
476/*
477 * writes 'guest_tsc' into guest's timestamp counter "register"
478 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
479 */
480static void guest_write_tsc(u64 guest_tsc)
481{
482 u64 host_tsc;
483
484 rdtscll(host_tsc);
485 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
486}
487
6aa8b732
AK		 488/*
489 * Reads an msr value (of 'msr_index') into 'pdata'.
490 * Returns 0 on success, non-0 otherwise.
491 * Assumes vcpu_load() was already called.
492 */
493static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
494{
495 u64 data;
496 struct vmx_msr_entry *msr;
497
498 if (!pdata) {
499 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
500 return -EINVAL;
501 }
502
503 switch (msr_index) {
05b3e0c2 504#ifdef CONFIG_X86_64
6aa8b732
AK		 505 case MSR_FS_BASE:
506 data = vmcs_readl(GUEST_FS_BASE);
507 break;
508 case MSR_GS_BASE:
509 data = vmcs_readl(GUEST_GS_BASE);
510 break;
511 case MSR_EFER:
3bab1f5d 512 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 513#endif
514 case MSR_IA32_TIME_STAMP_COUNTER:
515 data = guest_read_tsc();
516 break;
517 case MSR_IA32_SYSENTER_CS:
518 data = vmcs_read32(GUEST_SYSENTER_CS);
519 break;
520 case MSR_IA32_SYSENTER_EIP:
f5b42c33 521 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 522 break;
523 case MSR_IA32_SYSENTER_ESP:
f5b42c33 524 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 525 break;
6aa8b732
AK		 526 default:
527 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 528 if (msr) {
529 data = msr->data;
530 break;
6aa8b732 531 }
3bab1f5d 532 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 533 }
534
535 *pdata = data;
536 return 0;
537}
538
539/*
540 * Writes msr value into into the appropriate "register".
541 * Returns 0 on success, non-0 otherwise.
542 * Assumes vcpu_load() was already called.
543 */
544static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
545{
546 struct vmx_msr_entry *msr;
547 switch (msr_index) {
05b3e0c2 548#ifdef CONFIG_X86_64
3bab1f5d
AK		 549 case MSR_EFER:
550 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 551 case MSR_FS_BASE:
552 vmcs_writel(GUEST_FS_BASE, data);
553 break;
554 case MSR_GS_BASE:
555 vmcs_writel(GUEST_GS_BASE, data);
556 break;
e6adf283
AK		 557 case MSR_LSTAR:
558 case MSR_SYSCALL_MASK:
559 msr = find_msr_entry(vcpu, msr_index);
560 if (msr)
561 msr->data = data;
562 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
563 break;
6aa8b732
AK		 564#endif
565 case MSR_IA32_SYSENTER_CS:
566 vmcs_write32(GUEST_SYSENTER_CS, data);
567 break;
568 case MSR_IA32_SYSENTER_EIP:
f5b42c33 569 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 570 break;
571 case MSR_IA32_SYSENTER_ESP:
f5b42c33 572 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 573 break;
d27d4aca 574 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 575 guest_write_tsc(data);
576 break;
6aa8b732
AK		 577 default:
578 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 579 if (msr) {
580 msr->data = data;
581 break;
6aa8b732 582 }
3bab1f5d 583 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 584 msr->data = data;
585 break;
586 }
587
588 return 0;
589}
590
591/*
592 * Sync the rsp and rip registers into the vcpu structure. This allows
593 * registers to be accessed by indexing vcpu->regs.
594 */
595static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
596{
597 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
598 vcpu->rip = vmcs_readl(GUEST_RIP);
599}
600
601/*
602 * Syncs rsp and rip back into the vmcs. Should be called after possible
603 * modification.
604 */
605static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
606{
607 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
608 vmcs_writel(GUEST_RIP, vcpu->rip);
609}
610
611static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
612{
613 unsigned long dr7 = 0x400;
614 u32 exception_bitmap;
615 int old_singlestep;
616
617 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
618 old_singlestep = vcpu->guest_debug.singlestep;
619
620 vcpu->guest_debug.enabled = dbg->enabled;
621 if (vcpu->guest_debug.enabled) {
622 int i;
623
624 dr7 |= 0x200; /* exact */
625 for (i = 0; i < 4; ++i) {
626 if (!dbg->breakpoints[i].enabled)
627 continue;
628 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
629 dr7 |= 2 << (i*2); /* global enable */
630 dr7 |= 0 << (i*4+16); /* execution breakpoint */
631 }
632
633 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
634
635 vcpu->guest_debug.singlestep = dbg->singlestep;
636 } else {
637 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
638 vcpu->guest_debug.singlestep = 0;
639 }
640
641 if (old_singlestep && !vcpu->guest_debug.singlestep) {
642 unsigned long flags;
643
644 flags = vmcs_readl(GUEST_RFLAGS);
645 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
646 vmcs_writel(GUEST_RFLAGS, flags);
647 }
648
649 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
650 vmcs_writel(GUEST_DR7, dr7);
651
652 return 0;
653}
654
655static __init int cpu_has_kvm_support(void)
656{
657 unsigned long ecx = cpuid_ecx(1);
658 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
659}
660
661static __init int vmx_disabled_by_bios(void)
662{
663 u64 msr;
664
665 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
666 return (msr & 5) == 1; /* locked but not enabled */
667}
668
774c47f1 669static void hardware_enable(void *garbage)
6aa8b732
AK		 670{
671 int cpu = raw_smp_processor_id();
672 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
673 u64 old;
674
675 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 676 if ((old & 5) != 5)
6aa8b732
AK		 677 /* enable and lock */
678 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
679 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
680 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
681 : "memory", "cc");
682}
683
684static void hardware_disable(void *garbage)
685{
686 asm volatile (ASM_VMX_VMXOFF : : : "cc");
687}
688
689static __init void setup_vmcs_descriptor(void)
690{
691 u32 vmx_msr_low, vmx_msr_high;
692
c68876fd 693 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 694 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
695 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
696 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 697}
6aa8b732
AK		 698
699static struct vmcs *alloc_vmcs_cpu(int cpu)
700{
701 int node = cpu_to_node(cpu);
702 struct page *pages;
703 struct vmcs *vmcs;
704
705 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
706 if (!pages)
707 return NULL;
708 vmcs = page_address(pages);
709 memset(vmcs, 0, vmcs_descriptor.size);
710 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
711 return vmcs;
712}
713
714static struct vmcs *alloc_vmcs(void)
715{
d3b2c338 716 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 717}
718
719static void free_vmcs(struct vmcs *vmcs)
720{
721 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
722}
723
39959588 724static void free_kvm_area(void)
6aa8b732
AK		 725{
726 int cpu;
727
728 for_each_online_cpu(cpu)
729 free_vmcs(per_cpu(vmxarea, cpu));
730}
731
732extern struct vmcs *alloc_vmcs_cpu(int cpu);
733
734static __init int alloc_kvm_area(void)
735{
736 int cpu;
737
738 for_each_online_cpu(cpu) {
739 struct vmcs *vmcs;
740
741 vmcs = alloc_vmcs_cpu(cpu);
742 if (!vmcs) {
743 free_kvm_area();
744 return -ENOMEM;
745 }
746
747 per_cpu(vmxarea, cpu) = vmcs;
748 }
749 return 0;
750}
751
752static __init int hardware_setup(void)
753{
754 setup_vmcs_descriptor();
755 return alloc_kvm_area();
756}
757
758static __exit void hardware_unsetup(void)
759{
760 free_kvm_area();
761}
762
763static void update_exception_bitmap(struct kvm_vcpu *vcpu)
764{
765 if (vcpu->rmode.active)
766 vmcs_write32(EXCEPTION_BITMAP, ~0);
767 else
768 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
769}
770
771static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
772{
773 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
774
6af11b9e 775 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 776 vmcs_write16(sf->selector, save->selector);
777 vmcs_writel(sf->base, save->base);
778 vmcs_write32(sf->limit, save->limit);
779 vmcs_write32(sf->ar_bytes, save->ar);
780 } else {
781 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
782 << AR_DPL_SHIFT;
783 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
784 }
785}
786
787static void enter_pmode(struct kvm_vcpu *vcpu)
788{
789 unsigned long flags;
790
791 vcpu->rmode.active = 0;
792
793 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
794 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
795 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
796
797 flags = vmcs_readl(GUEST_RFLAGS);
798 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
799 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
800 vmcs_writel(GUEST_RFLAGS, flags);
801
802 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
803 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
804
805 update_exception_bitmap(vcpu);
806
807 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
808 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
809 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
810 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
811
812 vmcs_write16(GUEST_SS_SELECTOR, 0);
813 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
814
815 vmcs_write16(GUEST_CS_SELECTOR,
816 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
817 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
818}
819
820static int rmode_tss_base(struct kvm* kvm)
821{
822 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
823 return base_gfn << PAGE_SHIFT;
824}
825
826static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
827{
828 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
829
830 save->selector = vmcs_read16(sf->selector);
831 save->base = vmcs_readl(sf->base);
832 save->limit = vmcs_read32(sf->limit);
833 save->ar = vmcs_read32(sf->ar_bytes);
834 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
835 vmcs_write32(sf->limit, 0xffff);
836 vmcs_write32(sf->ar_bytes, 0xf3);
837}
838
839static void enter_rmode(struct kvm_vcpu *vcpu)
840{
841 unsigned long flags;
842
843 vcpu->rmode.active = 1;
844
845 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
846 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
847
848 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
849 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
850
851 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
852 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
853
854 flags = vmcs_readl(GUEST_RFLAGS);
855 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
856
857 flags |= IOPL_MASK | X86_EFLAGS_VM;
858
859 vmcs_writel(GUEST_RFLAGS, flags);
860 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
861 update_exception_bitmap(vcpu);
862
863 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
864 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
865 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
866
867 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 868 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 869 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
870 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 871 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
872
873 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
874 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
875 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
876 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
877}
878
05b3e0c2 879#ifdef CONFIG_X86_64
6aa8b732
AK		 880
881static void enter_lmode(struct kvm_vcpu *vcpu)
882{
883 u32 guest_tr_ar;
884
885 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
886 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
887 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
888 __FUNCTION__);
889 vmcs_write32(GUEST_TR_AR_BYTES,
890 (guest_tr_ar & ~AR_TYPE_MASK)
891 | AR_TYPE_BUSY_64_TSS);
892 }
893
894 vcpu->shadow_efer |= EFER_LMA;
895
896 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
897 vmcs_write32(VM_ENTRY_CONTROLS,
898 vmcs_read32(VM_ENTRY_CONTROLS)
899 | VM_ENTRY_CONTROLS_IA32E_MASK);
900}
901
902static void exit_lmode(struct kvm_vcpu *vcpu)
903{
904 vcpu->shadow_efer &= ~EFER_LMA;
905
906 vmcs_write32(VM_ENTRY_CONTROLS,
907 vmcs_read32(VM_ENTRY_CONTROLS)
908 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
909}
910
911#endif
912
25c4c276 913static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 914{
399badf3
AK		 915 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
916 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
917}
918
6aa8b732
AK		 919static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
920{
921 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
922 enter_pmode(vcpu);
923
924 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
925 enter_rmode(vcpu);
926
05b3e0c2 927#ifdef CONFIG_X86_64
6aa8b732
AK		 928 if (vcpu->shadow_efer & EFER_LME) {
929 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
930 enter_lmode(vcpu);
931 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
932 exit_lmode(vcpu);
933 }
934#endif
935
2ab455cc
AL		 936 if (!(cr0 & CR0_TS_MASK)) {
937 vcpu->fpu_active = 1;
938 vmcs_clear_bits(EXCEPTION_BITMAP, CR0_TS_MASK);
939 }
940
6aa8b732
AK		 941 vmcs_writel(CR0_READ_SHADOW, cr0);
942 vmcs_writel(GUEST_CR0,
943 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
944 vcpu->cr0 = cr0;
945}
946
6aa8b732
AK		 947static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
948{
949 vmcs_writel(GUEST_CR3, cr3);
2ab455cc
AL		 950
951 if (!(vcpu->cr0 & CR0_TS_MASK)) {
952 vcpu->fpu_active = 0;
953 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
954 vmcs_set_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
955 }
6aa8b732
AK		 956}
957
958static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
959{
960 vmcs_writel(CR4_READ_SHADOW, cr4);
961 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
962 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
963 vcpu->cr4 = cr4;
964}
965
05b3e0c2 966#ifdef CONFIG_X86_64
6aa8b732
AK		 967
968static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
969{
970 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
971
972 vcpu->shadow_efer = efer;
973 if (efer & EFER_LMA) {
974 vmcs_write32(VM_ENTRY_CONTROLS,
975 vmcs_read32(VM_ENTRY_CONTROLS) |
976 VM_ENTRY_CONTROLS_IA32E_MASK);
977 msr->data = efer;
978
979 } else {
980 vmcs_write32(VM_ENTRY_CONTROLS,
981 vmcs_read32(VM_ENTRY_CONTROLS) &
982 ~VM_ENTRY_CONTROLS_IA32E_MASK);
983
984 msr->data = efer & ~EFER_LME;
985 }
e38aea3e 986 setup_msrs(vcpu);
6aa8b732
AK		 987}
988
989#endif
990
991static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
992{
993 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
994
995 return vmcs_readl(sf->base);
996}
997
998static void vmx_get_segment(struct kvm_vcpu *vcpu,
999 struct kvm_segment *var, int seg)
1000{
1001 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1002 u32 ar;
1003
1004 var->base = vmcs_readl(sf->base);
1005 var->limit = vmcs_read32(sf->limit);
1006 var->selector = vmcs_read16(sf->selector);
1007 ar = vmcs_read32(sf->ar_bytes);
1008 if (ar & AR_UNUSABLE_MASK)
1009 ar = 0;
1010 var->type = ar & 15;
1011 var->s = (ar >> 4) & 1;
1012 var->dpl = (ar >> 5) & 3;
1013 var->present = (ar >> 7) & 1;
1014 var->avl = (ar >> 12) & 1;
1015 var->l = (ar >> 13) & 1;
1016 var->db = (ar >> 14) & 1;
1017 var->g = (ar >> 15) & 1;
1018 var->unusable = (ar >> 16) & 1;
1019}
1020
1021static void vmx_set_segment(struct kvm_vcpu *vcpu,
1022 struct kvm_segment *var, int seg)
1023{
1024 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1025 u32 ar;
1026
1027 vmcs_writel(sf->base, var->base);
1028 vmcs_write32(sf->limit, var->limit);
1029 vmcs_write16(sf->selector, var->selector);
038881c8
AK		 1030 if (vcpu->rmode.active && var->s) {
1031 /*
1032 * Hack real-mode segments into vm86 compatibility.
1033 */
1034 if (var->base == 0xffff0000 && var->selector == 0xf000)
1035 vmcs_writel(sf->base, 0xf0000);
1036 ar = 0xf3;
1037 } else if (var->unusable)
6aa8b732
AK		 1038 ar = 1 << 16;
1039 else {
1040 ar = var->type & 15;
1041 ar |= (var->s & 1) << 4;
1042 ar |= (var->dpl & 3) << 5;
1043 ar |= (var->present & 1) << 7;
1044 ar |= (var->avl & 1) << 12;
1045 ar |= (var->l & 1) << 13;
1046 ar |= (var->db & 1) << 14;
1047 ar |= (var->g & 1) << 15;
1048 }
f7fbf1fd
UL		 1049 if (ar == 0) /* a 0 value means unusable */
1050 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 1051 vmcs_write32(sf->ar_bytes, ar);
1052}
1053
6aa8b732
AK		 1054static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1055{
1056 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1057
1058 *db = (ar >> 14) & 1;
1059 *l = (ar >> 13) & 1;
1060}
1061
1062static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1063{
1064 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1065 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1066}
1067
1068static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1069{
1070 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1071 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1072}
1073
1074static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1075{
1076 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1077 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1078}
1079
1080static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1081{
1082 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1083 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1084}
1085
1086static int init_rmode_tss(struct kvm* kvm)
1087{
1088 struct page *p1, *p2, *p3;
1089 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1090 char *page;
1091
954bbbc2
AK		 1092 p1 = gfn_to_page(kvm, fn++);
1093 p2 = gfn_to_page(kvm, fn++);
1094 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1095
1096 if (!p1 || !p2 || !p3) {
1097 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1098 return 0;
1099 }
1100
1101 page = kmap_atomic(p1, KM_USER0);
1102 memset(page, 0, PAGE_SIZE);
1103 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1104 kunmap_atomic(page, KM_USER0);
1105
1106 page = kmap_atomic(p2, KM_USER0);
1107 memset(page, 0, PAGE_SIZE);
1108 kunmap_atomic(page, KM_USER0);
1109
1110 page = kmap_atomic(p3, KM_USER0);
1111 memset(page, 0, PAGE_SIZE);
1112 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1113 kunmap_atomic(page, KM_USER0);
1114
1115 return 1;
1116}
1117
1118static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1119{
1120 u32 msr_high, msr_low;
1121
1122 rdmsr(msr, msr_low, msr_high);
1123
1124 val &= msr_high;
1125 val |= msr_low;
1126 vmcs_write32(vmcs_field, val);
1127}
1128
1129static void seg_setup(int seg)
1130{
1131 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1132
1133 vmcs_write16(sf->selector, 0);
1134 vmcs_writel(sf->base, 0);
1135 vmcs_write32(sf->limit, 0xffff);
1136 vmcs_write32(sf->ar_bytes, 0x93);
1137}
1138
1139/*
1140 * Sets up the vmcs for emulated real mode.
1141 */
1142static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1143{
1144 u32 host_sysenter_cs;
1145 u32 junk;
1146 unsigned long a;
1147 struct descriptor_table dt;
1148 int i;
1149 int ret = 0;
6aa8b732
AK		 1150 extern asmlinkage void kvm_vmx_return(void);
1151
1152 if (!init_rmode_tss(vcpu->kvm)) {
1153 ret = -ENOMEM;
1154 goto out;
1155 }
1156
1157 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1158 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1159 vcpu->cr8 = 0;
1160 vcpu->apic_base = 0xfee00000 |
1161 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1162 MSR_IA32_APICBASE_ENABLE;
1163
1164 fx_init(vcpu);
1165
1166 /*
1167 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1168 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1169 */
1170 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1171 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1172 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1173 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1174
1175 seg_setup(VCPU_SREG_DS);
1176 seg_setup(VCPU_SREG_ES);
1177 seg_setup(VCPU_SREG_FS);
1178 seg_setup(VCPU_SREG_GS);
1179 seg_setup(VCPU_SREG_SS);
1180
1181 vmcs_write16(GUEST_TR_SELECTOR, 0);
1182 vmcs_writel(GUEST_TR_BASE, 0);
1183 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1184 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1185
1186 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1187 vmcs_writel(GUEST_LDTR_BASE, 0);
1188 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1189 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1190
1191 vmcs_write32(GUEST_SYSENTER_CS, 0);
1192 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1193 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1194
1195 vmcs_writel(GUEST_RFLAGS, 0x02);
1196 vmcs_writel(GUEST_RIP, 0xfff0);
1197 vmcs_writel(GUEST_RSP, 0);
1198
6aa8b732
AK		 1199 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1200 vmcs_writel(GUEST_DR7, 0x400);
1201
1202 vmcs_writel(GUEST_GDTR_BASE, 0);
1203 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1204
1205 vmcs_writel(GUEST_IDTR_BASE, 0);
1206 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1207
1208 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1209 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1210 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1211
1212 /* I/O */
fdef3ad1
HQ		 1213 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1214 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1215
1216 guest_write_tsc(0);
1217
1218 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1219
1220 /* Special registers */
1221 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1222
1223 /* Control */
c68876fd 1224 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1225 PIN_BASED_VM_EXEC_CONTROL,
1226 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1227 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1228 );
c68876fd 1229 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1230 CPU_BASED_VM_EXEC_CONTROL,
1231 CPU_BASED_HLT_EXITING /* 20.6.2 */
1232 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1233 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
fdef3ad1 1234 | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */
6aa8b732
AK		 1235 | CPU_BASED_MOV_DR_EXITING
1236 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1237 );
1238
1239 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1240 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1241 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1242 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1243
1244 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1245 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1246 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1247
1248 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1249 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1250 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1251 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1252 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1253 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1254#ifdef CONFIG_X86_64
6aa8b732
AK		 1255 rdmsrl(MSR_FS_BASE, a);
1256 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1257 rdmsrl(MSR_GS_BASE, a);
1258 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1259#else
1260 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1261 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1262#endif
1263
1264 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1265
1266 get_idt(&dt);
1267 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1268
1269
1270 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1271
1272 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1273 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1274 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1275 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1276 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1277 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1278
6aa8b732
AK		 1279 for (i = 0; i < NR_VMX_MSR; ++i) {
1280 u32 index = vmx_msr_index[i];
1281 u32 data_low, data_high;
1282 u64 data;
1283 int j = vcpu->nmsrs;
1284
1285 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1286 continue;
432bd6cb
AK		 1287 if (wrmsr_safe(index, data_low, data_high) < 0)
1288 continue;
6aa8b732
AK		 1289 data = data_low | ((u64)data_high << 32);
1290 vcpu->host_msrs[j].index = index;
1291 vcpu->host_msrs[j].reserved = 0;
1292 vcpu->host_msrs[j].data = data;
1293 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
2345df8c
AK		 1294#ifdef CONFIG_X86_64
1295 if (index == MSR_KERNEL_GS_BASE)
1296 msr_offset_kernel_gs_base = j;
1297#endif
6aa8b732
AK		 1298 ++vcpu->nmsrs;
1299 }
6aa8b732 1300
e38aea3e
AK		 1301 setup_msrs(vcpu);
1302
c68876fd 1303 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732 1304 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
6aa8b732
AK		 1305
1306 /* 22.2.1, 20.8.1 */
c68876fd 1307 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1308 VM_ENTRY_CONTROLS, 0);
1309 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1310
3b99ab24 1311#ifdef CONFIG_X86_64
6aa8b732
AK		 1312 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1313 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1314#endif
6aa8b732 1315
25c4c276 1316 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1317 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1318
1319 vcpu->cr0 = 0x60000010;
1320 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1321 vmx_set_cr4(vcpu, 0);
05b3e0c2 1322#ifdef CONFIG_X86_64
6aa8b732
AK		 1323 vmx_set_efer(vcpu, 0);
1324#endif
1325
1326 return 0;
1327
6aa8b732
AK		 1328out:
1329 return ret;
1330}
1331
1332static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1333{
1334 u16 ent[2];
1335 u16 cs;
1336 u16 ip;
1337 unsigned long flags;
1338 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1339 u16 sp = vmcs_readl(GUEST_RSP);
1340 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1341
3964994b 1342 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1343 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1344 __FUNCTION__,
1345 vmcs_readl(GUEST_RSP),
1346 vmcs_readl(GUEST_SS_BASE),
1347 vmcs_read32(GUEST_SS_LIMIT));
1348 return;
1349 }
1350
1351 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1352 sizeof(ent)) {
1353 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1354 return;
1355 }
1356
1357 flags = vmcs_readl(GUEST_RFLAGS);
1358 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1359 ip = vmcs_readl(GUEST_RIP);
1360
1361
1362 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1363 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1364 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1365 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1366 return;
1367 }
1368
1369 vmcs_writel(GUEST_RFLAGS, flags &
1370 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1371 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1372 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1373 vmcs_writel(GUEST_RIP, ent[0]);
1374 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1375}
1376
1377static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1378{
1379 int word_index = __ffs(vcpu->irq_summary);
1380 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1381 int irq = word_index * BITS_PER_LONG + bit_index;
1382
1383 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1384 if (!vcpu->irq_pending[word_index])
1385 clear_bit(word_index, &vcpu->irq_summary);
1386
1387 if (vcpu->rmode.active) {
1388 inject_rmode_irq(vcpu, irq);
1389 return;
1390 }
1391 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1392 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1393}
1394
c1150d8c
DL		 1395
1396static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1397 struct kvm_run *kvm_run)
6aa8b732 1398{
c1150d8c
DL		 1399 u32 cpu_based_vm_exec_control;
1400
1401 vcpu->interrupt_window_open =
1402 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1403 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1404
1405 if (vcpu->interrupt_window_open &&
1406 vcpu->irq_summary &&
1407 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1408 /*
c1150d8c 1409 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1410 */
1411 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1412
1413 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1414 if (!vcpu->interrupt_window_open &&
1415 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1416 /*
1417 * Interrupts blocked. Wait for unblock.
1418 */
c1150d8c
DL		 1419 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1420 else
1421 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1422 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1423}
1424
1425static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1426{
1427 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1428
1429 set_debugreg(dbg->bp[0], 0);
1430 set_debugreg(dbg->bp[1], 1);
1431 set_debugreg(dbg->bp[2], 2);
1432 set_debugreg(dbg->bp[3], 3);
1433
1434 if (dbg->singlestep) {
1435 unsigned long flags;
1436
1437 flags = vmcs_readl(GUEST_RFLAGS);
1438 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1439 vmcs_writel(GUEST_RFLAGS, flags);
1440 }
1441}
1442
1443static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1444 int vec, u32 err_code)
1445{
1446 if (!vcpu->rmode.active)
1447 return 0;
1448
1449 if (vec == GP_VECTOR && err_code == 0)
1450 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1451 return 1;
1452 return 0;
1453}
1454
1455static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1456{
1457 u32 intr_info, error_code;
1458 unsigned long cr2, rip;
1459 u32 vect_info;
1460 enum emulation_result er;
e2dec939 1461 int r;
6aa8b732
AK		 1462
1463 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1464 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1465
1466 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1467 !is_page_fault(intr_info)) {
1468 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1469 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1470 }
1471
1472 if (is_external_interrupt(vect_info)) {
1473 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1474 set_bit(irq, vcpu->irq_pending);
1475 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1476 }
1477
1478 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1479 asm ("int $2");
1480 return 1;
1481 }
2ab455cc
AL		 1482
1483 if (is_no_device(intr_info)) {
1484 vcpu->fpu_active = 1;
1485 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1486 if (!(vcpu->cr0 & CR0_TS_MASK))
1487 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1488 return 1;
1489 }
1490
6aa8b732
AK		 1491 error_code = 0;
1492 rip = vmcs_readl(GUEST_RIP);
1493 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1494 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1495 if (is_page_fault(intr_info)) {
1496 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1497
1498 spin_lock(&vcpu->kvm->lock);
e2dec939
AK		 1499 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1500 if (r < 0) {
1501 spin_unlock(&vcpu->kvm->lock);
1502 return r;
1503 }
1504 if (!r) {
6aa8b732
AK		 1505 spin_unlock(&vcpu->kvm->lock);
1506 return 1;
1507 }
1508
1509 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1510 spin_unlock(&vcpu->kvm->lock);
1511
1512 switch (er) {
1513 case EMULATE_DONE:
1514 return 1;
1515 case EMULATE_DO_MMIO:
1165f5fe 1516 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1517 kvm_run->exit_reason = KVM_EXIT_MMIO;
1518 return 0;
1519 case EMULATE_FAIL:
1520 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1521 break;
1522 default:
1523 BUG();
1524 }
1525 }
1526
1527 if (vcpu->rmode.active &&
1528 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1529 error_code))
1530 return 1;
1531
1532 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1533 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1534 return 0;
1535 }
1536 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1537 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1538 kvm_run->ex.error_code = error_code;
1539 return 0;
1540}
1541
1542static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1543 struct kvm_run *kvm_run)
1544{
1165f5fe 1545 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1546 return 1;
1547}
1548
988ad74f
AK		 1549static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1550{
1551 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1552 return 0;
1553}
6aa8b732 1554
039576c0 1555static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
6aa8b732
AK		 1556{
1557 u64 inst;
1558 gva_t rip;
1559 int countr_size;
1560 int i, n;
1561
1562 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1563 countr_size = 2;
1564 } else {
1565 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1566
1567 countr_size = (cs_ar & AR_L_MASK) ? 8:
1568 (cs_ar & AR_DB_MASK) ? 4: 2;
1569 }
1570
1571 rip = vmcs_readl(GUEST_RIP);
1572 if (countr_size != 8)
1573 rip += vmcs_readl(GUEST_CS_BASE);
1574
1575 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1576
1577 for (i = 0; i < n; i++) {
1578 switch (((u8*)&inst)[i]) {
1579 case 0xf0:
1580 case 0xf2:
1581 case 0xf3:
1582 case 0x2e:
1583 case 0x36:
1584 case 0x3e:
1585 case 0x26:
1586 case 0x64:
1587 case 0x65:
1588 case 0x66:
1589 break;
1590 case 0x67:
1591 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1592 default:
1593 goto done;
1594 }
1595 }
1596 return 0;
1597done:
1598 countr_size *= 8;
1599 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
039576c0 1600 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
6aa8b732
AK		 1601 return 1;
1602}
1603
1604static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1605{
1606 u64 exit_qualification;
039576c0
AK		 1607 int size, down, in, string, rep;
1608 unsigned port;
1609 unsigned long count;
1610 gva_t address;
6aa8b732 1611
1165f5fe 1612 ++vcpu->stat.io_exits;
6aa8b732 1613 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0
AK		 1614 in = (exit_qualification & 8) != 0;
1615 size = (exit_qualification & 7) + 1;
1616 string = (exit_qualification & 16) != 0;
1617 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1618 count = 1;
1619 rep = (exit_qualification & 32) != 0;
1620 port = exit_qualification >> 16;
1621 address = 0;
1622 if (string) {
1623 if (rep && !get_io_count(vcpu, &count))
6aa8b732 1624 return 1;
039576c0
AK		 1625 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1626 }
1627 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1628 address, rep, port);
6aa8b732
AK		 1629}
1630
102d8325
IM		 1631static void
1632vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1633{
1634 /*
1635 * Patch in the VMCALL instruction:
1636 */
1637 hypercall[0] = 0x0f;
1638 hypercall[1] = 0x01;
1639 hypercall[2] = 0xc1;
1640 hypercall[3] = 0xc3;
1641}
1642
6aa8b732
AK		 1643static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1644{
1645 u64 exit_qualification;
1646 int cr;
1647 int reg;
1648
1649 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1650 cr = exit_qualification & 15;
1651 reg = (exit_qualification >> 8) & 15;
1652 switch ((exit_qualification >> 4) & 3) {
1653 case 0: /* mov to cr */
1654 switch (cr) {
1655 case 0:
1656 vcpu_load_rsp_rip(vcpu);
1657 set_cr0(vcpu, vcpu->regs[reg]);
1658 skip_emulated_instruction(vcpu);
1659 return 1;
1660 case 3:
1661 vcpu_load_rsp_rip(vcpu);
1662 set_cr3(vcpu, vcpu->regs[reg]);
1663 skip_emulated_instruction(vcpu);
1664 return 1;
1665 case 4:
1666 vcpu_load_rsp_rip(vcpu);
1667 set_cr4(vcpu, vcpu->regs[reg]);
1668 skip_emulated_instruction(vcpu);
1669 return 1;
1670 case 8:
1671 vcpu_load_rsp_rip(vcpu);
1672 set_cr8(vcpu, vcpu->regs[reg]);
1673 skip_emulated_instruction(vcpu);
1674 return 1;
1675 };
1676 break;
25c4c276
AL		 1677 case 2: /* clts */
1678 vcpu_load_rsp_rip(vcpu);
2ab455cc
AL		 1679 vcpu->fpu_active = 1;
1680 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1681 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1682 vcpu->cr0 &= ~CR0_TS_MASK;
1683 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
25c4c276
AL		 1684 skip_emulated_instruction(vcpu);
1685 return 1;
6aa8b732
AK		 1686 case 1: /*mov from cr*/
1687 switch (cr) {
1688 case 3:
1689 vcpu_load_rsp_rip(vcpu);
1690 vcpu->regs[reg] = vcpu->cr3;
1691 vcpu_put_rsp_rip(vcpu);
1692 skip_emulated_instruction(vcpu);
1693 return 1;
1694 case 8:
6aa8b732
AK		 1695 vcpu_load_rsp_rip(vcpu);
1696 vcpu->regs[reg] = vcpu->cr8;
1697 vcpu_put_rsp_rip(vcpu);
1698 skip_emulated_instruction(vcpu);
1699 return 1;
1700 }
1701 break;
1702 case 3: /* lmsw */
1703 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1704
1705 skip_emulated_instruction(vcpu);
1706 return 1;
1707 default:
1708 break;
1709 }
1710 kvm_run->exit_reason = 0;
1711 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1712 (int)(exit_qualification >> 4) & 3, cr);
1713 return 0;
1714}
1715
1716static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1717{
1718 u64 exit_qualification;
1719 unsigned long val;
1720 int dr, reg;
1721
1722 /*
1723 * FIXME: this code assumes the host is debugging the guest.
1724 * need to deal with guest debugging itself too.
1725 */
1726 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1727 dr = exit_qualification & 7;
1728 reg = (exit_qualification >> 8) & 15;
1729 vcpu_load_rsp_rip(vcpu);
1730 if (exit_qualification & 16) {
1731 /* mov from dr */
1732 switch (dr) {
1733 case 6:
1734 val = 0xffff0ff0;
1735 break;
1736 case 7:
1737 val = 0x400;
1738 break;
1739 default:
1740 val = 0;
1741 }
1742 vcpu->regs[reg] = val;
1743 } else {
1744 /* mov to dr */
1745 }
1746 vcpu_put_rsp_rip(vcpu);
1747 skip_emulated_instruction(vcpu);
1748 return 1;
1749}
1750
1751static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1752{
06465c5a
AK		 1753 kvm_emulate_cpuid(vcpu);
1754 return 1;
6aa8b732
AK		 1755}
1756
1757static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1758{
1759 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1760 u64 data;
1761
1762 if (vmx_get_msr(vcpu, ecx, &data)) {
1763 vmx_inject_gp(vcpu, 0);
1764 return 1;
1765 }
1766
1767 /* FIXME: handling of bits 32:63 of rax, rdx */
1768 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1769 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1770 skip_emulated_instruction(vcpu);
1771 return 1;
1772}
1773
1774static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1775{
1776 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1777 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1778 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1779
1780 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1781 vmx_inject_gp(vcpu, 0);
1782 return 1;
1783 }
1784
1785 skip_emulated_instruction(vcpu);
1786 return 1;
1787}
1788
c1150d8c
DL		 1789static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1790 struct kvm_run *kvm_run)
1791{
1792 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1793 kvm_run->cr8 = vcpu->cr8;
1794 kvm_run->apic_base = vcpu->apic_base;
1795 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1796 vcpu->irq_summary == 0);
1797}
1798
6aa8b732
AK		 1799static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1800 struct kvm_run *kvm_run)
1801{
c1150d8c
DL		 1802 /*
1803 * If the user space waits to inject interrupts, exit as soon as
1804 * possible
1805 */
1806 if (kvm_run->request_interrupt_window &&
022a9308 1807 !vcpu->irq_summary) {
c1150d8c 1808 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 1809 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1810 return 0;
1811 }
6aa8b732
AK		 1812 return 1;
1813}
1814
1815static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1816{
1817 skip_emulated_instruction(vcpu);
c1150d8c 1818 if (vcpu->irq_summary)
6aa8b732
AK		 1819 return 1;
1820
1821 kvm_run->exit_reason = KVM_EXIT_HLT;
1165f5fe 1822 ++vcpu->stat.halt_exits;
6aa8b732
AK		 1823 return 0;
1824}
1825
c21415e8
IM		 1826static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1827{
510043da 1828 skip_emulated_instruction(vcpu);
270fd9b9 1829 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 1830}
1831
6aa8b732
AK		 1832/*
1833 * The exit handlers return 1 if the exit was handled fully and guest execution
1834 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1835 * to be done to userspace and return 0.
1836 */
1837static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1838 struct kvm_run *kvm_run) = {
1839 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1840 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 1841 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 1842 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 1843 [EXIT_REASON_CR_ACCESS] = handle_cr,
1844 [EXIT_REASON_DR_ACCESS] = handle_dr,
1845 [EXIT_REASON_CPUID] = handle_cpuid,
1846 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1847 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1848 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1849 [EXIT_REASON_HLT] = handle_halt,
c21415e8 1850 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 1851};
1852
1853static const int kvm_vmx_max_exit_handlers =
1854 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1855
1856/*
1857 * The guest has exited. See if we can fix it or if we need userspace
1858 * assistance.
1859 */
1860static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1861{
1862 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1863 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1864
1865 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1866 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1867 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1868 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 1869 if (exit_reason < kvm_vmx_max_exit_handlers
1870 && kvm_vmx_exit_handlers[exit_reason])
1871 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1872 else {
1873 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1874 kvm_run->hw.hardware_exit_reason = exit_reason;
1875 }
1876 return 0;
1877}
1878
c1150d8c
DL		 1879/*
1880 * Check if userspace requested an interrupt window, and that the
1881 * interrupt window is open.
1882 *
1883 * No need to exit to userspace if we already have an interrupt queued.
1884 */
1885static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1886 struct kvm_run *kvm_run)
1887{
1888 return (!vcpu->irq_summary &&
1889 kvm_run->request_interrupt_window &&
1890 vcpu->interrupt_window_open &&
1891 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1892}
1893
6aa8b732
AK		 1894static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1895{
1896 u8 fail;
e2dec939 1897 int r;
6aa8b732 1898
e6adf283 1899preempted:
cccf748b
AK		 1900 if (!vcpu->mmio_read_completed)
1901 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1902
1903 if (vcpu->guest_debug.enabled)
1904 kvm_guest_debug_pre(vcpu);
1905
2345df8c 1906#ifdef CONFIG_X86_64
e38aea3e
AK		 1907 if (is_long_mode(vcpu)) {
1908 save_msrs(vcpu->host_msrs + msr_offset_kernel_gs_base, 1);
1909 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1910 }
2345df8c 1911#endif
6aa8b732 1912
e6adf283 1913again:
33ed6329 1914 vmx_save_host_state(vcpu);
e6adf283
AK		 1915 kvm_load_guest_fpu(vcpu);
1916
1917 /*
1918 * Loading guest fpu may have cleared host cr0.ts
1919 */
1920 vmcs_writel(HOST_CR0, read_cr0());
1921
6aa8b732
AK		 1922 asm (
1923 /* Store host registers */
1924 "pushf \n\t"
05b3e0c2 1925#ifdef CONFIG_X86_64
6aa8b732
AK		 1926 "push %%rax; push %%rbx; push %%rdx;"
1927 "push %%rsi; push %%rdi; push %%rbp;"
1928 "push %%r8; push %%r9; push %%r10; push %%r11;"
1929 "push %%r12; push %%r13; push %%r14; push %%r15;"
1930 "push %%rcx \n\t"
1931 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1932#else
1933 "pusha; push %%ecx \n\t"
1934 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1935#endif
1936 /* Check if vmlaunch of vmresume is needed */
1937 "cmp $0, %1 \n\t"
1938 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1939#ifdef CONFIG_X86_64
6aa8b732
AK		 1940 "mov %c[cr2](%3), %%rax \n\t"
1941 "mov %%rax, %%cr2 \n\t"
1942 "mov %c[rax](%3), %%rax \n\t"
1943 "mov %c[rbx](%3), %%rbx \n\t"
1944 "mov %c[rdx](%3), %%rdx \n\t"
1945 "mov %c[rsi](%3), %%rsi \n\t"
1946 "mov %c[rdi](%3), %%rdi \n\t"
1947 "mov %c[rbp](%3), %%rbp \n\t"
1948 "mov %c[r8](%3), %%r8 \n\t"
1949 "mov %c[r9](%3), %%r9 \n\t"
1950 "mov %c[r10](%3), %%r10 \n\t"
1951 "mov %c[r11](%3), %%r11 \n\t"
1952 "mov %c[r12](%3), %%r12 \n\t"
1953 "mov %c[r13](%3), %%r13 \n\t"
1954 "mov %c[r14](%3), %%r14 \n\t"
1955 "mov %c[r15](%3), %%r15 \n\t"
1956 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1957#else
1958 "mov %c[cr2](%3), %%eax \n\t"
1959 "mov %%eax, %%cr2 \n\t"
1960 "mov %c[rax](%3), %%eax \n\t"
1961 "mov %c[rbx](%3), %%ebx \n\t"
1962 "mov %c[rdx](%3), %%edx \n\t"
1963 "mov %c[rsi](%3), %%esi \n\t"
1964 "mov %c[rdi](%3), %%edi \n\t"
1965 "mov %c[rbp](%3), %%ebp \n\t"
1966 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1967#endif
1968 /* Enter guest mode */
1969 "jne launched \n\t"
1970 ASM_VMX_VMLAUNCH "\n\t"
1971 "jmp kvm_vmx_return \n\t"
1972 "launched: " ASM_VMX_VMRESUME "\n\t"
1973 ".globl kvm_vmx_return \n\t"
1974 "kvm_vmx_return: "
1975 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1976#ifdef CONFIG_X86_64
96958231 1977 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 1978 "mov %%rax, %c[rax](%3) \n\t"
1979 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 1980 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 1981 "mov %%rdx, %c[rdx](%3) \n\t"
1982 "mov %%rsi, %c[rsi](%3) \n\t"
1983 "mov %%rdi, %c[rdi](%3) \n\t"
1984 "mov %%rbp, %c[rbp](%3) \n\t"
1985 "mov %%r8, %c[r8](%3) \n\t"
1986 "mov %%r9, %c[r9](%3) \n\t"
1987 "mov %%r10, %c[r10](%3) \n\t"
1988 "mov %%r11, %c[r11](%3) \n\t"
1989 "mov %%r12, %c[r12](%3) \n\t"
1990 "mov %%r13, %c[r13](%3) \n\t"
1991 "mov %%r14, %c[r14](%3) \n\t"
1992 "mov %%r15, %c[r15](%3) \n\t"
1993 "mov %%cr2, %%rax \n\t"
1994 "mov %%rax, %c[cr2](%3) \n\t"
96958231 1995 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 1996
1997 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1998 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1999 "pop %%rbp; pop %%rdi; pop %%rsi;"
2000 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2001#else
96958231 2002 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2003 "mov %%eax, %c[rax](%3) \n\t"
2004 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2005 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2006 "mov %%edx, %c[rdx](%3) \n\t"
2007 "mov %%esi, %c[rsi](%3) \n\t"
2008 "mov %%edi, %c[rdi](%3) \n\t"
2009 "mov %%ebp, %c[rbp](%3) \n\t"
2010 "mov %%cr2, %%eax \n\t"
2011 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2012 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2013
2014 "pop %%ecx; popa \n\t"
2015#endif
2016 "setbe %0 \n\t"
2017 "popf \n\t"
e0015489 2018 : "=q" (fail)
6aa8b732
AK		 2019 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
2020 "c"(vcpu),
2021 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2022 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2023 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2024 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2025 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2026 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2027 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2028#ifdef CONFIG_X86_64
6aa8b732
AK		 2029 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2030 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2031 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2032 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2033 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2034 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2035 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2036 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2037#endif
2038 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2039 : "cc", "memory" );
2040
1165f5fe 2041 ++vcpu->stat.exits;
6aa8b732 2042
c1150d8c 2043 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2044
6aa8b732 2045 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6aa8b732 2046
05e0c8c3 2047 if (unlikely(fail)) {
8eb7d334
AK		 2048 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2049 kvm_run->fail_entry.hardware_entry_failure_reason
2050 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2051 r = 0;
05e0c8c3
AK		 2052 goto out;
2053 }
2054 /*
2055 * Profile KVM exit RIPs:
2056 */
2057 if (unlikely(prof_on == KVM_PROFILING))
2058 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2059
2060 vcpu->launched = 1;
2061 r = kvm_handle_exit(kvm_run, vcpu);
2062 if (r > 0) {
2063 /* Give scheduler a change to reschedule. */
2064 if (signal_pending(current)) {
2065 r = -EINTR;
2066 kvm_run->exit_reason = KVM_EXIT_INTR;
2067 ++vcpu->stat.signal_exits;
2068 goto out;
2069 }
2070
2071 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2072 r = -EINTR;
2073 kvm_run->exit_reason = KVM_EXIT_INTR;
2074 ++vcpu->stat.request_irq_exits;
2075 goto out;
2076 }
2077 if (!need_resched()) {
2078 ++vcpu->stat.light_exits;
2079 goto again;
6aa8b732
AK		 2080 }
2081 }
c1150d8c 2082
e6adf283 2083out:
e6adf283
AK		 2084 if (r > 0) {
2085 kvm_resched(vcpu);
2086 goto preempted;
2087 }
2088
c1150d8c 2089 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2090 return r;
6aa8b732
AK		 2091}
2092
2093static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2094{
2095 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
2096}
2097
2098static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2099 unsigned long addr,
2100 u32 err_code)
2101{
2102 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2103
1165f5fe 2104 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2105
2106 if (is_page_fault(vect_info)) {
2107 printk(KERN_DEBUG "inject_page_fault: "
2108 "double fault 0x%lx @ 0x%lx\n",
2109 addr, vmcs_readl(GUEST_RIP));
2110 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2111 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2112 DF_VECTOR |
2113 INTR_TYPE_EXCEPTION |
2114 INTR_INFO_DELIEVER_CODE_MASK |
2115 INTR_INFO_VALID_MASK);
2116 return;
2117 }
2118 vcpu->cr2 = addr;
2119 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2120 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2121 PF_VECTOR |
2122 INTR_TYPE_EXCEPTION |
2123 INTR_INFO_DELIEVER_CODE_MASK |
2124 INTR_INFO_VALID_MASK);
2125
2126}
2127
2128static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2129{
2130 if (vcpu->vmcs) {
2131 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2132 free_vmcs(vcpu->vmcs);
2133 vcpu->vmcs = NULL;
2134 }
2135}
2136
2137static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2138{
2139 vmx_free_vmcs(vcpu);
2140}
2141
2142static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2143{
2144 struct vmcs *vmcs;
2145
965b58a5
IM		 2146 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2147 if (!vcpu->guest_msrs)
2148 return -ENOMEM;
2149
2150 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2151 if (!vcpu->host_msrs)
2152 goto out_free_guest_msrs;
2153
6aa8b732
AK		 2154 vmcs = alloc_vmcs();
2155 if (!vmcs)
965b58a5
IM		 2156 goto out_free_msrs;
2157
6aa8b732
AK		 2158 vmcs_clear(vmcs);
2159 vcpu->vmcs = vmcs;
2160 vcpu->launched = 0;
2ab455cc 2161 vcpu->fpu_active = 1;
965b58a5 2162
6aa8b732 2163 return 0;
965b58a5
IM		 2164
2165out_free_msrs:
2166 kfree(vcpu->host_msrs);
2167 vcpu->host_msrs = NULL;
2168
2169out_free_guest_msrs:
2170 kfree(vcpu->guest_msrs);
2171 vcpu->guest_msrs = NULL;
2172
2173 return -ENOMEM;
6aa8b732
AK		 2174}
2175
2176static struct kvm_arch_ops vmx_arch_ops = {
2177 .cpu_has_kvm_support = cpu_has_kvm_support,
2178 .disabled_by_bios = vmx_disabled_by_bios,
2179 .hardware_setup = hardware_setup,
2180 .hardware_unsetup = hardware_unsetup,
2181 .hardware_enable = hardware_enable,
2182 .hardware_disable = hardware_disable,
2183
2184 .vcpu_create = vmx_create_vcpu,
2185 .vcpu_free = vmx_free_vcpu,
2186
2187 .vcpu_load = vmx_vcpu_load,
2188 .vcpu_put = vmx_vcpu_put,
774c47f1 2189 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2190
2191 .set_guest_debug = set_guest_debug,
2192 .get_msr = vmx_get_msr,
2193 .set_msr = vmx_set_msr,
2194 .get_segment_base = vmx_get_segment_base,
2195 .get_segment = vmx_get_segment,
2196 .set_segment = vmx_set_segment,
6aa8b732 2197 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2198 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2199 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2200 .set_cr3 = vmx_set_cr3,
2201 .set_cr4 = vmx_set_cr4,
05b3e0c2 2202#ifdef CONFIG_X86_64
6aa8b732
AK		 2203 .set_efer = vmx_set_efer,
2204#endif
2205 .get_idt = vmx_get_idt,
2206 .set_idt = vmx_set_idt,
2207 .get_gdt = vmx_get_gdt,
2208 .set_gdt = vmx_set_gdt,
2209 .cache_regs = vcpu_load_rsp_rip,
2210 .decache_regs = vcpu_put_rsp_rip,
2211 .get_rflags = vmx_get_rflags,
2212 .set_rflags = vmx_set_rflags,
2213
2214 .tlb_flush = vmx_flush_tlb,
2215 .inject_page_fault = vmx_inject_page_fault,
2216
2217 .inject_gp = vmx_inject_gp,
2218
2219 .run = vmx_vcpu_run,
2220 .skip_emulated_instruction = skip_emulated_instruction,
2221 .vcpu_setup = vmx_vcpu_setup,
102d8325 2222 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2223};
2224
2225static int __init vmx_init(void)
2226{
fdef3ad1
HQ		 2227 void *iova;
2228 int r;
2229
2230 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2231 if (!vmx_io_bitmap_a)
2232 return -ENOMEM;
2233
2234 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2235 if (!vmx_io_bitmap_b) {
2236 r = -ENOMEM;
2237 goto out;
2238 }
2239
2240 /*
2241 * Allow direct access to the PC debug port (it is often used for I/O
2242 * delays, but the vmexits simply slow things down).
2243 */
2244 iova = kmap(vmx_io_bitmap_a);
2245 memset(iova, 0xff, PAGE_SIZE);
2246 clear_bit(0x80, iova);
2247 kunmap(iova);
2248
2249 iova = kmap(vmx_io_bitmap_b);
2250 memset(iova, 0xff, PAGE_SIZE);
2251 kunmap(iova);
2252
2253 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2254 if (r)
2255 goto out1;
2256
2257 return 0;
2258
2259out1:
2260 __free_page(vmx_io_bitmap_b);
2261out:
2262 __free_page(vmx_io_bitmap_a);
2263 return r;
6aa8b732
AK		 2264}
2265
2266static void __exit vmx_exit(void)
2267{
fdef3ad1
HQ		 2268 __free_page(vmx_io_bitmap_b);
2269 __free_page(vmx_io_bitmap_a);
2270
6aa8b732
AK		 2271 kvm_exit_arch();
2272}
2273
2274module_init(vmx_init)
2275module_exit(vmx_exit)
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