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KVM: Increase mmu shadow cache to 1024 pages
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
6aa8b732 20#include <linux/module.h>
9d8f549d 21#include <linux/kernel.h>
6aa8b732
AK		 22#include <linux/mm.h>
23#include <linux/highmem.h>
07031e14 24#include <linux/profile.h>
e8edc6e0 25#include <linux/sched.h>
6aa8b732 26#include <asm/io.h>
3b3be0d1 27#include <asm/desc.h>
6aa8b732
AK		 28
29#include "segment_descriptor.h"
30
6aa8b732
AK		 31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
fdef3ad1
HQ		 37static struct page *vmx_io_bitmap_a;
38static struct page *vmx_io_bitmap_b;
39
05b3e0c2 40#ifdef CONFIG_X86_64
6aa8b732
AK		 41#define HOST_IS_64 1
42#else
43#define HOST_IS_64 0
44#endif
45
46static struct vmcs_descriptor {
47 int size;
48 int order;
49 u32 revision_id;
50} vmcs_descriptor;
51
52#define VMX_SEGMENT_FIELD(seg) \
53 [VCPU_SREG_##seg] = { \
54 .selector = GUEST_##seg##_SELECTOR, \
55 .base = GUEST_##seg##_BASE, \
56 .limit = GUEST_##seg##_LIMIT, \
57 .ar_bytes = GUEST_##seg##_AR_BYTES, \
58 }
59
60static struct kvm_vmx_segment_field {
61 unsigned selector;
62 unsigned base;
63 unsigned limit;
64 unsigned ar_bytes;
65} kvm_vmx_segment_fields[] = {
66 VMX_SEGMENT_FIELD(CS),
67 VMX_SEGMENT_FIELD(DS),
68 VMX_SEGMENT_FIELD(ES),
69 VMX_SEGMENT_FIELD(FS),
70 VMX_SEGMENT_FIELD(GS),
71 VMX_SEGMENT_FIELD(SS),
72 VMX_SEGMENT_FIELD(TR),
73 VMX_SEGMENT_FIELD(LDTR),
74};
75
4d56c8a7
AK		 76/*
77 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
78 * away by decrementing the array size.
79 */
6aa8b732 80static const u32 vmx_msr_index[] = {
05b3e0c2 81#ifdef CONFIG_X86_64
6aa8b732
AK		 82 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
83#endif
84 MSR_EFER, MSR_K6_STAR,
85};
9d8f549d 86#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 87
2345df8c
AK		 88#ifdef CONFIG_X86_64
89static unsigned msr_offset_kernel_gs_base;
e38aea3e 90#define NR_64BIT_MSRS 4
35cc7f97
AK		 91/*
92 * avoid save/load MSR_SYSCALL_MASK and MSR_LSTAR by std vt
93 * mechanism (cpu bug AA24)
94 */
95#define NR_BAD_MSRS 2
e38aea3e
AK		 96#else
97#define NR_64BIT_MSRS 0
35cc7f97 98#define NR_BAD_MSRS 0
2345df8c
AK		 99#endif
100
6aa8b732
AK		 101static inline int is_page_fault(u32 intr_info)
102{
103 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
104 INTR_INFO_VALID_MASK)) ==
105 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
106}
107
2ab455cc
AL		 108static inline int is_no_device(u32 intr_info)
109{
110 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
111 INTR_INFO_VALID_MASK)) ==
112 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
113}
114
6aa8b732
AK		 115static inline int is_external_interrupt(u32 intr_info)
116{
117 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
118 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
119}
120
7725f0ba
AK		 121static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
122{
123 int i;
124
125 for (i = 0; i < vcpu->nmsrs; ++i)
126 if (vcpu->guest_msrs[i].index == msr)
127 return &vcpu->guest_msrs[i];
8b6d44c7 128 return NULL;
7725f0ba
AK		 129}
130
6aa8b732
AK		 131static void vmcs_clear(struct vmcs *vmcs)
132{
133 u64 phys_addr = __pa(vmcs);
134 u8 error;
135
136 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
137 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
138 : "cc", "memory");
139 if (error)
140 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
141 vmcs, phys_addr);
142}
143
144static void __vcpu_clear(void *arg)
145{
146 struct kvm_vcpu *vcpu = arg;
d3b2c338 147 int cpu = raw_smp_processor_id();
6aa8b732
AK		 148
149 if (vcpu->cpu == cpu)
150 vmcs_clear(vcpu->vmcs);
151 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
152 per_cpu(current_vmcs, cpu) = NULL;
153}
154
8d0be2b3
AK		 155static void vcpu_clear(struct kvm_vcpu *vcpu)
156{
157 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
158 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
159 else
160 __vcpu_clear(vcpu);
161 vcpu->launched = 0;
162}
163
6aa8b732
AK		 164static unsigned long vmcs_readl(unsigned long field)
165{
166 unsigned long value;
167
168 asm volatile (ASM_VMX_VMREAD_RDX_RAX
169 : "=a"(value) : "d"(field) : "cc");
170 return value;
171}
172
173static u16 vmcs_read16(unsigned long field)
174{
175 return vmcs_readl(field);
176}
177
178static u32 vmcs_read32(unsigned long field)
179{
180 return vmcs_readl(field);
181}
182
183static u64 vmcs_read64(unsigned long field)
184{
05b3e0c2 185#ifdef CONFIG_X86_64
6aa8b732
AK		 186 return vmcs_readl(field);
187#else
188 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
189#endif
190}
191
e52de1b8
AK		 192static noinline void vmwrite_error(unsigned long field, unsigned long value)
193{
194 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
195 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
196 dump_stack();
197}
198
6aa8b732
AK		 199static void vmcs_writel(unsigned long field, unsigned long value)
200{
201 u8 error;
202
203 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
204 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 205 if (unlikely(error))
206 vmwrite_error(field, value);
6aa8b732
AK		 207}
208
209static void vmcs_write16(unsigned long field, u16 value)
210{
211 vmcs_writel(field, value);
212}
213
214static void vmcs_write32(unsigned long field, u32 value)
215{
216 vmcs_writel(field, value);
217}
218
219static void vmcs_write64(unsigned long field, u64 value)
220{
05b3e0c2 221#ifdef CONFIG_X86_64
6aa8b732
AK		 222 vmcs_writel(field, value);
223#else
224 vmcs_writel(field, value);
225 asm volatile ("");
226 vmcs_writel(field+1, value >> 32);
227#endif
228}
229
2ab455cc
AL		 230static void vmcs_clear_bits(unsigned long field, u32 mask)
231{
232 vmcs_writel(field, vmcs_readl(field) & ~mask);
233}
234
235static void vmcs_set_bits(unsigned long field, u32 mask)
236{
237 vmcs_writel(field, vmcs_readl(field) | mask);
238}
239
6aa8b732
AK		 240/*
241 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
242 * vcpu mutex is already taken.
243 */
bccf2150 244static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732
AK		 245{
246 u64 phys_addr = __pa(vcpu->vmcs);
247 int cpu;
248
249 cpu = get_cpu();
250
8d0be2b3
AK		 251 if (vcpu->cpu != cpu)
252 vcpu_clear(vcpu);
6aa8b732
AK		 253
254 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
255 u8 error;
256
257 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
258 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
259 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
260 : "cc");
261 if (error)
262 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
263 vcpu->vmcs, phys_addr);
264 }
265
266 if (vcpu->cpu != cpu) {
267 struct descriptor_table dt;
268 unsigned long sysenter_esp;
269
270 vcpu->cpu = cpu;
271 /*
272 * Linux uses per-cpu TSS and GDT, so set these when switching
273 * processors.
274 */
275 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
276 get_gdt(&dt);
277 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
278
279 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
280 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
281 }
6aa8b732
AK		 282}
283
284static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
285{
7702fd1f 286 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 287 put_cpu();
288}
289
774c47f1
AK		 290static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
291{
292 vcpu_clear(vcpu);
293}
294
6aa8b732
AK		 295static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
296{
297 return vmcs_readl(GUEST_RFLAGS);
298}
299
300static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
301{
302 vmcs_writel(GUEST_RFLAGS, rflags);
303}
304
305static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
306{
307 unsigned long rip;
308 u32 interruptibility;
309
310 rip = vmcs_readl(GUEST_RIP);
311 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
312 vmcs_writel(GUEST_RIP, rip);
313
314 /*
315 * We emulated an instruction, so temporary interrupt blocking
316 * should be removed, if set.
317 */
318 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
319 if (interruptibility & 3)
320 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
321 interruptibility & ~3);
c1150d8c 322 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 323}
324
325static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
326{
327 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
328 vmcs_readl(GUEST_RIP));
329 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
330 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
331 GP_VECTOR |
332 INTR_TYPE_EXCEPTION |
333 INTR_INFO_DELIEVER_CODE_MASK |
334 INTR_INFO_VALID_MASK);
335}
336
e38aea3e
AK		 337/*
338 * Set up the vmcs to automatically save and restore system
339 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
340 * mode, as fiddling with msrs is very expensive.
341 */
342static void setup_msrs(struct kvm_vcpu *vcpu)
343{
344 int nr_skip, nr_good_msrs;
345
346 if (is_long_mode(vcpu))
347 nr_skip = NR_BAD_MSRS;
348 else
349 nr_skip = NR_64BIT_MSRS;
350 nr_good_msrs = vcpu->nmsrs - nr_skip;
351
4d56c8a7
AK		 352 /*
353 * MSR_K6_STAR is only needed on long mode guests, and only
354 * if efer.sce is enabled.
355 */
356 if (find_msr_entry(vcpu, MSR_K6_STAR)) {
357 --nr_good_msrs;
358#ifdef CONFIG_X86_64
359 if (is_long_mode(vcpu) && (vcpu->shadow_efer & EFER_SCE))
360 ++nr_good_msrs;
361#endif
362 }
363
e38aea3e
AK		 364 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
365 virt_to_phys(vcpu->guest_msrs + nr_skip));
366 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
367 virt_to_phys(vcpu->guest_msrs + nr_skip));
368 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
369 virt_to_phys(vcpu->host_msrs + nr_skip));
370 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
371 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
372 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
373}
374
6aa8b732
AK		 375/*
376 * reads and returns guest's timestamp counter "register"
377 * guest_tsc = host_tsc + tsc_offset -- 21.3
378 */
379static u64 guest_read_tsc(void)
380{
381 u64 host_tsc, tsc_offset;
382
383 rdtscll(host_tsc);
384 tsc_offset = vmcs_read64(TSC_OFFSET);
385 return host_tsc + tsc_offset;
386}
387
388/*
389 * writes 'guest_tsc' into guest's timestamp counter "register"
390 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
391 */
392static void guest_write_tsc(u64 guest_tsc)
393{
394 u64 host_tsc;
395
396 rdtscll(host_tsc);
397 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
398}
399
400static void reload_tss(void)
401{
05b3e0c2 402#ifndef CONFIG_X86_64
6aa8b732
AK		 403
404 /*
405 * VT restores TR but not its size. Useless.
406 */
407 struct descriptor_table gdt;
408 struct segment_descriptor *descs;
409
410 get_gdt(&gdt);
411 descs = (void *)gdt.base;
412 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
413 load_TR_desc();
414#endif
415}
416
417/*
418 * Reads an msr value (of 'msr_index') into 'pdata'.
419 * Returns 0 on success, non-0 otherwise.
420 * Assumes vcpu_load() was already called.
421 */
422static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
423{
424 u64 data;
425 struct vmx_msr_entry *msr;
426
427 if (!pdata) {
428 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
429 return -EINVAL;
430 }
431
432 switch (msr_index) {
05b3e0c2 433#ifdef CONFIG_X86_64
6aa8b732
AK		 434 case MSR_FS_BASE:
435 data = vmcs_readl(GUEST_FS_BASE);
436 break;
437 case MSR_GS_BASE:
438 data = vmcs_readl(GUEST_GS_BASE);
439 break;
440 case MSR_EFER:
3bab1f5d 441 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 442#endif
443 case MSR_IA32_TIME_STAMP_COUNTER:
444 data = guest_read_tsc();
445 break;
446 case MSR_IA32_SYSENTER_CS:
447 data = vmcs_read32(GUEST_SYSENTER_CS);
448 break;
449 case MSR_IA32_SYSENTER_EIP:
f5b42c33 450 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 451 break;
452 case MSR_IA32_SYSENTER_ESP:
f5b42c33 453 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 454 break;
6aa8b732
AK		 455 default:
456 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 457 if (msr) {
458 data = msr->data;
459 break;
6aa8b732 460 }
3bab1f5d 461 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 462 }
463
464 *pdata = data;
465 return 0;
466}
467
468/*
469 * Writes msr value into into the appropriate "register".
470 * Returns 0 on success, non-0 otherwise.
471 * Assumes vcpu_load() was already called.
472 */
473static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
474{
475 struct vmx_msr_entry *msr;
476 switch (msr_index) {
05b3e0c2 477#ifdef CONFIG_X86_64
3bab1f5d
AK		 478 case MSR_EFER:
479 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 480 case MSR_FS_BASE:
481 vmcs_writel(GUEST_FS_BASE, data);
482 break;
483 case MSR_GS_BASE:
484 vmcs_writel(GUEST_GS_BASE, data);
485 break;
e6adf283
AK		 486 case MSR_LSTAR:
487 case MSR_SYSCALL_MASK:
488 msr = find_msr_entry(vcpu, msr_index);
489 if (msr)
490 msr->data = data;
491 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
492 break;
6aa8b732
AK		 493#endif
494 case MSR_IA32_SYSENTER_CS:
495 vmcs_write32(GUEST_SYSENTER_CS, data);
496 break;
497 case MSR_IA32_SYSENTER_EIP:
f5b42c33 498 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 499 break;
500 case MSR_IA32_SYSENTER_ESP:
f5b42c33 501 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 502 break;
d27d4aca 503 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 504 guest_write_tsc(data);
505 break;
6aa8b732
AK		 506 default:
507 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 508 if (msr) {
509 msr->data = data;
510 break;
6aa8b732 511 }
3bab1f5d 512 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 513 msr->data = data;
514 break;
515 }
516
517 return 0;
518}
519
520/*
521 * Sync the rsp and rip registers into the vcpu structure. This allows
522 * registers to be accessed by indexing vcpu->regs.
523 */
524static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
525{
526 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
527 vcpu->rip = vmcs_readl(GUEST_RIP);
528}
529
530/*
531 * Syncs rsp and rip back into the vmcs. Should be called after possible
532 * modification.
533 */
534static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
535{
536 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
537 vmcs_writel(GUEST_RIP, vcpu->rip);
538}
539
540static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
541{
542 unsigned long dr7 = 0x400;
543 u32 exception_bitmap;
544 int old_singlestep;
545
546 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
547 old_singlestep = vcpu->guest_debug.singlestep;
548
549 vcpu->guest_debug.enabled = dbg->enabled;
550 if (vcpu->guest_debug.enabled) {
551 int i;
552
553 dr7 |= 0x200; /* exact */
554 for (i = 0; i < 4; ++i) {
555 if (!dbg->breakpoints[i].enabled)
556 continue;
557 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
558 dr7 |= 2 << (i*2); /* global enable */
559 dr7 |= 0 << (i*4+16); /* execution breakpoint */
560 }
561
562 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
563
564 vcpu->guest_debug.singlestep = dbg->singlestep;
565 } else {
566 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
567 vcpu->guest_debug.singlestep = 0;
568 }
569
570 if (old_singlestep && !vcpu->guest_debug.singlestep) {
571 unsigned long flags;
572
573 flags = vmcs_readl(GUEST_RFLAGS);
574 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
575 vmcs_writel(GUEST_RFLAGS, flags);
576 }
577
578 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
579 vmcs_writel(GUEST_DR7, dr7);
580
581 return 0;
582}
583
584static __init int cpu_has_kvm_support(void)
585{
586 unsigned long ecx = cpuid_ecx(1);
587 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
588}
589
590static __init int vmx_disabled_by_bios(void)
591{
592 u64 msr;
593
594 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
595 return (msr & 5) == 1; /* locked but not enabled */
596}
597
774c47f1 598static void hardware_enable(void *garbage)
6aa8b732
AK		 599{
600 int cpu = raw_smp_processor_id();
601 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
602 u64 old;
603
604 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 605 if ((old & 5) != 5)
6aa8b732
AK		 606 /* enable and lock */
607 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
608 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
609 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
610 : "memory", "cc");
611}
612
613static void hardware_disable(void *garbage)
614{
615 asm volatile (ASM_VMX_VMXOFF : : : "cc");
616}
617
618static __init void setup_vmcs_descriptor(void)
619{
620 u32 vmx_msr_low, vmx_msr_high;
621
c68876fd 622 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 623 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
624 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
625 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 626}
6aa8b732
AK		 627
628static struct vmcs *alloc_vmcs_cpu(int cpu)
629{
630 int node = cpu_to_node(cpu);
631 struct page *pages;
632 struct vmcs *vmcs;
633
634 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
635 if (!pages)
636 return NULL;
637 vmcs = page_address(pages);
638 memset(vmcs, 0, vmcs_descriptor.size);
639 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
640 return vmcs;
641}
642
643static struct vmcs *alloc_vmcs(void)
644{
d3b2c338 645 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 646}
647
648static void free_vmcs(struct vmcs *vmcs)
649{
650 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
651}
652
39959588 653static void free_kvm_area(void)
6aa8b732
AK		 654{
655 int cpu;
656
657 for_each_online_cpu(cpu)
658 free_vmcs(per_cpu(vmxarea, cpu));
659}
660
661extern struct vmcs *alloc_vmcs_cpu(int cpu);
662
663static __init int alloc_kvm_area(void)
664{
665 int cpu;
666
667 for_each_online_cpu(cpu) {
668 struct vmcs *vmcs;
669
670 vmcs = alloc_vmcs_cpu(cpu);
671 if (!vmcs) {
672 free_kvm_area();
673 return -ENOMEM;
674 }
675
676 per_cpu(vmxarea, cpu) = vmcs;
677 }
678 return 0;
679}
680
681static __init int hardware_setup(void)
682{
683 setup_vmcs_descriptor();
684 return alloc_kvm_area();
685}
686
687static __exit void hardware_unsetup(void)
688{
689 free_kvm_area();
690}
691
692static void update_exception_bitmap(struct kvm_vcpu *vcpu)
693{
694 if (vcpu->rmode.active)
695 vmcs_write32(EXCEPTION_BITMAP, ~0);
696 else
697 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
698}
699
700static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
701{
702 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
703
6af11b9e 704 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 705 vmcs_write16(sf->selector, save->selector);
706 vmcs_writel(sf->base, save->base);
707 vmcs_write32(sf->limit, save->limit);
708 vmcs_write32(sf->ar_bytes, save->ar);
709 } else {
710 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
711 << AR_DPL_SHIFT;
712 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
713 }
714}
715
716static void enter_pmode(struct kvm_vcpu *vcpu)
717{
718 unsigned long flags;
719
720 vcpu->rmode.active = 0;
721
722 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
723 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
724 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
725
726 flags = vmcs_readl(GUEST_RFLAGS);
727 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
728 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
729 vmcs_writel(GUEST_RFLAGS, flags);
730
731 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
732 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
733
734 update_exception_bitmap(vcpu);
735
736 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
737 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
738 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
739 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
740
741 vmcs_write16(GUEST_SS_SELECTOR, 0);
742 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
743
744 vmcs_write16(GUEST_CS_SELECTOR,
745 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
746 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
747}
748
749static int rmode_tss_base(struct kvm* kvm)
750{
751 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
752 return base_gfn << PAGE_SHIFT;
753}
754
755static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
756{
757 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
758
759 save->selector = vmcs_read16(sf->selector);
760 save->base = vmcs_readl(sf->base);
761 save->limit = vmcs_read32(sf->limit);
762 save->ar = vmcs_read32(sf->ar_bytes);
763 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
764 vmcs_write32(sf->limit, 0xffff);
765 vmcs_write32(sf->ar_bytes, 0xf3);
766}
767
768static void enter_rmode(struct kvm_vcpu *vcpu)
769{
770 unsigned long flags;
771
772 vcpu->rmode.active = 1;
773
774 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
775 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
776
777 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
778 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
779
780 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
781 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
782
783 flags = vmcs_readl(GUEST_RFLAGS);
784 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
785
786 flags |= IOPL_MASK | X86_EFLAGS_VM;
787
788 vmcs_writel(GUEST_RFLAGS, flags);
789 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
790 update_exception_bitmap(vcpu);
791
792 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
793 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
794 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
795
796 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 797 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 798 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
799 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 800 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
801
802 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
803 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
804 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
805 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
806}
807
05b3e0c2 808#ifdef CONFIG_X86_64
6aa8b732
AK		 809
810static void enter_lmode(struct kvm_vcpu *vcpu)
811{
812 u32 guest_tr_ar;
813
814 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
815 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
816 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
817 __FUNCTION__);
818 vmcs_write32(GUEST_TR_AR_BYTES,
819 (guest_tr_ar & ~AR_TYPE_MASK)
820 | AR_TYPE_BUSY_64_TSS);
821 }
822
823 vcpu->shadow_efer |= EFER_LMA;
824
825 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
826 vmcs_write32(VM_ENTRY_CONTROLS,
827 vmcs_read32(VM_ENTRY_CONTROLS)
828 | VM_ENTRY_CONTROLS_IA32E_MASK);
829}
830
831static void exit_lmode(struct kvm_vcpu *vcpu)
832{
833 vcpu->shadow_efer &= ~EFER_LMA;
834
835 vmcs_write32(VM_ENTRY_CONTROLS,
836 vmcs_read32(VM_ENTRY_CONTROLS)
837 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
838}
839
840#endif
841
25c4c276 842static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 843{
399badf3
AK		 844 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
845 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
846}
847
6aa8b732
AK		 848static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
849{
850 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
851 enter_pmode(vcpu);
852
853 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
854 enter_rmode(vcpu);
855
05b3e0c2 856#ifdef CONFIG_X86_64
6aa8b732
AK		 857 if (vcpu->shadow_efer & EFER_LME) {
858 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
859 enter_lmode(vcpu);
860 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
861 exit_lmode(vcpu);
862 }
863#endif
864
2ab455cc
AL		 865 if (!(cr0 & CR0_TS_MASK)) {
866 vcpu->fpu_active = 1;
867 vmcs_clear_bits(EXCEPTION_BITMAP, CR0_TS_MASK);
868 }
869
6aa8b732
AK		 870 vmcs_writel(CR0_READ_SHADOW, cr0);
871 vmcs_writel(GUEST_CR0,
872 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
873 vcpu->cr0 = cr0;
874}
875
6aa8b732
AK		 876static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
877{
878 vmcs_writel(GUEST_CR3, cr3);
2ab455cc
AL		 879
880 if (!(vcpu->cr0 & CR0_TS_MASK)) {
881 vcpu->fpu_active = 0;
882 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
883 vmcs_set_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
884 }
6aa8b732
AK		 885}
886
887static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
888{
889 vmcs_writel(CR4_READ_SHADOW, cr4);
890 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
891 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
892 vcpu->cr4 = cr4;
893}
894
05b3e0c2 895#ifdef CONFIG_X86_64
6aa8b732
AK		 896
897static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
898{
899 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
900
901 vcpu->shadow_efer = efer;
902 if (efer & EFER_LMA) {
903 vmcs_write32(VM_ENTRY_CONTROLS,
904 vmcs_read32(VM_ENTRY_CONTROLS) |
905 VM_ENTRY_CONTROLS_IA32E_MASK);
906 msr->data = efer;
907
908 } else {
909 vmcs_write32(VM_ENTRY_CONTROLS,
910 vmcs_read32(VM_ENTRY_CONTROLS) &
911 ~VM_ENTRY_CONTROLS_IA32E_MASK);
912
913 msr->data = efer & ~EFER_LME;
914 }
e38aea3e 915 setup_msrs(vcpu);
6aa8b732
AK		 916}
917
918#endif
919
920static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
921{
922 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
923
924 return vmcs_readl(sf->base);
925}
926
927static void vmx_get_segment(struct kvm_vcpu *vcpu,
928 struct kvm_segment *var, int seg)
929{
930 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
931 u32 ar;
932
933 var->base = vmcs_readl(sf->base);
934 var->limit = vmcs_read32(sf->limit);
935 var->selector = vmcs_read16(sf->selector);
936 ar = vmcs_read32(sf->ar_bytes);
937 if (ar & AR_UNUSABLE_MASK)
938 ar = 0;
939 var->type = ar & 15;
940 var->s = (ar >> 4) & 1;
941 var->dpl = (ar >> 5) & 3;
942 var->present = (ar >> 7) & 1;
943 var->avl = (ar >> 12) & 1;
944 var->l = (ar >> 13) & 1;
945 var->db = (ar >> 14) & 1;
946 var->g = (ar >> 15) & 1;
947 var->unusable = (ar >> 16) & 1;
948}
949
950static void vmx_set_segment(struct kvm_vcpu *vcpu,
951 struct kvm_segment *var, int seg)
952{
953 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
954 u32 ar;
955
956 vmcs_writel(sf->base, var->base);
957 vmcs_write32(sf->limit, var->limit);
958 vmcs_write16(sf->selector, var->selector);
038881c8
AK		 959 if (vcpu->rmode.active && var->s) {
960 /*
961 * Hack real-mode segments into vm86 compatibility.
962 */
963 if (var->base == 0xffff0000 && var->selector == 0xf000)
964 vmcs_writel(sf->base, 0xf0000);
965 ar = 0xf3;
966 } else if (var->unusable)
6aa8b732
AK		 967 ar = 1 << 16;
968 else {
969 ar = var->type & 15;
970 ar |= (var->s & 1) << 4;
971 ar |= (var->dpl & 3) << 5;
972 ar |= (var->present & 1) << 7;
973 ar |= (var->avl & 1) << 12;
974 ar |= (var->l & 1) << 13;
975 ar |= (var->db & 1) << 14;
976 ar |= (var->g & 1) << 15;
977 }
f7fbf1fd
UL		 978 if (ar == 0) /* a 0 value means unusable */
979 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 980 vmcs_write32(sf->ar_bytes, ar);
981}
982
6aa8b732
AK		 983static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
984{
985 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
986
987 *db = (ar >> 14) & 1;
988 *l = (ar >> 13) & 1;
989}
990
991static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
992{
993 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
994 dt->base = vmcs_readl(GUEST_IDTR_BASE);
995}
996
997static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
998{
999 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1000 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1001}
1002
1003static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1004{
1005 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1006 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1007}
1008
1009static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1010{
1011 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1012 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1013}
1014
1015static int init_rmode_tss(struct kvm* kvm)
1016{
1017 struct page *p1, *p2, *p3;
1018 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1019 char *page;
1020
954bbbc2
AK		 1021 p1 = gfn_to_page(kvm, fn++);
1022 p2 = gfn_to_page(kvm, fn++);
1023 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1024
1025 if (!p1 || !p2 || !p3) {
1026 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1027 return 0;
1028 }
1029
1030 page = kmap_atomic(p1, KM_USER0);
1031 memset(page, 0, PAGE_SIZE);
1032 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1033 kunmap_atomic(page, KM_USER0);
1034
1035 page = kmap_atomic(p2, KM_USER0);
1036 memset(page, 0, PAGE_SIZE);
1037 kunmap_atomic(page, KM_USER0);
1038
1039 page = kmap_atomic(p3, KM_USER0);
1040 memset(page, 0, PAGE_SIZE);
1041 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1042 kunmap_atomic(page, KM_USER0);
1043
1044 return 1;
1045}
1046
1047static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1048{
1049 u32 msr_high, msr_low;
1050
1051 rdmsr(msr, msr_low, msr_high);
1052
1053 val &= msr_high;
1054 val |= msr_low;
1055 vmcs_write32(vmcs_field, val);
1056}
1057
1058static void seg_setup(int seg)
1059{
1060 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1061
1062 vmcs_write16(sf->selector, 0);
1063 vmcs_writel(sf->base, 0);
1064 vmcs_write32(sf->limit, 0xffff);
1065 vmcs_write32(sf->ar_bytes, 0x93);
1066}
1067
1068/*
1069 * Sets up the vmcs for emulated real mode.
1070 */
1071static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1072{
1073 u32 host_sysenter_cs;
1074 u32 junk;
1075 unsigned long a;
1076 struct descriptor_table dt;
1077 int i;
1078 int ret = 0;
6aa8b732
AK		 1079 extern asmlinkage void kvm_vmx_return(void);
1080
1081 if (!init_rmode_tss(vcpu->kvm)) {
1082 ret = -ENOMEM;
1083 goto out;
1084 }
1085
1086 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1087 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1088 vcpu->cr8 = 0;
1089 vcpu->apic_base = 0xfee00000 |
1090 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1091 MSR_IA32_APICBASE_ENABLE;
1092
1093 fx_init(vcpu);
1094
1095 /*
1096 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1097 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1098 */
1099 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1100 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1101 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1102 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1103
1104 seg_setup(VCPU_SREG_DS);
1105 seg_setup(VCPU_SREG_ES);
1106 seg_setup(VCPU_SREG_FS);
1107 seg_setup(VCPU_SREG_GS);
1108 seg_setup(VCPU_SREG_SS);
1109
1110 vmcs_write16(GUEST_TR_SELECTOR, 0);
1111 vmcs_writel(GUEST_TR_BASE, 0);
1112 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1113 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1114
1115 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1116 vmcs_writel(GUEST_LDTR_BASE, 0);
1117 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1118 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1119
1120 vmcs_write32(GUEST_SYSENTER_CS, 0);
1121 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1122 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1123
1124 vmcs_writel(GUEST_RFLAGS, 0x02);
1125 vmcs_writel(GUEST_RIP, 0xfff0);
1126 vmcs_writel(GUEST_RSP, 0);
1127
6aa8b732
AK		 1128 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1129 vmcs_writel(GUEST_DR7, 0x400);
1130
1131 vmcs_writel(GUEST_GDTR_BASE, 0);
1132 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1133
1134 vmcs_writel(GUEST_IDTR_BASE, 0);
1135 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1136
1137 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1138 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1139 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1140
1141 /* I/O */
fdef3ad1
HQ		 1142 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1143 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1144
1145 guest_write_tsc(0);
1146
1147 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1148
1149 /* Special registers */
1150 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1151
1152 /* Control */
c68876fd 1153 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1154 PIN_BASED_VM_EXEC_CONTROL,
1155 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1156 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1157 );
c68876fd 1158 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1159 CPU_BASED_VM_EXEC_CONTROL,
1160 CPU_BASED_HLT_EXITING /* 20.6.2 */
1161 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1162 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
fdef3ad1 1163 | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */
6aa8b732
AK		 1164 | CPU_BASED_MOV_DR_EXITING
1165 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1166 );
1167
1168 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1169 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1170 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1171 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1172
1173 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1174 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1175 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1176
1177 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1178 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1179 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1180 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1181 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1182 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1183#ifdef CONFIG_X86_64
6aa8b732
AK		 1184 rdmsrl(MSR_FS_BASE, a);
1185 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1186 rdmsrl(MSR_GS_BASE, a);
1187 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1188#else
1189 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1190 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1191#endif
1192
1193 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1194
1195 get_idt(&dt);
1196 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1197
1198
1199 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1200
1201 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1202 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1203 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1204 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1205 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1206 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1207
6aa8b732
AK		 1208 for (i = 0; i < NR_VMX_MSR; ++i) {
1209 u32 index = vmx_msr_index[i];
1210 u32 data_low, data_high;
1211 u64 data;
1212 int j = vcpu->nmsrs;
1213
1214 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1215 continue;
432bd6cb
AK		 1216 if (wrmsr_safe(index, data_low, data_high) < 0)
1217 continue;
6aa8b732
AK		 1218 data = data_low | ((u64)data_high << 32);
1219 vcpu->host_msrs[j].index = index;
1220 vcpu->host_msrs[j].reserved = 0;
1221 vcpu->host_msrs[j].data = data;
1222 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
2345df8c
AK		 1223#ifdef CONFIG_X86_64
1224 if (index == MSR_KERNEL_GS_BASE)
1225 msr_offset_kernel_gs_base = j;
1226#endif
6aa8b732
AK		 1227 ++vcpu->nmsrs;
1228 }
6aa8b732 1229
e38aea3e
AK		 1230 setup_msrs(vcpu);
1231
c68876fd 1232 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732 1233 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
6aa8b732
AK		 1234
1235 /* 22.2.1, 20.8.1 */
c68876fd 1236 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1237 VM_ENTRY_CONTROLS, 0);
1238 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1239
3b99ab24 1240#ifdef CONFIG_X86_64
6aa8b732
AK		 1241 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1242 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1243#endif
6aa8b732 1244
25c4c276 1245 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1246 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1247
1248 vcpu->cr0 = 0x60000010;
1249 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1250 vmx_set_cr4(vcpu, 0);
05b3e0c2 1251#ifdef CONFIG_X86_64
6aa8b732
AK		 1252 vmx_set_efer(vcpu, 0);
1253#endif
1254
1255 return 0;
1256
6aa8b732
AK		 1257out:
1258 return ret;
1259}
1260
1261static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1262{
1263 u16 ent[2];
1264 u16 cs;
1265 u16 ip;
1266 unsigned long flags;
1267 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1268 u16 sp = vmcs_readl(GUEST_RSP);
1269 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1270
3964994b 1271 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1272 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1273 __FUNCTION__,
1274 vmcs_readl(GUEST_RSP),
1275 vmcs_readl(GUEST_SS_BASE),
1276 vmcs_read32(GUEST_SS_LIMIT));
1277 return;
1278 }
1279
1280 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1281 sizeof(ent)) {
1282 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1283 return;
1284 }
1285
1286 flags = vmcs_readl(GUEST_RFLAGS);
1287 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1288 ip = vmcs_readl(GUEST_RIP);
1289
1290
1291 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1292 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1293 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1294 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1295 return;
1296 }
1297
1298 vmcs_writel(GUEST_RFLAGS, flags &
1299 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1300 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1301 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1302 vmcs_writel(GUEST_RIP, ent[0]);
1303 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1304}
1305
1306static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1307{
1308 int word_index = __ffs(vcpu->irq_summary);
1309 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1310 int irq = word_index * BITS_PER_LONG + bit_index;
1311
1312 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1313 if (!vcpu->irq_pending[word_index])
1314 clear_bit(word_index, &vcpu->irq_summary);
1315
1316 if (vcpu->rmode.active) {
1317 inject_rmode_irq(vcpu, irq);
1318 return;
1319 }
1320 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1321 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1322}
1323
c1150d8c
DL		 1324
1325static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1326 struct kvm_run *kvm_run)
6aa8b732 1327{
c1150d8c
DL		 1328 u32 cpu_based_vm_exec_control;
1329
1330 vcpu->interrupt_window_open =
1331 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1332 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1333
1334 if (vcpu->interrupt_window_open &&
1335 vcpu->irq_summary &&
1336 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1337 /*
c1150d8c 1338 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1339 */
1340 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1341
1342 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1343 if (!vcpu->interrupt_window_open &&
1344 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1345 /*
1346 * Interrupts blocked. Wait for unblock.
1347 */
c1150d8c
DL		 1348 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1349 else
1350 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1351 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1352}
1353
1354static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1355{
1356 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1357
1358 set_debugreg(dbg->bp[0], 0);
1359 set_debugreg(dbg->bp[1], 1);
1360 set_debugreg(dbg->bp[2], 2);
1361 set_debugreg(dbg->bp[3], 3);
1362
1363 if (dbg->singlestep) {
1364 unsigned long flags;
1365
1366 flags = vmcs_readl(GUEST_RFLAGS);
1367 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1368 vmcs_writel(GUEST_RFLAGS, flags);
1369 }
1370}
1371
1372static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1373 int vec, u32 err_code)
1374{
1375 if (!vcpu->rmode.active)
1376 return 0;
1377
1378 if (vec == GP_VECTOR && err_code == 0)
1379 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1380 return 1;
1381 return 0;
1382}
1383
1384static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1385{
1386 u32 intr_info, error_code;
1387 unsigned long cr2, rip;
1388 u32 vect_info;
1389 enum emulation_result er;
e2dec939 1390 int r;
6aa8b732
AK		 1391
1392 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1393 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1394
1395 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1396 !is_page_fault(intr_info)) {
1397 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1398 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1399 }
1400
1401 if (is_external_interrupt(vect_info)) {
1402 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1403 set_bit(irq, vcpu->irq_pending);
1404 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1405 }
1406
1407 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1408 asm ("int $2");
1409 return 1;
1410 }
2ab455cc
AL		 1411
1412 if (is_no_device(intr_info)) {
1413 vcpu->fpu_active = 1;
1414 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1415 if (!(vcpu->cr0 & CR0_TS_MASK))
1416 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1417 return 1;
1418 }
1419
6aa8b732
AK		 1420 error_code = 0;
1421 rip = vmcs_readl(GUEST_RIP);
1422 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1423 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1424 if (is_page_fault(intr_info)) {
1425 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1426
1427 spin_lock(&vcpu->kvm->lock);
e2dec939
AK		 1428 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1429 if (r < 0) {
1430 spin_unlock(&vcpu->kvm->lock);
1431 return r;
1432 }
1433 if (!r) {
6aa8b732
AK		 1434 spin_unlock(&vcpu->kvm->lock);
1435 return 1;
1436 }
1437
1438 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1439 spin_unlock(&vcpu->kvm->lock);
1440
1441 switch (er) {
1442 case EMULATE_DONE:
1443 return 1;
1444 case EMULATE_DO_MMIO:
1165f5fe 1445 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1446 kvm_run->exit_reason = KVM_EXIT_MMIO;
1447 return 0;
1448 case EMULATE_FAIL:
1449 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1450 break;
1451 default:
1452 BUG();
1453 }
1454 }
1455
1456 if (vcpu->rmode.active &&
1457 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1458 error_code))
1459 return 1;
1460
1461 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1462 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1463 return 0;
1464 }
1465 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1466 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1467 kvm_run->ex.error_code = error_code;
1468 return 0;
1469}
1470
1471static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1472 struct kvm_run *kvm_run)
1473{
1165f5fe 1474 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1475 return 1;
1476}
1477
988ad74f
AK		 1478static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1479{
1480 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1481 return 0;
1482}
6aa8b732 1483
039576c0 1484static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
6aa8b732
AK		 1485{
1486 u64 inst;
1487 gva_t rip;
1488 int countr_size;
1489 int i, n;
1490
1491 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1492 countr_size = 2;
1493 } else {
1494 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1495
1496 countr_size = (cs_ar & AR_L_MASK) ? 8:
1497 (cs_ar & AR_DB_MASK) ? 4: 2;
1498 }
1499
1500 rip = vmcs_readl(GUEST_RIP);
1501 if (countr_size != 8)
1502 rip += vmcs_readl(GUEST_CS_BASE);
1503
1504 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1505
1506 for (i = 0; i < n; i++) {
1507 switch (((u8*)&inst)[i]) {
1508 case 0xf0:
1509 case 0xf2:
1510 case 0xf3:
1511 case 0x2e:
1512 case 0x36:
1513 case 0x3e:
1514 case 0x26:
1515 case 0x64:
1516 case 0x65:
1517 case 0x66:
1518 break;
1519 case 0x67:
1520 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1521 default:
1522 goto done;
1523 }
1524 }
1525 return 0;
1526done:
1527 countr_size *= 8;
1528 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
039576c0 1529 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
6aa8b732
AK		 1530 return 1;
1531}
1532
1533static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1534{
1535 u64 exit_qualification;
039576c0
AK		 1536 int size, down, in, string, rep;
1537 unsigned port;
1538 unsigned long count;
1539 gva_t address;
6aa8b732 1540
1165f5fe 1541 ++vcpu->stat.io_exits;
6aa8b732 1542 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0
AK		 1543 in = (exit_qualification & 8) != 0;
1544 size = (exit_qualification & 7) + 1;
1545 string = (exit_qualification & 16) != 0;
1546 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1547 count = 1;
1548 rep = (exit_qualification & 32) != 0;
1549 port = exit_qualification >> 16;
1550 address = 0;
1551 if (string) {
1552 if (rep && !get_io_count(vcpu, &count))
6aa8b732 1553 return 1;
039576c0
AK		 1554 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1555 }
1556 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1557 address, rep, port);
6aa8b732
AK		 1558}
1559
102d8325
IM		 1560static void
1561vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1562{
1563 /*
1564 * Patch in the VMCALL instruction:
1565 */
1566 hypercall[0] = 0x0f;
1567 hypercall[1] = 0x01;
1568 hypercall[2] = 0xc1;
1569 hypercall[3] = 0xc3;
1570}
1571
6aa8b732
AK		 1572static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1573{
1574 u64 exit_qualification;
1575 int cr;
1576 int reg;
1577
1578 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1579 cr = exit_qualification & 15;
1580 reg = (exit_qualification >> 8) & 15;
1581 switch ((exit_qualification >> 4) & 3) {
1582 case 0: /* mov to cr */
1583 switch (cr) {
1584 case 0:
1585 vcpu_load_rsp_rip(vcpu);
1586 set_cr0(vcpu, vcpu->regs[reg]);
1587 skip_emulated_instruction(vcpu);
1588 return 1;
1589 case 3:
1590 vcpu_load_rsp_rip(vcpu);
1591 set_cr3(vcpu, vcpu->regs[reg]);
1592 skip_emulated_instruction(vcpu);
1593 return 1;
1594 case 4:
1595 vcpu_load_rsp_rip(vcpu);
1596 set_cr4(vcpu, vcpu->regs[reg]);
1597 skip_emulated_instruction(vcpu);
1598 return 1;
1599 case 8:
1600 vcpu_load_rsp_rip(vcpu);
1601 set_cr8(vcpu, vcpu->regs[reg]);
1602 skip_emulated_instruction(vcpu);
1603 return 1;
1604 };
1605 break;
25c4c276
AL		 1606 case 2: /* clts */
1607 vcpu_load_rsp_rip(vcpu);
2ab455cc
AL		 1608 vcpu->fpu_active = 1;
1609 vmcs_clear_bits(EXCEPTION_BITMAP, 1 << NM_VECTOR);
1610 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
1611 vcpu->cr0 &= ~CR0_TS_MASK;
1612 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
25c4c276
AL		 1613 skip_emulated_instruction(vcpu);
1614 return 1;
6aa8b732
AK		 1615 case 1: /*mov from cr*/
1616 switch (cr) {
1617 case 3:
1618 vcpu_load_rsp_rip(vcpu);
1619 vcpu->regs[reg] = vcpu->cr3;
1620 vcpu_put_rsp_rip(vcpu);
1621 skip_emulated_instruction(vcpu);
1622 return 1;
1623 case 8:
6aa8b732
AK		 1624 vcpu_load_rsp_rip(vcpu);
1625 vcpu->regs[reg] = vcpu->cr8;
1626 vcpu_put_rsp_rip(vcpu);
1627 skip_emulated_instruction(vcpu);
1628 return 1;
1629 }
1630 break;
1631 case 3: /* lmsw */
1632 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1633
1634 skip_emulated_instruction(vcpu);
1635 return 1;
1636 default:
1637 break;
1638 }
1639 kvm_run->exit_reason = 0;
1640 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1641 (int)(exit_qualification >> 4) & 3, cr);
1642 return 0;
1643}
1644
1645static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1646{
1647 u64 exit_qualification;
1648 unsigned long val;
1649 int dr, reg;
1650
1651 /*
1652 * FIXME: this code assumes the host is debugging the guest.
1653 * need to deal with guest debugging itself too.
1654 */
1655 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1656 dr = exit_qualification & 7;
1657 reg = (exit_qualification >> 8) & 15;
1658 vcpu_load_rsp_rip(vcpu);
1659 if (exit_qualification & 16) {
1660 /* mov from dr */
1661 switch (dr) {
1662 case 6:
1663 val = 0xffff0ff0;
1664 break;
1665 case 7:
1666 val = 0x400;
1667 break;
1668 default:
1669 val = 0;
1670 }
1671 vcpu->regs[reg] = val;
1672 } else {
1673 /* mov to dr */
1674 }
1675 vcpu_put_rsp_rip(vcpu);
1676 skip_emulated_instruction(vcpu);
1677 return 1;
1678}
1679
1680static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1681{
06465c5a
AK		 1682 kvm_emulate_cpuid(vcpu);
1683 return 1;
6aa8b732
AK		 1684}
1685
1686static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1687{
1688 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1689 u64 data;
1690
1691 if (vmx_get_msr(vcpu, ecx, &data)) {
1692 vmx_inject_gp(vcpu, 0);
1693 return 1;
1694 }
1695
1696 /* FIXME: handling of bits 32:63 of rax, rdx */
1697 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1698 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1699 skip_emulated_instruction(vcpu);
1700 return 1;
1701}
1702
1703static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1704{
1705 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1706 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1707 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1708
1709 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1710 vmx_inject_gp(vcpu, 0);
1711 return 1;
1712 }
1713
1714 skip_emulated_instruction(vcpu);
1715 return 1;
1716}
1717
c1150d8c
DL		 1718static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1719 struct kvm_run *kvm_run)
1720{
1721 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1722 kvm_run->cr8 = vcpu->cr8;
1723 kvm_run->apic_base = vcpu->apic_base;
1724 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1725 vcpu->irq_summary == 0);
1726}
1727
6aa8b732
AK		 1728static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1729 struct kvm_run *kvm_run)
1730{
c1150d8c
DL		 1731 /*
1732 * If the user space waits to inject interrupts, exit as soon as
1733 * possible
1734 */
1735 if (kvm_run->request_interrupt_window &&
022a9308 1736 !vcpu->irq_summary) {
c1150d8c 1737 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 1738 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1739 return 0;
1740 }
6aa8b732
AK		 1741 return 1;
1742}
1743
1744static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1745{
1746 skip_emulated_instruction(vcpu);
c1150d8c 1747 if (vcpu->irq_summary)
6aa8b732
AK		 1748 return 1;
1749
1750 kvm_run->exit_reason = KVM_EXIT_HLT;
1165f5fe 1751 ++vcpu->stat.halt_exits;
6aa8b732
AK		 1752 return 0;
1753}
1754
c21415e8
IM		 1755static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1756{
510043da 1757 skip_emulated_instruction(vcpu);
270fd9b9 1758 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 1759}
1760
6aa8b732
AK		 1761/*
1762 * The exit handlers return 1 if the exit was handled fully and guest execution
1763 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1764 * to be done to userspace and return 0.
1765 */
1766static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1767 struct kvm_run *kvm_run) = {
1768 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1769 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 1770 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 1771 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 1772 [EXIT_REASON_CR_ACCESS] = handle_cr,
1773 [EXIT_REASON_DR_ACCESS] = handle_dr,
1774 [EXIT_REASON_CPUID] = handle_cpuid,
1775 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1776 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1777 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1778 [EXIT_REASON_HLT] = handle_halt,
c21415e8 1779 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 1780};
1781
1782static const int kvm_vmx_max_exit_handlers =
1783 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1784
1785/*
1786 * The guest has exited. See if we can fix it or if we need userspace
1787 * assistance.
1788 */
1789static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1790{
1791 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1792 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1793
1794 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1795 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1796 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1797 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 1798 if (exit_reason < kvm_vmx_max_exit_handlers
1799 && kvm_vmx_exit_handlers[exit_reason])
1800 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1801 else {
1802 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1803 kvm_run->hw.hardware_exit_reason = exit_reason;
1804 }
1805 return 0;
1806}
1807
c1150d8c
DL		 1808/*
1809 * Check if userspace requested an interrupt window, and that the
1810 * interrupt window is open.
1811 *
1812 * No need to exit to userspace if we already have an interrupt queued.
1813 */
1814static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1815 struct kvm_run *kvm_run)
1816{
1817 return (!vcpu->irq_summary &&
1818 kvm_run->request_interrupt_window &&
1819 vcpu->interrupt_window_open &&
1820 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1821}
1822
6aa8b732
AK		 1823static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1824{
1825 u8 fail;
1826 u16 fs_sel, gs_sel, ldt_sel;
1827 int fs_gs_ldt_reload_needed;
e2dec939 1828 int r;
6aa8b732 1829
e6adf283 1830preempted:
6aa8b732
AK		 1831 /*
1832 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1833 * allow segment selectors with cpl > 0 or ti == 1.
1834 */
6aa8b732 1835 ldt_sel = read_ldt();
62135845
AK		 1836 fs_gs_ldt_reload_needed = ldt_sel;
1837 fs_sel = read_fs();
1838 if (!(fs_sel & 7))
6aa8b732 1839 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
62135845 1840 else {
6aa8b732 1841 vmcs_write16(HOST_FS_SELECTOR, 0);
62135845
AK		 1842 fs_gs_ldt_reload_needed = 1;
1843 }
1844 gs_sel = read_gs();
1845 if (!(gs_sel & 7))
1846 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1847 else {
6aa8b732 1848 vmcs_write16(HOST_GS_SELECTOR, 0);
62135845 1849 fs_gs_ldt_reload_needed = 1;
6aa8b732
AK		 1850 }
1851
05b3e0c2 1852#ifdef CONFIG_X86_64
6aa8b732
AK		 1853 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1854 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1855#else
1856 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1857 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1858#endif
1859
cccf748b
AK		 1860 if (!vcpu->mmio_read_completed)
1861 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1862
1863 if (vcpu->guest_debug.enabled)
1864 kvm_guest_debug_pre(vcpu);
1865
2345df8c 1866#ifdef CONFIG_X86_64
e38aea3e
AK		 1867 if (is_long_mode(vcpu)) {
1868 save_msrs(vcpu->host_msrs + msr_offset_kernel_gs_base, 1);
1869 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1870 }
2345df8c 1871#endif
6aa8b732 1872
e6adf283
AK		 1873again:
1874 kvm_load_guest_fpu(vcpu);
1875
1876 /*
1877 * Loading guest fpu may have cleared host cr0.ts
1878 */
1879 vmcs_writel(HOST_CR0, read_cr0());
1880
6aa8b732
AK		 1881 asm (
1882 /* Store host registers */
1883 "pushf \n\t"
05b3e0c2 1884#ifdef CONFIG_X86_64
6aa8b732
AK		 1885 "push %%rax; push %%rbx; push %%rdx;"
1886 "push %%rsi; push %%rdi; push %%rbp;"
1887 "push %%r8; push %%r9; push %%r10; push %%r11;"
1888 "push %%r12; push %%r13; push %%r14; push %%r15;"
1889 "push %%rcx \n\t"
1890 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1891#else
1892 "pusha; push %%ecx \n\t"
1893 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1894#endif
1895 /* Check if vmlaunch of vmresume is needed */
1896 "cmp $0, %1 \n\t"
1897 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1898#ifdef CONFIG_X86_64
6aa8b732
AK		 1899 "mov %c[cr2](%3), %%rax \n\t"
1900 "mov %%rax, %%cr2 \n\t"
1901 "mov %c[rax](%3), %%rax \n\t"
1902 "mov %c[rbx](%3), %%rbx \n\t"
1903 "mov %c[rdx](%3), %%rdx \n\t"
1904 "mov %c[rsi](%3), %%rsi \n\t"
1905 "mov %c[rdi](%3), %%rdi \n\t"
1906 "mov %c[rbp](%3), %%rbp \n\t"
1907 "mov %c[r8](%3), %%r8 \n\t"
1908 "mov %c[r9](%3), %%r9 \n\t"
1909 "mov %c[r10](%3), %%r10 \n\t"
1910 "mov %c[r11](%3), %%r11 \n\t"
1911 "mov %c[r12](%3), %%r12 \n\t"
1912 "mov %c[r13](%3), %%r13 \n\t"
1913 "mov %c[r14](%3), %%r14 \n\t"
1914 "mov %c[r15](%3), %%r15 \n\t"
1915 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1916#else
1917 "mov %c[cr2](%3), %%eax \n\t"
1918 "mov %%eax, %%cr2 \n\t"
1919 "mov %c[rax](%3), %%eax \n\t"
1920 "mov %c[rbx](%3), %%ebx \n\t"
1921 "mov %c[rdx](%3), %%edx \n\t"
1922 "mov %c[rsi](%3), %%esi \n\t"
1923 "mov %c[rdi](%3), %%edi \n\t"
1924 "mov %c[rbp](%3), %%ebp \n\t"
1925 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1926#endif
1927 /* Enter guest mode */
1928 "jne launched \n\t"
1929 ASM_VMX_VMLAUNCH "\n\t"
1930 "jmp kvm_vmx_return \n\t"
1931 "launched: " ASM_VMX_VMRESUME "\n\t"
1932 ".globl kvm_vmx_return \n\t"
1933 "kvm_vmx_return: "
1934 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1935#ifdef CONFIG_X86_64
96958231 1936 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 1937 "mov %%rax, %c[rax](%3) \n\t"
1938 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 1939 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 1940 "mov %%rdx, %c[rdx](%3) \n\t"
1941 "mov %%rsi, %c[rsi](%3) \n\t"
1942 "mov %%rdi, %c[rdi](%3) \n\t"
1943 "mov %%rbp, %c[rbp](%3) \n\t"
1944 "mov %%r8, %c[r8](%3) \n\t"
1945 "mov %%r9, %c[r9](%3) \n\t"
1946 "mov %%r10, %c[r10](%3) \n\t"
1947 "mov %%r11, %c[r11](%3) \n\t"
1948 "mov %%r12, %c[r12](%3) \n\t"
1949 "mov %%r13, %c[r13](%3) \n\t"
1950 "mov %%r14, %c[r14](%3) \n\t"
1951 "mov %%r15, %c[r15](%3) \n\t"
1952 "mov %%cr2, %%rax \n\t"
1953 "mov %%rax, %c[cr2](%3) \n\t"
96958231 1954 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 1955
1956 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1957 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1958 "pop %%rbp; pop %%rdi; pop %%rsi;"
1959 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1960#else
96958231 1961 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 1962 "mov %%eax, %c[rax](%3) \n\t"
1963 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 1964 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 1965 "mov %%edx, %c[rdx](%3) \n\t"
1966 "mov %%esi, %c[rsi](%3) \n\t"
1967 "mov %%edi, %c[rdi](%3) \n\t"
1968 "mov %%ebp, %c[rbp](%3) \n\t"
1969 "mov %%cr2, %%eax \n\t"
1970 "mov %%eax, %c[cr2](%3) \n\t"
96958231 1971 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 1972
1973 "pop %%ecx; popa \n\t"
1974#endif
1975 "setbe %0 \n\t"
1976 "popf \n\t"
e0015489 1977 : "=q" (fail)
6aa8b732
AK		 1978 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1979 "c"(vcpu),
1980 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1981 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1982 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1983 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1984 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1985 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1986 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 1987#ifdef CONFIG_X86_64
6aa8b732
AK		 1988 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1989 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1990 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1991 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1992 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1993 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1994 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1995 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1996#endif
1997 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1998 : "cc", "memory" );
1999
1165f5fe 2000 ++vcpu->stat.exits;
6aa8b732 2001
c1150d8c 2002 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2003
6aa8b732 2004 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6aa8b732 2005
05e0c8c3 2006 if (unlikely(fail)) {
8eb7d334
AK		 2007 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2008 kvm_run->fail_entry.hardware_entry_failure_reason
2009 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2010 r = 0;
05e0c8c3
AK		 2011 goto out;
2012 }
2013 /*
2014 * Profile KVM exit RIPs:
2015 */
2016 if (unlikely(prof_on == KVM_PROFILING))
2017 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2018
2019 vcpu->launched = 1;
2020 r = kvm_handle_exit(kvm_run, vcpu);
2021 if (r > 0) {
2022 /* Give scheduler a change to reschedule. */
2023 if (signal_pending(current)) {
2024 r = -EINTR;
2025 kvm_run->exit_reason = KVM_EXIT_INTR;
2026 ++vcpu->stat.signal_exits;
2027 goto out;
2028 }
2029
2030 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2031 r = -EINTR;
2032 kvm_run->exit_reason = KVM_EXIT_INTR;
2033 ++vcpu->stat.request_irq_exits;
2034 goto out;
2035 }
2036 if (!need_resched()) {
2037 ++vcpu->stat.light_exits;
2038 goto again;
6aa8b732
AK		 2039 }
2040 }
c1150d8c 2041
e6adf283 2042out:
e6adf283
AK		 2043 if (fs_gs_ldt_reload_needed) {
2044 load_ldt(ldt_sel);
2045 load_fs(fs_sel);
2046 /*
2047 * If we have to reload gs, we must take care to
2048 * preserve our gs base.
2049 */
2050 local_irq_disable();
2051 load_gs(gs_sel);
2052#ifdef CONFIG_X86_64
2053 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
2054#endif
2055 local_irq_enable();
2056
2057 reload_tss();
2058 }
2059#ifdef CONFIG_X86_64
2060 if (is_long_mode(vcpu)) {
2061 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
2062 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
2063 }
2064#endif
2065
2066 if (r > 0) {
2067 kvm_resched(vcpu);
2068 goto preempted;
2069 }
2070
c1150d8c 2071 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2072 return r;
6aa8b732
AK		 2073}
2074
2075static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2076{
2077 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
2078}
2079
2080static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2081 unsigned long addr,
2082 u32 err_code)
2083{
2084 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2085
1165f5fe 2086 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2087
2088 if (is_page_fault(vect_info)) {
2089 printk(KERN_DEBUG "inject_page_fault: "
2090 "double fault 0x%lx @ 0x%lx\n",
2091 addr, vmcs_readl(GUEST_RIP));
2092 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2094 DF_VECTOR |
2095 INTR_TYPE_EXCEPTION |
2096 INTR_INFO_DELIEVER_CODE_MASK |
2097 INTR_INFO_VALID_MASK);
2098 return;
2099 }
2100 vcpu->cr2 = addr;
2101 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2102 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2103 PF_VECTOR |
2104 INTR_TYPE_EXCEPTION |
2105 INTR_INFO_DELIEVER_CODE_MASK |
2106 INTR_INFO_VALID_MASK);
2107
2108}
2109
2110static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2111{
2112 if (vcpu->vmcs) {
2113 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2114 free_vmcs(vcpu->vmcs);
2115 vcpu->vmcs = NULL;
2116 }
2117}
2118
2119static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2120{
2121 vmx_free_vmcs(vcpu);
2122}
2123
2124static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2125{
2126 struct vmcs *vmcs;
2127
965b58a5
IM		 2128 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2129 if (!vcpu->guest_msrs)
2130 return -ENOMEM;
2131
2132 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2133 if (!vcpu->host_msrs)
2134 goto out_free_guest_msrs;
2135
6aa8b732
AK		 2136 vmcs = alloc_vmcs();
2137 if (!vmcs)
965b58a5
IM		 2138 goto out_free_msrs;
2139
6aa8b732
AK		 2140 vmcs_clear(vmcs);
2141 vcpu->vmcs = vmcs;
2142 vcpu->launched = 0;
2ab455cc 2143 vcpu->fpu_active = 1;
965b58a5 2144
6aa8b732 2145 return 0;
965b58a5
IM		 2146
2147out_free_msrs:
2148 kfree(vcpu->host_msrs);
2149 vcpu->host_msrs = NULL;
2150
2151out_free_guest_msrs:
2152 kfree(vcpu->guest_msrs);
2153 vcpu->guest_msrs = NULL;
2154
2155 return -ENOMEM;
6aa8b732
AK		 2156}
2157
2158static struct kvm_arch_ops vmx_arch_ops = {
2159 .cpu_has_kvm_support = cpu_has_kvm_support,
2160 .disabled_by_bios = vmx_disabled_by_bios,
2161 .hardware_setup = hardware_setup,
2162 .hardware_unsetup = hardware_unsetup,
2163 .hardware_enable = hardware_enable,
2164 .hardware_disable = hardware_disable,
2165
2166 .vcpu_create = vmx_create_vcpu,
2167 .vcpu_free = vmx_free_vcpu,
2168
2169 .vcpu_load = vmx_vcpu_load,
2170 .vcpu_put = vmx_vcpu_put,
774c47f1 2171 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2172
2173 .set_guest_debug = set_guest_debug,
2174 .get_msr = vmx_get_msr,
2175 .set_msr = vmx_set_msr,
2176 .get_segment_base = vmx_get_segment_base,
2177 .get_segment = vmx_get_segment,
2178 .set_segment = vmx_set_segment,
6aa8b732 2179 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2180 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2181 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2182 .set_cr3 = vmx_set_cr3,
2183 .set_cr4 = vmx_set_cr4,
05b3e0c2 2184#ifdef CONFIG_X86_64
6aa8b732
AK		 2185 .set_efer = vmx_set_efer,
2186#endif
2187 .get_idt = vmx_get_idt,
2188 .set_idt = vmx_set_idt,
2189 .get_gdt = vmx_get_gdt,
2190 .set_gdt = vmx_set_gdt,
2191 .cache_regs = vcpu_load_rsp_rip,
2192 .decache_regs = vcpu_put_rsp_rip,
2193 .get_rflags = vmx_get_rflags,
2194 .set_rflags = vmx_set_rflags,
2195
2196 .tlb_flush = vmx_flush_tlb,
2197 .inject_page_fault = vmx_inject_page_fault,
2198
2199 .inject_gp = vmx_inject_gp,
2200
2201 .run = vmx_vcpu_run,
2202 .skip_emulated_instruction = skip_emulated_instruction,
2203 .vcpu_setup = vmx_vcpu_setup,
102d8325 2204 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2205};
2206
2207static int __init vmx_init(void)
2208{
fdef3ad1
HQ		 2209 void *iova;
2210 int r;
2211
2212 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2213 if (!vmx_io_bitmap_a)
2214 return -ENOMEM;
2215
2216 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2217 if (!vmx_io_bitmap_b) {
2218 r = -ENOMEM;
2219 goto out;
2220 }
2221
2222 /*
2223 * Allow direct access to the PC debug port (it is often used for I/O
2224 * delays, but the vmexits simply slow things down).
2225 */
2226 iova = kmap(vmx_io_bitmap_a);
2227 memset(iova, 0xff, PAGE_SIZE);
2228 clear_bit(0x80, iova);
2229 kunmap(iova);
2230
2231 iova = kmap(vmx_io_bitmap_b);
2232 memset(iova, 0xff, PAGE_SIZE);
2233 kunmap(iova);
2234
2235 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2236 if (r)
2237 goto out1;
2238
2239 return 0;
2240
2241out1:
2242 __free_page(vmx_io_bitmap_b);
2243out:
2244 __free_page(vmx_io_bitmap_a);
2245 return r;
6aa8b732
AK		 2246}
2247
2248static void __exit vmx_exit(void)
2249{
fdef3ad1
HQ		 2250 __free_page(vmx_io_bitmap_b);
2251 __free_page(vmx_io_bitmap_a);
2252
6aa8b732
AK		 2253 kvm_exit_arch();
2254}
2255
2256module_init(vmx_init)
2257module_exit(vmx_exit)
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