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KVM: Consolidate XX_VECTOR defines
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
6aa8b732 19#include "vmx.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
6aa8b732 34
4ecac3fd
AK		 35#define __ex(x) __kvm_handle_fault_on_reboot(x)
36
6aa8b732
AK		 37MODULE_AUTHOR("Qumranet");
38MODULE_LICENSE("GPL");
39
c7addb90
AK		 40static int bypass_guest_pf = 1;
41module_param(bypass_guest_pf, bool, 0);
42
2384d2b3
SY		 43static int enable_vpid = 1;
44module_param(enable_vpid, bool, 0);
45
4c9fc8ef
AK		 46static int flexpriority_enabled = 1;
47module_param(flexpriority_enabled, bool, 0);
48
1439442c 49static int enable_ept = 1;
d56f546d
SY		 50module_param(enable_ept, bool, 0);
51
a2fa3e9f
GH		 52struct vmcs {
53 u32 revision_id;
54 u32 abort;
55 char data[0];
56};
57
58struct vcpu_vmx {
fb3f0f51 59 struct kvm_vcpu vcpu;
543e4243 60 struct list_head local_vcpus_link;
a2fa3e9f 61 int launched;
29bd8a78 62 u8 fail;
1155f76a 63 u32 idt_vectoring_info;
a2fa3e9f
GH		 64 struct kvm_msr_entry *guest_msrs;
65 struct kvm_msr_entry *host_msrs;
66 int nmsrs;
67 int save_nmsrs;
68 int msr_offset_efer;
69#ifdef CONFIG_X86_64
70 int msr_offset_kernel_gs_base;
71#endif
72 struct vmcs *vmcs;
73 struct {
74 int loaded;
75 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 76 int gs_ldt_reload_needed;
77 int fs_reload_needed;
51c6cf66 78 int guest_efer_loaded;
d77c26fc 79 } host_state;
9c8cba37
AK		 80 struct {
81 struct {
82 bool pending;
83 u8 vector;
84 unsigned rip;
85 } irq;
86 } rmode;
2384d2b3 87 int vpid;
a2fa3e9f
GH		 88};
89
90static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
91{
fb3f0f51 92 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 93}
94
b7ebfb05 95static int init_rmode(struct kvm *kvm);
4e1096d2 96static u64 construct_eptp(unsigned long root_hpa);
75880a01 97
6aa8b732
AK		 98static DEFINE_PER_CPU(struct vmcs *, vmxarea);
99static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 100static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 101
fdef3ad1
HQ		 102static struct page *vmx_io_bitmap_a;
103static struct page *vmx_io_bitmap_b;
25c5f225 104static struct page *vmx_msr_bitmap;
fdef3ad1 105
2384d2b3
SY		 106static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
107static DEFINE_SPINLOCK(vmx_vpid_lock);
108
1c3d14fe 109static struct vmcs_config {
6aa8b732
AK		 110 int size;
111 int order;
112 u32 revision_id;
1c3d14fe
YS		 113 u32 pin_based_exec_ctrl;
114 u32 cpu_based_exec_ctrl;
f78e0e2e 115 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 116 u32 vmexit_ctrl;
117 u32 vmentry_ctrl;
118} vmcs_config;
6aa8b732 119
d56f546d
SY		 120struct vmx_capability {
121 u32 ept;
122 u32 vpid;
123} vmx_capability;
124
6aa8b732
AK		 125#define VMX_SEGMENT_FIELD(seg) \
126 [VCPU_SREG_##seg] = { \
127 .selector = GUEST_##seg##_SELECTOR, \
128 .base = GUEST_##seg##_BASE, \
129 .limit = GUEST_##seg##_LIMIT, \
130 .ar_bytes = GUEST_##seg##_AR_BYTES, \
131 }
132
133static struct kvm_vmx_segment_field {
134 unsigned selector;
135 unsigned base;
136 unsigned limit;
137 unsigned ar_bytes;
138} kvm_vmx_segment_fields[] = {
139 VMX_SEGMENT_FIELD(CS),
140 VMX_SEGMENT_FIELD(DS),
141 VMX_SEGMENT_FIELD(ES),
142 VMX_SEGMENT_FIELD(FS),
143 VMX_SEGMENT_FIELD(GS),
144 VMX_SEGMENT_FIELD(SS),
145 VMX_SEGMENT_FIELD(TR),
146 VMX_SEGMENT_FIELD(LDTR),
147};
148
4d56c8a7
AK		 149/*
150 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
151 * away by decrementing the array size.
152 */
6aa8b732 153static const u32 vmx_msr_index[] = {
05b3e0c2 154#ifdef CONFIG_X86_64
6aa8b732
AK		 155 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
156#endif
157 MSR_EFER, MSR_K6_STAR,
158};
9d8f549d 159#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 160
a2fa3e9f
GH		 161static void load_msrs(struct kvm_msr_entry *e, int n)
162{
163 int i;
164
165 for (i = 0; i < n; ++i)
166 wrmsrl(e[i].index, e[i].data);
167}
168
169static void save_msrs(struct kvm_msr_entry *e, int n)
170{
171 int i;
172
173 for (i = 0; i < n; ++i)
174 rdmsrl(e[i].index, e[i].data);
175}
176
6aa8b732
AK		 177static inline int is_page_fault(u32 intr_info)
178{
179 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
180 INTR_INFO_VALID_MASK)) ==
181 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
182}
183
2ab455cc
AL		 184static inline int is_no_device(u32 intr_info)
185{
186 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
187 INTR_INFO_VALID_MASK)) ==
188 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
189}
190
7aa81cc0
AL		 191static inline int is_invalid_opcode(u32 intr_info)
192{
193 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
194 INTR_INFO_VALID_MASK)) ==
195 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
196}
197
6aa8b732
AK		 198static inline int is_external_interrupt(u32 intr_info)
199{
200 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
201 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
202}
203
25c5f225
SY		 204static inline int cpu_has_vmx_msr_bitmap(void)
205{
206 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
207}
208
6e5d865c
YS		 209static inline int cpu_has_vmx_tpr_shadow(void)
210{
211 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
212}
213
214static inline int vm_need_tpr_shadow(struct kvm *kvm)
215{
216 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
217}
218
f78e0e2e
SY		 219static inline int cpu_has_secondary_exec_ctrls(void)
220{
221 return (vmcs_config.cpu_based_exec_ctrl &
222 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
223}
224
774ead3a 225static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 226{
4c9fc8ef
AK		 227 return flexpriority_enabled
228 && (vmcs_config.cpu_based_2nd_exec_ctrl &
229 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
f78e0e2e
SY		 230}
231
d56f546d
SY		 232static inline int cpu_has_vmx_invept_individual_addr(void)
233{
234 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
235}
236
237static inline int cpu_has_vmx_invept_context(void)
238{
239 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
240}
241
242static inline int cpu_has_vmx_invept_global(void)
243{
244 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
245}
246
247static inline int cpu_has_vmx_ept(void)
248{
249 return (vmcs_config.cpu_based_2nd_exec_ctrl &
250 SECONDARY_EXEC_ENABLE_EPT);
251}
252
253static inline int vm_need_ept(void)
254{
255 return (cpu_has_vmx_ept() && enable_ept);
256}
257
f78e0e2e
SY		 258static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
259{
260 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
261 (irqchip_in_kernel(kvm)));
262}
263
2384d2b3
SY		 264static inline int cpu_has_vmx_vpid(void)
265{
266 return (vmcs_config.cpu_based_2nd_exec_ctrl &
267 SECONDARY_EXEC_ENABLE_VPID);
268}
269
f08864b4
SY		 270static inline int cpu_has_virtual_nmis(void)
271{
272 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
273}
274
8b9cf98c 275static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 276{
277 int i;
278
a2fa3e9f
GH		 279 for (i = 0; i < vmx->nmsrs; ++i)
280 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 281 return i;
282 return -1;
283}
284
2384d2b3
SY		 285static inline void __invvpid(int ext, u16 vpid, gva_t gva)
286{
287 struct {
288 u64 vpid : 16;
289 u64 rsvd : 48;
290 u64 gva;
291 } operand = { vpid, 0, gva };
292
4ecac3fd 293 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 294 /* CF==1 or ZF==1 --> rc = -1 */
295 "; ja 1f ; ud2 ; 1:"
296 : : "a"(&operand), "c"(ext) : "cc", "memory");
297}
298
1439442c
SY		 299static inline void __invept(int ext, u64 eptp, gpa_t gpa)
300{
301 struct {
302 u64 eptp, gpa;
303 } operand = {eptp, gpa};
304
4ecac3fd 305 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 306 /* CF==1 or ZF==1 --> rc = -1 */
307 "; ja 1f ; ud2 ; 1:\n"
308 : : "a" (&operand), "c" (ext) : "cc", "memory");
309}
310
8b9cf98c 311static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 312{
313 int i;
314
8b9cf98c 315 i = __find_msr_index(vmx, msr);
a75beee6 316 if (i >= 0)
a2fa3e9f 317 return &vmx->guest_msrs[i];
8b6d44c7 318 return NULL;
7725f0ba
AK		 319}
320
6aa8b732
AK		 321static void vmcs_clear(struct vmcs *vmcs)
322{
323 u64 phys_addr = __pa(vmcs);
324 u8 error;
325
4ecac3fd 326 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 327 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
328 : "cc", "memory");
329 if (error)
330 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
331 vmcs, phys_addr);
332}
333
334static void __vcpu_clear(void *arg)
335{
8b9cf98c 336 struct vcpu_vmx *vmx = arg;
d3b2c338 337 int cpu = raw_smp_processor_id();
6aa8b732 338
8b9cf98c 339 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 340 vmcs_clear(vmx->vmcs);
341 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 342 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 343 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 344 list_del(&vmx->local_vcpus_link);
345 vmx->vcpu.cpu = -1;
346 vmx->launched = 0;
6aa8b732
AK		 347}
348
8b9cf98c 349static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 350{
eae5ecb5
AK		 351 if (vmx->vcpu.cpu == -1)
352 return;
8691e5a8 353 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 354}
355
2384d2b3
SY		 356static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
357{
358 if (vmx->vpid == 0)
359 return;
360
361 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
362}
363
1439442c
SY		 364static inline void ept_sync_global(void)
365{
366 if (cpu_has_vmx_invept_global())
367 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
368}
369
370static inline void ept_sync_context(u64 eptp)
371{
372 if (vm_need_ept()) {
373 if (cpu_has_vmx_invept_context())
374 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
375 else
376 ept_sync_global();
377 }
378}
379
380static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
381{
382 if (vm_need_ept()) {
383 if (cpu_has_vmx_invept_individual_addr())
384 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
385 eptp, gpa);
386 else
387 ept_sync_context(eptp);
388 }
389}
390
6aa8b732
AK		 391static unsigned long vmcs_readl(unsigned long field)
392{
393 unsigned long value;
394
4ecac3fd 395 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 396 : "=a"(value) : "d"(field) : "cc");
397 return value;
398}
399
400static u16 vmcs_read16(unsigned long field)
401{
402 return vmcs_readl(field);
403}
404
405static u32 vmcs_read32(unsigned long field)
406{
407 return vmcs_readl(field);
408}
409
410static u64 vmcs_read64(unsigned long field)
411{
05b3e0c2 412#ifdef CONFIG_X86_64
6aa8b732
AK		 413 return vmcs_readl(field);
414#else
415 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
416#endif
417}
418
e52de1b8
AK		 419static noinline void vmwrite_error(unsigned long field, unsigned long value)
420{
421 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
422 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
423 dump_stack();
424}
425
6aa8b732
AK		 426static void vmcs_writel(unsigned long field, unsigned long value)
427{
428 u8 error;
429
4ecac3fd 430 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 431 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 432 if (unlikely(error))
433 vmwrite_error(field, value);
6aa8b732
AK		 434}
435
436static void vmcs_write16(unsigned long field, u16 value)
437{
438 vmcs_writel(field, value);
439}
440
441static void vmcs_write32(unsigned long field, u32 value)
442{
443 vmcs_writel(field, value);
444}
445
446static void vmcs_write64(unsigned long field, u64 value)
447{
6aa8b732 448 vmcs_writel(field, value);
7682f2d0 449#ifndef CONFIG_X86_64
6aa8b732
AK		 450 asm volatile ("");
451 vmcs_writel(field+1, value >> 32);
452#endif
453}
454
2ab455cc
AL		 455static void vmcs_clear_bits(unsigned long field, u32 mask)
456{
457 vmcs_writel(field, vmcs_readl(field) & ~mask);
458}
459
460static void vmcs_set_bits(unsigned long field, u32 mask)
461{
462 vmcs_writel(field, vmcs_readl(field) | mask);
463}
464
abd3f2d6
AK		 465static void update_exception_bitmap(struct kvm_vcpu *vcpu)
466{
467 u32 eb;
468
7aa81cc0 469 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 470 if (!vcpu->fpu_active)
471 eb |= 1u << NM_VECTOR;
472 if (vcpu->guest_debug.enabled)
19bd8afd 473 eb |= 1u << DB_VECTOR;
ad312c7c 474 if (vcpu->arch.rmode.active)
abd3f2d6 475 eb = ~0;
1439442c
SY		 476 if (vm_need_ept())
477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 478 vmcs_write32(EXCEPTION_BITMAP, eb);
479}
480
33ed6329
AK		 481static void reload_tss(void)
482{
33ed6329
AK		 483 /*
484 * VT restores TR but not its size. Useless.
485 */
486 struct descriptor_table gdt;
a5f61300 487 struct desc_struct *descs;
33ed6329 488
d6e88aec 489 kvm_get_gdt(&gdt);
33ed6329
AK		 490 descs = (void *)gdt.base;
491 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
492 load_TR_desc();
33ed6329
AK		 493}
494
8b9cf98c 495static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 496{
a2fa3e9f 497 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 498 u64 host_efer = vmx->host_msrs[efer_offset].data;
499 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
500 u64 ignore_bits;
501
502 if (efer_offset < 0)
503 return;
504 /*
505 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
506 * outside long mode
507 */
508 ignore_bits = EFER_NX | EFER_SCE;
509#ifdef CONFIG_X86_64
510 ignore_bits |= EFER_LMA | EFER_LME;
511 /* SCE is meaningful only in long mode on Intel */
512 if (guest_efer & EFER_LMA)
513 ignore_bits &= ~(u64)EFER_SCE;
514#endif
515 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
516 return;
2cc51560 517
51c6cf66
AK		 518 vmx->host_state.guest_efer_loaded = 1;
519 guest_efer &= ~ignore_bits;
520 guest_efer |= host_efer & ignore_bits;
521 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 522 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 523}
524
51c6cf66
AK		 525static void reload_host_efer(struct vcpu_vmx *vmx)
526{
527 if (vmx->host_state.guest_efer_loaded) {
528 vmx->host_state.guest_efer_loaded = 0;
529 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
530 }
531}
532
04d2cc77 533static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 534{
04d2cc77
AK		 535 struct vcpu_vmx *vmx = to_vmx(vcpu);
536
a2fa3e9f 537 if (vmx->host_state.loaded)
33ed6329
AK		 538 return;
539
a2fa3e9f 540 vmx->host_state.loaded = 1;
33ed6329
AK		 541 /*
542 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
543 * allow segment selectors with cpl > 0 or ti == 1.
544 */
d6e88aec 545 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 546 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 547 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 548 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 549 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 550 vmx->host_state.fs_reload_needed = 0;
551 } else {
33ed6329 552 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 553 vmx->host_state.fs_reload_needed = 1;
33ed6329 554 }
d6e88aec 555 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 556 if (!(vmx->host_state.gs_sel & 7))
557 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 558 else {
559 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 560 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 561 }
562
563#ifdef CONFIG_X86_64
564 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
565 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
566#else
a2fa3e9f
GH		 567 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
568 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 569#endif
707c0874
AK		 570
571#ifdef CONFIG_X86_64
d77c26fc 572 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 573 save_msrs(vmx->host_msrs +
574 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 575
707c0874 576#endif
a2fa3e9f 577 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 578 load_transition_efer(vmx);
33ed6329
AK		 579}
580
a9b21b62 581static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 582{
15ad7146 583 unsigned long flags;
33ed6329 584
a2fa3e9f 585 if (!vmx->host_state.loaded)
33ed6329
AK		 586 return;
587
e1beb1d3 588 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 589 vmx->host_state.loaded = 0;
152d3f2f 590 if (vmx->host_state.fs_reload_needed)
d6e88aec 591 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 592 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 593 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 594 /*
595 * If we have to reload gs, we must take care to
596 * preserve our gs base.
597 */
15ad7146 598 local_irq_save(flags);
d6e88aec 599 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 600#ifdef CONFIG_X86_64
601 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
602#endif
15ad7146 603 local_irq_restore(flags);
33ed6329 604 }
152d3f2f 605 reload_tss();
a2fa3e9f
GH		 606 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
607 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 608 reload_host_efer(vmx);
33ed6329
AK		 609}
610
a9b21b62
AK		 611static void vmx_load_host_state(struct vcpu_vmx *vmx)
612{
613 preempt_disable();
614 __vmx_load_host_state(vmx);
615 preempt_enable();
616}
617
6aa8b732
AK		 618/*
619 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
620 * vcpu mutex is already taken.
621 */
15ad7146 622static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 623{
a2fa3e9f
GH		 624 struct vcpu_vmx *vmx = to_vmx(vcpu);
625 u64 phys_addr = __pa(vmx->vmcs);
019960ae 626 u64 tsc_this, delta, new_offset;
6aa8b732 627
a3d7f85f 628 if (vcpu->cpu != cpu) {
8b9cf98c 629 vcpu_clear(vmx);
2f599714 630 kvm_migrate_timers(vcpu);
2384d2b3 631 vpid_sync_vcpu_all(vmx);
543e4243
AK		 632 local_irq_disable();
633 list_add(&vmx->local_vcpus_link,
634 &per_cpu(vcpus_on_cpu, cpu));
635 local_irq_enable();
a3d7f85f 636 }
6aa8b732 637
a2fa3e9f 638 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 639 u8 error;
640
a2fa3e9f 641 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 642 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 643 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
644 : "cc");
645 if (error)
646 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 647 vmx->vmcs, phys_addr);
6aa8b732
AK		 648 }
649
650 if (vcpu->cpu != cpu) {
651 struct descriptor_table dt;
652 unsigned long sysenter_esp;
653
654 vcpu->cpu = cpu;
655 /*
656 * Linux uses per-cpu TSS and GDT, so set these when switching
657 * processors.
658 */
d6e88aec
AK		 659 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
660 kvm_get_gdt(&dt);
6aa8b732
AK		 661 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
662
663 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
664 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 665
666 /*
667 * Make sure the time stamp counter is monotonous.
668 */
669 rdtscll(tsc_this);
019960ae
AK		 670 if (tsc_this < vcpu->arch.host_tsc) {
671 delta = vcpu->arch.host_tsc - tsc_this;
672 new_offset = vmcs_read64(TSC_OFFSET) + delta;
673 vmcs_write64(TSC_OFFSET, new_offset);
674 }
6aa8b732 675 }
6aa8b732
AK		 676}
677
678static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
679{
a9b21b62 680 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 681}
682
5fd86fcf
AK		 683static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
684{
685 if (vcpu->fpu_active)
686 return;
687 vcpu->fpu_active = 1;
707d92fa 688 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 689 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 690 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 691 update_exception_bitmap(vcpu);
692}
693
694static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
695{
696 if (!vcpu->fpu_active)
697 return;
698 vcpu->fpu_active = 0;
707d92fa 699 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 700 update_exception_bitmap(vcpu);
701}
702
6aa8b732
AK		 703static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
704{
705 return vmcs_readl(GUEST_RFLAGS);
706}
707
708static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
709{
ad312c7c 710 if (vcpu->arch.rmode.active)
053de044 711 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 712 vmcs_writel(GUEST_RFLAGS, rflags);
713}
714
715static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
716{
717 unsigned long rip;
718 u32 interruptibility;
719
5fdbf976 720 rip = kvm_rip_read(vcpu);
6aa8b732 721 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 722 kvm_rip_write(vcpu, rip);
6aa8b732
AK		 723
724 /*
725 * We emulated an instruction, so temporary interrupt blocking
726 * should be removed, if set.
727 */
728 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
729 if (interruptibility & 3)
730 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
731 interruptibility & ~3);
ad312c7c 732 vcpu->arch.interrupt_window_open = 1;
6aa8b732
AK		 733}
734
298101da
AK		 735static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
736 bool has_error_code, u32 error_code)
737{
738 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
739 nr | INTR_TYPE_EXCEPTION
2e11384c 740 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
298101da
AK		 741 | INTR_INFO_VALID_MASK);
742 if (has_error_code)
743 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
744}
745
746static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
747{
35920a35 748 return false;
298101da
AK		 749}
750
a75beee6
ED		 751/*
752 * Swap MSR entry in host/guest MSR entry array.
753 */
54e11fa1 754#ifdef CONFIG_X86_64
8b9cf98c 755static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 756{
a2fa3e9f
GH		 757 struct kvm_msr_entry tmp;
758
759 tmp = vmx->guest_msrs[to];
760 vmx->guest_msrs[to] = vmx->guest_msrs[from];
761 vmx->guest_msrs[from] = tmp;
762 tmp = vmx->host_msrs[to];
763 vmx->host_msrs[to] = vmx->host_msrs[from];
764 vmx->host_msrs[from] = tmp;
a75beee6 765}
54e11fa1 766#endif
a75beee6 767
e38aea3e
AK		 768/*
769 * Set up the vmcs to automatically save and restore system
770 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
771 * mode, as fiddling with msrs is very expensive.
772 */
8b9cf98c 773static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 774{
2cc51560 775 int save_nmsrs;
e38aea3e 776
33f9c505 777 vmx_load_host_state(vmx);
a75beee6
ED		 778 save_nmsrs = 0;
779#ifdef CONFIG_X86_64
8b9cf98c 780 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 781 int index;
782
8b9cf98c 783 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 784 if (index >= 0)
8b9cf98c
RR		 785 move_msr_up(vmx, index, save_nmsrs++);
786 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 787 if (index >= 0)
8b9cf98c
RR		 788 move_msr_up(vmx, index, save_nmsrs++);
789 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 790 if (index >= 0)
8b9cf98c
RR		 791 move_msr_up(vmx, index, save_nmsrs++);
792 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 793 if (index >= 0)
8b9cf98c 794 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 795 /*
796 * MSR_K6_STAR is only needed on long mode guests, and only
797 * if efer.sce is enabled.
798 */
8b9cf98c 799 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 800 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 801 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 802 }
803#endif
a2fa3e9f 804 vmx->save_nmsrs = save_nmsrs;
e38aea3e 805
4d56c8a7 806#ifdef CONFIG_X86_64
a2fa3e9f 807 vmx->msr_offset_kernel_gs_base =
8b9cf98c 808 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 809#endif
8b9cf98c 810 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 811}
812
6aa8b732
AK		 813/*
814 * reads and returns guest's timestamp counter "register"
815 * guest_tsc = host_tsc + tsc_offset -- 21.3
816 */
817static u64 guest_read_tsc(void)
818{
819 u64 host_tsc, tsc_offset;
820
821 rdtscll(host_tsc);
822 tsc_offset = vmcs_read64(TSC_OFFSET);
823 return host_tsc + tsc_offset;
824}
825
826/*
827 * writes 'guest_tsc' into guest's timestamp counter "register"
828 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
829 */
830static void guest_write_tsc(u64 guest_tsc)
831{
832 u64 host_tsc;
833
834 rdtscll(host_tsc);
835 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
836}
837
6aa8b732
AK		 838/*
839 * Reads an msr value (of 'msr_index') into 'pdata'.
840 * Returns 0 on success, non-0 otherwise.
841 * Assumes vcpu_load() was already called.
842 */
843static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
844{
845 u64 data;
a2fa3e9f 846 struct kvm_msr_entry *msr;
6aa8b732
AK		 847
848 if (!pdata) {
849 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
850 return -EINVAL;
851 }
852
853 switch (msr_index) {
05b3e0c2 854#ifdef CONFIG_X86_64
6aa8b732
AK		 855 case MSR_FS_BASE:
856 data = vmcs_readl(GUEST_FS_BASE);
857 break;
858 case MSR_GS_BASE:
859 data = vmcs_readl(GUEST_GS_BASE);
860 break;
861 case MSR_EFER:
3bab1f5d 862 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 863#endif
864 case MSR_IA32_TIME_STAMP_COUNTER:
865 data = guest_read_tsc();
866 break;
867 case MSR_IA32_SYSENTER_CS:
868 data = vmcs_read32(GUEST_SYSENTER_CS);
869 break;
870 case MSR_IA32_SYSENTER_EIP:
f5b42c33 871 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 872 break;
873 case MSR_IA32_SYSENTER_ESP:
f5b42c33 874 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 875 break;
6aa8b732 876 default:
8b9cf98c 877 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 878 if (msr) {
879 data = msr->data;
880 break;
6aa8b732 881 }
3bab1f5d 882 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 883 }
884
885 *pdata = data;
886 return 0;
887}
888
889/*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
894static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
895{
a2fa3e9f
GH		 896 struct vcpu_vmx *vmx = to_vmx(vcpu);
897 struct kvm_msr_entry *msr;
2cc51560
ED		 898 int ret = 0;
899
6aa8b732 900 switch (msr_index) {
05b3e0c2 901#ifdef CONFIG_X86_64
3bab1f5d 902 case MSR_EFER:
a9b21b62 903 vmx_load_host_state(vmx);
2cc51560 904 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 905 break;
6aa8b732
AK		 906 case MSR_FS_BASE:
907 vmcs_writel(GUEST_FS_BASE, data);
908 break;
909 case MSR_GS_BASE:
910 vmcs_writel(GUEST_GS_BASE, data);
911 break;
912#endif
913 case MSR_IA32_SYSENTER_CS:
914 vmcs_write32(GUEST_SYSENTER_CS, data);
915 break;
916 case MSR_IA32_SYSENTER_EIP:
f5b42c33 917 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 918 break;
919 case MSR_IA32_SYSENTER_ESP:
f5b42c33 920 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 921 break;
d27d4aca 922 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732 923 guest_write_tsc(data);
efa67e0d
CL		 924 break;
925 case MSR_P6_PERFCTR0:
926 case MSR_P6_PERFCTR1:
927 case MSR_P6_EVNTSEL0:
928 case MSR_P6_EVNTSEL1:
929 /*
930 * Just discard all writes to the performance counters; this
931 * should keep both older linux and windows 64-bit guests
932 * happy
933 */
934 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
935
6aa8b732 936 break;
6aa8b732 937 default:
a9b21b62 938 vmx_load_host_state(vmx);
8b9cf98c 939 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 940 if (msr) {
941 msr->data = data;
942 break;
6aa8b732 943 }
2cc51560 944 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 945 }
946
2cc51560 947 return ret;
6aa8b732
AK		 948}
949
5fdbf976 950static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 951{
5fdbf976
MT		 952 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
953 switch (reg) {
954 case VCPU_REGS_RSP:
955 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
956 break;
957 case VCPU_REGS_RIP:
958 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
959 break;
960 default:
961 break;
962 }
6aa8b732
AK		 963}
964
965static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
966{
967 unsigned long dr7 = 0x400;
6aa8b732
AK		 968 int old_singlestep;
969
6aa8b732
AK		 970 old_singlestep = vcpu->guest_debug.singlestep;
971
972 vcpu->guest_debug.enabled = dbg->enabled;
973 if (vcpu->guest_debug.enabled) {
974 int i;
975
976 dr7 |= 0x200; /* exact */
977 for (i = 0; i < 4; ++i) {
978 if (!dbg->breakpoints[i].enabled)
979 continue;
980 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
981 dr7 |= 2 << (i*2); /* global enable */
982 dr7 |= 0 << (i*4+16); /* execution breakpoint */
983 }
984
6aa8b732 985 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 986 } else
6aa8b732 987 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 988
989 if (old_singlestep && !vcpu->guest_debug.singlestep) {
990 unsigned long flags;
991
992 flags = vmcs_readl(GUEST_RFLAGS);
993 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
994 vmcs_writel(GUEST_RFLAGS, flags);
995 }
996
abd3f2d6 997 update_exception_bitmap(vcpu);
6aa8b732
AK		 998 vmcs_writel(GUEST_DR7, dr7);
999
1000 return 0;
1001}
1002
2a8067f1
ED		 1003static int vmx_get_irq(struct kvm_vcpu *vcpu)
1004{
f7d9238f
AK		 1005 if (!vcpu->arch.interrupt.pending)
1006 return -1;
1007 return vcpu->arch.interrupt.nr;
2a8067f1
ED		 1008}
1009
6aa8b732
AK		 1010static __init int cpu_has_kvm_support(void)
1011{
1012 unsigned long ecx = cpuid_ecx(1);
1013 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1014}
1015
1016static __init int vmx_disabled_by_bios(void)
1017{
1018 u64 msr;
1019
1020 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
ca60dfbb
SY		 1021 return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1022 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1023 == IA32_FEATURE_CONTROL_LOCKED_BIT;
62b3ffb8 1024 /* locked but not enabled */
6aa8b732
AK		 1025}
1026
774c47f1 1027static void hardware_enable(void *garbage)
6aa8b732
AK		 1028{
1029 int cpu = raw_smp_processor_id();
1030 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1031 u64 old;
1032
543e4243 1033 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1034 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
ca60dfbb
SY		 1035 if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT |
1036 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
1037 != (IA32_FEATURE_CONTROL_LOCKED_BIT |
1038 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT))
6aa8b732 1039 /* enable and lock */
62b3ffb8 1040 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
ca60dfbb
SY		 1041 IA32_FEATURE_CONTROL_LOCKED_BIT |
1042 IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT);
66aee91a 1043 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1044 asm volatile (ASM_VMX_VMXON_RAX
1045 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1046 : "memory", "cc");
1047}
1048
543e4243
AK		 1049static void vmclear_local_vcpus(void)
1050{
1051 int cpu = raw_smp_processor_id();
1052 struct vcpu_vmx *vmx, *n;
1053
1054 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1055 local_vcpus_link)
1056 __vcpu_clear(vmx);
1057}
1058
6aa8b732
AK		 1059static void hardware_disable(void *garbage)
1060{
543e4243 1061 vmclear_local_vcpus();
4ecac3fd 1062 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1063 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1064}
1065
1c3d14fe 1066static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1067 u32 msr, u32 *result)
1c3d14fe
YS		 1068{
1069 u32 vmx_msr_low, vmx_msr_high;
1070 u32 ctl = ctl_min | ctl_opt;
1071
1072 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1073
1074 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1075 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1076
1077 /* Ensure minimum (required) set of control bits are supported. */
1078 if (ctl_min & ~ctl)
002c7f7c 1079 return -EIO;
1c3d14fe
YS		 1080
1081 *result = ctl;
1082 return 0;
1083}
1084
002c7f7c 1085static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1086{
1087 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1088 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1089 u32 _pin_based_exec_control = 0;
1090 u32 _cpu_based_exec_control = 0;
f78e0e2e 1091 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1092 u32 _vmexit_control = 0;
1093 u32 _vmentry_control = 0;
1094
1095 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1096 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1097 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1098 &_pin_based_exec_control) < 0)
002c7f7c 1099 return -EIO;
1c3d14fe
YS		 1100
1101 min = CPU_BASED_HLT_EXITING |
1102#ifdef CONFIG_X86_64
1103 CPU_BASED_CR8_LOAD_EXITING |
1104 CPU_BASED_CR8_STORE_EXITING |
1105#endif
d56f546d
SY		 1106 CPU_BASED_CR3_LOAD_EXITING |
1107 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1108 CPU_BASED_USE_IO_BITMAPS |
1109 CPU_BASED_MOV_DR_EXITING |
1110 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e 1111 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1112 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1113 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1114 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1115 &_cpu_based_exec_control) < 0)
002c7f7c 1116 return -EIO;
6e5d865c
YS		 1117#ifdef CONFIG_X86_64
1118 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1119 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1120 ~CPU_BASED_CR8_STORE_EXITING;
1121#endif
f78e0e2e 1122 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1123 min2 = 0;
1124 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1125 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d
SY		 1126 SECONDARY_EXEC_ENABLE_VPID |
1127 SECONDARY_EXEC_ENABLE_EPT;
1128 if (adjust_vmx_controls(min2, opt2,
1129 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1130 &_cpu_based_2nd_exec_control) < 0)
1131 return -EIO;
1132 }
1133#ifndef CONFIG_X86_64
1134 if (!(_cpu_based_2nd_exec_control &
1135 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1136 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1137#endif
d56f546d
SY		 1138 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1139 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1140 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1141 CPU_BASED_CR3_STORE_EXITING);
1142 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1143 &_cpu_based_exec_control) < 0)
1144 return -EIO;
1145 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1146 vmx_capability.ept, vmx_capability.vpid);
1147 }
1c3d14fe
YS		 1148
1149 min = 0;
1150#ifdef CONFIG_X86_64
1151 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1152#endif
1153 opt = 0;
1154 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1155 &_vmexit_control) < 0)
002c7f7c 1156 return -EIO;
1c3d14fe
YS		 1157
1158 min = opt = 0;
1159 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1160 &_vmentry_control) < 0)
002c7f7c 1161 return -EIO;
6aa8b732 1162
c68876fd 1163 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1164
1165 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1166 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1167 return -EIO;
1c3d14fe
YS		 1168
1169#ifdef CONFIG_X86_64
1170 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1171 if (vmx_msr_high & (1u<<16))
002c7f7c 1172 return -EIO;
1c3d14fe
YS		 1173#endif
1174
1175 /* Require Write-Back (WB) memory type for VMCS accesses. */
1176 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1177 return -EIO;
1c3d14fe 1178
002c7f7c
YS		 1179 vmcs_conf->size = vmx_msr_high & 0x1fff;
1180 vmcs_conf->order = get_order(vmcs_config.size);
1181 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1182
002c7f7c
YS		 1183 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1184 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1185 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1186 vmcs_conf->vmexit_ctrl = _vmexit_control;
1187 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1188
1189 return 0;
c68876fd 1190}
6aa8b732
AK		 1191
1192static struct vmcs *alloc_vmcs_cpu(int cpu)
1193{
1194 int node = cpu_to_node(cpu);
1195 struct page *pages;
1196 struct vmcs *vmcs;
1197
1c3d14fe 1198 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1199 if (!pages)
1200 return NULL;
1201 vmcs = page_address(pages);
1c3d14fe
YS		 1202 memset(vmcs, 0, vmcs_config.size);
1203 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1204 return vmcs;
1205}
1206
1207static struct vmcs *alloc_vmcs(void)
1208{
d3b2c338 1209 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1210}
1211
1212static void free_vmcs(struct vmcs *vmcs)
1213{
1c3d14fe 1214 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1215}
1216
39959588 1217static void free_kvm_area(void)
6aa8b732
AK		 1218{
1219 int cpu;
1220
1221 for_each_online_cpu(cpu)
1222 free_vmcs(per_cpu(vmxarea, cpu));
1223}
1224
6aa8b732
AK		 1225static __init int alloc_kvm_area(void)
1226{
1227 int cpu;
1228
1229 for_each_online_cpu(cpu) {
1230 struct vmcs *vmcs;
1231
1232 vmcs = alloc_vmcs_cpu(cpu);
1233 if (!vmcs) {
1234 free_kvm_area();
1235 return -ENOMEM;
1236 }
1237
1238 per_cpu(vmxarea, cpu) = vmcs;
1239 }
1240 return 0;
1241}
1242
1243static __init int hardware_setup(void)
1244{
002c7f7c
YS		 1245 if (setup_vmcs_config(&vmcs_config) < 0)
1246 return -EIO;
50a37eb4
JR		 1247
1248 if (boot_cpu_has(X86_FEATURE_NX))
1249 kvm_enable_efer_bits(EFER_NX);
1250
6aa8b732
AK		 1251 return alloc_kvm_area();
1252}
1253
1254static __exit void hardware_unsetup(void)
1255{
1256 free_kvm_area();
1257}
1258
6aa8b732
AK		 1259static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1260{
1261 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1262
6af11b9e 1263 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1264 vmcs_write16(sf->selector, save->selector);
1265 vmcs_writel(sf->base, save->base);
1266 vmcs_write32(sf->limit, save->limit);
1267 vmcs_write32(sf->ar_bytes, save->ar);
1268 } else {
1269 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1270 << AR_DPL_SHIFT;
1271 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1272 }
1273}
1274
1275static void enter_pmode(struct kvm_vcpu *vcpu)
1276{
1277 unsigned long flags;
1278
ad312c7c 1279 vcpu->arch.rmode.active = 0;
6aa8b732 1280
ad312c7c
ZX		 1281 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1282 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1283 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
6aa8b732
AK		 1284
1285 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1286 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
ad312c7c 1287 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1288 vmcs_writel(GUEST_RFLAGS, flags);
1289
66aee91a
RR		 1290 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1291 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1292
1293 update_exception_bitmap(vcpu);
1294
ad312c7c
ZX		 1295 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1296 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1297 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1298 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
6aa8b732
AK		 1299
1300 vmcs_write16(GUEST_SS_SELECTOR, 0);
1301 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1302
1303 vmcs_write16(GUEST_CS_SELECTOR,
1304 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1305 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1306}
1307
d77c26fc 1308static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1309{
bfc6d222 1310 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1311 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1312 kvm->memslots[0].npages - 3;
1313 return base_gfn << PAGE_SHIFT;
1314 }
bfc6d222 1315 return kvm->arch.tss_addr;
6aa8b732
AK		 1316}
1317
1318static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1319{
1320 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1321
1322 save->selector = vmcs_read16(sf->selector);
1323 save->base = vmcs_readl(sf->base);
1324 save->limit = vmcs_read32(sf->limit);
1325 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1326 vmcs_write16(sf->selector, save->base >> 4);
1327 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1328 vmcs_write32(sf->limit, 0xffff);
1329 vmcs_write32(sf->ar_bytes, 0xf3);
1330}
1331
1332static void enter_rmode(struct kvm_vcpu *vcpu)
1333{
1334 unsigned long flags;
1335
ad312c7c 1336 vcpu->arch.rmode.active = 1;
6aa8b732 1337
ad312c7c 1338 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1339 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1340
ad312c7c 1341 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1342 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1343
ad312c7c 1344 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1345 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1346
1347 flags = vmcs_readl(GUEST_RFLAGS);
ad312c7c
ZX		 1348 vcpu->arch.rmode.save_iopl
1349 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1350
053de044 1351 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1352
1353 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1354 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1355 update_exception_bitmap(vcpu);
1356
1357 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1358 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1359 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1360
1361 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1362 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1363 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1364 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1365 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1366
ad312c7c
ZX		 1367 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1368 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1369 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1370 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
75880a01 1371
8668a3c4 1372 kvm_mmu_reset_context(vcpu);
b7ebfb05 1373 init_rmode(vcpu->kvm);
6aa8b732
AK		 1374}
1375
05b3e0c2 1376#ifdef CONFIG_X86_64
6aa8b732
AK		 1377
1378static void enter_lmode(struct kvm_vcpu *vcpu)
1379{
1380 u32 guest_tr_ar;
1381
1382 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1383 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1384 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1385 __func__);
6aa8b732
AK		 1386 vmcs_write32(GUEST_TR_AR_BYTES,
1387 (guest_tr_ar & ~AR_TYPE_MASK)
1388 | AR_TYPE_BUSY_64_TSS);
1389 }
1390
ad312c7c 1391 vcpu->arch.shadow_efer |= EFER_LMA;
6aa8b732 1392
8b9cf98c 1393 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1394 vmcs_write32(VM_ENTRY_CONTROLS,
1395 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1396 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1397}
1398
1399static void exit_lmode(struct kvm_vcpu *vcpu)
1400{
ad312c7c 1401 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1402
1403 vmcs_write32(VM_ENTRY_CONTROLS,
1404 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1405 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1406}
1407
1408#endif
1409
2384d2b3
SY		 1410static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1411{
1412 vpid_sync_vcpu_all(to_vmx(vcpu));
4e1096d2
SY		 1413 if (vm_need_ept())
1414 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1415}
1416
25c4c276 1417static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1418{
ad312c7c
ZX		 1419 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1420 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
399badf3
AK		 1421}
1422
1439442c
SY		 1423static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1424{
1425 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1426 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1427 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1428 return;
1429 }
1430 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1431 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1432 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1433 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1434 }
1435}
1436
1437static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1438
1439static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1440 unsigned long cr0,
1441 struct kvm_vcpu *vcpu)
1442{
1443 if (!(cr0 & X86_CR0_PG)) {
1444 /* From paging/starting to nonpaging */
1445 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1446 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1447 (CPU_BASED_CR3_LOAD_EXITING |
1448 CPU_BASED_CR3_STORE_EXITING));
1449 vcpu->arch.cr0 = cr0;
1450 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1451 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1452 *hw_cr0 &= ~X86_CR0_WP;
1453 } else if (!is_paging(vcpu)) {
1454 /* From nonpaging to paging */
1455 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1456 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1457 ~(CPU_BASED_CR3_LOAD_EXITING |
1458 CPU_BASED_CR3_STORE_EXITING));
1459 vcpu->arch.cr0 = cr0;
1460 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1461 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1462 *hw_cr0 &= ~X86_CR0_WP;
1463 }
1464}
1465
1466static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1467 struct kvm_vcpu *vcpu)
1468{
1469 if (!is_paging(vcpu)) {
1470 *hw_cr4 &= ~X86_CR4_PAE;
1471 *hw_cr4 |= X86_CR4_PSE;
1472 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1473 *hw_cr4 &= ~X86_CR4_PAE;
1474}
1475
6aa8b732
AK		 1476static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1477{
1439442c
SY		 1478 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1479 KVM_VM_CR0_ALWAYS_ON;
1480
5fd86fcf
AK		 1481 vmx_fpu_deactivate(vcpu);
1482
ad312c7c 1483 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1484 enter_pmode(vcpu);
1485
ad312c7c 1486 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1487 enter_rmode(vcpu);
1488
05b3e0c2 1489#ifdef CONFIG_X86_64
ad312c7c 1490 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1491 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1492 enter_lmode(vcpu);
707d92fa 1493 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1494 exit_lmode(vcpu);
1495 }
1496#endif
1497
1439442c
SY		 1498 if (vm_need_ept())
1499 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1500
6aa8b732 1501 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1502 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1503 vcpu->arch.cr0 = cr0;
5fd86fcf 1504
707d92fa 1505 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1506 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1507}
1508
1439442c
SY		 1509static u64 construct_eptp(unsigned long root_hpa)
1510{
1511 u64 eptp;
1512
1513 /* TODO write the value reading from MSR */
1514 eptp = VMX_EPT_DEFAULT_MT |
1515 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1516 eptp |= (root_hpa & PAGE_MASK);
1517
1518 return eptp;
1519}
1520
6aa8b732
AK		 1521static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1522{
1439442c
SY		 1523 unsigned long guest_cr3;
1524 u64 eptp;
1525
1526 guest_cr3 = cr3;
1527 if (vm_need_ept()) {
1528 eptp = construct_eptp(cr3);
1529 vmcs_write64(EPT_POINTER, eptp);
1530 ept_sync_context(eptp);
1531 ept_load_pdptrs(vcpu);
1532 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1533 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1534 }
1535
2384d2b3 1536 vmx_flush_tlb(vcpu);
1439442c 1537 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1538 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1539 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1540}
1541
1542static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1543{
1439442c
SY		 1544 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1545 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1546
ad312c7c 1547 vcpu->arch.cr4 = cr4;
1439442c
SY		 1548 if (vm_need_ept())
1549 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1550
1551 vmcs_writel(CR4_READ_SHADOW, cr4);
1552 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1553}
1554
6aa8b732
AK		 1555static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1556{
8b9cf98c
RR		 1557 struct vcpu_vmx *vmx = to_vmx(vcpu);
1558 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732 1559
ad312c7c 1560 vcpu->arch.shadow_efer = efer;
9f62e19a
JR		 1561 if (!msr)
1562 return;
6aa8b732
AK		 1563 if (efer & EFER_LMA) {
1564 vmcs_write32(VM_ENTRY_CONTROLS,
1565 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1566 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1567 msr->data = efer;
1568
1569 } else {
1570 vmcs_write32(VM_ENTRY_CONTROLS,
1571 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1572 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1573
1574 msr->data = efer & ~EFER_LME;
1575 }
8b9cf98c 1576 setup_msrs(vmx);
6aa8b732
AK		 1577}
1578
6aa8b732
AK		 1579static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1580{
1581 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1582
1583 return vmcs_readl(sf->base);
1584}
1585
1586static void vmx_get_segment(struct kvm_vcpu *vcpu,
1587 struct kvm_segment *var, int seg)
1588{
1589 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1590 u32 ar;
1591
1592 var->base = vmcs_readl(sf->base);
1593 var->limit = vmcs_read32(sf->limit);
1594 var->selector = vmcs_read16(sf->selector);
1595 ar = vmcs_read32(sf->ar_bytes);
1596 if (ar & AR_UNUSABLE_MASK)
1597 ar = 0;
1598 var->type = ar & 15;
1599 var->s = (ar >> 4) & 1;
1600 var->dpl = (ar >> 5) & 3;
1601 var->present = (ar >> 7) & 1;
1602 var->avl = (ar >> 12) & 1;
1603 var->l = (ar >> 13) & 1;
1604 var->db = (ar >> 14) & 1;
1605 var->g = (ar >> 15) & 1;
1606 var->unusable = (ar >> 16) & 1;
1607}
1608
2e4d2653
IE		 1609static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1610{
1611 struct kvm_segment kvm_seg;
1612
1613 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1614 return 0;
1615
1616 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1617 return 3;
1618
1619 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1620 return kvm_seg.selector & 3;
1621}
1622
653e3108 1623static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1624{
6aa8b732
AK		 1625 u32 ar;
1626
653e3108 1627 if (var->unusable)
6aa8b732
AK		 1628 ar = 1 << 16;
1629 else {
1630 ar = var->type & 15;
1631 ar |= (var->s & 1) << 4;
1632 ar |= (var->dpl & 3) << 5;
1633 ar |= (var->present & 1) << 7;
1634 ar |= (var->avl & 1) << 12;
1635 ar |= (var->l & 1) << 13;
1636 ar |= (var->db & 1) << 14;
1637 ar |= (var->g & 1) << 15;
1638 }
f7fbf1fd
UL		 1639 if (ar == 0) /* a 0 value means unusable */
1640 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1641
1642 return ar;
1643}
1644
1645static void vmx_set_segment(struct kvm_vcpu *vcpu,
1646 struct kvm_segment *var, int seg)
1647{
1648 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1649 u32 ar;
1650
ad312c7c
ZX		 1651 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1652 vcpu->arch.rmode.tr.selector = var->selector;
1653 vcpu->arch.rmode.tr.base = var->base;
1654 vcpu->arch.rmode.tr.limit = var->limit;
1655 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1656 return;
1657 }
1658 vmcs_writel(sf->base, var->base);
1659 vmcs_write32(sf->limit, var->limit);
1660 vmcs_write16(sf->selector, var->selector);
ad312c7c 1661 if (vcpu->arch.rmode.active && var->s) {
653e3108
AK		 1662 /*
1663 * Hack real-mode segments into vm86 compatibility.
1664 */
1665 if (var->base == 0xffff0000 && var->selector == 0xf000)
1666 vmcs_writel(sf->base, 0xf0000);
1667 ar = 0xf3;
1668 } else
1669 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1670 vmcs_write32(sf->ar_bytes, ar);
1671}
1672
6aa8b732
AK		 1673static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1674{
1675 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1676
1677 *db = (ar >> 14) & 1;
1678 *l = (ar >> 13) & 1;
1679}
1680
1681static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1682{
1683 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1684 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1685}
1686
1687static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1688{
1689 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1690 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1691}
1692
1693static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1694{
1695 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1696 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1697}
1698
1699static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1700{
1701 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1702 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1703}
1704
d77c26fc 1705static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1706{
6aa8b732 1707 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 1708 u16 data = 0;
10589a46 1709 int ret = 0;
195aefde 1710 int r;
6aa8b732 1711
195aefde
IE		 1712 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1713 if (r < 0)
10589a46 1714 goto out;
195aefde
IE		 1715 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1716 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1717 if (r < 0)
10589a46 1718 goto out;
195aefde
IE		 1719 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1720 if (r < 0)
10589a46 1721 goto out;
195aefde
IE		 1722 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1723 if (r < 0)
10589a46 1724 goto out;
195aefde 1725 data = ~0;
10589a46
MT		 1726 r = kvm_write_guest_page(kvm, fn, &data,
1727 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1728 sizeof(u8));
195aefde 1729 if (r < 0)
10589a46
MT		 1730 goto out;
1731
1732 ret = 1;
1733out:
10589a46 1734 return ret;
6aa8b732
AK		 1735}
1736
b7ebfb05
SY		 1737static int init_rmode_identity_map(struct kvm *kvm)
1738{
1739 int i, r, ret;
1740 pfn_t identity_map_pfn;
1741 u32 tmp;
1742
1743 if (!vm_need_ept())
1744 return 1;
1745 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1746 printk(KERN_ERR "EPT: identity-mapping pagetable "
1747 "haven't been allocated!\n");
1748 return 0;
1749 }
1750 if (likely(kvm->arch.ept_identity_pagetable_done))
1751 return 1;
1752 ret = 0;
1753 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1754 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1755 if (r < 0)
1756 goto out;
1757 /* Set up identity-mapping pagetable for EPT in real mode */
1758 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1759 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1760 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1761 r = kvm_write_guest_page(kvm, identity_map_pfn,
1762 &tmp, i * sizeof(tmp), sizeof(tmp));
1763 if (r < 0)
1764 goto out;
1765 }
1766 kvm->arch.ept_identity_pagetable_done = true;
1767 ret = 1;
1768out:
1769 return ret;
1770}
1771
6aa8b732
AK		 1772static void seg_setup(int seg)
1773{
1774 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1775
1776 vmcs_write16(sf->selector, 0);
1777 vmcs_writel(sf->base, 0);
1778 vmcs_write32(sf->limit, 0xffff);
1779 vmcs_write32(sf->ar_bytes, 0x93);
1780}
1781
f78e0e2e
SY		 1782static int alloc_apic_access_page(struct kvm *kvm)
1783{
1784 struct kvm_userspace_memory_region kvm_userspace_mem;
1785 int r = 0;
1786
72dc67a6 1787 down_write(&kvm->slots_lock);
bfc6d222 1788 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 1789 goto out;
1790 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1791 kvm_userspace_mem.flags = 0;
1792 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1793 kvm_userspace_mem.memory_size = PAGE_SIZE;
1794 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1795 if (r)
1796 goto out;
72dc67a6
IE		 1797
1798 down_read(&current->mm->mmap_sem);
bfc6d222 1799 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
72dc67a6 1800 up_read(&current->mm->mmap_sem);
f78e0e2e 1801out:
72dc67a6 1802 up_write(&kvm->slots_lock);
f78e0e2e
SY		 1803 return r;
1804}
1805
b7ebfb05
SY		 1806static int alloc_identity_pagetable(struct kvm *kvm)
1807{
1808 struct kvm_userspace_memory_region kvm_userspace_mem;
1809 int r = 0;
1810
1811 down_write(&kvm->slots_lock);
1812 if (kvm->arch.ept_identity_pagetable)
1813 goto out;
1814 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1815 kvm_userspace_mem.flags = 0;
1816 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1817 kvm_userspace_mem.memory_size = PAGE_SIZE;
1818 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1819 if (r)
1820 goto out;
1821
1822 down_read(&current->mm->mmap_sem);
1823 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1824 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1825 up_read(&current->mm->mmap_sem);
1826out:
1827 up_write(&kvm->slots_lock);
1828 return r;
1829}
1830
2384d2b3
SY		 1831static void allocate_vpid(struct vcpu_vmx *vmx)
1832{
1833 int vpid;
1834
1835 vmx->vpid = 0;
1836 if (!enable_vpid || !cpu_has_vmx_vpid())
1837 return;
1838 spin_lock(&vmx_vpid_lock);
1839 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1840 if (vpid < VMX_NR_VPIDS) {
1841 vmx->vpid = vpid;
1842 __set_bit(vpid, vmx_vpid_bitmap);
1843 }
1844 spin_unlock(&vmx_vpid_lock);
1845}
1846
8b2cf73c 1847static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
25c5f225
SY		 1848{
1849 void *va;
1850
1851 if (!cpu_has_vmx_msr_bitmap())
1852 return;
1853
1854 /*
1855 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1856 * have the write-low and read-high bitmap offsets the wrong way round.
1857 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1858 */
1859 va = kmap(msr_bitmap);
1860 if (msr <= 0x1fff) {
1861 __clear_bit(msr, va + 0x000); /* read-low */
1862 __clear_bit(msr, va + 0x800); /* write-low */
1863 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1864 msr &= 0x1fff;
1865 __clear_bit(msr, va + 0x400); /* read-high */
1866 __clear_bit(msr, va + 0xc00); /* write-high */
1867 }
1868 kunmap(msr_bitmap);
1869}
1870
6aa8b732
AK		 1871/*
1872 * Sets up the vmcs for emulated real mode.
1873 */
8b9cf98c 1874static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1875{
1876 u32 host_sysenter_cs;
1877 u32 junk;
1878 unsigned long a;
1879 struct descriptor_table dt;
1880 int i;
cd2276a7 1881 unsigned long kvm_vmx_return;
6e5d865c 1882 u32 exec_control;
6aa8b732 1883
6aa8b732 1884 /* I/O */
fdef3ad1
HQ		 1885 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1886 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1887
25c5f225
SY		 1888 if (cpu_has_vmx_msr_bitmap())
1889 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1890
6aa8b732
AK		 1891 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1892
6aa8b732 1893 /* Control */
1c3d14fe
YS		 1894 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1895 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1896
1897 exec_control = vmcs_config.cpu_based_exec_ctrl;
1898 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1899 exec_control &= ~CPU_BASED_TPR_SHADOW;
1900#ifdef CONFIG_X86_64
1901 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1902 CPU_BASED_CR8_LOAD_EXITING;
1903#endif
1904 }
d56f546d
SY		 1905 if (!vm_need_ept())
1906 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1907 CPU_BASED_CR3_LOAD_EXITING;
6e5d865c 1908 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1909
83ff3b9d
SY		 1910 if (cpu_has_secondary_exec_ctrls()) {
1911 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1912 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1913 exec_control &=
1914 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 1915 if (vmx->vpid == 0)
1916 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
d56f546d
SY		 1917 if (!vm_need_ept())
1918 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
83ff3b9d
SY		 1919 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1920 }
f78e0e2e 1921
c7addb90
AK		 1922 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1923 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1924 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1925
1926 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1927 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1928 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1929
1930 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1931 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1932 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 1933 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
1934 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 1935 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1936#ifdef CONFIG_X86_64
6aa8b732
AK		 1937 rdmsrl(MSR_FS_BASE, a);
1938 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1939 rdmsrl(MSR_GS_BASE, a);
1940 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1941#else
1942 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1943 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1944#endif
1945
1946 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1947
d6e88aec 1948 kvm_get_idt(&dt);
6aa8b732
AK		 1949 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1950
d77c26fc 1951 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1952 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1953 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1954 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1955 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1956
1957 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1958 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1959 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1960 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1961 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1962 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1963
6aa8b732
AK		 1964 for (i = 0; i < NR_VMX_MSR; ++i) {
1965 u32 index = vmx_msr_index[i];
1966 u32 data_low, data_high;
1967 u64 data;
a2fa3e9f 1968 int j = vmx->nmsrs;
6aa8b732
AK		 1969
1970 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1971 continue;
432bd6cb
AK		 1972 if (wrmsr_safe(index, data_low, data_high) < 0)
1973 continue;
6aa8b732 1974 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1975 vmx->host_msrs[j].index = index;
1976 vmx->host_msrs[j].reserved = 0;
1977 vmx->host_msrs[j].data = data;
1978 vmx->guest_msrs[j] = vmx->host_msrs[j];
1979 ++vmx->nmsrs;
6aa8b732 1980 }
6aa8b732 1981
1c3d14fe 1982 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1983
1984 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1985 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1986
e00c8cf2
AK		 1987 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1988 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1989
f78e0e2e 1990
e00c8cf2
AK		 1991 return 0;
1992}
1993
b7ebfb05
SY		 1994static int init_rmode(struct kvm *kvm)
1995{
1996 if (!init_rmode_tss(kvm))
1997 return 0;
1998 if (!init_rmode_identity_map(kvm))
1999 return 0;
2000 return 1;
2001}
2002
e00c8cf2
AK		 2003static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2004{
2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
2006 u64 msr;
2007 int ret;
2008
5fdbf976 2009 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2010 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2011 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2012 ret = -ENOMEM;
2013 goto out;
2014 }
2015
ad312c7c 2016 vmx->vcpu.arch.rmode.active = 0;
e00c8cf2 2017
ad312c7c 2018 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2019 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2
AK		 2020 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2021 if (vmx->vcpu.vcpu_id == 0)
2022 msr |= MSR_IA32_APICBASE_BSP;
2023 kvm_set_apic_base(&vmx->vcpu, msr);
2024
2025 fx_init(&vmx->vcpu);
2026
2027 /*
2028 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2029 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2030 */
2031 if (vmx->vcpu.vcpu_id == 0) {
2032 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2033 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2034 } else {
ad312c7c
ZX		 2035 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2036 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2
AK		 2037 }
2038 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2039 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2040
2041 seg_setup(VCPU_SREG_DS);
2042 seg_setup(VCPU_SREG_ES);
2043 seg_setup(VCPU_SREG_FS);
2044 seg_setup(VCPU_SREG_GS);
2045 seg_setup(VCPU_SREG_SS);
2046
2047 vmcs_write16(GUEST_TR_SELECTOR, 0);
2048 vmcs_writel(GUEST_TR_BASE, 0);
2049 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2050 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2051
2052 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2053 vmcs_writel(GUEST_LDTR_BASE, 0);
2054 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2055 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2056
2057 vmcs_write32(GUEST_SYSENTER_CS, 0);
2058 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2059 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2060
2061 vmcs_writel(GUEST_RFLAGS, 0x02);
2062 if (vmx->vcpu.vcpu_id == 0)
5fdbf976 2063 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2064 else
5fdbf976
MT		 2065 kvm_rip_write(vcpu, 0);
2066 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2
AK		 2067
2068 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2069 vmcs_writel(GUEST_DR7, 0x400);
2070
2071 vmcs_writel(GUEST_GDTR_BASE, 0);
2072 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2073
2074 vmcs_writel(GUEST_IDTR_BASE, 0);
2075 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2076
2077 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2079 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2080
2081 guest_write_tsc(0);
2082
2083 /* Special registers */
2084 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2085
2086 setup_msrs(vmx);
2087
6aa8b732
AK		 2088 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2089
f78e0e2e
SY		 2090 if (cpu_has_vmx_tpr_shadow()) {
2091 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2092 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2093 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2094 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2095 vmcs_write32(TPR_THRESHOLD, 0);
2096 }
2097
2098 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2099 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2100 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2101
2384d2b3
SY		 2102 if (vmx->vpid != 0)
2103 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2104
ad312c7c
ZX		 2105 vmx->vcpu.arch.cr0 = 0x60000010;
2106 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2107 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2108 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2109 vmx_fpu_activate(&vmx->vcpu);
2110 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2111
2384d2b3
SY		 2112 vpid_sync_vcpu_all(vmx);
2113
3200f405 2114 ret = 0;
6aa8b732 2115
6aa8b732 2116out:
3200f405 2117 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2118 return ret;
2119}
2120
85f455f7
ED		 2121static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2122{
9c8cba37
AK		 2123 struct vcpu_vmx *vmx = to_vmx(vcpu);
2124
2714d1d3
FEL		 2125 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2126
ad312c7c 2127 if (vcpu->arch.rmode.active) {
9c8cba37
AK		 2128 vmx->rmode.irq.pending = true;
2129 vmx->rmode.irq.vector = irq;
5fdbf976 2130 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
9c5623e3
AK		 2131 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2132 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2133 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2134 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2135 return;
2136 }
2137 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2138 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2139}
2140
f08864b4
SY		 2141static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2142{
2143 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2144 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2145}
2146
6aa8b732
AK		 2147static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2148{
ad312c7c
ZX		 2149 int word_index = __ffs(vcpu->arch.irq_summary);
2150 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
6aa8b732
AK		 2151 int irq = word_index * BITS_PER_LONG + bit_index;
2152
ad312c7c
ZX		 2153 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2154 if (!vcpu->arch.irq_pending[word_index])
2155 clear_bit(word_index, &vcpu->arch.irq_summary);
85f455f7 2156 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 2157}
2158
c1150d8c
DL		 2159
2160static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2161 struct kvm_run *kvm_run)
6aa8b732 2162{
c1150d8c
DL		 2163 u32 cpu_based_vm_exec_control;
2164
ad312c7c 2165 vcpu->arch.interrupt_window_open =
c1150d8c
DL		 2166 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2167 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2168
ad312c7c
ZX		 2169 if (vcpu->arch.interrupt_window_open &&
2170 vcpu->arch.irq_summary &&
c1150d8c 2171 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 2172 /*
c1150d8c 2173 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 2174 */
2175 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 2176
2177 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
ad312c7c
ZX		 2178 if (!vcpu->arch.interrupt_window_open &&
2179 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 2180 /*
2181 * Interrupts blocked. Wait for unblock.
2182 */
c1150d8c
DL		 2183 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2184 else
2185 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2186 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 2187}
2188
cbc94022
IE		 2189static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2190{
2191 int ret;
2192 struct kvm_userspace_memory_region tss_mem = {
2193 .slot = 8,
2194 .guest_phys_addr = addr,
2195 .memory_size = PAGE_SIZE * 3,
2196 .flags = 0,
2197 };
2198
2199 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2200 if (ret)
2201 return ret;
bfc6d222 2202 kvm->arch.tss_addr = addr;
cbc94022
IE		 2203 return 0;
2204}
2205
6aa8b732
AK		 2206static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2207{
2208 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2209
2210 set_debugreg(dbg->bp[0], 0);
2211 set_debugreg(dbg->bp[1], 1);
2212 set_debugreg(dbg->bp[2], 2);
2213 set_debugreg(dbg->bp[3], 3);
2214
2215 if (dbg->singlestep) {
2216 unsigned long flags;
2217
2218 flags = vmcs_readl(GUEST_RFLAGS);
2219 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2220 vmcs_writel(GUEST_RFLAGS, flags);
2221 }
2222}
2223
2224static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2225 int vec, u32 err_code)
2226{
b3f37707
NK		 2227 /*
2228 * Instruction with address size override prefix opcode 0x67
2229 * Cause the #SS fault with 0 error code in VM86 mode.
2230 */
2231 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 2232 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 2233 return 1;
2234 return 0;
2235}
2236
2237static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2238{
1155f76a 2239 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2240 u32 intr_info, error_code;
2241 unsigned long cr2, rip;
2242 u32 vect_info;
2243 enum emulation_result er;
2244
1155f76a 2245 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2246 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2247
2248 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 2249 !is_page_fault(intr_info))
6aa8b732 2250 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
b8688d51 2251 "intr info 0x%x\n", __func__, vect_info, intr_info);
6aa8b732 2252
85f455f7 2253 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732 2254 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
ad312c7c
ZX		 2255 set_bit(irq, vcpu->arch.irq_pending);
2256 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
6aa8b732
AK		 2257 }
2258
1b6269db
AK		 2259 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2260 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2261
2262 if (is_no_device(intr_info)) {
5fd86fcf 2263 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2264 return 1;
2265 }
2266
7aa81cc0 2267 if (is_invalid_opcode(intr_info)) {
571008da 2268 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2269 if (er != EMULATE_DONE)
7ee5d940 2270 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2271 return 1;
2272 }
2273
6aa8b732 2274 error_code = 0;
5fdbf976 2275 rip = kvm_rip_read(vcpu);
2e11384c 2276 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2277 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2278 if (is_page_fault(intr_info)) {
1439442c
SY		 2279 /* EPT won't cause page fault directly */
2280 if (vm_need_ept())
2281 BUG();
6aa8b732 2282 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2714d1d3
FEL		 2283 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2284 (u32)((u64)cr2 >> 32), handler);
f7d9238f 2285 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
577bdc49 2286 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2287 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2288 }
2289
ad312c7c 2290 if (vcpu->arch.rmode.active &&
6aa8b732 2291 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2292 error_code)) {
ad312c7c
ZX		 2293 if (vcpu->arch.halt_request) {
2294 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2295 return kvm_emulate_halt(vcpu);
2296 }
6aa8b732 2297 return 1;
72d6e5a0 2298 }
6aa8b732 2299
d77c26fc
MD		 2300 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2301 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 2302 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2303 return 0;
2304 }
2305 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2306 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2307 kvm_run->ex.error_code = error_code;
2308 return 0;
2309}
2310
2311static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2312 struct kvm_run *kvm_run)
2313{
1165f5fe 2314 ++vcpu->stat.irq_exits;
2714d1d3 2315 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
6aa8b732
AK		 2316 return 1;
2317}
2318
988ad74f
AK		 2319static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2320{
2321 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2322 return 0;
2323}
6aa8b732 2324
6aa8b732
AK		 2325static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2326{
bfdaab09 2327 unsigned long exit_qualification;
039576c0
AK		 2328 int size, down, in, string, rep;
2329 unsigned port;
6aa8b732 2330
1165f5fe 2331 ++vcpu->stat.io_exits;
bfdaab09 2332 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2333 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2334
2335 if (string) {
3427318f
LV		 2336 if (emulate_instruction(vcpu,
2337 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2338 return 0;
2339 return 1;
2340 }
2341
2342 size = (exit_qualification & 7) + 1;
2343 in = (exit_qualification & 8) != 0;
039576c0 2344 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 2345 rep = (exit_qualification & 32) != 0;
2346 port = exit_qualification >> 16;
e70669ab 2347
3090dd73 2348 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 2349}
2350
102d8325
IM		 2351static void
2352vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2353{
2354 /*
2355 * Patch in the VMCALL instruction:
2356 */
2357 hypercall[0] = 0x0f;
2358 hypercall[1] = 0x01;
2359 hypercall[2] = 0xc1;
102d8325
IM		 2360}
2361
6aa8b732
AK		 2362static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2363{
bfdaab09 2364 unsigned long exit_qualification;
6aa8b732
AK		 2365 int cr;
2366 int reg;
2367
bfdaab09 2368 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2369 cr = exit_qualification & 15;
2370 reg = (exit_qualification >> 8) & 15;
2371 switch ((exit_qualification >> 4) & 3) {
2372 case 0: /* mov to cr */
5fdbf976
MT		 2373 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2374 (u32)kvm_register_read(vcpu, reg),
2375 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2376 handler);
6aa8b732
AK		 2377 switch (cr) {
2378 case 0:
5fdbf976 2379 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2380 skip_emulated_instruction(vcpu);
2381 return 1;
2382 case 3:
5fdbf976 2383 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2384 skip_emulated_instruction(vcpu);
2385 return 1;
2386 case 4:
5fdbf976 2387 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
6aa8b732
AK		 2388 skip_emulated_instruction(vcpu);
2389 return 1;
2390 case 8:
5fdbf976 2391 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
6aa8b732 2392 skip_emulated_instruction(vcpu);
e5314067
AK		 2393 if (irqchip_in_kernel(vcpu->kvm))
2394 return 1;
253abdee
YS		 2395 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2396 return 0;
6aa8b732
AK		 2397 };
2398 break;
25c4c276 2399 case 2: /* clts */
5fd86fcf 2400 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2401 vcpu->arch.cr0 &= ~X86_CR0_TS;
2402 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2403 vmx_fpu_activate(vcpu);
2714d1d3 2404 KVMTRACE_0D(CLTS, vcpu, handler);
25c4c276
AL		 2405 skip_emulated_instruction(vcpu);
2406 return 1;
6aa8b732
AK		 2407 case 1: /*mov from cr*/
2408 switch (cr) {
2409 case 3:
5fdbf976 2410 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2714d1d3 2411 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
5fdbf976
MT		 2412 (u32)kvm_register_read(vcpu, reg),
2413 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2714d1d3 2414 handler);
6aa8b732
AK		 2415 skip_emulated_instruction(vcpu);
2416 return 1;
2417 case 8:
5fdbf976 2418 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2714d1d3 2419 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
5fdbf976 2420 (u32)kvm_register_read(vcpu, reg), handler);
6aa8b732
AK		 2421 skip_emulated_instruction(vcpu);
2422 return 1;
2423 }
2424 break;
2425 case 3: /* lmsw */
2d3ad1f4 2426 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2427
2428 skip_emulated_instruction(vcpu);
2429 return 1;
2430 default:
2431 break;
2432 }
2433 kvm_run->exit_reason = 0;
f0242478 2434 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2435 (int)(exit_qualification >> 4) & 3, cr);
2436 return 0;
2437}
2438
2439static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2440{
bfdaab09 2441 unsigned long exit_qualification;
6aa8b732
AK		 2442 unsigned long val;
2443 int dr, reg;
2444
2445 /*
2446 * FIXME: this code assumes the host is debugging the guest.
2447 * need to deal with guest debugging itself too.
2448 */
bfdaab09 2449 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2450 dr = exit_qualification & 7;
2451 reg = (exit_qualification >> 8) & 15;
6aa8b732
AK		 2452 if (exit_qualification & 16) {
2453 /* mov from dr */
2454 switch (dr) {
2455 case 6:
2456 val = 0xffff0ff0;
2457 break;
2458 case 7:
2459 val = 0x400;
2460 break;
2461 default:
2462 val = 0;
2463 }
5fdbf976 2464 kvm_register_write(vcpu, reg, val);
2714d1d3 2465 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
6aa8b732
AK		 2466 } else {
2467 /* mov to dr */
2468 }
6aa8b732
AK		 2469 skip_emulated_instruction(vcpu);
2470 return 1;
2471}
2472
2473static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2474{
06465c5a
AK		 2475 kvm_emulate_cpuid(vcpu);
2476 return 1;
6aa8b732
AK		 2477}
2478
2479static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2480{
ad312c7c 2481 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 2482 u64 data;
2483
2484 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 2485 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2486 return 1;
2487 }
2488
2714d1d3
FEL		 2489 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2490 handler);
2491
6aa8b732 2492 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 2493 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2494 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 2495 skip_emulated_instruction(vcpu);
2496 return 1;
2497}
2498
2499static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2500{
ad312c7c
ZX		 2501 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2502 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2503 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 2504
2714d1d3
FEL		 2505 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2506 handler);
2507
6aa8b732 2508 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 2509 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 2510 return 1;
2511 }
2512
2513 skip_emulated_instruction(vcpu);
2514 return 1;
2515}
2516
6e5d865c
YS		 2517static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2518 struct kvm_run *kvm_run)
2519{
2520 return 1;
2521}
2522
6aa8b732
AK		 2523static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2524 struct kvm_run *kvm_run)
2525{
85f455f7
ED		 2526 u32 cpu_based_vm_exec_control;
2527
2528 /* clear pending irq */
2529 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2530 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2531 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3
FEL		 2532
2533 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2534
c1150d8c
DL		 2535 /*
2536 * If the user space waits to inject interrupts, exit as soon as
2537 * possible
2538 */
2539 if (kvm_run->request_interrupt_window &&
ad312c7c 2540 !vcpu->arch.irq_summary) {
c1150d8c 2541 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2542 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2543 return 0;
2544 }
6aa8b732
AK		 2545 return 1;
2546}
2547
2548static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2549{
2550 skip_emulated_instruction(vcpu);
d3bef15f 2551 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2552}
2553
c21415e8
IM		 2554static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2555{
510043da 2556 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2557 kvm_emulate_hypercall(vcpu);
2558 return 1;
c21415e8
IM		 2559}
2560
e5edaa01
ED		 2561static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2562{
2563 skip_emulated_instruction(vcpu);
2564 /* TODO: Add support for VT-d/pass-through device */
2565 return 1;
2566}
2567
f78e0e2e
SY		 2568static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2569{
2570 u64 exit_qualification;
2571 enum emulation_result er;
2572 unsigned long offset;
2573
2574 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2575 offset = exit_qualification & 0xffful;
2576
2577 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2578
2579 if (er != EMULATE_DONE) {
2580 printk(KERN_ERR
2581 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2582 offset);
2583 return -ENOTSUPP;
2584 }
2585 return 1;
2586}
2587
37817f29
IE		 2588static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2589{
2590 unsigned long exit_qualification;
2591 u16 tss_selector;
2592 int reason;
2593
2594 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2595
2596 reason = (u32)exit_qualification >> 30;
2597 tss_selector = exit_qualification;
2598
2599 return kvm_task_switch(vcpu, tss_selector, reason);
2600}
2601
1439442c
SY		 2602static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2603{
2604 u64 exit_qualification;
2605 enum emulation_result er;
2606 gpa_t gpa;
2607 unsigned long hva;
2608 int gla_validity;
2609 int r;
2610
2611 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2612
2613 if (exit_qualification & (1 << 6)) {
2614 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2615 return -ENOTSUPP;
2616 }
2617
2618 gla_validity = (exit_qualification >> 7) & 0x3;
2619 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2620 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2621 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2622 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2623 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2624 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2625 (long unsigned int)exit_qualification);
2626 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2627 kvm_run->hw.hardware_exit_reason = 0;
2628 return -ENOTSUPP;
2629 }
2630
2631 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2632 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2633 if (!kvm_is_error_hva(hva)) {
2634 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2635 if (r < 0) {
2636 printk(KERN_ERR "EPT: Not enough memory!\n");
2637 return -ENOMEM;
2638 }
2639 return 1;
2640 } else {
2641 /* must be MMIO */
2642 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2643
2644 if (er == EMULATE_FAIL) {
2645 printk(KERN_ERR
2646 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2647 er);
2648 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2649 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2650 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2651 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2652 (long unsigned int)exit_qualification);
2653 return -ENOTSUPP;
2654 } else if (er == EMULATE_DO_MMIO)
2655 return 0;
2656 }
2657 return 1;
2658}
2659
f08864b4
SY		 2660static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2661{
2662 u32 cpu_based_vm_exec_control;
2663
2664 /* clear pending NMI */
2665 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2666 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2667 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2668 ++vcpu->stat.nmi_window_exits;
2669
2670 return 1;
2671}
2672
6aa8b732
AK		 2673/*
2674 * The exit handlers return 1 if the exit was handled fully and guest execution
2675 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2676 * to be done to userspace and return 0.
2677 */
2678static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2679 struct kvm_run *kvm_run) = {
2680 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2681 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2682 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 2683 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 2684 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2685 [EXIT_REASON_CR_ACCESS] = handle_cr,
2686 [EXIT_REASON_DR_ACCESS] = handle_dr,
2687 [EXIT_REASON_CPUID] = handle_cpuid,
2688 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2689 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2690 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2691 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2692 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2693 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2694 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 2695 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 2696 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
1439442c 2697 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6aa8b732
AK		 2698};
2699
2700static const int kvm_vmx_max_exit_handlers =
50a3485c 2701 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2702
2703/*
2704 * The guest has exited. See if we can fix it or if we need userspace
2705 * assistance.
2706 */
2707static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2708{
6aa8b732 2709 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78 2710 struct vcpu_vmx *vmx = to_vmx(vcpu);
1155f76a 2711 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 2712
5fdbf976
MT		 2713 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
2714 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
2714d1d3 2715
1439442c
SY		 2716 /* Access CR3 don't cause VMExit in paging mode, so we need
2717 * to sync with guest real CR3. */
2718 if (vm_need_ept() && is_paging(vcpu)) {
2719 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2720 ept_load_pdptrs(vcpu);
2721 }
2722
29bd8a78
AK		 2723 if (unlikely(vmx->fail)) {
2724 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2725 kvm_run->fail_entry.hardware_entry_failure_reason
2726 = vmcs_read32(VM_INSTRUCTION_ERROR);
2727 return 0;
2728 }
6aa8b732 2729
d77c26fc 2730 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c
SY		 2731 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2732 exit_reason != EXIT_REASON_EPT_VIOLATION))
6aa8b732 2733 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
b8688d51 2734 "exit reason is 0x%x\n", __func__, exit_reason);
6aa8b732
AK		 2735 if (exit_reason < kvm_vmx_max_exit_handlers
2736 && kvm_vmx_exit_handlers[exit_reason])
2737 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2738 else {
2739 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2740 kvm_run->hw.hardware_exit_reason = exit_reason;
2741 }
2742 return 0;
2743}
2744
6e5d865c
YS		 2745static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2746{
2747 int max_irr, tpr;
2748
2749 if (!vm_need_tpr_shadow(vcpu->kvm))
2750 return;
2751
2752 if (!kvm_lapic_enabled(vcpu) ||
2753 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2754 vmcs_write32(TPR_THRESHOLD, 0);
2755 return;
2756 }
2757
2758 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2759 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2760}
2761
85f455f7
ED		 2762static void enable_irq_window(struct kvm_vcpu *vcpu)
2763{
2764 u32 cpu_based_vm_exec_control;
2765
2766 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2767 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2768 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2769}
2770
f08864b4
SY		 2771static void enable_nmi_window(struct kvm_vcpu *vcpu)
2772{
2773 u32 cpu_based_vm_exec_control;
2774
2775 if (!cpu_has_virtual_nmis())
2776 return;
2777
2778 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2779 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2780 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2781}
2782
2783static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2784{
2785 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2786 return !(guest_intr & (GUEST_INTR_STATE_NMI |
2787 GUEST_INTR_STATE_MOV_SS |
2788 GUEST_INTR_STATE_STI));
2789}
2790
2791static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2792{
2793 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2794 return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2795 GUEST_INTR_STATE_STI)) &&
2796 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2797}
2798
2799static void enable_intr_window(struct kvm_vcpu *vcpu)
2800{
2801 if (vcpu->arch.nmi_pending)
2802 enable_nmi_window(vcpu);
2803 else if (kvm_cpu_has_interrupt(vcpu))
2804 enable_irq_window(vcpu);
2805}
2806
cf393f75
AK		 2807static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
2808{
2809 u32 exit_intr_info;
668f612f 2810 u32 idt_vectoring_info;
cf393f75
AK		 2811 bool unblock_nmi;
2812 u8 vector;
668f612f
AK		 2813 int type;
2814 bool idtv_info_valid;
35920a35 2815 u32 error;
cf393f75
AK		 2816
2817 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2818 if (cpu_has_virtual_nmis()) {
2819 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
2820 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
2821 /*
2822 * SDM 3: 25.7.1.2
2823 * Re-set bit "block by NMI" before VM entry if vmexit caused by
2824 * a guest IRET fault.
2825 */
2826 if (unblock_nmi && vector != DF_VECTOR)
2827 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2828 GUEST_INTR_STATE_NMI);
2829 }
668f612f
AK		 2830
2831 idt_vectoring_info = vmx->idt_vectoring_info;
2832 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
2833 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
2834 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
2835 if (vmx->vcpu.arch.nmi_injected) {
2836 /*
2837 * SDM 3: 25.7.1.2
2838 * Clear bit "block by NMI" before VM entry if a NMI delivery
2839 * faulted.
2840 */
2841 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
2842 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2843 GUEST_INTR_STATE_NMI);
2844 else
2845 vmx->vcpu.arch.nmi_injected = false;
2846 }
35920a35
AK		 2847 kvm_clear_exception_queue(&vmx->vcpu);
2848 if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) {
2849 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
2850 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
2851 kvm_queue_exception_e(&vmx->vcpu, vector, error);
2852 } else
2853 kvm_queue_exception(&vmx->vcpu, vector);
2854 vmx->idt_vectoring_info = 0;
2855 }
f7d9238f
AK		 2856 kvm_clear_interrupt_queue(&vmx->vcpu);
2857 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
2858 kvm_queue_interrupt(&vmx->vcpu, vector);
2859 vmx->idt_vectoring_info = 0;
2860 }
cf393f75
AK		 2861}
2862
85f455f7
ED		 2863static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2864{
f7d9238f 2865 u32 intr_info_field;
85f455f7 2866
6e5d865c
YS		 2867 update_tpr_threshold(vcpu);
2868
85f455f7 2869 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
f08864b4 2870 if (cpu_has_virtual_nmis()) {
668f612f
AK		 2871 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2872 if (vmx_nmi_enabled(vcpu)) {
2873 vcpu->arch.nmi_pending = false;
2874 vcpu->arch.nmi_injected = true;
2875 } else {
2876 enable_intr_window(vcpu);
2877 return;
2878 }
2879 }
2880 if (vcpu->arch.nmi_injected) {
2881 vmx_inject_nmi(vcpu);
f08864b4
SY		 2882 enable_intr_window(vcpu);
2883 return;
2884 }
f08864b4 2885 }
f7d9238f
AK		 2886 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
2887 if (vmx_irq_enabled(vcpu))
2888 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
2889 else
2890 enable_irq_window(vcpu);
2891 }
2892 if (vcpu->arch.interrupt.pending) {
2893 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2894 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
2895 }
85f455f7
ED		 2896}
2897
9c8cba37
AK		 2898/*
2899 * Failure to inject an interrupt should give us the information
2900 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2901 * when fetching the interrupt redirection bitmap in the real-mode
2902 * tss, this doesn't happen. So we do it ourselves.
2903 */
2904static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2905{
2906 vmx->rmode.irq.pending = 0;
5fdbf976 2907 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 2908 return;
5fdbf976 2909 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 2910 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2911 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2912 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2913 return;
2914 }
2915 vmx->idt_vectoring_info =
2916 VECTORING_INFO_VALID_MASK
2917 | INTR_TYPE_EXT_INTR
2918 | vmx->rmode.irq.vector;
2919}
2920
04d2cc77 2921static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2922{
a2fa3e9f 2923 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2924 u32 intr_info;
e6adf283 2925
5fdbf976
MT		 2926 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
2927 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
2928 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
2929 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
2930
e6adf283
AK		 2931 /*
2932 * Loading guest fpu may have cleared host cr0.ts
2933 */
2934 vmcs_writel(HOST_CR0, read_cr0());
2935
d77c26fc 2936 asm(
6aa8b732 2937 /* Store host registers */
05b3e0c2 2938#ifdef CONFIG_X86_64
c2036300 2939 "push %%rdx; push %%rbp;"
6aa8b732 2940 "push %%rcx \n\t"
6aa8b732 2941#else
ff593e5a
LV		 2942 "push %%edx; push %%ebp;"
2943 "push %%ecx \n\t"
6aa8b732 2944#endif
4ecac3fd 2945 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6aa8b732 2946 /* Check if vmlaunch of vmresume is needed */
e08aa78a 2947 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 2948 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2949#ifdef CONFIG_X86_64
e08aa78a 2950 "mov %c[cr2](%0), %%rax \n\t"
6aa8b732 2951 "mov %%rax, %%cr2 \n\t"
e08aa78a
AK		 2952 "mov %c[rax](%0), %%rax \n\t"
2953 "mov %c[rbx](%0), %%rbx \n\t"
2954 "mov %c[rdx](%0), %%rdx \n\t"
2955 "mov %c[rsi](%0), %%rsi \n\t"
2956 "mov %c[rdi](%0), %%rdi \n\t"
2957 "mov %c[rbp](%0), %%rbp \n\t"
2958 "mov %c[r8](%0), %%r8 \n\t"
2959 "mov %c[r9](%0), %%r9 \n\t"
2960 "mov %c[r10](%0), %%r10 \n\t"
2961 "mov %c[r11](%0), %%r11 \n\t"
2962 "mov %c[r12](%0), %%r12 \n\t"
2963 "mov %c[r13](%0), %%r13 \n\t"
2964 "mov %c[r14](%0), %%r14 \n\t"
2965 "mov %c[r15](%0), %%r15 \n\t"
2966 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
6aa8b732 2967#else
e08aa78a 2968 "mov %c[cr2](%0), %%eax \n\t"
6aa8b732 2969 "mov %%eax, %%cr2 \n\t"
e08aa78a
AK		 2970 "mov %c[rax](%0), %%eax \n\t"
2971 "mov %c[rbx](%0), %%ebx \n\t"
2972 "mov %c[rdx](%0), %%edx \n\t"
2973 "mov %c[rsi](%0), %%esi \n\t"
2974 "mov %c[rdi](%0), %%edi \n\t"
2975 "mov %c[rbp](%0), %%ebp \n\t"
2976 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
6aa8b732
AK		 2977#endif
2978 /* Enter guest mode */
cd2276a7 2979 "jne .Llaunched \n\t"
4ecac3fd 2980 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 2981 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 2982 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 2983 ".Lkvm_vmx_return: "
6aa8b732 2984 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2985#ifdef CONFIG_X86_64
e08aa78a
AK		 2986 "xchg %0, (%%rsp) \n\t"
2987 "mov %%rax, %c[rax](%0) \n\t"
2988 "mov %%rbx, %c[rbx](%0) \n\t"
2989 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2990 "mov %%rdx, %c[rdx](%0) \n\t"
2991 "mov %%rsi, %c[rsi](%0) \n\t"
2992 "mov %%rdi, %c[rdi](%0) \n\t"
2993 "mov %%rbp, %c[rbp](%0) \n\t"
2994 "mov %%r8, %c[r8](%0) \n\t"
2995 "mov %%r9, %c[r9](%0) \n\t"
2996 "mov %%r10, %c[r10](%0) \n\t"
2997 "mov %%r11, %c[r11](%0) \n\t"
2998 "mov %%r12, %c[r12](%0) \n\t"
2999 "mov %%r13, %c[r13](%0) \n\t"
3000 "mov %%r14, %c[r14](%0) \n\t"
3001 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3002 "mov %%cr2, %%rax \n\t"
e08aa78a 3003 "mov %%rax, %c[cr2](%0) \n\t"
6aa8b732 3004
e08aa78a 3005 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
6aa8b732 3006#else
e08aa78a
AK		 3007 "xchg %0, (%%esp) \n\t"
3008 "mov %%eax, %c[rax](%0) \n\t"
3009 "mov %%ebx, %c[rbx](%0) \n\t"
3010 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3011 "mov %%edx, %c[rdx](%0) \n\t"
3012 "mov %%esi, %c[rsi](%0) \n\t"
3013 "mov %%edi, %c[rdi](%0) \n\t"
3014 "mov %%ebp, %c[rbp](%0) \n\t"
6aa8b732 3015 "mov %%cr2, %%eax \n\t"
e08aa78a 3016 "mov %%eax, %c[cr2](%0) \n\t"
6aa8b732 3017
e08aa78a 3018 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
6aa8b732 3019#endif
e08aa78a
AK		 3020 "setbe %c[fail](%0) \n\t"
3021 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3022 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3023 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
ad312c7c
ZX		 3024 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3025 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3026 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3027 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3028 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3029 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3030 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3031#ifdef CONFIG_X86_64
ad312c7c
ZX		 3032 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3033 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3034 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3035 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3036 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3037 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3038 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3039 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3040#endif
ad312c7c 3041 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300
LV		 3042 : "cc", "memory"
3043#ifdef CONFIG_X86_64
3044 , "rbx", "rdi", "rsi"
3045 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 3046#else
3047 , "ebx", "edi", "rsi"
c2036300
LV		 3048#endif
3049 );
6aa8b732 3050
5fdbf976
MT		 3051 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3052 vcpu->arch.regs_dirty = 0;
3053
1155f76a 3054 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3055 if (vmx->rmode.irq.pending)
3056 fixup_rmode_irq(vmx);
1155f76a 3057
ad312c7c 3058 vcpu->arch.interrupt_window_open =
f08864b4
SY		 3059 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3060 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
6aa8b732 3061
d77c26fc 3062 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3063 vmx->launched = 1;
1b6269db
AK		 3064
3065 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3066
3067 /* We need to handle NMIs before interrupts are enabled */
f08864b4
SY		 3068 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3069 (intr_info & INTR_INFO_VALID_MASK)) {
2714d1d3 3070 KVMTRACE_0D(NMI, vcpu, handler);
1b6269db 3071 asm("int $2");
2714d1d3 3072 }
cf393f75
AK		 3073
3074 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3075}
3076
6aa8b732
AK		 3077static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3078{
a2fa3e9f
GH		 3079 struct vcpu_vmx *vmx = to_vmx(vcpu);
3080
3081 if (vmx->vmcs) {
543e4243 3082 vcpu_clear(vmx);
a2fa3e9f
GH		 3083 free_vmcs(vmx->vmcs);
3084 vmx->vmcs = NULL;
6aa8b732
AK		 3085 }
3086}
3087
3088static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3089{
fb3f0f51
RR		 3090 struct vcpu_vmx *vmx = to_vmx(vcpu);
3091
2384d2b3
SY		 3092 spin_lock(&vmx_vpid_lock);
3093 if (vmx->vpid != 0)
3094 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3095 spin_unlock(&vmx_vpid_lock);
6aa8b732 3096 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3097 kfree(vmx->host_msrs);
3098 kfree(vmx->guest_msrs);
3099 kvm_vcpu_uninit(vcpu);
a4770347 3100 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3101}
3102
fb3f0f51 3103static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3104{
fb3f0f51 3105 int err;
c16f862d 3106 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3107 int cpu;
6aa8b732 3108
a2fa3e9f 3109 if (!vmx)
fb3f0f51
RR		 3110 return ERR_PTR(-ENOMEM);
3111
2384d2b3
SY		 3112 allocate_vpid(vmx);
3113
fb3f0f51
RR		 3114 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3115 if (err)
3116 goto free_vcpu;
965b58a5 3117
a2fa3e9f 3118 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3119 if (!vmx->guest_msrs) {
3120 err = -ENOMEM;
3121 goto uninit_vcpu;
3122 }
965b58a5 3123
a2fa3e9f
GH		 3124 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3125 if (!vmx->host_msrs)
fb3f0f51 3126 goto free_guest_msrs;
965b58a5 3127
a2fa3e9f
GH		 3128 vmx->vmcs = alloc_vmcs();
3129 if (!vmx->vmcs)
fb3f0f51 3130 goto free_msrs;
a2fa3e9f
GH		 3131
3132 vmcs_clear(vmx->vmcs);
3133
15ad7146
AK		 3134 cpu = get_cpu();
3135 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3136 err = vmx_vcpu_setup(vmx);
fb3f0f51 3137 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3138 put_cpu();
fb3f0f51
RR		 3139 if (err)
3140 goto free_vmcs;
5e4a0b3c
MT		 3141 if (vm_need_virtualize_apic_accesses(kvm))
3142 if (alloc_apic_access_page(kvm) != 0)
3143 goto free_vmcs;
fb3f0f51 3144
b7ebfb05
SY		 3145 if (vm_need_ept())
3146 if (alloc_identity_pagetable(kvm) != 0)
3147 goto free_vmcs;
3148
fb3f0f51
RR		 3149 return &vmx->vcpu;
3150
3151free_vmcs:
3152 free_vmcs(vmx->vmcs);
3153free_msrs:
3154 kfree(vmx->host_msrs);
3155free_guest_msrs:
3156 kfree(vmx->guest_msrs);
3157uninit_vcpu:
3158 kvm_vcpu_uninit(&vmx->vcpu);
3159free_vcpu:
a4770347 3160 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3161 return ERR_PTR(err);
6aa8b732
AK		 3162}
3163
002c7f7c
YS		 3164static void __init vmx_check_processor_compat(void *rtn)
3165{
3166 struct vmcs_config vmcs_conf;
3167
3168 *(int *)rtn = 0;
3169 if (setup_vmcs_config(&vmcs_conf) < 0)
3170 *(int *)rtn = -EIO;
3171 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3172 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3173 smp_processor_id());
3174 *(int *)rtn = -EIO;
3175 }
3176}
3177
67253af5
SY		 3178static int get_ept_level(void)
3179{
3180 return VMX_EPT_DEFAULT_GAW + 1;
3181}
3182
cbdd1bea 3183static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3184 .cpu_has_kvm_support = cpu_has_kvm_support,
3185 .disabled_by_bios = vmx_disabled_by_bios,
3186 .hardware_setup = hardware_setup,
3187 .hardware_unsetup = hardware_unsetup,
002c7f7c 3188 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3189 .hardware_enable = hardware_enable,
3190 .hardware_disable = hardware_disable,
774ead3a 3191 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
6aa8b732
AK		 3192
3193 .vcpu_create = vmx_create_vcpu,
3194 .vcpu_free = vmx_free_vcpu,
04d2cc77 3195 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 3196
04d2cc77 3197 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 3198 .vcpu_load = vmx_vcpu_load,
3199 .vcpu_put = vmx_vcpu_put,
3200
3201 .set_guest_debug = set_guest_debug,
04d2cc77 3202 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 3203 .get_msr = vmx_get_msr,
3204 .set_msr = vmx_set_msr,
3205 .get_segment_base = vmx_get_segment_base,
3206 .get_segment = vmx_get_segment,
3207 .set_segment = vmx_set_segment,
2e4d2653 3208 .get_cpl = vmx_get_cpl,
6aa8b732 3209 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 3210 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 3211 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 3212 .set_cr3 = vmx_set_cr3,
3213 .set_cr4 = vmx_set_cr4,
6aa8b732 3214 .set_efer = vmx_set_efer,
6aa8b732
AK		 3215 .get_idt = vmx_get_idt,
3216 .set_idt = vmx_set_idt,
3217 .get_gdt = vmx_get_gdt,
3218 .set_gdt = vmx_set_gdt,
5fdbf976 3219 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 3220 .get_rflags = vmx_get_rflags,
3221 .set_rflags = vmx_set_rflags,
3222
3223 .tlb_flush = vmx_flush_tlb,
6aa8b732 3224
6aa8b732 3225 .run = vmx_vcpu_run,
04d2cc77 3226 .handle_exit = kvm_handle_exit,
6aa8b732 3227 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 3228 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 3229 .get_irq = vmx_get_irq,
3230 .set_irq = vmx_inject_irq,
298101da
AK		 3231 .queue_exception = vmx_queue_exception,
3232 .exception_injected = vmx_exception_injected,
04d2cc77
AK		 3233 .inject_pending_irq = vmx_intr_assist,
3234 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 3235
3236 .set_tss_addr = vmx_set_tss_addr,
67253af5 3237 .get_tdp_level = get_ept_level,
6aa8b732
AK		 3238};
3239
3240static int __init vmx_init(void)
3241{
25c5f225 3242 void *va;
fdef3ad1
HQ		 3243 int r;
3244
3245 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3246 if (!vmx_io_bitmap_a)
3247 return -ENOMEM;
3248
3249 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3250 if (!vmx_io_bitmap_b) {
3251 r = -ENOMEM;
3252 goto out;
3253 }
3254
25c5f225
SY		 3255 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3256 if (!vmx_msr_bitmap) {
3257 r = -ENOMEM;
3258 goto out1;
3259 }
3260
fdef3ad1
HQ		 3261 /*
3262 * Allow direct access to the PC debug port (it is often used for I/O
3263 * delays, but the vmexits simply slow things down).
3264 */
25c5f225
SY		 3265 va = kmap(vmx_io_bitmap_a);
3266 memset(va, 0xff, PAGE_SIZE);
3267 clear_bit(0x80, va);
cd0536d7 3268 kunmap(vmx_io_bitmap_a);
fdef3ad1 3269
25c5f225
SY		 3270 va = kmap(vmx_io_bitmap_b);
3271 memset(va, 0xff, PAGE_SIZE);
cd0536d7 3272 kunmap(vmx_io_bitmap_b);
fdef3ad1 3273
25c5f225
SY		 3274 va = kmap(vmx_msr_bitmap);
3275 memset(va, 0xff, PAGE_SIZE);
3276 kunmap(vmx_msr_bitmap);
3277
2384d2b3
SY		 3278 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3279
cb498ea2 3280 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 3281 if (r)
25c5f225
SY		 3282 goto out2;
3283
3284 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3285 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3286 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3287 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3288 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
fdef3ad1 3289
5fdbcb9d 3290 if (vm_need_ept()) {
1439442c 3291 bypass_guest_pf = 0;
5fdbcb9d
SY		 3292 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3293 VMX_EPT_WRITABLE_MASK |
3294 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
534e38b4 3295 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5fdbcb9d
SY		 3296 VMX_EPT_EXECUTABLE_MASK);
3297 kvm_enable_tdp();
3298 } else
3299 kvm_disable_tdp();
1439442c 3300
c7addb90
AK		 3301 if (bypass_guest_pf)
3302 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3303
1439442c
SY		 3304 ept_sync_global();
3305
fdef3ad1
HQ		 3306 return 0;
3307
25c5f225
SY		 3308out2:
3309 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3310out1:
3311 __free_page(vmx_io_bitmap_b);
3312out:
3313 __free_page(vmx_io_bitmap_a);
3314 return r;
6aa8b732
AK		 3315}
3316
3317static void __exit vmx_exit(void)
3318{
25c5f225 3319 __free_page(vmx_msr_bitmap);
fdef3ad1
HQ		 3320 __free_page(vmx_io_bitmap_b);
3321 __free_page(vmx_io_bitmap_a);
3322
cb498ea2 3323 kvm_exit();
6aa8b732
AK		 3324}
3325
3326module_init(vmx_init)
3327module_exit(vmx_exit)
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