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KVM: VMX: Cleanup redundant code in MSR set
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
6aa8b732 20#include <linux/module.h>
9d8f549d 21#include <linux/kernel.h>
6aa8b732
AK		 22#include <linux/mm.h>
23#include <linux/highmem.h>
07031e14 24#include <linux/profile.h>
e8edc6e0 25#include <linux/sched.h>
6aa8b732 26#include <asm/io.h>
3b3be0d1 27#include <asm/desc.h>
6aa8b732
AK		 28
29#include "segment_descriptor.h"
30
6aa8b732
AK		 31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
fdef3ad1
HQ		 37static struct page *vmx_io_bitmap_a;
38static struct page *vmx_io_bitmap_b;
39
05b3e0c2 40#ifdef CONFIG_X86_64
6aa8b732
AK		 41#define HOST_IS_64 1
42#else
43#define HOST_IS_64 0
44#endif
45
46static struct vmcs_descriptor {
47 int size;
48 int order;
49 u32 revision_id;
50} vmcs_descriptor;
51
52#define VMX_SEGMENT_FIELD(seg) \
53 [VCPU_SREG_##seg] = { \
54 .selector = GUEST_##seg##_SELECTOR, \
55 .base = GUEST_##seg##_BASE, \
56 .limit = GUEST_##seg##_LIMIT, \
57 .ar_bytes = GUEST_##seg##_AR_BYTES, \
58 }
59
60static struct kvm_vmx_segment_field {
61 unsigned selector;
62 unsigned base;
63 unsigned limit;
64 unsigned ar_bytes;
65} kvm_vmx_segment_fields[] = {
66 VMX_SEGMENT_FIELD(CS),
67 VMX_SEGMENT_FIELD(DS),
68 VMX_SEGMENT_FIELD(ES),
69 VMX_SEGMENT_FIELD(FS),
70 VMX_SEGMENT_FIELD(GS),
71 VMX_SEGMENT_FIELD(SS),
72 VMX_SEGMENT_FIELD(TR),
73 VMX_SEGMENT_FIELD(LDTR),
74};
75
4d56c8a7
AK		 76/*
77 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
78 * away by decrementing the array size.
79 */
6aa8b732 80static const u32 vmx_msr_index[] = {
05b3e0c2 81#ifdef CONFIG_X86_64
6aa8b732
AK		 82 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
83#endif
84 MSR_EFER, MSR_K6_STAR,
85};
9d8f549d 86#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 87
6aa8b732
AK		 88static inline int is_page_fault(u32 intr_info)
89{
90 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
91 INTR_INFO_VALID_MASK)) ==
92 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
93}
94
2ab455cc
AL		 95static inline int is_no_device(u32 intr_info)
96{
97 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
98 INTR_INFO_VALID_MASK)) ==
99 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
100}
101
6aa8b732
AK		 102static inline int is_external_interrupt(u32 intr_info)
103{
104 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
105 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
106}
107
a75beee6 108static int __find_msr_index(struct kvm_vcpu *vcpu, u32 msr)
7725f0ba
AK		 109{
110 int i;
111
112 for (i = 0; i < vcpu->nmsrs; ++i)
113 if (vcpu->guest_msrs[i].index == msr)
a75beee6
ED		 114 return i;
115 return -1;
116}
117
118static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
119{
120 int i;
121
122 i = __find_msr_index(vcpu, msr);
123 if (i >= 0)
124 return &vcpu->guest_msrs[i];
8b6d44c7 125 return NULL;
7725f0ba
AK		 126}
127
6aa8b732
AK		 128static void vmcs_clear(struct vmcs *vmcs)
129{
130 u64 phys_addr = __pa(vmcs);
131 u8 error;
132
133 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
134 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
135 : "cc", "memory");
136 if (error)
137 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
138 vmcs, phys_addr);
139}
140
141static void __vcpu_clear(void *arg)
142{
143 struct kvm_vcpu *vcpu = arg;
d3b2c338 144 int cpu = raw_smp_processor_id();
6aa8b732
AK		 145
146 if (vcpu->cpu == cpu)
147 vmcs_clear(vcpu->vmcs);
148 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
149 per_cpu(current_vmcs, cpu) = NULL;
150}
151
8d0be2b3
AK		 152static void vcpu_clear(struct kvm_vcpu *vcpu)
153{
154 if (vcpu->cpu != raw_smp_processor_id() && vcpu->cpu != -1)
155 smp_call_function_single(vcpu->cpu, __vcpu_clear, vcpu, 0, 1);
156 else
157 __vcpu_clear(vcpu);
158 vcpu->launched = 0;
159}
160
6aa8b732
AK		 161static unsigned long vmcs_readl(unsigned long field)
162{
163 unsigned long value;
164
165 asm volatile (ASM_VMX_VMREAD_RDX_RAX
166 : "=a"(value) : "d"(field) : "cc");
167 return value;
168}
169
170static u16 vmcs_read16(unsigned long field)
171{
172 return vmcs_readl(field);
173}
174
175static u32 vmcs_read32(unsigned long field)
176{
177 return vmcs_readl(field);
178}
179
180static u64 vmcs_read64(unsigned long field)
181{
05b3e0c2 182#ifdef CONFIG_X86_64
6aa8b732
AK		 183 return vmcs_readl(field);
184#else
185 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
186#endif
187}
188
e52de1b8
AK		 189static noinline void vmwrite_error(unsigned long field, unsigned long value)
190{
191 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
192 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
193 dump_stack();
194}
195
6aa8b732
AK		 196static void vmcs_writel(unsigned long field, unsigned long value)
197{
198 u8 error;
199
200 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
201 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 202 if (unlikely(error))
203 vmwrite_error(field, value);
6aa8b732
AK		 204}
205
206static void vmcs_write16(unsigned long field, u16 value)
207{
208 vmcs_writel(field, value);
209}
210
211static void vmcs_write32(unsigned long field, u32 value)
212{
213 vmcs_writel(field, value);
214}
215
216static void vmcs_write64(unsigned long field, u64 value)
217{
05b3e0c2 218#ifdef CONFIG_X86_64
6aa8b732
AK		 219 vmcs_writel(field, value);
220#else
221 vmcs_writel(field, value);
222 asm volatile ("");
223 vmcs_writel(field+1, value >> 32);
224#endif
225}
226
2ab455cc
AL		 227static void vmcs_clear_bits(unsigned long field, u32 mask)
228{
229 vmcs_writel(field, vmcs_readl(field) & ~mask);
230}
231
232static void vmcs_set_bits(unsigned long field, u32 mask)
233{
234 vmcs_writel(field, vmcs_readl(field) | mask);
235}
236
abd3f2d6
AK		 237static void update_exception_bitmap(struct kvm_vcpu *vcpu)
238{
239 u32 eb;
240
241 eb = 1u << PF_VECTOR;
242 if (!vcpu->fpu_active)
243 eb |= 1u << NM_VECTOR;
244 if (vcpu->guest_debug.enabled)
245 eb |= 1u << 1;
246 if (vcpu->rmode.active)
247 eb = ~0;
248 vmcs_write32(EXCEPTION_BITMAP, eb);
249}
250
33ed6329
AK		 251static void reload_tss(void)
252{
253#ifndef CONFIG_X86_64
254
255 /*
256 * VT restores TR but not its size. Useless.
257 */
258 struct descriptor_table gdt;
259 struct segment_descriptor *descs;
260
261 get_gdt(&gdt);
262 descs = (void *)gdt.base;
263 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
264 load_TR_desc();
265#endif
266}
267
268static void vmx_save_host_state(struct kvm_vcpu *vcpu)
269{
270 struct vmx_host_state *hs = &vcpu->vmx_host_state;
271
272 if (hs->loaded)
273 return;
274
275 hs->loaded = 1;
276 /*
277 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
278 * allow segment selectors with cpl > 0 or ti == 1.
279 */
280 hs->ldt_sel = read_ldt();
281 hs->fs_gs_ldt_reload_needed = hs->ldt_sel;
282 hs->fs_sel = read_fs();
283 if (!(hs->fs_sel & 7))
284 vmcs_write16(HOST_FS_SELECTOR, hs->fs_sel);
285 else {
286 vmcs_write16(HOST_FS_SELECTOR, 0);
287 hs->fs_gs_ldt_reload_needed = 1;
288 }
289 hs->gs_sel = read_gs();
290 if (!(hs->gs_sel & 7))
291 vmcs_write16(HOST_GS_SELECTOR, hs->gs_sel);
292 else {
293 vmcs_write16(HOST_GS_SELECTOR, 0);
294 hs->fs_gs_ldt_reload_needed = 1;
295 }
296
297#ifdef CONFIG_X86_64
298 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
299 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
300#else
301 vmcs_writel(HOST_FS_BASE, segment_base(hs->fs_sel));
302 vmcs_writel(HOST_GS_BASE, segment_base(hs->gs_sel));
303#endif
707c0874
AK		 304
305#ifdef CONFIG_X86_64
306 if (is_long_mode(vcpu)) {
a75beee6 307 save_msrs(vcpu->host_msrs + vcpu->msr_offset_kernel_gs_base, 1);
707c0874
AK		 308 }
309#endif
a75beee6 310 load_msrs(vcpu->guest_msrs, vcpu->save_nmsrs);
33ed6329
AK		 311}
312
313static void vmx_load_host_state(struct kvm_vcpu *vcpu)
314{
315 struct vmx_host_state *hs = &vcpu->vmx_host_state;
316
317 if (!hs->loaded)
318 return;
319
320 hs->loaded = 0;
321 if (hs->fs_gs_ldt_reload_needed) {
322 load_ldt(hs->ldt_sel);
323 load_fs(hs->fs_sel);
324 /*
325 * If we have to reload gs, we must take care to
326 * preserve our gs base.
327 */
328 local_irq_disable();
329 load_gs(hs->gs_sel);
330#ifdef CONFIG_X86_64
331 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
332#endif
333 local_irq_enable();
334
335 reload_tss();
336 }
a75beee6
ED		 337 save_msrs(vcpu->guest_msrs, vcpu->save_nmsrs);
338 load_msrs(vcpu->host_msrs, vcpu->save_nmsrs);
33ed6329
AK		 339}
340
6aa8b732
AK		 341/*
342 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
343 * vcpu mutex is already taken.
344 */
bccf2150 345static void vmx_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732
AK		 346{
347 u64 phys_addr = __pa(vcpu->vmcs);
348 int cpu;
349
350 cpu = get_cpu();
351
8d0be2b3
AK		 352 if (vcpu->cpu != cpu)
353 vcpu_clear(vcpu);
6aa8b732
AK		 354
355 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
356 u8 error;
357
358 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
359 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
360 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
361 : "cc");
362 if (error)
363 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
364 vcpu->vmcs, phys_addr);
365 }
366
367 if (vcpu->cpu != cpu) {
368 struct descriptor_table dt;
369 unsigned long sysenter_esp;
370
371 vcpu->cpu = cpu;
372 /*
373 * Linux uses per-cpu TSS and GDT, so set these when switching
374 * processors.
375 */
376 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
377 get_gdt(&dt);
378 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
379
380 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
381 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
382 }
6aa8b732
AK		 383}
384
385static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
386{
33ed6329 387 vmx_load_host_state(vcpu);
7702fd1f 388 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 389 put_cpu();
390}
391
5fd86fcf
AK		 392static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
393{
394 if (vcpu->fpu_active)
395 return;
396 vcpu->fpu_active = 1;
397 vmcs_clear_bits(GUEST_CR0, CR0_TS_MASK);
398 if (vcpu->cr0 & CR0_TS_MASK)
399 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
400 update_exception_bitmap(vcpu);
401}
402
403static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
404{
405 if (!vcpu->fpu_active)
406 return;
407 vcpu->fpu_active = 0;
408 vmcs_set_bits(GUEST_CR0, CR0_TS_MASK);
409 update_exception_bitmap(vcpu);
410}
411
774c47f1
AK		 412static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
413{
414 vcpu_clear(vcpu);
415}
416
6aa8b732
AK		 417static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
418{
419 return vmcs_readl(GUEST_RFLAGS);
420}
421
422static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
423{
424 vmcs_writel(GUEST_RFLAGS, rflags);
425}
426
427static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
428{
429 unsigned long rip;
430 u32 interruptibility;
431
432 rip = vmcs_readl(GUEST_RIP);
433 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
434 vmcs_writel(GUEST_RIP, rip);
435
436 /*
437 * We emulated an instruction, so temporary interrupt blocking
438 * should be removed, if set.
439 */
440 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
441 if (interruptibility & 3)
442 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
443 interruptibility & ~3);
c1150d8c 444 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 445}
446
447static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
448{
449 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
450 vmcs_readl(GUEST_RIP));
451 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
452 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
453 GP_VECTOR |
454 INTR_TYPE_EXCEPTION |
455 INTR_INFO_DELIEVER_CODE_MASK |
456 INTR_INFO_VALID_MASK);
457}
458
a75beee6
ED		 459/*
460 * Swap MSR entry in host/guest MSR entry array.
461 */
462void move_msr_up(struct kvm_vcpu *vcpu, int from, int to)
463{
464 struct vmx_msr_entry tmp;
465 tmp = vcpu->guest_msrs[to];
466 vcpu->guest_msrs[to] = vcpu->guest_msrs[from];
467 vcpu->guest_msrs[from] = tmp;
468 tmp = vcpu->host_msrs[to];
469 vcpu->host_msrs[to] = vcpu->host_msrs[from];
470 vcpu->host_msrs[from] = tmp;
471}
472
e38aea3e
AK		 473/*
474 * Set up the vmcs to automatically save and restore system
475 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
476 * mode, as fiddling with msrs is very expensive.
477 */
478static void setup_msrs(struct kvm_vcpu *vcpu)
479{
a75beee6 480 int index, save_nmsrs;
e38aea3e 481
a75beee6
ED		 482 save_nmsrs = 0;
483#ifdef CONFIG_X86_64
484 if (is_long_mode(vcpu)) {
485 index = __find_msr_index(vcpu, MSR_SYSCALL_MASK);
486 if (index >= 0)
487 move_msr_up(vcpu, index, save_nmsrs++);
488 index = __find_msr_index(vcpu, MSR_LSTAR);
489 if (index >= 0)
490 move_msr_up(vcpu, index, save_nmsrs++);
491 index = __find_msr_index(vcpu, MSR_CSTAR);
492 if (index >= 0)
493 move_msr_up(vcpu, index, save_nmsrs++);
494 index = __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
495 if (index >= 0)
496 move_msr_up(vcpu, index, save_nmsrs++);
497 /*
498 * MSR_K6_STAR is only needed on long mode guests, and only
499 * if efer.sce is enabled.
500 */
501 index = __find_msr_index(vcpu, MSR_K6_STAR);
502 if ((index >= 0) && (vcpu->shadow_efer & EFER_SCE))
503 move_msr_up(vcpu, index, save_nmsrs++);
504 }
505#endif
506 vcpu->save_nmsrs = save_nmsrs;
e38aea3e 507
4d56c8a7 508#ifdef CONFIG_X86_64
a75beee6
ED		 509 vcpu->msr_offset_kernel_gs_base =
510 __find_msr_index(vcpu, MSR_KERNEL_GS_BASE);
4d56c8a7 511#endif
a75beee6
ED		 512 index = __find_msr_index(vcpu, MSR_EFER);
513 if (index >= 0)
514 save_nmsrs = 1;
515 else {
516 save_nmsrs = 0;
517 index = 0;
4d56c8a7 518 }
e38aea3e 519 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
a75beee6 520 virt_to_phys(vcpu->guest_msrs + index));
e38aea3e 521 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
a75beee6 522 virt_to_phys(vcpu->guest_msrs + index));
e38aea3e 523 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
a75beee6
ED		 524 virt_to_phys(vcpu->host_msrs + index));
525 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, save_nmsrs);
526 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, save_nmsrs);
527 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, save_nmsrs);
e38aea3e
AK		 528}
529
6aa8b732
AK		 530/*
531 * reads and returns guest's timestamp counter "register"
532 * guest_tsc = host_tsc + tsc_offset -- 21.3
533 */
534static u64 guest_read_tsc(void)
535{
536 u64 host_tsc, tsc_offset;
537
538 rdtscll(host_tsc);
539 tsc_offset = vmcs_read64(TSC_OFFSET);
540 return host_tsc + tsc_offset;
541}
542
543/*
544 * writes 'guest_tsc' into guest's timestamp counter "register"
545 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
546 */
547static void guest_write_tsc(u64 guest_tsc)
548{
549 u64 host_tsc;
550
551 rdtscll(host_tsc);
552 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
553}
554
6aa8b732
AK		 555/*
556 * Reads an msr value (of 'msr_index') into 'pdata'.
557 * Returns 0 on success, non-0 otherwise.
558 * Assumes vcpu_load() was already called.
559 */
560static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
561{
562 u64 data;
563 struct vmx_msr_entry *msr;
564
565 if (!pdata) {
566 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
567 return -EINVAL;
568 }
569
570 switch (msr_index) {
05b3e0c2 571#ifdef CONFIG_X86_64
6aa8b732
AK		 572 case MSR_FS_BASE:
573 data = vmcs_readl(GUEST_FS_BASE);
574 break;
575 case MSR_GS_BASE:
576 data = vmcs_readl(GUEST_GS_BASE);
577 break;
578 case MSR_EFER:
3bab1f5d 579 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 580#endif
581 case MSR_IA32_TIME_STAMP_COUNTER:
582 data = guest_read_tsc();
583 break;
584 case MSR_IA32_SYSENTER_CS:
585 data = vmcs_read32(GUEST_SYSENTER_CS);
586 break;
587 case MSR_IA32_SYSENTER_EIP:
f5b42c33 588 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 589 break;
590 case MSR_IA32_SYSENTER_ESP:
f5b42c33 591 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 592 break;
6aa8b732
AK		 593 default:
594 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 595 if (msr) {
596 data = msr->data;
597 break;
6aa8b732 598 }
3bab1f5d 599 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 600 }
601
602 *pdata = data;
603 return 0;
604}
605
606/*
607 * Writes msr value into into the appropriate "register".
608 * Returns 0 on success, non-0 otherwise.
609 * Assumes vcpu_load() was already called.
610 */
611static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
612{
613 struct vmx_msr_entry *msr;
614 switch (msr_index) {
05b3e0c2 615#ifdef CONFIG_X86_64
3bab1f5d
AK		 616 case MSR_EFER:
617 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 618 case MSR_FS_BASE:
619 vmcs_writel(GUEST_FS_BASE, data);
620 break;
621 case MSR_GS_BASE:
622 vmcs_writel(GUEST_GS_BASE, data);
623 break;
624#endif
625 case MSR_IA32_SYSENTER_CS:
626 vmcs_write32(GUEST_SYSENTER_CS, data);
627 break;
628 case MSR_IA32_SYSENTER_EIP:
f5b42c33 629 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 630 break;
631 case MSR_IA32_SYSENTER_ESP:
f5b42c33 632 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 633 break;
d27d4aca 634 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 635 guest_write_tsc(data);
636 break;
6aa8b732
AK		 637 default:
638 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 639 if (msr) {
640 msr->data = data;
a75beee6
ED		 641 if (vcpu->vmx_host_state.loaded)
642 load_msrs(vcpu->guest_msrs,vcpu->save_nmsrs);
3bab1f5d 643 break;
6aa8b732 644 }
3bab1f5d 645 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 646 }
647
648 return 0;
649}
650
651/*
652 * Sync the rsp and rip registers into the vcpu structure. This allows
653 * registers to be accessed by indexing vcpu->regs.
654 */
655static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
656{
657 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
658 vcpu->rip = vmcs_readl(GUEST_RIP);
659}
660
661/*
662 * Syncs rsp and rip back into the vmcs. Should be called after possible
663 * modification.
664 */
665static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
666{
667 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
668 vmcs_writel(GUEST_RIP, vcpu->rip);
669}
670
671static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
672{
673 unsigned long dr7 = 0x400;
6aa8b732
AK		 674 int old_singlestep;
675
6aa8b732
AK		 676 old_singlestep = vcpu->guest_debug.singlestep;
677
678 vcpu->guest_debug.enabled = dbg->enabled;
679 if (vcpu->guest_debug.enabled) {
680 int i;
681
682 dr7 |= 0x200; /* exact */
683 for (i = 0; i < 4; ++i) {
684 if (!dbg->breakpoints[i].enabled)
685 continue;
686 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
687 dr7 |= 2 << (i*2); /* global enable */
688 dr7 |= 0 << (i*4+16); /* execution breakpoint */
689 }
690
6aa8b732 691 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 692 } else
6aa8b732 693 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 694
695 if (old_singlestep && !vcpu->guest_debug.singlestep) {
696 unsigned long flags;
697
698 flags = vmcs_readl(GUEST_RFLAGS);
699 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
700 vmcs_writel(GUEST_RFLAGS, flags);
701 }
702
abd3f2d6 703 update_exception_bitmap(vcpu);
6aa8b732
AK		 704 vmcs_writel(GUEST_DR7, dr7);
705
706 return 0;
707}
708
709static __init int cpu_has_kvm_support(void)
710{
711 unsigned long ecx = cpuid_ecx(1);
712 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
713}
714
715static __init int vmx_disabled_by_bios(void)
716{
717 u64 msr;
718
719 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
720 return (msr & 5) == 1; /* locked but not enabled */
721}
722
774c47f1 723static void hardware_enable(void *garbage)
6aa8b732
AK		 724{
725 int cpu = raw_smp_processor_id();
726 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
727 u64 old;
728
729 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 730 if ((old & 5) != 5)
6aa8b732
AK		 731 /* enable and lock */
732 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
733 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
734 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
735 : "memory", "cc");
736}
737
738static void hardware_disable(void *garbage)
739{
740 asm volatile (ASM_VMX_VMXOFF : : : "cc");
741}
742
743static __init void setup_vmcs_descriptor(void)
744{
745 u32 vmx_msr_low, vmx_msr_high;
746
c68876fd 747 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 748 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
749 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
750 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 751}
6aa8b732
AK		 752
753static struct vmcs *alloc_vmcs_cpu(int cpu)
754{
755 int node = cpu_to_node(cpu);
756 struct page *pages;
757 struct vmcs *vmcs;
758
759 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
760 if (!pages)
761 return NULL;
762 vmcs = page_address(pages);
763 memset(vmcs, 0, vmcs_descriptor.size);
764 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
765 return vmcs;
766}
767
768static struct vmcs *alloc_vmcs(void)
769{
d3b2c338 770 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 771}
772
773static void free_vmcs(struct vmcs *vmcs)
774{
775 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
776}
777
39959588 778static void free_kvm_area(void)
6aa8b732
AK		 779{
780 int cpu;
781
782 for_each_online_cpu(cpu)
783 free_vmcs(per_cpu(vmxarea, cpu));
784}
785
786extern struct vmcs *alloc_vmcs_cpu(int cpu);
787
788static __init int alloc_kvm_area(void)
789{
790 int cpu;
791
792 for_each_online_cpu(cpu) {
793 struct vmcs *vmcs;
794
795 vmcs = alloc_vmcs_cpu(cpu);
796 if (!vmcs) {
797 free_kvm_area();
798 return -ENOMEM;
799 }
800
801 per_cpu(vmxarea, cpu) = vmcs;
802 }
803 return 0;
804}
805
806static __init int hardware_setup(void)
807{
808 setup_vmcs_descriptor();
809 return alloc_kvm_area();
810}
811
812static __exit void hardware_unsetup(void)
813{
814 free_kvm_area();
815}
816
6aa8b732
AK		 817static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
818{
819 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
820
6af11b9e 821 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 822 vmcs_write16(sf->selector, save->selector);
823 vmcs_writel(sf->base, save->base);
824 vmcs_write32(sf->limit, save->limit);
825 vmcs_write32(sf->ar_bytes, save->ar);
826 } else {
827 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
828 << AR_DPL_SHIFT;
829 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
830 }
831}
832
833static void enter_pmode(struct kvm_vcpu *vcpu)
834{
835 unsigned long flags;
836
837 vcpu->rmode.active = 0;
838
839 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
840 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
841 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
842
843 flags = vmcs_readl(GUEST_RFLAGS);
844 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
845 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
846 vmcs_writel(GUEST_RFLAGS, flags);
847
848 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
849 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
850
851 update_exception_bitmap(vcpu);
852
853 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
854 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
855 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
856 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
857
858 vmcs_write16(GUEST_SS_SELECTOR, 0);
859 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
860
861 vmcs_write16(GUEST_CS_SELECTOR,
862 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
863 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
864}
865
866static int rmode_tss_base(struct kvm* kvm)
867{
868 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
869 return base_gfn << PAGE_SHIFT;
870}
871
872static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
873{
874 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
875
876 save->selector = vmcs_read16(sf->selector);
877 save->base = vmcs_readl(sf->base);
878 save->limit = vmcs_read32(sf->limit);
879 save->ar = vmcs_read32(sf->ar_bytes);
880 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
881 vmcs_write32(sf->limit, 0xffff);
882 vmcs_write32(sf->ar_bytes, 0xf3);
883}
884
885static void enter_rmode(struct kvm_vcpu *vcpu)
886{
887 unsigned long flags;
888
889 vcpu->rmode.active = 1;
890
891 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
892 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
893
894 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
895 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
896
897 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
898 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
899
900 flags = vmcs_readl(GUEST_RFLAGS);
901 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
902
903 flags |= IOPL_MASK | X86_EFLAGS_VM;
904
905 vmcs_writel(GUEST_RFLAGS, flags);
906 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
907 update_exception_bitmap(vcpu);
908
909 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
910 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
911 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
912
913 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 914 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 915 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
916 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 917 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
918
919 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
920 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
921 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
922 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
923}
924
05b3e0c2 925#ifdef CONFIG_X86_64
6aa8b732
AK		 926
927static void enter_lmode(struct kvm_vcpu *vcpu)
928{
929 u32 guest_tr_ar;
930
931 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
932 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
933 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
934 __FUNCTION__);
935 vmcs_write32(GUEST_TR_AR_BYTES,
936 (guest_tr_ar & ~AR_TYPE_MASK)
937 | AR_TYPE_BUSY_64_TSS);
938 }
939
940 vcpu->shadow_efer |= EFER_LMA;
941
942 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
943 vmcs_write32(VM_ENTRY_CONTROLS,
944 vmcs_read32(VM_ENTRY_CONTROLS)
945 | VM_ENTRY_CONTROLS_IA32E_MASK);
946}
947
948static void exit_lmode(struct kvm_vcpu *vcpu)
949{
950 vcpu->shadow_efer &= ~EFER_LMA;
951
952 vmcs_write32(VM_ENTRY_CONTROLS,
953 vmcs_read32(VM_ENTRY_CONTROLS)
954 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
955}
956
957#endif
958
25c4c276 959static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 960{
399badf3
AK		 961 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
962 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
963}
964
6aa8b732
AK		 965static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
966{
5fd86fcf
AK		 967 vmx_fpu_deactivate(vcpu);
968
6aa8b732
AK		 969 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
970 enter_pmode(vcpu);
971
972 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
973 enter_rmode(vcpu);
974
05b3e0c2 975#ifdef CONFIG_X86_64
6aa8b732
AK		 976 if (vcpu->shadow_efer & EFER_LME) {
977 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
978 enter_lmode(vcpu);
979 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
980 exit_lmode(vcpu);
981 }
982#endif
983
984 vmcs_writel(CR0_READ_SHADOW, cr0);
985 vmcs_writel(GUEST_CR0,
986 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
987 vcpu->cr0 = cr0;
5fd86fcf
AK		 988
989 if (!(cr0 & CR0_TS_MASK) || !(cr0 & CR0_PE_MASK))
990 vmx_fpu_activate(vcpu);
6aa8b732
AK		 991}
992
6aa8b732
AK		 993static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
994{
995 vmcs_writel(GUEST_CR3, cr3);
5fd86fcf
AK		 996 if (vcpu->cr0 & CR0_PE_MASK)
997 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 998}
999
1000static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1001{
1002 vmcs_writel(CR4_READ_SHADOW, cr4);
1003 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1004 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1005 vcpu->cr4 = cr4;
1006}
1007
05b3e0c2 1008#ifdef CONFIG_X86_64
6aa8b732
AK		 1009
1010static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1011{
1012 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
1013
1014 vcpu->shadow_efer = efer;
1015 if (efer & EFER_LMA) {
1016 vmcs_write32(VM_ENTRY_CONTROLS,
1017 vmcs_read32(VM_ENTRY_CONTROLS) |
1018 VM_ENTRY_CONTROLS_IA32E_MASK);
1019 msr->data = efer;
1020
1021 } else {
1022 vmcs_write32(VM_ENTRY_CONTROLS,
1023 vmcs_read32(VM_ENTRY_CONTROLS) &
1024 ~VM_ENTRY_CONTROLS_IA32E_MASK);
1025
1026 msr->data = efer & ~EFER_LME;
1027 }
e38aea3e 1028 setup_msrs(vcpu);
6aa8b732
AK		 1029}
1030
1031#endif
1032
1033static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1034{
1035 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1036
1037 return vmcs_readl(sf->base);
1038}
1039
1040static void vmx_get_segment(struct kvm_vcpu *vcpu,
1041 struct kvm_segment *var, int seg)
1042{
1043 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1044 u32 ar;
1045
1046 var->base = vmcs_readl(sf->base);
1047 var->limit = vmcs_read32(sf->limit);
1048 var->selector = vmcs_read16(sf->selector);
1049 ar = vmcs_read32(sf->ar_bytes);
1050 if (ar & AR_UNUSABLE_MASK)
1051 ar = 0;
1052 var->type = ar & 15;
1053 var->s = (ar >> 4) & 1;
1054 var->dpl = (ar >> 5) & 3;
1055 var->present = (ar >> 7) & 1;
1056 var->avl = (ar >> 12) & 1;
1057 var->l = (ar >> 13) & 1;
1058 var->db = (ar >> 14) & 1;
1059 var->g = (ar >> 15) & 1;
1060 var->unusable = (ar >> 16) & 1;
1061}
1062
653e3108 1063static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1064{
6aa8b732
AK		 1065 u32 ar;
1066
653e3108 1067 if (var->unusable)
6aa8b732
AK		 1068 ar = 1 << 16;
1069 else {
1070 ar = var->type & 15;
1071 ar |= (var->s & 1) << 4;
1072 ar |= (var->dpl & 3) << 5;
1073 ar |= (var->present & 1) << 7;
1074 ar |= (var->avl & 1) << 12;
1075 ar |= (var->l & 1) << 13;
1076 ar |= (var->db & 1) << 14;
1077 ar |= (var->g & 1) << 15;
1078 }
f7fbf1fd
UL		 1079 if (ar == 0) /* a 0 value means unusable */
1080 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1081
1082 return ar;
1083}
1084
1085static void vmx_set_segment(struct kvm_vcpu *vcpu,
1086 struct kvm_segment *var, int seg)
1087{
1088 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1089 u32 ar;
1090
1091 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1092 vcpu->rmode.tr.selector = var->selector;
1093 vcpu->rmode.tr.base = var->base;
1094 vcpu->rmode.tr.limit = var->limit;
1095 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1096 return;
1097 }
1098 vmcs_writel(sf->base, var->base);
1099 vmcs_write32(sf->limit, var->limit);
1100 vmcs_write16(sf->selector, var->selector);
1101 if (vcpu->rmode.active && var->s) {
1102 /*
1103 * Hack real-mode segments into vm86 compatibility.
1104 */
1105 if (var->base == 0xffff0000 && var->selector == 0xf000)
1106 vmcs_writel(sf->base, 0xf0000);
1107 ar = 0xf3;
1108 } else
1109 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1110 vmcs_write32(sf->ar_bytes, ar);
1111}
1112
6aa8b732
AK		 1113static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1114{
1115 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1116
1117 *db = (ar >> 14) & 1;
1118 *l = (ar >> 13) & 1;
1119}
1120
1121static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1122{
1123 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1124 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1125}
1126
1127static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1128{
1129 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1130 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1131}
1132
1133static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1134{
1135 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1136 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1137}
1138
1139static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1140{
1141 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1142 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1143}
1144
1145static int init_rmode_tss(struct kvm* kvm)
1146{
1147 struct page *p1, *p2, *p3;
1148 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1149 char *page;
1150
954bbbc2
AK		 1151 p1 = gfn_to_page(kvm, fn++);
1152 p2 = gfn_to_page(kvm, fn++);
1153 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1154
1155 if (!p1 || !p2 || !p3) {
1156 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1157 return 0;
1158 }
1159
1160 page = kmap_atomic(p1, KM_USER0);
1161 memset(page, 0, PAGE_SIZE);
1162 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1163 kunmap_atomic(page, KM_USER0);
1164
1165 page = kmap_atomic(p2, KM_USER0);
1166 memset(page, 0, PAGE_SIZE);
1167 kunmap_atomic(page, KM_USER0);
1168
1169 page = kmap_atomic(p3, KM_USER0);
1170 memset(page, 0, PAGE_SIZE);
1171 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1172 kunmap_atomic(page, KM_USER0);
1173
1174 return 1;
1175}
1176
1177static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
1178{
1179 u32 msr_high, msr_low;
1180
1181 rdmsr(msr, msr_low, msr_high);
1182
1183 val &= msr_high;
1184 val |= msr_low;
1185 vmcs_write32(vmcs_field, val);
1186}
1187
1188static void seg_setup(int seg)
1189{
1190 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1191
1192 vmcs_write16(sf->selector, 0);
1193 vmcs_writel(sf->base, 0);
1194 vmcs_write32(sf->limit, 0xffff);
1195 vmcs_write32(sf->ar_bytes, 0x93);
1196}
1197
1198/*
1199 * Sets up the vmcs for emulated real mode.
1200 */
1201static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
1202{
1203 u32 host_sysenter_cs;
1204 u32 junk;
1205 unsigned long a;
1206 struct descriptor_table dt;
1207 int i;
1208 int ret = 0;
cd2276a7 1209 unsigned long kvm_vmx_return;
6aa8b732
AK		 1210
1211 if (!init_rmode_tss(vcpu->kvm)) {
1212 ret = -ENOMEM;
1213 goto out;
1214 }
1215
1216 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1217 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1218 vcpu->cr8 = 0;
1219 vcpu->apic_base = 0xfee00000 |
1220 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1221 MSR_IA32_APICBASE_ENABLE;
1222
1223 fx_init(vcpu);
1224
1225 /*
1226 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1227 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1228 */
1229 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1230 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1231 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1232 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1233
1234 seg_setup(VCPU_SREG_DS);
1235 seg_setup(VCPU_SREG_ES);
1236 seg_setup(VCPU_SREG_FS);
1237 seg_setup(VCPU_SREG_GS);
1238 seg_setup(VCPU_SREG_SS);
1239
1240 vmcs_write16(GUEST_TR_SELECTOR, 0);
1241 vmcs_writel(GUEST_TR_BASE, 0);
1242 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1243 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1244
1245 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1246 vmcs_writel(GUEST_LDTR_BASE, 0);
1247 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1248 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1249
1250 vmcs_write32(GUEST_SYSENTER_CS, 0);
1251 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1252 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1253
1254 vmcs_writel(GUEST_RFLAGS, 0x02);
1255 vmcs_writel(GUEST_RIP, 0xfff0);
1256 vmcs_writel(GUEST_RSP, 0);
1257
6aa8b732
AK		 1258 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1259 vmcs_writel(GUEST_DR7, 0x400);
1260
1261 vmcs_writel(GUEST_GDTR_BASE, 0);
1262 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1263
1264 vmcs_writel(GUEST_IDTR_BASE, 0);
1265 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1266
1267 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1268 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1269 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1270
1271 /* I/O */
fdef3ad1
HQ		 1272 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1273 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1274
1275 guest_write_tsc(0);
1276
1277 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1278
1279 /* Special registers */
1280 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1281
1282 /* Control */
c68876fd 1283 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1284 PIN_BASED_VM_EXEC_CONTROL,
1285 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1286 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1287 );
c68876fd 1288 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1289 CPU_BASED_VM_EXEC_CONTROL,
1290 CPU_BASED_HLT_EXITING /* 20.6.2 */
1291 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1292 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
fdef3ad1 1293 | CPU_BASED_ACTIVATE_IO_BITMAP /* 20.6.2 */
6aa8b732
AK		 1294 | CPU_BASED_MOV_DR_EXITING
1295 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1296 );
1297
6aa8b732
AK		 1298 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1299 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1300 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1301
1302 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1303 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1304 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1305
1306 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1307 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1308 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1309 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1310 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1311 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1312#ifdef CONFIG_X86_64
6aa8b732
AK		 1313 rdmsrl(MSR_FS_BASE, a);
1314 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1315 rdmsrl(MSR_GS_BASE, a);
1316 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1317#else
1318 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1319 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1320#endif
1321
1322 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1323
1324 get_idt(&dt);
1325 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1326
cd2276a7
AK		 1327 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1328 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
6aa8b732
AK		 1329
1330 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1331 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1332 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1333 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1334 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1335 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1336
6aa8b732
AK		 1337 for (i = 0; i < NR_VMX_MSR; ++i) {
1338 u32 index = vmx_msr_index[i];
1339 u32 data_low, data_high;
1340 u64 data;
1341 int j = vcpu->nmsrs;
1342
1343 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1344 continue;
432bd6cb
AK		 1345 if (wrmsr_safe(index, data_low, data_high) < 0)
1346 continue;
6aa8b732
AK		 1347 data = data_low | ((u64)data_high << 32);
1348 vcpu->host_msrs[j].index = index;
1349 vcpu->host_msrs[j].reserved = 0;
1350 vcpu->host_msrs[j].data = data;
1351 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1352 ++vcpu->nmsrs;
1353 }
6aa8b732 1354
e38aea3e
AK		 1355 setup_msrs(vcpu);
1356
c68876fd 1357 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732 1358 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
6aa8b732
AK		 1359
1360 /* 22.2.1, 20.8.1 */
c68876fd 1361 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1362 VM_ENTRY_CONTROLS, 0);
1363 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1364
3b99ab24 1365#ifdef CONFIG_X86_64
6aa8b732
AK		 1366 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1367 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1368#endif
6aa8b732 1369
25c4c276 1370 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1371 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1372
1373 vcpu->cr0 = 0x60000010;
1374 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1375 vmx_set_cr4(vcpu, 0);
05b3e0c2 1376#ifdef CONFIG_X86_64
6aa8b732
AK		 1377 vmx_set_efer(vcpu, 0);
1378#endif
5fd86fcf 1379 vmx_fpu_activate(vcpu);
abd3f2d6 1380 update_exception_bitmap(vcpu);
6aa8b732
AK		 1381
1382 return 0;
1383
6aa8b732
AK		 1384out:
1385 return ret;
1386}
1387
1388static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1389{
1390 u16 ent[2];
1391 u16 cs;
1392 u16 ip;
1393 unsigned long flags;
1394 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1395 u16 sp = vmcs_readl(GUEST_RSP);
1396 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1397
3964994b 1398 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1399 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1400 __FUNCTION__,
1401 vmcs_readl(GUEST_RSP),
1402 vmcs_readl(GUEST_SS_BASE),
1403 vmcs_read32(GUEST_SS_LIMIT));
1404 return;
1405 }
1406
1407 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1408 sizeof(ent)) {
1409 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1410 return;
1411 }
1412
1413 flags = vmcs_readl(GUEST_RFLAGS);
1414 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1415 ip = vmcs_readl(GUEST_RIP);
1416
1417
1418 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1419 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1420 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1421 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1422 return;
1423 }
1424
1425 vmcs_writel(GUEST_RFLAGS, flags &
1426 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1427 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1428 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1429 vmcs_writel(GUEST_RIP, ent[0]);
1430 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1431}
1432
1433static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1434{
1435 int word_index = __ffs(vcpu->irq_summary);
1436 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1437 int irq = word_index * BITS_PER_LONG + bit_index;
1438
1439 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1440 if (!vcpu->irq_pending[word_index])
1441 clear_bit(word_index, &vcpu->irq_summary);
1442
1443 if (vcpu->rmode.active) {
1444 inject_rmode_irq(vcpu, irq);
1445 return;
1446 }
1447 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1448 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1449}
1450
c1150d8c
DL		 1451
1452static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1453 struct kvm_run *kvm_run)
6aa8b732 1454{
c1150d8c
DL		 1455 u32 cpu_based_vm_exec_control;
1456
1457 vcpu->interrupt_window_open =
1458 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1459 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1460
1461 if (vcpu->interrupt_window_open &&
1462 vcpu->irq_summary &&
1463 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1464 /*
c1150d8c 1465 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1466 */
1467 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1468
1469 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1470 if (!vcpu->interrupt_window_open &&
1471 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1472 /*
1473 * Interrupts blocked. Wait for unblock.
1474 */
c1150d8c
DL		 1475 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1476 else
1477 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1478 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1479}
1480
1481static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1482{
1483 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1484
1485 set_debugreg(dbg->bp[0], 0);
1486 set_debugreg(dbg->bp[1], 1);
1487 set_debugreg(dbg->bp[2], 2);
1488 set_debugreg(dbg->bp[3], 3);
1489
1490 if (dbg->singlestep) {
1491 unsigned long flags;
1492
1493 flags = vmcs_readl(GUEST_RFLAGS);
1494 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1495 vmcs_writel(GUEST_RFLAGS, flags);
1496 }
1497}
1498
1499static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1500 int vec, u32 err_code)
1501{
1502 if (!vcpu->rmode.active)
1503 return 0;
1504
b3f37707
NK		 1505 /*
1506 * Instruction with address size override prefix opcode 0x67
1507 * Cause the #SS fault with 0 error code in VM86 mode.
1508 */
1509 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1510 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1511 return 1;
1512 return 0;
1513}
1514
1515static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1516{
1517 u32 intr_info, error_code;
1518 unsigned long cr2, rip;
1519 u32 vect_info;
1520 enum emulation_result er;
e2dec939 1521 int r;
6aa8b732
AK		 1522
1523 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1524 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1525
1526 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1527 !is_page_fault(intr_info)) {
1528 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1529 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1530 }
1531
1532 if (is_external_interrupt(vect_info)) {
1533 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1534 set_bit(irq, vcpu->irq_pending);
1535 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1536 }
1537
1538 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1539 asm ("int $2");
1540 return 1;
1541 }
2ab455cc
AL		 1542
1543 if (is_no_device(intr_info)) {
5fd86fcf 1544 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1545 return 1;
1546 }
1547
6aa8b732
AK		 1548 error_code = 0;
1549 rip = vmcs_readl(GUEST_RIP);
1550 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1551 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1552 if (is_page_fault(intr_info)) {
1553 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1554
1555 spin_lock(&vcpu->kvm->lock);
e2dec939
AK		 1556 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1557 if (r < 0) {
1558 spin_unlock(&vcpu->kvm->lock);
1559 return r;
1560 }
1561 if (!r) {
6aa8b732
AK		 1562 spin_unlock(&vcpu->kvm->lock);
1563 return 1;
1564 }
1565
1566 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1567 spin_unlock(&vcpu->kvm->lock);
1568
1569 switch (er) {
1570 case EMULATE_DONE:
1571 return 1;
1572 case EMULATE_DO_MMIO:
1165f5fe 1573 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1574 kvm_run->exit_reason = KVM_EXIT_MMIO;
1575 return 0;
1576 case EMULATE_FAIL:
1577 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1578 break;
1579 default:
1580 BUG();
1581 }
1582 }
1583
1584 if (vcpu->rmode.active &&
1585 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1586 error_code))
1587 return 1;
1588
1589 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1590 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1591 return 0;
1592 }
1593 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1594 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1595 kvm_run->ex.error_code = error_code;
1596 return 0;
1597}
1598
1599static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1600 struct kvm_run *kvm_run)
1601{
1165f5fe 1602 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1603 return 1;
1604}
1605
988ad74f
AK		 1606static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1607{
1608 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1609 return 0;
1610}
6aa8b732 1611
039576c0 1612static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
6aa8b732
AK		 1613{
1614 u64 inst;
1615 gva_t rip;
1616 int countr_size;
1617 int i, n;
1618
1619 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1620 countr_size = 2;
1621 } else {
1622 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1623
1624 countr_size = (cs_ar & AR_L_MASK) ? 8:
1625 (cs_ar & AR_DB_MASK) ? 4: 2;
1626 }
1627
1628 rip = vmcs_readl(GUEST_RIP);
1629 if (countr_size != 8)
1630 rip += vmcs_readl(GUEST_CS_BASE);
1631
1632 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1633
1634 for (i = 0; i < n; i++) {
1635 switch (((u8*)&inst)[i]) {
1636 case 0xf0:
1637 case 0xf2:
1638 case 0xf3:
1639 case 0x2e:
1640 case 0x36:
1641 case 0x3e:
1642 case 0x26:
1643 case 0x64:
1644 case 0x65:
1645 case 0x66:
1646 break;
1647 case 0x67:
1648 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1649 default:
1650 goto done;
1651 }
1652 }
1653 return 0;
1654done:
1655 countr_size *= 8;
1656 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
039576c0 1657 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
6aa8b732
AK		 1658 return 1;
1659}
1660
1661static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1662{
1663 u64 exit_qualification;
039576c0
AK		 1664 int size, down, in, string, rep;
1665 unsigned port;
1666 unsigned long count;
1667 gva_t address;
6aa8b732 1668
1165f5fe 1669 ++vcpu->stat.io_exits;
6aa8b732 1670 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0
AK		 1671 in = (exit_qualification & 8) != 0;
1672 size = (exit_qualification & 7) + 1;
1673 string = (exit_qualification & 16) != 0;
1674 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1675 count = 1;
1676 rep = (exit_qualification & 32) != 0;
1677 port = exit_qualification >> 16;
1678 address = 0;
1679 if (string) {
1680 if (rep && !get_io_count(vcpu, &count))
6aa8b732 1681 return 1;
039576c0
AK		 1682 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1683 }
1684 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1685 address, rep, port);
6aa8b732
AK		 1686}
1687
102d8325
IM		 1688static void
1689vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1690{
1691 /*
1692 * Patch in the VMCALL instruction:
1693 */
1694 hypercall[0] = 0x0f;
1695 hypercall[1] = 0x01;
1696 hypercall[2] = 0xc1;
1697 hypercall[3] = 0xc3;
1698}
1699
6aa8b732
AK		 1700static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1701{
1702 u64 exit_qualification;
1703 int cr;
1704 int reg;
1705
1706 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1707 cr = exit_qualification & 15;
1708 reg = (exit_qualification >> 8) & 15;
1709 switch ((exit_qualification >> 4) & 3) {
1710 case 0: /* mov to cr */
1711 switch (cr) {
1712 case 0:
1713 vcpu_load_rsp_rip(vcpu);
1714 set_cr0(vcpu, vcpu->regs[reg]);
1715 skip_emulated_instruction(vcpu);
1716 return 1;
1717 case 3:
1718 vcpu_load_rsp_rip(vcpu);
1719 set_cr3(vcpu, vcpu->regs[reg]);
1720 skip_emulated_instruction(vcpu);
1721 return 1;
1722 case 4:
1723 vcpu_load_rsp_rip(vcpu);
1724 set_cr4(vcpu, vcpu->regs[reg]);
1725 skip_emulated_instruction(vcpu);
1726 return 1;
1727 case 8:
1728 vcpu_load_rsp_rip(vcpu);
1729 set_cr8(vcpu, vcpu->regs[reg]);
1730 skip_emulated_instruction(vcpu);
1731 return 1;
1732 };
1733 break;
25c4c276
AL		 1734 case 2: /* clts */
1735 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1736 vmx_fpu_deactivate(vcpu);
2ab455cc
AL		 1737 vcpu->cr0 &= ~CR0_TS_MASK;
1738 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1739 vmx_fpu_activate(vcpu);
25c4c276
AL		 1740 skip_emulated_instruction(vcpu);
1741 return 1;
6aa8b732
AK		 1742 case 1: /*mov from cr*/
1743 switch (cr) {
1744 case 3:
1745 vcpu_load_rsp_rip(vcpu);
1746 vcpu->regs[reg] = vcpu->cr3;
1747 vcpu_put_rsp_rip(vcpu);
1748 skip_emulated_instruction(vcpu);
1749 return 1;
1750 case 8:
6aa8b732
AK		 1751 vcpu_load_rsp_rip(vcpu);
1752 vcpu->regs[reg] = vcpu->cr8;
1753 vcpu_put_rsp_rip(vcpu);
1754 skip_emulated_instruction(vcpu);
1755 return 1;
1756 }
1757 break;
1758 case 3: /* lmsw */
1759 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1760
1761 skip_emulated_instruction(vcpu);
1762 return 1;
1763 default:
1764 break;
1765 }
1766 kvm_run->exit_reason = 0;
1767 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1768 (int)(exit_qualification >> 4) & 3, cr);
1769 return 0;
1770}
1771
1772static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1773{
1774 u64 exit_qualification;
1775 unsigned long val;
1776 int dr, reg;
1777
1778 /*
1779 * FIXME: this code assumes the host is debugging the guest.
1780 * need to deal with guest debugging itself too.
1781 */
1782 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1783 dr = exit_qualification & 7;
1784 reg = (exit_qualification >> 8) & 15;
1785 vcpu_load_rsp_rip(vcpu);
1786 if (exit_qualification & 16) {
1787 /* mov from dr */
1788 switch (dr) {
1789 case 6:
1790 val = 0xffff0ff0;
1791 break;
1792 case 7:
1793 val = 0x400;
1794 break;
1795 default:
1796 val = 0;
1797 }
1798 vcpu->regs[reg] = val;
1799 } else {
1800 /* mov to dr */
1801 }
1802 vcpu_put_rsp_rip(vcpu);
1803 skip_emulated_instruction(vcpu);
1804 return 1;
1805}
1806
1807static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1808{
06465c5a
AK		 1809 kvm_emulate_cpuid(vcpu);
1810 return 1;
6aa8b732
AK		 1811}
1812
1813static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1814{
1815 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1816 u64 data;
1817
1818 if (vmx_get_msr(vcpu, ecx, &data)) {
1819 vmx_inject_gp(vcpu, 0);
1820 return 1;
1821 }
1822
1823 /* FIXME: handling of bits 32:63 of rax, rdx */
1824 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1825 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1826 skip_emulated_instruction(vcpu);
1827 return 1;
1828}
1829
1830static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1831{
1832 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1833 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1834 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1835
1836 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1837 vmx_inject_gp(vcpu, 0);
1838 return 1;
1839 }
1840
1841 skip_emulated_instruction(vcpu);
1842 return 1;
1843}
1844
c1150d8c
DL		 1845static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1846 struct kvm_run *kvm_run)
1847{
1848 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1849 kvm_run->cr8 = vcpu->cr8;
1850 kvm_run->apic_base = vcpu->apic_base;
1851 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1852 vcpu->irq_summary == 0);
1853}
1854
6aa8b732
AK		 1855static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1856 struct kvm_run *kvm_run)
1857{
c1150d8c
DL		 1858 /*
1859 * If the user space waits to inject interrupts, exit as soon as
1860 * possible
1861 */
1862 if (kvm_run->request_interrupt_window &&
022a9308 1863 !vcpu->irq_summary) {
c1150d8c 1864 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 1865 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1866 return 0;
1867 }
6aa8b732
AK		 1868 return 1;
1869}
1870
1871static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1872{
1873 skip_emulated_instruction(vcpu);
c1150d8c 1874 if (vcpu->irq_summary)
6aa8b732
AK		 1875 return 1;
1876
1877 kvm_run->exit_reason = KVM_EXIT_HLT;
1165f5fe 1878 ++vcpu->stat.halt_exits;
6aa8b732
AK		 1879 return 0;
1880}
1881
c21415e8
IM		 1882static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1883{
510043da 1884 skip_emulated_instruction(vcpu);
270fd9b9 1885 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 1886}
1887
6aa8b732
AK		 1888/*
1889 * The exit handlers return 1 if the exit was handled fully and guest execution
1890 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1891 * to be done to userspace and return 0.
1892 */
1893static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1894 struct kvm_run *kvm_run) = {
1895 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1896 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 1897 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 1898 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 1899 [EXIT_REASON_CR_ACCESS] = handle_cr,
1900 [EXIT_REASON_DR_ACCESS] = handle_dr,
1901 [EXIT_REASON_CPUID] = handle_cpuid,
1902 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1903 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1904 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1905 [EXIT_REASON_HLT] = handle_halt,
c21415e8 1906 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 1907};
1908
1909static const int kvm_vmx_max_exit_handlers =
1910 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1911
1912/*
1913 * The guest has exited. See if we can fix it or if we need userspace
1914 * assistance.
1915 */
1916static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1917{
1918 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1919 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1920
1921 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1922 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1923 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1924 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 1925 if (exit_reason < kvm_vmx_max_exit_handlers
1926 && kvm_vmx_exit_handlers[exit_reason])
1927 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1928 else {
1929 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1930 kvm_run->hw.hardware_exit_reason = exit_reason;
1931 }
1932 return 0;
1933}
1934
c1150d8c
DL		 1935/*
1936 * Check if userspace requested an interrupt window, and that the
1937 * interrupt window is open.
1938 *
1939 * No need to exit to userspace if we already have an interrupt queued.
1940 */
1941static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1942 struct kvm_run *kvm_run)
1943{
1944 return (!vcpu->irq_summary &&
1945 kvm_run->request_interrupt_window &&
1946 vcpu->interrupt_window_open &&
1947 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1948}
1949
6aa8b732
AK		 1950static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1951{
1952 u8 fail;
e2dec939 1953 int r;
6aa8b732 1954
e6adf283 1955preempted:
cccf748b
AK		 1956 if (!vcpu->mmio_read_completed)
1957 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1958
1959 if (vcpu->guest_debug.enabled)
1960 kvm_guest_debug_pre(vcpu);
1961
e6adf283 1962again:
33ed6329 1963 vmx_save_host_state(vcpu);
e6adf283
AK		 1964 kvm_load_guest_fpu(vcpu);
1965
1966 /*
1967 * Loading guest fpu may have cleared host cr0.ts
1968 */
1969 vmcs_writel(HOST_CR0, read_cr0());
1970
6aa8b732
AK		 1971 asm (
1972 /* Store host registers */
1973 "pushf \n\t"
05b3e0c2 1974#ifdef CONFIG_X86_64
6aa8b732
AK		 1975 "push %%rax; push %%rbx; push %%rdx;"
1976 "push %%rsi; push %%rdi; push %%rbp;"
1977 "push %%r8; push %%r9; push %%r10; push %%r11;"
1978 "push %%r12; push %%r13; push %%r14; push %%r15;"
1979 "push %%rcx \n\t"
1980 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1981#else
1982 "pusha; push %%ecx \n\t"
1983 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1984#endif
1985 /* Check if vmlaunch of vmresume is needed */
1986 "cmp $0, %1 \n\t"
1987 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1988#ifdef CONFIG_X86_64
6aa8b732
AK		 1989 "mov %c[cr2](%3), %%rax \n\t"
1990 "mov %%rax, %%cr2 \n\t"
1991 "mov %c[rax](%3), %%rax \n\t"
1992 "mov %c[rbx](%3), %%rbx \n\t"
1993 "mov %c[rdx](%3), %%rdx \n\t"
1994 "mov %c[rsi](%3), %%rsi \n\t"
1995 "mov %c[rdi](%3), %%rdi \n\t"
1996 "mov %c[rbp](%3), %%rbp \n\t"
1997 "mov %c[r8](%3), %%r8 \n\t"
1998 "mov %c[r9](%3), %%r9 \n\t"
1999 "mov %c[r10](%3), %%r10 \n\t"
2000 "mov %c[r11](%3), %%r11 \n\t"
2001 "mov %c[r12](%3), %%r12 \n\t"
2002 "mov %c[r13](%3), %%r13 \n\t"
2003 "mov %c[r14](%3), %%r14 \n\t"
2004 "mov %c[r15](%3), %%r15 \n\t"
2005 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2006#else
2007 "mov %c[cr2](%3), %%eax \n\t"
2008 "mov %%eax, %%cr2 \n\t"
2009 "mov %c[rax](%3), %%eax \n\t"
2010 "mov %c[rbx](%3), %%ebx \n\t"
2011 "mov %c[rdx](%3), %%edx \n\t"
2012 "mov %c[rsi](%3), %%esi \n\t"
2013 "mov %c[rdi](%3), %%edi \n\t"
2014 "mov %c[rbp](%3), %%ebp \n\t"
2015 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2016#endif
2017 /* Enter guest mode */
cd2276a7 2018 "jne .Llaunched \n\t"
6aa8b732 2019 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2020 "jmp .Lkvm_vmx_return \n\t"
2021 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2022 ".Lkvm_vmx_return: "
6aa8b732 2023 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2024#ifdef CONFIG_X86_64
96958231 2025 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2026 "mov %%rax, %c[rax](%3) \n\t"
2027 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2028 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2029 "mov %%rdx, %c[rdx](%3) \n\t"
2030 "mov %%rsi, %c[rsi](%3) \n\t"
2031 "mov %%rdi, %c[rdi](%3) \n\t"
2032 "mov %%rbp, %c[rbp](%3) \n\t"
2033 "mov %%r8, %c[r8](%3) \n\t"
2034 "mov %%r9, %c[r9](%3) \n\t"
2035 "mov %%r10, %c[r10](%3) \n\t"
2036 "mov %%r11, %c[r11](%3) \n\t"
2037 "mov %%r12, %c[r12](%3) \n\t"
2038 "mov %%r13, %c[r13](%3) \n\t"
2039 "mov %%r14, %c[r14](%3) \n\t"
2040 "mov %%r15, %c[r15](%3) \n\t"
2041 "mov %%cr2, %%rax \n\t"
2042 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2043 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2044
2045 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2046 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2047 "pop %%rbp; pop %%rdi; pop %%rsi;"
2048 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2049#else
96958231 2050 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2051 "mov %%eax, %c[rax](%3) \n\t"
2052 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2053 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2054 "mov %%edx, %c[rdx](%3) \n\t"
2055 "mov %%esi, %c[rsi](%3) \n\t"
2056 "mov %%edi, %c[rdi](%3) \n\t"
2057 "mov %%ebp, %c[rbp](%3) \n\t"
2058 "mov %%cr2, %%eax \n\t"
2059 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2060 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2061
2062 "pop %%ecx; popa \n\t"
2063#endif
2064 "setbe %0 \n\t"
2065 "popf \n\t"
e0015489 2066 : "=q" (fail)
6aa8b732
AK		 2067 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
2068 "c"(vcpu),
2069 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2070 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2071 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2072 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2073 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2074 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2075 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2076#ifdef CONFIG_X86_64
6aa8b732
AK		 2077 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2078 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2079 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2080 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2081 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2082 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2083 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2084 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2085#endif
2086 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2087 : "cc", "memory" );
2088
1165f5fe 2089 ++vcpu->stat.exits;
6aa8b732 2090
c1150d8c 2091 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2092
6aa8b732 2093 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6aa8b732 2094
05e0c8c3 2095 if (unlikely(fail)) {
8eb7d334
AK		 2096 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2097 kvm_run->fail_entry.hardware_entry_failure_reason
2098 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2099 r = 0;
05e0c8c3
AK		 2100 goto out;
2101 }
2102 /*
2103 * Profile KVM exit RIPs:
2104 */
2105 if (unlikely(prof_on == KVM_PROFILING))
2106 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2107
2108 vcpu->launched = 1;
2109 r = kvm_handle_exit(kvm_run, vcpu);
2110 if (r > 0) {
2111 /* Give scheduler a change to reschedule. */
2112 if (signal_pending(current)) {
2113 r = -EINTR;
2114 kvm_run->exit_reason = KVM_EXIT_INTR;
2115 ++vcpu->stat.signal_exits;
2116 goto out;
2117 }
2118
2119 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2120 r = -EINTR;
2121 kvm_run->exit_reason = KVM_EXIT_INTR;
2122 ++vcpu->stat.request_irq_exits;
2123 goto out;
2124 }
2125 if (!need_resched()) {
2126 ++vcpu->stat.light_exits;
2127 goto again;
6aa8b732
AK		 2128 }
2129 }
c1150d8c 2130
e6adf283 2131out:
e6adf283
AK		 2132 if (r > 0) {
2133 kvm_resched(vcpu);
2134 goto preempted;
2135 }
2136
c1150d8c 2137 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2138 return r;
6aa8b732
AK		 2139}
2140
2141static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2142{
2143 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
2144}
2145
2146static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2147 unsigned long addr,
2148 u32 err_code)
2149{
2150 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2151
1165f5fe 2152 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2153
2154 if (is_page_fault(vect_info)) {
2155 printk(KERN_DEBUG "inject_page_fault: "
2156 "double fault 0x%lx @ 0x%lx\n",
2157 addr, vmcs_readl(GUEST_RIP));
2158 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2159 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2160 DF_VECTOR |
2161 INTR_TYPE_EXCEPTION |
2162 INTR_INFO_DELIEVER_CODE_MASK |
2163 INTR_INFO_VALID_MASK);
2164 return;
2165 }
2166 vcpu->cr2 = addr;
2167 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2168 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2169 PF_VECTOR |
2170 INTR_TYPE_EXCEPTION |
2171 INTR_INFO_DELIEVER_CODE_MASK |
2172 INTR_INFO_VALID_MASK);
2173
2174}
2175
2176static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2177{
2178 if (vcpu->vmcs) {
2179 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
2180 free_vmcs(vcpu->vmcs);
2181 vcpu->vmcs = NULL;
2182 }
2183}
2184
2185static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2186{
2187 vmx_free_vmcs(vcpu);
2188}
2189
2190static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
2191{
2192 struct vmcs *vmcs;
2193
965b58a5
IM		 2194 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2195 if (!vcpu->guest_msrs)
2196 return -ENOMEM;
2197
2198 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2199 if (!vcpu->host_msrs)
2200 goto out_free_guest_msrs;
2201
6aa8b732
AK		 2202 vmcs = alloc_vmcs();
2203 if (!vmcs)
965b58a5
IM		 2204 goto out_free_msrs;
2205
6aa8b732
AK		 2206 vmcs_clear(vmcs);
2207 vcpu->vmcs = vmcs;
2208 vcpu->launched = 0;
965b58a5 2209
6aa8b732 2210 return 0;
965b58a5
IM		 2211
2212out_free_msrs:
2213 kfree(vcpu->host_msrs);
2214 vcpu->host_msrs = NULL;
2215
2216out_free_guest_msrs:
2217 kfree(vcpu->guest_msrs);
2218 vcpu->guest_msrs = NULL;
2219
2220 return -ENOMEM;
6aa8b732
AK		 2221}
2222
2223static struct kvm_arch_ops vmx_arch_ops = {
2224 .cpu_has_kvm_support = cpu_has_kvm_support,
2225 .disabled_by_bios = vmx_disabled_by_bios,
2226 .hardware_setup = hardware_setup,
2227 .hardware_unsetup = hardware_unsetup,
2228 .hardware_enable = hardware_enable,
2229 .hardware_disable = hardware_disable,
2230
2231 .vcpu_create = vmx_create_vcpu,
2232 .vcpu_free = vmx_free_vcpu,
2233
2234 .vcpu_load = vmx_vcpu_load,
2235 .vcpu_put = vmx_vcpu_put,
774c47f1 2236 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2237
2238 .set_guest_debug = set_guest_debug,
2239 .get_msr = vmx_get_msr,
2240 .set_msr = vmx_set_msr,
2241 .get_segment_base = vmx_get_segment_base,
2242 .get_segment = vmx_get_segment,
2243 .set_segment = vmx_set_segment,
6aa8b732 2244 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2245 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2246 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2247 .set_cr3 = vmx_set_cr3,
2248 .set_cr4 = vmx_set_cr4,
05b3e0c2 2249#ifdef CONFIG_X86_64
6aa8b732
AK		 2250 .set_efer = vmx_set_efer,
2251#endif
2252 .get_idt = vmx_get_idt,
2253 .set_idt = vmx_set_idt,
2254 .get_gdt = vmx_get_gdt,
2255 .set_gdt = vmx_set_gdt,
2256 .cache_regs = vcpu_load_rsp_rip,
2257 .decache_regs = vcpu_put_rsp_rip,
2258 .get_rflags = vmx_get_rflags,
2259 .set_rflags = vmx_set_rflags,
2260
2261 .tlb_flush = vmx_flush_tlb,
2262 .inject_page_fault = vmx_inject_page_fault,
2263
2264 .inject_gp = vmx_inject_gp,
2265
2266 .run = vmx_vcpu_run,
2267 .skip_emulated_instruction = skip_emulated_instruction,
2268 .vcpu_setup = vmx_vcpu_setup,
102d8325 2269 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2270};
2271
2272static int __init vmx_init(void)
2273{
fdef3ad1
HQ		 2274 void *iova;
2275 int r;
2276
2277 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2278 if (!vmx_io_bitmap_a)
2279 return -ENOMEM;
2280
2281 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2282 if (!vmx_io_bitmap_b) {
2283 r = -ENOMEM;
2284 goto out;
2285 }
2286
2287 /*
2288 * Allow direct access to the PC debug port (it is often used for I/O
2289 * delays, but the vmexits simply slow things down).
2290 */
2291 iova = kmap(vmx_io_bitmap_a);
2292 memset(iova, 0xff, PAGE_SIZE);
2293 clear_bit(0x80, iova);
cd0536d7 2294 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2295
2296 iova = kmap(vmx_io_bitmap_b);
2297 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2298 kunmap(vmx_io_bitmap_b);
fdef3ad1
HQ		 2299
2300 r = kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2301 if (r)
2302 goto out1;
2303
2304 return 0;
2305
2306out1:
2307 __free_page(vmx_io_bitmap_b);
2308out:
2309 __free_page(vmx_io_bitmap_a);
2310 return r;
6aa8b732
AK		 2311}
2312
2313static void __exit vmx_exit(void)
2314{
fdef3ad1
HQ		 2315 __free_page(vmx_io_bitmap_b);
2316 __free_page(vmx_io_bitmap_a);
2317
6aa8b732
AK		 2318 kvm_exit_arch();
2319}
2320
2321module_init(vmx_init)
2322module_exit(vmx_exit)
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