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x86: Raise vsyscall priority on hotplug notifier chain
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 72#define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
74 | X86_CR4_OSXMMEXCPT)
75
cdc0e244
AK		 76#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
78
4b8d54f9
ZE		 79/*
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
89 */
90#define KVM_VMX_DEFAULT_PLE_GAP 41
91#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93module_param(ple_gap, int, S_IRUGO);
94
95static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96module_param(ple_window, int, S_IRUGO);
97
a2fa3e9f
GH		 98struct vmcs {
99 u32 revision_id;
100 u32 abort;
101 char data[0];
102};
103
26bb0981
AK		 104struct shared_msr_entry {
105 unsigned index;
106 u64 data;
d5696725 107 u64 mask;
26bb0981
AK		 108};
109
a2fa3e9f 110struct vcpu_vmx {
fb3f0f51 111 struct kvm_vcpu vcpu;
543e4243 112 struct list_head local_vcpus_link;
313dbd49 113 unsigned long host_rsp;
a2fa3e9f 114 int launched;
29bd8a78 115 u8 fail;
1155f76a 116 u32 idt_vectoring_info;
26bb0981 117 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 118 int nmsrs;
119 int save_nmsrs;
a2fa3e9f 120#ifdef CONFIG_X86_64
44ea2b17
AK		 121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 123#endif
124 struct vmcs *vmcs;
125 struct {
126 int loaded;
127 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
d77c26fc 130 } host_state;
9c8cba37 131 struct {
7ffd92c5
AK		 132 int vm86_active;
133 u8 save_iopl;
134 struct kvm_save_segment {
135 u16 selector;
136 unsigned long base;
137 u32 limit;
138 u32 ar;
139 } tr, es, ds, fs, gs;
9c8cba37
AK		 140 struct {
141 bool pending;
142 u8 vector;
143 unsigned rip;
144 } irq;
145 } rmode;
2384d2b3 146 int vpid;
04fa4d32 147 bool emulation_required;
3b86cd99
JK		 148
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
151 ktime_t entry_time;
152 s64 vnmi_blocked_time;
a0861c02 153 u32 exit_reason;
a2fa3e9f
GH		 154};
155
156static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
157{
fb3f0f51 158 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 159}
160
b7ebfb05 161static int init_rmode(struct kvm *kvm);
4e1096d2 162static u64 construct_eptp(unsigned long root_hpa);
75880a01 163
6aa8b732
AK		 164static DEFINE_PER_CPU(struct vmcs *, vmxarea);
165static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 166static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 167
3e7c73e9
AK		 168static unsigned long *vmx_io_bitmap_a;
169static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 170static unsigned long *vmx_msr_bitmap_legacy;
171static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 172
2384d2b3
SY		 173static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
174static DEFINE_SPINLOCK(vmx_vpid_lock);
175
1c3d14fe 176static struct vmcs_config {
6aa8b732
AK		 177 int size;
178 int order;
179 u32 revision_id;
1c3d14fe
YS		 180 u32 pin_based_exec_ctrl;
181 u32 cpu_based_exec_ctrl;
f78e0e2e 182 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 183 u32 vmexit_ctrl;
184 u32 vmentry_ctrl;
185} vmcs_config;
6aa8b732 186
efff9e53 187static struct vmx_capability {
d56f546d
SY		 188 u32 ept;
189 u32 vpid;
190} vmx_capability;
191
6aa8b732
AK		 192#define VMX_SEGMENT_FIELD(seg) \
193 [VCPU_SREG_##seg] = { \
194 .selector = GUEST_##seg##_SELECTOR, \
195 .base = GUEST_##seg##_BASE, \
196 .limit = GUEST_##seg##_LIMIT, \
197 .ar_bytes = GUEST_##seg##_AR_BYTES, \
198 }
199
200static struct kvm_vmx_segment_field {
201 unsigned selector;
202 unsigned base;
203 unsigned limit;
204 unsigned ar_bytes;
205} kvm_vmx_segment_fields[] = {
206 VMX_SEGMENT_FIELD(CS),
207 VMX_SEGMENT_FIELD(DS),
208 VMX_SEGMENT_FIELD(ES),
209 VMX_SEGMENT_FIELD(FS),
210 VMX_SEGMENT_FIELD(GS),
211 VMX_SEGMENT_FIELD(SS),
212 VMX_SEGMENT_FIELD(TR),
213 VMX_SEGMENT_FIELD(LDTR),
214};
215
26bb0981
AK		 216static u64 host_efer;
217
6de4f3ad
AK		 218static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
219
4d56c8a7
AK		 220/*
221 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
222 * away by decrementing the array size.
223 */
6aa8b732 224static const u32 vmx_msr_index[] = {
05b3e0c2 225#ifdef CONFIG_X86_64
44ea2b17 226 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 227#endif
228 MSR_EFER, MSR_K6_STAR,
229};
9d8f549d 230#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 231
6aa8b732
AK		 232static inline int is_page_fault(u32 intr_info)
233{
234 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
235 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 236 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 237}
238
2ab455cc
AL		 239static inline int is_no_device(u32 intr_info)
240{
241 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
242 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 243 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 244}
245
7aa81cc0
AL		 246static inline int is_invalid_opcode(u32 intr_info)
247{
248 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
249 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 250 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 251}
252
6aa8b732
AK		 253static inline int is_external_interrupt(u32 intr_info)
254{
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
256 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
257}
258
a0861c02
AK		 259static inline int is_machine_check(u32 intr_info)
260{
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
263 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
264}
265
25c5f225
SY		 266static inline int cpu_has_vmx_msr_bitmap(void)
267{
04547156 268 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 269}
270
6e5d865c
YS		 271static inline int cpu_has_vmx_tpr_shadow(void)
272{
04547156 273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 274}
275
276static inline int vm_need_tpr_shadow(struct kvm *kvm)
277{
04547156 278 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 279}
280
f78e0e2e
SY		 281static inline int cpu_has_secondary_exec_ctrls(void)
282{
04547156
SY		 283 return vmcs_config.cpu_based_exec_ctrl &
284 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 285}
286
774ead3a 287static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 288{
04547156
SY		 289 return vmcs_config.cpu_based_2nd_exec_ctrl &
290 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
291}
292
293static inline bool cpu_has_vmx_flexpriority(void)
294{
295 return cpu_has_vmx_tpr_shadow() &&
296 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 297}
298
e799794e
MT		 299static inline bool cpu_has_vmx_ept_execute_only(void)
300{
301 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
302}
303
304static inline bool cpu_has_vmx_eptp_uncacheable(void)
305{
306 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
307}
308
309static inline bool cpu_has_vmx_eptp_writeback(void)
310{
311 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
312}
313
314static inline bool cpu_has_vmx_ept_2m_page(void)
315{
316 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
317}
318
d56f546d
SY		 319static inline int cpu_has_vmx_invept_individual_addr(void)
320{
04547156 321 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 322}
323
324static inline int cpu_has_vmx_invept_context(void)
325{
04547156 326 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 327}
328
329static inline int cpu_has_vmx_invept_global(void)
330{
04547156 331 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 332}
333
334static inline int cpu_has_vmx_ept(void)
335{
04547156
SY		 336 return vmcs_config.cpu_based_2nd_exec_ctrl &
337 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 338}
339
3a624e29
NK		 340static inline int cpu_has_vmx_unrestricted_guest(void)
341{
342 return vmcs_config.cpu_based_2nd_exec_ctrl &
343 SECONDARY_EXEC_UNRESTRICTED_GUEST;
344}
345
4b8d54f9
ZE		 346static inline int cpu_has_vmx_ple(void)
347{
348 return vmcs_config.cpu_based_2nd_exec_ctrl &
349 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
350}
351
f78e0e2e
SY		 352static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
353{
04547156
SY		 354 return flexpriority_enabled &&
355 (cpu_has_vmx_virtualize_apic_accesses()) &&
356 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 357}
358
2384d2b3
SY		 359static inline int cpu_has_vmx_vpid(void)
360{
04547156
SY		 361 return vmcs_config.cpu_based_2nd_exec_ctrl &
362 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 363}
364
f08864b4
SY		 365static inline int cpu_has_virtual_nmis(void)
366{
367 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
368}
369
04547156
SY		 370static inline bool report_flexpriority(void)
371{
372 return flexpriority_enabled;
373}
374
8b9cf98c 375static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 376{
377 int i;
378
a2fa3e9f 379 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 380 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 381 return i;
382 return -1;
383}
384
2384d2b3
SY		 385static inline void __invvpid(int ext, u16 vpid, gva_t gva)
386{
387 struct {
388 u64 vpid : 16;
389 u64 rsvd : 48;
390 u64 gva;
391 } operand = { vpid, 0, gva };
392
4ecac3fd 393 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 394 /* CF==1 or ZF==1 --> rc = -1 */
395 "; ja 1f ; ud2 ; 1:"
396 : : "a"(&operand), "c"(ext) : "cc", "memory");
397}
398
1439442c
SY		 399static inline void __invept(int ext, u64 eptp, gpa_t gpa)
400{
401 struct {
402 u64 eptp, gpa;
403 } operand = {eptp, gpa};
404
4ecac3fd 405 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 406 /* CF==1 or ZF==1 --> rc = -1 */
407 "; ja 1f ; ud2 ; 1:\n"
408 : : "a" (&operand), "c" (ext) : "cc", "memory");
409}
410
26bb0981 411static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 412{
413 int i;
414
8b9cf98c 415 i = __find_msr_index(vmx, msr);
a75beee6 416 if (i >= 0)
a2fa3e9f 417 return &vmx->guest_msrs[i];
8b6d44c7 418 return NULL;
7725f0ba
AK		 419}
420
6aa8b732
AK		 421static void vmcs_clear(struct vmcs *vmcs)
422{
423 u64 phys_addr = __pa(vmcs);
424 u8 error;
425
4ecac3fd 426 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 427 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
428 : "cc", "memory");
429 if (error)
430 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
431 vmcs, phys_addr);
432}
433
434static void __vcpu_clear(void *arg)
435{
8b9cf98c 436 struct vcpu_vmx *vmx = arg;
d3b2c338 437 int cpu = raw_smp_processor_id();
6aa8b732 438
8b9cf98c 439 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 440 vmcs_clear(vmx->vmcs);
441 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 442 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 443 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 444 list_del(&vmx->local_vcpus_link);
445 vmx->vcpu.cpu = -1;
446 vmx->launched = 0;
6aa8b732
AK		 447}
448
8b9cf98c 449static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 450{
eae5ecb5
AK		 451 if (vmx->vcpu.cpu == -1)
452 return;
8691e5a8 453 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 454}
455
2384d2b3
SY		 456static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
457{
458 if (vmx->vpid == 0)
459 return;
460
461 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
462}
463
1439442c
SY		 464static inline void ept_sync_global(void)
465{
466 if (cpu_has_vmx_invept_global())
467 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
468}
469
470static inline void ept_sync_context(u64 eptp)
471{
089d034e 472 if (enable_ept) {
1439442c
SY		 473 if (cpu_has_vmx_invept_context())
474 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
475 else
476 ept_sync_global();
477 }
478}
479
480static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
481{
089d034e 482 if (enable_ept) {
1439442c
SY		 483 if (cpu_has_vmx_invept_individual_addr())
484 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
485 eptp, gpa);
486 else
487 ept_sync_context(eptp);
488 }
489}
490
6aa8b732
AK		 491static unsigned long vmcs_readl(unsigned long field)
492{
493 unsigned long value;
494
4ecac3fd 495 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 496 : "=a"(value) : "d"(field) : "cc");
497 return value;
498}
499
500static u16 vmcs_read16(unsigned long field)
501{
502 return vmcs_readl(field);
503}
504
505static u32 vmcs_read32(unsigned long field)
506{
507 return vmcs_readl(field);
508}
509
510static u64 vmcs_read64(unsigned long field)
511{
05b3e0c2 512#ifdef CONFIG_X86_64
6aa8b732
AK		 513 return vmcs_readl(field);
514#else
515 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
516#endif
517}
518
e52de1b8
AK		 519static noinline void vmwrite_error(unsigned long field, unsigned long value)
520{
521 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
522 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
523 dump_stack();
524}
525
6aa8b732
AK		 526static void vmcs_writel(unsigned long field, unsigned long value)
527{
528 u8 error;
529
4ecac3fd 530 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 531 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 532 if (unlikely(error))
533 vmwrite_error(field, value);
6aa8b732
AK		 534}
535
536static void vmcs_write16(unsigned long field, u16 value)
537{
538 vmcs_writel(field, value);
539}
540
541static void vmcs_write32(unsigned long field, u32 value)
542{
543 vmcs_writel(field, value);
544}
545
546static void vmcs_write64(unsigned long field, u64 value)
547{
6aa8b732 548 vmcs_writel(field, value);
7682f2d0 549#ifndef CONFIG_X86_64
6aa8b732
AK		 550 asm volatile ("");
551 vmcs_writel(field+1, value >> 32);
552#endif
553}
554
2ab455cc
AL		 555static void vmcs_clear_bits(unsigned long field, u32 mask)
556{
557 vmcs_writel(field, vmcs_readl(field) & ~mask);
558}
559
560static void vmcs_set_bits(unsigned long field, u32 mask)
561{
562 vmcs_writel(field, vmcs_readl(field) | mask);
563}
564
abd3f2d6
AK		 565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
566{
567 u32 eb;
568
a0861c02 569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 570 if (!vcpu->fpu_active)
571 eb |= 1u << NM_VECTOR;
e8a48342
AK		 572 /*
573 * Unconditionally intercept #DB so we can maintain dr6 without
574 * reading it every exit.
575 */
576 eb |= 1u << DB_VECTOR;
d0bfb940 577 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 578 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
579 eb |= 1u << BP_VECTOR;
580 }
7ffd92c5 581 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 582 eb = ~0;
089d034e 583 if (enable_ept)
1439442c 584 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 585 vmcs_write32(EXCEPTION_BITMAP, eb);
586}
587
33ed6329
AK		 588static void reload_tss(void)
589{
33ed6329
AK		 590 /*
591 * VT restores TR but not its size. Useless.
592 */
593 struct descriptor_table gdt;
a5f61300 594 struct desc_struct *descs;
33ed6329 595
d6e88aec 596 kvm_get_gdt(&gdt);
33ed6329
AK		 597 descs = (void *)gdt.base;
598 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
599 load_TR_desc();
33ed6329
AK		 600}
601
92c0d900 602static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 603{
3a34a881 604 u64 guest_efer;
51c6cf66
AK		 605 u64 ignore_bits;
606
26bb0981 607 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 608
51c6cf66
AK		 609 /*
610 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
611 * outside long mode
612 */
613 ignore_bits = EFER_NX | EFER_SCE;
614#ifdef CONFIG_X86_64
615 ignore_bits |= EFER_LMA | EFER_LME;
616 /* SCE is meaningful only in long mode on Intel */
617 if (guest_efer & EFER_LMA)
618 ignore_bits &= ~(u64)EFER_SCE;
619#endif
51c6cf66
AK		 620 guest_efer &= ~ignore_bits;
621 guest_efer |= host_efer & ignore_bits;
26bb0981 622 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 623 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 624 return true;
51c6cf66
AK		 625}
626
04d2cc77 627static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 628{
04d2cc77 629 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 630 int i;
04d2cc77 631
a2fa3e9f 632 if (vmx->host_state.loaded)
33ed6329
AK		 633 return;
634
a2fa3e9f 635 vmx->host_state.loaded = 1;
33ed6329
AK		 636 /*
637 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
638 * allow segment selectors with cpl > 0 or ti == 1.
639 */
d6e88aec 640 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 641 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 642 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 643 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 644 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 645 vmx->host_state.fs_reload_needed = 0;
646 } else {
33ed6329 647 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 648 vmx->host_state.fs_reload_needed = 1;
33ed6329 649 }
d6e88aec 650 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 651 if (!(vmx->host_state.gs_sel & 7))
652 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 653 else {
654 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 655 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 656 }
657
658#ifdef CONFIG_X86_64
659 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
660 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
661#else
a2fa3e9f
GH		 662 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
663 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 664#endif
707c0874
AK		 665
666#ifdef CONFIG_X86_64
44ea2b17
AK		 667 if (is_long_mode(&vmx->vcpu)) {
668 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
669 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
670 }
707c0874 671#endif
26bb0981
AK		 672 for (i = 0; i < vmx->save_nmsrs; ++i)
673 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 674 vmx->guest_msrs[i].data,
675 vmx->guest_msrs[i].mask);
33ed6329
AK		 676}
677
a9b21b62 678static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 679{
15ad7146 680 unsigned long flags;
33ed6329 681
a2fa3e9f 682 if (!vmx->host_state.loaded)
33ed6329
AK		 683 return;
684
e1beb1d3 685 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 686 vmx->host_state.loaded = 0;
152d3f2f 687 if (vmx->host_state.fs_reload_needed)
d6e88aec 688 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 689 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 690 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 691 /*
692 * If we have to reload gs, we must take care to
693 * preserve our gs base.
694 */
15ad7146 695 local_irq_save(flags);
d6e88aec 696 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 697#ifdef CONFIG_X86_64
698 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
699#endif
15ad7146 700 local_irq_restore(flags);
33ed6329 701 }
152d3f2f 702 reload_tss();
44ea2b17
AK		 703#ifdef CONFIG_X86_64
704 if (is_long_mode(&vmx->vcpu)) {
705 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
706 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
707 }
708#endif
33ed6329
AK		 709}
710
a9b21b62
AK		 711static void vmx_load_host_state(struct vcpu_vmx *vmx)
712{
713 preempt_disable();
714 __vmx_load_host_state(vmx);
715 preempt_enable();
716}
717
6aa8b732
AK		 718/*
719 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
720 * vcpu mutex is already taken.
721 */
15ad7146 722static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 723{
a2fa3e9f
GH		 724 struct vcpu_vmx *vmx = to_vmx(vcpu);
725 u64 phys_addr = __pa(vmx->vmcs);
019960ae 726 u64 tsc_this, delta, new_offset;
6aa8b732 727
a3d7f85f 728 if (vcpu->cpu != cpu) {
8b9cf98c 729 vcpu_clear(vmx);
2f599714 730 kvm_migrate_timers(vcpu);
eb5109e3 731 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 732 local_irq_disable();
733 list_add(&vmx->local_vcpus_link,
734 &per_cpu(vcpus_on_cpu, cpu));
735 local_irq_enable();
a3d7f85f 736 }
6aa8b732 737
a2fa3e9f 738 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 739 u8 error;
740
a2fa3e9f 741 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 742 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 743 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
744 : "cc");
745 if (error)
746 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 747 vmx->vmcs, phys_addr);
6aa8b732
AK		 748 }
749
750 if (vcpu->cpu != cpu) {
751 struct descriptor_table dt;
752 unsigned long sysenter_esp;
753
754 vcpu->cpu = cpu;
755 /*
756 * Linux uses per-cpu TSS and GDT, so set these when switching
757 * processors.
758 */
d6e88aec
AK		 759 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
760 kvm_get_gdt(&dt);
6aa8b732
AK		 761 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
762
763 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
764 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 765
766 /*
767 * Make sure the time stamp counter is monotonous.
768 */
769 rdtscll(tsc_this);
019960ae
AK		 770 if (tsc_this < vcpu->arch.host_tsc) {
771 delta = vcpu->arch.host_tsc - tsc_this;
772 new_offset = vmcs_read64(TSC_OFFSET) + delta;
773 vmcs_write64(TSC_OFFSET, new_offset);
774 }
6aa8b732 775 }
6aa8b732
AK		 776}
777
778static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
779{
a9b21b62 780 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 781}
782
5fd86fcf
AK		 783static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
784{
785 if (vcpu->fpu_active)
786 return;
787 vcpu->fpu_active = 1;
707d92fa 788 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 789 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 790 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 791 update_exception_bitmap(vcpu);
792}
793
794static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
795{
796 if (!vcpu->fpu_active)
797 return;
798 vcpu->fpu_active = 0;
707d92fa 799 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 800 update_exception_bitmap(vcpu);
801}
802
6aa8b732
AK		 803static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
804{
345dcaa8
AK		 805 unsigned long rflags;
806
807 rflags = vmcs_readl(GUEST_RFLAGS);
808 if (to_vmx(vcpu)->rmode.vm86_active)
809 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
810 return rflags;
6aa8b732
AK		 811}
812
813static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
814{
7ffd92c5 815 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 816 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 817 vmcs_writel(GUEST_RFLAGS, rflags);
818}
819
2809f5d2
GC		 820static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
821{
822 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
823 int ret = 0;
824
825 if (interruptibility & GUEST_INTR_STATE_STI)
826 ret |= X86_SHADOW_INT_STI;
827 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
828 ret |= X86_SHADOW_INT_MOV_SS;
829
830 return ret & mask;
831}
832
833static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
834{
835 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
836 u32 interruptibility = interruptibility_old;
837
838 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
839
840 if (mask & X86_SHADOW_INT_MOV_SS)
841 interruptibility |= GUEST_INTR_STATE_MOV_SS;
842 if (mask & X86_SHADOW_INT_STI)
843 interruptibility |= GUEST_INTR_STATE_STI;
844
845 if ((interruptibility != interruptibility_old))
846 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
847}
848
6aa8b732
AK		 849static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
850{
851 unsigned long rip;
6aa8b732 852
5fdbf976 853 rip = kvm_rip_read(vcpu);
6aa8b732 854 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 855 kvm_rip_write(vcpu, rip);
6aa8b732 856
2809f5d2
GC		 857 /* skipping an emulated instruction also counts */
858 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 859}
860
298101da
AK		 861static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
862 bool has_error_code, u32 error_code)
863{
77ab6db0 864 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 865 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 866
8ab2d2e2 867 if (has_error_code) {
77ab6db0 868 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 869 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
870 }
77ab6db0 871
7ffd92c5 872 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 873 vmx->rmode.irq.pending = true;
874 vmx->rmode.irq.vector = nr;
875 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 876 if (kvm_exception_is_soft(nr))
877 vmx->rmode.irq.rip +=
878 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 879 intr_info |= INTR_TYPE_SOFT_INTR;
880 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 881 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
882 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
883 return;
884 }
885
66fd3f7f
GN		 886 if (kvm_exception_is_soft(nr)) {
887 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
888 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 889 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
890 } else
891 intr_info |= INTR_TYPE_HARD_EXCEPTION;
892
893 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 894}
895
a75beee6
ED		 896/*
897 * Swap MSR entry in host/guest MSR entry array.
898 */
8b9cf98c 899static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 900{
26bb0981 901 struct shared_msr_entry tmp;
a2fa3e9f
GH		 902
903 tmp = vmx->guest_msrs[to];
904 vmx->guest_msrs[to] = vmx->guest_msrs[from];
905 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 906}
907
e38aea3e
AK		 908/*
909 * Set up the vmcs to automatically save and restore system
910 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
911 * mode, as fiddling with msrs is very expensive.
912 */
8b9cf98c 913static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 914{
26bb0981 915 int save_nmsrs, index;
5897297b 916 unsigned long *msr_bitmap;
e38aea3e 917
33f9c505 918 vmx_load_host_state(vmx);
a75beee6
ED		 919 save_nmsrs = 0;
920#ifdef CONFIG_X86_64
8b9cf98c 921 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 922 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 923 if (index >= 0)
8b9cf98c
RR		 924 move_msr_up(vmx, index, save_nmsrs++);
925 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 926 if (index >= 0)
8b9cf98c
RR		 927 move_msr_up(vmx, index, save_nmsrs++);
928 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 929 if (index >= 0)
8b9cf98c 930 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 931 /*
932 * MSR_K6_STAR is only needed on long mode guests, and only
933 * if efer.sce is enabled.
934 */
8b9cf98c 935 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 936 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 937 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 938 }
939#endif
92c0d900
AK		 940 index = __find_msr_index(vmx, MSR_EFER);
941 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 942 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 943
26bb0981 944 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 945
946 if (cpu_has_vmx_msr_bitmap()) {
947 if (is_long_mode(&vmx->vcpu))
948 msr_bitmap = vmx_msr_bitmap_longmode;
949 else
950 msr_bitmap = vmx_msr_bitmap_legacy;
951
952 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
953 }
e38aea3e
AK		 954}
955
6aa8b732
AK		 956/*
957 * reads and returns guest's timestamp counter "register"
958 * guest_tsc = host_tsc + tsc_offset -- 21.3
959 */
960static u64 guest_read_tsc(void)
961{
962 u64 host_tsc, tsc_offset;
963
964 rdtscll(host_tsc);
965 tsc_offset = vmcs_read64(TSC_OFFSET);
966 return host_tsc + tsc_offset;
967}
968
969/*
970 * writes 'guest_tsc' into guest's timestamp counter "register"
971 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
972 */
53f658b3 973static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 974{
6aa8b732
AK		 975 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
976}
977
6aa8b732
AK		 978/*
979 * Reads an msr value (of 'msr_index') into 'pdata'.
980 * Returns 0 on success, non-0 otherwise.
981 * Assumes vcpu_load() was already called.
982 */
983static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
984{
985 u64 data;
26bb0981 986 struct shared_msr_entry *msr;
6aa8b732
AK		 987
988 if (!pdata) {
989 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
990 return -EINVAL;
991 }
992
993 switch (msr_index) {
05b3e0c2 994#ifdef CONFIG_X86_64
6aa8b732
AK		 995 case MSR_FS_BASE:
996 data = vmcs_readl(GUEST_FS_BASE);
997 break;
998 case MSR_GS_BASE:
999 data = vmcs_readl(GUEST_GS_BASE);
1000 break;
44ea2b17
AK		 1001 case MSR_KERNEL_GS_BASE:
1002 vmx_load_host_state(to_vmx(vcpu));
1003 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1004 break;
26bb0981 1005#endif
6aa8b732 1006 case MSR_EFER:
3bab1f5d 1007 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1008 case MSR_IA32_TSC:
6aa8b732
AK		 1009 data = guest_read_tsc();
1010 break;
1011 case MSR_IA32_SYSENTER_CS:
1012 data = vmcs_read32(GUEST_SYSENTER_CS);
1013 break;
1014 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1015 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1016 break;
1017 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1018 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1019 break;
6aa8b732 1020 default:
26bb0981 1021 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1022 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1023 if (msr) {
542423b0 1024 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1025 data = msr->data;
1026 break;
6aa8b732 1027 }
3bab1f5d 1028 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1029 }
1030
1031 *pdata = data;
1032 return 0;
1033}
1034
1035/*
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1039 */
1040static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1041{
a2fa3e9f 1042 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1043 struct shared_msr_entry *msr;
53f658b3 1044 u64 host_tsc;
2cc51560
ED		 1045 int ret = 0;
1046
6aa8b732 1047 switch (msr_index) {
3bab1f5d 1048 case MSR_EFER:
a9b21b62 1049 vmx_load_host_state(vmx);
2cc51560 1050 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1051 break;
16175a79 1052#ifdef CONFIG_X86_64
6aa8b732
AK		 1053 case MSR_FS_BASE:
1054 vmcs_writel(GUEST_FS_BASE, data);
1055 break;
1056 case MSR_GS_BASE:
1057 vmcs_writel(GUEST_GS_BASE, data);
1058 break;
44ea2b17
AK		 1059 case MSR_KERNEL_GS_BASE:
1060 vmx_load_host_state(vmx);
1061 vmx->msr_guest_kernel_gs_base = data;
1062 break;
6aa8b732
AK		 1063#endif
1064 case MSR_IA32_SYSENTER_CS:
1065 vmcs_write32(GUEST_SYSENTER_CS, data);
1066 break;
1067 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1068 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1069 break;
1070 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1071 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1072 break;
af24a4e4 1073 case MSR_IA32_TSC:
53f658b3
MT		 1074 rdtscll(host_tsc);
1075 guest_write_tsc(data, host_tsc);
6aa8b732 1076 break;
468d472f
SY		 1077 case MSR_IA32_CR_PAT:
1078 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1079 vmcs_write64(GUEST_IA32_PAT, data);
1080 vcpu->arch.pat = data;
1081 break;
1082 }
1083 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1084 default:
8b9cf98c 1085 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1086 if (msr) {
542423b0 1087 vmx_load_host_state(vmx);
3bab1f5d
AK		 1088 msr->data = data;
1089 break;
6aa8b732 1090 }
2cc51560 1091 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1092 }
1093
2cc51560 1094 return ret;
6aa8b732
AK		 1095}
1096
5fdbf976 1097static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1098{
5fdbf976
MT		 1099 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1100 switch (reg) {
1101 case VCPU_REGS_RSP:
1102 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1103 break;
1104 case VCPU_REGS_RIP:
1105 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1106 break;
6de4f3ad
AK		 1107 case VCPU_EXREG_PDPTR:
1108 if (enable_ept)
1109 ept_save_pdptrs(vcpu);
1110 break;
5fdbf976
MT		 1111 default:
1112 break;
1113 }
6aa8b732
AK		 1114}
1115
355be0b9 1116static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1117{
ae675ef0
JK		 1118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1120 else
1121 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1122
abd3f2d6 1123 update_exception_bitmap(vcpu);
6aa8b732
AK		 1124}
1125
1126static __init int cpu_has_kvm_support(void)
1127{
6210e37b 1128 return cpu_has_vmx();
6aa8b732
AK		 1129}
1130
1131static __init int vmx_disabled_by_bios(void)
1132{
1133 u64 msr;
1134
1135 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1136 return (msr & (FEATURE_CONTROL_LOCKED |
1137 FEATURE_CONTROL_VMXON_ENABLED))
1138 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1139 /* locked but not enabled */
6aa8b732
AK		 1140}
1141
10474ae8 1142static int hardware_enable(void *garbage)
6aa8b732
AK		 1143{
1144 int cpu = raw_smp_processor_id();
1145 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1146 u64 old;
1147
10474ae8
AG		 1148 if (read_cr4() & X86_CR4_VMXE)
1149 return -EBUSY;
1150
543e4243 1151 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1152 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1153 if ((old & (FEATURE_CONTROL_LOCKED |
1154 FEATURE_CONTROL_VMXON_ENABLED))
1155 != (FEATURE_CONTROL_LOCKED |
1156 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1157 /* enable and lock */
62b3ffb8 1158 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1159 FEATURE_CONTROL_LOCKED |
1160 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1161 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1162 asm volatile (ASM_VMX_VMXON_RAX
1163 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1164 : "memory", "cc");
10474ae8
AG		 1165
1166 ept_sync_global();
1167
1168 return 0;
6aa8b732
AK		 1169}
1170
543e4243
AK		 1171static void vmclear_local_vcpus(void)
1172{
1173 int cpu = raw_smp_processor_id();
1174 struct vcpu_vmx *vmx, *n;
1175
1176 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1177 local_vcpus_link)
1178 __vcpu_clear(vmx);
1179}
1180
710ff4a8
EH		 1181
1182/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1183 * tricks.
1184 */
1185static void kvm_cpu_vmxoff(void)
6aa8b732 1186{
4ecac3fd 1187 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1188 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1189}
1190
710ff4a8
EH		 1191static void hardware_disable(void *garbage)
1192{
1193 vmclear_local_vcpus();
1194 kvm_cpu_vmxoff();
1195}
1196
1c3d14fe 1197static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1198 u32 msr, u32 *result)
1c3d14fe
YS		 1199{
1200 u32 vmx_msr_low, vmx_msr_high;
1201 u32 ctl = ctl_min | ctl_opt;
1202
1203 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1204
1205 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1206 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1207
1208 /* Ensure minimum (required) set of control bits are supported. */
1209 if (ctl_min & ~ctl)
002c7f7c 1210 return -EIO;
1c3d14fe
YS		 1211
1212 *result = ctl;
1213 return 0;
1214}
1215
002c7f7c 1216static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1217{
1218 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1219 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1220 u32 _pin_based_exec_control = 0;
1221 u32 _cpu_based_exec_control = 0;
f78e0e2e 1222 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1223 u32 _vmexit_control = 0;
1224 u32 _vmentry_control = 0;
1225
1226 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1227 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1228 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1229 &_pin_based_exec_control) < 0)
002c7f7c 1230 return -EIO;
1c3d14fe
YS		 1231
1232 min = CPU_BASED_HLT_EXITING |
1233#ifdef CONFIG_X86_64
1234 CPU_BASED_CR8_LOAD_EXITING |
1235 CPU_BASED_CR8_STORE_EXITING |
1236#endif
d56f546d
SY		 1237 CPU_BASED_CR3_LOAD_EXITING |
1238 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1239 CPU_BASED_USE_IO_BITMAPS |
1240 CPU_BASED_MOV_DR_EXITING |
a7052897 1241 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1242 CPU_BASED_MWAIT_EXITING |
1243 CPU_BASED_MONITOR_EXITING |
a7052897 1244 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1245 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1246 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1247 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1248 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1249 &_cpu_based_exec_control) < 0)
002c7f7c 1250 return -EIO;
6e5d865c
YS		 1251#ifdef CONFIG_X86_64
1252 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1253 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1254 ~CPU_BASED_CR8_STORE_EXITING;
1255#endif
f78e0e2e 1256 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1257 min2 = 0;
1258 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1259 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1260 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1261 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1262 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1263 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1264 if (adjust_vmx_controls(min2, opt2,
1265 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1266 &_cpu_based_2nd_exec_control) < 0)
1267 return -EIO;
1268 }
1269#ifndef CONFIG_X86_64
1270 if (!(_cpu_based_2nd_exec_control &
1271 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1272 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1273#endif
d56f546d 1274 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1275 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1276 enabled */
5fff7d27
GN		 1277 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1278 CPU_BASED_CR3_STORE_EXITING |
1279 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1280 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1281 vmx_capability.ept, vmx_capability.vpid);
1282 }
1c3d14fe
YS		 1283
1284 min = 0;
1285#ifdef CONFIG_X86_64
1286 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1287#endif
468d472f 1288 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1289 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1290 &_vmexit_control) < 0)
002c7f7c 1291 return -EIO;
1c3d14fe 1292
468d472f
SY		 1293 min = 0;
1294 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1295 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1296 &_vmentry_control) < 0)
002c7f7c 1297 return -EIO;
6aa8b732 1298
c68876fd 1299 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1300
1301 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1302 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1303 return -EIO;
1c3d14fe
YS		 1304
1305#ifdef CONFIG_X86_64
1306 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1307 if (vmx_msr_high & (1u<<16))
002c7f7c 1308 return -EIO;
1c3d14fe
YS		 1309#endif
1310
1311 /* Require Write-Back (WB) memory type for VMCS accesses. */
1312 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1313 return -EIO;
1c3d14fe 1314
002c7f7c
YS		 1315 vmcs_conf->size = vmx_msr_high & 0x1fff;
1316 vmcs_conf->order = get_order(vmcs_config.size);
1317 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1318
002c7f7c
YS		 1319 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1320 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1321 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1322 vmcs_conf->vmexit_ctrl = _vmexit_control;
1323 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1324
1325 return 0;
c68876fd 1326}
6aa8b732
AK		 1327
1328static struct vmcs *alloc_vmcs_cpu(int cpu)
1329{
1330 int node = cpu_to_node(cpu);
1331 struct page *pages;
1332 struct vmcs *vmcs;
1333
6484eb3e 1334 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1335 if (!pages)
1336 return NULL;
1337 vmcs = page_address(pages);
1c3d14fe
YS		 1338 memset(vmcs, 0, vmcs_config.size);
1339 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1340 return vmcs;
1341}
1342
1343static struct vmcs *alloc_vmcs(void)
1344{
d3b2c338 1345 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1346}
1347
1348static void free_vmcs(struct vmcs *vmcs)
1349{
1c3d14fe 1350 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1351}
1352
39959588 1353static void free_kvm_area(void)
6aa8b732
AK		 1354{
1355 int cpu;
1356
3230bb47 1357 for_each_possible_cpu(cpu) {
6aa8b732 1358 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1359 per_cpu(vmxarea, cpu) = NULL;
1360 }
6aa8b732
AK		 1361}
1362
6aa8b732
AK		 1363static __init int alloc_kvm_area(void)
1364{
1365 int cpu;
1366
3230bb47 1367 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1368 struct vmcs *vmcs;
1369
1370 vmcs = alloc_vmcs_cpu(cpu);
1371 if (!vmcs) {
1372 free_kvm_area();
1373 return -ENOMEM;
1374 }
1375
1376 per_cpu(vmxarea, cpu) = vmcs;
1377 }
1378 return 0;
1379}
1380
1381static __init int hardware_setup(void)
1382{
002c7f7c
YS		 1383 if (setup_vmcs_config(&vmcs_config) < 0)
1384 return -EIO;
50a37eb4
JR		 1385
1386 if (boot_cpu_has(X86_FEATURE_NX))
1387 kvm_enable_efer_bits(EFER_NX);
1388
93ba03c2
SY		 1389 if (!cpu_has_vmx_vpid())
1390 enable_vpid = 0;
1391
3a624e29 1392 if (!cpu_has_vmx_ept()) {
93ba03c2 1393 enable_ept = 0;
3a624e29
NK		 1394 enable_unrestricted_guest = 0;
1395 }
1396
1397 if (!cpu_has_vmx_unrestricted_guest())
1398 enable_unrestricted_guest = 0;
93ba03c2
SY		 1399
1400 if (!cpu_has_vmx_flexpriority())
1401 flexpriority_enabled = 0;
1402
95ba8273
GN		 1403 if (!cpu_has_vmx_tpr_shadow())
1404 kvm_x86_ops->update_cr8_intercept = NULL;
1405
54dee993
MT		 1406 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1407 kvm_disable_largepages();
1408
4b8d54f9
ZE		 1409 if (!cpu_has_vmx_ple())
1410 ple_gap = 0;
1411
6aa8b732
AK		 1412 return alloc_kvm_area();
1413}
1414
1415static __exit void hardware_unsetup(void)
1416{
1417 free_kvm_area();
1418}
1419
6aa8b732
AK		 1420static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1421{
1422 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1423
6af11b9e 1424 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1425 vmcs_write16(sf->selector, save->selector);
1426 vmcs_writel(sf->base, save->base);
1427 vmcs_write32(sf->limit, save->limit);
1428 vmcs_write32(sf->ar_bytes, save->ar);
1429 } else {
1430 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1431 << AR_DPL_SHIFT;
1432 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1433 }
1434}
1435
1436static void enter_pmode(struct kvm_vcpu *vcpu)
1437{
1438 unsigned long flags;
a89a8fb9 1439 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1440
a89a8fb9 1441 vmx->emulation_required = 1;
7ffd92c5 1442 vmx->rmode.vm86_active = 0;
6aa8b732 1443
7ffd92c5
AK		 1444 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1445 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1446 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1447
1448 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1449 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1450 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1451 vmcs_writel(GUEST_RFLAGS, flags);
1452
66aee91a
RR		 1453 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1454 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1455
1456 update_exception_bitmap(vcpu);
1457
a89a8fb9
MG		 1458 if (emulate_invalid_guest_state)
1459 return;
1460
7ffd92c5
AK		 1461 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1462 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1463 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1464 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1465
1466 vmcs_write16(GUEST_SS_SELECTOR, 0);
1467 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1468
1469 vmcs_write16(GUEST_CS_SELECTOR,
1470 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1471 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1472}
1473
d77c26fc 1474static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1475{
bfc6d222 1476 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1477 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1478 kvm->memslots[0].npages - 3;
1479 return base_gfn << PAGE_SHIFT;
1480 }
bfc6d222 1481 return kvm->arch.tss_addr;
6aa8b732
AK		 1482}
1483
1484static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1485{
1486 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1487
1488 save->selector = vmcs_read16(sf->selector);
1489 save->base = vmcs_readl(sf->base);
1490 save->limit = vmcs_read32(sf->limit);
1491 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1492 vmcs_write16(sf->selector, save->base >> 4);
1493 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1494 vmcs_write32(sf->limit, 0xffff);
1495 vmcs_write32(sf->ar_bytes, 0xf3);
1496}
1497
1498static void enter_rmode(struct kvm_vcpu *vcpu)
1499{
1500 unsigned long flags;
a89a8fb9 1501 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1502
3a624e29
NK		 1503 if (enable_unrestricted_guest)
1504 return;
1505
a89a8fb9 1506 vmx->emulation_required = 1;
7ffd92c5 1507 vmx->rmode.vm86_active = 1;
6aa8b732 1508
7ffd92c5 1509 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1510 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1511
7ffd92c5 1512 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1513 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1514
7ffd92c5 1515 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1516 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1517
1518 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1519 vmx->rmode.save_iopl
ad312c7c 1520 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1521
053de044 1522 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1523
1524 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1525 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1526 update_exception_bitmap(vcpu);
1527
a89a8fb9
MG		 1528 if (emulate_invalid_guest_state)
1529 goto continue_rmode;
1530
6aa8b732
AK		 1531 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1532 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1533 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1534
1535 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1536 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1537 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1538 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1539 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1540
7ffd92c5
AK		 1541 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1542 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1543 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1544 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1545
a89a8fb9 1546continue_rmode:
8668a3c4 1547 kvm_mmu_reset_context(vcpu);
b7ebfb05 1548 init_rmode(vcpu->kvm);
6aa8b732
AK		 1549}
1550
401d10de
AS		 1551static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1552{
1553 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1554 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1555
1556 if (!msr)
1557 return;
401d10de 1558
44ea2b17
AK		 1559 /*
1560 * Force kernel_gs_base reloading before EFER changes, as control
1561 * of this msr depends on is_long_mode().
1562 */
1563 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1564 vcpu->arch.shadow_efer = efer;
1565 if (!msr)
1566 return;
1567 if (efer & EFER_LMA) {
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS) |
1570 VM_ENTRY_IA32E_MODE);
1571 msr->data = efer;
1572 } else {
1573 vmcs_write32(VM_ENTRY_CONTROLS,
1574 vmcs_read32(VM_ENTRY_CONTROLS) &
1575 ~VM_ENTRY_IA32E_MODE);
1576
1577 msr->data = efer & ~EFER_LME;
1578 }
1579 setup_msrs(vmx);
1580}
1581
05b3e0c2 1582#ifdef CONFIG_X86_64
6aa8b732
AK		 1583
1584static void enter_lmode(struct kvm_vcpu *vcpu)
1585{
1586 u32 guest_tr_ar;
1587
1588 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1589 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1590 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1591 __func__);
6aa8b732
AK		 1592 vmcs_write32(GUEST_TR_AR_BYTES,
1593 (guest_tr_ar & ~AR_TYPE_MASK)
1594 | AR_TYPE_BUSY_64_TSS);
1595 }
ad312c7c 1596 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1597 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1598}
1599
1600static void exit_lmode(struct kvm_vcpu *vcpu)
1601{
ad312c7c 1602 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1603
1604 vmcs_write32(VM_ENTRY_CONTROLS,
1605 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1606 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1607}
1608
1609#endif
1610
2384d2b3
SY		 1611static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1612{
1613 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1614 if (enable_ept)
4e1096d2 1615 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1616}
1617
25c4c276 1618static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1619{
fc78f519
AK		 1620 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1621
1622 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1623 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1624}
1625
1439442c
SY		 1626static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1627{
6de4f3ad
AK		 1628 if (!test_bit(VCPU_EXREG_PDPTR,
1629 (unsigned long *)&vcpu->arch.regs_dirty))
1630 return;
1631
1439442c 1632 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1633 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1634 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1635 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1636 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1637 }
1638}
1639
8f5d549f
AK		 1640static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1641{
1642 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1643 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1644 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1645 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1646 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1647 }
6de4f3ad
AK		 1648
1649 __set_bit(VCPU_EXREG_PDPTR,
1650 (unsigned long *)&vcpu->arch.regs_avail);
1651 __set_bit(VCPU_EXREG_PDPTR,
1652 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1653}
1654
1439442c
SY		 1655static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1656
1657static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1658 unsigned long cr0,
1659 struct kvm_vcpu *vcpu)
1660{
1661 if (!(cr0 & X86_CR0_PG)) {
1662 /* From paging/starting to nonpaging */
1663 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1664 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1665 (CPU_BASED_CR3_LOAD_EXITING |
1666 CPU_BASED_CR3_STORE_EXITING));
1667 vcpu->arch.cr0 = cr0;
fc78f519 1668 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1669 } else if (!is_paging(vcpu)) {
1670 /* From nonpaging to paging */
1671 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1672 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1673 ~(CPU_BASED_CR3_LOAD_EXITING |
1674 CPU_BASED_CR3_STORE_EXITING));
1675 vcpu->arch.cr0 = cr0;
fc78f519 1676 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1677 }
95eb84a7
SY		 1678
1679 if (!(cr0 & X86_CR0_WP))
1680 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1681}
1682
6aa8b732
AK		 1683static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1684{
7ffd92c5 1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1686 unsigned long hw_cr0;
1687
1688 if (enable_unrestricted_guest)
1689 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1690 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1691 else
1692 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1693
5fd86fcf
AK		 1694 vmx_fpu_deactivate(vcpu);
1695
7ffd92c5 1696 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1697 enter_pmode(vcpu);
1698
7ffd92c5 1699 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1700 enter_rmode(vcpu);
1701
05b3e0c2 1702#ifdef CONFIG_X86_64
ad312c7c 1703 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1704 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1705 enter_lmode(vcpu);
707d92fa 1706 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1707 exit_lmode(vcpu);
1708 }
1709#endif
1710
089d034e 1711 if (enable_ept)
1439442c
SY		 1712 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1713
6aa8b732 1714 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1715 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1716 vcpu->arch.cr0 = cr0;
5fd86fcf 1717
707d92fa 1718 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1719 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1720}
1721
1439442c
SY		 1722static u64 construct_eptp(unsigned long root_hpa)
1723{
1724 u64 eptp;
1725
1726 /* TODO write the value reading from MSR */
1727 eptp = VMX_EPT_DEFAULT_MT |
1728 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1729 eptp |= (root_hpa & PAGE_MASK);
1730
1731 return eptp;
1732}
1733
6aa8b732
AK		 1734static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1735{
1439442c
SY		 1736 unsigned long guest_cr3;
1737 u64 eptp;
1738
1739 guest_cr3 = cr3;
089d034e 1740 if (enable_ept) {
1439442c
SY		 1741 eptp = construct_eptp(cr3);
1742 vmcs_write64(EPT_POINTER, eptp);
1439442c 1743 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1744 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1745 ept_load_pdptrs(vcpu);
1439442c
SY		 1746 }
1747
2384d2b3 1748 vmx_flush_tlb(vcpu);
1439442c 1749 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1750 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1751 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1752}
1753
1754static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1755{
7ffd92c5 1756 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1757 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1758
ad312c7c 1759 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1760 if (enable_ept) {
1761 if (!is_paging(vcpu)) {
1762 hw_cr4 &= ~X86_CR4_PAE;
1763 hw_cr4 |= X86_CR4_PSE;
1764 } else if (!(cr4 & X86_CR4_PAE)) {
1765 hw_cr4 &= ~X86_CR4_PAE;
1766 }
1767 }
1439442c
SY		 1768
1769 vmcs_writel(CR4_READ_SHADOW, cr4);
1770 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1771}
1772
6aa8b732
AK		 1773static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1774{
1775 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1776
1777 return vmcs_readl(sf->base);
1778}
1779
1780static void vmx_get_segment(struct kvm_vcpu *vcpu,
1781 struct kvm_segment *var, int seg)
1782{
1783 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1784 u32 ar;
1785
1786 var->base = vmcs_readl(sf->base);
1787 var->limit = vmcs_read32(sf->limit);
1788 var->selector = vmcs_read16(sf->selector);
1789 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1790 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1791 ar = 0;
1792 var->type = ar & 15;
1793 var->s = (ar >> 4) & 1;
1794 var->dpl = (ar >> 5) & 3;
1795 var->present = (ar >> 7) & 1;
1796 var->avl = (ar >> 12) & 1;
1797 var->l = (ar >> 13) & 1;
1798 var->db = (ar >> 14) & 1;
1799 var->g = (ar >> 15) & 1;
1800 var->unusable = (ar >> 16) & 1;
1801}
1802
2e4d2653
IE		 1803static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1804{
2e4d2653
IE		 1805 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1806 return 0;
1807
1808 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1809 return 3;
1810
eab4b8aa 1811 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1812}
1813
653e3108 1814static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1815{
6aa8b732
AK		 1816 u32 ar;
1817
653e3108 1818 if (var->unusable)
6aa8b732
AK		 1819 ar = 1 << 16;
1820 else {
1821 ar = var->type & 15;
1822 ar |= (var->s & 1) << 4;
1823 ar |= (var->dpl & 3) << 5;
1824 ar |= (var->present & 1) << 7;
1825 ar |= (var->avl & 1) << 12;
1826 ar |= (var->l & 1) << 13;
1827 ar |= (var->db & 1) << 14;
1828 ar |= (var->g & 1) << 15;
1829 }
f7fbf1fd
UL		 1830 if (ar == 0) /* a 0 value means unusable */
1831 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1832
1833 return ar;
1834}
1835
1836static void vmx_set_segment(struct kvm_vcpu *vcpu,
1837 struct kvm_segment *var, int seg)
1838{
7ffd92c5 1839 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1840 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1841 u32 ar;
1842
7ffd92c5
AK		 1843 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1844 vmx->rmode.tr.selector = var->selector;
1845 vmx->rmode.tr.base = var->base;
1846 vmx->rmode.tr.limit = var->limit;
1847 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1848 return;
1849 }
1850 vmcs_writel(sf->base, var->base);
1851 vmcs_write32(sf->limit, var->limit);
1852 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1853 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1854 /*
1855 * Hack real-mode segments into vm86 compatibility.
1856 */
1857 if (var->base == 0xffff0000 && var->selector == 0xf000)
1858 vmcs_writel(sf->base, 0xf0000);
1859 ar = 0xf3;
1860 } else
1861 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1862
1863 /*
1864 * Fix the "Accessed" bit in AR field of segment registers for older
1865 * qemu binaries.
1866 * IA32 arch specifies that at the time of processor reset the
1867 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1868 * is setting it to 0 in the usedland code. This causes invalid guest
1869 * state vmexit when "unrestricted guest" mode is turned on.
1870 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1871 * tree. Newer qemu binaries with that qemu fix would not need this
1872 * kvm hack.
1873 */
1874 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1875 ar |= 0x1; /* Accessed */
1876
6aa8b732
AK		 1877 vmcs_write32(sf->ar_bytes, ar);
1878}
1879
6aa8b732
AK		 1880static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1881{
1882 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1883
1884 *db = (ar >> 14) & 1;
1885 *l = (ar >> 13) & 1;
1886}
1887
1888static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1889{
1890 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1891 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1892}
1893
1894static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1895{
1896 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1897 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1898}
1899
1900static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1901{
1902 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1903 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1904}
1905
1906static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1907{
1908 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1909 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1910}
1911
648dfaa7
MG		 1912static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1913{
1914 struct kvm_segment var;
1915 u32 ar;
1916
1917 vmx_get_segment(vcpu, &var, seg);
1918 ar = vmx_segment_access_rights(&var);
1919
1920 if (var.base != (var.selector << 4))
1921 return false;
1922 if (var.limit != 0xffff)
1923 return false;
1924 if (ar != 0xf3)
1925 return false;
1926
1927 return true;
1928}
1929
1930static bool code_segment_valid(struct kvm_vcpu *vcpu)
1931{
1932 struct kvm_segment cs;
1933 unsigned int cs_rpl;
1934
1935 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1936 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1937
1872a3f4
AK		 1938 if (cs.unusable)
1939 return false;
648dfaa7
MG		 1940 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1941 return false;
1942 if (!cs.s)
1943 return false;
1872a3f4 1944 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1945 if (cs.dpl > cs_rpl)
1946 return false;
1872a3f4 1947 } else {
648dfaa7
MG		 1948 if (cs.dpl != cs_rpl)
1949 return false;
1950 }
1951 if (!cs.present)
1952 return false;
1953
1954 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1955 return true;
1956}
1957
1958static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1959{
1960 struct kvm_segment ss;
1961 unsigned int ss_rpl;
1962
1963 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1964 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1965
1872a3f4
AK		 1966 if (ss.unusable)
1967 return true;
1968 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1969 return false;
1970 if (!ss.s)
1971 return false;
1972 if (ss.dpl != ss_rpl) /* DPL != RPL */
1973 return false;
1974 if (!ss.present)
1975 return false;
1976
1977 return true;
1978}
1979
1980static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1981{
1982 struct kvm_segment var;
1983 unsigned int rpl;
1984
1985 vmx_get_segment(vcpu, &var, seg);
1986 rpl = var.selector & SELECTOR_RPL_MASK;
1987
1872a3f4
AK		 1988 if (var.unusable)
1989 return true;
648dfaa7
MG		 1990 if (!var.s)
1991 return false;
1992 if (!var.present)
1993 return false;
1994 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1995 if (var.dpl < rpl) /* DPL < RPL */
1996 return false;
1997 }
1998
1999 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2000 * rights flags
2001 */
2002 return true;
2003}
2004
2005static bool tr_valid(struct kvm_vcpu *vcpu)
2006{
2007 struct kvm_segment tr;
2008
2009 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2010
1872a3f4
AK		 2011 if (tr.unusable)
2012 return false;
648dfaa7
MG		 2013 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2014 return false;
1872a3f4 2015 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2016 return false;
2017 if (!tr.present)
2018 return false;
2019
2020 return true;
2021}
2022
2023static bool ldtr_valid(struct kvm_vcpu *vcpu)
2024{
2025 struct kvm_segment ldtr;
2026
2027 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2028
1872a3f4
AK		 2029 if (ldtr.unusable)
2030 return true;
648dfaa7
MG		 2031 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2032 return false;
2033 if (ldtr.type != 2)
2034 return false;
2035 if (!ldtr.present)
2036 return false;
2037
2038 return true;
2039}
2040
2041static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2042{
2043 struct kvm_segment cs, ss;
2044
2045 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2046 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2047
2048 return ((cs.selector & SELECTOR_RPL_MASK) ==
2049 (ss.selector & SELECTOR_RPL_MASK));
2050}
2051
2052/*
2053 * Check if guest state is valid. Returns true if valid, false if
2054 * not.
2055 * We assume that registers are always usable
2056 */
2057static bool guest_state_valid(struct kvm_vcpu *vcpu)
2058{
2059 /* real mode guest state checks */
2060 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2061 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2062 return false;
2063 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2064 return false;
2065 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2066 return false;
2067 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2068 return false;
2069 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2070 return false;
2071 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2072 return false;
2073 } else {
2074 /* protected mode guest state checks */
2075 if (!cs_ss_rpl_check(vcpu))
2076 return false;
2077 if (!code_segment_valid(vcpu))
2078 return false;
2079 if (!stack_segment_valid(vcpu))
2080 return false;
2081 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2082 return false;
2083 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2084 return false;
2085 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2086 return false;
2087 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2088 return false;
2089 if (!tr_valid(vcpu))
2090 return false;
2091 if (!ldtr_valid(vcpu))
2092 return false;
2093 }
2094 /* TODO:
2095 * - Add checks on RIP
2096 * - Add checks on RFLAGS
2097 */
2098
2099 return true;
2100}
2101
d77c26fc 2102static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2103{
6aa8b732 2104 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2105 u16 data = 0;
10589a46 2106 int ret = 0;
195aefde 2107 int r;
6aa8b732 2108
195aefde
IE		 2109 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2110 if (r < 0)
10589a46 2111 goto out;
195aefde 2112 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2113 r = kvm_write_guest_page(kvm, fn++, &data,
2114 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2115 if (r < 0)
10589a46 2116 goto out;
195aefde
IE		 2117 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2118 if (r < 0)
10589a46 2119 goto out;
195aefde
IE		 2120 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2121 if (r < 0)
10589a46 2122 goto out;
195aefde 2123 data = ~0;
10589a46
MT		 2124 r = kvm_write_guest_page(kvm, fn, &data,
2125 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2126 sizeof(u8));
195aefde 2127 if (r < 0)
10589a46
MT		 2128 goto out;
2129
2130 ret = 1;
2131out:
10589a46 2132 return ret;
6aa8b732
AK		 2133}
2134
b7ebfb05
SY		 2135static int init_rmode_identity_map(struct kvm *kvm)
2136{
2137 int i, r, ret;
2138 pfn_t identity_map_pfn;
2139 u32 tmp;
2140
089d034e 2141 if (!enable_ept)
b7ebfb05
SY		 2142 return 1;
2143 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2144 printk(KERN_ERR "EPT: identity-mapping pagetable "
2145 "haven't been allocated!\n");
2146 return 0;
2147 }
2148 if (likely(kvm->arch.ept_identity_pagetable_done))
2149 return 1;
2150 ret = 0;
b927a3ce 2151 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2152 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2153 if (r < 0)
2154 goto out;
2155 /* Set up identity-mapping pagetable for EPT in real mode */
2156 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2157 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2158 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2159 r = kvm_write_guest_page(kvm, identity_map_pfn,
2160 &tmp, i * sizeof(tmp), sizeof(tmp));
2161 if (r < 0)
2162 goto out;
2163 }
2164 kvm->arch.ept_identity_pagetable_done = true;
2165 ret = 1;
2166out:
2167 return ret;
2168}
2169
6aa8b732
AK		 2170static void seg_setup(int seg)
2171{
2172 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2173 unsigned int ar;
6aa8b732
AK		 2174
2175 vmcs_write16(sf->selector, 0);
2176 vmcs_writel(sf->base, 0);
2177 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2178 if (enable_unrestricted_guest) {
2179 ar = 0x93;
2180 if (seg == VCPU_SREG_CS)
2181 ar |= 0x08; /* code segment */
2182 } else
2183 ar = 0xf3;
2184
2185 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2186}
2187
f78e0e2e
SY		 2188static int alloc_apic_access_page(struct kvm *kvm)
2189{
2190 struct kvm_userspace_memory_region kvm_userspace_mem;
2191 int r = 0;
2192
72dc67a6 2193 down_write(&kvm->slots_lock);
bfc6d222 2194 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2195 goto out;
2196 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2197 kvm_userspace_mem.flags = 0;
2198 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2199 kvm_userspace_mem.memory_size = PAGE_SIZE;
2200 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2201 if (r)
2202 goto out;
72dc67a6 2203
bfc6d222 2204 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2205out:
72dc67a6 2206 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2207 return r;
2208}
2209
b7ebfb05
SY		 2210static int alloc_identity_pagetable(struct kvm *kvm)
2211{
2212 struct kvm_userspace_memory_region kvm_userspace_mem;
2213 int r = 0;
2214
2215 down_write(&kvm->slots_lock);
2216 if (kvm->arch.ept_identity_pagetable)
2217 goto out;
2218 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2219 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2220 kvm_userspace_mem.guest_phys_addr =
2221 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2222 kvm_userspace_mem.memory_size = PAGE_SIZE;
2223 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2224 if (r)
2225 goto out;
2226
b7ebfb05 2227 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2228 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2229out:
2230 up_write(&kvm->slots_lock);
2231 return r;
2232}
2233
2384d2b3
SY		 2234static void allocate_vpid(struct vcpu_vmx *vmx)
2235{
2236 int vpid;
2237
2238 vmx->vpid = 0;
919818ab 2239 if (!enable_vpid)
2384d2b3
SY		 2240 return;
2241 spin_lock(&vmx_vpid_lock);
2242 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2243 if (vpid < VMX_NR_VPIDS) {
2244 vmx->vpid = vpid;
2245 __set_bit(vpid, vmx_vpid_bitmap);
2246 }
2247 spin_unlock(&vmx_vpid_lock);
2248}
2249
5897297b 2250static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2251{
3e7c73e9 2252 int f = sizeof(unsigned long);
25c5f225
SY		 2253
2254 if (!cpu_has_vmx_msr_bitmap())
2255 return;
2256
2257 /*
2258 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2259 * have the write-low and read-high bitmap offsets the wrong way round.
2260 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2261 */
25c5f225 2262 if (msr <= 0x1fff) {
3e7c73e9
AK		 2263 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2264 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2265 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2266 msr &= 0x1fff;
3e7c73e9
AK		 2267 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2268 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2269 }
25c5f225
SY		 2270}
2271
5897297b
AK		 2272static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2273{
2274 if (!longmode_only)
2275 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2276 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2277}
2278
6aa8b732
AK		 2279/*
2280 * Sets up the vmcs for emulated real mode.
2281 */
8b9cf98c 2282static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2283{
468d472f 2284 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2285 u32 junk;
53f658b3 2286 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2287 unsigned long a;
2288 struct descriptor_table dt;
2289 int i;
cd2276a7 2290 unsigned long kvm_vmx_return;
6e5d865c 2291 u32 exec_control;
6aa8b732 2292
6aa8b732 2293 /* I/O */
3e7c73e9
AK		 2294 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2295 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2296
25c5f225 2297 if (cpu_has_vmx_msr_bitmap())
5897297b 2298 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2299
6aa8b732
AK		 2300 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2301
6aa8b732 2302 /* Control */
1c3d14fe
YS		 2303 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2304 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2305
2306 exec_control = vmcs_config.cpu_based_exec_ctrl;
2307 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2308 exec_control &= ~CPU_BASED_TPR_SHADOW;
2309#ifdef CONFIG_X86_64
2310 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2311 CPU_BASED_CR8_LOAD_EXITING;
2312#endif
2313 }
089d034e 2314 if (!enable_ept)
d56f546d 2315 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2316 CPU_BASED_CR3_LOAD_EXITING |
2317 CPU_BASED_INVLPG_EXITING;
6e5d865c 2318 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2319
83ff3b9d
SY		 2320 if (cpu_has_secondary_exec_ctrls()) {
2321 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2322 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2323 exec_control &=
2324 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2325 if (vmx->vpid == 0)
2326 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2327 if (!enable_ept) {
d56f546d 2328 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2329 enable_unrestricted_guest = 0;
2330 }
3a624e29
NK		 2331 if (!enable_unrestricted_guest)
2332 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2333 if (!ple_gap)
2334 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2335 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2336 }
f78e0e2e 2337
4b8d54f9
ZE		 2338 if (ple_gap) {
2339 vmcs_write32(PLE_GAP, ple_gap);
2340 vmcs_write32(PLE_WINDOW, ple_window);
2341 }
2342
c7addb90
AK		 2343 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2344 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2345 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2346
2347 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2348 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2349 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2350
2351 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2352 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2353 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2354 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2355 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2356 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2357#ifdef CONFIG_X86_64
6aa8b732
AK		 2358 rdmsrl(MSR_FS_BASE, a);
2359 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2360 rdmsrl(MSR_GS_BASE, a);
2361 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2362#else
2363 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2364 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2365#endif
2366
2367 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2368
d6e88aec 2369 kvm_get_idt(&dt);
6aa8b732
AK		 2370 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2371
d77c26fc 2372 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2373 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2374 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2376 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2377
2378 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2379 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2380 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2381 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2382 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2383 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2384
468d472f
SY		 2385 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2386 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2387 host_pat = msr_low | ((u64) msr_high << 32);
2388 vmcs_write64(HOST_IA32_PAT, host_pat);
2389 }
2390 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2391 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2392 host_pat = msr_low | ((u64) msr_high << 32);
2393 /* Write the default value follow host pat */
2394 vmcs_write64(GUEST_IA32_PAT, host_pat);
2395 /* Keep arch.pat sync with GUEST_IA32_PAT */
2396 vmx->vcpu.arch.pat = host_pat;
2397 }
2398
6aa8b732
AK		 2399 for (i = 0; i < NR_VMX_MSR; ++i) {
2400 u32 index = vmx_msr_index[i];
2401 u32 data_low, data_high;
a2fa3e9f 2402 int j = vmx->nmsrs;
6aa8b732
AK		 2403
2404 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2405 continue;
432bd6cb
AK		 2406 if (wrmsr_safe(index, data_low, data_high) < 0)
2407 continue;
26bb0981
AK		 2408 vmx->guest_msrs[j].index = i;
2409 vmx->guest_msrs[j].data = 0;
d5696725 2410 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2411 ++vmx->nmsrs;
6aa8b732 2412 }
6aa8b732 2413
1c3d14fe 2414 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2415
2416 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2417 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2418
e00c8cf2 2419 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2420 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2421 if (enable_ept)
2422 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2423 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2424
53f658b3
MT		 2425 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2426 rdtscll(tsc_this);
2427 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2428 tsc_base = tsc_this;
2429
2430 guest_write_tsc(0, tsc_base);
f78e0e2e 2431
e00c8cf2
AK		 2432 return 0;
2433}
2434
b7ebfb05
SY		 2435static int init_rmode(struct kvm *kvm)
2436{
2437 if (!init_rmode_tss(kvm))
2438 return 0;
2439 if (!init_rmode_identity_map(kvm))
2440 return 0;
2441 return 1;
2442}
2443
e00c8cf2
AK		 2444static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2445{
2446 struct vcpu_vmx *vmx = to_vmx(vcpu);
2447 u64 msr;
2448 int ret;
2449
5fdbf976 2450 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2451 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2452 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2453 ret = -ENOMEM;
2454 goto out;
2455 }
2456
7ffd92c5 2457 vmx->rmode.vm86_active = 0;
e00c8cf2 2458
3b86cd99
JK		 2459 vmx->soft_vnmi_blocked = 0;
2460
ad312c7c 2461 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2462 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2463 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2464 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2465 msr |= MSR_IA32_APICBASE_BSP;
2466 kvm_set_apic_base(&vmx->vcpu, msr);
2467
2468 fx_init(&vmx->vcpu);
2469
5706be0d 2470 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2471 /*
2472 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2473 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2474 */
c5af89b6 2475 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2476 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2477 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2478 } else {
ad312c7c
ZX		 2479 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2480 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2481 }
e00c8cf2
AK		 2482
2483 seg_setup(VCPU_SREG_DS);
2484 seg_setup(VCPU_SREG_ES);
2485 seg_setup(VCPU_SREG_FS);
2486 seg_setup(VCPU_SREG_GS);
2487 seg_setup(VCPU_SREG_SS);
2488
2489 vmcs_write16(GUEST_TR_SELECTOR, 0);
2490 vmcs_writel(GUEST_TR_BASE, 0);
2491 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2492 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2493
2494 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2495 vmcs_writel(GUEST_LDTR_BASE, 0);
2496 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2497 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2498
2499 vmcs_write32(GUEST_SYSENTER_CS, 0);
2500 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2501 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2502
2503 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2504 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2505 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2506 else
5fdbf976
MT		 2507 kvm_rip_write(vcpu, 0);
2508 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2509
e00c8cf2
AK		 2510 vmcs_writel(GUEST_DR7, 0x400);
2511
2512 vmcs_writel(GUEST_GDTR_BASE, 0);
2513 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2514
2515 vmcs_writel(GUEST_IDTR_BASE, 0);
2516 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2517
2518 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2519 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2520 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2521
e00c8cf2
AK		 2522 /* Special registers */
2523 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2524
2525 setup_msrs(vmx);
2526
6aa8b732
AK		 2527 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2528
f78e0e2e
SY		 2529 if (cpu_has_vmx_tpr_shadow()) {
2530 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2531 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2532 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2533 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2534 vmcs_write32(TPR_THRESHOLD, 0);
2535 }
2536
2537 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2538 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2539 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2540
2384d2b3
SY		 2541 if (vmx->vpid != 0)
2542 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2543
fa40052c 2544 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2545 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2546 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2547 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2548 vmx_fpu_activate(&vmx->vcpu);
2549 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2550
2384d2b3
SY		 2551 vpid_sync_vcpu_all(vmx);
2552
3200f405 2553 ret = 0;
6aa8b732 2554
a89a8fb9
MG		 2555 /* HACK: Don't enable emulation on guest boot/reset */
2556 vmx->emulation_required = 0;
2557
6aa8b732 2558out:
3200f405 2559 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2560 return ret;
2561}
2562
3b86cd99
JK		 2563static void enable_irq_window(struct kvm_vcpu *vcpu)
2564{
2565 u32 cpu_based_vm_exec_control;
2566
2567 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2568 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2570}
2571
2572static void enable_nmi_window(struct kvm_vcpu *vcpu)
2573{
2574 u32 cpu_based_vm_exec_control;
2575
2576 if (!cpu_has_virtual_nmis()) {
2577 enable_irq_window(vcpu);
2578 return;
2579 }
2580
2581 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2582 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2583 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2584}
2585
66fd3f7f 2586static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2587{
9c8cba37 2588 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2589 uint32_t intr;
2590 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2591
229456fc 2592 trace_kvm_inj_virq(irq);
2714d1d3 2593
fa89a817 2594 ++vcpu->stat.irq_injections;
7ffd92c5 2595 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2596 vmx->rmode.irq.pending = true;
2597 vmx->rmode.irq.vector = irq;
5fdbf976 2598 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2599 if (vcpu->arch.interrupt.soft)
2600 vmx->rmode.irq.rip +=
2601 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2602 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2603 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2604 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2605 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2606 return;
2607 }
66fd3f7f
GN		 2608 intr = irq | INTR_INFO_VALID_MASK;
2609 if (vcpu->arch.interrupt.soft) {
2610 intr |= INTR_TYPE_SOFT_INTR;
2611 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2612 vmx->vcpu.arch.event_exit_inst_len);
2613 } else
2614 intr |= INTR_TYPE_EXT_INTR;
2615 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2616}
2617
f08864b4
SY		 2618static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2619{
66a5a347
JK		 2620 struct vcpu_vmx *vmx = to_vmx(vcpu);
2621
3b86cd99
JK		 2622 if (!cpu_has_virtual_nmis()) {
2623 /*
2624 * Tracking the NMI-blocked state in software is built upon
2625 * finding the next open IRQ window. This, in turn, depends on
2626 * well-behaving guests: They have to keep IRQs disabled at
2627 * least as long as the NMI handler runs. Otherwise we may
2628 * cause NMI nesting, maybe breaking the guest. But as this is
2629 * highly unlikely, we can live with the residual risk.
2630 */
2631 vmx->soft_vnmi_blocked = 1;
2632 vmx->vnmi_blocked_time = 0;
2633 }
2634
487b391d 2635 ++vcpu->stat.nmi_injections;
7ffd92c5 2636 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2637 vmx->rmode.irq.pending = true;
2638 vmx->rmode.irq.vector = NMI_VECTOR;
2639 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2640 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2641 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2642 INTR_INFO_VALID_MASK);
2643 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2644 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2645 return;
2646 }
f08864b4
SY		 2647 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2648 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2649}
2650
c4282df9 2651static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2652{
3b86cd99 2653 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2654 return 0;
33f089ca 2655
c4282df9
GN		 2656 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2657 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2658 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2659}
2660
3cfc3092
JK		 2661static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2662{
2663 if (!cpu_has_virtual_nmis())
2664 return to_vmx(vcpu)->soft_vnmi_blocked;
2665 else
2666 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2667 GUEST_INTR_STATE_NMI);
2668}
2669
2670static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2671{
2672 struct vcpu_vmx *vmx = to_vmx(vcpu);
2673
2674 if (!cpu_has_virtual_nmis()) {
2675 if (vmx->soft_vnmi_blocked != masked) {
2676 vmx->soft_vnmi_blocked = masked;
2677 vmx->vnmi_blocked_time = 0;
2678 }
2679 } else {
2680 if (masked)
2681 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2682 GUEST_INTR_STATE_NMI);
2683 else
2684 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2685 GUEST_INTR_STATE_NMI);
2686 }
2687}
2688
78646121
GN		 2689static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2690{
c4282df9
GN		 2691 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2692 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2693 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2694}
2695
cbc94022
IE		 2696static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2697{
2698 int ret;
2699 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2700 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2701 .guest_phys_addr = addr,
2702 .memory_size = PAGE_SIZE * 3,
2703 .flags = 0,
2704 };
2705
2706 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2707 if (ret)
2708 return ret;
bfc6d222 2709 kvm->arch.tss_addr = addr;
cbc94022
IE		 2710 return 0;
2711}
2712
6aa8b732
AK		 2713static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2714 int vec, u32 err_code)
2715{
b3f37707
NK		 2716 /*
2717 * Instruction with address size override prefix opcode 0x67
2718 * Cause the #SS fault with 0 error code in VM86 mode.
2719 */
2720 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2721 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2722 return 1;
77ab6db0
JK		 2723 /*
2724 * Forward all other exceptions that are valid in real mode.
2725 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2726 * the required debugging infrastructure rework.
2727 */
2728 switch (vec) {
77ab6db0 2729 case DB_VECTOR:
d0bfb940
JK		 2730 if (vcpu->guest_debug &
2731 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2732 return 0;
2733 kvm_queue_exception(vcpu, vec);
2734 return 1;
77ab6db0 2735 case BP_VECTOR:
d0bfb940
JK		 2736 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2737 return 0;
2738 /* fall through */
2739 case DE_VECTOR:
77ab6db0
JK		 2740 case OF_VECTOR:
2741 case BR_VECTOR:
2742 case UD_VECTOR:
2743 case DF_VECTOR:
2744 case SS_VECTOR:
2745 case GP_VECTOR:
2746 case MF_VECTOR:
2747 kvm_queue_exception(vcpu, vec);
2748 return 1;
2749 }
6aa8b732
AK		 2750 return 0;
2751}
2752
a0861c02
AK		 2753/*
2754 * Trigger machine check on the host. We assume all the MSRs are already set up
2755 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2756 * We pass a fake environment to the machine check handler because we want
2757 * the guest to be always treated like user space, no matter what context
2758 * it used internally.
2759 */
2760static void kvm_machine_check(void)
2761{
2762#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2763 struct pt_regs regs = {
2764 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2765 .flags = X86_EFLAGS_IF,
2766 };
2767
2768 do_machine_check(&regs, 0);
2769#endif
2770}
2771
851ba692 2772static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2773{
2774 /* already handled by vcpu_run */
2775 return 1;
2776}
2777
851ba692 2778static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2779{
1155f76a 2780 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2781 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2782 u32 intr_info, ex_no, error_code;
42dbaa5a 2783 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2784 u32 vect_info;
2785 enum emulation_result er;
2786
1155f76a 2787 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2788 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2789
a0861c02 2790 if (is_machine_check(intr_info))
851ba692 2791 return handle_machine_check(vcpu);
a0861c02 2792
6aa8b732 2793 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2794 !is_page_fault(intr_info)) {
2795 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2796 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2797 vcpu->run->internal.ndata = 2;
2798 vcpu->run->internal.data[0] = vect_info;
2799 vcpu->run->internal.data[1] = intr_info;
2800 return 0;
2801 }
6aa8b732 2802
e4a41889 2803 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2804 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2805
2806 if (is_no_device(intr_info)) {
5fd86fcf 2807 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2808 return 1;
2809 }
2810
7aa81cc0 2811 if (is_invalid_opcode(intr_info)) {
851ba692 2812 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2813 if (er != EMULATE_DONE)
7ee5d940 2814 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2815 return 1;
2816 }
2817
6aa8b732 2818 error_code = 0;
5fdbf976 2819 rip = kvm_rip_read(vcpu);
2e11384c 2820 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2821 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2822 if (is_page_fault(intr_info)) {
1439442c 2823 /* EPT won't cause page fault directly */
089d034e 2824 if (enable_ept)
1439442c 2825 BUG();
6aa8b732 2826 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2827 trace_kvm_page_fault(cr2, error_code);
2828
3298b75c 2829 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2830 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2831 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2832 }
2833
7ffd92c5 2834 if (vmx->rmode.vm86_active &&
6aa8b732 2835 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2836 error_code)) {
ad312c7c
ZX		 2837 if (vcpu->arch.halt_request) {
2838 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2839 return kvm_emulate_halt(vcpu);
2840 }
6aa8b732 2841 return 1;
72d6e5a0 2842 }
6aa8b732 2843
d0bfb940 2844 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2845 switch (ex_no) {
2846 case DB_VECTOR:
2847 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2848 if (!(vcpu->guest_debug &
2849 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2850 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2851 kvm_queue_exception(vcpu, DB_VECTOR);
2852 return 1;
2853 }
2854 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2855 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2856 /* fall through */
2857 case BP_VECTOR:
6aa8b732 2858 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2859 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2860 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2861 break;
2862 default:
d0bfb940
JK		 2863 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2864 kvm_run->ex.exception = ex_no;
2865 kvm_run->ex.error_code = error_code;
42dbaa5a 2866 break;
6aa8b732 2867 }
6aa8b732
AK		 2868 return 0;
2869}
2870
851ba692 2871static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2872{
1165f5fe 2873 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2874 return 1;
2875}
2876
851ba692 2877static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2878{
851ba692 2879 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2880 return 0;
2881}
6aa8b732 2882
851ba692 2883static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2884{
bfdaab09 2885 unsigned long exit_qualification;
34c33d16 2886 int size, in, string;
039576c0 2887 unsigned port;
6aa8b732 2888
1165f5fe 2889 ++vcpu->stat.io_exits;
bfdaab09 2890 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2891 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2892
2893 if (string) {
851ba692 2894 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2895 return 0;
2896 return 1;
2897 }
2898
2899 size = (exit_qualification & 7) + 1;
2900 in = (exit_qualification & 8) != 0;
039576c0 2901 port = exit_qualification >> 16;
e70669ab 2902
e93f36bc 2903 skip_emulated_instruction(vcpu);
851ba692 2904 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2905}
2906
102d8325
IM		 2907static void
2908vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2909{
2910 /*
2911 * Patch in the VMCALL instruction:
2912 */
2913 hypercall[0] = 0x0f;
2914 hypercall[1] = 0x01;
2915 hypercall[2] = 0xc1;
102d8325
IM		 2916}
2917
851ba692 2918static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2919{
229456fc 2920 unsigned long exit_qualification, val;
6aa8b732
AK		 2921 int cr;
2922 int reg;
2923
bfdaab09 2924 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2925 cr = exit_qualification & 15;
2926 reg = (exit_qualification >> 8) & 15;
2927 switch ((exit_qualification >> 4) & 3) {
2928 case 0: /* mov to cr */
229456fc
MT		 2929 val = kvm_register_read(vcpu, reg);
2930 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2931 switch (cr) {
2932 case 0:
229456fc 2933 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2934 skip_emulated_instruction(vcpu);
2935 return 1;
2936 case 3:
229456fc 2937 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2938 skip_emulated_instruction(vcpu);
2939 return 1;
2940 case 4:
229456fc 2941 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2942 skip_emulated_instruction(vcpu);
2943 return 1;
0a5fff19
GN		 2944 case 8: {
2945 u8 cr8_prev = kvm_get_cr8(vcpu);
2946 u8 cr8 = kvm_register_read(vcpu, reg);
2947 kvm_set_cr8(vcpu, cr8);
2948 skip_emulated_instruction(vcpu);
2949 if (irqchip_in_kernel(vcpu->kvm))
2950 return 1;
2951 if (cr8_prev <= cr8)
2952 return 1;
851ba692 2953 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2954 return 0;
2955 }
6aa8b732
AK		 2956 };
2957 break;
25c4c276 2958 case 2: /* clts */
5fd86fcf 2959 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2960 vcpu->arch.cr0 &= ~X86_CR0_TS;
2961 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2962 vmx_fpu_activate(vcpu);
25c4c276
AL		 2963 skip_emulated_instruction(vcpu);
2964 return 1;
6aa8b732
AK		 2965 case 1: /*mov from cr*/
2966 switch (cr) {
2967 case 3:
5fdbf976 2968 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2969 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2970 skip_emulated_instruction(vcpu);
2971 return 1;
2972 case 8:
229456fc
MT		 2973 val = kvm_get_cr8(vcpu);
2974 kvm_register_write(vcpu, reg, val);
2975 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2976 skip_emulated_instruction(vcpu);
2977 return 1;
2978 }
2979 break;
2980 case 3: /* lmsw */
2d3ad1f4 2981 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2982
2983 skip_emulated_instruction(vcpu);
2984 return 1;
2985 default:
2986 break;
2987 }
851ba692 2988 vcpu->run->exit_reason = 0;
f0242478 2989 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2990 (int)(exit_qualification >> 4) & 3, cr);
2991 return 0;
2992}
2993
851ba692 2994static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2995{
bfdaab09 2996 unsigned long exit_qualification;
6aa8b732
AK		 2997 unsigned long val;
2998 int dr, reg;
2999
0a79b009
AK		 3000 if (!kvm_require_cpl(vcpu, 0))
3001 return 1;
42dbaa5a
JK		 3002 dr = vmcs_readl(GUEST_DR7);
3003 if (dr & DR7_GD) {
3004 /*
3005 * As the vm-exit takes precedence over the debug trap, we
3006 * need to emulate the latter, either for the host or the
3007 * guest debugging itself.
3008 */
3009 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3010 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3011 vcpu->run->debug.arch.dr7 = dr;
3012 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3013 vmcs_readl(GUEST_CS_BASE) +
3014 vmcs_readl(GUEST_RIP);
851ba692
AK		 3015 vcpu->run->debug.arch.exception = DB_VECTOR;
3016 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3017 return 0;
3018 } else {
3019 vcpu->arch.dr7 &= ~DR7_GD;
3020 vcpu->arch.dr6 |= DR6_BD;
3021 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3022 kvm_queue_exception(vcpu, DB_VECTOR);
3023 return 1;
3024 }
3025 }
3026
bfdaab09 3027 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3028 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3029 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3030 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3031 switch (dr) {
42dbaa5a
JK		 3032 case 0 ... 3:
3033 val = vcpu->arch.db[dr];
3034 break;
6aa8b732 3035 case 6:
42dbaa5a 3036 val = vcpu->arch.dr6;
6aa8b732
AK		 3037 break;
3038 case 7:
42dbaa5a 3039 val = vcpu->arch.dr7;
6aa8b732
AK		 3040 break;
3041 default:
3042 val = 0;
3043 }
5fdbf976 3044 kvm_register_write(vcpu, reg, val);
6aa8b732 3045 } else {
42dbaa5a
JK		 3046 val = vcpu->arch.regs[reg];
3047 switch (dr) {
3048 case 0 ... 3:
3049 vcpu->arch.db[dr] = val;
3050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3051 vcpu->arch.eff_db[dr] = val;
3052 break;
3053 case 4 ... 5:
fc78f519 3054 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
42dbaa5a
JK		 3055 kvm_queue_exception(vcpu, UD_VECTOR);
3056 break;
3057 case 6:
3058 if (val & 0xffffffff00000000ULL) {
3059 kvm_queue_exception(vcpu, GP_VECTOR);
3060 break;
3061 }
3062 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3063 break;
3064 case 7:
3065 if (val & 0xffffffff00000000ULL) {
3066 kvm_queue_exception(vcpu, GP_VECTOR);
3067 break;
3068 }
3069 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3070 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3071 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3072 vcpu->arch.switch_db_regs =
3073 (val & DR7_BP_EN_MASK);
3074 }
3075 break;
3076 }
6aa8b732 3077 }
6aa8b732
AK		 3078 skip_emulated_instruction(vcpu);
3079 return 1;
3080}
3081
851ba692 3082static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3083{
06465c5a
AK		 3084 kvm_emulate_cpuid(vcpu);
3085 return 1;
6aa8b732
AK		 3086}
3087
851ba692 3088static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3089{
ad312c7c 3090 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3091 u64 data;
3092
3093 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3094 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3095 return 1;
3096 }
3097
229456fc 3098 trace_kvm_msr_read(ecx, data);
2714d1d3 3099
6aa8b732 3100 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3101 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3102 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3103 skip_emulated_instruction(vcpu);
3104 return 1;
3105}
3106
851ba692 3107static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3108{
ad312c7c
ZX		 3109 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3110 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3111 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3112
229456fc 3113 trace_kvm_msr_write(ecx, data);
2714d1d3 3114
6aa8b732 3115 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3116 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3117 return 1;
3118 }
3119
3120 skip_emulated_instruction(vcpu);
3121 return 1;
3122}
3123
851ba692 3124static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3125{
3126 return 1;
3127}
3128
851ba692 3129static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3130{
85f455f7
ED		 3131 u32 cpu_based_vm_exec_control;
3132
3133 /* clear pending irq */
3134 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3135 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3136 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3137
a26bf12a 3138 ++vcpu->stat.irq_window_exits;
2714d1d3 3139
c1150d8c
DL		 3140 /*
3141 * If the user space waits to inject interrupts, exit as soon as
3142 * possible
3143 */
8061823a 3144 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3145 vcpu->run->request_interrupt_window &&
8061823a 3146 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3147 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3148 return 0;
3149 }
6aa8b732
AK		 3150 return 1;
3151}
3152
851ba692 3153static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3154{
3155 skip_emulated_instruction(vcpu);
d3bef15f 3156 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3157}
3158
851ba692 3159static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3160{
510043da 3161 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3162 kvm_emulate_hypercall(vcpu);
3163 return 1;
c21415e8
IM		 3164}
3165
851ba692 3166static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3167{
3168 kvm_queue_exception(vcpu, UD_VECTOR);
3169 return 1;
3170}
3171
851ba692 3172static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3173{
f9c617f6 3174 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3175
3176 kvm_mmu_invlpg(vcpu, exit_qualification);
3177 skip_emulated_instruction(vcpu);
3178 return 1;
3179}
3180
851ba692 3181static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3182{
3183 skip_emulated_instruction(vcpu);
3184 /* TODO: Add support for VT-d/pass-through device */
3185 return 1;
3186}
3187
851ba692 3188static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3189{
f9c617f6 3190 unsigned long exit_qualification;
f78e0e2e
SY		 3191 enum emulation_result er;
3192 unsigned long offset;
3193
f9c617f6 3194 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3195 offset = exit_qualification & 0xffful;
3196
851ba692 3197 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3198
3199 if (er != EMULATE_DONE) {
3200 printk(KERN_ERR
3201 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3202 offset);
7f582ab6 3203 return -ENOEXEC;
f78e0e2e
SY		 3204 }
3205 return 1;
3206}
3207
851ba692 3208static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3209{
60637aac 3210 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3211 unsigned long exit_qualification;
3212 u16 tss_selector;
64a7ec06
GN		 3213 int reason, type, idt_v;
3214
3215 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3216 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3217
3218 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3219
3220 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3221 if (reason == TASK_SWITCH_GATE && idt_v) {
3222 switch (type) {
3223 case INTR_TYPE_NMI_INTR:
3224 vcpu->arch.nmi_injected = false;
3225 if (cpu_has_virtual_nmis())
3226 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3227 GUEST_INTR_STATE_NMI);
3228 break;
3229 case INTR_TYPE_EXT_INTR:
66fd3f7f 3230 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3231 kvm_clear_interrupt_queue(vcpu);
3232 break;
3233 case INTR_TYPE_HARD_EXCEPTION:
3234 case INTR_TYPE_SOFT_EXCEPTION:
3235 kvm_clear_exception_queue(vcpu);
3236 break;
3237 default:
3238 break;
3239 }
60637aac 3240 }
37817f29
IE		 3241 tss_selector = exit_qualification;
3242
64a7ec06
GN		 3243 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3244 type != INTR_TYPE_EXT_INTR &&
3245 type != INTR_TYPE_NMI_INTR))
3246 skip_emulated_instruction(vcpu);
3247
42dbaa5a
JK		 3248 if (!kvm_task_switch(vcpu, tss_selector, reason))
3249 return 0;
3250
3251 /* clear all local breakpoint enable flags */
3252 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3253
3254 /*
3255 * TODO: What about debug traps on tss switch?
3256 * Are we supposed to inject them and update dr6?
3257 */
3258
3259 return 1;
37817f29
IE		 3260}
3261
851ba692 3262static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3263{
f9c617f6 3264 unsigned long exit_qualification;
1439442c 3265 gpa_t gpa;
1439442c 3266 int gla_validity;
1439442c 3267
f9c617f6 3268 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3269
3270 if (exit_qualification & (1 << 6)) {
3271 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3272 return -EINVAL;
1439442c
SY		 3273 }
3274
3275 gla_validity = (exit_qualification >> 7) & 0x3;
3276 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3277 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3278 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3279 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3280 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3281 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3282 (long unsigned int)exit_qualification);
851ba692
AK		 3283 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3284 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3285 return 0;
1439442c
SY		 3286 }
3287
3288 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3289 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3290 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3291}
3292
68f89400
MT		 3293static u64 ept_rsvd_mask(u64 spte, int level)
3294{
3295 int i;
3296 u64 mask = 0;
3297
3298 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3299 mask |= (1ULL << i);
3300
3301 if (level > 2)
3302 /* bits 7:3 reserved */
3303 mask |= 0xf8;
3304 else if (level == 2) {
3305 if (spte & (1ULL << 7))
3306 /* 2MB ref, bits 20:12 reserved */
3307 mask |= 0x1ff000;
3308 else
3309 /* bits 6:3 reserved */
3310 mask |= 0x78;
3311 }
3312
3313 return mask;
3314}
3315
3316static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3317 int level)
3318{
3319 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3320
3321 /* 010b (write-only) */
3322 WARN_ON((spte & 0x7) == 0x2);
3323
3324 /* 110b (write/execute) */
3325 WARN_ON((spte & 0x7) == 0x6);
3326
3327 /* 100b (execute-only) and value not supported by logical processor */
3328 if (!cpu_has_vmx_ept_execute_only())
3329 WARN_ON((spte & 0x7) == 0x4);
3330
3331 /* not 000b */
3332 if ((spte & 0x7)) {
3333 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3334
3335 if (rsvd_bits != 0) {
3336 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3337 __func__, rsvd_bits);
3338 WARN_ON(1);
3339 }
3340
3341 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3342 u64 ept_mem_type = (spte & 0x38) >> 3;
3343
3344 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3345 ept_mem_type == 7) {
3346 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3347 __func__, ept_mem_type);
3348 WARN_ON(1);
3349 }
3350 }
3351 }
3352}
3353
851ba692 3354static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3355{
3356 u64 sptes[4];
3357 int nr_sptes, i;
3358 gpa_t gpa;
3359
3360 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3361
3362 printk(KERN_ERR "EPT: Misconfiguration.\n");
3363 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3364
3365 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3366
3367 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3368 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3369
851ba692
AK		 3370 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3371 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3372
3373 return 0;
3374}
3375
851ba692 3376static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3377{
3378 u32 cpu_based_vm_exec_control;
3379
3380 /* clear pending NMI */
3381 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3382 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3383 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3384 ++vcpu->stat.nmi_window_exits;
3385
3386 return 1;
3387}
3388
80ced186 3389static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3390{
8b3079a5
AK		 3391 struct vcpu_vmx *vmx = to_vmx(vcpu);
3392 enum emulation_result err = EMULATE_DONE;
80ced186 3393 int ret = 1;
ea953ef0
MG		 3394
3395 while (!guest_state_valid(vcpu)) {
851ba692 3396 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3397
80ced186
MG		 3398 if (err == EMULATE_DO_MMIO) {
3399 ret = 0;
3400 goto out;
3401 }
1d5a4d9b
GT		 3402
3403 if (err != EMULATE_DONE) {
3404 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3405 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3406 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3407 vcpu->run->internal.ndata = 0;
80ced186
MG		 3408 ret = 0;
3409 goto out;
ea953ef0
MG		 3410 }
3411
3412 if (signal_pending(current))
80ced186 3413 goto out;
ea953ef0
MG		 3414 if (need_resched())
3415 schedule();
3416 }
3417
80ced186
MG		 3418 vmx->emulation_required = 0;
3419out:
3420 return ret;
ea953ef0
MG		 3421}
3422
4b8d54f9
ZE		 3423/*
3424 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3425 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3426 */
9fb41ba8 3427static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3428{
3429 skip_emulated_instruction(vcpu);
3430 kvm_vcpu_on_spin(vcpu);
3431
3432 return 1;
3433}
3434
59708670
SY		 3435static int handle_invalid_op(struct kvm_vcpu *vcpu)
3436{
3437 kvm_queue_exception(vcpu, UD_VECTOR);
3438 return 1;
3439}
3440
6aa8b732
AK		 3441/*
3442 * The exit handlers return 1 if the exit was handled fully and guest execution
3443 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3444 * to be done to userspace and return 0.
3445 */
851ba692 3446static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3447 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3448 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3449 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3450 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3451 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3452 [EXIT_REASON_CR_ACCESS] = handle_cr,
3453 [EXIT_REASON_DR_ACCESS] = handle_dr,
3454 [EXIT_REASON_CPUID] = handle_cpuid,
3455 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3456 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3457 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3458 [EXIT_REASON_HLT] = handle_halt,
a7052897 3459 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3460 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3461 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3462 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3463 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3464 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3465 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3466 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3467 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3468 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3469 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3470 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3471 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3472 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3473 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3474 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3475 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3476 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3477 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3478 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3479 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3480};
3481
3482static const int kvm_vmx_max_exit_handlers =
50a3485c 3483 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3484
3485/*
3486 * The guest has exited. See if we can fix it or if we need userspace
3487 * assistance.
3488 */
851ba692 3489static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3490{
29bd8a78 3491 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3492 u32 exit_reason = vmx->exit_reason;
1155f76a 3493 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3494
229456fc 3495 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3496
80ced186
MG		 3497 /* If guest state is invalid, start emulating */
3498 if (vmx->emulation_required && emulate_invalid_guest_state)
3499 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3500
1439442c
SY		 3501 /* Access CR3 don't cause VMExit in paging mode, so we need
3502 * to sync with guest real CR3. */
6de4f3ad 3503 if (enable_ept && is_paging(vcpu))
1439442c 3504 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3505
29bd8a78 3506 if (unlikely(vmx->fail)) {
851ba692
AK		 3507 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3508 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3509 = vmcs_read32(VM_INSTRUCTION_ERROR);
3510 return 0;
3511 }
6aa8b732 3512
d77c26fc 3513 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3514 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3515 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3516 exit_reason != EXIT_REASON_TASK_SWITCH))
3517 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3518 "(0x%x) and exit reason is 0x%x\n",
3519 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3520
3521 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3522 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3523 vmx->soft_vnmi_blocked = 0;
3b86cd99 3524 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3525 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3526 /*
3527 * This CPU don't support us in finding the end of an
3528 * NMI-blocked window if the guest runs with IRQs
3529 * disabled. So we pull the trigger after 1 s of
3530 * futile waiting, but inform the user about this.
3531 */
3532 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3533 "state on VCPU %d after 1 s timeout\n",
3534 __func__, vcpu->vcpu_id);
3535 vmx->soft_vnmi_blocked = 0;
3b86cd99 3536 }
3b86cd99
JK		 3537 }
3538
6aa8b732
AK		 3539 if (exit_reason < kvm_vmx_max_exit_handlers
3540 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3541 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3542 else {
851ba692
AK		 3543 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3544 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3545 }
3546 return 0;
3547}
3548
95ba8273 3549static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3550{
95ba8273 3551 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3552 vmcs_write32(TPR_THRESHOLD, 0);
3553 return;
3554 }
3555
95ba8273 3556 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3557}
3558
cf393f75
AK		 3559static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3560{
3561 u32 exit_intr_info;
7b4a25cb 3562 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3563 bool unblock_nmi;
3564 u8 vector;
668f612f
AK		 3565 int type;
3566 bool idtv_info_valid;
cf393f75
AK		 3567
3568 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3569
a0861c02
AK		 3570 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3571
3572 /* Handle machine checks before interrupts are enabled */
3573 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3574 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3575 && is_machine_check(exit_intr_info)))
3576 kvm_machine_check();
3577
20f65983
GN		 3578 /* We need to handle NMIs before interrupts are enabled */
3579 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3580 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3581 asm("int $2");
20f65983
GN		 3582
3583 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3584
cf393f75
AK		 3585 if (cpu_has_virtual_nmis()) {
3586 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3587 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3588 /*
7b4a25cb 3589 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3590 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3591 * a guest IRET fault.
7b4a25cb
GN		 3592 * SDM 3: 23.2.2 (September 2008)
3593 * Bit 12 is undefined in any of the following cases:
3594 * If the VM exit sets the valid bit in the IDT-vectoring
3595 * information field.
3596 * If the VM exit is due to a double fault.
cf393f75 3597 */
7b4a25cb
GN		 3598 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3599 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3600 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3601 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3602 } else if (unlikely(vmx->soft_vnmi_blocked))
3603 vmx->vnmi_blocked_time +=
3604 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3605
37b96e98
GN		 3606 vmx->vcpu.arch.nmi_injected = false;
3607 kvm_clear_exception_queue(&vmx->vcpu);
3608 kvm_clear_interrupt_queue(&vmx->vcpu);
3609
3610 if (!idtv_info_valid)
3611 return;
3612
668f612f
AK		 3613 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3614 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3615
64a7ec06 3616 switch (type) {
37b96e98
GN		 3617 case INTR_TYPE_NMI_INTR:
3618 vmx->vcpu.arch.nmi_injected = true;
668f612f 3619 /*
7b4a25cb 3620 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3621 * Clear bit "block by NMI" before VM entry if a NMI
3622 * delivery faulted.
668f612f 3623 */
37b96e98
GN		 3624 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3625 GUEST_INTR_STATE_NMI);
3626 break;
37b96e98 3627 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3628 vmx->vcpu.arch.event_exit_inst_len =
3629 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3630 /* fall through */
3631 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3632 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3633 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3634 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3635 } else
3636 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3637 break;
66fd3f7f
GN		 3638 case INTR_TYPE_SOFT_INTR:
3639 vmx->vcpu.arch.event_exit_inst_len =
3640 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3641 /* fall through */
37b96e98 3642 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3643 kvm_queue_interrupt(&vmx->vcpu, vector,
3644 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3645 break;
3646 default:
3647 break;
f7d9238f 3648 }
cf393f75
AK		 3649}
3650
9c8cba37
AK		 3651/*
3652 * Failure to inject an interrupt should give us the information
3653 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3654 * when fetching the interrupt redirection bitmap in the real-mode
3655 * tss, this doesn't happen. So we do it ourselves.
3656 */
3657static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3658{
3659 vmx->rmode.irq.pending = 0;
5fdbf976 3660 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3661 return;
5fdbf976 3662 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3663 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3664 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3665 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3666 return;
3667 }
3668 vmx->idt_vectoring_info =
3669 VECTORING_INFO_VALID_MASK
3670 | INTR_TYPE_EXT_INTR
3671 | vmx->rmode.irq.vector;
3672}
3673
c801949d
AK		 3674#ifdef CONFIG_X86_64
3675#define R "r"
3676#define Q "q"
3677#else
3678#define R "e"
3679#define Q "l"
3680#endif
3681
851ba692 3682static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3683{
a2fa3e9f 3684 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3685
3b86cd99
JK		 3686 /* Record the guest's net vcpu time for enforced NMI injections. */
3687 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3688 vmx->entry_time = ktime_get();
3689
80ced186
MG		 3690 /* Don't enter VMX if guest state is invalid, let the exit handler
3691 start emulation until we arrive back to a valid state */
3692 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3693 return;
a89a8fb9 3694
5fdbf976
MT		 3695 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3696 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3697 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3698 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3699
787ff736
GN		 3700 /* When single-stepping over STI and MOV SS, we must clear the
3701 * corresponding interruptibility bits in the guest state. Otherwise
3702 * vmentry fails as it then expects bit 14 (BS) in pending debug
3703 * exceptions being set, but that's not correct for the guest debugging
3704 * case. */
3705 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3706 vmx_set_interrupt_shadow(vcpu, 0);
3707
e6adf283
AK		 3708 /*
3709 * Loading guest fpu may have cleared host cr0.ts
3710 */
3711 vmcs_writel(HOST_CR0, read_cr0());
3712
e8a48342
AK		 3713 if (vcpu->arch.switch_db_regs)
3714 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3715
d77c26fc 3716 asm(
6aa8b732 3717 /* Store host registers */
c801949d
AK		 3718 "push %%"R"dx; push %%"R"bp;"
3719 "push %%"R"cx \n\t"
313dbd49
AK		 3720 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3721 "je 1f \n\t"
3722 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3723 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3724 "1: \n\t"
d3edefc0
AK		 3725 /* Reload cr2 if changed */
3726 "mov %c[cr2](%0), %%"R"ax \n\t"
3727 "mov %%cr2, %%"R"dx \n\t"
3728 "cmp %%"R"ax, %%"R"dx \n\t"
3729 "je 2f \n\t"
3730 "mov %%"R"ax, %%cr2 \n\t"
3731 "2: \n\t"
6aa8b732 3732 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3733 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3734 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3735 "mov %c[rax](%0), %%"R"ax \n\t"
3736 "mov %c[rbx](%0), %%"R"bx \n\t"
3737 "mov %c[rdx](%0), %%"R"dx \n\t"
3738 "mov %c[rsi](%0), %%"R"si \n\t"
3739 "mov %c[rdi](%0), %%"R"di \n\t"
3740 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3741#ifdef CONFIG_X86_64
e08aa78a
AK		 3742 "mov %c[r8](%0), %%r8 \n\t"
3743 "mov %c[r9](%0), %%r9 \n\t"
3744 "mov %c[r10](%0), %%r10 \n\t"
3745 "mov %c[r11](%0), %%r11 \n\t"
3746 "mov %c[r12](%0), %%r12 \n\t"
3747 "mov %c[r13](%0), %%r13 \n\t"
3748 "mov %c[r14](%0), %%r14 \n\t"
3749 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3750#endif
c801949d
AK		 3751 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3752
6aa8b732 3753 /* Enter guest mode */
cd2276a7 3754 "jne .Llaunched \n\t"
4ecac3fd 3755 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3756 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3757 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3758 ".Lkvm_vmx_return: "
6aa8b732 3759 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3760 "xchg %0, (%%"R"sp) \n\t"
3761 "mov %%"R"ax, %c[rax](%0) \n\t"
3762 "mov %%"R"bx, %c[rbx](%0) \n\t"
3763 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3764 "mov %%"R"dx, %c[rdx](%0) \n\t"
3765 "mov %%"R"si, %c[rsi](%0) \n\t"
3766 "mov %%"R"di, %c[rdi](%0) \n\t"
3767 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3768#ifdef CONFIG_X86_64
e08aa78a
AK		 3769 "mov %%r8, %c[r8](%0) \n\t"
3770 "mov %%r9, %c[r9](%0) \n\t"
3771 "mov %%r10, %c[r10](%0) \n\t"
3772 "mov %%r11, %c[r11](%0) \n\t"
3773 "mov %%r12, %c[r12](%0) \n\t"
3774 "mov %%r13, %c[r13](%0) \n\t"
3775 "mov %%r14, %c[r14](%0) \n\t"
3776 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3777#endif
c801949d
AK		 3778 "mov %%cr2, %%"R"ax \n\t"
3779 "mov %%"R"ax, %c[cr2](%0) \n\t"
3780
3781 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3782 "setbe %c[fail](%0) \n\t"
3783 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3784 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3785 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3786 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3787 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3788 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3789 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3790 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3791 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3792 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3793 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3794#ifdef CONFIG_X86_64
ad312c7c
ZX		 3795 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3796 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3797 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3798 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3799 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3800 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3801 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3802 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3803#endif
ad312c7c 3804 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3805 : "cc", "memory"
c801949d 3806 , R"bx", R"di", R"si"
c2036300 3807#ifdef CONFIG_X86_64
c2036300
LV		 3808 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3809#endif
3810 );
6aa8b732 3811
6de4f3ad
AK		 3812 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3813 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3814 vcpu->arch.regs_dirty = 0;
3815
e8a48342
AK		 3816 if (vcpu->arch.switch_db_regs)
3817 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3818
1155f76a 3819 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3820 if (vmx->rmode.irq.pending)
3821 fixup_rmode_irq(vmx);
1155f76a 3822
d77c26fc 3823 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3824 vmx->launched = 1;
1b6269db 3825
cf393f75 3826 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3827}
3828
c801949d
AK		 3829#undef R
3830#undef Q
3831
6aa8b732
AK		 3832static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3833{
a2fa3e9f
GH		 3834 struct vcpu_vmx *vmx = to_vmx(vcpu);
3835
3836 if (vmx->vmcs) {
543e4243 3837 vcpu_clear(vmx);
a2fa3e9f
GH		 3838 free_vmcs(vmx->vmcs);
3839 vmx->vmcs = NULL;
6aa8b732
AK		 3840 }
3841}
3842
3843static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3844{
fb3f0f51
RR		 3845 struct vcpu_vmx *vmx = to_vmx(vcpu);
3846
2384d2b3
SY		 3847 spin_lock(&vmx_vpid_lock);
3848 if (vmx->vpid != 0)
3849 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3850 spin_unlock(&vmx_vpid_lock);
6aa8b732 3851 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3852 kfree(vmx->guest_msrs);
3853 kvm_vcpu_uninit(vcpu);
a4770347 3854 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3855}
3856
fb3f0f51 3857static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3858{
fb3f0f51 3859 int err;
c16f862d 3860 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3861 int cpu;
6aa8b732 3862
a2fa3e9f 3863 if (!vmx)
fb3f0f51
RR		 3864 return ERR_PTR(-ENOMEM);
3865
2384d2b3
SY		 3866 allocate_vpid(vmx);
3867
fb3f0f51
RR		 3868 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3869 if (err)
3870 goto free_vcpu;
965b58a5 3871
a2fa3e9f 3872 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3873 if (!vmx->guest_msrs) {
3874 err = -ENOMEM;
3875 goto uninit_vcpu;
3876 }
965b58a5 3877
a2fa3e9f
GH		 3878 vmx->vmcs = alloc_vmcs();
3879 if (!vmx->vmcs)
fb3f0f51 3880 goto free_msrs;
a2fa3e9f
GH		 3881
3882 vmcs_clear(vmx->vmcs);
3883
15ad7146
AK		 3884 cpu = get_cpu();
3885 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3886 err = vmx_vcpu_setup(vmx);
fb3f0f51 3887 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3888 put_cpu();
fb3f0f51
RR		 3889 if (err)
3890 goto free_vmcs;
5e4a0b3c
MT		 3891 if (vm_need_virtualize_apic_accesses(kvm))
3892 if (alloc_apic_access_page(kvm) != 0)
3893 goto free_vmcs;
fb3f0f51 3894
b927a3ce
SY		 3895 if (enable_ept) {
3896 if (!kvm->arch.ept_identity_map_addr)
3897 kvm->arch.ept_identity_map_addr =
3898 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3899 if (alloc_identity_pagetable(kvm) != 0)
3900 goto free_vmcs;
b927a3ce 3901 }
b7ebfb05 3902
fb3f0f51
RR		 3903 return &vmx->vcpu;
3904
3905free_vmcs:
3906 free_vmcs(vmx->vmcs);
3907free_msrs:
fb3f0f51
RR		 3908 kfree(vmx->guest_msrs);
3909uninit_vcpu:
3910 kvm_vcpu_uninit(&vmx->vcpu);
3911free_vcpu:
a4770347 3912 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3913 return ERR_PTR(err);
6aa8b732
AK		 3914}
3915
002c7f7c
YS		 3916static void __init vmx_check_processor_compat(void *rtn)
3917{
3918 struct vmcs_config vmcs_conf;
3919
3920 *(int *)rtn = 0;
3921 if (setup_vmcs_config(&vmcs_conf) < 0)
3922 *(int *)rtn = -EIO;
3923 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3924 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3925 smp_processor_id());
3926 *(int *)rtn = -EIO;
3927 }
3928}
3929
67253af5
SY		 3930static int get_ept_level(void)
3931{
3932 return VMX_EPT_DEFAULT_GAW + 1;
3933}
3934
4b12f0de 3935static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3936{
4b12f0de
SY		 3937 u64 ret;
3938
522c68c4
SY		 3939 /* For VT-d and EPT combination
3940 * 1. MMIO: always map as UC
3941 * 2. EPT with VT-d:
3942 * a. VT-d without snooping control feature: can't guarantee the
3943 * result, try to trust guest.
3944 * b. VT-d with snooping control feature: snooping control feature of
3945 * VT-d engine can guarantee the cache correctness. Just set it
3946 * to WB to keep consistent with host. So the same as item 3.
3947 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3948 * consistent with host MTRR
3949 */
4b12f0de
SY		 3950 if (is_mmio)
3951 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3952 else if (vcpu->kvm->arch.iommu_domain &&
3953 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3954 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3955 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3956 else
522c68c4
SY		 3957 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3958 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3959
3960 return ret;
64d4d521
SY		 3961}
3962
229456fc
MT		 3963static const struct trace_print_flags vmx_exit_reasons_str[] = {
3964 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3965 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3966 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3967 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3968 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3969 { EXIT_REASON_CR_ACCESS, "cr_access" },
3970 { EXIT_REASON_DR_ACCESS, "dr_access" },
3971 { EXIT_REASON_CPUID, "cpuid" },
3972 { EXIT_REASON_MSR_READ, "rdmsr" },
3973 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3974 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3975 { EXIT_REASON_HLT, "halt" },
3976 { EXIT_REASON_INVLPG, "invlpg" },
3977 { EXIT_REASON_VMCALL, "hypercall" },
3978 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3979 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3980 { EXIT_REASON_WBINVD, "wbinvd" },
3981 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3982 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3983 { -1, NULL }
3984};
3985
344f414f
JR		 3986static bool vmx_gb_page_enable(void)
3987{
3988 return false;
3989}
3990
cbdd1bea 3991static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3992 .cpu_has_kvm_support = cpu_has_kvm_support,
3993 .disabled_by_bios = vmx_disabled_by_bios,
3994 .hardware_setup = hardware_setup,
3995 .hardware_unsetup = hardware_unsetup,
002c7f7c 3996 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 3997 .hardware_enable = hardware_enable,
3998 .hardware_disable = hardware_disable,
04547156 3999 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4000
4001 .vcpu_create = vmx_create_vcpu,
4002 .vcpu_free = vmx_free_vcpu,
04d2cc77 4003 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4004
04d2cc77 4005 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4006 .vcpu_load = vmx_vcpu_load,
4007 .vcpu_put = vmx_vcpu_put,
4008
4009 .set_guest_debug = set_guest_debug,
4010 .get_msr = vmx_get_msr,
4011 .set_msr = vmx_set_msr,
4012 .get_segment_base = vmx_get_segment_base,
4013 .get_segment = vmx_get_segment,
4014 .set_segment = vmx_set_segment,
2e4d2653 4015 .get_cpl = vmx_get_cpl,
6aa8b732 4016 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 4017 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4018 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4019 .set_cr3 = vmx_set_cr3,
4020 .set_cr4 = vmx_set_cr4,
6aa8b732 4021 .set_efer = vmx_set_efer,
6aa8b732
AK		 4022 .get_idt = vmx_get_idt,
4023 .set_idt = vmx_set_idt,
4024 .get_gdt = vmx_get_gdt,
4025 .set_gdt = vmx_set_gdt,
5fdbf976 4026 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4027 .get_rflags = vmx_get_rflags,
4028 .set_rflags = vmx_set_rflags,
4029
4030 .tlb_flush = vmx_flush_tlb,
6aa8b732 4031
6aa8b732 4032 .run = vmx_vcpu_run,
6062d012 4033 .handle_exit = vmx_handle_exit,
6aa8b732 4034 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4035 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4036 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4037 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4038 .set_irq = vmx_inject_irq,
95ba8273 4039 .set_nmi = vmx_inject_nmi,
298101da 4040 .queue_exception = vmx_queue_exception,
78646121 4041 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4042 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4043 .get_nmi_mask = vmx_get_nmi_mask,
4044 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4045 .enable_nmi_window = enable_nmi_window,
4046 .enable_irq_window = enable_irq_window,
4047 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4048
cbc94022 4049 .set_tss_addr = vmx_set_tss_addr,
67253af5 4050 .get_tdp_level = get_ept_level,
4b12f0de 4051 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4052
4053 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 4054 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 4055};
4056
4057static int __init vmx_init(void)
4058{
26bb0981
AK		 4059 int r, i;
4060
4061 rdmsrl_safe(MSR_EFER, &host_efer);
4062
4063 for (i = 0; i < NR_VMX_MSR; ++i)
4064 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4065
3e7c73e9 4066 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4067 if (!vmx_io_bitmap_a)
4068 return -ENOMEM;
4069
3e7c73e9 4070 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4071 if (!vmx_io_bitmap_b) {
4072 r = -ENOMEM;
4073 goto out;
4074 }
4075
5897297b
AK		 4076 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4077 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4078 r = -ENOMEM;
4079 goto out1;
4080 }
4081
5897297b
AK		 4082 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4083 if (!vmx_msr_bitmap_longmode) {
4084 r = -ENOMEM;
4085 goto out2;
4086 }
4087
fdef3ad1
HQ		 4088 /*
4089 * Allow direct access to the PC debug port (it is often used for I/O
4090 * delays, but the vmexits simply slow things down).
4091 */
3e7c73e9
AK		 4092 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4093 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4094
3e7c73e9 4095 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4096
5897297b
AK		 4097 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4098 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4099
2384d2b3
SY		 4100 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4101
cb498ea2 4102 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4103 if (r)
5897297b 4104 goto out3;
25c5f225 4105
5897297b
AK		 4106 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4107 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4108 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4109 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4110 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4111 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4112
089d034e 4113 if (enable_ept) {
1439442c 4114 bypass_guest_pf = 0;
5fdbcb9d 4115 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4116 VMX_EPT_WRITABLE_MASK);
534e38b4 4117 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4118 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4119 kvm_enable_tdp();
4120 } else
4121 kvm_disable_tdp();
1439442c 4122
c7addb90
AK		 4123 if (bypass_guest_pf)
4124 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4125
fdef3ad1
HQ		 4126 return 0;
4127
5897297b
AK		 4128out3:
4129 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4130out2:
5897297b 4131 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4132out1:
3e7c73e9 4133 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4134out:
3e7c73e9 4135 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4136 return r;
6aa8b732
AK		 4137}
4138
4139static void __exit vmx_exit(void)
4140{
5897297b
AK		 4141 free_page((unsigned long)vmx_msr_bitmap_legacy);
4142 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4143 free_page((unsigned long)vmx_io_bitmap_b);
4144 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4145
cb498ea2 4146 kvm_exit();
6aa8b732
AK		 4147}
4148
4149module_init(vmx_init)
4150module_exit(vmx_exit)
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