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KVM: Replace reads of vcpu->arch.cr3 by an accessor
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103#define KVM_VMX_DEFAULT_PLE_GAP 41
104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
51aa01d1 131 u32 exit_intr_info;
1155f76a 132 u32 idt_vectoring_info;
26bb0981 133 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 134 int nmsrs;
135 int save_nmsrs;
a2fa3e9f 136#ifdef CONFIG_X86_64
44ea2b17
AK		 137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 139#endif
140 struct vmcs *vmcs;
61d2ef2c
AK		 141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
a2fa3e9f
GH		 146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
d77c26fc 151 } host_state;
9c8cba37 152 struct {
7ffd92c5 153 int vm86_active;
78ac8b47 154 ulong save_rflags;
7ffd92c5
AK		 155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
9c8cba37 161 } rmode;
2384d2b3 162 int vpid;
04fa4d32 163 bool emulation_required;
3b86cd99
JK		 164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
a0861c02 169 u32 exit_reason;
4e47c7a6
SY		 170
171 bool rdtscp_enabled;
a2fa3e9f
GH		 172};
173
174static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175{
fb3f0f51 176 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 177}
178
b7ebfb05 179static int init_rmode(struct kvm *kvm);
4e1096d2 180static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 181static void kvm_cpu_vmxon(u64 addr);
182static void kvm_cpu_vmxoff(void);
75880a01 183
6aa8b732
AK		 184static DEFINE_PER_CPU(struct vmcs *, vmxarea);
185static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 186static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 187static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 188
3e7c73e9
AK		 189static unsigned long *vmx_io_bitmap_a;
190static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 191static unsigned long *vmx_msr_bitmap_legacy;
192static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 193
110312c8
AK		 194static bool cpu_has_load_ia32_efer;
195
2384d2b3
SY		 196static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
197static DEFINE_SPINLOCK(vmx_vpid_lock);
198
1c3d14fe 199static struct vmcs_config {
6aa8b732
AK		 200 int size;
201 int order;
202 u32 revision_id;
1c3d14fe
YS		 203 u32 pin_based_exec_ctrl;
204 u32 cpu_based_exec_ctrl;
f78e0e2e 205 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 206 u32 vmexit_ctrl;
207 u32 vmentry_ctrl;
208} vmcs_config;
6aa8b732 209
efff9e53 210static struct vmx_capability {
d56f546d
SY		 211 u32 ept;
212 u32 vpid;
213} vmx_capability;
214
6aa8b732
AK		 215#define VMX_SEGMENT_FIELD(seg) \
216 [VCPU_SREG_##seg] = { \
217 .selector = GUEST_##seg##_SELECTOR, \
218 .base = GUEST_##seg##_BASE, \
219 .limit = GUEST_##seg##_LIMIT, \
220 .ar_bytes = GUEST_##seg##_AR_BYTES, \
221 }
222
223static struct kvm_vmx_segment_field {
224 unsigned selector;
225 unsigned base;
226 unsigned limit;
227 unsigned ar_bytes;
228} kvm_vmx_segment_fields[] = {
229 VMX_SEGMENT_FIELD(CS),
230 VMX_SEGMENT_FIELD(DS),
231 VMX_SEGMENT_FIELD(ES),
232 VMX_SEGMENT_FIELD(FS),
233 VMX_SEGMENT_FIELD(GS),
234 VMX_SEGMENT_FIELD(SS),
235 VMX_SEGMENT_FIELD(TR),
236 VMX_SEGMENT_FIELD(LDTR),
237};
238
26bb0981
AK		 239static u64 host_efer;
240
6de4f3ad
AK		 241static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
242
4d56c8a7 243/*
8c06585d 244 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 245 * away by decrementing the array size.
246 */
6aa8b732 247static const u32 vmx_msr_index[] = {
05b3e0c2 248#ifdef CONFIG_X86_64
44ea2b17 249 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 250#endif
8c06585d 251 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 252};
9d8f549d 253#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 254
31299944 255static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 256{
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
258 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 259 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 260}
261
31299944 262static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 263{
264 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
265 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 266 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 267}
268
31299944 269static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 270{
271 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
272 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 273 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 274}
275
31299944 276static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 277{
278 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
279 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
280}
281
31299944 282static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 283{
284 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
285 INTR_INFO_VALID_MASK)) ==
286 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
287}
288
31299944 289static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 290{
04547156 291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 292}
293
31299944 294static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 295{
04547156 296 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 297}
298
31299944 299static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 300{
04547156 301 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 302}
303
31299944 304static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 305{
04547156
SY		 306 return vmcs_config.cpu_based_exec_ctrl &
307 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 308}
309
774ead3a 310static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 311{
04547156
SY		 312 return vmcs_config.cpu_based_2nd_exec_ctrl &
313 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
314}
315
316static inline bool cpu_has_vmx_flexpriority(void)
317{
318 return cpu_has_vmx_tpr_shadow() &&
319 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 320}
321
e799794e
MT		 322static inline bool cpu_has_vmx_ept_execute_only(void)
323{
31299944 324 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 325}
326
327static inline bool cpu_has_vmx_eptp_uncacheable(void)
328{
31299944 329 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 330}
331
332static inline bool cpu_has_vmx_eptp_writeback(void)
333{
31299944 334 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 335}
336
337static inline bool cpu_has_vmx_ept_2m_page(void)
338{
31299944 339 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 340}
341
878403b7
SY		 342static inline bool cpu_has_vmx_ept_1g_page(void)
343{
31299944 344 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 345}
346
4bc9b982
SY		 347static inline bool cpu_has_vmx_ept_4levels(void)
348{
349 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
350}
351
31299944 352static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 353{
31299944 354 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 355}
356
31299944 357static inline bool cpu_has_vmx_invept_context(void)
d56f546d 358{
31299944 359 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 360}
361
31299944 362static inline bool cpu_has_vmx_invept_global(void)
d56f546d 363{
31299944 364 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 365}
366
518c8aee
GJ		 367static inline bool cpu_has_vmx_invvpid_single(void)
368{
369 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
370}
371
b9d762fa
GJ		 372static inline bool cpu_has_vmx_invvpid_global(void)
373{
374 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
375}
376
31299944 377static inline bool cpu_has_vmx_ept(void)
d56f546d 378{
04547156
SY		 379 return vmcs_config.cpu_based_2nd_exec_ctrl &
380 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 381}
382
31299944 383static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 384{
385 return vmcs_config.cpu_based_2nd_exec_ctrl &
386 SECONDARY_EXEC_UNRESTRICTED_GUEST;
387}
388
31299944 389static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 390{
391 return vmcs_config.cpu_based_2nd_exec_ctrl &
392 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
393}
394
31299944 395static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 396{
6d3e435e 397 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 398}
399
31299944 400static inline bool cpu_has_vmx_vpid(void)
2384d2b3 401{
04547156
SY		 402 return vmcs_config.cpu_based_2nd_exec_ctrl &
403 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 404}
405
31299944 406static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 407{
408 return vmcs_config.cpu_based_2nd_exec_ctrl &
409 SECONDARY_EXEC_RDTSCP;
410}
411
31299944 412static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 413{
414 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
415}
416
f5f48ee1
SY		 417static inline bool cpu_has_vmx_wbinvd_exit(void)
418{
419 return vmcs_config.cpu_based_2nd_exec_ctrl &
420 SECONDARY_EXEC_WBINVD_EXITING;
421}
422
04547156
SY		 423static inline bool report_flexpriority(void)
424{
425 return flexpriority_enabled;
426}
427
8b9cf98c 428static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 429{
430 int i;
431
a2fa3e9f 432 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 433 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 434 return i;
435 return -1;
436}
437
2384d2b3
SY		 438static inline void __invvpid(int ext, u16 vpid, gva_t gva)
439{
440 struct {
441 u64 vpid : 16;
442 u64 rsvd : 48;
443 u64 gva;
444 } operand = { vpid, 0, gva };
445
4ecac3fd 446 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 447 /* CF==1 or ZF==1 --> rc = -1 */
448 "; ja 1f ; ud2 ; 1:"
449 : : "a"(&operand), "c"(ext) : "cc", "memory");
450}
451
1439442c
SY		 452static inline void __invept(int ext, u64 eptp, gpa_t gpa)
453{
454 struct {
455 u64 eptp, gpa;
456 } operand = {eptp, gpa};
457
4ecac3fd 458 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 459 /* CF==1 or ZF==1 --> rc = -1 */
460 "; ja 1f ; ud2 ; 1:\n"
461 : : "a" (&operand), "c" (ext) : "cc", "memory");
462}
463
26bb0981 464static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 465{
466 int i;
467
8b9cf98c 468 i = __find_msr_index(vmx, msr);
a75beee6 469 if (i >= 0)
a2fa3e9f 470 return &vmx->guest_msrs[i];
8b6d44c7 471 return NULL;
7725f0ba
AK		 472}
473
6aa8b732
AK		 474static void vmcs_clear(struct vmcs *vmcs)
475{
476 u64 phys_addr = __pa(vmcs);
477 u8 error;
478
4ecac3fd 479 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 480 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 481 : "cc", "memory");
482 if (error)
483 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
484 vmcs, phys_addr);
485}
486
7725b894
DX		 487static void vmcs_load(struct vmcs *vmcs)
488{
489 u64 phys_addr = __pa(vmcs);
490 u8 error;
491
492 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 493 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 494 : "cc", "memory");
495 if (error)
496 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
497 vmcs, phys_addr);
498}
499
6aa8b732
AK		 500static void __vcpu_clear(void *arg)
501{
8b9cf98c 502 struct vcpu_vmx *vmx = arg;
d3b2c338 503 int cpu = raw_smp_processor_id();
6aa8b732 504
8b9cf98c 505 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 506 vmcs_clear(vmx->vmcs);
507 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 508 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 509 list_del(&vmx->local_vcpus_link);
510 vmx->vcpu.cpu = -1;
511 vmx->launched = 0;
6aa8b732
AK		 512}
513
8b9cf98c 514static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 515{
eae5ecb5
AK		 516 if (vmx->vcpu.cpu == -1)
517 return;
8691e5a8 518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 519}
520
1760dd49 521static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 522{
523 if (vmx->vpid == 0)
524 return;
525
518c8aee
GJ		 526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 528}
529
b9d762fa
GJ		 530static inline void vpid_sync_vcpu_global(void)
531{
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
534}
535
536static inline void vpid_sync_context(struct vcpu_vmx *vmx)
537{
538 if (cpu_has_vmx_invvpid_single())
1760dd49 539 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 540 else
541 vpid_sync_vcpu_global();
542}
543
1439442c
SY		 544static inline void ept_sync_global(void)
545{
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
548}
549
550static inline void ept_sync_context(u64 eptp)
551{
089d034e 552 if (enable_ept) {
1439442c
SY		 553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 else
556 ept_sync_global();
557 }
558}
559
560static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
561{
089d034e 562 if (enable_ept) {
1439442c
SY		 563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
565 eptp, gpa);
566 else
567 ept_sync_context(eptp);
568 }
569}
570
6aa8b732
AK		 571static unsigned long vmcs_readl(unsigned long field)
572{
a295673a 573 unsigned long value = 0;
6aa8b732 574
4ecac3fd 575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 576 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 577 return value;
578}
579
580static u16 vmcs_read16(unsigned long field)
581{
582 return vmcs_readl(field);
583}
584
585static u32 vmcs_read32(unsigned long field)
586{
587 return vmcs_readl(field);
588}
589
590static u64 vmcs_read64(unsigned long field)
591{
05b3e0c2 592#ifdef CONFIG_X86_64
6aa8b732
AK		 593 return vmcs_readl(field);
594#else
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
596#endif
597}
598
e52de1b8
AK		 599static noinline void vmwrite_error(unsigned long field, unsigned long value)
600{
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
603 dump_stack();
604}
605
6aa8b732
AK		 606static void vmcs_writel(unsigned long field, unsigned long value)
607{
608 u8 error;
609
4ecac3fd 610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 611 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 612 if (unlikely(error))
613 vmwrite_error(field, value);
6aa8b732
AK		 614}
615
616static void vmcs_write16(unsigned long field, u16 value)
617{
618 vmcs_writel(field, value);
619}
620
621static void vmcs_write32(unsigned long field, u32 value)
622{
623 vmcs_writel(field, value);
624}
625
626static void vmcs_write64(unsigned long field, u64 value)
627{
6aa8b732 628 vmcs_writel(field, value);
7682f2d0 629#ifndef CONFIG_X86_64
6aa8b732
AK		 630 asm volatile ("");
631 vmcs_writel(field+1, value >> 32);
632#endif
633}
634
2ab455cc
AL		 635static void vmcs_clear_bits(unsigned long field, u32 mask)
636{
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
638}
639
640static void vmcs_set_bits(unsigned long field, u32 mask)
641{
642 vmcs_writel(field, vmcs_readl(field) | mask);
643}
644
abd3f2d6
AK		 645static void update_exception_bitmap(struct kvm_vcpu *vcpu)
646{
647 u32 eb;
648
fd7373cc
JK		 649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
7ffd92c5 655 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 656 eb = ~0;
089d034e 657 if (enable_ept)
1439442c 658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 661 vmcs_write32(EXCEPTION_BITMAP, eb);
662}
663
61d2ef2c
AK		 664static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
665{
666 unsigned i;
667 struct msr_autoload *m = &vmx->msr_autoload;
668
110312c8
AK		 669 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
670 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
671 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
672 return;
673 }
674
61d2ef2c
AK		 675 for (i = 0; i < m->nr; ++i)
676 if (m->guest[i].index == msr)
677 break;
678
679 if (i == m->nr)
680 return;
681 --m->nr;
682 m->guest[i] = m->guest[m->nr];
683 m->host[i] = m->host[m->nr];
684 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
686}
687
688static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
689 u64 guest_val, u64 host_val)
690{
691 unsigned i;
692 struct msr_autoload *m = &vmx->msr_autoload;
693
110312c8
AK		 694 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
695 vmcs_write64(GUEST_IA32_EFER, guest_val);
696 vmcs_write64(HOST_IA32_EFER, host_val);
697 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
698 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
699 return;
700 }
701
61d2ef2c
AK		 702 for (i = 0; i < m->nr; ++i)
703 if (m->guest[i].index == msr)
704 break;
705
706 if (i == m->nr) {
707 ++m->nr;
708 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
709 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
710 }
711
712 m->guest[i].index = msr;
713 m->guest[i].value = guest_val;
714 m->host[i].index = msr;
715 m->host[i].value = host_val;
716}
717
33ed6329
AK		 718static void reload_tss(void)
719{
33ed6329
AK		 720 /*
721 * VT restores TR but not its size. Useless.
722 */
d359192f 723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 724 struct desc_struct *descs;
33ed6329 725
d359192f 726 descs = (void *)gdt->address;
33ed6329
AK		 727 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
728 load_TR_desc();
33ed6329
AK		 729}
730
92c0d900 731static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 732{
3a34a881 733 u64 guest_efer;
51c6cf66
AK		 734 u64 ignore_bits;
735
f6801dff 736 guest_efer = vmx->vcpu.arch.efer;
3a34a881 737
51c6cf66
AK		 738 /*
739 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
740 * outside long mode
741 */
742 ignore_bits = EFER_NX | EFER_SCE;
743#ifdef CONFIG_X86_64
744 ignore_bits |= EFER_LMA | EFER_LME;
745 /* SCE is meaningful only in long mode on Intel */
746 if (guest_efer & EFER_LMA)
747 ignore_bits &= ~(u64)EFER_SCE;
748#endif
51c6cf66
AK		 749 guest_efer &= ~ignore_bits;
750 guest_efer |= host_efer & ignore_bits;
26bb0981 751 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 752 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 753
754 clear_atomic_switch_msr(vmx, MSR_EFER);
755 /* On ept, can't emulate nx, and must switch nx atomically */
756 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
757 guest_efer = vmx->vcpu.arch.efer;
758 if (!(guest_efer & EFER_LMA))
759 guest_efer &= ~EFER_LME;
760 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
761 return false;
762 }
763
26bb0981 764 return true;
51c6cf66
AK		 765}
766
2d49ec72
GN		 767static unsigned long segment_base(u16 selector)
768{
d359192f 769 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 770 struct desc_struct *d;
771 unsigned long table_base;
772 unsigned long v;
773
774 if (!(selector & ~3))
775 return 0;
776
d359192f 777 table_base = gdt->address;
2d49ec72
GN		 778
779 if (selector & 4) { /* from ldt */
780 u16 ldt_selector = kvm_read_ldt();
781
782 if (!(ldt_selector & ~3))
783 return 0;
784
785 table_base = segment_base(ldt_selector);
786 }
787 d = (struct desc_struct *)(table_base + (selector & ~7));
788 v = get_desc_base(d);
789#ifdef CONFIG_X86_64
790 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
791 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
792#endif
793 return v;
794}
795
796static inline unsigned long kvm_read_tr_base(void)
797{
798 u16 tr;
799 asm("str %0" : "=g"(tr));
800 return segment_base(tr);
801}
802
04d2cc77 803static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 804{
04d2cc77 805 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 806 int i;
04d2cc77 807
a2fa3e9f 808 if (vmx->host_state.loaded)
33ed6329
AK		 809 return;
810
a2fa3e9f 811 vmx->host_state.loaded = 1;
33ed6329
AK		 812 /*
813 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
814 * allow segment selectors with cpl > 0 or ti == 1.
815 */
d6e88aec 816 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 817 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 818 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 819 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 820 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 821 vmx->host_state.fs_reload_needed = 0;
822 } else {
33ed6329 823 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 824 vmx->host_state.fs_reload_needed = 1;
33ed6329 825 }
9581d442 826 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 827 if (!(vmx->host_state.gs_sel & 7))
828 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 829 else {
830 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 831 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 832 }
833
834#ifdef CONFIG_X86_64
835 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
836 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
837#else
a2fa3e9f
GH		 838 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
839 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 840#endif
707c0874
AK		 841
842#ifdef CONFIG_X86_64
c8770e7b
AK		 843 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
844 if (is_long_mode(&vmx->vcpu))
44ea2b17 845 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 846#endif
26bb0981
AK		 847 for (i = 0; i < vmx->save_nmsrs; ++i)
848 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 849 vmx->guest_msrs[i].data,
850 vmx->guest_msrs[i].mask);
33ed6329
AK		 851}
852
a9b21b62 853static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 854{
a2fa3e9f 855 if (!vmx->host_state.loaded)
33ed6329
AK		 856 return;
857
e1beb1d3 858 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 859 vmx->host_state.loaded = 0;
c8770e7b
AK		 860#ifdef CONFIG_X86_64
861 if (is_long_mode(&vmx->vcpu))
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
863#endif
152d3f2f 864 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 865 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 866#ifdef CONFIG_X86_64
9581d442 867 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 868#else
869 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 870#endif
33ed6329 871 }
0a77fe4c
AK		 872 if (vmx->host_state.fs_reload_needed)
873 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 874 reload_tss();
44ea2b17 875#ifdef CONFIG_X86_64
c8770e7b 876 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 877#endif
1c11e713
AK		 878 if (current_thread_info()->status & TS_USEDFPU)
879 clts();
3444d7da 880 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 881}
882
a9b21b62
AK		 883static void vmx_load_host_state(struct vcpu_vmx *vmx)
884{
885 preempt_disable();
886 __vmx_load_host_state(vmx);
887 preempt_enable();
888}
889
6aa8b732
AK		 890/*
891 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
892 * vcpu mutex is already taken.
893 */
15ad7146 894static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 895{
a2fa3e9f 896 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 897 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 898
4610c9cc
DX		 899 if (!vmm_exclusive)
900 kvm_cpu_vmxon(phys_addr);
901 else if (vcpu->cpu != cpu)
8b9cf98c 902 vcpu_clear(vmx);
6aa8b732 903
a2fa3e9f 904 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 905 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 906 vmcs_load(vmx->vmcs);
6aa8b732
AK		 907 }
908
909 if (vcpu->cpu != cpu) {
d359192f 910 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 911 unsigned long sysenter_esp;
912
a8eeb04a 913 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 914 local_irq_disable();
915 list_add(&vmx->local_vcpus_link,
916 &per_cpu(vcpus_on_cpu, cpu));
917 local_irq_enable();
918
6aa8b732
AK		 919 /*
920 * Linux uses per-cpu TSS and GDT, so set these when switching
921 * processors.
922 */
d6e88aec 923 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 924 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 925
926 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
927 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
928 }
6aa8b732
AK		 929}
930
931static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
932{
a9b21b62 933 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 934 if (!vmm_exclusive) {
b923e62e 935 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 936 kvm_cpu_vmxoff();
937 }
6aa8b732
AK		 938}
939
5fd86fcf
AK		 940static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
941{
81231c69
AK		 942 ulong cr0;
943
5fd86fcf
AK		 944 if (vcpu->fpu_active)
945 return;
946 vcpu->fpu_active = 1;
81231c69
AK		 947 cr0 = vmcs_readl(GUEST_CR0);
948 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
949 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
950 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 951 update_exception_bitmap(vcpu);
edcafe3c
AK		 952 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
953 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 954}
955
edcafe3c
AK		 956static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
957
5fd86fcf
AK		 958static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
959{
edcafe3c 960 vmx_decache_cr0_guest_bits(vcpu);
81231c69 961 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 962 update_exception_bitmap(vcpu);
edcafe3c
AK		 963 vcpu->arch.cr0_guest_owned_bits = 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 966}
967
6aa8b732
AK		 968static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
969{
78ac8b47 970 unsigned long rflags, save_rflags;
345dcaa8
AK		 971
972 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 973 if (to_vmx(vcpu)->rmode.vm86_active) {
974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
977 }
345dcaa8 978 return rflags;
6aa8b732
AK		 979}
980
981static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
982{
78ac8b47
AK		 983 if (to_vmx(vcpu)->rmode.vm86_active) {
984 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 985 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 986 }
6aa8b732
AK		 987 vmcs_writel(GUEST_RFLAGS, rflags);
988}
989
2809f5d2
GC		 990static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991{
992 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
993 int ret = 0;
994
995 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 996 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 997 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 998 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 999
1000 return ret & mask;
1001}
1002
1003static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004{
1005 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006 u32 interruptibility = interruptibility_old;
1007
1008 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
48005f64 1010 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1011 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1012 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1013 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015 if ((interruptibility != interruptibility_old))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017}
1018
6aa8b732
AK		 1019static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020{
1021 unsigned long rip;
6aa8b732 1022
5fdbf976 1023 rip = kvm_rip_read(vcpu);
6aa8b732 1024 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1025 kvm_rip_write(vcpu, rip);
6aa8b732 1026
2809f5d2
GC		 1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1029}
1030
443381a8
AL		 1031static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1032{
1033 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1034 * explicitly skip the instruction because if the HLT state is set, then
1035 * the instruction is already executing and RIP has already been
1036 * advanced. */
1037 if (!yield_on_hlt &&
1038 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1039 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1040}
1041
298101da 1042static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1043 bool has_error_code, u32 error_code,
1044 bool reinject)
298101da 1045{
77ab6db0 1046 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1047 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1048
8ab2d2e2 1049 if (has_error_code) {
77ab6db0 1050 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1051 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1052 }
77ab6db0 1053
7ffd92c5 1054 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1055 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1056 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1057 return;
1058 }
1059
66fd3f7f
GN		 1060 if (kvm_exception_is_soft(nr)) {
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1062 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1063 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1064 } else
1065 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1066
1067 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1068 vmx_clear_hlt(vcpu);
298101da
AK		 1069}
1070
4e47c7a6
SY		 1071static bool vmx_rdtscp_supported(void)
1072{
1073 return cpu_has_vmx_rdtscp();
1074}
1075
a75beee6
ED		 1076/*
1077 * Swap MSR entry in host/guest MSR entry array.
1078 */
8b9cf98c 1079static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1080{
26bb0981 1081 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1082
1083 tmp = vmx->guest_msrs[to];
1084 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1085 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1086}
1087
e38aea3e
AK		 1088/*
1089 * Set up the vmcs to automatically save and restore system
1090 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1091 * mode, as fiddling with msrs is very expensive.
1092 */
8b9cf98c 1093static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1094{
26bb0981 1095 int save_nmsrs, index;
5897297b 1096 unsigned long *msr_bitmap;
e38aea3e 1097
33f9c505 1098 vmx_load_host_state(vmx);
a75beee6
ED		 1099 save_nmsrs = 0;
1100#ifdef CONFIG_X86_64
8b9cf98c 1101 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1102 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1103 if (index >= 0)
8b9cf98c
RR		 1104 move_msr_up(vmx, index, save_nmsrs++);
1105 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1106 if (index >= 0)
8b9cf98c
RR		 1107 move_msr_up(vmx, index, save_nmsrs++);
1108 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1109 if (index >= 0)
8b9cf98c 1110 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1111 index = __find_msr_index(vmx, MSR_TSC_AUX);
1112 if (index >= 0 && vmx->rdtscp_enabled)
1113 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1114 /*
8c06585d 1115 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1116 * if efer.sce is enabled.
1117 */
8c06585d 1118 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1119 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1120 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1121 }
1122#endif
92c0d900
AK		 1123 index = __find_msr_index(vmx, MSR_EFER);
1124 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1125 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1126
26bb0981 1127 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1128
1129 if (cpu_has_vmx_msr_bitmap()) {
1130 if (is_long_mode(&vmx->vcpu))
1131 msr_bitmap = vmx_msr_bitmap_longmode;
1132 else
1133 msr_bitmap = vmx_msr_bitmap_legacy;
1134
1135 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1136 }
e38aea3e
AK		 1137}
1138
6aa8b732
AK		 1139/*
1140 * reads and returns guest's timestamp counter "register"
1141 * guest_tsc = host_tsc + tsc_offset -- 21.3
1142 */
1143static u64 guest_read_tsc(void)
1144{
1145 u64 host_tsc, tsc_offset;
1146
1147 rdtscll(host_tsc);
1148 tsc_offset = vmcs_read64(TSC_OFFSET);
1149 return host_tsc + tsc_offset;
1150}
1151
1152/*
99e3e30a 1153 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1154 */
99e3e30a 1155static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1156{
f4e1b3c8 1157 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1158}
1159
e48672fa
ZA		 1160static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1161{
1162 u64 offset = vmcs_read64(TSC_OFFSET);
1163 vmcs_write64(TSC_OFFSET, offset + adjustment);
1164}
1165
6aa8b732
AK		 1166/*
1167 * Reads an msr value (of 'msr_index') into 'pdata'.
1168 * Returns 0 on success, non-0 otherwise.
1169 * Assumes vcpu_load() was already called.
1170 */
1171static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1172{
1173 u64 data;
26bb0981 1174 struct shared_msr_entry *msr;
6aa8b732
AK		 1175
1176 if (!pdata) {
1177 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1178 return -EINVAL;
1179 }
1180
1181 switch (msr_index) {
05b3e0c2 1182#ifdef CONFIG_X86_64
6aa8b732
AK		 1183 case MSR_FS_BASE:
1184 data = vmcs_readl(GUEST_FS_BASE);
1185 break;
1186 case MSR_GS_BASE:
1187 data = vmcs_readl(GUEST_GS_BASE);
1188 break;
44ea2b17
AK		 1189 case MSR_KERNEL_GS_BASE:
1190 vmx_load_host_state(to_vmx(vcpu));
1191 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1192 break;
26bb0981 1193#endif
6aa8b732 1194 case MSR_EFER:
3bab1f5d 1195 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1196 case MSR_IA32_TSC:
6aa8b732
AK		 1197 data = guest_read_tsc();
1198 break;
1199 case MSR_IA32_SYSENTER_CS:
1200 data = vmcs_read32(GUEST_SYSENTER_CS);
1201 break;
1202 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1203 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1204 break;
1205 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1206 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1207 break;
4e47c7a6
SY		 1208 case MSR_TSC_AUX:
1209 if (!to_vmx(vcpu)->rdtscp_enabled)
1210 return 1;
1211 /* Otherwise falls through */
6aa8b732 1212 default:
26bb0981 1213 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1214 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1215 if (msr) {
542423b0 1216 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1217 data = msr->data;
1218 break;
6aa8b732 1219 }
3bab1f5d 1220 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1221 }
1222
1223 *pdata = data;
1224 return 0;
1225}
1226
1227/*
1228 * Writes msr value into into the appropriate "register".
1229 * Returns 0 on success, non-0 otherwise.
1230 * Assumes vcpu_load() was already called.
1231 */
1232static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1233{
a2fa3e9f 1234 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1235 struct shared_msr_entry *msr;
2cc51560
ED		 1236 int ret = 0;
1237
6aa8b732 1238 switch (msr_index) {
3bab1f5d 1239 case MSR_EFER:
a9b21b62 1240 vmx_load_host_state(vmx);
2cc51560 1241 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1242 break;
16175a79 1243#ifdef CONFIG_X86_64
6aa8b732
AK		 1244 case MSR_FS_BASE:
1245 vmcs_writel(GUEST_FS_BASE, data);
1246 break;
1247 case MSR_GS_BASE:
1248 vmcs_writel(GUEST_GS_BASE, data);
1249 break;
44ea2b17
AK		 1250 case MSR_KERNEL_GS_BASE:
1251 vmx_load_host_state(vmx);
1252 vmx->msr_guest_kernel_gs_base = data;
1253 break;
6aa8b732
AK		 1254#endif
1255 case MSR_IA32_SYSENTER_CS:
1256 vmcs_write32(GUEST_SYSENTER_CS, data);
1257 break;
1258 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1259 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1260 break;
1261 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1262 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1263 break;
af24a4e4 1264 case MSR_IA32_TSC:
99e3e30a 1265 kvm_write_tsc(vcpu, data);
6aa8b732 1266 break;
468d472f
SY		 1267 case MSR_IA32_CR_PAT:
1268 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1269 vmcs_write64(GUEST_IA32_PAT, data);
1270 vcpu->arch.pat = data;
1271 break;
1272 }
4e47c7a6
SY		 1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274 break;
1275 case MSR_TSC_AUX:
1276 if (!vmx->rdtscp_enabled)
1277 return 1;
1278 /* Check reserved bit, higher 32 bits should be zero */
1279 if ((data >> 32) != 0)
1280 return 1;
1281 /* Otherwise falls through */
6aa8b732 1282 default:
8b9cf98c 1283 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1284 if (msr) {
542423b0 1285 vmx_load_host_state(vmx);
3bab1f5d
AK		 1286 msr->data = data;
1287 break;
6aa8b732 1288 }
2cc51560 1289 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1290 }
1291
2cc51560 1292 return ret;
6aa8b732
AK		 1293}
1294
5fdbf976 1295static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1296{
5fdbf976
MT		 1297 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1298 switch (reg) {
1299 case VCPU_REGS_RSP:
1300 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1301 break;
1302 case VCPU_REGS_RIP:
1303 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1304 break;
6de4f3ad
AK		 1305 case VCPU_EXREG_PDPTR:
1306 if (enable_ept)
1307 ept_save_pdptrs(vcpu);
1308 break;
5fdbf976
MT		 1309 default:
1310 break;
1311 }
6aa8b732
AK		 1312}
1313
355be0b9 1314static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1315{
ae675ef0
JK		 1316 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1317 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1318 else
1319 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1320
abd3f2d6 1321 update_exception_bitmap(vcpu);
6aa8b732
AK		 1322}
1323
1324static __init int cpu_has_kvm_support(void)
1325{
6210e37b 1326 return cpu_has_vmx();
6aa8b732
AK		 1327}
1328
1329static __init int vmx_disabled_by_bios(void)
1330{
1331 u64 msr;
1332
1333 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1334 if (msr & FEATURE_CONTROL_LOCKED) {
1335 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1336 && tboot_enabled())
1337 return 1;
1338 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
f9335afe
SW		 1339 && !tboot_enabled()) {
1340 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1341 " activate TXT before enabling KVM\n");
cafd6659 1342 return 1;
f9335afe 1343 }
cafd6659
SW		 1344 }
1345
1346 return 0;
62b3ffb8 1347 /* locked but not enabled */
6aa8b732
AK		 1348}
1349
7725b894
DX		 1350static void kvm_cpu_vmxon(u64 addr)
1351{
1352 asm volatile (ASM_VMX_VMXON_RAX
1353 : : "a"(&addr), "m"(addr)
1354 : "memory", "cc");
1355}
1356
10474ae8 1357static int hardware_enable(void *garbage)
6aa8b732
AK		 1358{
1359 int cpu = raw_smp_processor_id();
1360 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1361 u64 old, test_bits;
6aa8b732 1362
10474ae8
AG		 1363 if (read_cr4() & X86_CR4_VMXE)
1364 return -EBUSY;
1365
543e4243 1366 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1367 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1368
1369 test_bits = FEATURE_CONTROL_LOCKED;
1370 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1371 if (tboot_enabled())
1372 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1373
1374 if ((old & test_bits) != test_bits) {
6aa8b732 1375 /* enable and lock */
cafd6659
SW		 1376 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1377 }
66aee91a 1378 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1379
4610c9cc
DX		 1380 if (vmm_exclusive) {
1381 kvm_cpu_vmxon(phys_addr);
1382 ept_sync_global();
1383 }
10474ae8 1384
3444d7da
AK		 1385 store_gdt(&__get_cpu_var(host_gdt));
1386
10474ae8 1387 return 0;
6aa8b732
AK		 1388}
1389
543e4243
AK		 1390static void vmclear_local_vcpus(void)
1391{
1392 int cpu = raw_smp_processor_id();
1393 struct vcpu_vmx *vmx, *n;
1394
1395 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1396 local_vcpus_link)
1397 __vcpu_clear(vmx);
1398}
1399
710ff4a8
EH		 1400
1401/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1402 * tricks.
1403 */
1404static void kvm_cpu_vmxoff(void)
6aa8b732 1405{
4ecac3fd 1406 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1407}
1408
710ff4a8
EH		 1409static void hardware_disable(void *garbage)
1410{
4610c9cc
DX		 1411 if (vmm_exclusive) {
1412 vmclear_local_vcpus();
1413 kvm_cpu_vmxoff();
1414 }
7725b894 1415 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1416}
1417
1c3d14fe 1418static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1419 u32 msr, u32 *result)
1c3d14fe
YS		 1420{
1421 u32 vmx_msr_low, vmx_msr_high;
1422 u32 ctl = ctl_min | ctl_opt;
1423
1424 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1425
1426 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1427 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1428
1429 /* Ensure minimum (required) set of control bits are supported. */
1430 if (ctl_min & ~ctl)
002c7f7c 1431 return -EIO;
1c3d14fe
YS		 1432
1433 *result = ctl;
1434 return 0;
1435}
1436
110312c8
AK		 1437static __init bool allow_1_setting(u32 msr, u32 ctl)
1438{
1439 u32 vmx_msr_low, vmx_msr_high;
1440
1441 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1442 return vmx_msr_high & ctl;
1443}
1444
002c7f7c 1445static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1446{
1447 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1448 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1449 u32 _pin_based_exec_control = 0;
1450 u32 _cpu_based_exec_control = 0;
f78e0e2e 1451 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1452 u32 _vmexit_control = 0;
1453 u32 _vmentry_control = 0;
1454
1455 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1456 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1458 &_pin_based_exec_control) < 0)
002c7f7c 1459 return -EIO;
1c3d14fe 1460
443381a8 1461 min =
1c3d14fe
YS		 1462#ifdef CONFIG_X86_64
1463 CPU_BASED_CR8_LOAD_EXITING |
1464 CPU_BASED_CR8_STORE_EXITING |
1465#endif
d56f546d
SY		 1466 CPU_BASED_CR3_LOAD_EXITING |
1467 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1468 CPU_BASED_USE_IO_BITMAPS |
1469 CPU_BASED_MOV_DR_EXITING |
a7052897 1470 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1471 CPU_BASED_MWAIT_EXITING |
1472 CPU_BASED_MONITOR_EXITING |
a7052897 1473 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1474
1475 if (yield_on_hlt)
1476 min |= CPU_BASED_HLT_EXITING;
1477
f78e0e2e 1478 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1479 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1480 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1481 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1482 &_cpu_based_exec_control) < 0)
002c7f7c 1483 return -EIO;
6e5d865c
YS		 1484#ifdef CONFIG_X86_64
1485 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1486 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1487 ~CPU_BASED_CR8_STORE_EXITING;
1488#endif
f78e0e2e 1489 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1490 min2 = 0;
1491 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1492 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1493 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1494 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1495 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1496 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1497 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1498 if (adjust_vmx_controls(min2, opt2,
1499 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1500 &_cpu_based_2nd_exec_control) < 0)
1501 return -EIO;
1502 }
1503#ifndef CONFIG_X86_64
1504 if (!(_cpu_based_2nd_exec_control &
1505 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1506 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1507#endif
d56f546d 1508 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1509 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1510 enabled */
5fff7d27
GN		 1511 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1512 CPU_BASED_CR3_STORE_EXITING |
1513 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1514 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1515 vmx_capability.ept, vmx_capability.vpid);
1516 }
1c3d14fe
YS		 1517
1518 min = 0;
1519#ifdef CONFIG_X86_64
1520 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1521#endif
468d472f 1522 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1523 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1524 &_vmexit_control) < 0)
002c7f7c 1525 return -EIO;
1c3d14fe 1526
468d472f
SY		 1527 min = 0;
1528 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1529 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1530 &_vmentry_control) < 0)
002c7f7c 1531 return -EIO;
6aa8b732 1532
c68876fd 1533 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1534
1535 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1536 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1537 return -EIO;
1c3d14fe
YS		 1538
1539#ifdef CONFIG_X86_64
1540 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1541 if (vmx_msr_high & (1u<<16))
002c7f7c 1542 return -EIO;
1c3d14fe
YS		 1543#endif
1544
1545 /* Require Write-Back (WB) memory type for VMCS accesses. */
1546 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1547 return -EIO;
1c3d14fe 1548
002c7f7c
YS		 1549 vmcs_conf->size = vmx_msr_high & 0x1fff;
1550 vmcs_conf->order = get_order(vmcs_config.size);
1551 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1552
002c7f7c
YS		 1553 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1554 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1555 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1556 vmcs_conf->vmexit_ctrl = _vmexit_control;
1557 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1558
110312c8
AK		 1559 cpu_has_load_ia32_efer =
1560 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1561 VM_ENTRY_LOAD_IA32_EFER)
1562 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1563 VM_EXIT_LOAD_IA32_EFER);
1564
1c3d14fe 1565 return 0;
c68876fd 1566}
6aa8b732
AK		 1567
1568static struct vmcs *alloc_vmcs_cpu(int cpu)
1569{
1570 int node = cpu_to_node(cpu);
1571 struct page *pages;
1572 struct vmcs *vmcs;
1573
6484eb3e 1574 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1575 if (!pages)
1576 return NULL;
1577 vmcs = page_address(pages);
1c3d14fe
YS		 1578 memset(vmcs, 0, vmcs_config.size);
1579 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1580 return vmcs;
1581}
1582
1583static struct vmcs *alloc_vmcs(void)
1584{
d3b2c338 1585 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1586}
1587
1588static void free_vmcs(struct vmcs *vmcs)
1589{
1c3d14fe 1590 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1591}
1592
39959588 1593static void free_kvm_area(void)
6aa8b732
AK		 1594{
1595 int cpu;
1596
3230bb47 1597 for_each_possible_cpu(cpu) {
6aa8b732 1598 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1599 per_cpu(vmxarea, cpu) = NULL;
1600 }
6aa8b732
AK		 1601}
1602
6aa8b732
AK		 1603static __init int alloc_kvm_area(void)
1604{
1605 int cpu;
1606
3230bb47 1607 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1608 struct vmcs *vmcs;
1609
1610 vmcs = alloc_vmcs_cpu(cpu);
1611 if (!vmcs) {
1612 free_kvm_area();
1613 return -ENOMEM;
1614 }
1615
1616 per_cpu(vmxarea, cpu) = vmcs;
1617 }
1618 return 0;
1619}
1620
1621static __init int hardware_setup(void)
1622{
002c7f7c
YS		 1623 if (setup_vmcs_config(&vmcs_config) < 0)
1624 return -EIO;
50a37eb4
JR		 1625
1626 if (boot_cpu_has(X86_FEATURE_NX))
1627 kvm_enable_efer_bits(EFER_NX);
1628
93ba03c2
SY		 1629 if (!cpu_has_vmx_vpid())
1630 enable_vpid = 0;
1631
4bc9b982
SY		 1632 if (!cpu_has_vmx_ept() ||
1633 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1634 enable_ept = 0;
3a624e29
NK		 1635 enable_unrestricted_guest = 0;
1636 }
1637
1638 if (!cpu_has_vmx_unrestricted_guest())
1639 enable_unrestricted_guest = 0;
93ba03c2
SY		 1640
1641 if (!cpu_has_vmx_flexpriority())
1642 flexpriority_enabled = 0;
1643
95ba8273
GN		 1644 if (!cpu_has_vmx_tpr_shadow())
1645 kvm_x86_ops->update_cr8_intercept = NULL;
1646
54dee993
MT		 1647 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1648 kvm_disable_largepages();
1649
4b8d54f9
ZE		 1650 if (!cpu_has_vmx_ple())
1651 ple_gap = 0;
1652
6aa8b732
AK		 1653 return alloc_kvm_area();
1654}
1655
1656static __exit void hardware_unsetup(void)
1657{
1658 free_kvm_area();
1659}
1660
6aa8b732
AK		 1661static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1662{
1663 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1664
6af11b9e 1665 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1666 vmcs_write16(sf->selector, save->selector);
1667 vmcs_writel(sf->base, save->base);
1668 vmcs_write32(sf->limit, save->limit);
1669 vmcs_write32(sf->ar_bytes, save->ar);
1670 } else {
1671 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1672 << AR_DPL_SHIFT;
1673 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1674 }
1675}
1676
1677static void enter_pmode(struct kvm_vcpu *vcpu)
1678{
1679 unsigned long flags;
a89a8fb9 1680 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1681
a89a8fb9 1682 vmx->emulation_required = 1;
7ffd92c5 1683 vmx->rmode.vm86_active = 0;
6aa8b732 1684
7ffd92c5
AK		 1685 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1686 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1687 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1688
1689 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1690 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1691 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1692 vmcs_writel(GUEST_RFLAGS, flags);
1693
66aee91a
RR		 1694 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1695 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1696
1697 update_exception_bitmap(vcpu);
1698
a89a8fb9
MG		 1699 if (emulate_invalid_guest_state)
1700 return;
1701
7ffd92c5
AK		 1702 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1703 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1704 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1705 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1706
1707 vmcs_write16(GUEST_SS_SELECTOR, 0);
1708 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1709
1710 vmcs_write16(GUEST_CS_SELECTOR,
1711 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1712 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1713}
1714
d77c26fc 1715static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1716{
bfc6d222 1717 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1718 struct kvm_memslots *slots;
1719 gfn_t base_gfn;
1720
90d83dc3 1721 slots = kvm_memslots(kvm);
f495c6e5 1722 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1723 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1724 return base_gfn << PAGE_SHIFT;
1725 }
bfc6d222 1726 return kvm->arch.tss_addr;
6aa8b732
AK		 1727}
1728
1729static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1730{
1731 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1732
1733 save->selector = vmcs_read16(sf->selector);
1734 save->base = vmcs_readl(sf->base);
1735 save->limit = vmcs_read32(sf->limit);
1736 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1737 vmcs_write16(sf->selector, save->base >> 4);
1738 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1739 vmcs_write32(sf->limit, 0xffff);
1740 vmcs_write32(sf->ar_bytes, 0xf3);
1741}
1742
1743static void enter_rmode(struct kvm_vcpu *vcpu)
1744{
1745 unsigned long flags;
a89a8fb9 1746 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1747
3a624e29
NK		 1748 if (enable_unrestricted_guest)
1749 return;
1750
a89a8fb9 1751 vmx->emulation_required = 1;
7ffd92c5 1752 vmx->rmode.vm86_active = 1;
6aa8b732 1753
7ffd92c5 1754 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1755 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1756
7ffd92c5 1757 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1758 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1759
7ffd92c5 1760 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1761 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1762
1763 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1764 vmx->rmode.save_rflags = flags;
6aa8b732 1765
053de044 1766 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1767
1768 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1769 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1770 update_exception_bitmap(vcpu);
1771
a89a8fb9
MG		 1772 if (emulate_invalid_guest_state)
1773 goto continue_rmode;
1774
6aa8b732
AK		 1775 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1776 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1777 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1778
1779 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1780 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1781 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1782 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1783 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1784
7ffd92c5
AK		 1785 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1786 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1787 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1788 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1789
a89a8fb9 1790continue_rmode:
8668a3c4 1791 kvm_mmu_reset_context(vcpu);
b7ebfb05 1792 init_rmode(vcpu->kvm);
6aa8b732
AK		 1793}
1794
401d10de
AS		 1795static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1796{
1797 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1798 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1799
1800 if (!msr)
1801 return;
401d10de 1802
44ea2b17
AK		 1803 /*
1804 * Force kernel_gs_base reloading before EFER changes, as control
1805 * of this msr depends on is_long_mode().
1806 */
1807 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1808 vcpu->arch.efer = efer;
401d10de
AS		 1809 if (efer & EFER_LMA) {
1810 vmcs_write32(VM_ENTRY_CONTROLS,
1811 vmcs_read32(VM_ENTRY_CONTROLS) |
1812 VM_ENTRY_IA32E_MODE);
1813 msr->data = efer;
1814 } else {
1815 vmcs_write32(VM_ENTRY_CONTROLS,
1816 vmcs_read32(VM_ENTRY_CONTROLS) &
1817 ~VM_ENTRY_IA32E_MODE);
1818
1819 msr->data = efer & ~EFER_LME;
1820 }
1821 setup_msrs(vmx);
1822}
1823
05b3e0c2 1824#ifdef CONFIG_X86_64
6aa8b732
AK		 1825
1826static void enter_lmode(struct kvm_vcpu *vcpu)
1827{
1828 u32 guest_tr_ar;
1829
1830 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1831 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1832 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1833 __func__);
6aa8b732
AK		 1834 vmcs_write32(GUEST_TR_AR_BYTES,
1835 (guest_tr_ar & ~AR_TYPE_MASK)
1836 | AR_TYPE_BUSY_64_TSS);
1837 }
da38f438 1838 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1839}
1840
1841static void exit_lmode(struct kvm_vcpu *vcpu)
1842{
6aa8b732
AK		 1843 vmcs_write32(VM_ENTRY_CONTROLS,
1844 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1845 & ~VM_ENTRY_IA32E_MODE);
da38f438 1846 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1847}
1848
1849#endif
1850
2384d2b3
SY		 1851static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1852{
b9d762fa 1853 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1854 if (enable_ept) {
1855 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1856 return;
4e1096d2 1857 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1858 }
2384d2b3
SY		 1859}
1860
e8467fda
AK		 1861static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1862{
1863 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1864
1865 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1866 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1867}
1868
25c4c276 1869static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1870{
fc78f519
AK		 1871 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1872
1873 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1874 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1875}
1876
1439442c
SY		 1877static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1878{
6de4f3ad
AK		 1879 if (!test_bit(VCPU_EXREG_PDPTR,
1880 (unsigned long *)&vcpu->arch.regs_dirty))
1881 return;
1882
1439442c 1883 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1884 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1885 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1886 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1887 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1888 }
1889}
1890
8f5d549f
AK		 1891static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1892{
1893 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1894 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1895 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1896 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1897 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1898 }
6de4f3ad
AK		 1899
1900 __set_bit(VCPU_EXREG_PDPTR,
1901 (unsigned long *)&vcpu->arch.regs_avail);
1902 __set_bit(VCPU_EXREG_PDPTR,
1903 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1904}
1905
1439442c
SY		 1906static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1907
1908static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1909 unsigned long cr0,
1910 struct kvm_vcpu *vcpu)
1911{
1912 if (!(cr0 & X86_CR0_PG)) {
1913 /* From paging/starting to nonpaging */
1914 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1915 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1916 (CPU_BASED_CR3_LOAD_EXITING |
1917 CPU_BASED_CR3_STORE_EXITING));
1918 vcpu->arch.cr0 = cr0;
fc78f519 1919 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1920 } else if (!is_paging(vcpu)) {
1921 /* From nonpaging to paging */
1922 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1923 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1924 ~(CPU_BASED_CR3_LOAD_EXITING |
1925 CPU_BASED_CR3_STORE_EXITING));
1926 vcpu->arch.cr0 = cr0;
fc78f519 1927 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1928 }
95eb84a7
SY		 1929
1930 if (!(cr0 & X86_CR0_WP))
1931 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1932}
1933
6aa8b732
AK		 1934static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1935{
7ffd92c5 1936 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1937 unsigned long hw_cr0;
1938
1939 if (enable_unrestricted_guest)
1940 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1941 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1942 else
1943 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1944
7ffd92c5 1945 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1946 enter_pmode(vcpu);
1947
7ffd92c5 1948 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1949 enter_rmode(vcpu);
1950
05b3e0c2 1951#ifdef CONFIG_X86_64
f6801dff 1952 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1953 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1954 enter_lmode(vcpu);
707d92fa 1955 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1956 exit_lmode(vcpu);
1957 }
1958#endif
1959
089d034e 1960 if (enable_ept)
1439442c
SY		 1961 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1962
02daab21 1963 if (!vcpu->fpu_active)
81231c69 1964 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1965
6aa8b732 1966 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1967 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1968 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1969}
1970
1439442c
SY		 1971static u64 construct_eptp(unsigned long root_hpa)
1972{
1973 u64 eptp;
1974
1975 /* TODO write the value reading from MSR */
1976 eptp = VMX_EPT_DEFAULT_MT |
1977 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1978 eptp |= (root_hpa & PAGE_MASK);
1979
1980 return eptp;
1981}
1982
6aa8b732
AK		 1983static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1984{
1439442c
SY		 1985 unsigned long guest_cr3;
1986 u64 eptp;
1987
1988 guest_cr3 = cr3;
089d034e 1989 if (enable_ept) {
1439442c
SY		 1990 eptp = construct_eptp(cr3);
1991 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 1992 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 1993 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1994 ept_load_pdptrs(vcpu);
1439442c
SY		 1995 }
1996
2384d2b3 1997 vmx_flush_tlb(vcpu);
1439442c 1998 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1999}
2000
2001static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2002{
7ffd92c5 2003 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2004 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2005
ad312c7c 2006 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2007 if (enable_ept) {
2008 if (!is_paging(vcpu)) {
2009 hw_cr4 &= ~X86_CR4_PAE;
2010 hw_cr4 |= X86_CR4_PSE;
2011 } else if (!(cr4 & X86_CR4_PAE)) {
2012 hw_cr4 &= ~X86_CR4_PAE;
2013 }
2014 }
1439442c
SY		 2015
2016 vmcs_writel(CR4_READ_SHADOW, cr4);
2017 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2018}
2019
6aa8b732
AK		 2020static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2021{
2022 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2023
2024 return vmcs_readl(sf->base);
2025}
2026
2027static void vmx_get_segment(struct kvm_vcpu *vcpu,
2028 struct kvm_segment *var, int seg)
2029{
2030 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2031 u32 ar;
2032
2033 var->base = vmcs_readl(sf->base);
2034 var->limit = vmcs_read32(sf->limit);
2035 var->selector = vmcs_read16(sf->selector);
2036 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2037 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2038 ar = 0;
2039 var->type = ar & 15;
2040 var->s = (ar >> 4) & 1;
2041 var->dpl = (ar >> 5) & 3;
2042 var->present = (ar >> 7) & 1;
2043 var->avl = (ar >> 12) & 1;
2044 var->l = (ar >> 13) & 1;
2045 var->db = (ar >> 14) & 1;
2046 var->g = (ar >> 15) & 1;
2047 var->unusable = (ar >> 16) & 1;
2048}
2049
2e4d2653
IE		 2050static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2051{
3eeb3288 2052 if (!is_protmode(vcpu))
2e4d2653
IE		 2053 return 0;
2054
2055 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2056 return 3;
2057
eab4b8aa 2058 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2059}
2060
653e3108 2061static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2062{
6aa8b732
AK		 2063 u32 ar;
2064
653e3108 2065 if (var->unusable)
6aa8b732
AK		 2066 ar = 1 << 16;
2067 else {
2068 ar = var->type & 15;
2069 ar |= (var->s & 1) << 4;
2070 ar |= (var->dpl & 3) << 5;
2071 ar |= (var->present & 1) << 7;
2072 ar |= (var->avl & 1) << 12;
2073 ar |= (var->l & 1) << 13;
2074 ar |= (var->db & 1) << 14;
2075 ar |= (var->g & 1) << 15;
2076 }
f7fbf1fd
UL		 2077 if (ar == 0) /* a 0 value means unusable */
2078 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2079
2080 return ar;
2081}
2082
2083static void vmx_set_segment(struct kvm_vcpu *vcpu,
2084 struct kvm_segment *var, int seg)
2085{
7ffd92c5 2086 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2087 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2088 u32 ar;
2089
7ffd92c5
AK		 2090 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2091 vmx->rmode.tr.selector = var->selector;
2092 vmx->rmode.tr.base = var->base;
2093 vmx->rmode.tr.limit = var->limit;
2094 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2095 return;
2096 }
2097 vmcs_writel(sf->base, var->base);
2098 vmcs_write32(sf->limit, var->limit);
2099 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2100 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2101 /*
2102 * Hack real-mode segments into vm86 compatibility.
2103 */
2104 if (var->base == 0xffff0000 && var->selector == 0xf000)
2105 vmcs_writel(sf->base, 0xf0000);
2106 ar = 0xf3;
2107 } else
2108 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2109
2110 /*
2111 * Fix the "Accessed" bit in AR field of segment registers for older
2112 * qemu binaries.
2113 * IA32 arch specifies that at the time of processor reset the
2114 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2115 * is setting it to 0 in the usedland code. This causes invalid guest
2116 * state vmexit when "unrestricted guest" mode is turned on.
2117 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2118 * tree. Newer qemu binaries with that qemu fix would not need this
2119 * kvm hack.
2120 */
2121 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2122 ar |= 0x1; /* Accessed */
2123
6aa8b732
AK		 2124 vmcs_write32(sf->ar_bytes, ar);
2125}
2126
6aa8b732
AK		 2127static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2128{
2129 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2130
2131 *db = (ar >> 14) & 1;
2132 *l = (ar >> 13) & 1;
2133}
2134
89a27f4d 2135static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2136{
89a27f4d
GN		 2137 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2138 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2139}
2140
89a27f4d 2141static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2142{
89a27f4d
GN		 2143 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2144 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2145}
2146
89a27f4d 2147static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2148{
89a27f4d
GN		 2149 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2150 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2151}
2152
89a27f4d 2153static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2154{
89a27f4d
GN		 2155 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2156 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2157}
2158
648dfaa7
MG		 2159static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2160{
2161 struct kvm_segment var;
2162 u32 ar;
2163
2164 vmx_get_segment(vcpu, &var, seg);
2165 ar = vmx_segment_access_rights(&var);
2166
2167 if (var.base != (var.selector << 4))
2168 return false;
2169 if (var.limit != 0xffff)
2170 return false;
2171 if (ar != 0xf3)
2172 return false;
2173
2174 return true;
2175}
2176
2177static bool code_segment_valid(struct kvm_vcpu *vcpu)
2178{
2179 struct kvm_segment cs;
2180 unsigned int cs_rpl;
2181
2182 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2183 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2184
1872a3f4
AK		 2185 if (cs.unusable)
2186 return false;
648dfaa7
MG		 2187 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2188 return false;
2189 if (!cs.s)
2190 return false;
1872a3f4 2191 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2192 if (cs.dpl > cs_rpl)
2193 return false;
1872a3f4 2194 } else {
648dfaa7
MG		 2195 if (cs.dpl != cs_rpl)
2196 return false;
2197 }
2198 if (!cs.present)
2199 return false;
2200
2201 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2202 return true;
2203}
2204
2205static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2206{
2207 struct kvm_segment ss;
2208 unsigned int ss_rpl;
2209
2210 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2211 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2212
1872a3f4
AK		 2213 if (ss.unusable)
2214 return true;
2215 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2216 return false;
2217 if (!ss.s)
2218 return false;
2219 if (ss.dpl != ss_rpl) /* DPL != RPL */
2220 return false;
2221 if (!ss.present)
2222 return false;
2223
2224 return true;
2225}
2226
2227static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2228{
2229 struct kvm_segment var;
2230 unsigned int rpl;
2231
2232 vmx_get_segment(vcpu, &var, seg);
2233 rpl = var.selector & SELECTOR_RPL_MASK;
2234
1872a3f4
AK		 2235 if (var.unusable)
2236 return true;
648dfaa7
MG		 2237 if (!var.s)
2238 return false;
2239 if (!var.present)
2240 return false;
2241 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2242 if (var.dpl < rpl) /* DPL < RPL */
2243 return false;
2244 }
2245
2246 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2247 * rights flags
2248 */
2249 return true;
2250}
2251
2252static bool tr_valid(struct kvm_vcpu *vcpu)
2253{
2254 struct kvm_segment tr;
2255
2256 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2257
1872a3f4
AK		 2258 if (tr.unusable)
2259 return false;
648dfaa7
MG		 2260 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2261 return false;
1872a3f4 2262 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2263 return false;
2264 if (!tr.present)
2265 return false;
2266
2267 return true;
2268}
2269
2270static bool ldtr_valid(struct kvm_vcpu *vcpu)
2271{
2272 struct kvm_segment ldtr;
2273
2274 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2275
1872a3f4
AK		 2276 if (ldtr.unusable)
2277 return true;
648dfaa7
MG		 2278 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2279 return false;
2280 if (ldtr.type != 2)
2281 return false;
2282 if (!ldtr.present)
2283 return false;
2284
2285 return true;
2286}
2287
2288static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2289{
2290 struct kvm_segment cs, ss;
2291
2292 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2293 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2294
2295 return ((cs.selector & SELECTOR_RPL_MASK) ==
2296 (ss.selector & SELECTOR_RPL_MASK));
2297}
2298
2299/*
2300 * Check if guest state is valid. Returns true if valid, false if
2301 * not.
2302 * We assume that registers are always usable
2303 */
2304static bool guest_state_valid(struct kvm_vcpu *vcpu)
2305{
2306 /* real mode guest state checks */
3eeb3288 2307 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2308 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2309 return false;
2310 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2311 return false;
2312 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2313 return false;
2314 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2315 return false;
2316 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2317 return false;
2318 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2319 return false;
2320 } else {
2321 /* protected mode guest state checks */
2322 if (!cs_ss_rpl_check(vcpu))
2323 return false;
2324 if (!code_segment_valid(vcpu))
2325 return false;
2326 if (!stack_segment_valid(vcpu))
2327 return false;
2328 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2329 return false;
2330 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2331 return false;
2332 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2333 return false;
2334 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2335 return false;
2336 if (!tr_valid(vcpu))
2337 return false;
2338 if (!ldtr_valid(vcpu))
2339 return false;
2340 }
2341 /* TODO:
2342 * - Add checks on RIP
2343 * - Add checks on RFLAGS
2344 */
2345
2346 return true;
2347}
2348
d77c26fc 2349static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2350{
6aa8b732 2351 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2352 u16 data = 0;
10589a46 2353 int ret = 0;
195aefde 2354 int r;
6aa8b732 2355
195aefde
IE		 2356 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2357 if (r < 0)
10589a46 2358 goto out;
195aefde 2359 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2360 r = kvm_write_guest_page(kvm, fn++, &data,
2361 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2362 if (r < 0)
10589a46 2363 goto out;
195aefde
IE		 2364 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2365 if (r < 0)
10589a46 2366 goto out;
195aefde
IE		 2367 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2368 if (r < 0)
10589a46 2369 goto out;
195aefde 2370 data = ~0;
10589a46
MT		 2371 r = kvm_write_guest_page(kvm, fn, &data,
2372 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2373 sizeof(u8));
195aefde 2374 if (r < 0)
10589a46
MT		 2375 goto out;
2376
2377 ret = 1;
2378out:
10589a46 2379 return ret;
6aa8b732
AK		 2380}
2381
b7ebfb05
SY		 2382static int init_rmode_identity_map(struct kvm *kvm)
2383{
2384 int i, r, ret;
2385 pfn_t identity_map_pfn;
2386 u32 tmp;
2387
089d034e 2388 if (!enable_ept)
b7ebfb05
SY		 2389 return 1;
2390 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2391 printk(KERN_ERR "EPT: identity-mapping pagetable "
2392 "haven't been allocated!\n");
2393 return 0;
2394 }
2395 if (likely(kvm->arch.ept_identity_pagetable_done))
2396 return 1;
2397 ret = 0;
b927a3ce 2398 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2399 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2400 if (r < 0)
2401 goto out;
2402 /* Set up identity-mapping pagetable for EPT in real mode */
2403 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2404 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2405 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2406 r = kvm_write_guest_page(kvm, identity_map_pfn,
2407 &tmp, i * sizeof(tmp), sizeof(tmp));
2408 if (r < 0)
2409 goto out;
2410 }
2411 kvm->arch.ept_identity_pagetable_done = true;
2412 ret = 1;
2413out:
2414 return ret;
2415}
2416
6aa8b732
AK		 2417static void seg_setup(int seg)
2418{
2419 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2420 unsigned int ar;
6aa8b732
AK		 2421
2422 vmcs_write16(sf->selector, 0);
2423 vmcs_writel(sf->base, 0);
2424 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2425 if (enable_unrestricted_guest) {
2426 ar = 0x93;
2427 if (seg == VCPU_SREG_CS)
2428 ar |= 0x08; /* code segment */
2429 } else
2430 ar = 0xf3;
2431
2432 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2433}
2434
f78e0e2e
SY		 2435static int alloc_apic_access_page(struct kvm *kvm)
2436{
2437 struct kvm_userspace_memory_region kvm_userspace_mem;
2438 int r = 0;
2439
79fac95e 2440 mutex_lock(&kvm->slots_lock);
bfc6d222 2441 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2442 goto out;
2443 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2444 kvm_userspace_mem.flags = 0;
2445 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2446 kvm_userspace_mem.memory_size = PAGE_SIZE;
2447 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2448 if (r)
2449 goto out;
72dc67a6 2450
bfc6d222 2451 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2452out:
79fac95e 2453 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2454 return r;
2455}
2456
b7ebfb05
SY		 2457static int alloc_identity_pagetable(struct kvm *kvm)
2458{
2459 struct kvm_userspace_memory_region kvm_userspace_mem;
2460 int r = 0;
2461
79fac95e 2462 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2463 if (kvm->arch.ept_identity_pagetable)
2464 goto out;
2465 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2466 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2467 kvm_userspace_mem.guest_phys_addr =
2468 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2469 kvm_userspace_mem.memory_size = PAGE_SIZE;
2470 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2471 if (r)
2472 goto out;
2473
b7ebfb05 2474 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2475 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2476out:
79fac95e 2477 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2478 return r;
2479}
2480
2384d2b3
SY		 2481static void allocate_vpid(struct vcpu_vmx *vmx)
2482{
2483 int vpid;
2484
2485 vmx->vpid = 0;
919818ab 2486 if (!enable_vpid)
2384d2b3
SY		 2487 return;
2488 spin_lock(&vmx_vpid_lock);
2489 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2490 if (vpid < VMX_NR_VPIDS) {
2491 vmx->vpid = vpid;
2492 __set_bit(vpid, vmx_vpid_bitmap);
2493 }
2494 spin_unlock(&vmx_vpid_lock);
2495}
2496
cdbecfc3
LJ		 2497static void free_vpid(struct vcpu_vmx *vmx)
2498{
2499 if (!enable_vpid)
2500 return;
2501 spin_lock(&vmx_vpid_lock);
2502 if (vmx->vpid != 0)
2503 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2504 spin_unlock(&vmx_vpid_lock);
2505}
2506
5897297b 2507static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2508{
3e7c73e9 2509 int f = sizeof(unsigned long);
25c5f225
SY		 2510
2511 if (!cpu_has_vmx_msr_bitmap())
2512 return;
2513
2514 /*
2515 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2516 * have the write-low and read-high bitmap offsets the wrong way round.
2517 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2518 */
25c5f225 2519 if (msr <= 0x1fff) {
3e7c73e9
AK		 2520 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2521 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2522 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2523 msr &= 0x1fff;
3e7c73e9
AK		 2524 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2525 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2526 }
25c5f225
SY		 2527}
2528
5897297b
AK		 2529static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2530{
2531 if (!longmode_only)
2532 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2533 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2534}
2535
6aa8b732
AK		 2536/*
2537 * Sets up the vmcs for emulated real mode.
2538 */
8b9cf98c 2539static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2540{
468d472f 2541 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2542 u32 junk;
f4e1b3c8 2543 u64 host_pat;
6aa8b732 2544 unsigned long a;
89a27f4d 2545 struct desc_ptr dt;
6aa8b732 2546 int i;
cd2276a7 2547 unsigned long kvm_vmx_return;
6e5d865c 2548 u32 exec_control;
6aa8b732 2549
6aa8b732 2550 /* I/O */
3e7c73e9
AK		 2551 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2552 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2553
25c5f225 2554 if (cpu_has_vmx_msr_bitmap())
5897297b 2555 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2556
6aa8b732
AK		 2557 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2558
6aa8b732 2559 /* Control */
1c3d14fe
YS		 2560 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2561 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2562
2563 exec_control = vmcs_config.cpu_based_exec_ctrl;
2564 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2565 exec_control &= ~CPU_BASED_TPR_SHADOW;
2566#ifdef CONFIG_X86_64
2567 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2568 CPU_BASED_CR8_LOAD_EXITING;
2569#endif
2570 }
089d034e 2571 if (!enable_ept)
d56f546d 2572 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2573 CPU_BASED_CR3_LOAD_EXITING |
2574 CPU_BASED_INVLPG_EXITING;
6e5d865c 2575 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2576
83ff3b9d
SY		 2577 if (cpu_has_secondary_exec_ctrls()) {
2578 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2579 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2580 exec_control &=
2581 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2582 if (vmx->vpid == 0)
2583 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2584 if (!enable_ept) {
d56f546d 2585 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2586 enable_unrestricted_guest = 0;
2587 }
3a624e29
NK		 2588 if (!enable_unrestricted_guest)
2589 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2590 if (!ple_gap)
2591 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2592 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2593 }
f78e0e2e 2594
4b8d54f9
ZE		 2595 if (ple_gap) {
2596 vmcs_write32(PLE_GAP, ple_gap);
2597 vmcs_write32(PLE_WINDOW, ple_window);
2598 }
2599
c7addb90
AK		 2600 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2601 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2602 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2603
1c11e713 2604 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2605 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2606 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2607
2608 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2609 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2610 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2611 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2612 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2613 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2614#ifdef CONFIG_X86_64
6aa8b732
AK		 2615 rdmsrl(MSR_FS_BASE, a);
2616 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2617 rdmsrl(MSR_GS_BASE, a);
2618 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2619#else
2620 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2621 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2622#endif
2623
2624 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2625
ec68798c 2626 native_store_idt(&dt);
89a27f4d 2627 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2628
d77c26fc 2629 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2630 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2631 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2632 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2633 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2635 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2636
2637 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2638 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2639 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2640 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2641 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2642 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2643
468d472f
SY		 2644 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2645 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2646 host_pat = msr_low | ((u64) msr_high << 32);
2647 vmcs_write64(HOST_IA32_PAT, host_pat);
2648 }
2649 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2650 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2651 host_pat = msr_low | ((u64) msr_high << 32);
2652 /* Write the default value follow host pat */
2653 vmcs_write64(GUEST_IA32_PAT, host_pat);
2654 /* Keep arch.pat sync with GUEST_IA32_PAT */
2655 vmx->vcpu.arch.pat = host_pat;
2656 }
2657
6aa8b732
AK		 2658 for (i = 0; i < NR_VMX_MSR; ++i) {
2659 u32 index = vmx_msr_index[i];
2660 u32 data_low, data_high;
a2fa3e9f 2661 int j = vmx->nmsrs;
6aa8b732
AK		 2662
2663 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2664 continue;
432bd6cb
AK		 2665 if (wrmsr_safe(index, data_low, data_high) < 0)
2666 continue;
26bb0981
AK		 2667 vmx->guest_msrs[j].index = i;
2668 vmx->guest_msrs[j].data = 0;
d5696725 2669 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2670 ++vmx->nmsrs;
6aa8b732 2671 }
6aa8b732 2672
1c3d14fe 2673 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2674
2675 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2676 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2677
e00c8cf2 2678 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2679 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2680 if (enable_ept)
2681 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2682 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2683
99e3e30a 2684 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2685
e00c8cf2
AK		 2686 return 0;
2687}
2688
b7ebfb05
SY		 2689static int init_rmode(struct kvm *kvm)
2690{
4b9d3a04
XG		 2691 int idx, ret = 0;
2692
2693 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2694 if (!init_rmode_tss(kvm))
4b9d3a04 2695 goto exit;
b7ebfb05 2696 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2697 goto exit;
2698
2699 ret = 1;
2700exit:
2701 srcu_read_unlock(&kvm->srcu, idx);
2702 return ret;
b7ebfb05
SY		 2703}
2704
e00c8cf2
AK		 2705static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2706{
2707 struct vcpu_vmx *vmx = to_vmx(vcpu);
2708 u64 msr;
4b9d3a04 2709 int ret;
e00c8cf2 2710
5fdbf976 2711 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2712 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2713 ret = -ENOMEM;
2714 goto out;
2715 }
2716
7ffd92c5 2717 vmx->rmode.vm86_active = 0;
e00c8cf2 2718
3b86cd99
JK		 2719 vmx->soft_vnmi_blocked = 0;
2720
ad312c7c 2721 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2722 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2723 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2724 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2725 msr |= MSR_IA32_APICBASE_BSP;
2726 kvm_set_apic_base(&vmx->vcpu, msr);
2727
10ab25cd
JK		 2728 ret = fx_init(&vmx->vcpu);
2729 if (ret != 0)
2730 goto out;
e00c8cf2 2731
5706be0d 2732 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2733 /*
2734 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2735 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2736 */
c5af89b6 2737 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2738 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2739 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2740 } else {
ad312c7c
ZX		 2741 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2742 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2743 }
e00c8cf2
AK		 2744
2745 seg_setup(VCPU_SREG_DS);
2746 seg_setup(VCPU_SREG_ES);
2747 seg_setup(VCPU_SREG_FS);
2748 seg_setup(VCPU_SREG_GS);
2749 seg_setup(VCPU_SREG_SS);
2750
2751 vmcs_write16(GUEST_TR_SELECTOR, 0);
2752 vmcs_writel(GUEST_TR_BASE, 0);
2753 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2754 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2755
2756 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2757 vmcs_writel(GUEST_LDTR_BASE, 0);
2758 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2759 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2760
2761 vmcs_write32(GUEST_SYSENTER_CS, 0);
2762 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2763 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2764
2765 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2766 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2767 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2768 else
5fdbf976
MT		 2769 kvm_rip_write(vcpu, 0);
2770 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2771
e00c8cf2
AK		 2772 vmcs_writel(GUEST_DR7, 0x400);
2773
2774 vmcs_writel(GUEST_GDTR_BASE, 0);
2775 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2776
2777 vmcs_writel(GUEST_IDTR_BASE, 0);
2778 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2779
443381a8 2780 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2781 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2782 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2783
e00c8cf2
AK		 2784 /* Special registers */
2785 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2786
2787 setup_msrs(vmx);
2788
6aa8b732
AK		 2789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2790
f78e0e2e
SY		 2791 if (cpu_has_vmx_tpr_shadow()) {
2792 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2793 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2794 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2795 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2796 vmcs_write32(TPR_THRESHOLD, 0);
2797 }
2798
2799 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2800 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2801 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2802
2384d2b3
SY		 2803 if (vmx->vpid != 0)
2804 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2805
fa40052c 2806 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2807 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2808 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2809 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2810 vmx_fpu_activate(&vmx->vcpu);
2811 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2812
b9d762fa 2813 vpid_sync_context(vmx);
2384d2b3 2814
3200f405 2815 ret = 0;
6aa8b732 2816
a89a8fb9
MG		 2817 /* HACK: Don't enable emulation on guest boot/reset */
2818 vmx->emulation_required = 0;
2819
6aa8b732
AK		 2820out:
2821 return ret;
2822}
2823
3b86cd99
JK		 2824static void enable_irq_window(struct kvm_vcpu *vcpu)
2825{
2826 u32 cpu_based_vm_exec_control;
2827
2828 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2829 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2830 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2831}
2832
2833static void enable_nmi_window(struct kvm_vcpu *vcpu)
2834{
2835 u32 cpu_based_vm_exec_control;
2836
2837 if (!cpu_has_virtual_nmis()) {
2838 enable_irq_window(vcpu);
2839 return;
2840 }
2841
30bd0c4c
AK		 2842 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2843 enable_irq_window(vcpu);
2844 return;
2845 }
3b86cd99
JK		 2846 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2847 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2848 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2849}
2850
66fd3f7f 2851static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2852{
9c8cba37 2853 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2854 uint32_t intr;
2855 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2856
229456fc 2857 trace_kvm_inj_virq(irq);
2714d1d3 2858
fa89a817 2859 ++vcpu->stat.irq_injections;
7ffd92c5 2860 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2861 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2862 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2863 return;
2864 }
66fd3f7f
GN		 2865 intr = irq | INTR_INFO_VALID_MASK;
2866 if (vcpu->arch.interrupt.soft) {
2867 intr |= INTR_TYPE_SOFT_INTR;
2868 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2869 vmx->vcpu.arch.event_exit_inst_len);
2870 } else
2871 intr |= INTR_TYPE_EXT_INTR;
2872 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2873 vmx_clear_hlt(vcpu);
85f455f7
ED		 2874}
2875
f08864b4
SY		 2876static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2877{
66a5a347
JK		 2878 struct vcpu_vmx *vmx = to_vmx(vcpu);
2879
3b86cd99
JK		 2880 if (!cpu_has_virtual_nmis()) {
2881 /*
2882 * Tracking the NMI-blocked state in software is built upon
2883 * finding the next open IRQ window. This, in turn, depends on
2884 * well-behaving guests: They have to keep IRQs disabled at
2885 * least as long as the NMI handler runs. Otherwise we may
2886 * cause NMI nesting, maybe breaking the guest. But as this is
2887 * highly unlikely, we can live with the residual risk.
2888 */
2889 vmx->soft_vnmi_blocked = 1;
2890 vmx->vnmi_blocked_time = 0;
2891 }
2892
487b391d 2893 ++vcpu->stat.nmi_injections;
7ffd92c5 2894 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2895 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2896 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2897 return;
2898 }
f08864b4
SY		 2899 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2900 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2901 vmx_clear_hlt(vcpu);
f08864b4
SY		 2902}
2903
c4282df9 2904static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2905{
3b86cd99 2906 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2907 return 0;
33f089ca 2908
c4282df9 2909 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 2910 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2911 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2912}
2913
3cfc3092
JK		 2914static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2915{
2916 if (!cpu_has_virtual_nmis())
2917 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2918 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2919}
2920
2921static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2922{
2923 struct vcpu_vmx *vmx = to_vmx(vcpu);
2924
2925 if (!cpu_has_virtual_nmis()) {
2926 if (vmx->soft_vnmi_blocked != masked) {
2927 vmx->soft_vnmi_blocked = masked;
2928 vmx->vnmi_blocked_time = 0;
2929 }
2930 } else {
2931 if (masked)
2932 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2933 GUEST_INTR_STATE_NMI);
2934 else
2935 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2936 GUEST_INTR_STATE_NMI);
2937 }
2938}
2939
78646121
GN		 2940static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2941{
c4282df9
GN		 2942 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2943 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2944 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2945}
2946
cbc94022
IE		 2947static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2948{
2949 int ret;
2950 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2951 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2952 .guest_phys_addr = addr,
2953 .memory_size = PAGE_SIZE * 3,
2954 .flags = 0,
2955 };
2956
2957 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2958 if (ret)
2959 return ret;
bfc6d222 2960 kvm->arch.tss_addr = addr;
cbc94022
IE		 2961 return 0;
2962}
2963
6aa8b732
AK		 2964static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2965 int vec, u32 err_code)
2966{
b3f37707
NK		 2967 /*
2968 * Instruction with address size override prefix opcode 0x67
2969 * Cause the #SS fault with 0 error code in VM86 mode.
2970 */
2971 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 2972 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 2973 return 1;
77ab6db0
JK		 2974 /*
2975 * Forward all other exceptions that are valid in real mode.
2976 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2977 * the required debugging infrastructure rework.
2978 */
2979 switch (vec) {
77ab6db0 2980 case DB_VECTOR:
d0bfb940
JK		 2981 if (vcpu->guest_debug &
2982 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2983 return 0;
2984 kvm_queue_exception(vcpu, vec);
2985 return 1;
77ab6db0 2986 case BP_VECTOR:
c573cd22
JK		 2987 /*
2988 * Update instruction length as we may reinject the exception
2989 * from user space while in guest debugging mode.
2990 */
2991 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2992 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2993 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2994 return 0;
2995 /* fall through */
2996 case DE_VECTOR:
77ab6db0
JK		 2997 case OF_VECTOR:
2998 case BR_VECTOR:
2999 case UD_VECTOR:
3000 case DF_VECTOR:
3001 case SS_VECTOR:
3002 case GP_VECTOR:
3003 case MF_VECTOR:
3004 kvm_queue_exception(vcpu, vec);
3005 return 1;
3006 }
6aa8b732
AK		 3007 return 0;
3008}
3009
a0861c02
AK		 3010/*
3011 * Trigger machine check on the host. We assume all the MSRs are already set up
3012 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3013 * We pass a fake environment to the machine check handler because we want
3014 * the guest to be always treated like user space, no matter what context
3015 * it used internally.
3016 */
3017static void kvm_machine_check(void)
3018{
3019#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3020 struct pt_regs regs = {
3021 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3022 .flags = X86_EFLAGS_IF,
3023 };
3024
3025 do_machine_check(&regs, 0);
3026#endif
3027}
3028
851ba692 3029static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3030{
3031 /* already handled by vcpu_run */
3032 return 1;
3033}
3034
851ba692 3035static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3036{
1155f76a 3037 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3038 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3039 u32 intr_info, ex_no, error_code;
42dbaa5a 3040 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3041 u32 vect_info;
3042 enum emulation_result er;
3043
1155f76a 3044 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3045 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3046
a0861c02 3047 if (is_machine_check(intr_info))
851ba692 3048 return handle_machine_check(vcpu);
a0861c02 3049
6aa8b732 3050 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3051 !is_page_fault(intr_info)) {
3052 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3053 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3054 vcpu->run->internal.ndata = 2;
3055 vcpu->run->internal.data[0] = vect_info;
3056 vcpu->run->internal.data[1] = intr_info;
3057 return 0;
3058 }
6aa8b732 3059
e4a41889 3060 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3061 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3062
3063 if (is_no_device(intr_info)) {
5fd86fcf 3064 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3065 return 1;
3066 }
3067
7aa81cc0 3068 if (is_invalid_opcode(intr_info)) {
51d8b661 3069 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3070 if (er != EMULATE_DONE)
7ee5d940 3071 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3072 return 1;
3073 }
3074
6aa8b732 3075 error_code = 0;
5fdbf976 3076 rip = kvm_rip_read(vcpu);
2e11384c 3077 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3078 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3079 if (is_page_fault(intr_info)) {
1439442c 3080 /* EPT won't cause page fault directly */
089d034e 3081 if (enable_ept)
1439442c 3082 BUG();
6aa8b732 3083 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3084 trace_kvm_page_fault(cr2, error_code);
3085
3298b75c 3086 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3087 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3088 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3089 }
3090
7ffd92c5 3091 if (vmx->rmode.vm86_active &&
6aa8b732 3092 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3093 error_code)) {
ad312c7c
ZX		 3094 if (vcpu->arch.halt_request) {
3095 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3096 return kvm_emulate_halt(vcpu);
3097 }
6aa8b732 3098 return 1;
72d6e5a0 3099 }
6aa8b732 3100
d0bfb940 3101 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3102 switch (ex_no) {
3103 case DB_VECTOR:
3104 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3105 if (!(vcpu->guest_debug &
3106 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3107 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3108 kvm_queue_exception(vcpu, DB_VECTOR);
3109 return 1;
3110 }
3111 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3112 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3113 /* fall through */
3114 case BP_VECTOR:
c573cd22
JK		 3115 /*
3116 * Update instruction length as we may reinject #BP from
3117 * user space while in guest debugging mode. Reading it for
3118 * #DB as well causes no harm, it is not used in that case.
3119 */
3120 vmx->vcpu.arch.event_exit_inst_len =
3121 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3122 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3123 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3124 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3125 break;
3126 default:
d0bfb940
JK		 3127 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3128 kvm_run->ex.exception = ex_no;
3129 kvm_run->ex.error_code = error_code;
42dbaa5a 3130 break;
6aa8b732 3131 }
6aa8b732
AK		 3132 return 0;
3133}
3134
851ba692 3135static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3136{
1165f5fe 3137 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3138 return 1;
3139}
3140
851ba692 3141static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3142{
851ba692 3143 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3144 return 0;
3145}
6aa8b732 3146
851ba692 3147static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3148{
bfdaab09 3149 unsigned long exit_qualification;
34c33d16 3150 int size, in, string;
039576c0 3151 unsigned port;
6aa8b732 3152
bfdaab09 3153 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3154 string = (exit_qualification & 16) != 0;
cf8f70bf 3155 in = (exit_qualification & 8) != 0;
e70669ab 3156
cf8f70bf 3157 ++vcpu->stat.io_exits;
e70669ab 3158
cf8f70bf 3159 if (string || in)
51d8b661 3160 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3161
cf8f70bf
GN		 3162 port = exit_qualification >> 16;
3163 size = (exit_qualification & 7) + 1;
e93f36bc 3164 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3165
3166 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3167}
3168
102d8325
IM		 3169static void
3170vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3171{
3172 /*
3173 * Patch in the VMCALL instruction:
3174 */
3175 hypercall[0] = 0x0f;
3176 hypercall[1] = 0x01;
3177 hypercall[2] = 0xc1;
102d8325
IM		 3178}
3179
851ba692 3180static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3181{
229456fc 3182 unsigned long exit_qualification, val;
6aa8b732
AK		 3183 int cr;
3184 int reg;
49a9b07e 3185 int err;
6aa8b732 3186
bfdaab09 3187 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3188 cr = exit_qualification & 15;
3189 reg = (exit_qualification >> 8) & 15;
3190 switch ((exit_qualification >> 4) & 3) {
3191 case 0: /* mov to cr */
229456fc
MT		 3192 val = kvm_register_read(vcpu, reg);
3193 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3194 switch (cr) {
3195 case 0:
49a9b07e 3196 err = kvm_set_cr0(vcpu, val);
db8fcefa 3197 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3198 return 1;
3199 case 3:
2390218b 3200 err = kvm_set_cr3(vcpu, val);
db8fcefa 3201 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3202 return 1;
3203 case 4:
a83b29c6 3204 err = kvm_set_cr4(vcpu, val);
db8fcefa 3205 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3206 return 1;
0a5fff19
GN		 3207 case 8: {
3208 u8 cr8_prev = kvm_get_cr8(vcpu);
3209 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3210 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3211 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3212 if (irqchip_in_kernel(vcpu->kvm))
3213 return 1;
3214 if (cr8_prev <= cr8)
3215 return 1;
851ba692 3216 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3217 return 0;
3218 }
6aa8b732
AK		 3219 };
3220 break;
25c4c276 3221 case 2: /* clts */
edcafe3c 3222 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3223 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3224 skip_emulated_instruction(vcpu);
6b52d186 3225 vmx_fpu_activate(vcpu);
25c4c276 3226 return 1;
6aa8b732
AK		 3227 case 1: /*mov from cr*/
3228 switch (cr) {
3229 case 3:
9f8fe504
AK		 3230 val = kvm_read_cr3(vcpu);
3231 kvm_register_write(vcpu, reg, val);
3232 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3233 skip_emulated_instruction(vcpu);
3234 return 1;
3235 case 8:
229456fc
MT		 3236 val = kvm_get_cr8(vcpu);
3237 kvm_register_write(vcpu, reg, val);
3238 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3239 skip_emulated_instruction(vcpu);
3240 return 1;
3241 }
3242 break;
3243 case 3: /* lmsw */
a1f83a74 3244 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3245 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3246 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3247
3248 skip_emulated_instruction(vcpu);
3249 return 1;
3250 default:
3251 break;
3252 }
851ba692 3253 vcpu->run->exit_reason = 0;
f0242478 3254 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3255 (int)(exit_qualification >> 4) & 3, cr);
3256 return 0;
3257}
3258
851ba692 3259static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3260{
bfdaab09 3261 unsigned long exit_qualification;
6aa8b732
AK		 3262 int dr, reg;
3263
f2483415 3264 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3265 if (!kvm_require_cpl(vcpu, 0))
3266 return 1;
42dbaa5a
JK		 3267 dr = vmcs_readl(GUEST_DR7);
3268 if (dr & DR7_GD) {
3269 /*
3270 * As the vm-exit takes precedence over the debug trap, we
3271 * need to emulate the latter, either for the host or the
3272 * guest debugging itself.
3273 */
3274 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3275 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3276 vcpu->run->debug.arch.dr7 = dr;
3277 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3278 vmcs_readl(GUEST_CS_BASE) +
3279 vmcs_readl(GUEST_RIP);
851ba692
AK		 3280 vcpu->run->debug.arch.exception = DB_VECTOR;
3281 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3282 return 0;
3283 } else {
3284 vcpu->arch.dr7 &= ~DR7_GD;
3285 vcpu->arch.dr6 |= DR6_BD;
3286 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3287 kvm_queue_exception(vcpu, DB_VECTOR);
3288 return 1;
3289 }
3290 }
3291
bfdaab09 3292 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3293 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3294 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3295 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3296 unsigned long val;
3297 if (!kvm_get_dr(vcpu, dr, &val))
3298 kvm_register_write(vcpu, reg, val);
3299 } else
3300 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3301 skip_emulated_instruction(vcpu);
3302 return 1;
3303}
3304
020df079
GN		 3305static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3306{
3307 vmcs_writel(GUEST_DR7, val);
3308}
3309
851ba692 3310static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3311{
06465c5a
AK		 3312 kvm_emulate_cpuid(vcpu);
3313 return 1;
6aa8b732
AK		 3314}
3315
851ba692 3316static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3317{
ad312c7c 3318 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3319 u64 data;
3320
3321 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3322 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3323 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3324 return 1;
3325 }
3326
229456fc 3327 trace_kvm_msr_read(ecx, data);
2714d1d3 3328
6aa8b732 3329 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3330 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3331 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3332 skip_emulated_instruction(vcpu);
3333 return 1;
3334}
3335
851ba692 3336static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3337{
ad312c7c
ZX		 3338 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3339 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3340 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3341
3342 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3343 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3344 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3345 return 1;
3346 }
3347
59200273 3348 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3349 skip_emulated_instruction(vcpu);
3350 return 1;
3351}
3352
851ba692 3353static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3354{
3842d135 3355 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3356 return 1;
3357}
3358
851ba692 3359static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3360{
85f455f7
ED		 3361 u32 cpu_based_vm_exec_control;
3362
3363 /* clear pending irq */
3364 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3365 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3366 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3367
3842d135
AK		 3368 kvm_make_request(KVM_REQ_EVENT, vcpu);
3369
a26bf12a 3370 ++vcpu->stat.irq_window_exits;
2714d1d3 3371
c1150d8c
DL		 3372 /*
3373 * If the user space waits to inject interrupts, exit as soon as
3374 * possible
3375 */
8061823a 3376 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3377 vcpu->run->request_interrupt_window &&
8061823a 3378 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3379 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3380 return 0;
3381 }
6aa8b732
AK		 3382 return 1;
3383}
3384
851ba692 3385static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3386{
3387 skip_emulated_instruction(vcpu);
d3bef15f 3388 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3389}
3390
851ba692 3391static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3392{
510043da 3393 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3394 kvm_emulate_hypercall(vcpu);
3395 return 1;
c21415e8
IM		 3396}
3397
851ba692 3398static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3399{
3400 kvm_queue_exception(vcpu, UD_VECTOR);
3401 return 1;
3402}
3403
ec25d5e6
GN		 3404static int handle_invd(struct kvm_vcpu *vcpu)
3405{
51d8b661 3406 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3407}
3408
851ba692 3409static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3410{
f9c617f6 3411 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3412
3413 kvm_mmu_invlpg(vcpu, exit_qualification);
3414 skip_emulated_instruction(vcpu);
3415 return 1;
3416}
3417
851ba692 3418static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3419{
3420 skip_emulated_instruction(vcpu);
f5f48ee1 3421 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3422 return 1;
3423}
3424
2acf923e
DC		 3425static int handle_xsetbv(struct kvm_vcpu *vcpu)
3426{
3427 u64 new_bv = kvm_read_edx_eax(vcpu);
3428 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3429
3430 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3431 skip_emulated_instruction(vcpu);
3432 return 1;
3433}
3434
851ba692 3435static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3436{
51d8b661 3437 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3438}
3439
851ba692 3440static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3441{
60637aac 3442 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3443 unsigned long exit_qualification;
e269fb21
JK		 3444 bool has_error_code = false;
3445 u32 error_code = 0;
37817f29 3446 u16 tss_selector;
64a7ec06
GN		 3447 int reason, type, idt_v;
3448
3449 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3450 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3451
3452 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3453
3454 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3455 if (reason == TASK_SWITCH_GATE && idt_v) {
3456 switch (type) {
3457 case INTR_TYPE_NMI_INTR:
3458 vcpu->arch.nmi_injected = false;
3459 if (cpu_has_virtual_nmis())
3460 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3461 GUEST_INTR_STATE_NMI);
3462 break;
3463 case INTR_TYPE_EXT_INTR:
66fd3f7f 3464 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3465 kvm_clear_interrupt_queue(vcpu);
3466 break;
3467 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3468 if (vmx->idt_vectoring_info &
3469 VECTORING_INFO_DELIVER_CODE_MASK) {
3470 has_error_code = true;
3471 error_code =
3472 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3473 }
3474 /* fall through */
64a7ec06
GN		 3475 case INTR_TYPE_SOFT_EXCEPTION:
3476 kvm_clear_exception_queue(vcpu);
3477 break;
3478 default:
3479 break;
3480 }
60637aac 3481 }
37817f29
IE		 3482 tss_selector = exit_qualification;
3483
64a7ec06
GN		 3484 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3485 type != INTR_TYPE_EXT_INTR &&
3486 type != INTR_TYPE_NMI_INTR))
3487 skip_emulated_instruction(vcpu);
3488
acb54517
GN		 3489 if (kvm_task_switch(vcpu, tss_selector, reason,
3490 has_error_code, error_code) == EMULATE_FAIL) {
3491 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3492 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3493 vcpu->run->internal.ndata = 0;
42dbaa5a 3494 return 0;
acb54517 3495 }
42dbaa5a
JK		 3496
3497 /* clear all local breakpoint enable flags */
3498 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3499
3500 /*
3501 * TODO: What about debug traps on tss switch?
3502 * Are we supposed to inject them and update dr6?
3503 */
3504
3505 return 1;
37817f29
IE		 3506}
3507
851ba692 3508static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3509{
f9c617f6 3510 unsigned long exit_qualification;
1439442c 3511 gpa_t gpa;
1439442c 3512 int gla_validity;
1439442c 3513
f9c617f6 3514 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3515
3516 if (exit_qualification & (1 << 6)) {
3517 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3518 return -EINVAL;
1439442c
SY		 3519 }
3520
3521 gla_validity = (exit_qualification >> 7) & 0x3;
3522 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3523 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3524 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3525 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3526 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3527 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3528 (long unsigned int)exit_qualification);
851ba692
AK		 3529 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3530 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3531 return 0;
1439442c
SY		 3532 }
3533
3534 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3535 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3536 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3537}
3538
68f89400
MT		 3539static u64 ept_rsvd_mask(u64 spte, int level)
3540{
3541 int i;
3542 u64 mask = 0;
3543
3544 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3545 mask |= (1ULL << i);
3546
3547 if (level > 2)
3548 /* bits 7:3 reserved */
3549 mask |= 0xf8;
3550 else if (level == 2) {
3551 if (spte & (1ULL << 7))
3552 /* 2MB ref, bits 20:12 reserved */
3553 mask |= 0x1ff000;
3554 else
3555 /* bits 6:3 reserved */
3556 mask |= 0x78;
3557 }
3558
3559 return mask;
3560}
3561
3562static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3563 int level)
3564{
3565 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3566
3567 /* 010b (write-only) */
3568 WARN_ON((spte & 0x7) == 0x2);
3569
3570 /* 110b (write/execute) */
3571 WARN_ON((spte & 0x7) == 0x6);
3572
3573 /* 100b (execute-only) and value not supported by logical processor */
3574 if (!cpu_has_vmx_ept_execute_only())
3575 WARN_ON((spte & 0x7) == 0x4);
3576
3577 /* not 000b */
3578 if ((spte & 0x7)) {
3579 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3580
3581 if (rsvd_bits != 0) {
3582 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3583 __func__, rsvd_bits);
3584 WARN_ON(1);
3585 }
3586
3587 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3588 u64 ept_mem_type = (spte & 0x38) >> 3;
3589
3590 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3591 ept_mem_type == 7) {
3592 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3593 __func__, ept_mem_type);
3594 WARN_ON(1);
3595 }
3596 }
3597 }
3598}
3599
851ba692 3600static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3601{
3602 u64 sptes[4];
3603 int nr_sptes, i;
3604 gpa_t gpa;
3605
3606 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3607
3608 printk(KERN_ERR "EPT: Misconfiguration.\n");
3609 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3610
3611 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3612
3613 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3614 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3615
851ba692
AK		 3616 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3617 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3618
3619 return 0;
3620}
3621
851ba692 3622static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3623{
3624 u32 cpu_based_vm_exec_control;
3625
3626 /* clear pending NMI */
3627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3628 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3630 ++vcpu->stat.nmi_window_exits;
3842d135 3631 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3632
3633 return 1;
3634}
3635
80ced186 3636static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3637{
8b3079a5
AK		 3638 struct vcpu_vmx *vmx = to_vmx(vcpu);
3639 enum emulation_result err = EMULATE_DONE;
80ced186 3640 int ret = 1;
49e9d557
AK		 3641 u32 cpu_exec_ctrl;
3642 bool intr_window_requested;
3643
3644 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3645 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3646
3647 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3648 if (intr_window_requested
3649 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3650 return handle_interrupt_window(&vmx->vcpu);
3651
51d8b661 3652 err = emulate_instruction(vcpu, 0);
ea953ef0 3653
80ced186
MG		 3654 if (err == EMULATE_DO_MMIO) {
3655 ret = 0;
3656 goto out;
3657 }
1d5a4d9b 3658
6d77dbfc
GN		 3659 if (err != EMULATE_DONE)
3660 return 0;
ea953ef0
MG		 3661
3662 if (signal_pending(current))
80ced186 3663 goto out;
ea953ef0
MG		 3664 if (need_resched())
3665 schedule();
3666 }
3667
80ced186
MG		 3668 vmx->emulation_required = 0;
3669out:
3670 return ret;
ea953ef0
MG		 3671}
3672
4b8d54f9
ZE		 3673/*
3674 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3675 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3676 */
9fb41ba8 3677static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3678{
3679 skip_emulated_instruction(vcpu);
3680 kvm_vcpu_on_spin(vcpu);
3681
3682 return 1;
3683}
3684
59708670
SY		 3685static int handle_invalid_op(struct kvm_vcpu *vcpu)
3686{
3687 kvm_queue_exception(vcpu, UD_VECTOR);
3688 return 1;
3689}
3690
6aa8b732
AK		 3691/*
3692 * The exit handlers return 1 if the exit was handled fully and guest execution
3693 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3694 * to be done to userspace and return 0.
3695 */
851ba692 3696static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3697 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3698 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3699 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3700 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3701 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3702 [EXIT_REASON_CR_ACCESS] = handle_cr,
3703 [EXIT_REASON_DR_ACCESS] = handle_dr,
3704 [EXIT_REASON_CPUID] = handle_cpuid,
3705 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3706 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3707 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3708 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3709 [EXIT_REASON_INVD] = handle_invd,
a7052897 3710 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3711 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3712 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3713 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3714 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3715 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3716 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3717 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3718 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3719 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3720 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3721 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3722 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3723 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3724 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3725 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3726 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3727 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3728 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3729 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3730 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3731 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3732};
3733
3734static const int kvm_vmx_max_exit_handlers =
50a3485c 3735 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3736
586f9607
AK		 3737static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3738{
3739 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3740 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3741}
3742
6aa8b732
AK		 3743/*
3744 * The guest has exited. See if we can fix it or if we need userspace
3745 * assistance.
3746 */
851ba692 3747static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3748{
29bd8a78 3749 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3750 u32 exit_reason = vmx->exit_reason;
1155f76a 3751 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3752
aa17911e 3753 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3754
80ced186
MG		 3755 /* If guest state is invalid, start emulating */
3756 if (vmx->emulation_required && emulate_invalid_guest_state)
3757 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3758
1439442c
SY		 3759 /* Access CR3 don't cause VMExit in paging mode, so we need
3760 * to sync with guest real CR3. */
6de4f3ad 3761 if (enable_ept && is_paging(vcpu))
1439442c 3762 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3763
5120702e
MG		 3764 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3765 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3766 vcpu->run->fail_entry.hardware_entry_failure_reason
3767 = exit_reason;
3768 return 0;
3769 }
3770
29bd8a78 3771 if (unlikely(vmx->fail)) {
851ba692
AK		 3772 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3773 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3774 = vmcs_read32(VM_INSTRUCTION_ERROR);
3775 return 0;
3776 }
6aa8b732 3777
d77c26fc 3778 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3779 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3780 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3781 exit_reason != EXIT_REASON_TASK_SWITCH))
3782 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3783 "(0x%x) and exit reason is 0x%x\n",
3784 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3785
3786 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3787 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3788 vmx->soft_vnmi_blocked = 0;
3b86cd99 3789 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3790 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3791 /*
3792 * This CPU don't support us in finding the end of an
3793 * NMI-blocked window if the guest runs with IRQs
3794 * disabled. So we pull the trigger after 1 s of
3795 * futile waiting, but inform the user about this.
3796 */
3797 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3798 "state on VCPU %d after 1 s timeout\n",
3799 __func__, vcpu->vcpu_id);
3800 vmx->soft_vnmi_blocked = 0;
3b86cd99 3801 }
3b86cd99
JK		 3802 }
3803
6aa8b732
AK		 3804 if (exit_reason < kvm_vmx_max_exit_handlers
3805 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3806 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3807 else {
851ba692
AK		 3808 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3809 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3810 }
3811 return 0;
3812}
3813
95ba8273 3814static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3815{
95ba8273 3816 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3817 vmcs_write32(TPR_THRESHOLD, 0);
3818 return;
3819 }
3820
95ba8273 3821 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3822}
3823
51aa01d1 3824static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3825{
51aa01d1 3826 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3827
3828 /* Handle machine checks before interrupts are enabled */
3829 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3830 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3831 && is_machine_check(exit_intr_info)))
3832 kvm_machine_check();
3833
20f65983
GN		 3834 /* We need to handle NMIs before interrupts are enabled */
3835 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3836 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3837 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3838 asm("int $2");
ff9d07a0
ZY		 3839 kvm_after_handle_nmi(&vmx->vcpu);
3840 }
51aa01d1 3841}
20f65983 3842
51aa01d1
AK		 3843static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3844{
3845 u32 exit_intr_info = vmx->exit_intr_info;
3846 bool unblock_nmi;
3847 u8 vector;
3848 bool idtv_info_valid;
3849
3850 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3851
cf393f75
AK		 3852 if (cpu_has_virtual_nmis()) {
3853 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3854 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3855 /*
7b4a25cb 3856 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3857 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3858 * a guest IRET fault.
7b4a25cb
GN		 3859 * SDM 3: 23.2.2 (September 2008)
3860 * Bit 12 is undefined in any of the following cases:
3861 * If the VM exit sets the valid bit in the IDT-vectoring
3862 * information field.
3863 * If the VM exit is due to a double fault.
cf393f75 3864 */
7b4a25cb
GN		 3865 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3866 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3867 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3868 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3869 } else if (unlikely(vmx->soft_vnmi_blocked))
3870 vmx->vnmi_blocked_time +=
3871 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3872}
3873
83422e17
AK		 3874static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3875 u32 idt_vectoring_info,
3876 int instr_len_field,
3877 int error_code_field)
51aa01d1 3878{
51aa01d1
AK		 3879 u8 vector;
3880 int type;
3881 bool idtv_info_valid;
3882
3883 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3884
37b96e98
GN		 3885 vmx->vcpu.arch.nmi_injected = false;
3886 kvm_clear_exception_queue(&vmx->vcpu);
3887 kvm_clear_interrupt_queue(&vmx->vcpu);
3888
3889 if (!idtv_info_valid)
3890 return;
3891
3842d135
AK		 3892 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3893
668f612f
AK		 3894 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3895 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3896
64a7ec06 3897 switch (type) {
37b96e98
GN		 3898 case INTR_TYPE_NMI_INTR:
3899 vmx->vcpu.arch.nmi_injected = true;
668f612f 3900 /*
7b4a25cb 3901 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3902 * Clear bit "block by NMI" before VM entry if a NMI
3903 * delivery faulted.
668f612f 3904 */
37b96e98
GN		 3905 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3906 GUEST_INTR_STATE_NMI);
3907 break;
37b96e98 3908 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3909 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3910 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3911 /* fall through */
3912 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3913 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3914 u32 err = vmcs_read32(error_code_field);
37b96e98 3915 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3916 } else
3917 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3918 break;
66fd3f7f
GN		 3919 case INTR_TYPE_SOFT_INTR:
3920 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3921 vmcs_read32(instr_len_field);
66fd3f7f 3922 /* fall through */
37b96e98 3923 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3924 kvm_queue_interrupt(&vmx->vcpu, vector,
3925 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3926 break;
3927 default:
3928 break;
f7d9238f 3929 }
cf393f75
AK		 3930}
3931
83422e17
AK		 3932static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3933{
3934 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3935 VM_EXIT_INSTRUCTION_LEN,
3936 IDT_VECTORING_ERROR_CODE);
3937}
3938
b463a6f7
AK		 3939static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3940{
3941 __vmx_complete_interrupts(to_vmx(vcpu),
3942 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3943 VM_ENTRY_INSTRUCTION_LEN,
3944 VM_ENTRY_EXCEPTION_ERROR_CODE);
3945
3946 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3947}
3948
c801949d
AK		 3949#ifdef CONFIG_X86_64
3950#define R "r"
3951#define Q "q"
3952#else
3953#define R "e"
3954#define Q "l"
3955#endif
3956
104f226b 3957static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3958{
a2fa3e9f 3959 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 3960
3961 /* Record the guest's net vcpu time for enforced NMI injections. */
3962 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3963 vmx->entry_time = ktime_get();
3964
3965 /* Don't enter VMX if guest state is invalid, let the exit handler
3966 start emulation until we arrive back to a valid state */
3967 if (vmx->emulation_required && emulate_invalid_guest_state)
3968 return;
3969
3970 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3971 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3972 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3973 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3974
3975 /* When single-stepping over STI and MOV SS, we must clear the
3976 * corresponding interruptibility bits in the guest state. Otherwise
3977 * vmentry fails as it then expects bit 14 (BS) in pending debug
3978 * exceptions being set, but that's not correct for the guest debugging
3979 * case. */
3980 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3981 vmx_set_interrupt_shadow(vcpu, 0);
3982
3983 asm(
6aa8b732 3984 /* Store host registers */
c801949d
AK		 3985 "push %%"R"dx; push %%"R"bp;"
3986 "push %%"R"cx \n\t"
313dbd49
AK		 3987 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3988 "je 1f \n\t"
3989 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3990 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3991 "1: \n\t"
d3edefc0
AK		 3992 /* Reload cr2 if changed */
3993 "mov %c[cr2](%0), %%"R"ax \n\t"
3994 "mov %%cr2, %%"R"dx \n\t"
3995 "cmp %%"R"ax, %%"R"dx \n\t"
3996 "je 2f \n\t"
3997 "mov %%"R"ax, %%cr2 \n\t"
3998 "2: \n\t"
6aa8b732 3999 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4000 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4001 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4002 "mov %c[rax](%0), %%"R"ax \n\t"
4003 "mov %c[rbx](%0), %%"R"bx \n\t"
4004 "mov %c[rdx](%0), %%"R"dx \n\t"
4005 "mov %c[rsi](%0), %%"R"si \n\t"
4006 "mov %c[rdi](%0), %%"R"di \n\t"
4007 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4008#ifdef CONFIG_X86_64
e08aa78a
AK		 4009 "mov %c[r8](%0), %%r8 \n\t"
4010 "mov %c[r9](%0), %%r9 \n\t"
4011 "mov %c[r10](%0), %%r10 \n\t"
4012 "mov %c[r11](%0), %%r11 \n\t"
4013 "mov %c[r12](%0), %%r12 \n\t"
4014 "mov %c[r13](%0), %%r13 \n\t"
4015 "mov %c[r14](%0), %%r14 \n\t"
4016 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4017#endif
c801949d
AK		 4018 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4019
6aa8b732 4020 /* Enter guest mode */
cd2276a7 4021 "jne .Llaunched \n\t"
4ecac3fd 4022 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4023 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4024 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4025 ".Lkvm_vmx_return: "
6aa8b732 4026 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 4027 "xchg %0, (%%"R"sp) \n\t"
4028 "mov %%"R"ax, %c[rax](%0) \n\t"
4029 "mov %%"R"bx, %c[rbx](%0) \n\t"
4030 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4031 "mov %%"R"dx, %c[rdx](%0) \n\t"
4032 "mov %%"R"si, %c[rsi](%0) \n\t"
4033 "mov %%"R"di, %c[rdi](%0) \n\t"
4034 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4035#ifdef CONFIG_X86_64
e08aa78a
AK		 4036 "mov %%r8, %c[r8](%0) \n\t"
4037 "mov %%r9, %c[r9](%0) \n\t"
4038 "mov %%r10, %c[r10](%0) \n\t"
4039 "mov %%r11, %c[r11](%0) \n\t"
4040 "mov %%r12, %c[r12](%0) \n\t"
4041 "mov %%r13, %c[r13](%0) \n\t"
4042 "mov %%r14, %c[r14](%0) \n\t"
4043 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4044#endif
c801949d
AK		 4045 "mov %%cr2, %%"R"ax \n\t"
4046 "mov %%"R"ax, %c[cr2](%0) \n\t"
4047
4048 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4049 "setbe %c[fail](%0) \n\t"
4050 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4051 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4052 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4053 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4054 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4055 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4056 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4057 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4058 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4059 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4060 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4061#ifdef CONFIG_X86_64
ad312c7c
ZX		 4062 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4063 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4064 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4065 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4066 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4067 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4068 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4069 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4070#endif
ad312c7c 4071 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4072 : "cc", "memory"
07d6f555 4073 , R"ax", R"bx", R"di", R"si"
c2036300 4074#ifdef CONFIG_X86_64
c2036300
LV		 4075 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4076#endif
4077 );
6aa8b732 4078
6de4f3ad
AK		 4079 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4080 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4081 vcpu->arch.regs_dirty = 0;
4082
1155f76a
AK		 4083 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4084
d77c26fc 4085 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4086 vmx->launched = 1;
1b6269db 4087
51aa01d1
AK		 4088 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4089 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4090
4091 vmx_complete_atomic_exit(vmx);
4092 vmx_recover_nmi_blocking(vmx);
cf393f75 4093 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4094}
4095
c801949d
AK		 4096#undef R
4097#undef Q
4098
6aa8b732
AK		 4099static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4100{
a2fa3e9f
GH		 4101 struct vcpu_vmx *vmx = to_vmx(vcpu);
4102
4103 if (vmx->vmcs) {
543e4243 4104 vcpu_clear(vmx);
a2fa3e9f
GH		 4105 free_vmcs(vmx->vmcs);
4106 vmx->vmcs = NULL;
6aa8b732
AK		 4107 }
4108}
4109
4110static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4111{
fb3f0f51
RR		 4112 struct vcpu_vmx *vmx = to_vmx(vcpu);
4113
cdbecfc3 4114 free_vpid(vmx);
6aa8b732 4115 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4116 kfree(vmx->guest_msrs);
4117 kvm_vcpu_uninit(vcpu);
a4770347 4118 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4119}
4120
4610c9cc
DX		 4121static inline void vmcs_init(struct vmcs *vmcs)
4122{
4123 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4124
4125 if (!vmm_exclusive)
4126 kvm_cpu_vmxon(phys_addr);
4127
4128 vmcs_clear(vmcs);
4129
4130 if (!vmm_exclusive)
4131 kvm_cpu_vmxoff();
4132}
4133
fb3f0f51 4134static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4135{
fb3f0f51 4136 int err;
c16f862d 4137 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4138 int cpu;
6aa8b732 4139
a2fa3e9f 4140 if (!vmx)
fb3f0f51
RR		 4141 return ERR_PTR(-ENOMEM);
4142
2384d2b3
SY		 4143 allocate_vpid(vmx);
4144
fb3f0f51
RR		 4145 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4146 if (err)
4147 goto free_vcpu;
965b58a5 4148
a2fa3e9f 4149 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4150 if (!vmx->guest_msrs) {
4151 err = -ENOMEM;
4152 goto uninit_vcpu;
4153 }
965b58a5 4154
a2fa3e9f
GH		 4155 vmx->vmcs = alloc_vmcs();
4156 if (!vmx->vmcs)
fb3f0f51 4157 goto free_msrs;
a2fa3e9f 4158
4610c9cc 4159 vmcs_init(vmx->vmcs);
a2fa3e9f 4160
15ad7146
AK		 4161 cpu = get_cpu();
4162 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4163 vmx->vcpu.cpu = cpu;
8b9cf98c 4164 err = vmx_vcpu_setup(vmx);
fb3f0f51 4165 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4166 put_cpu();
fb3f0f51
RR		 4167 if (err)
4168 goto free_vmcs;
5e4a0b3c
MT		 4169 if (vm_need_virtualize_apic_accesses(kvm))
4170 if (alloc_apic_access_page(kvm) != 0)
4171 goto free_vmcs;
fb3f0f51 4172
b927a3ce
SY		 4173 if (enable_ept) {
4174 if (!kvm->arch.ept_identity_map_addr)
4175 kvm->arch.ept_identity_map_addr =
4176 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4177 if (alloc_identity_pagetable(kvm) != 0)
4178 goto free_vmcs;
b927a3ce 4179 }
b7ebfb05 4180
fb3f0f51
RR		 4181 return &vmx->vcpu;
4182
4183free_vmcs:
4184 free_vmcs(vmx->vmcs);
4185free_msrs:
fb3f0f51
RR		 4186 kfree(vmx->guest_msrs);
4187uninit_vcpu:
4188 kvm_vcpu_uninit(&vmx->vcpu);
4189free_vcpu:
cdbecfc3 4190 free_vpid(vmx);
a4770347 4191 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4192 return ERR_PTR(err);
6aa8b732
AK		 4193}
4194
002c7f7c
YS		 4195static void __init vmx_check_processor_compat(void *rtn)
4196{
4197 struct vmcs_config vmcs_conf;
4198
4199 *(int *)rtn = 0;
4200 if (setup_vmcs_config(&vmcs_conf) < 0)
4201 *(int *)rtn = -EIO;
4202 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4203 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4204 smp_processor_id());
4205 *(int *)rtn = -EIO;
4206 }
4207}
4208
67253af5
SY		 4209static int get_ept_level(void)
4210{
4211 return VMX_EPT_DEFAULT_GAW + 1;
4212}
4213
4b12f0de 4214static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4215{
4b12f0de
SY		 4216 u64 ret;
4217
522c68c4
SY		 4218 /* For VT-d and EPT combination
4219 * 1. MMIO: always map as UC
4220 * 2. EPT with VT-d:
4221 * a. VT-d without snooping control feature: can't guarantee the
4222 * result, try to trust guest.
4223 * b. VT-d with snooping control feature: snooping control feature of
4224 * VT-d engine can guarantee the cache correctness. Just set it
4225 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4226 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4227 * consistent with host MTRR
4228 */
4b12f0de
SY		 4229 if (is_mmio)
4230 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4231 else if (vcpu->kvm->arch.iommu_domain &&
4232 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4233 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4234 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4235 else
522c68c4 4236 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4237 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4238
4239 return ret;
64d4d521
SY		 4240}
4241
f4c9e87c
AK		 4242#define _ER(x) { EXIT_REASON_##x, #x }
4243
229456fc 4244static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4245 _ER(EXCEPTION_NMI),
4246 _ER(EXTERNAL_INTERRUPT),
4247 _ER(TRIPLE_FAULT),
4248 _ER(PENDING_INTERRUPT),
4249 _ER(NMI_WINDOW),
4250 _ER(TASK_SWITCH),
4251 _ER(CPUID),
4252 _ER(HLT),
4253 _ER(INVLPG),
4254 _ER(RDPMC),
4255 _ER(RDTSC),
4256 _ER(VMCALL),
4257 _ER(VMCLEAR),
4258 _ER(VMLAUNCH),
4259 _ER(VMPTRLD),
4260 _ER(VMPTRST),
4261 _ER(VMREAD),
4262 _ER(VMRESUME),
4263 _ER(VMWRITE),
4264 _ER(VMOFF),
4265 _ER(VMON),
4266 _ER(CR_ACCESS),
4267 _ER(DR_ACCESS),
4268 _ER(IO_INSTRUCTION),
4269 _ER(MSR_READ),
4270 _ER(MSR_WRITE),
4271 _ER(MWAIT_INSTRUCTION),
4272 _ER(MONITOR_INSTRUCTION),
4273 _ER(PAUSE_INSTRUCTION),
4274 _ER(MCE_DURING_VMENTRY),
4275 _ER(TPR_BELOW_THRESHOLD),
4276 _ER(APIC_ACCESS),
4277 _ER(EPT_VIOLATION),
4278 _ER(EPT_MISCONFIG),
4279 _ER(WBINVD),
229456fc
MT		 4280 { -1, NULL }
4281};
4282
f4c9e87c
AK		 4283#undef _ER
4284
17cc3935 4285static int vmx_get_lpage_level(void)
344f414f 4286{
878403b7
SY		 4287 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4288 return PT_DIRECTORY_LEVEL;
4289 else
4290 /* For shadow and EPT supported 1GB page */
4291 return PT_PDPE_LEVEL;
344f414f
JR		 4292}
4293
0e851880
SY		 4294static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4295{
4e47c7a6
SY		 4296 struct kvm_cpuid_entry2 *best;
4297 struct vcpu_vmx *vmx = to_vmx(vcpu);
4298 u32 exec_control;
4299
4300 vmx->rdtscp_enabled = false;
4301 if (vmx_rdtscp_supported()) {
4302 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4303 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4304 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4305 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4306 vmx->rdtscp_enabled = true;
4307 else {
4308 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4309 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4310 exec_control);
4311 }
4312 }
4313 }
0e851880
SY		 4314}
4315
d4330ef2
JR		 4316static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4317{
4318}
4319
cbdd1bea 4320static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4321 .cpu_has_kvm_support = cpu_has_kvm_support,
4322 .disabled_by_bios = vmx_disabled_by_bios,
4323 .hardware_setup = hardware_setup,
4324 .hardware_unsetup = hardware_unsetup,
002c7f7c 4325 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4326 .hardware_enable = hardware_enable,
4327 .hardware_disable = hardware_disable,
04547156 4328 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4329
4330 .vcpu_create = vmx_create_vcpu,
4331 .vcpu_free = vmx_free_vcpu,
04d2cc77 4332 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4333
04d2cc77 4334 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4335 .vcpu_load = vmx_vcpu_load,
4336 .vcpu_put = vmx_vcpu_put,
4337
4338 .set_guest_debug = set_guest_debug,
4339 .get_msr = vmx_get_msr,
4340 .set_msr = vmx_set_msr,
4341 .get_segment_base = vmx_get_segment_base,
4342 .get_segment = vmx_get_segment,
4343 .set_segment = vmx_set_segment,
2e4d2653 4344 .get_cpl = vmx_get_cpl,
6aa8b732 4345 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4346 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4347 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4348 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4349 .set_cr3 = vmx_set_cr3,
4350 .set_cr4 = vmx_set_cr4,
6aa8b732 4351 .set_efer = vmx_set_efer,
6aa8b732
AK		 4352 .get_idt = vmx_get_idt,
4353 .set_idt = vmx_set_idt,
4354 .get_gdt = vmx_get_gdt,
4355 .set_gdt = vmx_set_gdt,
020df079 4356 .set_dr7 = vmx_set_dr7,
5fdbf976 4357 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4358 .get_rflags = vmx_get_rflags,
4359 .set_rflags = vmx_set_rflags,
ebcbab4c 4360 .fpu_activate = vmx_fpu_activate,
02daab21 4361 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4362
4363 .tlb_flush = vmx_flush_tlb,
6aa8b732 4364
6aa8b732 4365 .run = vmx_vcpu_run,
6062d012 4366 .handle_exit = vmx_handle_exit,
6aa8b732 4367 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4368 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4369 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4370 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4371 .set_irq = vmx_inject_irq,
95ba8273 4372 .set_nmi = vmx_inject_nmi,
298101da 4373 .queue_exception = vmx_queue_exception,
b463a6f7 4374 .cancel_injection = vmx_cancel_injection,
78646121 4375 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4376 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4377 .get_nmi_mask = vmx_get_nmi_mask,
4378 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4379 .enable_nmi_window = enable_nmi_window,
4380 .enable_irq_window = enable_irq_window,
4381 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4382
cbc94022 4383 .set_tss_addr = vmx_set_tss_addr,
67253af5 4384 .get_tdp_level = get_ept_level,
4b12f0de 4385 .get_mt_mask = vmx_get_mt_mask,
229456fc 4386
586f9607 4387 .get_exit_info = vmx_get_exit_info,
229456fc 4388 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4389
17cc3935 4390 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4391
4392 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4393
4394 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4395
4396 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4397
4398 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4399
4400 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4401 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4402
4403 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4404};
4405
4406static int __init vmx_init(void)
4407{
26bb0981
AK		 4408 int r, i;
4409
4410 rdmsrl_safe(MSR_EFER, &host_efer);
4411
4412 for (i = 0; i < NR_VMX_MSR; ++i)
4413 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4414
3e7c73e9 4415 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4416 if (!vmx_io_bitmap_a)
4417 return -ENOMEM;
4418
3e7c73e9 4419 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4420 if (!vmx_io_bitmap_b) {
4421 r = -ENOMEM;
4422 goto out;
4423 }
4424
5897297b
AK		 4425 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4426 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4427 r = -ENOMEM;
4428 goto out1;
4429 }
4430
5897297b
AK		 4431 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4432 if (!vmx_msr_bitmap_longmode) {
4433 r = -ENOMEM;
4434 goto out2;
4435 }
4436
fdef3ad1
HQ		 4437 /*
4438 * Allow direct access to the PC debug port (it is often used for I/O
4439 * delays, but the vmexits simply slow things down).
4440 */
3e7c73e9
AK		 4441 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4442 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4443
3e7c73e9 4444 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4445
5897297b
AK		 4446 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4447 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4448
2384d2b3
SY		 4449 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4450
0ee75bea
AK		 4451 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4452 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4453 if (r)
5897297b 4454 goto out3;
25c5f225 4455
5897297b
AK		 4456 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4457 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4458 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4459 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4460 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4461 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4462
089d034e 4463 if (enable_ept) {
1439442c 4464 bypass_guest_pf = 0;
534e38b4 4465 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4466 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4467 kvm_enable_tdp();
4468 } else
4469 kvm_disable_tdp();
1439442c 4470
c7addb90
AK		 4471 if (bypass_guest_pf)
4472 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4473
fdef3ad1
HQ		 4474 return 0;
4475
5897297b
AK		 4476out3:
4477 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4478out2:
5897297b 4479 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4480out1:
3e7c73e9 4481 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4482out:
3e7c73e9 4483 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4484 return r;
6aa8b732
AK		 4485}
4486
4487static void __exit vmx_exit(void)
4488{
5897297b
AK		 4489 free_page((unsigned long)vmx_msr_bitmap_legacy);
4490 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4491 free_page((unsigned long)vmx_io_bitmap_b);
4492 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4493
cb498ea2 4494 kvm_exit();
6aa8b732
AK		 4495}
4496
4497module_init(vmx_init)
4498module_exit(vmx_exit)
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