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[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 69 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 72#define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
74 | X86_CR4_OSXMMEXCPT)
75
cdc0e244
AK		 76#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
78
4b8d54f9
ZE		 79/*
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
89 */
90#define KVM_VMX_DEFAULT_PLE_GAP 41
91#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93module_param(ple_gap, int, S_IRUGO);
94
95static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96module_param(ple_window, int, S_IRUGO);
97
a2fa3e9f
GH		 98struct vmcs {
99 u32 revision_id;
100 u32 abort;
101 char data[0];
102};
103
26bb0981
AK		 104struct shared_msr_entry {
105 unsigned index;
106 u64 data;
d5696725 107 u64 mask;
26bb0981
AK		 108};
109
a2fa3e9f 110struct vcpu_vmx {
fb3f0f51 111 struct kvm_vcpu vcpu;
543e4243 112 struct list_head local_vcpus_link;
313dbd49 113 unsigned long host_rsp;
a2fa3e9f 114 int launched;
29bd8a78 115 u8 fail;
1155f76a 116 u32 idt_vectoring_info;
26bb0981 117 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 118 int nmsrs;
119 int save_nmsrs;
a2fa3e9f 120#ifdef CONFIG_X86_64
44ea2b17
AK		 121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 123#endif
124 struct vmcs *vmcs;
125 struct {
126 int loaded;
127 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
d77c26fc 130 } host_state;
9c8cba37 131 struct {
7ffd92c5
AK		 132 int vm86_active;
133 u8 save_iopl;
134 struct kvm_save_segment {
135 u16 selector;
136 unsigned long base;
137 u32 limit;
138 u32 ar;
139 } tr, es, ds, fs, gs;
9c8cba37
AK		 140 struct {
141 bool pending;
142 u8 vector;
143 unsigned rip;
144 } irq;
145 } rmode;
2384d2b3 146 int vpid;
04fa4d32 147 bool emulation_required;
3b86cd99
JK		 148
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
151 ktime_t entry_time;
152 s64 vnmi_blocked_time;
a0861c02 153 u32 exit_reason;
4e47c7a6
SY		 154
155 bool rdtscp_enabled;
a2fa3e9f
GH		 156};
157
158static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
159{
fb3f0f51 160 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 161}
162
b7ebfb05 163static int init_rmode(struct kvm *kvm);
4e1096d2 164static u64 construct_eptp(unsigned long root_hpa);
75880a01 165
6aa8b732
AK		 166static DEFINE_PER_CPU(struct vmcs *, vmxarea);
167static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 168static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 169
3e7c73e9
AK		 170static unsigned long *vmx_io_bitmap_a;
171static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 172static unsigned long *vmx_msr_bitmap_legacy;
173static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 174
2384d2b3
SY		 175static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
176static DEFINE_SPINLOCK(vmx_vpid_lock);
177
1c3d14fe 178static struct vmcs_config {
6aa8b732
AK		 179 int size;
180 int order;
181 u32 revision_id;
1c3d14fe
YS		 182 u32 pin_based_exec_ctrl;
183 u32 cpu_based_exec_ctrl;
f78e0e2e 184 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 185 u32 vmexit_ctrl;
186 u32 vmentry_ctrl;
187} vmcs_config;
6aa8b732 188
efff9e53 189static struct vmx_capability {
d56f546d
SY		 190 u32 ept;
191 u32 vpid;
192} vmx_capability;
193
6aa8b732
AK		 194#define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
200 }
201
202static struct kvm_vmx_segment_field {
203 unsigned selector;
204 unsigned base;
205 unsigned limit;
206 unsigned ar_bytes;
207} kvm_vmx_segment_fields[] = {
208 VMX_SEGMENT_FIELD(CS),
209 VMX_SEGMENT_FIELD(DS),
210 VMX_SEGMENT_FIELD(ES),
211 VMX_SEGMENT_FIELD(FS),
212 VMX_SEGMENT_FIELD(GS),
213 VMX_SEGMENT_FIELD(SS),
214 VMX_SEGMENT_FIELD(TR),
215 VMX_SEGMENT_FIELD(LDTR),
216};
217
26bb0981
AK		 218static u64 host_efer;
219
6de4f3ad
AK		 220static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
221
4d56c8a7
AK		 222/*
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
225 */
6aa8b732 226static const u32 vmx_msr_index[] = {
05b3e0c2 227#ifdef CONFIG_X86_64
44ea2b17 228 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 229#endif
4e47c7a6 230 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 231};
9d8f549d 232#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 233
6aa8b732
AK		 234static inline int is_page_fault(u32 intr_info)
235{
236 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
237 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 238 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 239}
240
2ab455cc
AL		 241static inline int is_no_device(u32 intr_info)
242{
243 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
244 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 245 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 246}
247
7aa81cc0
AL		 248static inline int is_invalid_opcode(u32 intr_info)
249{
250 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
251 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 252 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 253}
254
6aa8b732
AK		 255static inline int is_external_interrupt(u32 intr_info)
256{
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
258 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
259}
260
a0861c02
AK		 261static inline int is_machine_check(u32 intr_info)
262{
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
266}
267
25c5f225
SY		 268static inline int cpu_has_vmx_msr_bitmap(void)
269{
04547156 270 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 271}
272
6e5d865c
YS		 273static inline int cpu_has_vmx_tpr_shadow(void)
274{
04547156 275 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 276}
277
278static inline int vm_need_tpr_shadow(struct kvm *kvm)
279{
04547156 280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 281}
282
f78e0e2e
SY		 283static inline int cpu_has_secondary_exec_ctrls(void)
284{
04547156
SY		 285 return vmcs_config.cpu_based_exec_ctrl &
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 287}
288
774ead3a 289static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 290{
04547156
SY		 291 return vmcs_config.cpu_based_2nd_exec_ctrl &
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
293}
294
295static inline bool cpu_has_vmx_flexpriority(void)
296{
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 299}
300
e799794e
MT		 301static inline bool cpu_has_vmx_ept_execute_only(void)
302{
303 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
304}
305
306static inline bool cpu_has_vmx_eptp_uncacheable(void)
307{
308 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
309}
310
311static inline bool cpu_has_vmx_eptp_writeback(void)
312{
313 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
314}
315
316static inline bool cpu_has_vmx_ept_2m_page(void)
317{
318 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
319}
320
878403b7
SY		 321static inline bool cpu_has_vmx_ept_1g_page(void)
322{
323 return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
324}
325
d56f546d
SY		 326static inline int cpu_has_vmx_invept_individual_addr(void)
327{
04547156 328 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 329}
330
331static inline int cpu_has_vmx_invept_context(void)
332{
04547156 333 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 334}
335
336static inline int cpu_has_vmx_invept_global(void)
337{
04547156 338 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 339}
340
341static inline int cpu_has_vmx_ept(void)
342{
04547156
SY		 343 return vmcs_config.cpu_based_2nd_exec_ctrl &
344 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 345}
346
3a624e29
NK		 347static inline int cpu_has_vmx_unrestricted_guest(void)
348{
349 return vmcs_config.cpu_based_2nd_exec_ctrl &
350 SECONDARY_EXEC_UNRESTRICTED_GUEST;
351}
352
4b8d54f9
ZE		 353static inline int cpu_has_vmx_ple(void)
354{
355 return vmcs_config.cpu_based_2nd_exec_ctrl &
356 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
357}
358
f78e0e2e
SY		 359static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
360{
6d3e435e 361 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 362}
363
2384d2b3
SY		 364static inline int cpu_has_vmx_vpid(void)
365{
04547156
SY		 366 return vmcs_config.cpu_based_2nd_exec_ctrl &
367 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 368}
369
4e47c7a6
SY		 370static inline int cpu_has_vmx_rdtscp(void)
371{
372 return vmcs_config.cpu_based_2nd_exec_ctrl &
373 SECONDARY_EXEC_RDTSCP;
374}
375
f08864b4
SY		 376static inline int cpu_has_virtual_nmis(void)
377{
378 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
379}
380
04547156
SY		 381static inline bool report_flexpriority(void)
382{
383 return flexpriority_enabled;
384}
385
8b9cf98c 386static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 387{
388 int i;
389
a2fa3e9f 390 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 391 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 392 return i;
393 return -1;
394}
395
2384d2b3
SY		 396static inline void __invvpid(int ext, u16 vpid, gva_t gva)
397{
398 struct {
399 u64 vpid : 16;
400 u64 rsvd : 48;
401 u64 gva;
402 } operand = { vpid, 0, gva };
403
4ecac3fd 404 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 405 /* CF==1 or ZF==1 --> rc = -1 */
406 "; ja 1f ; ud2 ; 1:"
407 : : "a"(&operand), "c"(ext) : "cc", "memory");
408}
409
1439442c
SY		 410static inline void __invept(int ext, u64 eptp, gpa_t gpa)
411{
412 struct {
413 u64 eptp, gpa;
414 } operand = {eptp, gpa};
415
4ecac3fd 416 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 417 /* CF==1 or ZF==1 --> rc = -1 */
418 "; ja 1f ; ud2 ; 1:\n"
419 : : "a" (&operand), "c" (ext) : "cc", "memory");
420}
421
26bb0981 422static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 423{
424 int i;
425
8b9cf98c 426 i = __find_msr_index(vmx, msr);
a75beee6 427 if (i >= 0)
a2fa3e9f 428 return &vmx->guest_msrs[i];
8b6d44c7 429 return NULL;
7725f0ba
AK		 430}
431
6aa8b732
AK		 432static void vmcs_clear(struct vmcs *vmcs)
433{
434 u64 phys_addr = __pa(vmcs);
435 u8 error;
436
4ecac3fd 437 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 438 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
439 : "cc", "memory");
440 if (error)
441 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
442 vmcs, phys_addr);
443}
444
445static void __vcpu_clear(void *arg)
446{
8b9cf98c 447 struct vcpu_vmx *vmx = arg;
d3b2c338 448 int cpu = raw_smp_processor_id();
6aa8b732 449
8b9cf98c 450 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 451 vmcs_clear(vmx->vmcs);
452 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 453 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 454 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 455 list_del(&vmx->local_vcpus_link);
456 vmx->vcpu.cpu = -1;
457 vmx->launched = 0;
6aa8b732
AK		 458}
459
8b9cf98c 460static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 461{
eae5ecb5
AK		 462 if (vmx->vcpu.cpu == -1)
463 return;
8691e5a8 464 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 465}
466
2384d2b3
SY		 467static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
468{
469 if (vmx->vpid == 0)
470 return;
471
472 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
473}
474
1439442c
SY		 475static inline void ept_sync_global(void)
476{
477 if (cpu_has_vmx_invept_global())
478 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
479}
480
481static inline void ept_sync_context(u64 eptp)
482{
089d034e 483 if (enable_ept) {
1439442c
SY		 484 if (cpu_has_vmx_invept_context())
485 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
486 else
487 ept_sync_global();
488 }
489}
490
491static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
492{
089d034e 493 if (enable_ept) {
1439442c
SY		 494 if (cpu_has_vmx_invept_individual_addr())
495 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
496 eptp, gpa);
497 else
498 ept_sync_context(eptp);
499 }
500}
501
6aa8b732
AK		 502static unsigned long vmcs_readl(unsigned long field)
503{
504 unsigned long value;
505
4ecac3fd 506 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 507 : "=a"(value) : "d"(field) : "cc");
508 return value;
509}
510
511static u16 vmcs_read16(unsigned long field)
512{
513 return vmcs_readl(field);
514}
515
516static u32 vmcs_read32(unsigned long field)
517{
518 return vmcs_readl(field);
519}
520
521static u64 vmcs_read64(unsigned long field)
522{
05b3e0c2 523#ifdef CONFIG_X86_64
6aa8b732
AK		 524 return vmcs_readl(field);
525#else
526 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
527#endif
528}
529
e52de1b8
AK		 530static noinline void vmwrite_error(unsigned long field, unsigned long value)
531{
532 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
533 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
534 dump_stack();
535}
536
6aa8b732
AK		 537static void vmcs_writel(unsigned long field, unsigned long value)
538{
539 u8 error;
540
4ecac3fd 541 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 542 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 543 if (unlikely(error))
544 vmwrite_error(field, value);
6aa8b732
AK		 545}
546
547static void vmcs_write16(unsigned long field, u16 value)
548{
549 vmcs_writel(field, value);
550}
551
552static void vmcs_write32(unsigned long field, u32 value)
553{
554 vmcs_writel(field, value);
555}
556
557static void vmcs_write64(unsigned long field, u64 value)
558{
6aa8b732 559 vmcs_writel(field, value);
7682f2d0 560#ifndef CONFIG_X86_64
6aa8b732
AK		 561 asm volatile ("");
562 vmcs_writel(field+1, value >> 32);
563#endif
564}
565
2ab455cc
AL		 566static void vmcs_clear_bits(unsigned long field, u32 mask)
567{
568 vmcs_writel(field, vmcs_readl(field) & ~mask);
569}
570
571static void vmcs_set_bits(unsigned long field, u32 mask)
572{
573 vmcs_writel(field, vmcs_readl(field) | mask);
574}
575
abd3f2d6
AK		 576static void update_exception_bitmap(struct kvm_vcpu *vcpu)
577{
578 u32 eb;
579
fd7373cc
JK		 580 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
581 (1u << NM_VECTOR) | (1u << DB_VECTOR);
582 if ((vcpu->guest_debug &
583 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
584 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
585 eb |= 1u << BP_VECTOR;
7ffd92c5 586 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 587 eb = ~0;
089d034e 588 if (enable_ept)
1439442c 589 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 590 if (vcpu->fpu_active)
591 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 592 vmcs_write32(EXCEPTION_BITMAP, eb);
593}
594
33ed6329
AK		 595static void reload_tss(void)
596{
33ed6329
AK		 597 /*
598 * VT restores TR but not its size. Useless.
599 */
600 struct descriptor_table gdt;
a5f61300 601 struct desc_struct *descs;
33ed6329 602
d6e88aec 603 kvm_get_gdt(&gdt);
33ed6329
AK		 604 descs = (void *)gdt.base;
605 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
606 load_TR_desc();
33ed6329
AK		 607}
608
92c0d900 609static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 610{
3a34a881 611 u64 guest_efer;
51c6cf66
AK		 612 u64 ignore_bits;
613
f6801dff 614 guest_efer = vmx->vcpu.arch.efer;
3a34a881 615
51c6cf66
AK		 616 /*
617 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
618 * outside long mode
619 */
620 ignore_bits = EFER_NX | EFER_SCE;
621#ifdef CONFIG_X86_64
622 ignore_bits |= EFER_LMA | EFER_LME;
623 /* SCE is meaningful only in long mode on Intel */
624 if (guest_efer & EFER_LMA)
625 ignore_bits &= ~(u64)EFER_SCE;
626#endif
51c6cf66
AK		 627 guest_efer &= ~ignore_bits;
628 guest_efer |= host_efer & ignore_bits;
26bb0981 629 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 630 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 631 return true;
51c6cf66
AK		 632}
633
04d2cc77 634static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 635{
04d2cc77 636 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 637 int i;
04d2cc77 638
a2fa3e9f 639 if (vmx->host_state.loaded)
33ed6329
AK		 640 return;
641
a2fa3e9f 642 vmx->host_state.loaded = 1;
33ed6329
AK		 643 /*
644 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
645 * allow segment selectors with cpl > 0 or ti == 1.
646 */
d6e88aec 647 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 648 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 649 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 650 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 651 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 652 vmx->host_state.fs_reload_needed = 0;
653 } else {
33ed6329 654 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 655 vmx->host_state.fs_reload_needed = 1;
33ed6329 656 }
d6e88aec 657 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 658 if (!(vmx->host_state.gs_sel & 7))
659 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 660 else {
661 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 662 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 663 }
664
665#ifdef CONFIG_X86_64
666 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
667 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
668#else
a2fa3e9f
GH		 669 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
670 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 671#endif
707c0874
AK		 672
673#ifdef CONFIG_X86_64
44ea2b17
AK		 674 if (is_long_mode(&vmx->vcpu)) {
675 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
676 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
677 }
707c0874 678#endif
26bb0981
AK		 679 for (i = 0; i < vmx->save_nmsrs; ++i)
680 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 681 vmx->guest_msrs[i].data,
682 vmx->guest_msrs[i].mask);
33ed6329
AK		 683}
684
a9b21b62 685static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 686{
15ad7146 687 unsigned long flags;
33ed6329 688
a2fa3e9f 689 if (!vmx->host_state.loaded)
33ed6329
AK		 690 return;
691
e1beb1d3 692 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 693 vmx->host_state.loaded = 0;
152d3f2f 694 if (vmx->host_state.fs_reload_needed)
d6e88aec 695 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 696 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 697 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 698 /*
699 * If we have to reload gs, we must take care to
700 * preserve our gs base.
701 */
15ad7146 702 local_irq_save(flags);
d6e88aec 703 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 704#ifdef CONFIG_X86_64
705 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
706#endif
15ad7146 707 local_irq_restore(flags);
33ed6329 708 }
152d3f2f 709 reload_tss();
44ea2b17
AK		 710#ifdef CONFIG_X86_64
711 if (is_long_mode(&vmx->vcpu)) {
712 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
713 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
714 }
715#endif
33ed6329
AK		 716}
717
a9b21b62
AK		 718static void vmx_load_host_state(struct vcpu_vmx *vmx)
719{
720 preempt_disable();
721 __vmx_load_host_state(vmx);
722 preempt_enable();
723}
724
6aa8b732
AK		 725/*
726 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
727 * vcpu mutex is already taken.
728 */
15ad7146 729static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 730{
a2fa3e9f
GH		 731 struct vcpu_vmx *vmx = to_vmx(vcpu);
732 u64 phys_addr = __pa(vmx->vmcs);
019960ae 733 u64 tsc_this, delta, new_offset;
6aa8b732 734
a3d7f85f 735 if (vcpu->cpu != cpu) {
8b9cf98c 736 vcpu_clear(vmx);
2f599714 737 kvm_migrate_timers(vcpu);
eb5109e3 738 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 739 local_irq_disable();
740 list_add(&vmx->local_vcpus_link,
741 &per_cpu(vcpus_on_cpu, cpu));
742 local_irq_enable();
a3d7f85f 743 }
6aa8b732 744
a2fa3e9f 745 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 746 u8 error;
747
a2fa3e9f 748 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 749 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 750 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
751 : "cc");
752 if (error)
753 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 754 vmx->vmcs, phys_addr);
6aa8b732
AK		 755 }
756
757 if (vcpu->cpu != cpu) {
758 struct descriptor_table dt;
759 unsigned long sysenter_esp;
760
761 vcpu->cpu = cpu;
762 /*
763 * Linux uses per-cpu TSS and GDT, so set these when switching
764 * processors.
765 */
d6e88aec
AK		 766 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
767 kvm_get_gdt(&dt);
6aa8b732
AK		 768 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
769
770 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
771 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 772
773 /*
774 * Make sure the time stamp counter is monotonous.
775 */
776 rdtscll(tsc_this);
019960ae
AK		 777 if (tsc_this < vcpu->arch.host_tsc) {
778 delta = vcpu->arch.host_tsc - tsc_this;
779 new_offset = vmcs_read64(TSC_OFFSET) + delta;
780 vmcs_write64(TSC_OFFSET, new_offset);
781 }
6aa8b732 782 }
6aa8b732
AK		 783}
784
785static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
786{
a9b21b62 787 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 788}
789
5fd86fcf
AK		 790static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
791{
81231c69
AK		 792 ulong cr0;
793
5fd86fcf
AK		 794 if (vcpu->fpu_active)
795 return;
796 vcpu->fpu_active = 1;
81231c69
AK		 797 cr0 = vmcs_readl(GUEST_CR0);
798 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
799 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
800 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 801 update_exception_bitmap(vcpu);
edcafe3c
AK		 802 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
803 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 804}
805
edcafe3c
AK		 806static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
807
5fd86fcf
AK		 808static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
809{
edcafe3c 810 vmx_decache_cr0_guest_bits(vcpu);
81231c69 811 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 812 update_exception_bitmap(vcpu);
edcafe3c
AK		 813 vcpu->arch.cr0_guest_owned_bits = 0;
814 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
815 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 816}
817
6aa8b732
AK		 818static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
819{
345dcaa8
AK		 820 unsigned long rflags;
821
822 rflags = vmcs_readl(GUEST_RFLAGS);
823 if (to_vmx(vcpu)->rmode.vm86_active)
824 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
825 return rflags;
6aa8b732
AK		 826}
827
828static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
829{
7ffd92c5 830 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 831 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 832 vmcs_writel(GUEST_RFLAGS, rflags);
833}
834
2809f5d2
GC		 835static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
836{
837 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
838 int ret = 0;
839
840 if (interruptibility & GUEST_INTR_STATE_STI)
841 ret |= X86_SHADOW_INT_STI;
842 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
843 ret |= X86_SHADOW_INT_MOV_SS;
844
845 return ret & mask;
846}
847
848static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
849{
850 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
851 u32 interruptibility = interruptibility_old;
852
853 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
854
855 if (mask & X86_SHADOW_INT_MOV_SS)
856 interruptibility |= GUEST_INTR_STATE_MOV_SS;
857 if (mask & X86_SHADOW_INT_STI)
858 interruptibility |= GUEST_INTR_STATE_STI;
859
860 if ((interruptibility != interruptibility_old))
861 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
862}
863
6aa8b732
AK		 864static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
865{
866 unsigned long rip;
6aa8b732 867
5fdbf976 868 rip = kvm_rip_read(vcpu);
6aa8b732 869 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 870 kvm_rip_write(vcpu, rip);
6aa8b732 871
2809f5d2
GC		 872 /* skipping an emulated instruction also counts */
873 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 874}
875
298101da
AK		 876static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
877 bool has_error_code, u32 error_code)
878{
77ab6db0 879 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 880 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 881
8ab2d2e2 882 if (has_error_code) {
77ab6db0 883 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 884 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
885 }
77ab6db0 886
7ffd92c5 887 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 888 vmx->rmode.irq.pending = true;
889 vmx->rmode.irq.vector = nr;
890 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 891 if (kvm_exception_is_soft(nr))
892 vmx->rmode.irq.rip +=
893 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 894 intr_info |= INTR_TYPE_SOFT_INTR;
895 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 896 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
897 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
898 return;
899 }
900
66fd3f7f
GN		 901 if (kvm_exception_is_soft(nr)) {
902 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
903 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 904 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
905 } else
906 intr_info |= INTR_TYPE_HARD_EXCEPTION;
907
908 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 909}
910
4e47c7a6
SY		 911static bool vmx_rdtscp_supported(void)
912{
913 return cpu_has_vmx_rdtscp();
914}
915
a75beee6
ED		 916/*
917 * Swap MSR entry in host/guest MSR entry array.
918 */
8b9cf98c 919static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 920{
26bb0981 921 struct shared_msr_entry tmp;
a2fa3e9f
GH		 922
923 tmp = vmx->guest_msrs[to];
924 vmx->guest_msrs[to] = vmx->guest_msrs[from];
925 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 926}
927
e38aea3e
AK		 928/*
929 * Set up the vmcs to automatically save and restore system
930 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
931 * mode, as fiddling with msrs is very expensive.
932 */
8b9cf98c 933static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 934{
26bb0981 935 int save_nmsrs, index;
5897297b 936 unsigned long *msr_bitmap;
e38aea3e 937
33f9c505 938 vmx_load_host_state(vmx);
a75beee6
ED		 939 save_nmsrs = 0;
940#ifdef CONFIG_X86_64
8b9cf98c 941 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 942 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 943 if (index >= 0)
8b9cf98c
RR		 944 move_msr_up(vmx, index, save_nmsrs++);
945 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 946 if (index >= 0)
8b9cf98c
RR		 947 move_msr_up(vmx, index, save_nmsrs++);
948 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 949 if (index >= 0)
8b9cf98c 950 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 951 index = __find_msr_index(vmx, MSR_TSC_AUX);
952 if (index >= 0 && vmx->rdtscp_enabled)
953 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 954 /*
955 * MSR_K6_STAR is only needed on long mode guests, and only
956 * if efer.sce is enabled.
957 */
8b9cf98c 958 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 959 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 960 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 961 }
962#endif
92c0d900
AK		 963 index = __find_msr_index(vmx, MSR_EFER);
964 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 965 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 966
26bb0981 967 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 968
969 if (cpu_has_vmx_msr_bitmap()) {
970 if (is_long_mode(&vmx->vcpu))
971 msr_bitmap = vmx_msr_bitmap_longmode;
972 else
973 msr_bitmap = vmx_msr_bitmap_legacy;
974
975 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
976 }
e38aea3e
AK		 977}
978
6aa8b732
AK		 979/*
980 * reads and returns guest's timestamp counter "register"
981 * guest_tsc = host_tsc + tsc_offset -- 21.3
982 */
983static u64 guest_read_tsc(void)
984{
985 u64 host_tsc, tsc_offset;
986
987 rdtscll(host_tsc);
988 tsc_offset = vmcs_read64(TSC_OFFSET);
989 return host_tsc + tsc_offset;
990}
991
992/*
993 * writes 'guest_tsc' into guest's timestamp counter "register"
994 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
995 */
53f658b3 996static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 997{
6aa8b732
AK		 998 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
999}
1000
6aa8b732
AK		 1001/*
1002 * Reads an msr value (of 'msr_index') into 'pdata'.
1003 * Returns 0 on success, non-0 otherwise.
1004 * Assumes vcpu_load() was already called.
1005 */
1006static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1007{
1008 u64 data;
26bb0981 1009 struct shared_msr_entry *msr;
6aa8b732
AK		 1010
1011 if (!pdata) {
1012 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1013 return -EINVAL;
1014 }
1015
1016 switch (msr_index) {
05b3e0c2 1017#ifdef CONFIG_X86_64
6aa8b732
AK		 1018 case MSR_FS_BASE:
1019 data = vmcs_readl(GUEST_FS_BASE);
1020 break;
1021 case MSR_GS_BASE:
1022 data = vmcs_readl(GUEST_GS_BASE);
1023 break;
44ea2b17
AK		 1024 case MSR_KERNEL_GS_BASE:
1025 vmx_load_host_state(to_vmx(vcpu));
1026 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1027 break;
26bb0981 1028#endif
6aa8b732 1029 case MSR_EFER:
3bab1f5d 1030 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1031 case MSR_IA32_TSC:
6aa8b732
AK		 1032 data = guest_read_tsc();
1033 break;
1034 case MSR_IA32_SYSENTER_CS:
1035 data = vmcs_read32(GUEST_SYSENTER_CS);
1036 break;
1037 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1038 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1039 break;
1040 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1041 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1042 break;
4e47c7a6
SY		 1043 case MSR_TSC_AUX:
1044 if (!to_vmx(vcpu)->rdtscp_enabled)
1045 return 1;
1046 /* Otherwise falls through */
6aa8b732 1047 default:
26bb0981 1048 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1049 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1050 if (msr) {
542423b0 1051 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1052 data = msr->data;
1053 break;
6aa8b732 1054 }
3bab1f5d 1055 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1056 }
1057
1058 *pdata = data;
1059 return 0;
1060}
1061
1062/*
1063 * Writes msr value into into the appropriate "register".
1064 * Returns 0 on success, non-0 otherwise.
1065 * Assumes vcpu_load() was already called.
1066 */
1067static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1068{
a2fa3e9f 1069 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1070 struct shared_msr_entry *msr;
53f658b3 1071 u64 host_tsc;
2cc51560
ED		 1072 int ret = 0;
1073
6aa8b732 1074 switch (msr_index) {
3bab1f5d 1075 case MSR_EFER:
a9b21b62 1076 vmx_load_host_state(vmx);
2cc51560 1077 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1078 break;
16175a79 1079#ifdef CONFIG_X86_64
6aa8b732
AK		 1080 case MSR_FS_BASE:
1081 vmcs_writel(GUEST_FS_BASE, data);
1082 break;
1083 case MSR_GS_BASE:
1084 vmcs_writel(GUEST_GS_BASE, data);
1085 break;
44ea2b17
AK		 1086 case MSR_KERNEL_GS_BASE:
1087 vmx_load_host_state(vmx);
1088 vmx->msr_guest_kernel_gs_base = data;
1089 break;
6aa8b732
AK		 1090#endif
1091 case MSR_IA32_SYSENTER_CS:
1092 vmcs_write32(GUEST_SYSENTER_CS, data);
1093 break;
1094 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1095 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1096 break;
1097 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1098 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1099 break;
af24a4e4 1100 case MSR_IA32_TSC:
53f658b3
MT		 1101 rdtscll(host_tsc);
1102 guest_write_tsc(data, host_tsc);
6aa8b732 1103 break;
468d472f
SY		 1104 case MSR_IA32_CR_PAT:
1105 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1106 vmcs_write64(GUEST_IA32_PAT, data);
1107 vcpu->arch.pat = data;
1108 break;
1109 }
4e47c7a6
SY		 1110 ret = kvm_set_msr_common(vcpu, msr_index, data);
1111 break;
1112 case MSR_TSC_AUX:
1113 if (!vmx->rdtscp_enabled)
1114 return 1;
1115 /* Check reserved bit, higher 32 bits should be zero */
1116 if ((data >> 32) != 0)
1117 return 1;
1118 /* Otherwise falls through */
6aa8b732 1119 default:
8b9cf98c 1120 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1121 if (msr) {
542423b0 1122 vmx_load_host_state(vmx);
3bab1f5d
AK		 1123 msr->data = data;
1124 break;
6aa8b732 1125 }
2cc51560 1126 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1127 }
1128
2cc51560 1129 return ret;
6aa8b732
AK		 1130}
1131
5fdbf976 1132static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1133{
5fdbf976
MT		 1134 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1135 switch (reg) {
1136 case VCPU_REGS_RSP:
1137 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1138 break;
1139 case VCPU_REGS_RIP:
1140 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1141 break;
6de4f3ad
AK		 1142 case VCPU_EXREG_PDPTR:
1143 if (enable_ept)
1144 ept_save_pdptrs(vcpu);
1145 break;
5fdbf976
MT		 1146 default:
1147 break;
1148 }
6aa8b732
AK		 1149}
1150
355be0b9 1151static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1152{
ae675ef0
JK		 1153 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1154 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1155 else
1156 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1157
abd3f2d6 1158 update_exception_bitmap(vcpu);
6aa8b732
AK		 1159}
1160
1161static __init int cpu_has_kvm_support(void)
1162{
6210e37b 1163 return cpu_has_vmx();
6aa8b732
AK		 1164}
1165
1166static __init int vmx_disabled_by_bios(void)
1167{
1168 u64 msr;
1169
1170 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1171 return (msr & (FEATURE_CONTROL_LOCKED |
1172 FEATURE_CONTROL_VMXON_ENABLED))
1173 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1174 /* locked but not enabled */
6aa8b732
AK		 1175}
1176
10474ae8 1177static int hardware_enable(void *garbage)
6aa8b732
AK		 1178{
1179 int cpu = raw_smp_processor_id();
1180 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1181 u64 old;
1182
10474ae8
AG		 1183 if (read_cr4() & X86_CR4_VMXE)
1184 return -EBUSY;
1185
543e4243 1186 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1187 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1188 if ((old & (FEATURE_CONTROL_LOCKED |
1189 FEATURE_CONTROL_VMXON_ENABLED))
1190 != (FEATURE_CONTROL_LOCKED |
1191 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1192 /* enable and lock */
62b3ffb8 1193 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1194 FEATURE_CONTROL_LOCKED |
1195 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1196 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1197 asm volatile (ASM_VMX_VMXON_RAX
1198 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1199 : "memory", "cc");
10474ae8
AG		 1200
1201 ept_sync_global();
1202
1203 return 0;
6aa8b732
AK		 1204}
1205
543e4243
AK		 1206static void vmclear_local_vcpus(void)
1207{
1208 int cpu = raw_smp_processor_id();
1209 struct vcpu_vmx *vmx, *n;
1210
1211 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1212 local_vcpus_link)
1213 __vcpu_clear(vmx);
1214}
1215
710ff4a8
EH		 1216
1217/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1218 * tricks.
1219 */
1220static void kvm_cpu_vmxoff(void)
6aa8b732 1221{
4ecac3fd 1222 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1223 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1224}
1225
710ff4a8
EH		 1226static void hardware_disable(void *garbage)
1227{
1228 vmclear_local_vcpus();
1229 kvm_cpu_vmxoff();
1230}
1231
1c3d14fe 1232static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1233 u32 msr, u32 *result)
1c3d14fe
YS		 1234{
1235 u32 vmx_msr_low, vmx_msr_high;
1236 u32 ctl = ctl_min | ctl_opt;
1237
1238 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1239
1240 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1241 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1242
1243 /* Ensure minimum (required) set of control bits are supported. */
1244 if (ctl_min & ~ctl)
002c7f7c 1245 return -EIO;
1c3d14fe
YS		 1246
1247 *result = ctl;
1248 return 0;
1249}
1250
002c7f7c 1251static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1252{
1253 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1254 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1255 u32 _pin_based_exec_control = 0;
1256 u32 _cpu_based_exec_control = 0;
f78e0e2e 1257 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1258 u32 _vmexit_control = 0;
1259 u32 _vmentry_control = 0;
1260
1261 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1262 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1263 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1264 &_pin_based_exec_control) < 0)
002c7f7c 1265 return -EIO;
1c3d14fe
YS		 1266
1267 min = CPU_BASED_HLT_EXITING |
1268#ifdef CONFIG_X86_64
1269 CPU_BASED_CR8_LOAD_EXITING |
1270 CPU_BASED_CR8_STORE_EXITING |
1271#endif
d56f546d
SY		 1272 CPU_BASED_CR3_LOAD_EXITING |
1273 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1274 CPU_BASED_USE_IO_BITMAPS |
1275 CPU_BASED_MOV_DR_EXITING |
a7052897 1276 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1277 CPU_BASED_MWAIT_EXITING |
1278 CPU_BASED_MONITOR_EXITING |
a7052897 1279 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1280 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1281 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1282 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1283 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1284 &_cpu_based_exec_control) < 0)
002c7f7c 1285 return -EIO;
6e5d865c
YS		 1286#ifdef CONFIG_X86_64
1287 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1288 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1289 ~CPU_BASED_CR8_STORE_EXITING;
1290#endif
f78e0e2e 1291 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1292 min2 = 0;
1293 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1294 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1295 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1296 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1297 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1298 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1299 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1300 if (adjust_vmx_controls(min2, opt2,
1301 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1302 &_cpu_based_2nd_exec_control) < 0)
1303 return -EIO;
1304 }
1305#ifndef CONFIG_X86_64
1306 if (!(_cpu_based_2nd_exec_control &
1307 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1308 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1309#endif
d56f546d 1310 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1311 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1312 enabled */
5fff7d27
GN		 1313 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1314 CPU_BASED_CR3_STORE_EXITING |
1315 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1316 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1317 vmx_capability.ept, vmx_capability.vpid);
1318 }
1c3d14fe
YS		 1319
1320 min = 0;
1321#ifdef CONFIG_X86_64
1322 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1323#endif
468d472f 1324 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1325 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1326 &_vmexit_control) < 0)
002c7f7c 1327 return -EIO;
1c3d14fe 1328
468d472f
SY		 1329 min = 0;
1330 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1331 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1332 &_vmentry_control) < 0)
002c7f7c 1333 return -EIO;
6aa8b732 1334
c68876fd 1335 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1336
1337 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1338 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1339 return -EIO;
1c3d14fe
YS		 1340
1341#ifdef CONFIG_X86_64
1342 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1343 if (vmx_msr_high & (1u<<16))
002c7f7c 1344 return -EIO;
1c3d14fe
YS		 1345#endif
1346
1347 /* Require Write-Back (WB) memory type for VMCS accesses. */
1348 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1349 return -EIO;
1c3d14fe 1350
002c7f7c
YS		 1351 vmcs_conf->size = vmx_msr_high & 0x1fff;
1352 vmcs_conf->order = get_order(vmcs_config.size);
1353 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1354
002c7f7c
YS		 1355 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1356 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1357 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1358 vmcs_conf->vmexit_ctrl = _vmexit_control;
1359 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1360
1361 return 0;
c68876fd 1362}
6aa8b732
AK		 1363
1364static struct vmcs *alloc_vmcs_cpu(int cpu)
1365{
1366 int node = cpu_to_node(cpu);
1367 struct page *pages;
1368 struct vmcs *vmcs;
1369
6484eb3e 1370 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1371 if (!pages)
1372 return NULL;
1373 vmcs = page_address(pages);
1c3d14fe
YS		 1374 memset(vmcs, 0, vmcs_config.size);
1375 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1376 return vmcs;
1377}
1378
1379static struct vmcs *alloc_vmcs(void)
1380{
d3b2c338 1381 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1382}
1383
1384static void free_vmcs(struct vmcs *vmcs)
1385{
1c3d14fe 1386 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1387}
1388
39959588 1389static void free_kvm_area(void)
6aa8b732
AK		 1390{
1391 int cpu;
1392
3230bb47 1393 for_each_possible_cpu(cpu) {
6aa8b732 1394 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1395 per_cpu(vmxarea, cpu) = NULL;
1396 }
6aa8b732
AK		 1397}
1398
6aa8b732
AK		 1399static __init int alloc_kvm_area(void)
1400{
1401 int cpu;
1402
3230bb47 1403 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1404 struct vmcs *vmcs;
1405
1406 vmcs = alloc_vmcs_cpu(cpu);
1407 if (!vmcs) {
1408 free_kvm_area();
1409 return -ENOMEM;
1410 }
1411
1412 per_cpu(vmxarea, cpu) = vmcs;
1413 }
1414 return 0;
1415}
1416
1417static __init int hardware_setup(void)
1418{
002c7f7c
YS		 1419 if (setup_vmcs_config(&vmcs_config) < 0)
1420 return -EIO;
50a37eb4
JR		 1421
1422 if (boot_cpu_has(X86_FEATURE_NX))
1423 kvm_enable_efer_bits(EFER_NX);
1424
93ba03c2
SY		 1425 if (!cpu_has_vmx_vpid())
1426 enable_vpid = 0;
1427
3a624e29 1428 if (!cpu_has_vmx_ept()) {
93ba03c2 1429 enable_ept = 0;
3a624e29
NK		 1430 enable_unrestricted_guest = 0;
1431 }
1432
1433 if (!cpu_has_vmx_unrestricted_guest())
1434 enable_unrestricted_guest = 0;
93ba03c2
SY		 1435
1436 if (!cpu_has_vmx_flexpriority())
1437 flexpriority_enabled = 0;
1438
95ba8273
GN		 1439 if (!cpu_has_vmx_tpr_shadow())
1440 kvm_x86_ops->update_cr8_intercept = NULL;
1441
54dee993
MT		 1442 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1443 kvm_disable_largepages();
1444
4b8d54f9
ZE		 1445 if (!cpu_has_vmx_ple())
1446 ple_gap = 0;
1447
6aa8b732
AK		 1448 return alloc_kvm_area();
1449}
1450
1451static __exit void hardware_unsetup(void)
1452{
1453 free_kvm_area();
1454}
1455
6aa8b732
AK		 1456static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1457{
1458 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1459
6af11b9e 1460 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1461 vmcs_write16(sf->selector, save->selector);
1462 vmcs_writel(sf->base, save->base);
1463 vmcs_write32(sf->limit, save->limit);
1464 vmcs_write32(sf->ar_bytes, save->ar);
1465 } else {
1466 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1467 << AR_DPL_SHIFT;
1468 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1469 }
1470}
1471
1472static void enter_pmode(struct kvm_vcpu *vcpu)
1473{
1474 unsigned long flags;
a89a8fb9 1475 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1476
a89a8fb9 1477 vmx->emulation_required = 1;
7ffd92c5 1478 vmx->rmode.vm86_active = 0;
6aa8b732 1479
7ffd92c5
AK		 1480 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1481 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1482 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1483
1484 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1485 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1486 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1487 vmcs_writel(GUEST_RFLAGS, flags);
1488
66aee91a
RR		 1489 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1490 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1491
1492 update_exception_bitmap(vcpu);
1493
a89a8fb9
MG		 1494 if (emulate_invalid_guest_state)
1495 return;
1496
7ffd92c5
AK		 1497 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1498 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1499 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1500 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1501
1502 vmcs_write16(GUEST_SS_SELECTOR, 0);
1503 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1504
1505 vmcs_write16(GUEST_CS_SELECTOR,
1506 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1507 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1508}
1509
d77c26fc 1510static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1511{
bfc6d222 1512 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1513 struct kvm_memslots *slots;
1514 gfn_t base_gfn;
1515
1516 slots = rcu_dereference(kvm->memslots);
1517 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1518 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1519 return base_gfn << PAGE_SHIFT;
1520 }
bfc6d222 1521 return kvm->arch.tss_addr;
6aa8b732
AK		 1522}
1523
1524static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1525{
1526 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1527
1528 save->selector = vmcs_read16(sf->selector);
1529 save->base = vmcs_readl(sf->base);
1530 save->limit = vmcs_read32(sf->limit);
1531 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1532 vmcs_write16(sf->selector, save->base >> 4);
1533 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1534 vmcs_write32(sf->limit, 0xffff);
1535 vmcs_write32(sf->ar_bytes, 0xf3);
1536}
1537
1538static void enter_rmode(struct kvm_vcpu *vcpu)
1539{
1540 unsigned long flags;
a89a8fb9 1541 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1542
3a624e29
NK		 1543 if (enable_unrestricted_guest)
1544 return;
1545
a89a8fb9 1546 vmx->emulation_required = 1;
7ffd92c5 1547 vmx->rmode.vm86_active = 1;
6aa8b732 1548
7ffd92c5 1549 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1550 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1551
7ffd92c5 1552 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1553 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1554
7ffd92c5 1555 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1556 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1557
1558 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1559 vmx->rmode.save_iopl
ad312c7c 1560 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1561
053de044 1562 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1563
1564 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1565 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1566 update_exception_bitmap(vcpu);
1567
a89a8fb9
MG		 1568 if (emulate_invalid_guest_state)
1569 goto continue_rmode;
1570
6aa8b732
AK		 1571 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1572 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1573 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1574
1575 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1576 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1577 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1578 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1579 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1580
7ffd92c5
AK		 1581 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1582 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1583 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1584 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1585
a89a8fb9 1586continue_rmode:
8668a3c4 1587 kvm_mmu_reset_context(vcpu);
b7ebfb05 1588 init_rmode(vcpu->kvm);
6aa8b732
AK		 1589}
1590
401d10de
AS		 1591static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1592{
1593 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1594 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1595
1596 if (!msr)
1597 return;
401d10de 1598
44ea2b17
AK		 1599 /*
1600 * Force kernel_gs_base reloading before EFER changes, as control
1601 * of this msr depends on is_long_mode().
1602 */
1603 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1604 vcpu->arch.efer = efer;
401d10de
AS		 1605 if (efer & EFER_LMA) {
1606 vmcs_write32(VM_ENTRY_CONTROLS,
1607 vmcs_read32(VM_ENTRY_CONTROLS) |
1608 VM_ENTRY_IA32E_MODE);
1609 msr->data = efer;
1610 } else {
1611 vmcs_write32(VM_ENTRY_CONTROLS,
1612 vmcs_read32(VM_ENTRY_CONTROLS) &
1613 ~VM_ENTRY_IA32E_MODE);
1614
1615 msr->data = efer & ~EFER_LME;
1616 }
1617 setup_msrs(vmx);
1618}
1619
05b3e0c2 1620#ifdef CONFIG_X86_64
6aa8b732
AK		 1621
1622static void enter_lmode(struct kvm_vcpu *vcpu)
1623{
1624 u32 guest_tr_ar;
1625
1626 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1627 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1628 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1629 __func__);
6aa8b732
AK		 1630 vmcs_write32(GUEST_TR_AR_BYTES,
1631 (guest_tr_ar & ~AR_TYPE_MASK)
1632 | AR_TYPE_BUSY_64_TSS);
1633 }
f6801dff
AK		 1634 vcpu->arch.efer |= EFER_LMA;
1635 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1636}
1637
1638static void exit_lmode(struct kvm_vcpu *vcpu)
1639{
f6801dff 1640 vcpu->arch.efer &= ~EFER_LMA;
6aa8b732
AK		 1641
1642 vmcs_write32(VM_ENTRY_CONTROLS,
1643 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1644 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1645}
1646
1647#endif
1648
2384d2b3
SY		 1649static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1650{
1651 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1652 if (enable_ept)
4e1096d2 1653 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1654}
1655
e8467fda
AK		 1656static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1657{
1658 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1659
1660 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1661 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1662}
1663
25c4c276 1664static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1665{
fc78f519
AK		 1666 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1667
1668 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1669 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1670}
1671
1439442c
SY		 1672static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1673{
6de4f3ad
AK		 1674 if (!test_bit(VCPU_EXREG_PDPTR,
1675 (unsigned long *)&vcpu->arch.regs_dirty))
1676 return;
1677
1439442c 1678 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1679 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1680 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1681 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1682 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1683 }
1684}
1685
8f5d549f
AK		 1686static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1687{
1688 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1689 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1690 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1691 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1692 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1693 }
6de4f3ad
AK		 1694
1695 __set_bit(VCPU_EXREG_PDPTR,
1696 (unsigned long *)&vcpu->arch.regs_avail);
1697 __set_bit(VCPU_EXREG_PDPTR,
1698 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1699}
1700
1439442c
SY		 1701static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1702
1703static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1704 unsigned long cr0,
1705 struct kvm_vcpu *vcpu)
1706{
1707 if (!(cr0 & X86_CR0_PG)) {
1708 /* From paging/starting to nonpaging */
1709 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1710 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1711 (CPU_BASED_CR3_LOAD_EXITING |
1712 CPU_BASED_CR3_STORE_EXITING));
1713 vcpu->arch.cr0 = cr0;
fc78f519 1714 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1715 } else if (!is_paging(vcpu)) {
1716 /* From nonpaging to paging */
1717 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1718 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1719 ~(CPU_BASED_CR3_LOAD_EXITING |
1720 CPU_BASED_CR3_STORE_EXITING));
1721 vcpu->arch.cr0 = cr0;
fc78f519 1722 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1723 }
95eb84a7
SY		 1724
1725 if (!(cr0 & X86_CR0_WP))
1726 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1727}
1728
6aa8b732
AK		 1729static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1730{
7ffd92c5 1731 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1732 unsigned long hw_cr0;
1733
1734 if (enable_unrestricted_guest)
1735 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1736 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1737 else
1738 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1739
7ffd92c5 1740 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1741 enter_pmode(vcpu);
1742
7ffd92c5 1743 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1744 enter_rmode(vcpu);
1745
05b3e0c2 1746#ifdef CONFIG_X86_64
f6801dff 1747 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1748 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1749 enter_lmode(vcpu);
707d92fa 1750 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1751 exit_lmode(vcpu);
1752 }
1753#endif
1754
089d034e 1755 if (enable_ept)
1439442c
SY		 1756 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1757
02daab21 1758 if (!vcpu->fpu_active)
81231c69 1759 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1760
6aa8b732 1761 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1762 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1763 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1764}
1765
1439442c
SY		 1766static u64 construct_eptp(unsigned long root_hpa)
1767{
1768 u64 eptp;
1769
1770 /* TODO write the value reading from MSR */
1771 eptp = VMX_EPT_DEFAULT_MT |
1772 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1773 eptp |= (root_hpa & PAGE_MASK);
1774
1775 return eptp;
1776}
1777
6aa8b732
AK		 1778static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1779{
1439442c
SY		 1780 unsigned long guest_cr3;
1781 u64 eptp;
1782
1783 guest_cr3 = cr3;
089d034e 1784 if (enable_ept) {
1439442c
SY		 1785 eptp = construct_eptp(cr3);
1786 vmcs_write64(EPT_POINTER, eptp);
1439442c 1787 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1788 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1789 ept_load_pdptrs(vcpu);
1439442c
SY		 1790 }
1791
2384d2b3 1792 vmx_flush_tlb(vcpu);
1439442c 1793 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1794}
1795
1796static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1797{
7ffd92c5 1798 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1799 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1800
ad312c7c 1801 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1802 if (enable_ept) {
1803 if (!is_paging(vcpu)) {
1804 hw_cr4 &= ~X86_CR4_PAE;
1805 hw_cr4 |= X86_CR4_PSE;
1806 } else if (!(cr4 & X86_CR4_PAE)) {
1807 hw_cr4 &= ~X86_CR4_PAE;
1808 }
1809 }
1439442c
SY		 1810
1811 vmcs_writel(CR4_READ_SHADOW, cr4);
1812 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1813}
1814
6aa8b732
AK		 1815static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1816{
1817 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1818
1819 return vmcs_readl(sf->base);
1820}
1821
1822static void vmx_get_segment(struct kvm_vcpu *vcpu,
1823 struct kvm_segment *var, int seg)
1824{
1825 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1826 u32 ar;
1827
1828 var->base = vmcs_readl(sf->base);
1829 var->limit = vmcs_read32(sf->limit);
1830 var->selector = vmcs_read16(sf->selector);
1831 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1832 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1833 ar = 0;
1834 var->type = ar & 15;
1835 var->s = (ar >> 4) & 1;
1836 var->dpl = (ar >> 5) & 3;
1837 var->present = (ar >> 7) & 1;
1838 var->avl = (ar >> 12) & 1;
1839 var->l = (ar >> 13) & 1;
1840 var->db = (ar >> 14) & 1;
1841 var->g = (ar >> 15) & 1;
1842 var->unusable = (ar >> 16) & 1;
1843}
1844
2e4d2653
IE		 1845static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1846{
3eeb3288 1847 if (!is_protmode(vcpu))
2e4d2653
IE		 1848 return 0;
1849
1850 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1851 return 3;
1852
eab4b8aa 1853 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1854}
1855
653e3108 1856static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1857{
6aa8b732
AK		 1858 u32 ar;
1859
653e3108 1860 if (var->unusable)
6aa8b732
AK		 1861 ar = 1 << 16;
1862 else {
1863 ar = var->type & 15;
1864 ar |= (var->s & 1) << 4;
1865 ar |= (var->dpl & 3) << 5;
1866 ar |= (var->present & 1) << 7;
1867 ar |= (var->avl & 1) << 12;
1868 ar |= (var->l & 1) << 13;
1869 ar |= (var->db & 1) << 14;
1870 ar |= (var->g & 1) << 15;
1871 }
f7fbf1fd
UL		 1872 if (ar == 0) /* a 0 value means unusable */
1873 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1874
1875 return ar;
1876}
1877
1878static void vmx_set_segment(struct kvm_vcpu *vcpu,
1879 struct kvm_segment *var, int seg)
1880{
7ffd92c5 1881 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1882 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1883 u32 ar;
1884
7ffd92c5
AK		 1885 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1886 vmx->rmode.tr.selector = var->selector;
1887 vmx->rmode.tr.base = var->base;
1888 vmx->rmode.tr.limit = var->limit;
1889 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1890 return;
1891 }
1892 vmcs_writel(sf->base, var->base);
1893 vmcs_write32(sf->limit, var->limit);
1894 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1895 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1896 /*
1897 * Hack real-mode segments into vm86 compatibility.
1898 */
1899 if (var->base == 0xffff0000 && var->selector == 0xf000)
1900 vmcs_writel(sf->base, 0xf0000);
1901 ar = 0xf3;
1902 } else
1903 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1904
1905 /*
1906 * Fix the "Accessed" bit in AR field of segment registers for older
1907 * qemu binaries.
1908 * IA32 arch specifies that at the time of processor reset the
1909 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1910 * is setting it to 0 in the usedland code. This causes invalid guest
1911 * state vmexit when "unrestricted guest" mode is turned on.
1912 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1913 * tree. Newer qemu binaries with that qemu fix would not need this
1914 * kvm hack.
1915 */
1916 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1917 ar |= 0x1; /* Accessed */
1918
6aa8b732
AK		 1919 vmcs_write32(sf->ar_bytes, ar);
1920}
1921
6aa8b732
AK		 1922static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1923{
1924 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1925
1926 *db = (ar >> 14) & 1;
1927 *l = (ar >> 13) & 1;
1928}
1929
1930static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1931{
1932 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1933 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1934}
1935
1936static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1937{
1938 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1939 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1940}
1941
1942static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1943{
1944 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1945 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1946}
1947
1948static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1949{
1950 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1951 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1952}
1953
648dfaa7
MG		 1954static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1955{
1956 struct kvm_segment var;
1957 u32 ar;
1958
1959 vmx_get_segment(vcpu, &var, seg);
1960 ar = vmx_segment_access_rights(&var);
1961
1962 if (var.base != (var.selector << 4))
1963 return false;
1964 if (var.limit != 0xffff)
1965 return false;
1966 if (ar != 0xf3)
1967 return false;
1968
1969 return true;
1970}
1971
1972static bool code_segment_valid(struct kvm_vcpu *vcpu)
1973{
1974 struct kvm_segment cs;
1975 unsigned int cs_rpl;
1976
1977 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1978 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1979
1872a3f4
AK		 1980 if (cs.unusable)
1981 return false;
648dfaa7
MG		 1982 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1983 return false;
1984 if (!cs.s)
1985 return false;
1872a3f4 1986 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1987 if (cs.dpl > cs_rpl)
1988 return false;
1872a3f4 1989 } else {
648dfaa7
MG		 1990 if (cs.dpl != cs_rpl)
1991 return false;
1992 }
1993 if (!cs.present)
1994 return false;
1995
1996 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1997 return true;
1998}
1999
2000static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2001{
2002 struct kvm_segment ss;
2003 unsigned int ss_rpl;
2004
2005 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2006 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2007
1872a3f4
AK		 2008 if (ss.unusable)
2009 return true;
2010 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2011 return false;
2012 if (!ss.s)
2013 return false;
2014 if (ss.dpl != ss_rpl) /* DPL != RPL */
2015 return false;
2016 if (!ss.present)
2017 return false;
2018
2019 return true;
2020}
2021
2022static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2023{
2024 struct kvm_segment var;
2025 unsigned int rpl;
2026
2027 vmx_get_segment(vcpu, &var, seg);
2028 rpl = var.selector & SELECTOR_RPL_MASK;
2029
1872a3f4
AK		 2030 if (var.unusable)
2031 return true;
648dfaa7
MG		 2032 if (!var.s)
2033 return false;
2034 if (!var.present)
2035 return false;
2036 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2037 if (var.dpl < rpl) /* DPL < RPL */
2038 return false;
2039 }
2040
2041 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2042 * rights flags
2043 */
2044 return true;
2045}
2046
2047static bool tr_valid(struct kvm_vcpu *vcpu)
2048{
2049 struct kvm_segment tr;
2050
2051 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2052
1872a3f4
AK		 2053 if (tr.unusable)
2054 return false;
648dfaa7
MG		 2055 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2056 return false;
1872a3f4 2057 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2058 return false;
2059 if (!tr.present)
2060 return false;
2061
2062 return true;
2063}
2064
2065static bool ldtr_valid(struct kvm_vcpu *vcpu)
2066{
2067 struct kvm_segment ldtr;
2068
2069 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2070
1872a3f4
AK		 2071 if (ldtr.unusable)
2072 return true;
648dfaa7
MG		 2073 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2074 return false;
2075 if (ldtr.type != 2)
2076 return false;
2077 if (!ldtr.present)
2078 return false;
2079
2080 return true;
2081}
2082
2083static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2084{
2085 struct kvm_segment cs, ss;
2086
2087 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2088 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2089
2090 return ((cs.selector & SELECTOR_RPL_MASK) ==
2091 (ss.selector & SELECTOR_RPL_MASK));
2092}
2093
2094/*
2095 * Check if guest state is valid. Returns true if valid, false if
2096 * not.
2097 * We assume that registers are always usable
2098 */
2099static bool guest_state_valid(struct kvm_vcpu *vcpu)
2100{
2101 /* real mode guest state checks */
3eeb3288 2102 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2103 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2104 return false;
2105 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2106 return false;
2107 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2108 return false;
2109 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2110 return false;
2111 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2112 return false;
2113 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2114 return false;
2115 } else {
2116 /* protected mode guest state checks */
2117 if (!cs_ss_rpl_check(vcpu))
2118 return false;
2119 if (!code_segment_valid(vcpu))
2120 return false;
2121 if (!stack_segment_valid(vcpu))
2122 return false;
2123 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2124 return false;
2125 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2126 return false;
2127 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2128 return false;
2129 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2130 return false;
2131 if (!tr_valid(vcpu))
2132 return false;
2133 if (!ldtr_valid(vcpu))
2134 return false;
2135 }
2136 /* TODO:
2137 * - Add checks on RIP
2138 * - Add checks on RFLAGS
2139 */
2140
2141 return true;
2142}
2143
d77c26fc 2144static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2145{
6aa8b732 2146 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2147 u16 data = 0;
10589a46 2148 int ret = 0;
195aefde 2149 int r;
6aa8b732 2150
195aefde
IE		 2151 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2152 if (r < 0)
10589a46 2153 goto out;
195aefde 2154 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2155 r = kvm_write_guest_page(kvm, fn++, &data,
2156 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2157 if (r < 0)
10589a46 2158 goto out;
195aefde
IE		 2159 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2160 if (r < 0)
10589a46 2161 goto out;
195aefde
IE		 2162 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2163 if (r < 0)
10589a46 2164 goto out;
195aefde 2165 data = ~0;
10589a46
MT		 2166 r = kvm_write_guest_page(kvm, fn, &data,
2167 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2168 sizeof(u8));
195aefde 2169 if (r < 0)
10589a46
MT		 2170 goto out;
2171
2172 ret = 1;
2173out:
10589a46 2174 return ret;
6aa8b732
AK		 2175}
2176
b7ebfb05
SY		 2177static int init_rmode_identity_map(struct kvm *kvm)
2178{
2179 int i, r, ret;
2180 pfn_t identity_map_pfn;
2181 u32 tmp;
2182
089d034e 2183 if (!enable_ept)
b7ebfb05
SY		 2184 return 1;
2185 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2186 printk(KERN_ERR "EPT: identity-mapping pagetable "
2187 "haven't been allocated!\n");
2188 return 0;
2189 }
2190 if (likely(kvm->arch.ept_identity_pagetable_done))
2191 return 1;
2192 ret = 0;
b927a3ce 2193 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2194 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2195 if (r < 0)
2196 goto out;
2197 /* Set up identity-mapping pagetable for EPT in real mode */
2198 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2199 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2200 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2201 r = kvm_write_guest_page(kvm, identity_map_pfn,
2202 &tmp, i * sizeof(tmp), sizeof(tmp));
2203 if (r < 0)
2204 goto out;
2205 }
2206 kvm->arch.ept_identity_pagetable_done = true;
2207 ret = 1;
2208out:
2209 return ret;
2210}
2211
6aa8b732
AK		 2212static void seg_setup(int seg)
2213{
2214 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2215 unsigned int ar;
6aa8b732
AK		 2216
2217 vmcs_write16(sf->selector, 0);
2218 vmcs_writel(sf->base, 0);
2219 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2220 if (enable_unrestricted_guest) {
2221 ar = 0x93;
2222 if (seg == VCPU_SREG_CS)
2223 ar |= 0x08; /* code segment */
2224 } else
2225 ar = 0xf3;
2226
2227 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2228}
2229
f78e0e2e
SY		 2230static int alloc_apic_access_page(struct kvm *kvm)
2231{
2232 struct kvm_userspace_memory_region kvm_userspace_mem;
2233 int r = 0;
2234
79fac95e 2235 mutex_lock(&kvm->slots_lock);
bfc6d222 2236 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2237 goto out;
2238 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2239 kvm_userspace_mem.flags = 0;
2240 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2241 kvm_userspace_mem.memory_size = PAGE_SIZE;
2242 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2243 if (r)
2244 goto out;
72dc67a6 2245
bfc6d222 2246 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2247out:
79fac95e 2248 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2249 return r;
2250}
2251
b7ebfb05
SY		 2252static int alloc_identity_pagetable(struct kvm *kvm)
2253{
2254 struct kvm_userspace_memory_region kvm_userspace_mem;
2255 int r = 0;
2256
79fac95e 2257 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2258 if (kvm->arch.ept_identity_pagetable)
2259 goto out;
2260 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2261 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2262 kvm_userspace_mem.guest_phys_addr =
2263 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2264 kvm_userspace_mem.memory_size = PAGE_SIZE;
2265 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2266 if (r)
2267 goto out;
2268
b7ebfb05 2269 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2270 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2271out:
79fac95e 2272 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2273 return r;
2274}
2275
2384d2b3
SY		 2276static void allocate_vpid(struct vcpu_vmx *vmx)
2277{
2278 int vpid;
2279
2280 vmx->vpid = 0;
919818ab 2281 if (!enable_vpid)
2384d2b3
SY		 2282 return;
2283 spin_lock(&vmx_vpid_lock);
2284 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2285 if (vpid < VMX_NR_VPIDS) {
2286 vmx->vpid = vpid;
2287 __set_bit(vpid, vmx_vpid_bitmap);
2288 }
2289 spin_unlock(&vmx_vpid_lock);
2290}
2291
5897297b 2292static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2293{
3e7c73e9 2294 int f = sizeof(unsigned long);
25c5f225
SY		 2295
2296 if (!cpu_has_vmx_msr_bitmap())
2297 return;
2298
2299 /*
2300 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2301 * have the write-low and read-high bitmap offsets the wrong way round.
2302 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2303 */
25c5f225 2304 if (msr <= 0x1fff) {
3e7c73e9
AK		 2305 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2306 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2307 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2308 msr &= 0x1fff;
3e7c73e9
AK		 2309 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2310 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2311 }
25c5f225
SY		 2312}
2313
5897297b
AK		 2314static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2315{
2316 if (!longmode_only)
2317 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2318 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2319}
2320
6aa8b732
AK		 2321/*
2322 * Sets up the vmcs for emulated real mode.
2323 */
8b9cf98c 2324static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2325{
468d472f 2326 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2327 u32 junk;
53f658b3 2328 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2329 unsigned long a;
2330 struct descriptor_table dt;
2331 int i;
cd2276a7 2332 unsigned long kvm_vmx_return;
6e5d865c 2333 u32 exec_control;
6aa8b732 2334
6aa8b732 2335 /* I/O */
3e7c73e9
AK		 2336 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2337 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2338
25c5f225 2339 if (cpu_has_vmx_msr_bitmap())
5897297b 2340 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2341
6aa8b732
AK		 2342 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2343
6aa8b732 2344 /* Control */
1c3d14fe
YS		 2345 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2346 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2347
2348 exec_control = vmcs_config.cpu_based_exec_ctrl;
2349 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2350 exec_control &= ~CPU_BASED_TPR_SHADOW;
2351#ifdef CONFIG_X86_64
2352 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2353 CPU_BASED_CR8_LOAD_EXITING;
2354#endif
2355 }
089d034e 2356 if (!enable_ept)
d56f546d 2357 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2358 CPU_BASED_CR3_LOAD_EXITING |
2359 CPU_BASED_INVLPG_EXITING;
6e5d865c 2360 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2361
83ff3b9d
SY		 2362 if (cpu_has_secondary_exec_ctrls()) {
2363 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2364 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2365 exec_control &=
2366 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2367 if (vmx->vpid == 0)
2368 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2369 if (!enable_ept) {
d56f546d 2370 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2371 enable_unrestricted_guest = 0;
2372 }
3a624e29
NK		 2373 if (!enable_unrestricted_guest)
2374 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2375 if (!ple_gap)
2376 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2377 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2378 }
f78e0e2e 2379
4b8d54f9
ZE		 2380 if (ple_gap) {
2381 vmcs_write32(PLE_GAP, ple_gap);
2382 vmcs_write32(PLE_WINDOW, ple_window);
2383 }
2384
c7addb90
AK		 2385 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2386 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2387 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2388
2389 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2390 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2391 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2392
2393 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2394 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2395 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2396 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2397 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2398 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2399#ifdef CONFIG_X86_64
6aa8b732
AK		 2400 rdmsrl(MSR_FS_BASE, a);
2401 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2402 rdmsrl(MSR_GS_BASE, a);
2403 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2404#else
2405 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2406 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2407#endif
2408
2409 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2410
d6e88aec 2411 kvm_get_idt(&dt);
6aa8b732
AK		 2412 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2413
d77c26fc 2414 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2415 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2416 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2417 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2418 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2419
2420 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2421 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2422 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2423 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2424 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2425 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2426
468d472f
SY		 2427 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2428 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2429 host_pat = msr_low | ((u64) msr_high << 32);
2430 vmcs_write64(HOST_IA32_PAT, host_pat);
2431 }
2432 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2433 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2434 host_pat = msr_low | ((u64) msr_high << 32);
2435 /* Write the default value follow host pat */
2436 vmcs_write64(GUEST_IA32_PAT, host_pat);
2437 /* Keep arch.pat sync with GUEST_IA32_PAT */
2438 vmx->vcpu.arch.pat = host_pat;
2439 }
2440
6aa8b732
AK		 2441 for (i = 0; i < NR_VMX_MSR; ++i) {
2442 u32 index = vmx_msr_index[i];
2443 u32 data_low, data_high;
a2fa3e9f 2444 int j = vmx->nmsrs;
6aa8b732
AK		 2445
2446 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2447 continue;
432bd6cb
AK		 2448 if (wrmsr_safe(index, data_low, data_high) < 0)
2449 continue;
26bb0981
AK		 2450 vmx->guest_msrs[j].index = i;
2451 vmx->guest_msrs[j].data = 0;
d5696725 2452 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2453 ++vmx->nmsrs;
6aa8b732 2454 }
6aa8b732 2455
1c3d14fe 2456 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2457
2458 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2459 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2460
e00c8cf2 2461 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2462 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2463 if (enable_ept)
2464 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2465 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2466
53f658b3
MT		 2467 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2468 rdtscll(tsc_this);
2469 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2470 tsc_base = tsc_this;
2471
2472 guest_write_tsc(0, tsc_base);
f78e0e2e 2473
e00c8cf2
AK		 2474 return 0;
2475}
2476
b7ebfb05
SY		 2477static int init_rmode(struct kvm *kvm)
2478{
2479 if (!init_rmode_tss(kvm))
2480 return 0;
2481 if (!init_rmode_identity_map(kvm))
2482 return 0;
2483 return 1;
2484}
2485
e00c8cf2
AK		 2486static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2487{
2488 struct vcpu_vmx *vmx = to_vmx(vcpu);
2489 u64 msr;
f656ce01 2490 int ret, idx;
e00c8cf2 2491
5fdbf976 2492 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2493 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2494 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2495 ret = -ENOMEM;
2496 goto out;
2497 }
2498
7ffd92c5 2499 vmx->rmode.vm86_active = 0;
e00c8cf2 2500
3b86cd99
JK		 2501 vmx->soft_vnmi_blocked = 0;
2502
ad312c7c 2503 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2504 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2505 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2506 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2507 msr |= MSR_IA32_APICBASE_BSP;
2508 kvm_set_apic_base(&vmx->vcpu, msr);
2509
2510 fx_init(&vmx->vcpu);
2511
5706be0d 2512 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2513 /*
2514 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2515 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2516 */
c5af89b6 2517 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2518 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2519 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2520 } else {
ad312c7c
ZX		 2521 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2522 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2523 }
e00c8cf2
AK		 2524
2525 seg_setup(VCPU_SREG_DS);
2526 seg_setup(VCPU_SREG_ES);
2527 seg_setup(VCPU_SREG_FS);
2528 seg_setup(VCPU_SREG_GS);
2529 seg_setup(VCPU_SREG_SS);
2530
2531 vmcs_write16(GUEST_TR_SELECTOR, 0);
2532 vmcs_writel(GUEST_TR_BASE, 0);
2533 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2534 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2535
2536 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2537 vmcs_writel(GUEST_LDTR_BASE, 0);
2538 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2539 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2540
2541 vmcs_write32(GUEST_SYSENTER_CS, 0);
2542 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2543 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2544
2545 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2546 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2547 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2548 else
5fdbf976
MT		 2549 kvm_rip_write(vcpu, 0);
2550 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2551
e00c8cf2
AK		 2552 vmcs_writel(GUEST_DR7, 0x400);
2553
2554 vmcs_writel(GUEST_GDTR_BASE, 0);
2555 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2556
2557 vmcs_writel(GUEST_IDTR_BASE, 0);
2558 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2559
2560 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2561 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2562 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2563
e00c8cf2
AK		 2564 /* Special registers */
2565 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2566
2567 setup_msrs(vmx);
2568
6aa8b732
AK		 2569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2570
f78e0e2e
SY		 2571 if (cpu_has_vmx_tpr_shadow()) {
2572 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2573 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2574 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2575 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2576 vmcs_write32(TPR_THRESHOLD, 0);
2577 }
2578
2579 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2580 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2581 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2582
2384d2b3
SY		 2583 if (vmx->vpid != 0)
2584 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2585
fa40052c 2586 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2587 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2588 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2589 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2590 vmx_fpu_activate(&vmx->vcpu);
2591 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2592
2384d2b3
SY		 2593 vpid_sync_vcpu_all(vmx);
2594
3200f405 2595 ret = 0;
6aa8b732 2596
a89a8fb9
MG		 2597 /* HACK: Don't enable emulation on guest boot/reset */
2598 vmx->emulation_required = 0;
2599
6aa8b732 2600out:
f656ce01 2601 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2602 return ret;
2603}
2604
3b86cd99
JK		 2605static void enable_irq_window(struct kvm_vcpu *vcpu)
2606{
2607 u32 cpu_based_vm_exec_control;
2608
2609 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2610 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2611 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2612}
2613
2614static void enable_nmi_window(struct kvm_vcpu *vcpu)
2615{
2616 u32 cpu_based_vm_exec_control;
2617
2618 if (!cpu_has_virtual_nmis()) {
2619 enable_irq_window(vcpu);
2620 return;
2621 }
2622
2623 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2624 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2625 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2626}
2627
66fd3f7f 2628static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2629{
9c8cba37 2630 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2631 uint32_t intr;
2632 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2633
229456fc 2634 trace_kvm_inj_virq(irq);
2714d1d3 2635
fa89a817 2636 ++vcpu->stat.irq_injections;
7ffd92c5 2637 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2638 vmx->rmode.irq.pending = true;
2639 vmx->rmode.irq.vector = irq;
5fdbf976 2640 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2641 if (vcpu->arch.interrupt.soft)
2642 vmx->rmode.irq.rip +=
2643 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2645 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2646 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2647 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2648 return;
2649 }
66fd3f7f
GN		 2650 intr = irq | INTR_INFO_VALID_MASK;
2651 if (vcpu->arch.interrupt.soft) {
2652 intr |= INTR_TYPE_SOFT_INTR;
2653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2654 vmx->vcpu.arch.event_exit_inst_len);
2655 } else
2656 intr |= INTR_TYPE_EXT_INTR;
2657 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2658}
2659
f08864b4
SY		 2660static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2661{
66a5a347
JK		 2662 struct vcpu_vmx *vmx = to_vmx(vcpu);
2663
3b86cd99
JK		 2664 if (!cpu_has_virtual_nmis()) {
2665 /*
2666 * Tracking the NMI-blocked state in software is built upon
2667 * finding the next open IRQ window. This, in turn, depends on
2668 * well-behaving guests: They have to keep IRQs disabled at
2669 * least as long as the NMI handler runs. Otherwise we may
2670 * cause NMI nesting, maybe breaking the guest. But as this is
2671 * highly unlikely, we can live with the residual risk.
2672 */
2673 vmx->soft_vnmi_blocked = 1;
2674 vmx->vnmi_blocked_time = 0;
2675 }
2676
487b391d 2677 ++vcpu->stat.nmi_injections;
7ffd92c5 2678 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2679 vmx->rmode.irq.pending = true;
2680 vmx->rmode.irq.vector = NMI_VECTOR;
2681 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2682 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2683 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2684 INTR_INFO_VALID_MASK);
2685 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2686 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2687 return;
2688 }
f08864b4
SY		 2689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2690 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2691}
2692
c4282df9 2693static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2694{
3b86cd99 2695 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2696 return 0;
33f089ca 2697
c4282df9
GN		 2698 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2699 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2700 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2701}
2702
3cfc3092
JK		 2703static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2704{
2705 if (!cpu_has_virtual_nmis())
2706 return to_vmx(vcpu)->soft_vnmi_blocked;
2707 else
2708 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2709 GUEST_INTR_STATE_NMI);
2710}
2711
2712static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2713{
2714 struct vcpu_vmx *vmx = to_vmx(vcpu);
2715
2716 if (!cpu_has_virtual_nmis()) {
2717 if (vmx->soft_vnmi_blocked != masked) {
2718 vmx->soft_vnmi_blocked = masked;
2719 vmx->vnmi_blocked_time = 0;
2720 }
2721 } else {
2722 if (masked)
2723 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2724 GUEST_INTR_STATE_NMI);
2725 else
2726 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2727 GUEST_INTR_STATE_NMI);
2728 }
2729}
2730
78646121
GN		 2731static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2732{
c4282df9
GN		 2733 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2734 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2735 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2736}
2737
cbc94022
IE		 2738static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2739{
2740 int ret;
2741 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2742 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2743 .guest_phys_addr = addr,
2744 .memory_size = PAGE_SIZE * 3,
2745 .flags = 0,
2746 };
2747
2748 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2749 if (ret)
2750 return ret;
bfc6d222 2751 kvm->arch.tss_addr = addr;
cbc94022
IE		 2752 return 0;
2753}
2754
6aa8b732
AK		 2755static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2756 int vec, u32 err_code)
2757{
b3f37707
NK		 2758 /*
2759 * Instruction with address size override prefix opcode 0x67
2760 * Cause the #SS fault with 0 error code in VM86 mode.
2761 */
2762 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2763 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2764 return 1;
77ab6db0
JK		 2765 /*
2766 * Forward all other exceptions that are valid in real mode.
2767 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2768 * the required debugging infrastructure rework.
2769 */
2770 switch (vec) {
77ab6db0 2771 case DB_VECTOR:
d0bfb940
JK		 2772 if (vcpu->guest_debug &
2773 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2774 return 0;
2775 kvm_queue_exception(vcpu, vec);
2776 return 1;
77ab6db0 2777 case BP_VECTOR:
c573cd22
JK		 2778 /*
2779 * Update instruction length as we may reinject the exception
2780 * from user space while in guest debugging mode.
2781 */
2782 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2783 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2784 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2785 return 0;
2786 /* fall through */
2787 case DE_VECTOR:
77ab6db0
JK		 2788 case OF_VECTOR:
2789 case BR_VECTOR:
2790 case UD_VECTOR:
2791 case DF_VECTOR:
2792 case SS_VECTOR:
2793 case GP_VECTOR:
2794 case MF_VECTOR:
2795 kvm_queue_exception(vcpu, vec);
2796 return 1;
2797 }
6aa8b732
AK		 2798 return 0;
2799}
2800
a0861c02
AK		 2801/*
2802 * Trigger machine check on the host. We assume all the MSRs are already set up
2803 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2804 * We pass a fake environment to the machine check handler because we want
2805 * the guest to be always treated like user space, no matter what context
2806 * it used internally.
2807 */
2808static void kvm_machine_check(void)
2809{
2810#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2811 struct pt_regs regs = {
2812 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2813 .flags = X86_EFLAGS_IF,
2814 };
2815
2816 do_machine_check(&regs, 0);
2817#endif
2818}
2819
851ba692 2820static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2821{
2822 /* already handled by vcpu_run */
2823 return 1;
2824}
2825
851ba692 2826static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2827{
1155f76a 2828 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2829 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2830 u32 intr_info, ex_no, error_code;
42dbaa5a 2831 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2832 u32 vect_info;
2833 enum emulation_result er;
2834
1155f76a 2835 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2836 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2837
a0861c02 2838 if (is_machine_check(intr_info))
851ba692 2839 return handle_machine_check(vcpu);
a0861c02 2840
6aa8b732 2841 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2842 !is_page_fault(intr_info)) {
2843 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2844 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2845 vcpu->run->internal.ndata = 2;
2846 vcpu->run->internal.data[0] = vect_info;
2847 vcpu->run->internal.data[1] = intr_info;
2848 return 0;
2849 }
6aa8b732 2850
e4a41889 2851 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2852 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2853
2854 if (is_no_device(intr_info)) {
5fd86fcf 2855 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2856 return 1;
2857 }
2858
7aa81cc0 2859 if (is_invalid_opcode(intr_info)) {
851ba692 2860 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2861 if (er != EMULATE_DONE)
7ee5d940 2862 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2863 return 1;
2864 }
2865
6aa8b732 2866 error_code = 0;
5fdbf976 2867 rip = kvm_rip_read(vcpu);
2e11384c 2868 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2869 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2870 if (is_page_fault(intr_info)) {
1439442c 2871 /* EPT won't cause page fault directly */
089d034e 2872 if (enable_ept)
1439442c 2873 BUG();
6aa8b732 2874 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2875 trace_kvm_page_fault(cr2, error_code);
2876
3298b75c 2877 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2878 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2879 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2880 }
2881
7ffd92c5 2882 if (vmx->rmode.vm86_active &&
6aa8b732 2883 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2884 error_code)) {
ad312c7c
ZX		 2885 if (vcpu->arch.halt_request) {
2886 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2887 return kvm_emulate_halt(vcpu);
2888 }
6aa8b732 2889 return 1;
72d6e5a0 2890 }
6aa8b732 2891
d0bfb940 2892 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2893 switch (ex_no) {
2894 case DB_VECTOR:
2895 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2896 if (!(vcpu->guest_debug &
2897 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2898 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2899 kvm_queue_exception(vcpu, DB_VECTOR);
2900 return 1;
2901 }
2902 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2903 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2904 /* fall through */
2905 case BP_VECTOR:
c573cd22
JK		 2906 /*
2907 * Update instruction length as we may reinject #BP from
2908 * user space while in guest debugging mode. Reading it for
2909 * #DB as well causes no harm, it is not used in that case.
2910 */
2911 vmx->vcpu.arch.event_exit_inst_len =
2912 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 2913 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2914 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2915 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2916 break;
2917 default:
d0bfb940
JK		 2918 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2919 kvm_run->ex.exception = ex_no;
2920 kvm_run->ex.error_code = error_code;
42dbaa5a 2921 break;
6aa8b732 2922 }
6aa8b732
AK		 2923 return 0;
2924}
2925
851ba692 2926static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2927{
1165f5fe 2928 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2929 return 1;
2930}
2931
851ba692 2932static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2933{
851ba692 2934 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2935 return 0;
2936}
6aa8b732 2937
851ba692 2938static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2939{
bfdaab09 2940 unsigned long exit_qualification;
34c33d16 2941 int size, in, string;
039576c0 2942 unsigned port;
6aa8b732 2943
1165f5fe 2944 ++vcpu->stat.io_exits;
bfdaab09 2945 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2946 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2947
2948 if (string) {
851ba692 2949 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2950 return 0;
2951 return 1;
2952 }
2953
2954 size = (exit_qualification & 7) + 1;
2955 in = (exit_qualification & 8) != 0;
039576c0 2956 port = exit_qualification >> 16;
e70669ab 2957
e93f36bc 2958 skip_emulated_instruction(vcpu);
851ba692 2959 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2960}
2961
102d8325
IM		 2962static void
2963vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2964{
2965 /*
2966 * Patch in the VMCALL instruction:
2967 */
2968 hypercall[0] = 0x0f;
2969 hypercall[1] = 0x01;
2970 hypercall[2] = 0xc1;
102d8325
IM		 2971}
2972
851ba692 2973static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2974{
229456fc 2975 unsigned long exit_qualification, val;
6aa8b732
AK		 2976 int cr;
2977 int reg;
2978
bfdaab09 2979 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2980 cr = exit_qualification & 15;
2981 reg = (exit_qualification >> 8) & 15;
2982 switch ((exit_qualification >> 4) & 3) {
2983 case 0: /* mov to cr */
229456fc
MT		 2984 val = kvm_register_read(vcpu, reg);
2985 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2986 switch (cr) {
2987 case 0:
229456fc 2988 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2989 skip_emulated_instruction(vcpu);
2990 return 1;
2991 case 3:
229456fc 2992 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2993 skip_emulated_instruction(vcpu);
2994 return 1;
2995 case 4:
229456fc 2996 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2997 skip_emulated_instruction(vcpu);
2998 return 1;
0a5fff19
GN		 2999 case 8: {
3000 u8 cr8_prev = kvm_get_cr8(vcpu);
3001 u8 cr8 = kvm_register_read(vcpu, reg);
3002 kvm_set_cr8(vcpu, cr8);
3003 skip_emulated_instruction(vcpu);
3004 if (irqchip_in_kernel(vcpu->kvm))
3005 return 1;
3006 if (cr8_prev <= cr8)
3007 return 1;
851ba692 3008 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3009 return 0;
3010 }
6aa8b732
AK		 3011 };
3012 break;
25c4c276 3013 case 2: /* clts */
edcafe3c 3014 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3015 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3016 skip_emulated_instruction(vcpu);
6b52d186 3017 vmx_fpu_activate(vcpu);
25c4c276 3018 return 1;
6aa8b732
AK		 3019 case 1: /*mov from cr*/
3020 switch (cr) {
3021 case 3:
5fdbf976 3022 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3023 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3024 skip_emulated_instruction(vcpu);
3025 return 1;
3026 case 8:
229456fc
MT		 3027 val = kvm_get_cr8(vcpu);
3028 kvm_register_write(vcpu, reg, val);
3029 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3030 skip_emulated_instruction(vcpu);
3031 return 1;
3032 }
3033 break;
3034 case 3: /* lmsw */
a1f83a74 3035 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3036 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3037 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3038
3039 skip_emulated_instruction(vcpu);
3040 return 1;
3041 default:
3042 break;
3043 }
851ba692 3044 vcpu->run->exit_reason = 0;
f0242478 3045 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3046 (int)(exit_qualification >> 4) & 3, cr);
3047 return 0;
3048}
3049
138ac8d8
JK		 3050static int check_dr_alias(struct kvm_vcpu *vcpu)
3051{
3052 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3053 kvm_queue_exception(vcpu, UD_VECTOR);
3054 return -1;
3055 }
3056 return 0;
3057}
3058
851ba692 3059static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3060{
bfdaab09 3061 unsigned long exit_qualification;
6aa8b732
AK		 3062 unsigned long val;
3063 int dr, reg;
3064
f2483415 3065 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3066 if (!kvm_require_cpl(vcpu, 0))
3067 return 1;
42dbaa5a
JK		 3068 dr = vmcs_readl(GUEST_DR7);
3069 if (dr & DR7_GD) {
3070 /*
3071 * As the vm-exit takes precedence over the debug trap, we
3072 * need to emulate the latter, either for the host or the
3073 * guest debugging itself.
3074 */
3075 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3076 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3077 vcpu->run->debug.arch.dr7 = dr;
3078 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3079 vmcs_readl(GUEST_CS_BASE) +
3080 vmcs_readl(GUEST_RIP);
851ba692
AK		 3081 vcpu->run->debug.arch.exception = DB_VECTOR;
3082 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3083 return 0;
3084 } else {
3085 vcpu->arch.dr7 &= ~DR7_GD;
3086 vcpu->arch.dr6 |= DR6_BD;
3087 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3088 kvm_queue_exception(vcpu, DB_VECTOR);
3089 return 1;
3090 }
3091 }
3092
bfdaab09 3093 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3094 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3095 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3096 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3097 switch (dr) {
42dbaa5a
JK		 3098 case 0 ... 3:
3099 val = vcpu->arch.db[dr];
3100 break;
138ac8d8
JK		 3101 case 4:
3102 if (check_dr_alias(vcpu) < 0)
3103 return 1;
3104 /* fall through */
6aa8b732 3105 case 6:
42dbaa5a 3106 val = vcpu->arch.dr6;
6aa8b732 3107 break;
138ac8d8
JK		 3108 case 5:
3109 if (check_dr_alias(vcpu) < 0)
3110 return 1;
3111 /* fall through */
3112 default: /* 7 */
42dbaa5a 3113 val = vcpu->arch.dr7;
6aa8b732 3114 break;
6aa8b732 3115 }
5fdbf976 3116 kvm_register_write(vcpu, reg, val);
6aa8b732 3117 } else {
42dbaa5a
JK		 3118 val = vcpu->arch.regs[reg];
3119 switch (dr) {
3120 case 0 ... 3:
3121 vcpu->arch.db[dr] = val;
3122 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3123 vcpu->arch.eff_db[dr] = val;
3124 break;
138ac8d8
JK		 3125 case 4:
3126 if (check_dr_alias(vcpu) < 0)
f2483415 3127 return 1;
138ac8d8 3128 /* fall through */
42dbaa5a
JK		 3129 case 6:
3130 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3131 kvm_inject_gp(vcpu, 0);
3132 return 1;
42dbaa5a
JK		 3133 }
3134 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3135 break;
138ac8d8
JK		 3136 case 5:
3137 if (check_dr_alias(vcpu) < 0)
3138 return 1;
3139 /* fall through */
3140 default: /* 7 */
42dbaa5a 3141 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3142 kvm_inject_gp(vcpu, 0);
3143 return 1;
42dbaa5a
JK		 3144 }
3145 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3146 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3147 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3148 vcpu->arch.switch_db_regs =
3149 (val & DR7_BP_EN_MASK);
3150 }
3151 break;
3152 }
6aa8b732 3153 }
6aa8b732
AK		 3154 skip_emulated_instruction(vcpu);
3155 return 1;
3156}
3157
851ba692 3158static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3159{
06465c5a
AK		 3160 kvm_emulate_cpuid(vcpu);
3161 return 1;
6aa8b732
AK		 3162}
3163
851ba692 3164static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3165{
ad312c7c 3166 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3167 u64 data;
3168
3169 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3170 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3171 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3172 return 1;
3173 }
3174
229456fc 3175 trace_kvm_msr_read(ecx, data);
2714d1d3 3176
6aa8b732 3177 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3178 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3179 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3180 skip_emulated_instruction(vcpu);
3181 return 1;
3182}
3183
851ba692 3184static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3185{
ad312c7c
ZX		 3186 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3187 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3188 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3189
3190 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3191 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3192 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3193 return 1;
3194 }
3195
59200273 3196 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3197 skip_emulated_instruction(vcpu);
3198 return 1;
3199}
3200
851ba692 3201static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3202{
3203 return 1;
3204}
3205
851ba692 3206static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3207{
85f455f7
ED		 3208 u32 cpu_based_vm_exec_control;
3209
3210 /* clear pending irq */
3211 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3212 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3213 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3214
a26bf12a 3215 ++vcpu->stat.irq_window_exits;
2714d1d3 3216
c1150d8c
DL		 3217 /*
3218 * If the user space waits to inject interrupts, exit as soon as
3219 * possible
3220 */
8061823a 3221 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3222 vcpu->run->request_interrupt_window &&
8061823a 3223 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3224 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3225 return 0;
3226 }
6aa8b732
AK		 3227 return 1;
3228}
3229
851ba692 3230static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3231{
3232 skip_emulated_instruction(vcpu);
d3bef15f 3233 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3234}
3235
851ba692 3236static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3237{
510043da 3238 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3239 kvm_emulate_hypercall(vcpu);
3240 return 1;
c21415e8
IM		 3241}
3242
851ba692 3243static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3244{
3245 kvm_queue_exception(vcpu, UD_VECTOR);
3246 return 1;
3247}
3248
851ba692 3249static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3250{
f9c617f6 3251 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3252
3253 kvm_mmu_invlpg(vcpu, exit_qualification);
3254 skip_emulated_instruction(vcpu);
3255 return 1;
3256}
3257
851ba692 3258static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3259{
3260 skip_emulated_instruction(vcpu);
3261 /* TODO: Add support for VT-d/pass-through device */
3262 return 1;
3263}
3264
851ba692 3265static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3266{
f9c617f6 3267 unsigned long exit_qualification;
f78e0e2e
SY		 3268 enum emulation_result er;
3269 unsigned long offset;
3270
f9c617f6 3271 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3272 offset = exit_qualification & 0xffful;
3273
851ba692 3274 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3275
3276 if (er != EMULATE_DONE) {
3277 printk(KERN_ERR
3278 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3279 offset);
7f582ab6 3280 return -ENOEXEC;
f78e0e2e
SY		 3281 }
3282 return 1;
3283}
3284
851ba692 3285static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3286{
60637aac 3287 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3288 unsigned long exit_qualification;
3289 u16 tss_selector;
64a7ec06
GN		 3290 int reason, type, idt_v;
3291
3292 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3293 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3294
3295 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3296
3297 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3298 if (reason == TASK_SWITCH_GATE && idt_v) {
3299 switch (type) {
3300 case INTR_TYPE_NMI_INTR:
3301 vcpu->arch.nmi_injected = false;
3302 if (cpu_has_virtual_nmis())
3303 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3304 GUEST_INTR_STATE_NMI);
3305 break;
3306 case INTR_TYPE_EXT_INTR:
66fd3f7f 3307 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3308 kvm_clear_interrupt_queue(vcpu);
3309 break;
3310 case INTR_TYPE_HARD_EXCEPTION:
3311 case INTR_TYPE_SOFT_EXCEPTION:
3312 kvm_clear_exception_queue(vcpu);
3313 break;
3314 default:
3315 break;
3316 }
60637aac 3317 }
37817f29
IE		 3318 tss_selector = exit_qualification;
3319
64a7ec06
GN		 3320 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3321 type != INTR_TYPE_EXT_INTR &&
3322 type != INTR_TYPE_NMI_INTR))
3323 skip_emulated_instruction(vcpu);
3324
42dbaa5a
JK		 3325 if (!kvm_task_switch(vcpu, tss_selector, reason))
3326 return 0;
3327
3328 /* clear all local breakpoint enable flags */
3329 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3330
3331 /*
3332 * TODO: What about debug traps on tss switch?
3333 * Are we supposed to inject them and update dr6?
3334 */
3335
3336 return 1;
37817f29
IE		 3337}
3338
851ba692 3339static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3340{
f9c617f6 3341 unsigned long exit_qualification;
1439442c 3342 gpa_t gpa;
1439442c 3343 int gla_validity;
1439442c 3344
f9c617f6 3345 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3346
3347 if (exit_qualification & (1 << 6)) {
3348 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3349 return -EINVAL;
1439442c
SY		 3350 }
3351
3352 gla_validity = (exit_qualification >> 7) & 0x3;
3353 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3354 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3355 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3356 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3357 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3358 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3359 (long unsigned int)exit_qualification);
851ba692
AK		 3360 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3361 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3362 return 0;
1439442c
SY		 3363 }
3364
3365 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3366 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3367 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3368}
3369
68f89400
MT		 3370static u64 ept_rsvd_mask(u64 spte, int level)
3371{
3372 int i;
3373 u64 mask = 0;
3374
3375 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3376 mask |= (1ULL << i);
3377
3378 if (level > 2)
3379 /* bits 7:3 reserved */
3380 mask |= 0xf8;
3381 else if (level == 2) {
3382 if (spte & (1ULL << 7))
3383 /* 2MB ref, bits 20:12 reserved */
3384 mask |= 0x1ff000;
3385 else
3386 /* bits 6:3 reserved */
3387 mask |= 0x78;
3388 }
3389
3390 return mask;
3391}
3392
3393static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3394 int level)
3395{
3396 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3397
3398 /* 010b (write-only) */
3399 WARN_ON((spte & 0x7) == 0x2);
3400
3401 /* 110b (write/execute) */
3402 WARN_ON((spte & 0x7) == 0x6);
3403
3404 /* 100b (execute-only) and value not supported by logical processor */
3405 if (!cpu_has_vmx_ept_execute_only())
3406 WARN_ON((spte & 0x7) == 0x4);
3407
3408 /* not 000b */
3409 if ((spte & 0x7)) {
3410 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3411
3412 if (rsvd_bits != 0) {
3413 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3414 __func__, rsvd_bits);
3415 WARN_ON(1);
3416 }
3417
3418 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3419 u64 ept_mem_type = (spte & 0x38) >> 3;
3420
3421 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3422 ept_mem_type == 7) {
3423 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3424 __func__, ept_mem_type);
3425 WARN_ON(1);
3426 }
3427 }
3428 }
3429}
3430
851ba692 3431static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3432{
3433 u64 sptes[4];
3434 int nr_sptes, i;
3435 gpa_t gpa;
3436
3437 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3438
3439 printk(KERN_ERR "EPT: Misconfiguration.\n");
3440 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3441
3442 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3443
3444 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3445 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3446
851ba692
AK		 3447 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3448 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3449
3450 return 0;
3451}
3452
851ba692 3453static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3454{
3455 u32 cpu_based_vm_exec_control;
3456
3457 /* clear pending NMI */
3458 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3459 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3461 ++vcpu->stat.nmi_window_exits;
3462
3463 return 1;
3464}
3465
80ced186 3466static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3467{
8b3079a5
AK		 3468 struct vcpu_vmx *vmx = to_vmx(vcpu);
3469 enum emulation_result err = EMULATE_DONE;
80ced186 3470 int ret = 1;
ea953ef0
MG		 3471
3472 while (!guest_state_valid(vcpu)) {
851ba692 3473 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3474
80ced186
MG		 3475 if (err == EMULATE_DO_MMIO) {
3476 ret = 0;
3477 goto out;
3478 }
1d5a4d9b
GT		 3479
3480 if (err != EMULATE_DONE) {
80ced186
MG		 3481 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3482 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3483 vcpu->run->internal.ndata = 0;
80ced186
MG		 3484 ret = 0;
3485 goto out;
ea953ef0
MG		 3486 }
3487
3488 if (signal_pending(current))
80ced186 3489 goto out;
ea953ef0
MG		 3490 if (need_resched())
3491 schedule();
3492 }
3493
80ced186
MG		 3494 vmx->emulation_required = 0;
3495out:
3496 return ret;
ea953ef0
MG		 3497}
3498
4b8d54f9
ZE		 3499/*
3500 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3501 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3502 */
9fb41ba8 3503static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3504{
3505 skip_emulated_instruction(vcpu);
3506 kvm_vcpu_on_spin(vcpu);
3507
3508 return 1;
3509}
3510
59708670
SY		 3511static int handle_invalid_op(struct kvm_vcpu *vcpu)
3512{
3513 kvm_queue_exception(vcpu, UD_VECTOR);
3514 return 1;
3515}
3516
6aa8b732
AK		 3517/*
3518 * The exit handlers return 1 if the exit was handled fully and guest execution
3519 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3520 * to be done to userspace and return 0.
3521 */
851ba692 3522static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3523 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3524 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3525 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3526 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3527 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3528 [EXIT_REASON_CR_ACCESS] = handle_cr,
3529 [EXIT_REASON_DR_ACCESS] = handle_dr,
3530 [EXIT_REASON_CPUID] = handle_cpuid,
3531 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3532 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3533 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3534 [EXIT_REASON_HLT] = handle_halt,
a7052897 3535 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3536 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3537 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3538 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3539 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3540 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3541 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3542 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3543 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3544 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3545 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3546 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3547 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3548 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3549 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3550 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3551 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3552 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3553 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3554 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3555 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3556};
3557
3558static const int kvm_vmx_max_exit_handlers =
50a3485c 3559 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3560
3561/*
3562 * The guest has exited. See if we can fix it or if we need userspace
3563 * assistance.
3564 */
851ba692 3565static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3566{
29bd8a78 3567 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3568 u32 exit_reason = vmx->exit_reason;
1155f76a 3569 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3570
229456fc 3571 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3572
80ced186
MG		 3573 /* If guest state is invalid, start emulating */
3574 if (vmx->emulation_required && emulate_invalid_guest_state)
3575 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3576
1439442c
SY		 3577 /* Access CR3 don't cause VMExit in paging mode, so we need
3578 * to sync with guest real CR3. */
6de4f3ad 3579 if (enable_ept && is_paging(vcpu))
1439442c 3580 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3581
29bd8a78 3582 if (unlikely(vmx->fail)) {
851ba692
AK		 3583 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3584 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3585 = vmcs_read32(VM_INSTRUCTION_ERROR);
3586 return 0;
3587 }
6aa8b732 3588
d77c26fc 3589 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3590 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3591 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3592 exit_reason != EXIT_REASON_TASK_SWITCH))
3593 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3594 "(0x%x) and exit reason is 0x%x\n",
3595 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3596
3597 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3598 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3599 vmx->soft_vnmi_blocked = 0;
3b86cd99 3600 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3601 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3602 /*
3603 * This CPU don't support us in finding the end of an
3604 * NMI-blocked window if the guest runs with IRQs
3605 * disabled. So we pull the trigger after 1 s of
3606 * futile waiting, but inform the user about this.
3607 */
3608 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3609 "state on VCPU %d after 1 s timeout\n",
3610 __func__, vcpu->vcpu_id);
3611 vmx->soft_vnmi_blocked = 0;
3b86cd99 3612 }
3b86cd99
JK		 3613 }
3614
6aa8b732
AK		 3615 if (exit_reason < kvm_vmx_max_exit_handlers
3616 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3617 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3618 else {
851ba692
AK		 3619 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3620 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3621 }
3622 return 0;
3623}
3624
95ba8273 3625static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3626{
95ba8273 3627 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3628 vmcs_write32(TPR_THRESHOLD, 0);
3629 return;
3630 }
3631
95ba8273 3632 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3633}
3634
cf393f75
AK		 3635static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3636{
3637 u32 exit_intr_info;
7b4a25cb 3638 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3639 bool unblock_nmi;
3640 u8 vector;
668f612f
AK		 3641 int type;
3642 bool idtv_info_valid;
cf393f75
AK		 3643
3644 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3645
a0861c02
AK		 3646 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3647
3648 /* Handle machine checks before interrupts are enabled */
3649 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3650 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3651 && is_machine_check(exit_intr_info)))
3652 kvm_machine_check();
3653
20f65983
GN		 3654 /* We need to handle NMIs before interrupts are enabled */
3655 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3656 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3657 asm("int $2");
20f65983
GN		 3658
3659 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3660
cf393f75
AK		 3661 if (cpu_has_virtual_nmis()) {
3662 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3663 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3664 /*
7b4a25cb 3665 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3666 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3667 * a guest IRET fault.
7b4a25cb
GN		 3668 * SDM 3: 23.2.2 (September 2008)
3669 * Bit 12 is undefined in any of the following cases:
3670 * If the VM exit sets the valid bit in the IDT-vectoring
3671 * information field.
3672 * If the VM exit is due to a double fault.
cf393f75 3673 */
7b4a25cb
GN		 3674 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3675 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3677 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3678 } else if (unlikely(vmx->soft_vnmi_blocked))
3679 vmx->vnmi_blocked_time +=
3680 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3681
37b96e98
GN		 3682 vmx->vcpu.arch.nmi_injected = false;
3683 kvm_clear_exception_queue(&vmx->vcpu);
3684 kvm_clear_interrupt_queue(&vmx->vcpu);
3685
3686 if (!idtv_info_valid)
3687 return;
3688
668f612f
AK		 3689 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3690 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3691
64a7ec06 3692 switch (type) {
37b96e98
GN		 3693 case INTR_TYPE_NMI_INTR:
3694 vmx->vcpu.arch.nmi_injected = true;
668f612f 3695 /*
7b4a25cb 3696 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3697 * Clear bit "block by NMI" before VM entry if a NMI
3698 * delivery faulted.
668f612f 3699 */
37b96e98
GN		 3700 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3701 GUEST_INTR_STATE_NMI);
3702 break;
37b96e98 3703 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3704 vmx->vcpu.arch.event_exit_inst_len =
3705 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3706 /* fall through */
3707 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3708 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3709 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3710 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3711 } else
3712 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3713 break;
66fd3f7f
GN		 3714 case INTR_TYPE_SOFT_INTR:
3715 vmx->vcpu.arch.event_exit_inst_len =
3716 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3717 /* fall through */
37b96e98 3718 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3719 kvm_queue_interrupt(&vmx->vcpu, vector,
3720 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3721 break;
3722 default:
3723 break;
f7d9238f 3724 }
cf393f75
AK		 3725}
3726
9c8cba37
AK		 3727/*
3728 * Failure to inject an interrupt should give us the information
3729 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3730 * when fetching the interrupt redirection bitmap in the real-mode
3731 * tss, this doesn't happen. So we do it ourselves.
3732 */
3733static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3734{
3735 vmx->rmode.irq.pending = 0;
5fdbf976 3736 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3737 return;
5fdbf976 3738 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3739 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3740 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3741 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3742 return;
3743 }
3744 vmx->idt_vectoring_info =
3745 VECTORING_INFO_VALID_MASK
3746 | INTR_TYPE_EXT_INTR
3747 | vmx->rmode.irq.vector;
3748}
3749
c801949d
AK		 3750#ifdef CONFIG_X86_64
3751#define R "r"
3752#define Q "q"
3753#else
3754#define R "e"
3755#define Q "l"
3756#endif
3757
851ba692 3758static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3759{
a2fa3e9f 3760 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3761
3b86cd99
JK		 3762 /* Record the guest's net vcpu time for enforced NMI injections. */
3763 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3764 vmx->entry_time = ktime_get();
3765
80ced186
MG		 3766 /* Don't enter VMX if guest state is invalid, let the exit handler
3767 start emulation until we arrive back to a valid state */
3768 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3769 return;
a89a8fb9 3770
5fdbf976
MT		 3771 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3772 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3773 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3774 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3775
787ff736
GN		 3776 /* When single-stepping over STI and MOV SS, we must clear the
3777 * corresponding interruptibility bits in the guest state. Otherwise
3778 * vmentry fails as it then expects bit 14 (BS) in pending debug
3779 * exceptions being set, but that's not correct for the guest debugging
3780 * case. */
3781 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3782 vmx_set_interrupt_shadow(vcpu, 0);
3783
e6adf283
AK		 3784 /*
3785 * Loading guest fpu may have cleared host cr0.ts
3786 */
3787 vmcs_writel(HOST_CR0, read_cr0());
3788
d77c26fc 3789 asm(
6aa8b732 3790 /* Store host registers */
c801949d
AK		 3791 "push %%"R"dx; push %%"R"bp;"
3792 "push %%"R"cx \n\t"
313dbd49
AK		 3793 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3794 "je 1f \n\t"
3795 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3796 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3797 "1: \n\t"
d3edefc0
AK		 3798 /* Reload cr2 if changed */
3799 "mov %c[cr2](%0), %%"R"ax \n\t"
3800 "mov %%cr2, %%"R"dx \n\t"
3801 "cmp %%"R"ax, %%"R"dx \n\t"
3802 "je 2f \n\t"
3803 "mov %%"R"ax, %%cr2 \n\t"
3804 "2: \n\t"
6aa8b732 3805 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3806 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3807 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3808 "mov %c[rax](%0), %%"R"ax \n\t"
3809 "mov %c[rbx](%0), %%"R"bx \n\t"
3810 "mov %c[rdx](%0), %%"R"dx \n\t"
3811 "mov %c[rsi](%0), %%"R"si \n\t"
3812 "mov %c[rdi](%0), %%"R"di \n\t"
3813 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3814#ifdef CONFIG_X86_64
e08aa78a
AK		 3815 "mov %c[r8](%0), %%r8 \n\t"
3816 "mov %c[r9](%0), %%r9 \n\t"
3817 "mov %c[r10](%0), %%r10 \n\t"
3818 "mov %c[r11](%0), %%r11 \n\t"
3819 "mov %c[r12](%0), %%r12 \n\t"
3820 "mov %c[r13](%0), %%r13 \n\t"
3821 "mov %c[r14](%0), %%r14 \n\t"
3822 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3823#endif
c801949d
AK		 3824 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3825
6aa8b732 3826 /* Enter guest mode */
cd2276a7 3827 "jne .Llaunched \n\t"
4ecac3fd 3828 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3829 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3830 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3831 ".Lkvm_vmx_return: "
6aa8b732 3832 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3833 "xchg %0, (%%"R"sp) \n\t"
3834 "mov %%"R"ax, %c[rax](%0) \n\t"
3835 "mov %%"R"bx, %c[rbx](%0) \n\t"
3836 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3837 "mov %%"R"dx, %c[rdx](%0) \n\t"
3838 "mov %%"R"si, %c[rsi](%0) \n\t"
3839 "mov %%"R"di, %c[rdi](%0) \n\t"
3840 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3841#ifdef CONFIG_X86_64
e08aa78a
AK		 3842 "mov %%r8, %c[r8](%0) \n\t"
3843 "mov %%r9, %c[r9](%0) \n\t"
3844 "mov %%r10, %c[r10](%0) \n\t"
3845 "mov %%r11, %c[r11](%0) \n\t"
3846 "mov %%r12, %c[r12](%0) \n\t"
3847 "mov %%r13, %c[r13](%0) \n\t"
3848 "mov %%r14, %c[r14](%0) \n\t"
3849 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3850#endif
c801949d
AK		 3851 "mov %%cr2, %%"R"ax \n\t"
3852 "mov %%"R"ax, %c[cr2](%0) \n\t"
3853
3854 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3855 "setbe %c[fail](%0) \n\t"
3856 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3857 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3858 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3859 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3860 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3861 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3862 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3863 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3864 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3865 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3866 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3867#ifdef CONFIG_X86_64
ad312c7c
ZX		 3868 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3869 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3870 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3871 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3872 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3873 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3874 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3875 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3876#endif
ad312c7c 3877 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3878 : "cc", "memory"
c801949d 3879 , R"bx", R"di", R"si"
c2036300 3880#ifdef CONFIG_X86_64
c2036300
LV		 3881 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3882#endif
3883 );
6aa8b732 3884
6de4f3ad
AK		 3885 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3886 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3887 vcpu->arch.regs_dirty = 0;
3888
1155f76a 3889 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3890 if (vmx->rmode.irq.pending)
3891 fixup_rmode_irq(vmx);
1155f76a 3892
d77c26fc 3893 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3894 vmx->launched = 1;
1b6269db 3895
cf393f75 3896 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3897}
3898
c801949d
AK		 3899#undef R
3900#undef Q
3901
6aa8b732
AK		 3902static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3903{
a2fa3e9f
GH		 3904 struct vcpu_vmx *vmx = to_vmx(vcpu);
3905
3906 if (vmx->vmcs) {
543e4243 3907 vcpu_clear(vmx);
a2fa3e9f
GH		 3908 free_vmcs(vmx->vmcs);
3909 vmx->vmcs = NULL;
6aa8b732
AK		 3910 }
3911}
3912
3913static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3914{
fb3f0f51
RR		 3915 struct vcpu_vmx *vmx = to_vmx(vcpu);
3916
2384d2b3
SY		 3917 spin_lock(&vmx_vpid_lock);
3918 if (vmx->vpid != 0)
3919 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3920 spin_unlock(&vmx_vpid_lock);
6aa8b732 3921 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3922 kfree(vmx->guest_msrs);
3923 kvm_vcpu_uninit(vcpu);
a4770347 3924 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3925}
3926
fb3f0f51 3927static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3928{
fb3f0f51 3929 int err;
c16f862d 3930 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3931 int cpu;
6aa8b732 3932
a2fa3e9f 3933 if (!vmx)
fb3f0f51
RR		 3934 return ERR_PTR(-ENOMEM);
3935
2384d2b3
SY		 3936 allocate_vpid(vmx);
3937
fb3f0f51
RR		 3938 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3939 if (err)
3940 goto free_vcpu;
965b58a5 3941
a2fa3e9f 3942 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3943 if (!vmx->guest_msrs) {
3944 err = -ENOMEM;
3945 goto uninit_vcpu;
3946 }
965b58a5 3947
a2fa3e9f
GH		 3948 vmx->vmcs = alloc_vmcs();
3949 if (!vmx->vmcs)
fb3f0f51 3950 goto free_msrs;
a2fa3e9f
GH		 3951
3952 vmcs_clear(vmx->vmcs);
3953
15ad7146
AK		 3954 cpu = get_cpu();
3955 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3956 err = vmx_vcpu_setup(vmx);
fb3f0f51 3957 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3958 put_cpu();
fb3f0f51
RR		 3959 if (err)
3960 goto free_vmcs;
5e4a0b3c
MT		 3961 if (vm_need_virtualize_apic_accesses(kvm))
3962 if (alloc_apic_access_page(kvm) != 0)
3963 goto free_vmcs;
fb3f0f51 3964
b927a3ce
SY		 3965 if (enable_ept) {
3966 if (!kvm->arch.ept_identity_map_addr)
3967 kvm->arch.ept_identity_map_addr =
3968 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3969 if (alloc_identity_pagetable(kvm) != 0)
3970 goto free_vmcs;
b927a3ce 3971 }
b7ebfb05 3972
fb3f0f51
RR		 3973 return &vmx->vcpu;
3974
3975free_vmcs:
3976 free_vmcs(vmx->vmcs);
3977free_msrs:
fb3f0f51
RR		 3978 kfree(vmx->guest_msrs);
3979uninit_vcpu:
3980 kvm_vcpu_uninit(&vmx->vcpu);
3981free_vcpu:
a4770347 3982 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3983 return ERR_PTR(err);
6aa8b732
AK		 3984}
3985
002c7f7c
YS		 3986static void __init vmx_check_processor_compat(void *rtn)
3987{
3988 struct vmcs_config vmcs_conf;
3989
3990 *(int *)rtn = 0;
3991 if (setup_vmcs_config(&vmcs_conf) < 0)
3992 *(int *)rtn = -EIO;
3993 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3994 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3995 smp_processor_id());
3996 *(int *)rtn = -EIO;
3997 }
3998}
3999
67253af5
SY		 4000static int get_ept_level(void)
4001{
4002 return VMX_EPT_DEFAULT_GAW + 1;
4003}
4004
4b12f0de 4005static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4006{
4b12f0de
SY		 4007 u64 ret;
4008
522c68c4
SY		 4009 /* For VT-d and EPT combination
4010 * 1. MMIO: always map as UC
4011 * 2. EPT with VT-d:
4012 * a. VT-d without snooping control feature: can't guarantee the
4013 * result, try to trust guest.
4014 * b. VT-d with snooping control feature: snooping control feature of
4015 * VT-d engine can guarantee the cache correctness. Just set it
4016 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4017 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4018 * consistent with host MTRR
4019 */
4b12f0de
SY		 4020 if (is_mmio)
4021 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4022 else if (vcpu->kvm->arch.iommu_domain &&
4023 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4024 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4025 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4026 else
522c68c4 4027 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4028 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4029
4030 return ret;
64d4d521
SY		 4031}
4032
f4c9e87c
AK		 4033#define _ER(x) { EXIT_REASON_##x, #x }
4034
229456fc 4035static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4036 _ER(EXCEPTION_NMI),
4037 _ER(EXTERNAL_INTERRUPT),
4038 _ER(TRIPLE_FAULT),
4039 _ER(PENDING_INTERRUPT),
4040 _ER(NMI_WINDOW),
4041 _ER(TASK_SWITCH),
4042 _ER(CPUID),
4043 _ER(HLT),
4044 _ER(INVLPG),
4045 _ER(RDPMC),
4046 _ER(RDTSC),
4047 _ER(VMCALL),
4048 _ER(VMCLEAR),
4049 _ER(VMLAUNCH),
4050 _ER(VMPTRLD),
4051 _ER(VMPTRST),
4052 _ER(VMREAD),
4053 _ER(VMRESUME),
4054 _ER(VMWRITE),
4055 _ER(VMOFF),
4056 _ER(VMON),
4057 _ER(CR_ACCESS),
4058 _ER(DR_ACCESS),
4059 _ER(IO_INSTRUCTION),
4060 _ER(MSR_READ),
4061 _ER(MSR_WRITE),
4062 _ER(MWAIT_INSTRUCTION),
4063 _ER(MONITOR_INSTRUCTION),
4064 _ER(PAUSE_INSTRUCTION),
4065 _ER(MCE_DURING_VMENTRY),
4066 _ER(TPR_BELOW_THRESHOLD),
4067 _ER(APIC_ACCESS),
4068 _ER(EPT_VIOLATION),
4069 _ER(EPT_MISCONFIG),
4070 _ER(WBINVD),
229456fc
MT		 4071 { -1, NULL }
4072};
4073
f4c9e87c
AK		 4074#undef _ER
4075
17cc3935 4076static int vmx_get_lpage_level(void)
344f414f 4077{
878403b7
SY		 4078 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4079 return PT_DIRECTORY_LEVEL;
4080 else
4081 /* For shadow and EPT supported 1GB page */
4082 return PT_PDPE_LEVEL;
344f414f
JR		 4083}
4084
4e47c7a6
SY		 4085static inline u32 bit(int bitno)
4086{
4087 return 1 << (bitno & 31);
4088}
4089
0e851880
SY		 4090static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4091{
4e47c7a6
SY		 4092 struct kvm_cpuid_entry2 *best;
4093 struct vcpu_vmx *vmx = to_vmx(vcpu);
4094 u32 exec_control;
4095
4096 vmx->rdtscp_enabled = false;
4097 if (vmx_rdtscp_supported()) {
4098 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4099 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4100 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4101 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4102 vmx->rdtscp_enabled = true;
4103 else {
4104 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4105 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4106 exec_control);
4107 }
4108 }
4109 }
0e851880
SY		 4110}
4111
cbdd1bea 4112static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4113 .cpu_has_kvm_support = cpu_has_kvm_support,
4114 .disabled_by_bios = vmx_disabled_by_bios,
4115 .hardware_setup = hardware_setup,
4116 .hardware_unsetup = hardware_unsetup,
002c7f7c 4117 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4118 .hardware_enable = hardware_enable,
4119 .hardware_disable = hardware_disable,
04547156 4120 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4121
4122 .vcpu_create = vmx_create_vcpu,
4123 .vcpu_free = vmx_free_vcpu,
04d2cc77 4124 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4125
04d2cc77 4126 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4127 .vcpu_load = vmx_vcpu_load,
4128 .vcpu_put = vmx_vcpu_put,
4129
4130 .set_guest_debug = set_guest_debug,
4131 .get_msr = vmx_get_msr,
4132 .set_msr = vmx_set_msr,
4133 .get_segment_base = vmx_get_segment_base,
4134 .get_segment = vmx_get_segment,
4135 .set_segment = vmx_set_segment,
2e4d2653 4136 .get_cpl = vmx_get_cpl,
6aa8b732 4137 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4138 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4139 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4140 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4141 .set_cr3 = vmx_set_cr3,
4142 .set_cr4 = vmx_set_cr4,
6aa8b732 4143 .set_efer = vmx_set_efer,
6aa8b732
AK		 4144 .get_idt = vmx_get_idt,
4145 .set_idt = vmx_set_idt,
4146 .get_gdt = vmx_get_gdt,
4147 .set_gdt = vmx_set_gdt,
5fdbf976 4148 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4149 .get_rflags = vmx_get_rflags,
4150 .set_rflags = vmx_set_rflags,
ebcbab4c 4151 .fpu_activate = vmx_fpu_activate,
02daab21 4152 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4153
4154 .tlb_flush = vmx_flush_tlb,
6aa8b732 4155
6aa8b732 4156 .run = vmx_vcpu_run,
6062d012 4157 .handle_exit = vmx_handle_exit,
6aa8b732 4158 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4159 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4160 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4161 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4162 .set_irq = vmx_inject_irq,
95ba8273 4163 .set_nmi = vmx_inject_nmi,
298101da 4164 .queue_exception = vmx_queue_exception,
78646121 4165 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4166 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4167 .get_nmi_mask = vmx_get_nmi_mask,
4168 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4169 .enable_nmi_window = enable_nmi_window,
4170 .enable_irq_window = enable_irq_window,
4171 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4172
cbc94022 4173 .set_tss_addr = vmx_set_tss_addr,
67253af5 4174 .get_tdp_level = get_ept_level,
4b12f0de 4175 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4176
4177 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4178 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4179
4180 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4181
4182 .rdtscp_supported = vmx_rdtscp_supported,
6aa8b732
AK		 4183};
4184
4185static int __init vmx_init(void)
4186{
26bb0981
AK		 4187 int r, i;
4188
4189 rdmsrl_safe(MSR_EFER, &host_efer);
4190
4191 for (i = 0; i < NR_VMX_MSR; ++i)
4192 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4193
3e7c73e9 4194 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4195 if (!vmx_io_bitmap_a)
4196 return -ENOMEM;
4197
3e7c73e9 4198 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4199 if (!vmx_io_bitmap_b) {
4200 r = -ENOMEM;
4201 goto out;
4202 }
4203
5897297b
AK		 4204 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4205 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4206 r = -ENOMEM;
4207 goto out1;
4208 }
4209
5897297b
AK		 4210 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4211 if (!vmx_msr_bitmap_longmode) {
4212 r = -ENOMEM;
4213 goto out2;
4214 }
4215
fdef3ad1
HQ		 4216 /*
4217 * Allow direct access to the PC debug port (it is often used for I/O
4218 * delays, but the vmexits simply slow things down).
4219 */
3e7c73e9
AK		 4220 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4221 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4222
3e7c73e9 4223 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4224
5897297b
AK		 4225 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4226 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4227
2384d2b3
SY		 4228 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4229
cb498ea2 4230 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4231 if (r)
5897297b 4232 goto out3;
25c5f225 4233
5897297b
AK		 4234 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4235 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4236 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4237 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4238 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4239 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4240
089d034e 4241 if (enable_ept) {
1439442c 4242 bypass_guest_pf = 0;
5fdbcb9d 4243 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4244 VMX_EPT_WRITABLE_MASK);
534e38b4 4245 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4246 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4247 kvm_enable_tdp();
4248 } else
4249 kvm_disable_tdp();
1439442c 4250
c7addb90
AK		 4251 if (bypass_guest_pf)
4252 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4253
fdef3ad1
HQ		 4254 return 0;
4255
5897297b
AK		 4256out3:
4257 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4258out2:
5897297b 4259 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4260out1:
3e7c73e9 4261 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4262out:
3e7c73e9 4263 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4264 return r;
6aa8b732
AK		 4265}
4266
4267static void __exit vmx_exit(void)
4268{
5897297b
AK		 4269 free_page((unsigned long)vmx_msr_bitmap_legacy);
4270 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4271 free_page((unsigned long)vmx_io_bitmap_b);
4272 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4273
cb498ea2 4274 kvm_exit();
6aa8b732
AK		 4275}
4276
4277module_init(vmx_init)
4278module_exit(vmx_exit)
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