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KVM: Correct ordering of ldt reload wrt fs/gs reload
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
51aa01d1 128 u32 exit_intr_info;
1155f76a 129 u32 idt_vectoring_info;
26bb0981 130 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 131 int nmsrs;
132 int save_nmsrs;
a2fa3e9f 133#ifdef CONFIG_X86_64
44ea2b17
AK		 134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 136#endif
137 struct vmcs *vmcs;
61d2ef2c
AK		 138 struct msr_autoload {
139 unsigned nr;
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 } msr_autoload;
a2fa3e9f
GH		 143 struct {
144 int loaded;
145 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
d77c26fc 148 } host_state;
9c8cba37 149 struct {
7ffd92c5 150 int vm86_active;
78ac8b47 151 ulong save_rflags;
7ffd92c5
AK		 152 struct kvm_save_segment {
153 u16 selector;
154 unsigned long base;
155 u32 limit;
156 u32 ar;
157 } tr, es, ds, fs, gs;
9c8cba37 158 } rmode;
2384d2b3 159 int vpid;
04fa4d32 160 bool emulation_required;
3b86cd99
JK		 161
162 /* Support for vnmi-less CPUs */
163 int soft_vnmi_blocked;
164 ktime_t entry_time;
165 s64 vnmi_blocked_time;
a0861c02 166 u32 exit_reason;
4e47c7a6
SY		 167
168 bool rdtscp_enabled;
a2fa3e9f
GH		 169};
170
171static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
172{
fb3f0f51 173 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 174}
175
b7ebfb05 176static int init_rmode(struct kvm *kvm);
4e1096d2 177static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 178static void kvm_cpu_vmxon(u64 addr);
179static void kvm_cpu_vmxoff(void);
75880a01 180
6aa8b732
AK		 181static DEFINE_PER_CPU(struct vmcs *, vmxarea);
182static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 183static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 184static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 185
3e7c73e9
AK		 186static unsigned long *vmx_io_bitmap_a;
187static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 188static unsigned long *vmx_msr_bitmap_legacy;
189static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 190
2384d2b3
SY		 191static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
192static DEFINE_SPINLOCK(vmx_vpid_lock);
193
1c3d14fe 194static struct vmcs_config {
6aa8b732
AK		 195 int size;
196 int order;
197 u32 revision_id;
1c3d14fe
YS		 198 u32 pin_based_exec_ctrl;
199 u32 cpu_based_exec_ctrl;
f78e0e2e 200 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 201 u32 vmexit_ctrl;
202 u32 vmentry_ctrl;
203} vmcs_config;
6aa8b732 204
efff9e53 205static struct vmx_capability {
d56f546d
SY		 206 u32 ept;
207 u32 vpid;
208} vmx_capability;
209
6aa8b732
AK		 210#define VMX_SEGMENT_FIELD(seg) \
211 [VCPU_SREG_##seg] = { \
212 .selector = GUEST_##seg##_SELECTOR, \
213 .base = GUEST_##seg##_BASE, \
214 .limit = GUEST_##seg##_LIMIT, \
215 .ar_bytes = GUEST_##seg##_AR_BYTES, \
216 }
217
218static struct kvm_vmx_segment_field {
219 unsigned selector;
220 unsigned base;
221 unsigned limit;
222 unsigned ar_bytes;
223} kvm_vmx_segment_fields[] = {
224 VMX_SEGMENT_FIELD(CS),
225 VMX_SEGMENT_FIELD(DS),
226 VMX_SEGMENT_FIELD(ES),
227 VMX_SEGMENT_FIELD(FS),
228 VMX_SEGMENT_FIELD(GS),
229 VMX_SEGMENT_FIELD(SS),
230 VMX_SEGMENT_FIELD(TR),
231 VMX_SEGMENT_FIELD(LDTR),
232};
233
26bb0981
AK		 234static u64 host_efer;
235
6de4f3ad
AK		 236static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
237
4d56c8a7 238/*
8c06585d 239 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 240 * away by decrementing the array size.
241 */
6aa8b732 242static const u32 vmx_msr_index[] = {
05b3e0c2 243#ifdef CONFIG_X86_64
44ea2b17 244 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 245#endif
8c06585d 246 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 247};
9d8f549d 248#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 249
31299944 250static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 251{
252 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
253 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 254 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 255}
256
31299944 257static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 258{
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 261 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 262}
263
31299944 264static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 265{
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 268 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 269}
270
31299944 271static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 272{
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
274 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
275}
276
31299944 277static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 278{
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
280 INTR_INFO_VALID_MASK)) ==
281 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
282}
283
31299944 284static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 285{
04547156 286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 287}
288
31299944 289static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 290{
04547156 291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 292}
293
31299944 294static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 295{
04547156 296 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 297}
298
31299944 299static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 300{
04547156
SY		 301 return vmcs_config.cpu_based_exec_ctrl &
302 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 303}
304
774ead3a 305static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 306{
04547156
SY		 307 return vmcs_config.cpu_based_2nd_exec_ctrl &
308 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
309}
310
311static inline bool cpu_has_vmx_flexpriority(void)
312{
313 return cpu_has_vmx_tpr_shadow() &&
314 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 315}
316
e799794e
MT		 317static inline bool cpu_has_vmx_ept_execute_only(void)
318{
31299944 319 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 320}
321
322static inline bool cpu_has_vmx_eptp_uncacheable(void)
323{
31299944 324 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 325}
326
327static inline bool cpu_has_vmx_eptp_writeback(void)
328{
31299944 329 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 330}
331
332static inline bool cpu_has_vmx_ept_2m_page(void)
333{
31299944 334 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 335}
336
878403b7
SY		 337static inline bool cpu_has_vmx_ept_1g_page(void)
338{
31299944 339 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 340}
341
4bc9b982
SY		 342static inline bool cpu_has_vmx_ept_4levels(void)
343{
344 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
345}
346
31299944 347static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 348{
31299944 349 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 350}
351
31299944 352static inline bool cpu_has_vmx_invept_context(void)
d56f546d 353{
31299944 354 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 355}
356
31299944 357static inline bool cpu_has_vmx_invept_global(void)
d56f546d 358{
31299944 359 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 360}
361
518c8aee
GJ		 362static inline bool cpu_has_vmx_invvpid_single(void)
363{
364 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
365}
366
b9d762fa
GJ		 367static inline bool cpu_has_vmx_invvpid_global(void)
368{
369 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
370}
371
31299944 372static inline bool cpu_has_vmx_ept(void)
d56f546d 373{
04547156
SY		 374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 376}
377
31299944 378static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 379{
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_UNRESTRICTED_GUEST;
382}
383
31299944 384static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 385{
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
388}
389
31299944 390static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 391{
6d3e435e 392 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 393}
394
31299944 395static inline bool cpu_has_vmx_vpid(void)
2384d2b3 396{
04547156
SY		 397 return vmcs_config.cpu_based_2nd_exec_ctrl &
398 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 399}
400
31299944 401static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 402{
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_RDTSCP;
405}
406
31299944 407static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 408{
409 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
410}
411
f5f48ee1
SY		 412static inline bool cpu_has_vmx_wbinvd_exit(void)
413{
414 return vmcs_config.cpu_based_2nd_exec_ctrl &
415 SECONDARY_EXEC_WBINVD_EXITING;
416}
417
04547156
SY		 418static inline bool report_flexpriority(void)
419{
420 return flexpriority_enabled;
421}
422
8b9cf98c 423static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 424{
425 int i;
426
a2fa3e9f 427 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 428 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 429 return i;
430 return -1;
431}
432
2384d2b3
SY		 433static inline void __invvpid(int ext, u16 vpid, gva_t gva)
434{
435 struct {
436 u64 vpid : 16;
437 u64 rsvd : 48;
438 u64 gva;
439 } operand = { vpid, 0, gva };
440
4ecac3fd 441 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 442 /* CF==1 or ZF==1 --> rc = -1 */
443 "; ja 1f ; ud2 ; 1:"
444 : : "a"(&operand), "c"(ext) : "cc", "memory");
445}
446
1439442c
SY		 447static inline void __invept(int ext, u64 eptp, gpa_t gpa)
448{
449 struct {
450 u64 eptp, gpa;
451 } operand = {eptp, gpa};
452
4ecac3fd 453 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 454 /* CF==1 or ZF==1 --> rc = -1 */
455 "; ja 1f ; ud2 ; 1:\n"
456 : : "a" (&operand), "c" (ext) : "cc", "memory");
457}
458
26bb0981 459static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 460{
461 int i;
462
8b9cf98c 463 i = __find_msr_index(vmx, msr);
a75beee6 464 if (i >= 0)
a2fa3e9f 465 return &vmx->guest_msrs[i];
8b6d44c7 466 return NULL;
7725f0ba
AK		 467}
468
6aa8b732
AK		 469static void vmcs_clear(struct vmcs *vmcs)
470{
471 u64 phys_addr = __pa(vmcs);
472 u8 error;
473
4ecac3fd 474 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 475 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
476 : "cc", "memory");
477 if (error)
478 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
479 vmcs, phys_addr);
480}
481
7725b894
DX		 482static void vmcs_load(struct vmcs *vmcs)
483{
484 u64 phys_addr = __pa(vmcs);
485 u8 error;
486
487 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
488 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
489 : "cc", "memory");
490 if (error)
491 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
492 vmcs, phys_addr);
493}
494
6aa8b732
AK		 495static void __vcpu_clear(void *arg)
496{
8b9cf98c 497 struct vcpu_vmx *vmx = arg;
d3b2c338 498 int cpu = raw_smp_processor_id();
6aa8b732 499
8b9cf98c 500 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 501 vmcs_clear(vmx->vmcs);
502 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 503 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 504 list_del(&vmx->local_vcpus_link);
505 vmx->vcpu.cpu = -1;
506 vmx->launched = 0;
6aa8b732
AK		 507}
508
8b9cf98c 509static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 510{
eae5ecb5
AK		 511 if (vmx->vcpu.cpu == -1)
512 return;
8691e5a8 513 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 514}
515
1760dd49 516static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 517{
518 if (vmx->vpid == 0)
519 return;
520
518c8aee
GJ		 521 if (cpu_has_vmx_invvpid_single())
522 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 523}
524
b9d762fa
GJ		 525static inline void vpid_sync_vcpu_global(void)
526{
527 if (cpu_has_vmx_invvpid_global())
528 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
529}
530
531static inline void vpid_sync_context(struct vcpu_vmx *vmx)
532{
533 if (cpu_has_vmx_invvpid_single())
1760dd49 534 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 535 else
536 vpid_sync_vcpu_global();
537}
538
1439442c
SY		 539static inline void ept_sync_global(void)
540{
541 if (cpu_has_vmx_invept_global())
542 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
543}
544
545static inline void ept_sync_context(u64 eptp)
546{
089d034e 547 if (enable_ept) {
1439442c
SY		 548 if (cpu_has_vmx_invept_context())
549 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
550 else
551 ept_sync_global();
552 }
553}
554
555static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
556{
089d034e 557 if (enable_ept) {
1439442c
SY		 558 if (cpu_has_vmx_invept_individual_addr())
559 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
560 eptp, gpa);
561 else
562 ept_sync_context(eptp);
563 }
564}
565
6aa8b732
AK		 566static unsigned long vmcs_readl(unsigned long field)
567{
568 unsigned long value;
569
4ecac3fd 570 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 571 : "=a"(value) : "d"(field) : "cc");
572 return value;
573}
574
575static u16 vmcs_read16(unsigned long field)
576{
577 return vmcs_readl(field);
578}
579
580static u32 vmcs_read32(unsigned long field)
581{
582 return vmcs_readl(field);
583}
584
585static u64 vmcs_read64(unsigned long field)
586{
05b3e0c2 587#ifdef CONFIG_X86_64
6aa8b732
AK		 588 return vmcs_readl(field);
589#else
590 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
591#endif
592}
593
e52de1b8
AK		 594static noinline void vmwrite_error(unsigned long field, unsigned long value)
595{
596 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
597 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
598 dump_stack();
599}
600
6aa8b732
AK		 601static void vmcs_writel(unsigned long field, unsigned long value)
602{
603 u8 error;
604
4ecac3fd 605 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 606 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 607 if (unlikely(error))
608 vmwrite_error(field, value);
6aa8b732
AK		 609}
610
611static void vmcs_write16(unsigned long field, u16 value)
612{
613 vmcs_writel(field, value);
614}
615
616static void vmcs_write32(unsigned long field, u32 value)
617{
618 vmcs_writel(field, value);
619}
620
621static void vmcs_write64(unsigned long field, u64 value)
622{
6aa8b732 623 vmcs_writel(field, value);
7682f2d0 624#ifndef CONFIG_X86_64
6aa8b732
AK		 625 asm volatile ("");
626 vmcs_writel(field+1, value >> 32);
627#endif
628}
629
2ab455cc
AL		 630static void vmcs_clear_bits(unsigned long field, u32 mask)
631{
632 vmcs_writel(field, vmcs_readl(field) & ~mask);
633}
634
635static void vmcs_set_bits(unsigned long field, u32 mask)
636{
637 vmcs_writel(field, vmcs_readl(field) | mask);
638}
639
abd3f2d6
AK		 640static void update_exception_bitmap(struct kvm_vcpu *vcpu)
641{
642 u32 eb;
643
fd7373cc
JK		 644 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
645 (1u << NM_VECTOR) | (1u << DB_VECTOR);
646 if ((vcpu->guest_debug &
647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
648 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
649 eb |= 1u << BP_VECTOR;
7ffd92c5 650 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 651 eb = ~0;
089d034e 652 if (enable_ept)
1439442c 653 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 654 if (vcpu->fpu_active)
655 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 656 vmcs_write32(EXCEPTION_BITMAP, eb);
657}
658
61d2ef2c
AK		 659static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
660{
661 unsigned i;
662 struct msr_autoload *m = &vmx->msr_autoload;
663
664 for (i = 0; i < m->nr; ++i)
665 if (m->guest[i].index == msr)
666 break;
667
668 if (i == m->nr)
669 return;
670 --m->nr;
671 m->guest[i] = m->guest[m->nr];
672 m->host[i] = m->host[m->nr];
673 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
674 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
675}
676
677static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
678 u64 guest_val, u64 host_val)
679{
680 unsigned i;
681 struct msr_autoload *m = &vmx->msr_autoload;
682
683 for (i = 0; i < m->nr; ++i)
684 if (m->guest[i].index == msr)
685 break;
686
687 if (i == m->nr) {
688 ++m->nr;
689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
691 }
692
693 m->guest[i].index = msr;
694 m->guest[i].value = guest_val;
695 m->host[i].index = msr;
696 m->host[i].value = host_val;
697}
698
33ed6329
AK		 699static void reload_tss(void)
700{
33ed6329
AK		 701 /*
702 * VT restores TR but not its size. Useless.
703 */
d359192f 704 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 705 struct desc_struct *descs;
33ed6329 706
d359192f 707 descs = (void *)gdt->address;
33ed6329
AK		 708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
709 load_TR_desc();
33ed6329
AK		 710}
711
92c0d900 712static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 713{
3a34a881 714 u64 guest_efer;
51c6cf66
AK		 715 u64 ignore_bits;
716
f6801dff 717 guest_efer = vmx->vcpu.arch.efer;
3a34a881 718
51c6cf66
AK		 719 /*
720 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
721 * outside long mode
722 */
723 ignore_bits = EFER_NX | EFER_SCE;
724#ifdef CONFIG_X86_64
725 ignore_bits |= EFER_LMA | EFER_LME;
726 /* SCE is meaningful only in long mode on Intel */
727 if (guest_efer & EFER_LMA)
728 ignore_bits &= ~(u64)EFER_SCE;
729#endif
51c6cf66
AK		 730 guest_efer &= ~ignore_bits;
731 guest_efer |= host_efer & ignore_bits;
26bb0981 732 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 734
735 clear_atomic_switch_msr(vmx, MSR_EFER);
736 /* On ept, can't emulate nx, and must switch nx atomically */
737 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
738 guest_efer = vmx->vcpu.arch.efer;
739 if (!(guest_efer & EFER_LMA))
740 guest_efer &= ~EFER_LME;
741 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
742 return false;
743 }
744
26bb0981 745 return true;
51c6cf66
AK		 746}
747
2d49ec72
GN		 748static unsigned long segment_base(u16 selector)
749{
d359192f 750 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 751 struct desc_struct *d;
752 unsigned long table_base;
753 unsigned long v;
754
755 if (!(selector & ~3))
756 return 0;
757
d359192f 758 table_base = gdt->address;
2d49ec72
GN		 759
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
762
763 if (!(ldt_selector & ~3))
764 return 0;
765
766 table_base = segment_base(ldt_selector);
767 }
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
770#ifdef CONFIG_X86_64
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
773#endif
774 return v;
775}
776
777static inline unsigned long kvm_read_tr_base(void)
778{
779 u16 tr;
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
782}
783
04d2cc77 784static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 785{
04d2cc77 786 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 787 int i;
04d2cc77 788
a2fa3e9f 789 if (vmx->host_state.loaded)
33ed6329
AK		 790 return;
791
a2fa3e9f 792 vmx->host_state.loaded = 1;
33ed6329
AK		 793 /*
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
796 */
d6e88aec 797 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 799 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 800 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 802 vmx->host_state.fs_reload_needed = 0;
803 } else {
33ed6329 804 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 805 vmx->host_state.fs_reload_needed = 1;
33ed6329 806 }
9581d442 807 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 810 else {
811 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 812 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 813 }
814
815#ifdef CONFIG_X86_64
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
818#else
a2fa3e9f
GH		 819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 821#endif
707c0874
AK		 822
823#ifdef CONFIG_X86_64
44ea2b17
AK		 824 if (is_long_mode(&vmx->vcpu)) {
825 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
827 }
707c0874 828#endif
26bb0981
AK		 829 for (i = 0; i < vmx->save_nmsrs; ++i)
830 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 831 vmx->guest_msrs[i].data,
832 vmx->guest_msrs[i].mask);
33ed6329
AK		 833}
834
a9b21b62 835static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 836{
a2fa3e9f 837 if (!vmx->host_state.loaded)
33ed6329
AK		 838 return;
839
e1beb1d3 840 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 841 vmx->host_state.loaded = 0;
152d3f2f 842 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 843 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 844#ifdef CONFIG_X86_64
9581d442
AK		 845 load_gs_index(vmx->host_state.gs_sel);
846 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
847#else
848 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 849#endif
33ed6329 850 }
0a77fe4c
AK		 851 if (vmx->host_state.fs_reload_needed)
852 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 853 reload_tss();
44ea2b17
AK		 854#ifdef CONFIG_X86_64
855 if (is_long_mode(&vmx->vcpu)) {
856 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
857 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
858 }
859#endif
1c11e713
AK		 860 if (current_thread_info()->status & TS_USEDFPU)
861 clts();
3444d7da 862 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 863}
864
a9b21b62
AK		 865static void vmx_load_host_state(struct vcpu_vmx *vmx)
866{
867 preempt_disable();
868 __vmx_load_host_state(vmx);
869 preempt_enable();
870}
871
6aa8b732
AK		 872/*
873 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
874 * vcpu mutex is already taken.
875 */
15ad7146 876static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 877{
a2fa3e9f 878 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 879 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 880
4610c9cc
DX		 881 if (!vmm_exclusive)
882 kvm_cpu_vmxon(phys_addr);
883 else if (vcpu->cpu != cpu)
8b9cf98c 884 vcpu_clear(vmx);
6aa8b732 885
a2fa3e9f 886 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 887 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 888 vmcs_load(vmx->vmcs);
6aa8b732
AK		 889 }
890
891 if (vcpu->cpu != cpu) {
d359192f 892 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 893 unsigned long sysenter_esp;
894
a8eeb04a 895 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 896 local_irq_disable();
897 list_add(&vmx->local_vcpus_link,
898 &per_cpu(vcpus_on_cpu, cpu));
899 local_irq_enable();
900
6aa8b732
AK		 901 /*
902 * Linux uses per-cpu TSS and GDT, so set these when switching
903 * processors.
904 */
d6e88aec 905 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 906 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 907
908 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
909 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
910 }
6aa8b732
AK		 911}
912
913static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
914{
a9b21b62 915 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 916 if (!vmm_exclusive) {
b923e62e 917 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 918 kvm_cpu_vmxoff();
919 }
6aa8b732
AK		 920}
921
5fd86fcf
AK		 922static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
923{
81231c69
AK		 924 ulong cr0;
925
5fd86fcf
AK		 926 if (vcpu->fpu_active)
927 return;
928 vcpu->fpu_active = 1;
81231c69
AK		 929 cr0 = vmcs_readl(GUEST_CR0);
930 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
931 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
932 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 933 update_exception_bitmap(vcpu);
edcafe3c
AK		 934 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
935 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 936}
937
edcafe3c
AK		 938static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
939
5fd86fcf
AK		 940static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
941{
edcafe3c 942 vmx_decache_cr0_guest_bits(vcpu);
81231c69 943 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 944 update_exception_bitmap(vcpu);
edcafe3c
AK		 945 vcpu->arch.cr0_guest_owned_bits = 0;
946 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
947 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 948}
949
6aa8b732
AK		 950static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
951{
78ac8b47 952 unsigned long rflags, save_rflags;
345dcaa8
AK		 953
954 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 955 if (to_vmx(vcpu)->rmode.vm86_active) {
956 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
957 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
958 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
959 }
345dcaa8 960 return rflags;
6aa8b732
AK		 961}
962
963static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
964{
78ac8b47
AK		 965 if (to_vmx(vcpu)->rmode.vm86_active) {
966 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 967 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 968 }
6aa8b732
AK		 969 vmcs_writel(GUEST_RFLAGS, rflags);
970}
971
2809f5d2
GC		 972static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
973{
974 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
975 int ret = 0;
976
977 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 978 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 979 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 980 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 981
982 return ret & mask;
983}
984
985static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
986{
987 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
988 u32 interruptibility = interruptibility_old;
989
990 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
991
48005f64 992 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 993 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 994 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 995 interruptibility |= GUEST_INTR_STATE_STI;
996
997 if ((interruptibility != interruptibility_old))
998 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
999}
1000
6aa8b732
AK		 1001static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1002{
1003 unsigned long rip;
6aa8b732 1004
5fdbf976 1005 rip = kvm_rip_read(vcpu);
6aa8b732 1006 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1007 kvm_rip_write(vcpu, rip);
6aa8b732 1008
2809f5d2
GC		 1009 /* skipping an emulated instruction also counts */
1010 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1011}
1012
298101da 1013static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1014 bool has_error_code, u32 error_code,
1015 bool reinject)
298101da 1016{
77ab6db0 1017 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1018 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1019
8ab2d2e2 1020 if (has_error_code) {
77ab6db0 1021 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1022 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1023 }
77ab6db0 1024
7ffd92c5 1025 if (vmx->rmode.vm86_active) {
a92601bb
MG		 1026 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1027 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1028 return;
1029 }
1030
66fd3f7f
GN		 1031 if (kvm_exception_is_soft(nr)) {
1032 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1033 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1034 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1035 } else
1036 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1037
1038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1039}
1040
4e47c7a6
SY		 1041static bool vmx_rdtscp_supported(void)
1042{
1043 return cpu_has_vmx_rdtscp();
1044}
1045
a75beee6
ED		 1046/*
1047 * Swap MSR entry in host/guest MSR entry array.
1048 */
8b9cf98c 1049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1050{
26bb0981 1051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1052
1053 tmp = vmx->guest_msrs[to];
1054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1056}
1057
e38aea3e
AK		 1058/*
1059 * Set up the vmcs to automatically save and restore system
1060 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1061 * mode, as fiddling with msrs is very expensive.
1062 */
8b9cf98c 1063static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1064{
26bb0981 1065 int save_nmsrs, index;
5897297b 1066 unsigned long *msr_bitmap;
e38aea3e 1067
33f9c505 1068 vmx_load_host_state(vmx);
a75beee6
ED		 1069 save_nmsrs = 0;
1070#ifdef CONFIG_X86_64
8b9cf98c 1071 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1072 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1073 if (index >= 0)
8b9cf98c
RR		 1074 move_msr_up(vmx, index, save_nmsrs++);
1075 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1076 if (index >= 0)
8b9cf98c
RR		 1077 move_msr_up(vmx, index, save_nmsrs++);
1078 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1079 if (index >= 0)
8b9cf98c 1080 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1081 index = __find_msr_index(vmx, MSR_TSC_AUX);
1082 if (index >= 0 && vmx->rdtscp_enabled)
1083 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1084 /*
8c06585d 1085 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1086 * if efer.sce is enabled.
1087 */
8c06585d 1088 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1089 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1090 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1091 }
1092#endif
92c0d900
AK		 1093 index = __find_msr_index(vmx, MSR_EFER);
1094 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1095 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1096
26bb0981 1097 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1098
1099 if (cpu_has_vmx_msr_bitmap()) {
1100 if (is_long_mode(&vmx->vcpu))
1101 msr_bitmap = vmx_msr_bitmap_longmode;
1102 else
1103 msr_bitmap = vmx_msr_bitmap_legacy;
1104
1105 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1106 }
e38aea3e
AK		 1107}
1108
6aa8b732
AK		 1109/*
1110 * reads and returns guest's timestamp counter "register"
1111 * guest_tsc = host_tsc + tsc_offset -- 21.3
1112 */
1113static u64 guest_read_tsc(void)
1114{
1115 u64 host_tsc, tsc_offset;
1116
1117 rdtscll(host_tsc);
1118 tsc_offset = vmcs_read64(TSC_OFFSET);
1119 return host_tsc + tsc_offset;
1120}
1121
1122/*
99e3e30a 1123 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1124 */
99e3e30a 1125static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1126{
f4e1b3c8 1127 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1128}
1129
e48672fa
ZA		 1130static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1131{
1132 u64 offset = vmcs_read64(TSC_OFFSET);
1133 vmcs_write64(TSC_OFFSET, offset + adjustment);
1134}
1135
6aa8b732
AK		 1136/*
1137 * Reads an msr value (of 'msr_index') into 'pdata'.
1138 * Returns 0 on success, non-0 otherwise.
1139 * Assumes vcpu_load() was already called.
1140 */
1141static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1142{
1143 u64 data;
26bb0981 1144 struct shared_msr_entry *msr;
6aa8b732
AK		 1145
1146 if (!pdata) {
1147 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1148 return -EINVAL;
1149 }
1150
1151 switch (msr_index) {
05b3e0c2 1152#ifdef CONFIG_X86_64
6aa8b732
AK		 1153 case MSR_FS_BASE:
1154 data = vmcs_readl(GUEST_FS_BASE);
1155 break;
1156 case MSR_GS_BASE:
1157 data = vmcs_readl(GUEST_GS_BASE);
1158 break;
44ea2b17
AK		 1159 case MSR_KERNEL_GS_BASE:
1160 vmx_load_host_state(to_vmx(vcpu));
1161 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1162 break;
26bb0981 1163#endif
6aa8b732 1164 case MSR_EFER:
3bab1f5d 1165 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1166 case MSR_IA32_TSC:
6aa8b732
AK		 1167 data = guest_read_tsc();
1168 break;
1169 case MSR_IA32_SYSENTER_CS:
1170 data = vmcs_read32(GUEST_SYSENTER_CS);
1171 break;
1172 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1173 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1174 break;
1175 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1176 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1177 break;
4e47c7a6
SY		 1178 case MSR_TSC_AUX:
1179 if (!to_vmx(vcpu)->rdtscp_enabled)
1180 return 1;
1181 /* Otherwise falls through */
6aa8b732 1182 default:
26bb0981 1183 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1184 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1185 if (msr) {
542423b0 1186 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1187 data = msr->data;
1188 break;
6aa8b732 1189 }
3bab1f5d 1190 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1191 }
1192
1193 *pdata = data;
1194 return 0;
1195}
1196
1197/*
1198 * Writes msr value into into the appropriate "register".
1199 * Returns 0 on success, non-0 otherwise.
1200 * Assumes vcpu_load() was already called.
1201 */
1202static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1203{
a2fa3e9f 1204 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1205 struct shared_msr_entry *msr;
2cc51560
ED		 1206 int ret = 0;
1207
6aa8b732 1208 switch (msr_index) {
3bab1f5d 1209 case MSR_EFER:
a9b21b62 1210 vmx_load_host_state(vmx);
2cc51560 1211 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1212 break;
16175a79 1213#ifdef CONFIG_X86_64
6aa8b732
AK		 1214 case MSR_FS_BASE:
1215 vmcs_writel(GUEST_FS_BASE, data);
1216 break;
1217 case MSR_GS_BASE:
1218 vmcs_writel(GUEST_GS_BASE, data);
1219 break;
44ea2b17
AK		 1220 case MSR_KERNEL_GS_BASE:
1221 vmx_load_host_state(vmx);
1222 vmx->msr_guest_kernel_gs_base = data;
1223 break;
6aa8b732
AK		 1224#endif
1225 case MSR_IA32_SYSENTER_CS:
1226 vmcs_write32(GUEST_SYSENTER_CS, data);
1227 break;
1228 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1229 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1230 break;
1231 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1232 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1233 break;
af24a4e4 1234 case MSR_IA32_TSC:
99e3e30a 1235 kvm_write_tsc(vcpu, data);
6aa8b732 1236 break;
468d472f
SY		 1237 case MSR_IA32_CR_PAT:
1238 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1239 vmcs_write64(GUEST_IA32_PAT, data);
1240 vcpu->arch.pat = data;
1241 break;
1242 }
4e47c7a6
SY		 1243 ret = kvm_set_msr_common(vcpu, msr_index, data);
1244 break;
1245 case MSR_TSC_AUX:
1246 if (!vmx->rdtscp_enabled)
1247 return 1;
1248 /* Check reserved bit, higher 32 bits should be zero */
1249 if ((data >> 32) != 0)
1250 return 1;
1251 /* Otherwise falls through */
6aa8b732 1252 default:
8b9cf98c 1253 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1254 if (msr) {
542423b0 1255 vmx_load_host_state(vmx);
3bab1f5d
AK		 1256 msr->data = data;
1257 break;
6aa8b732 1258 }
2cc51560 1259 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1260 }
1261
2cc51560 1262 return ret;
6aa8b732
AK		 1263}
1264
5fdbf976 1265static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1266{
5fdbf976
MT		 1267 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1268 switch (reg) {
1269 case VCPU_REGS_RSP:
1270 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1271 break;
1272 case VCPU_REGS_RIP:
1273 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1274 break;
6de4f3ad
AK		 1275 case VCPU_EXREG_PDPTR:
1276 if (enable_ept)
1277 ept_save_pdptrs(vcpu);
1278 break;
5fdbf976
MT		 1279 default:
1280 break;
1281 }
6aa8b732
AK		 1282}
1283
355be0b9 1284static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1285{
ae675ef0
JK		 1286 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1287 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1288 else
1289 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1290
abd3f2d6 1291 update_exception_bitmap(vcpu);
6aa8b732
AK		 1292}
1293
1294static __init int cpu_has_kvm_support(void)
1295{
6210e37b 1296 return cpu_has_vmx();
6aa8b732
AK		 1297}
1298
1299static __init int vmx_disabled_by_bios(void)
1300{
1301 u64 msr;
1302
1303 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1304 if (msr & FEATURE_CONTROL_LOCKED) {
1305 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1306 && tboot_enabled())
1307 return 1;
1308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1309 && !tboot_enabled())
1310 return 1;
1311 }
1312
1313 return 0;
62b3ffb8 1314 /* locked but not enabled */
6aa8b732
AK		 1315}
1316
7725b894
DX		 1317static void kvm_cpu_vmxon(u64 addr)
1318{
1319 asm volatile (ASM_VMX_VMXON_RAX
1320 : : "a"(&addr), "m"(addr)
1321 : "memory", "cc");
1322}
1323
10474ae8 1324static int hardware_enable(void *garbage)
6aa8b732
AK		 1325{
1326 int cpu = raw_smp_processor_id();
1327 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1328 u64 old, test_bits;
6aa8b732 1329
10474ae8
AG		 1330 if (read_cr4() & X86_CR4_VMXE)
1331 return -EBUSY;
1332
543e4243 1333 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1335
1336 test_bits = FEATURE_CONTROL_LOCKED;
1337 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1338 if (tboot_enabled())
1339 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1340
1341 if ((old & test_bits) != test_bits) {
6aa8b732 1342 /* enable and lock */
cafd6659
SW		 1343 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1344 }
66aee91a 1345 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1346
4610c9cc
DX		 1347 if (vmm_exclusive) {
1348 kvm_cpu_vmxon(phys_addr);
1349 ept_sync_global();
1350 }
10474ae8 1351
3444d7da
AK		 1352 store_gdt(&__get_cpu_var(host_gdt));
1353
10474ae8 1354 return 0;
6aa8b732
AK		 1355}
1356
543e4243
AK		 1357static void vmclear_local_vcpus(void)
1358{
1359 int cpu = raw_smp_processor_id();
1360 struct vcpu_vmx *vmx, *n;
1361
1362 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1363 local_vcpus_link)
1364 __vcpu_clear(vmx);
1365}
1366
710ff4a8
EH		 1367
1368/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1369 * tricks.
1370 */
1371static void kvm_cpu_vmxoff(void)
6aa8b732 1372{
4ecac3fd 1373 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1374}
1375
710ff4a8
EH		 1376static void hardware_disable(void *garbage)
1377{
4610c9cc
DX		 1378 if (vmm_exclusive) {
1379 vmclear_local_vcpus();
1380 kvm_cpu_vmxoff();
1381 }
7725b894 1382 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1383}
1384
1c3d14fe 1385static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1386 u32 msr, u32 *result)
1c3d14fe
YS		 1387{
1388 u32 vmx_msr_low, vmx_msr_high;
1389 u32 ctl = ctl_min | ctl_opt;
1390
1391 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1392
1393 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1394 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1395
1396 /* Ensure minimum (required) set of control bits are supported. */
1397 if (ctl_min & ~ctl)
002c7f7c 1398 return -EIO;
1c3d14fe
YS		 1399
1400 *result = ctl;
1401 return 0;
1402}
1403
002c7f7c 1404static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1405{
1406 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1407 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1408 u32 _pin_based_exec_control = 0;
1409 u32 _cpu_based_exec_control = 0;
f78e0e2e 1410 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1411 u32 _vmexit_control = 0;
1412 u32 _vmentry_control = 0;
1413
1414 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1415 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1416 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1417 &_pin_based_exec_control) < 0)
002c7f7c 1418 return -EIO;
1c3d14fe
YS		 1419
1420 min = CPU_BASED_HLT_EXITING |
1421#ifdef CONFIG_X86_64
1422 CPU_BASED_CR8_LOAD_EXITING |
1423 CPU_BASED_CR8_STORE_EXITING |
1424#endif
d56f546d
SY		 1425 CPU_BASED_CR3_LOAD_EXITING |
1426 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1427 CPU_BASED_USE_IO_BITMAPS |
1428 CPU_BASED_MOV_DR_EXITING |
a7052897 1429 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1430 CPU_BASED_MWAIT_EXITING |
1431 CPU_BASED_MONITOR_EXITING |
a7052897 1432 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1433 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1434 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1435 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1436 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1437 &_cpu_based_exec_control) < 0)
002c7f7c 1438 return -EIO;
6e5d865c
YS		 1439#ifdef CONFIG_X86_64
1440 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1441 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1442 ~CPU_BASED_CR8_STORE_EXITING;
1443#endif
f78e0e2e 1444 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1445 min2 = 0;
1446 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1447 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1448 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1449 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1450 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1451 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1452 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1453 if (adjust_vmx_controls(min2, opt2,
1454 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1455 &_cpu_based_2nd_exec_control) < 0)
1456 return -EIO;
1457 }
1458#ifndef CONFIG_X86_64
1459 if (!(_cpu_based_2nd_exec_control &
1460 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1461 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1462#endif
d56f546d 1463 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1464 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1465 enabled */
5fff7d27
GN		 1466 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1467 CPU_BASED_CR3_STORE_EXITING |
1468 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1469 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1470 vmx_capability.ept, vmx_capability.vpid);
1471 }
1c3d14fe
YS		 1472
1473 min = 0;
1474#ifdef CONFIG_X86_64
1475 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1476#endif
468d472f 1477 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1478 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1479 &_vmexit_control) < 0)
002c7f7c 1480 return -EIO;
1c3d14fe 1481
468d472f
SY		 1482 min = 0;
1483 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1484 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1485 &_vmentry_control) < 0)
002c7f7c 1486 return -EIO;
6aa8b732 1487
c68876fd 1488 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1489
1490 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1491 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1492 return -EIO;
1c3d14fe
YS		 1493
1494#ifdef CONFIG_X86_64
1495 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1496 if (vmx_msr_high & (1u<<16))
002c7f7c 1497 return -EIO;
1c3d14fe
YS		 1498#endif
1499
1500 /* Require Write-Back (WB) memory type for VMCS accesses. */
1501 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1502 return -EIO;
1c3d14fe 1503
002c7f7c
YS		 1504 vmcs_conf->size = vmx_msr_high & 0x1fff;
1505 vmcs_conf->order = get_order(vmcs_config.size);
1506 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1507
002c7f7c
YS		 1508 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1509 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1510 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1511 vmcs_conf->vmexit_ctrl = _vmexit_control;
1512 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1513
1514 return 0;
c68876fd 1515}
6aa8b732
AK		 1516
1517static struct vmcs *alloc_vmcs_cpu(int cpu)
1518{
1519 int node = cpu_to_node(cpu);
1520 struct page *pages;
1521 struct vmcs *vmcs;
1522
6484eb3e 1523 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1524 if (!pages)
1525 return NULL;
1526 vmcs = page_address(pages);
1c3d14fe
YS		 1527 memset(vmcs, 0, vmcs_config.size);
1528 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1529 return vmcs;
1530}
1531
1532static struct vmcs *alloc_vmcs(void)
1533{
d3b2c338 1534 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1535}
1536
1537static void free_vmcs(struct vmcs *vmcs)
1538{
1c3d14fe 1539 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1540}
1541
39959588 1542static void free_kvm_area(void)
6aa8b732
AK		 1543{
1544 int cpu;
1545
3230bb47 1546 for_each_possible_cpu(cpu) {
6aa8b732 1547 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1548 per_cpu(vmxarea, cpu) = NULL;
1549 }
6aa8b732
AK		 1550}
1551
6aa8b732
AK		 1552static __init int alloc_kvm_area(void)
1553{
1554 int cpu;
1555
3230bb47 1556 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1557 struct vmcs *vmcs;
1558
1559 vmcs = alloc_vmcs_cpu(cpu);
1560 if (!vmcs) {
1561 free_kvm_area();
1562 return -ENOMEM;
1563 }
1564
1565 per_cpu(vmxarea, cpu) = vmcs;
1566 }
1567 return 0;
1568}
1569
1570static __init int hardware_setup(void)
1571{
002c7f7c
YS		 1572 if (setup_vmcs_config(&vmcs_config) < 0)
1573 return -EIO;
50a37eb4
JR		 1574
1575 if (boot_cpu_has(X86_FEATURE_NX))
1576 kvm_enable_efer_bits(EFER_NX);
1577
93ba03c2
SY		 1578 if (!cpu_has_vmx_vpid())
1579 enable_vpid = 0;
1580
4bc9b982
SY		 1581 if (!cpu_has_vmx_ept() ||
1582 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1583 enable_ept = 0;
3a624e29
NK		 1584 enable_unrestricted_guest = 0;
1585 }
1586
1587 if (!cpu_has_vmx_unrestricted_guest())
1588 enable_unrestricted_guest = 0;
93ba03c2
SY		 1589
1590 if (!cpu_has_vmx_flexpriority())
1591 flexpriority_enabled = 0;
1592
95ba8273
GN		 1593 if (!cpu_has_vmx_tpr_shadow())
1594 kvm_x86_ops->update_cr8_intercept = NULL;
1595
54dee993
MT		 1596 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1597 kvm_disable_largepages();
1598
4b8d54f9
ZE		 1599 if (!cpu_has_vmx_ple())
1600 ple_gap = 0;
1601
6aa8b732
AK		 1602 return alloc_kvm_area();
1603}
1604
1605static __exit void hardware_unsetup(void)
1606{
1607 free_kvm_area();
1608}
1609
6aa8b732
AK		 1610static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1611{
1612 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1613
6af11b9e 1614 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1615 vmcs_write16(sf->selector, save->selector);
1616 vmcs_writel(sf->base, save->base);
1617 vmcs_write32(sf->limit, save->limit);
1618 vmcs_write32(sf->ar_bytes, save->ar);
1619 } else {
1620 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1621 << AR_DPL_SHIFT;
1622 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1623 }
1624}
1625
1626static void enter_pmode(struct kvm_vcpu *vcpu)
1627{
1628 unsigned long flags;
a89a8fb9 1629 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1630
a89a8fb9 1631 vmx->emulation_required = 1;
7ffd92c5 1632 vmx->rmode.vm86_active = 0;
6aa8b732 1633
7ffd92c5
AK		 1634 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1635 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1636 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1637
1638 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1639 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1640 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1641 vmcs_writel(GUEST_RFLAGS, flags);
1642
66aee91a
RR		 1643 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1644 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1645
1646 update_exception_bitmap(vcpu);
1647
a89a8fb9
MG		 1648 if (emulate_invalid_guest_state)
1649 return;
1650
7ffd92c5
AK		 1651 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1652 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1653 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1654 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1655
1656 vmcs_write16(GUEST_SS_SELECTOR, 0);
1657 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1658
1659 vmcs_write16(GUEST_CS_SELECTOR,
1660 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1661 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1662}
1663
d77c26fc 1664static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1665{
bfc6d222 1666 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1667 struct kvm_memslots *slots;
1668 gfn_t base_gfn;
1669
90d83dc3 1670 slots = kvm_memslots(kvm);
f495c6e5 1671 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1672 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1673 return base_gfn << PAGE_SHIFT;
1674 }
bfc6d222 1675 return kvm->arch.tss_addr;
6aa8b732
AK		 1676}
1677
1678static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1679{
1680 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1681
1682 save->selector = vmcs_read16(sf->selector);
1683 save->base = vmcs_readl(sf->base);
1684 save->limit = vmcs_read32(sf->limit);
1685 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1686 vmcs_write16(sf->selector, save->base >> 4);
1687 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1688 vmcs_write32(sf->limit, 0xffff);
1689 vmcs_write32(sf->ar_bytes, 0xf3);
1690}
1691
1692static void enter_rmode(struct kvm_vcpu *vcpu)
1693{
1694 unsigned long flags;
a89a8fb9 1695 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1696
3a624e29
NK		 1697 if (enable_unrestricted_guest)
1698 return;
1699
a89a8fb9 1700 vmx->emulation_required = 1;
7ffd92c5 1701 vmx->rmode.vm86_active = 1;
6aa8b732 1702
7ffd92c5 1703 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1704 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1705
7ffd92c5 1706 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1707 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1708
7ffd92c5 1709 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1710 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1711
1712 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1713 vmx->rmode.save_rflags = flags;
6aa8b732 1714
053de044 1715 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1716
1717 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1718 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1719 update_exception_bitmap(vcpu);
1720
a89a8fb9
MG		 1721 if (emulate_invalid_guest_state)
1722 goto continue_rmode;
1723
6aa8b732
AK		 1724 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1725 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1726 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1727
1728 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1729 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1730 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1731 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1732 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1733
7ffd92c5
AK		 1734 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1735 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1736 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1737 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1738
a89a8fb9 1739continue_rmode:
8668a3c4 1740 kvm_mmu_reset_context(vcpu);
b7ebfb05 1741 init_rmode(vcpu->kvm);
6aa8b732
AK		 1742}
1743
401d10de
AS		 1744static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1745{
1746 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1747 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1748
1749 if (!msr)
1750 return;
401d10de 1751
44ea2b17
AK		 1752 /*
1753 * Force kernel_gs_base reloading before EFER changes, as control
1754 * of this msr depends on is_long_mode().
1755 */
1756 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1757 vcpu->arch.efer = efer;
401d10de
AS		 1758 if (efer & EFER_LMA) {
1759 vmcs_write32(VM_ENTRY_CONTROLS,
1760 vmcs_read32(VM_ENTRY_CONTROLS) |
1761 VM_ENTRY_IA32E_MODE);
1762 msr->data = efer;
1763 } else {
1764 vmcs_write32(VM_ENTRY_CONTROLS,
1765 vmcs_read32(VM_ENTRY_CONTROLS) &
1766 ~VM_ENTRY_IA32E_MODE);
1767
1768 msr->data = efer & ~EFER_LME;
1769 }
1770 setup_msrs(vmx);
1771}
1772
05b3e0c2 1773#ifdef CONFIG_X86_64
6aa8b732
AK		 1774
1775static void enter_lmode(struct kvm_vcpu *vcpu)
1776{
1777 u32 guest_tr_ar;
1778
1779 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1780 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1781 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1782 __func__);
6aa8b732
AK		 1783 vmcs_write32(GUEST_TR_AR_BYTES,
1784 (guest_tr_ar & ~AR_TYPE_MASK)
1785 | AR_TYPE_BUSY_64_TSS);
1786 }
da38f438 1787 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1788}
1789
1790static void exit_lmode(struct kvm_vcpu *vcpu)
1791{
6aa8b732
AK		 1792 vmcs_write32(VM_ENTRY_CONTROLS,
1793 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1794 & ~VM_ENTRY_IA32E_MODE);
da38f438 1795 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1796}
1797
1798#endif
1799
2384d2b3
SY		 1800static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1801{
b9d762fa 1802 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1803 if (enable_ept) {
1804 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1805 return;
4e1096d2 1806 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1807 }
2384d2b3
SY		 1808}
1809
e8467fda
AK		 1810static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1811{
1812 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1813
1814 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1815 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1816}
1817
25c4c276 1818static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1819{
fc78f519
AK		 1820 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1821
1822 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1823 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1824}
1825
1439442c
SY		 1826static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1827{
6de4f3ad
AK		 1828 if (!test_bit(VCPU_EXREG_PDPTR,
1829 (unsigned long *)&vcpu->arch.regs_dirty))
1830 return;
1831
1439442c 1832 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1833 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1834 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1835 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1836 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1837 }
1838}
1839
8f5d549f
AK		 1840static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1841{
1842 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1843 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1844 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1845 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1846 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1847 }
6de4f3ad
AK		 1848
1849 __set_bit(VCPU_EXREG_PDPTR,
1850 (unsigned long *)&vcpu->arch.regs_avail);
1851 __set_bit(VCPU_EXREG_PDPTR,
1852 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1853}
1854
1439442c
SY		 1855static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1856
1857static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1858 unsigned long cr0,
1859 struct kvm_vcpu *vcpu)
1860{
1861 if (!(cr0 & X86_CR0_PG)) {
1862 /* From paging/starting to nonpaging */
1863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1864 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1865 (CPU_BASED_CR3_LOAD_EXITING |
1866 CPU_BASED_CR3_STORE_EXITING));
1867 vcpu->arch.cr0 = cr0;
fc78f519 1868 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1869 } else if (!is_paging(vcpu)) {
1870 /* From nonpaging to paging */
1871 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1872 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1873 ~(CPU_BASED_CR3_LOAD_EXITING |
1874 CPU_BASED_CR3_STORE_EXITING));
1875 vcpu->arch.cr0 = cr0;
fc78f519 1876 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1877 }
95eb84a7
SY		 1878
1879 if (!(cr0 & X86_CR0_WP))
1880 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1881}
1882
6aa8b732
AK		 1883static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1884{
7ffd92c5 1885 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1886 unsigned long hw_cr0;
1887
1888 if (enable_unrestricted_guest)
1889 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1890 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1891 else
1892 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1893
7ffd92c5 1894 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1895 enter_pmode(vcpu);
1896
7ffd92c5 1897 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1898 enter_rmode(vcpu);
1899
05b3e0c2 1900#ifdef CONFIG_X86_64
f6801dff 1901 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1902 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1903 enter_lmode(vcpu);
707d92fa 1904 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1905 exit_lmode(vcpu);
1906 }
1907#endif
1908
089d034e 1909 if (enable_ept)
1439442c
SY		 1910 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1911
02daab21 1912 if (!vcpu->fpu_active)
81231c69 1913 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1914
6aa8b732 1915 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1916 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1917 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1918}
1919
1439442c
SY		 1920static u64 construct_eptp(unsigned long root_hpa)
1921{
1922 u64 eptp;
1923
1924 /* TODO write the value reading from MSR */
1925 eptp = VMX_EPT_DEFAULT_MT |
1926 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1927 eptp |= (root_hpa & PAGE_MASK);
1928
1929 return eptp;
1930}
1931
6aa8b732
AK		 1932static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1933{
1439442c
SY		 1934 unsigned long guest_cr3;
1935 u64 eptp;
1936
1937 guest_cr3 = cr3;
089d034e 1938 if (enable_ept) {
1439442c
SY		 1939 eptp = construct_eptp(cr3);
1940 vmcs_write64(EPT_POINTER, eptp);
1439442c 1941 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1942 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1943 ept_load_pdptrs(vcpu);
1439442c
SY		 1944 }
1945
2384d2b3 1946 vmx_flush_tlb(vcpu);
1439442c 1947 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1948}
1949
1950static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1951{
7ffd92c5 1952 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1953 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1954
ad312c7c 1955 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1956 if (enable_ept) {
1957 if (!is_paging(vcpu)) {
1958 hw_cr4 &= ~X86_CR4_PAE;
1959 hw_cr4 |= X86_CR4_PSE;
1960 } else if (!(cr4 & X86_CR4_PAE)) {
1961 hw_cr4 &= ~X86_CR4_PAE;
1962 }
1963 }
1439442c
SY		 1964
1965 vmcs_writel(CR4_READ_SHADOW, cr4);
1966 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1967}
1968
6aa8b732
AK		 1969static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1970{
1971 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1972
1973 return vmcs_readl(sf->base);
1974}
1975
1976static void vmx_get_segment(struct kvm_vcpu *vcpu,
1977 struct kvm_segment *var, int seg)
1978{
1979 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1980 u32 ar;
1981
1982 var->base = vmcs_readl(sf->base);
1983 var->limit = vmcs_read32(sf->limit);
1984 var->selector = vmcs_read16(sf->selector);
1985 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1986 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1987 ar = 0;
1988 var->type = ar & 15;
1989 var->s = (ar >> 4) & 1;
1990 var->dpl = (ar >> 5) & 3;
1991 var->present = (ar >> 7) & 1;
1992 var->avl = (ar >> 12) & 1;
1993 var->l = (ar >> 13) & 1;
1994 var->db = (ar >> 14) & 1;
1995 var->g = (ar >> 15) & 1;
1996 var->unusable = (ar >> 16) & 1;
1997}
1998
2e4d2653
IE		 1999static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2000{
3eeb3288 2001 if (!is_protmode(vcpu))
2e4d2653
IE		 2002 return 0;
2003
2004 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2005 return 3;
2006
eab4b8aa 2007 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2008}
2009
653e3108 2010static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2011{
6aa8b732
AK		 2012 u32 ar;
2013
653e3108 2014 if (var->unusable)
6aa8b732
AK		 2015 ar = 1 << 16;
2016 else {
2017 ar = var->type & 15;
2018 ar |= (var->s & 1) << 4;
2019 ar |= (var->dpl & 3) << 5;
2020 ar |= (var->present & 1) << 7;
2021 ar |= (var->avl & 1) << 12;
2022 ar |= (var->l & 1) << 13;
2023 ar |= (var->db & 1) << 14;
2024 ar |= (var->g & 1) << 15;
2025 }
f7fbf1fd
UL		 2026 if (ar == 0) /* a 0 value means unusable */
2027 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2028
2029 return ar;
2030}
2031
2032static void vmx_set_segment(struct kvm_vcpu *vcpu,
2033 struct kvm_segment *var, int seg)
2034{
7ffd92c5 2035 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2036 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2037 u32 ar;
2038
7ffd92c5
AK		 2039 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2040 vmx->rmode.tr.selector = var->selector;
2041 vmx->rmode.tr.base = var->base;
2042 vmx->rmode.tr.limit = var->limit;
2043 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2044 return;
2045 }
2046 vmcs_writel(sf->base, var->base);
2047 vmcs_write32(sf->limit, var->limit);
2048 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2049 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2050 /*
2051 * Hack real-mode segments into vm86 compatibility.
2052 */
2053 if (var->base == 0xffff0000 && var->selector == 0xf000)
2054 vmcs_writel(sf->base, 0xf0000);
2055 ar = 0xf3;
2056 } else
2057 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2058
2059 /*
2060 * Fix the "Accessed" bit in AR field of segment registers for older
2061 * qemu binaries.
2062 * IA32 arch specifies that at the time of processor reset the
2063 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2064 * is setting it to 0 in the usedland code. This causes invalid guest
2065 * state vmexit when "unrestricted guest" mode is turned on.
2066 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2067 * tree. Newer qemu binaries with that qemu fix would not need this
2068 * kvm hack.
2069 */
2070 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2071 ar |= 0x1; /* Accessed */
2072
6aa8b732
AK		 2073 vmcs_write32(sf->ar_bytes, ar);
2074}
2075
6aa8b732
AK		 2076static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2077{
2078 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2079
2080 *db = (ar >> 14) & 1;
2081 *l = (ar >> 13) & 1;
2082}
2083
89a27f4d 2084static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2085{
89a27f4d
GN		 2086 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2087 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2088}
2089
89a27f4d 2090static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2091{
89a27f4d
GN		 2092 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2093 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2094}
2095
89a27f4d 2096static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2097{
89a27f4d
GN		 2098 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2099 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2100}
2101
89a27f4d 2102static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2103{
89a27f4d
GN		 2104 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2105 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2106}
2107
648dfaa7
MG		 2108static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2109{
2110 struct kvm_segment var;
2111 u32 ar;
2112
2113 vmx_get_segment(vcpu, &var, seg);
2114 ar = vmx_segment_access_rights(&var);
2115
2116 if (var.base != (var.selector << 4))
2117 return false;
2118 if (var.limit != 0xffff)
2119 return false;
2120 if (ar != 0xf3)
2121 return false;
2122
2123 return true;
2124}
2125
2126static bool code_segment_valid(struct kvm_vcpu *vcpu)
2127{
2128 struct kvm_segment cs;
2129 unsigned int cs_rpl;
2130
2131 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2132 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2133
1872a3f4
AK		 2134 if (cs.unusable)
2135 return false;
648dfaa7
MG		 2136 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2137 return false;
2138 if (!cs.s)
2139 return false;
1872a3f4 2140 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2141 if (cs.dpl > cs_rpl)
2142 return false;
1872a3f4 2143 } else {
648dfaa7
MG		 2144 if (cs.dpl != cs_rpl)
2145 return false;
2146 }
2147 if (!cs.present)
2148 return false;
2149
2150 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2151 return true;
2152}
2153
2154static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2155{
2156 struct kvm_segment ss;
2157 unsigned int ss_rpl;
2158
2159 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2160 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2161
1872a3f4
AK		 2162 if (ss.unusable)
2163 return true;
2164 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2165 return false;
2166 if (!ss.s)
2167 return false;
2168 if (ss.dpl != ss_rpl) /* DPL != RPL */
2169 return false;
2170 if (!ss.present)
2171 return false;
2172
2173 return true;
2174}
2175
2176static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2177{
2178 struct kvm_segment var;
2179 unsigned int rpl;
2180
2181 vmx_get_segment(vcpu, &var, seg);
2182 rpl = var.selector & SELECTOR_RPL_MASK;
2183
1872a3f4
AK		 2184 if (var.unusable)
2185 return true;
648dfaa7
MG		 2186 if (!var.s)
2187 return false;
2188 if (!var.present)
2189 return false;
2190 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2191 if (var.dpl < rpl) /* DPL < RPL */
2192 return false;
2193 }
2194
2195 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2196 * rights flags
2197 */
2198 return true;
2199}
2200
2201static bool tr_valid(struct kvm_vcpu *vcpu)
2202{
2203 struct kvm_segment tr;
2204
2205 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2206
1872a3f4
AK		 2207 if (tr.unusable)
2208 return false;
648dfaa7
MG		 2209 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2210 return false;
1872a3f4 2211 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2212 return false;
2213 if (!tr.present)
2214 return false;
2215
2216 return true;
2217}
2218
2219static bool ldtr_valid(struct kvm_vcpu *vcpu)
2220{
2221 struct kvm_segment ldtr;
2222
2223 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2224
1872a3f4
AK		 2225 if (ldtr.unusable)
2226 return true;
648dfaa7
MG		 2227 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2228 return false;
2229 if (ldtr.type != 2)
2230 return false;
2231 if (!ldtr.present)
2232 return false;
2233
2234 return true;
2235}
2236
2237static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2238{
2239 struct kvm_segment cs, ss;
2240
2241 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2242 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2243
2244 return ((cs.selector & SELECTOR_RPL_MASK) ==
2245 (ss.selector & SELECTOR_RPL_MASK));
2246}
2247
2248/*
2249 * Check if guest state is valid. Returns true if valid, false if
2250 * not.
2251 * We assume that registers are always usable
2252 */
2253static bool guest_state_valid(struct kvm_vcpu *vcpu)
2254{
2255 /* real mode guest state checks */
3eeb3288 2256 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2257 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2258 return false;
2259 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2260 return false;
2261 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2262 return false;
2263 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2264 return false;
2265 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2266 return false;
2267 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2268 return false;
2269 } else {
2270 /* protected mode guest state checks */
2271 if (!cs_ss_rpl_check(vcpu))
2272 return false;
2273 if (!code_segment_valid(vcpu))
2274 return false;
2275 if (!stack_segment_valid(vcpu))
2276 return false;
2277 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2278 return false;
2279 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2280 return false;
2281 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2282 return false;
2283 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2284 return false;
2285 if (!tr_valid(vcpu))
2286 return false;
2287 if (!ldtr_valid(vcpu))
2288 return false;
2289 }
2290 /* TODO:
2291 * - Add checks on RIP
2292 * - Add checks on RFLAGS
2293 */
2294
2295 return true;
2296}
2297
d77c26fc 2298static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2299{
6aa8b732 2300 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2301 u16 data = 0;
10589a46 2302 int ret = 0;
195aefde 2303 int r;
6aa8b732 2304
195aefde
IE		 2305 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2306 if (r < 0)
10589a46 2307 goto out;
195aefde 2308 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2309 r = kvm_write_guest_page(kvm, fn++, &data,
2310 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2311 if (r < 0)
10589a46 2312 goto out;
195aefde
IE		 2313 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2314 if (r < 0)
10589a46 2315 goto out;
195aefde
IE		 2316 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2317 if (r < 0)
10589a46 2318 goto out;
195aefde 2319 data = ~0;
10589a46
MT		 2320 r = kvm_write_guest_page(kvm, fn, &data,
2321 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2322 sizeof(u8));
195aefde 2323 if (r < 0)
10589a46
MT		 2324 goto out;
2325
2326 ret = 1;
2327out:
10589a46 2328 return ret;
6aa8b732
AK		 2329}
2330
b7ebfb05
SY		 2331static int init_rmode_identity_map(struct kvm *kvm)
2332{
2333 int i, r, ret;
2334 pfn_t identity_map_pfn;
2335 u32 tmp;
2336
089d034e 2337 if (!enable_ept)
b7ebfb05
SY		 2338 return 1;
2339 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2340 printk(KERN_ERR "EPT: identity-mapping pagetable "
2341 "haven't been allocated!\n");
2342 return 0;
2343 }
2344 if (likely(kvm->arch.ept_identity_pagetable_done))
2345 return 1;
2346 ret = 0;
b927a3ce 2347 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2348 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2349 if (r < 0)
2350 goto out;
2351 /* Set up identity-mapping pagetable for EPT in real mode */
2352 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2353 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2354 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2355 r = kvm_write_guest_page(kvm, identity_map_pfn,
2356 &tmp, i * sizeof(tmp), sizeof(tmp));
2357 if (r < 0)
2358 goto out;
2359 }
2360 kvm->arch.ept_identity_pagetable_done = true;
2361 ret = 1;
2362out:
2363 return ret;
2364}
2365
6aa8b732
AK		 2366static void seg_setup(int seg)
2367{
2368 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2369 unsigned int ar;
6aa8b732
AK		 2370
2371 vmcs_write16(sf->selector, 0);
2372 vmcs_writel(sf->base, 0);
2373 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2374 if (enable_unrestricted_guest) {
2375 ar = 0x93;
2376 if (seg == VCPU_SREG_CS)
2377 ar |= 0x08; /* code segment */
2378 } else
2379 ar = 0xf3;
2380
2381 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2382}
2383
f78e0e2e
SY		 2384static int alloc_apic_access_page(struct kvm *kvm)
2385{
2386 struct kvm_userspace_memory_region kvm_userspace_mem;
2387 int r = 0;
2388
79fac95e 2389 mutex_lock(&kvm->slots_lock);
bfc6d222 2390 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2391 goto out;
2392 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2393 kvm_userspace_mem.flags = 0;
2394 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2395 kvm_userspace_mem.memory_size = PAGE_SIZE;
2396 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2397 if (r)
2398 goto out;
72dc67a6 2399
bfc6d222 2400 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2401out:
79fac95e 2402 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2403 return r;
2404}
2405
b7ebfb05
SY		 2406static int alloc_identity_pagetable(struct kvm *kvm)
2407{
2408 struct kvm_userspace_memory_region kvm_userspace_mem;
2409 int r = 0;
2410
79fac95e 2411 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2412 if (kvm->arch.ept_identity_pagetable)
2413 goto out;
2414 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2415 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2416 kvm_userspace_mem.guest_phys_addr =
2417 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2418 kvm_userspace_mem.memory_size = PAGE_SIZE;
2419 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2420 if (r)
2421 goto out;
2422
b7ebfb05 2423 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2424 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2425out:
79fac95e 2426 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2427 return r;
2428}
2429
2384d2b3
SY		 2430static void allocate_vpid(struct vcpu_vmx *vmx)
2431{
2432 int vpid;
2433
2434 vmx->vpid = 0;
919818ab 2435 if (!enable_vpid)
2384d2b3
SY		 2436 return;
2437 spin_lock(&vmx_vpid_lock);
2438 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2439 if (vpid < VMX_NR_VPIDS) {
2440 vmx->vpid = vpid;
2441 __set_bit(vpid, vmx_vpid_bitmap);
2442 }
2443 spin_unlock(&vmx_vpid_lock);
2444}
2445
cdbecfc3
LJ		 2446static void free_vpid(struct vcpu_vmx *vmx)
2447{
2448 if (!enable_vpid)
2449 return;
2450 spin_lock(&vmx_vpid_lock);
2451 if (vmx->vpid != 0)
2452 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2453 spin_unlock(&vmx_vpid_lock);
2454}
2455
5897297b 2456static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2457{
3e7c73e9 2458 int f = sizeof(unsigned long);
25c5f225
SY		 2459
2460 if (!cpu_has_vmx_msr_bitmap())
2461 return;
2462
2463 /*
2464 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2465 * have the write-low and read-high bitmap offsets the wrong way round.
2466 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2467 */
25c5f225 2468 if (msr <= 0x1fff) {
3e7c73e9
AK		 2469 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2470 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2471 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2472 msr &= 0x1fff;
3e7c73e9
AK		 2473 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2474 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2475 }
25c5f225
SY		 2476}
2477
5897297b
AK		 2478static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2479{
2480 if (!longmode_only)
2481 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2482 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2483}
2484
6aa8b732
AK		 2485/*
2486 * Sets up the vmcs for emulated real mode.
2487 */
8b9cf98c 2488static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2489{
468d472f 2490 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2491 u32 junk;
f4e1b3c8 2492 u64 host_pat;
6aa8b732 2493 unsigned long a;
89a27f4d 2494 struct desc_ptr dt;
6aa8b732 2495 int i;
cd2276a7 2496 unsigned long kvm_vmx_return;
6e5d865c 2497 u32 exec_control;
6aa8b732 2498
6aa8b732 2499 /* I/O */
3e7c73e9
AK		 2500 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2501 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2502
25c5f225 2503 if (cpu_has_vmx_msr_bitmap())
5897297b 2504 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2505
6aa8b732
AK		 2506 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2507
6aa8b732 2508 /* Control */
1c3d14fe
YS		 2509 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2510 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2511
2512 exec_control = vmcs_config.cpu_based_exec_ctrl;
2513 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2514 exec_control &= ~CPU_BASED_TPR_SHADOW;
2515#ifdef CONFIG_X86_64
2516 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2517 CPU_BASED_CR8_LOAD_EXITING;
2518#endif
2519 }
089d034e 2520 if (!enable_ept)
d56f546d 2521 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2522 CPU_BASED_CR3_LOAD_EXITING |
2523 CPU_BASED_INVLPG_EXITING;
6e5d865c 2524 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2525
83ff3b9d
SY		 2526 if (cpu_has_secondary_exec_ctrls()) {
2527 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2528 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2529 exec_control &=
2530 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2531 if (vmx->vpid == 0)
2532 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2533 if (!enable_ept) {
d56f546d 2534 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2535 enable_unrestricted_guest = 0;
2536 }
3a624e29
NK		 2537 if (!enable_unrestricted_guest)
2538 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2539 if (!ple_gap)
2540 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2541 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2542 }
f78e0e2e 2543
4b8d54f9
ZE		 2544 if (ple_gap) {
2545 vmcs_write32(PLE_GAP, ple_gap);
2546 vmcs_write32(PLE_WINDOW, ple_window);
2547 }
2548
c7addb90
AK		 2549 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2550 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2551 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2552
1c11e713 2553 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2554 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2555 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2556
2557 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2558 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2559 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2560 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2561 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2562 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2563#ifdef CONFIG_X86_64
6aa8b732
AK		 2564 rdmsrl(MSR_FS_BASE, a);
2565 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2566 rdmsrl(MSR_GS_BASE, a);
2567 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2568#else
2569 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2570 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2571#endif
2572
2573 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2574
ec68798c 2575 native_store_idt(&dt);
89a27f4d 2576 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2577
d77c26fc 2578 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2579 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2580 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2581 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2582 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2583 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2584 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2585
2586 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2587 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2588 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2589 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2590 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2591 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2592
468d472f
SY		 2593 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2594 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2595 host_pat = msr_low | ((u64) msr_high << 32);
2596 vmcs_write64(HOST_IA32_PAT, host_pat);
2597 }
2598 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2599 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2600 host_pat = msr_low | ((u64) msr_high << 32);
2601 /* Write the default value follow host pat */
2602 vmcs_write64(GUEST_IA32_PAT, host_pat);
2603 /* Keep arch.pat sync with GUEST_IA32_PAT */
2604 vmx->vcpu.arch.pat = host_pat;
2605 }
2606
6aa8b732
AK		 2607 for (i = 0; i < NR_VMX_MSR; ++i) {
2608 u32 index = vmx_msr_index[i];
2609 u32 data_low, data_high;
a2fa3e9f 2610 int j = vmx->nmsrs;
6aa8b732
AK		 2611
2612 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2613 continue;
432bd6cb
AK		 2614 if (wrmsr_safe(index, data_low, data_high) < 0)
2615 continue;
26bb0981
AK		 2616 vmx->guest_msrs[j].index = i;
2617 vmx->guest_msrs[j].data = 0;
d5696725 2618 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2619 ++vmx->nmsrs;
6aa8b732 2620 }
6aa8b732 2621
1c3d14fe 2622 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2623
2624 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2625 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2626
e00c8cf2 2627 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2628 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2629 if (enable_ept)
2630 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2631 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2632
99e3e30a 2633 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2634
e00c8cf2
AK		 2635 return 0;
2636}
2637
b7ebfb05
SY		 2638static int init_rmode(struct kvm *kvm)
2639{
4b9d3a04
XG		 2640 int idx, ret = 0;
2641
2642 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2643 if (!init_rmode_tss(kvm))
4b9d3a04 2644 goto exit;
b7ebfb05 2645 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2646 goto exit;
2647
2648 ret = 1;
2649exit:
2650 srcu_read_unlock(&kvm->srcu, idx);
2651 return ret;
b7ebfb05
SY		 2652}
2653
e00c8cf2
AK		 2654static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2655{
2656 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657 u64 msr;
4b9d3a04 2658 int ret;
e00c8cf2 2659
5fdbf976 2660 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2661 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2662 ret = -ENOMEM;
2663 goto out;
2664 }
2665
7ffd92c5 2666 vmx->rmode.vm86_active = 0;
e00c8cf2 2667
3b86cd99
JK		 2668 vmx->soft_vnmi_blocked = 0;
2669
ad312c7c 2670 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2671 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2672 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2673 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2674 msr |= MSR_IA32_APICBASE_BSP;
2675 kvm_set_apic_base(&vmx->vcpu, msr);
2676
10ab25cd
JK		 2677 ret = fx_init(&vmx->vcpu);
2678 if (ret != 0)
2679 goto out;
e00c8cf2 2680
5706be0d 2681 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2682 /*
2683 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2684 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2685 */
c5af89b6 2686 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2687 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2688 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2689 } else {
ad312c7c
ZX		 2690 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2691 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2692 }
e00c8cf2
AK		 2693
2694 seg_setup(VCPU_SREG_DS);
2695 seg_setup(VCPU_SREG_ES);
2696 seg_setup(VCPU_SREG_FS);
2697 seg_setup(VCPU_SREG_GS);
2698 seg_setup(VCPU_SREG_SS);
2699
2700 vmcs_write16(GUEST_TR_SELECTOR, 0);
2701 vmcs_writel(GUEST_TR_BASE, 0);
2702 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2703 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2704
2705 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2706 vmcs_writel(GUEST_LDTR_BASE, 0);
2707 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2708 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2709
2710 vmcs_write32(GUEST_SYSENTER_CS, 0);
2711 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2712 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2713
2714 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2715 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2716 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2717 else
5fdbf976
MT		 2718 kvm_rip_write(vcpu, 0);
2719 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2720
e00c8cf2
AK		 2721 vmcs_writel(GUEST_DR7, 0x400);
2722
2723 vmcs_writel(GUEST_GDTR_BASE, 0);
2724 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2725
2726 vmcs_writel(GUEST_IDTR_BASE, 0);
2727 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2728
2729 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2730 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2731 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2732
e00c8cf2
AK		 2733 /* Special registers */
2734 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2735
2736 setup_msrs(vmx);
2737
6aa8b732
AK		 2738 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2739
f78e0e2e
SY		 2740 if (cpu_has_vmx_tpr_shadow()) {
2741 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2742 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2743 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2744 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2745 vmcs_write32(TPR_THRESHOLD, 0);
2746 }
2747
2748 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2749 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2750 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2751
2384d2b3
SY		 2752 if (vmx->vpid != 0)
2753 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2754
fa40052c 2755 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2756 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2757 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2758 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2759 vmx_fpu_activate(&vmx->vcpu);
2760 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2761
b9d762fa 2762 vpid_sync_context(vmx);
2384d2b3 2763
3200f405 2764 ret = 0;
6aa8b732 2765
a89a8fb9
MG		 2766 /* HACK: Don't enable emulation on guest boot/reset */
2767 vmx->emulation_required = 0;
2768
6aa8b732
AK		 2769out:
2770 return ret;
2771}
2772
3b86cd99
JK		 2773static void enable_irq_window(struct kvm_vcpu *vcpu)
2774{
2775 u32 cpu_based_vm_exec_control;
2776
2777 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2778 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2780}
2781
2782static void enable_nmi_window(struct kvm_vcpu *vcpu)
2783{
2784 u32 cpu_based_vm_exec_control;
2785
2786 if (!cpu_has_virtual_nmis()) {
2787 enable_irq_window(vcpu);
2788 return;
2789 }
2790
2791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2792 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2794}
2795
66fd3f7f 2796static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2797{
9c8cba37 2798 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2799 uint32_t intr;
2800 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2801
229456fc 2802 trace_kvm_inj_virq(irq);
2714d1d3 2803
fa89a817 2804 ++vcpu->stat.irq_injections;
7ffd92c5 2805 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2806 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2807 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2808 return;
2809 }
66fd3f7f
GN		 2810 intr = irq | INTR_INFO_VALID_MASK;
2811 if (vcpu->arch.interrupt.soft) {
2812 intr |= INTR_TYPE_SOFT_INTR;
2813 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2814 vmx->vcpu.arch.event_exit_inst_len);
2815 } else
2816 intr |= INTR_TYPE_EXT_INTR;
2817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2818}
2819
f08864b4
SY		 2820static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2821{
66a5a347
JK		 2822 struct vcpu_vmx *vmx = to_vmx(vcpu);
2823
3b86cd99
JK		 2824 if (!cpu_has_virtual_nmis()) {
2825 /*
2826 * Tracking the NMI-blocked state in software is built upon
2827 * finding the next open IRQ window. This, in turn, depends on
2828 * well-behaving guests: They have to keep IRQs disabled at
2829 * least as long as the NMI handler runs. Otherwise we may
2830 * cause NMI nesting, maybe breaking the guest. But as this is
2831 * highly unlikely, we can live with the residual risk.
2832 */
2833 vmx->soft_vnmi_blocked = 1;
2834 vmx->vnmi_blocked_time = 0;
2835 }
2836
487b391d 2837 ++vcpu->stat.nmi_injections;
7ffd92c5 2838 if (vmx->rmode.vm86_active) {
a92601bb
MG		 2839 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2840 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2841 return;
2842 }
f08864b4
SY		 2843 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2844 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2845}
2846
c4282df9 2847static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2848{
3b86cd99 2849 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2850 return 0;
33f089ca 2851
c4282df9 2852 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2853 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2854}
2855
3cfc3092
JK		 2856static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2857{
2858 if (!cpu_has_virtual_nmis())
2859 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2860 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2861}
2862
2863static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2864{
2865 struct vcpu_vmx *vmx = to_vmx(vcpu);
2866
2867 if (!cpu_has_virtual_nmis()) {
2868 if (vmx->soft_vnmi_blocked != masked) {
2869 vmx->soft_vnmi_blocked = masked;
2870 vmx->vnmi_blocked_time = 0;
2871 }
2872 } else {
2873 if (masked)
2874 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2875 GUEST_INTR_STATE_NMI);
2876 else
2877 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2878 GUEST_INTR_STATE_NMI);
2879 }
2880}
2881
78646121
GN		 2882static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2883{
c4282df9
GN		 2884 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2885 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2886 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2887}
2888
cbc94022
IE		 2889static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2890{
2891 int ret;
2892 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2893 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2894 .guest_phys_addr = addr,
2895 .memory_size = PAGE_SIZE * 3,
2896 .flags = 0,
2897 };
2898
2899 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2900 if (ret)
2901 return ret;
bfc6d222 2902 kvm->arch.tss_addr = addr;
cbc94022
IE		 2903 return 0;
2904}
2905
6aa8b732
AK		 2906static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2907 int vec, u32 err_code)
2908{
b3f37707
NK		 2909 /*
2910 * Instruction with address size override prefix opcode 0x67
2911 * Cause the #SS fault with 0 error code in VM86 mode.
2912 */
2913 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2914 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2915 return 1;
77ab6db0
JK		 2916 /*
2917 * Forward all other exceptions that are valid in real mode.
2918 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2919 * the required debugging infrastructure rework.
2920 */
2921 switch (vec) {
77ab6db0 2922 case DB_VECTOR:
d0bfb940
JK		 2923 if (vcpu->guest_debug &
2924 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2925 return 0;
2926 kvm_queue_exception(vcpu, vec);
2927 return 1;
77ab6db0 2928 case BP_VECTOR:
c573cd22
JK		 2929 /*
2930 * Update instruction length as we may reinject the exception
2931 * from user space while in guest debugging mode.
2932 */
2933 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2934 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2936 return 0;
2937 /* fall through */
2938 case DE_VECTOR:
77ab6db0
JK		 2939 case OF_VECTOR:
2940 case BR_VECTOR:
2941 case UD_VECTOR:
2942 case DF_VECTOR:
2943 case SS_VECTOR:
2944 case GP_VECTOR:
2945 case MF_VECTOR:
2946 kvm_queue_exception(vcpu, vec);
2947 return 1;
2948 }
6aa8b732
AK		 2949 return 0;
2950}
2951
a0861c02
AK		 2952/*
2953 * Trigger machine check on the host. We assume all the MSRs are already set up
2954 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2955 * We pass a fake environment to the machine check handler because we want
2956 * the guest to be always treated like user space, no matter what context
2957 * it used internally.
2958 */
2959static void kvm_machine_check(void)
2960{
2961#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2962 struct pt_regs regs = {
2963 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2964 .flags = X86_EFLAGS_IF,
2965 };
2966
2967 do_machine_check(&regs, 0);
2968#endif
2969}
2970
851ba692 2971static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2972{
2973 /* already handled by vcpu_run */
2974 return 1;
2975}
2976
851ba692 2977static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2978{
1155f76a 2979 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2980 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2981 u32 intr_info, ex_no, error_code;
42dbaa5a 2982 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2983 u32 vect_info;
2984 enum emulation_result er;
2985
1155f76a 2986 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2987 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2988
a0861c02 2989 if (is_machine_check(intr_info))
851ba692 2990 return handle_machine_check(vcpu);
a0861c02 2991
6aa8b732 2992 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2993 !is_page_fault(intr_info)) {
2994 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2995 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2996 vcpu->run->internal.ndata = 2;
2997 vcpu->run->internal.data[0] = vect_info;
2998 vcpu->run->internal.data[1] = intr_info;
2999 return 0;
3000 }
6aa8b732 3001
e4a41889 3002 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3003 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3004
3005 if (is_no_device(intr_info)) {
5fd86fcf 3006 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3007 return 1;
3008 }
3009
7aa81cc0 3010 if (is_invalid_opcode(intr_info)) {
851ba692 3011 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3012 if (er != EMULATE_DONE)
7ee5d940 3013 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3014 return 1;
3015 }
3016
6aa8b732 3017 error_code = 0;
5fdbf976 3018 rip = kvm_rip_read(vcpu);
2e11384c 3019 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3020 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3021 if (is_page_fault(intr_info)) {
1439442c 3022 /* EPT won't cause page fault directly */
089d034e 3023 if (enable_ept)
1439442c 3024 BUG();
6aa8b732 3025 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3026 trace_kvm_page_fault(cr2, error_code);
3027
3298b75c 3028 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3029 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3030 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3031 }
3032
7ffd92c5 3033 if (vmx->rmode.vm86_active &&
6aa8b732 3034 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3035 error_code)) {
ad312c7c
ZX		 3036 if (vcpu->arch.halt_request) {
3037 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3038 return kvm_emulate_halt(vcpu);
3039 }
6aa8b732 3040 return 1;
72d6e5a0 3041 }
6aa8b732 3042
d0bfb940 3043 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3044 switch (ex_no) {
3045 case DB_VECTOR:
3046 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3047 if (!(vcpu->guest_debug &
3048 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3049 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3050 kvm_queue_exception(vcpu, DB_VECTOR);
3051 return 1;
3052 }
3053 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3054 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3055 /* fall through */
3056 case BP_VECTOR:
c573cd22
JK		 3057 /*
3058 * Update instruction length as we may reinject #BP from
3059 * user space while in guest debugging mode. Reading it for
3060 * #DB as well causes no harm, it is not used in that case.
3061 */
3062 vmx->vcpu.arch.event_exit_inst_len =
3063 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3064 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3065 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3066 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3067 break;
3068 default:
d0bfb940
JK		 3069 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3070 kvm_run->ex.exception = ex_no;
3071 kvm_run->ex.error_code = error_code;
42dbaa5a 3072 break;
6aa8b732 3073 }
6aa8b732
AK		 3074 return 0;
3075}
3076
851ba692 3077static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3078{
1165f5fe 3079 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3080 return 1;
3081}
3082
851ba692 3083static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3084{
851ba692 3085 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3086 return 0;
3087}
6aa8b732 3088
851ba692 3089static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3090{
bfdaab09 3091 unsigned long exit_qualification;
34c33d16 3092 int size, in, string;
039576c0 3093 unsigned port;
6aa8b732 3094
bfdaab09 3095 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3096 string = (exit_qualification & 16) != 0;
cf8f70bf 3097 in = (exit_qualification & 8) != 0;
e70669ab 3098
cf8f70bf 3099 ++vcpu->stat.io_exits;
e70669ab 3100
cf8f70bf 3101 if (string || in)
6d77dbfc 3102 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3103
cf8f70bf
GN		 3104 port = exit_qualification >> 16;
3105 size = (exit_qualification & 7) + 1;
e93f36bc 3106 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3107
3108 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3109}
3110
102d8325
IM		 3111static void
3112vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3113{
3114 /*
3115 * Patch in the VMCALL instruction:
3116 */
3117 hypercall[0] = 0x0f;
3118 hypercall[1] = 0x01;
3119 hypercall[2] = 0xc1;
102d8325
IM		 3120}
3121
49a9b07e
AK		 3122static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3123{
3124 if (err)
3125 kvm_inject_gp(vcpu, 0);
3126 else
3127 skip_emulated_instruction(vcpu);
3128}
3129
851ba692 3130static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3131{
229456fc 3132 unsigned long exit_qualification, val;
6aa8b732
AK		 3133 int cr;
3134 int reg;
49a9b07e 3135 int err;
6aa8b732 3136
bfdaab09 3137 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3138 cr = exit_qualification & 15;
3139 reg = (exit_qualification >> 8) & 15;
3140 switch ((exit_qualification >> 4) & 3) {
3141 case 0: /* mov to cr */
229456fc
MT		 3142 val = kvm_register_read(vcpu, reg);
3143 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3144 switch (cr) {
3145 case 0:
49a9b07e
AK		 3146 err = kvm_set_cr0(vcpu, val);
3147 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3148 return 1;
3149 case 3:
2390218b
AK		 3150 err = kvm_set_cr3(vcpu, val);
3151 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3152 return 1;
3153 case 4:
a83b29c6
AK		 3154 err = kvm_set_cr4(vcpu, val);
3155 complete_insn_gp(vcpu, err);
6aa8b732 3156 return 1;
0a5fff19
GN		 3157 case 8: {
3158 u8 cr8_prev = kvm_get_cr8(vcpu);
3159 u8 cr8 = kvm_register_read(vcpu, reg);
3160 kvm_set_cr8(vcpu, cr8);
3161 skip_emulated_instruction(vcpu);
3162 if (irqchip_in_kernel(vcpu->kvm))
3163 return 1;
3164 if (cr8_prev <= cr8)
3165 return 1;
851ba692 3166 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3167 return 0;
3168 }
6aa8b732
AK		 3169 };
3170 break;
25c4c276 3171 case 2: /* clts */
edcafe3c 3172 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3173 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3174 skip_emulated_instruction(vcpu);
6b52d186 3175 vmx_fpu_activate(vcpu);
25c4c276 3176 return 1;
6aa8b732
AK		 3177 case 1: /*mov from cr*/
3178 switch (cr) {
3179 case 3:
5fdbf976 3180 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3181 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3182 skip_emulated_instruction(vcpu);
3183 return 1;
3184 case 8:
229456fc
MT		 3185 val = kvm_get_cr8(vcpu);
3186 kvm_register_write(vcpu, reg, val);
3187 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3188 skip_emulated_instruction(vcpu);
3189 return 1;
3190 }
3191 break;
3192 case 3: /* lmsw */
a1f83a74 3193 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3194 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3195 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3196
3197 skip_emulated_instruction(vcpu);
3198 return 1;
3199 default:
3200 break;
3201 }
851ba692 3202 vcpu->run->exit_reason = 0;
f0242478 3203 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3204 (int)(exit_qualification >> 4) & 3, cr);
3205 return 0;
3206}
3207
851ba692 3208static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3209{
bfdaab09 3210 unsigned long exit_qualification;
6aa8b732
AK		 3211 int dr, reg;
3212
f2483415 3213 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3214 if (!kvm_require_cpl(vcpu, 0))
3215 return 1;
42dbaa5a
JK		 3216 dr = vmcs_readl(GUEST_DR7);
3217 if (dr & DR7_GD) {
3218 /*
3219 * As the vm-exit takes precedence over the debug trap, we
3220 * need to emulate the latter, either for the host or the
3221 * guest debugging itself.
3222 */
3223 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3224 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3225 vcpu->run->debug.arch.dr7 = dr;
3226 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3227 vmcs_readl(GUEST_CS_BASE) +
3228 vmcs_readl(GUEST_RIP);
851ba692
AK		 3229 vcpu->run->debug.arch.exception = DB_VECTOR;
3230 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3231 return 0;
3232 } else {
3233 vcpu->arch.dr7 &= ~DR7_GD;
3234 vcpu->arch.dr6 |= DR6_BD;
3235 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3236 kvm_queue_exception(vcpu, DB_VECTOR);
3237 return 1;
3238 }
3239 }
3240
bfdaab09 3241 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3242 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3243 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3244 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3245 unsigned long val;
3246 if (!kvm_get_dr(vcpu, dr, &val))
3247 kvm_register_write(vcpu, reg, val);
3248 } else
3249 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3250 skip_emulated_instruction(vcpu);
3251 return 1;
3252}
3253
020df079
GN		 3254static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3255{
3256 vmcs_writel(GUEST_DR7, val);
3257}
3258
851ba692 3259static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3260{
06465c5a
AK		 3261 kvm_emulate_cpuid(vcpu);
3262 return 1;
6aa8b732
AK		 3263}
3264
851ba692 3265static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3266{
ad312c7c 3267 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3268 u64 data;
3269
3270 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3271 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3272 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3273 return 1;
3274 }
3275
229456fc 3276 trace_kvm_msr_read(ecx, data);
2714d1d3 3277
6aa8b732 3278 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3279 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3280 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3281 skip_emulated_instruction(vcpu);
3282 return 1;
3283}
3284
851ba692 3285static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3286{
ad312c7c
ZX		 3287 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3288 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3289 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3290
3291 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3292 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3293 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3294 return 1;
3295 }
3296
59200273 3297 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3298 skip_emulated_instruction(vcpu);
3299 return 1;
3300}
3301
851ba692 3302static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3303{
3842d135 3304 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3305 return 1;
3306}
3307
851ba692 3308static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3309{
85f455f7
ED		 3310 u32 cpu_based_vm_exec_control;
3311
3312 /* clear pending irq */
3313 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3314 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3315 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3316
3842d135
AK		 3317 kvm_make_request(KVM_REQ_EVENT, vcpu);
3318
a26bf12a 3319 ++vcpu->stat.irq_window_exits;
2714d1d3 3320
c1150d8c
DL		 3321 /*
3322 * If the user space waits to inject interrupts, exit as soon as
3323 * possible
3324 */
8061823a 3325 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3326 vcpu->run->request_interrupt_window &&
8061823a 3327 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3328 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3329 return 0;
3330 }
6aa8b732
AK		 3331 return 1;
3332}
3333
851ba692 3334static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3335{
3336 skip_emulated_instruction(vcpu);
d3bef15f 3337 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3338}
3339
851ba692 3340static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3341{
510043da 3342 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3343 kvm_emulate_hypercall(vcpu);
3344 return 1;
c21415e8
IM		 3345}
3346
851ba692 3347static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3348{
3349 kvm_queue_exception(vcpu, UD_VECTOR);
3350 return 1;
3351}
3352
851ba692 3353static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3354{
f9c617f6 3355 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3356
3357 kvm_mmu_invlpg(vcpu, exit_qualification);
3358 skip_emulated_instruction(vcpu);
3359 return 1;
3360}
3361
851ba692 3362static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3363{
3364 skip_emulated_instruction(vcpu);
f5f48ee1 3365 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3366 return 1;
3367}
3368
2acf923e
DC		 3369static int handle_xsetbv(struct kvm_vcpu *vcpu)
3370{
3371 u64 new_bv = kvm_read_edx_eax(vcpu);
3372 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3373
3374 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3375 skip_emulated_instruction(vcpu);
3376 return 1;
3377}
3378
851ba692 3379static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3380{
6d77dbfc 3381 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3382}
3383
851ba692 3384static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3385{
60637aac 3386 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3387 unsigned long exit_qualification;
e269fb21
JK		 3388 bool has_error_code = false;
3389 u32 error_code = 0;
37817f29 3390 u16 tss_selector;
64a7ec06
GN		 3391 int reason, type, idt_v;
3392
3393 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3394 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3395
3396 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3397
3398 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3399 if (reason == TASK_SWITCH_GATE && idt_v) {
3400 switch (type) {
3401 case INTR_TYPE_NMI_INTR:
3402 vcpu->arch.nmi_injected = false;
3403 if (cpu_has_virtual_nmis())
3404 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3405 GUEST_INTR_STATE_NMI);
3406 break;
3407 case INTR_TYPE_EXT_INTR:
66fd3f7f 3408 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3409 kvm_clear_interrupt_queue(vcpu);
3410 break;
3411 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3412 if (vmx->idt_vectoring_info &
3413 VECTORING_INFO_DELIVER_CODE_MASK) {
3414 has_error_code = true;
3415 error_code =
3416 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3417 }
3418 /* fall through */
64a7ec06
GN		 3419 case INTR_TYPE_SOFT_EXCEPTION:
3420 kvm_clear_exception_queue(vcpu);
3421 break;
3422 default:
3423 break;
3424 }
60637aac 3425 }
37817f29
IE		 3426 tss_selector = exit_qualification;
3427
64a7ec06
GN		 3428 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3429 type != INTR_TYPE_EXT_INTR &&
3430 type != INTR_TYPE_NMI_INTR))
3431 skip_emulated_instruction(vcpu);
3432
acb54517
GN		 3433 if (kvm_task_switch(vcpu, tss_selector, reason,
3434 has_error_code, error_code) == EMULATE_FAIL) {
3435 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3436 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3437 vcpu->run->internal.ndata = 0;
42dbaa5a 3438 return 0;
acb54517 3439 }
42dbaa5a
JK		 3440
3441 /* clear all local breakpoint enable flags */
3442 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3443
3444 /*
3445 * TODO: What about debug traps on tss switch?
3446 * Are we supposed to inject them and update dr6?
3447 */
3448
3449 return 1;
37817f29
IE		 3450}
3451
851ba692 3452static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3453{
f9c617f6 3454 unsigned long exit_qualification;
1439442c 3455 gpa_t gpa;
1439442c 3456 int gla_validity;
1439442c 3457
f9c617f6 3458 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3459
3460 if (exit_qualification & (1 << 6)) {
3461 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3462 return -EINVAL;
1439442c
SY		 3463 }
3464
3465 gla_validity = (exit_qualification >> 7) & 0x3;
3466 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3467 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3468 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3469 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3470 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3471 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3472 (long unsigned int)exit_qualification);
851ba692
AK		 3473 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3474 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3475 return 0;
1439442c
SY		 3476 }
3477
3478 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3479 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3480 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3481}
3482
68f89400
MT		 3483static u64 ept_rsvd_mask(u64 spte, int level)
3484{
3485 int i;
3486 u64 mask = 0;
3487
3488 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3489 mask |= (1ULL << i);
3490
3491 if (level > 2)
3492 /* bits 7:3 reserved */
3493 mask |= 0xf8;
3494 else if (level == 2) {
3495 if (spte & (1ULL << 7))
3496 /* 2MB ref, bits 20:12 reserved */
3497 mask |= 0x1ff000;
3498 else
3499 /* bits 6:3 reserved */
3500 mask |= 0x78;
3501 }
3502
3503 return mask;
3504}
3505
3506static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3507 int level)
3508{
3509 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3510
3511 /* 010b (write-only) */
3512 WARN_ON((spte & 0x7) == 0x2);
3513
3514 /* 110b (write/execute) */
3515 WARN_ON((spte & 0x7) == 0x6);
3516
3517 /* 100b (execute-only) and value not supported by logical processor */
3518 if (!cpu_has_vmx_ept_execute_only())
3519 WARN_ON((spte & 0x7) == 0x4);
3520
3521 /* not 000b */
3522 if ((spte & 0x7)) {
3523 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3524
3525 if (rsvd_bits != 0) {
3526 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3527 __func__, rsvd_bits);
3528 WARN_ON(1);
3529 }
3530
3531 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3532 u64 ept_mem_type = (spte & 0x38) >> 3;
3533
3534 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3535 ept_mem_type == 7) {
3536 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3537 __func__, ept_mem_type);
3538 WARN_ON(1);
3539 }
3540 }
3541 }
3542}
3543
851ba692 3544static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3545{
3546 u64 sptes[4];
3547 int nr_sptes, i;
3548 gpa_t gpa;
3549
3550 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3551
3552 printk(KERN_ERR "EPT: Misconfiguration.\n");
3553 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3554
3555 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3556
3557 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3558 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3559
851ba692
AK		 3560 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3561 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3562
3563 return 0;
3564}
3565
851ba692 3566static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3567{
3568 u32 cpu_based_vm_exec_control;
3569
3570 /* clear pending NMI */
3571 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3572 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3574 ++vcpu->stat.nmi_window_exits;
3842d135 3575 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3576
3577 return 1;
3578}
3579
80ced186 3580static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3581{
8b3079a5
AK		 3582 struct vcpu_vmx *vmx = to_vmx(vcpu);
3583 enum emulation_result err = EMULATE_DONE;
80ced186 3584 int ret = 1;
49e9d557
AK		 3585 u32 cpu_exec_ctrl;
3586 bool intr_window_requested;
3587
3588 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3589 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3590
3591 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3592 if (intr_window_requested
3593 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3594 return handle_interrupt_window(&vmx->vcpu);
3595
851ba692 3596 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3597
80ced186
MG		 3598 if (err == EMULATE_DO_MMIO) {
3599 ret = 0;
3600 goto out;
3601 }
1d5a4d9b 3602
6d77dbfc
GN		 3603 if (err != EMULATE_DONE)
3604 return 0;
ea953ef0
MG		 3605
3606 if (signal_pending(current))
80ced186 3607 goto out;
ea953ef0
MG		 3608 if (need_resched())
3609 schedule();
3610 }
3611
80ced186
MG		 3612 vmx->emulation_required = 0;
3613out:
3614 return ret;
ea953ef0
MG		 3615}
3616
4b8d54f9
ZE		 3617/*
3618 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3619 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3620 */
9fb41ba8 3621static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3622{
3623 skip_emulated_instruction(vcpu);
3624 kvm_vcpu_on_spin(vcpu);
3625
3626 return 1;
3627}
3628
59708670
SY		 3629static int handle_invalid_op(struct kvm_vcpu *vcpu)
3630{
3631 kvm_queue_exception(vcpu, UD_VECTOR);
3632 return 1;
3633}
3634
6aa8b732
AK		 3635/*
3636 * The exit handlers return 1 if the exit was handled fully and guest execution
3637 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3638 * to be done to userspace and return 0.
3639 */
851ba692 3640static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3641 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3642 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3643 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3644 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3645 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3646 [EXIT_REASON_CR_ACCESS] = handle_cr,
3647 [EXIT_REASON_DR_ACCESS] = handle_dr,
3648 [EXIT_REASON_CPUID] = handle_cpuid,
3649 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3650 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3651 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3652 [EXIT_REASON_HLT] = handle_halt,
a7052897 3653 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3654 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3655 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3656 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3657 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3658 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3659 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3660 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3661 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3662 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3663 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3664 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3665 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3666 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3667 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3668 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3669 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3670 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3671 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3672 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3673 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3674 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3675};
3676
3677static const int kvm_vmx_max_exit_handlers =
50a3485c 3678 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3679
3680/*
3681 * The guest has exited. See if we can fix it or if we need userspace
3682 * assistance.
3683 */
851ba692 3684static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3685{
29bd8a78 3686 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3687 u32 exit_reason = vmx->exit_reason;
1155f76a 3688 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3689
5bfd8b54 3690 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3691
80ced186
MG		 3692 /* If guest state is invalid, start emulating */
3693 if (vmx->emulation_required && emulate_invalid_guest_state)
3694 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3695
1439442c
SY		 3696 /* Access CR3 don't cause VMExit in paging mode, so we need
3697 * to sync with guest real CR3. */
6de4f3ad 3698 if (enable_ept && is_paging(vcpu))
1439442c 3699 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3700
5120702e
MG		 3701 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3702 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3703 vcpu->run->fail_entry.hardware_entry_failure_reason
3704 = exit_reason;
3705 return 0;
3706 }
3707
29bd8a78 3708 if (unlikely(vmx->fail)) {
851ba692
AK		 3709 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3710 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3711 = vmcs_read32(VM_INSTRUCTION_ERROR);
3712 return 0;
3713 }
6aa8b732 3714
d77c26fc 3715 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3716 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3717 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3718 exit_reason != EXIT_REASON_TASK_SWITCH))
3719 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3720 "(0x%x) and exit reason is 0x%x\n",
3721 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3722
3723 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3724 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3725 vmx->soft_vnmi_blocked = 0;
3b86cd99 3726 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3727 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3728 /*
3729 * This CPU don't support us in finding the end of an
3730 * NMI-blocked window if the guest runs with IRQs
3731 * disabled. So we pull the trigger after 1 s of
3732 * futile waiting, but inform the user about this.
3733 */
3734 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3735 "state on VCPU %d after 1 s timeout\n",
3736 __func__, vcpu->vcpu_id);
3737 vmx->soft_vnmi_blocked = 0;
3b86cd99 3738 }
3b86cd99
JK		 3739 }
3740
6aa8b732
AK		 3741 if (exit_reason < kvm_vmx_max_exit_handlers
3742 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3743 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3744 else {
851ba692
AK		 3745 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3746 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3747 }
3748 return 0;
3749}
3750
95ba8273 3751static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3752{
95ba8273 3753 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3754 vmcs_write32(TPR_THRESHOLD, 0);
3755 return;
3756 }
3757
95ba8273 3758 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3759}
3760
51aa01d1 3761static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3762{
51aa01d1 3763 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3764
3765 /* Handle machine checks before interrupts are enabled */
3766 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3767 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3768 && is_machine_check(exit_intr_info)))
3769 kvm_machine_check();
3770
20f65983
GN		 3771 /* We need to handle NMIs before interrupts are enabled */
3772 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3773 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3774 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3775 asm("int $2");
ff9d07a0
ZY		 3776 kvm_after_handle_nmi(&vmx->vcpu);
3777 }
51aa01d1 3778}
20f65983 3779
51aa01d1
AK		 3780static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3781{
3782 u32 exit_intr_info = vmx->exit_intr_info;
3783 bool unblock_nmi;
3784 u8 vector;
3785 bool idtv_info_valid;
3786
3787 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3788
cf393f75
AK		 3789 if (cpu_has_virtual_nmis()) {
3790 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3791 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3792 /*
7b4a25cb 3793 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3794 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3795 * a guest IRET fault.
7b4a25cb
GN		 3796 * SDM 3: 23.2.2 (September 2008)
3797 * Bit 12 is undefined in any of the following cases:
3798 * If the VM exit sets the valid bit in the IDT-vectoring
3799 * information field.
3800 * If the VM exit is due to a double fault.
cf393f75 3801 */
7b4a25cb
GN		 3802 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3803 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3804 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3805 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3806 } else if (unlikely(vmx->soft_vnmi_blocked))
3807 vmx->vnmi_blocked_time +=
3808 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3809}
3810
83422e17
AK		 3811static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3812 u32 idt_vectoring_info,
3813 int instr_len_field,
3814 int error_code_field)
51aa01d1 3815{
51aa01d1
AK		 3816 u8 vector;
3817 int type;
3818 bool idtv_info_valid;
3819
3820 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3821
37b96e98
GN		 3822 vmx->vcpu.arch.nmi_injected = false;
3823 kvm_clear_exception_queue(&vmx->vcpu);
3824 kvm_clear_interrupt_queue(&vmx->vcpu);
3825
3826 if (!idtv_info_valid)
3827 return;
3828
3842d135
AK		 3829 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3830
668f612f
AK		 3831 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3832 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3833
64a7ec06 3834 switch (type) {
37b96e98
GN		 3835 case INTR_TYPE_NMI_INTR:
3836 vmx->vcpu.arch.nmi_injected = true;
668f612f 3837 /*
7b4a25cb 3838 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3839 * Clear bit "block by NMI" before VM entry if a NMI
3840 * delivery faulted.
668f612f 3841 */
37b96e98
GN		 3842 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3843 GUEST_INTR_STATE_NMI);
3844 break;
37b96e98 3845 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 3846 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3847 vmcs_read32(instr_len_field);
66fd3f7f
GN		 3848 /* fall through */
3849 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3850 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 3851 u32 err = vmcs_read32(error_code_field);
37b96e98 3852 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3853 } else
3854 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3855 break;
66fd3f7f
GN		 3856 case INTR_TYPE_SOFT_INTR:
3857 vmx->vcpu.arch.event_exit_inst_len =
83422e17 3858 vmcs_read32(instr_len_field);
66fd3f7f 3859 /* fall through */
37b96e98 3860 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3861 kvm_queue_interrupt(&vmx->vcpu, vector,
3862 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3863 break;
3864 default:
3865 break;
f7d9238f 3866 }
cf393f75
AK		 3867}
3868
83422e17
AK		 3869static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3870{
3871 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3872 VM_EXIT_INSTRUCTION_LEN,
3873 IDT_VECTORING_ERROR_CODE);
3874}
3875
b463a6f7
AK		 3876static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3877{
3878 __vmx_complete_interrupts(to_vmx(vcpu),
3879 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3880 VM_ENTRY_INSTRUCTION_LEN,
3881 VM_ENTRY_EXCEPTION_ERROR_CODE);
3882
3883 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3884}
3885
c801949d
AK		 3886#ifdef CONFIG_X86_64
3887#define R "r"
3888#define Q "q"
3889#else
3890#define R "e"
3891#define Q "l"
3892#endif
3893
851ba692 3894static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3895{
a2fa3e9f 3896 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3897
3b86cd99
JK		 3898 /* Record the guest's net vcpu time for enforced NMI injections. */
3899 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3900 vmx->entry_time = ktime_get();
3901
80ced186
MG		 3902 /* Don't enter VMX if guest state is invalid, let the exit handler
3903 start emulation until we arrive back to a valid state */
3904 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3905 return;
a89a8fb9 3906
5fdbf976
MT		 3907 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3908 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3909 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3910 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3911
787ff736
GN		 3912 /* When single-stepping over STI and MOV SS, we must clear the
3913 * corresponding interruptibility bits in the guest state. Otherwise
3914 * vmentry fails as it then expects bit 14 (BS) in pending debug
3915 * exceptions being set, but that's not correct for the guest debugging
3916 * case. */
3917 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3918 vmx_set_interrupt_shadow(vcpu, 0);
3919
d77c26fc 3920 asm(
6aa8b732 3921 /* Store host registers */
c801949d
AK		 3922 "push %%"R"dx; push %%"R"bp;"
3923 "push %%"R"cx \n\t"
313dbd49
AK		 3924 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3925 "je 1f \n\t"
3926 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3927 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3928 "1: \n\t"
d3edefc0
AK		 3929 /* Reload cr2 if changed */
3930 "mov %c[cr2](%0), %%"R"ax \n\t"
3931 "mov %%cr2, %%"R"dx \n\t"
3932 "cmp %%"R"ax, %%"R"dx \n\t"
3933 "je 2f \n\t"
3934 "mov %%"R"ax, %%cr2 \n\t"
3935 "2: \n\t"
6aa8b732 3936 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3937 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3938 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3939 "mov %c[rax](%0), %%"R"ax \n\t"
3940 "mov %c[rbx](%0), %%"R"bx \n\t"
3941 "mov %c[rdx](%0), %%"R"dx \n\t"
3942 "mov %c[rsi](%0), %%"R"si \n\t"
3943 "mov %c[rdi](%0), %%"R"di \n\t"
3944 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3945#ifdef CONFIG_X86_64
e08aa78a
AK		 3946 "mov %c[r8](%0), %%r8 \n\t"
3947 "mov %c[r9](%0), %%r9 \n\t"
3948 "mov %c[r10](%0), %%r10 \n\t"
3949 "mov %c[r11](%0), %%r11 \n\t"
3950 "mov %c[r12](%0), %%r12 \n\t"
3951 "mov %c[r13](%0), %%r13 \n\t"
3952 "mov %c[r14](%0), %%r14 \n\t"
3953 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3954#endif
c801949d
AK		 3955 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3956
6aa8b732 3957 /* Enter guest mode */
cd2276a7 3958 "jne .Llaunched \n\t"
4ecac3fd 3959 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3960 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3961 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3962 ".Lkvm_vmx_return: "
6aa8b732 3963 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3964 "xchg %0, (%%"R"sp) \n\t"
3965 "mov %%"R"ax, %c[rax](%0) \n\t"
3966 "mov %%"R"bx, %c[rbx](%0) \n\t"
3967 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3968 "mov %%"R"dx, %c[rdx](%0) \n\t"
3969 "mov %%"R"si, %c[rsi](%0) \n\t"
3970 "mov %%"R"di, %c[rdi](%0) \n\t"
3971 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3972#ifdef CONFIG_X86_64
e08aa78a
AK		 3973 "mov %%r8, %c[r8](%0) \n\t"
3974 "mov %%r9, %c[r9](%0) \n\t"
3975 "mov %%r10, %c[r10](%0) \n\t"
3976 "mov %%r11, %c[r11](%0) \n\t"
3977 "mov %%r12, %c[r12](%0) \n\t"
3978 "mov %%r13, %c[r13](%0) \n\t"
3979 "mov %%r14, %c[r14](%0) \n\t"
3980 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3981#endif
c801949d
AK		 3982 "mov %%cr2, %%"R"ax \n\t"
3983 "mov %%"R"ax, %c[cr2](%0) \n\t"
3984
3985 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3986 "setbe %c[fail](%0) \n\t"
3987 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3988 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3989 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3990 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3991 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3992 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3993 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3994 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3995 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3996 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3997 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3998#ifdef CONFIG_X86_64
ad312c7c
ZX		 3999 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4000 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4001 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4002 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4003 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4004 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4005 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4006 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4007#endif
ad312c7c 4008 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4009 : "cc", "memory"
07d6f555 4010 , R"ax", R"bx", R"di", R"si"
c2036300 4011#ifdef CONFIG_X86_64
c2036300
LV		 4012 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4013#endif
4014 );
6aa8b732 4015
6de4f3ad
AK		 4016 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4017 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4018 vcpu->arch.regs_dirty = 0;
4019
1155f76a
AK		 4020 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4021
d77c26fc 4022 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4023 vmx->launched = 1;
1b6269db 4024
51aa01d1
AK		 4025 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4026 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4027
4028 vmx_complete_atomic_exit(vmx);
4029 vmx_recover_nmi_blocking(vmx);
cf393f75 4030 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4031}
4032
c801949d
AK		 4033#undef R
4034#undef Q
4035
6aa8b732
AK		 4036static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4037{
a2fa3e9f
GH		 4038 struct vcpu_vmx *vmx = to_vmx(vcpu);
4039
4040 if (vmx->vmcs) {
543e4243 4041 vcpu_clear(vmx);
a2fa3e9f
GH		 4042 free_vmcs(vmx->vmcs);
4043 vmx->vmcs = NULL;
6aa8b732
AK		 4044 }
4045}
4046
4047static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4048{
fb3f0f51
RR		 4049 struct vcpu_vmx *vmx = to_vmx(vcpu);
4050
cdbecfc3 4051 free_vpid(vmx);
6aa8b732 4052 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4053 kfree(vmx->guest_msrs);
4054 kvm_vcpu_uninit(vcpu);
a4770347 4055 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4056}
4057
4610c9cc
DX		 4058static inline void vmcs_init(struct vmcs *vmcs)
4059{
4060 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4061
4062 if (!vmm_exclusive)
4063 kvm_cpu_vmxon(phys_addr);
4064
4065 vmcs_clear(vmcs);
4066
4067 if (!vmm_exclusive)
4068 kvm_cpu_vmxoff();
4069}
4070
fb3f0f51 4071static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4072{
fb3f0f51 4073 int err;
c16f862d 4074 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4075 int cpu;
6aa8b732 4076
a2fa3e9f 4077 if (!vmx)
fb3f0f51
RR		 4078 return ERR_PTR(-ENOMEM);
4079
2384d2b3
SY		 4080 allocate_vpid(vmx);
4081
fb3f0f51
RR		 4082 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4083 if (err)
4084 goto free_vcpu;
965b58a5 4085
a2fa3e9f 4086 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4087 if (!vmx->guest_msrs) {
4088 err = -ENOMEM;
4089 goto uninit_vcpu;
4090 }
965b58a5 4091
a2fa3e9f
GH		 4092 vmx->vmcs = alloc_vmcs();
4093 if (!vmx->vmcs)
fb3f0f51 4094 goto free_msrs;
a2fa3e9f 4095
4610c9cc 4096 vmcs_init(vmx->vmcs);
a2fa3e9f 4097
15ad7146
AK		 4098 cpu = get_cpu();
4099 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4100 vmx->vcpu.cpu = cpu;
8b9cf98c 4101 err = vmx_vcpu_setup(vmx);
fb3f0f51 4102 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4103 put_cpu();
fb3f0f51
RR		 4104 if (err)
4105 goto free_vmcs;
5e4a0b3c
MT		 4106 if (vm_need_virtualize_apic_accesses(kvm))
4107 if (alloc_apic_access_page(kvm) != 0)
4108 goto free_vmcs;
fb3f0f51 4109
b927a3ce
SY		 4110 if (enable_ept) {
4111 if (!kvm->arch.ept_identity_map_addr)
4112 kvm->arch.ept_identity_map_addr =
4113 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4114 if (alloc_identity_pagetable(kvm) != 0)
4115 goto free_vmcs;
b927a3ce 4116 }
b7ebfb05 4117
fb3f0f51
RR		 4118 return &vmx->vcpu;
4119
4120free_vmcs:
4121 free_vmcs(vmx->vmcs);
4122free_msrs:
fb3f0f51
RR		 4123 kfree(vmx->guest_msrs);
4124uninit_vcpu:
4125 kvm_vcpu_uninit(&vmx->vcpu);
4126free_vcpu:
cdbecfc3 4127 free_vpid(vmx);
a4770347 4128 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4129 return ERR_PTR(err);
6aa8b732
AK		 4130}
4131
002c7f7c
YS		 4132static void __init vmx_check_processor_compat(void *rtn)
4133{
4134 struct vmcs_config vmcs_conf;
4135
4136 *(int *)rtn = 0;
4137 if (setup_vmcs_config(&vmcs_conf) < 0)
4138 *(int *)rtn = -EIO;
4139 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4140 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4141 smp_processor_id());
4142 *(int *)rtn = -EIO;
4143 }
4144}
4145
67253af5
SY		 4146static int get_ept_level(void)
4147{
4148 return VMX_EPT_DEFAULT_GAW + 1;
4149}
4150
4b12f0de 4151static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4152{
4b12f0de
SY		 4153 u64 ret;
4154
522c68c4
SY		 4155 /* For VT-d and EPT combination
4156 * 1. MMIO: always map as UC
4157 * 2. EPT with VT-d:
4158 * a. VT-d without snooping control feature: can't guarantee the
4159 * result, try to trust guest.
4160 * b. VT-d with snooping control feature: snooping control feature of
4161 * VT-d engine can guarantee the cache correctness. Just set it
4162 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4163 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4164 * consistent with host MTRR
4165 */
4b12f0de
SY		 4166 if (is_mmio)
4167 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4168 else if (vcpu->kvm->arch.iommu_domain &&
4169 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4170 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4171 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4172 else
522c68c4 4173 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4174 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4175
4176 return ret;
64d4d521
SY		 4177}
4178
f4c9e87c
AK		 4179#define _ER(x) { EXIT_REASON_##x, #x }
4180
229456fc 4181static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4182 _ER(EXCEPTION_NMI),
4183 _ER(EXTERNAL_INTERRUPT),
4184 _ER(TRIPLE_FAULT),
4185 _ER(PENDING_INTERRUPT),
4186 _ER(NMI_WINDOW),
4187 _ER(TASK_SWITCH),
4188 _ER(CPUID),
4189 _ER(HLT),
4190 _ER(INVLPG),
4191 _ER(RDPMC),
4192 _ER(RDTSC),
4193 _ER(VMCALL),
4194 _ER(VMCLEAR),
4195 _ER(VMLAUNCH),
4196 _ER(VMPTRLD),
4197 _ER(VMPTRST),
4198 _ER(VMREAD),
4199 _ER(VMRESUME),
4200 _ER(VMWRITE),
4201 _ER(VMOFF),
4202 _ER(VMON),
4203 _ER(CR_ACCESS),
4204 _ER(DR_ACCESS),
4205 _ER(IO_INSTRUCTION),
4206 _ER(MSR_READ),
4207 _ER(MSR_WRITE),
4208 _ER(MWAIT_INSTRUCTION),
4209 _ER(MONITOR_INSTRUCTION),
4210 _ER(PAUSE_INSTRUCTION),
4211 _ER(MCE_DURING_VMENTRY),
4212 _ER(TPR_BELOW_THRESHOLD),
4213 _ER(APIC_ACCESS),
4214 _ER(EPT_VIOLATION),
4215 _ER(EPT_MISCONFIG),
4216 _ER(WBINVD),
229456fc
MT		 4217 { -1, NULL }
4218};
4219
f4c9e87c
AK		 4220#undef _ER
4221
17cc3935 4222static int vmx_get_lpage_level(void)
344f414f 4223{
878403b7
SY		 4224 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4225 return PT_DIRECTORY_LEVEL;
4226 else
4227 /* For shadow and EPT supported 1GB page */
4228 return PT_PDPE_LEVEL;
344f414f
JR		 4229}
4230
4e47c7a6
SY		 4231static inline u32 bit(int bitno)
4232{
4233 return 1 << (bitno & 31);
4234}
4235
0e851880
SY		 4236static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4237{
4e47c7a6
SY		 4238 struct kvm_cpuid_entry2 *best;
4239 struct vcpu_vmx *vmx = to_vmx(vcpu);
4240 u32 exec_control;
4241
4242 vmx->rdtscp_enabled = false;
4243 if (vmx_rdtscp_supported()) {
4244 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4245 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4246 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4247 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4248 vmx->rdtscp_enabled = true;
4249 else {
4250 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4251 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4252 exec_control);
4253 }
4254 }
4255 }
0e851880
SY		 4256}
4257
d4330ef2
JR		 4258static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4259{
4260}
4261
cbdd1bea 4262static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4263 .cpu_has_kvm_support = cpu_has_kvm_support,
4264 .disabled_by_bios = vmx_disabled_by_bios,
4265 .hardware_setup = hardware_setup,
4266 .hardware_unsetup = hardware_unsetup,
002c7f7c 4267 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4268 .hardware_enable = hardware_enable,
4269 .hardware_disable = hardware_disable,
04547156 4270 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4271
4272 .vcpu_create = vmx_create_vcpu,
4273 .vcpu_free = vmx_free_vcpu,
04d2cc77 4274 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4275
04d2cc77 4276 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4277 .vcpu_load = vmx_vcpu_load,
4278 .vcpu_put = vmx_vcpu_put,
4279
4280 .set_guest_debug = set_guest_debug,
4281 .get_msr = vmx_get_msr,
4282 .set_msr = vmx_set_msr,
4283 .get_segment_base = vmx_get_segment_base,
4284 .get_segment = vmx_get_segment,
4285 .set_segment = vmx_set_segment,
2e4d2653 4286 .get_cpl = vmx_get_cpl,
6aa8b732 4287 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4288 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4289 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4290 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4291 .set_cr3 = vmx_set_cr3,
4292 .set_cr4 = vmx_set_cr4,
6aa8b732 4293 .set_efer = vmx_set_efer,
6aa8b732
AK		 4294 .get_idt = vmx_get_idt,
4295 .set_idt = vmx_set_idt,
4296 .get_gdt = vmx_get_gdt,
4297 .set_gdt = vmx_set_gdt,
020df079 4298 .set_dr7 = vmx_set_dr7,
5fdbf976 4299 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4300 .get_rflags = vmx_get_rflags,
4301 .set_rflags = vmx_set_rflags,
ebcbab4c 4302 .fpu_activate = vmx_fpu_activate,
02daab21 4303 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4304
4305 .tlb_flush = vmx_flush_tlb,
6aa8b732 4306
6aa8b732 4307 .run = vmx_vcpu_run,
6062d012 4308 .handle_exit = vmx_handle_exit,
6aa8b732 4309 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4310 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4311 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4312 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4313 .set_irq = vmx_inject_irq,
95ba8273 4314 .set_nmi = vmx_inject_nmi,
298101da 4315 .queue_exception = vmx_queue_exception,
b463a6f7 4316 .cancel_injection = vmx_cancel_injection,
78646121 4317 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4318 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4319 .get_nmi_mask = vmx_get_nmi_mask,
4320 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4321 .enable_nmi_window = enable_nmi_window,
4322 .enable_irq_window = enable_irq_window,
4323 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4324
cbc94022 4325 .set_tss_addr = vmx_set_tss_addr,
67253af5 4326 .get_tdp_level = get_ept_level,
4b12f0de 4327 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4328
4329 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4330 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4331
4332 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4333
4334 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4335
4336 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4337
4338 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4339
4340 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4341 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4342
4343 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4344};
4345
4346static int __init vmx_init(void)
4347{
26bb0981
AK		 4348 int r, i;
4349
4350 rdmsrl_safe(MSR_EFER, &host_efer);
4351
4352 for (i = 0; i < NR_VMX_MSR; ++i)
4353 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4354
3e7c73e9 4355 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4356 if (!vmx_io_bitmap_a)
4357 return -ENOMEM;
4358
3e7c73e9 4359 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4360 if (!vmx_io_bitmap_b) {
4361 r = -ENOMEM;
4362 goto out;
4363 }
4364
5897297b
AK		 4365 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4366 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4367 r = -ENOMEM;
4368 goto out1;
4369 }
4370
5897297b
AK		 4371 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4372 if (!vmx_msr_bitmap_longmode) {
4373 r = -ENOMEM;
4374 goto out2;
4375 }
4376
fdef3ad1
HQ		 4377 /*
4378 * Allow direct access to the PC debug port (it is often used for I/O
4379 * delays, but the vmexits simply slow things down).
4380 */
3e7c73e9
AK		 4381 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4382 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4383
3e7c73e9 4384 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4385
5897297b
AK		 4386 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4387 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4388
2384d2b3
SY		 4389 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4390
0ee75bea
AK		 4391 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4392 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4393 if (r)
5897297b 4394 goto out3;
25c5f225 4395
5897297b
AK		 4396 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4397 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4398 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4399 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4400 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4401 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4402
089d034e 4403 if (enable_ept) {
1439442c 4404 bypass_guest_pf = 0;
5fdbcb9d 4405 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4406 VMX_EPT_WRITABLE_MASK);
534e38b4 4407 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4408 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4409 kvm_enable_tdp();
4410 } else
4411 kvm_disable_tdp();
1439442c 4412
c7addb90
AK		 4413 if (bypass_guest_pf)
4414 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4415
fdef3ad1
HQ		 4416 return 0;
4417
5897297b
AK		 4418out3:
4419 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4420out2:
5897297b 4421 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4422out1:
3e7c73e9 4423 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4424out:
3e7c73e9 4425 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4426 return r;
6aa8b732
AK		 4427}
4428
4429static void __exit vmx_exit(void)
4430{
5897297b
AK		 4431 free_page((unsigned long)vmx_msr_bitmap_legacy);
4432 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4433 free_page((unsigned long)vmx_io_bitmap_b);
4434 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4435
cb498ea2 4436 kvm_exit();
6aa8b732
AK		 4437}
4438
4439module_init(vmx_init)
4440module_exit(vmx_exit)
Ubuntu Artful kernel mirror