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KVM: VMX: Define new functions to wrapper direct call of asm code
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
cafd6659 30#include <linux/tboot.h>
5fdbf976 31#include "kvm_cache_regs.h"
35920a35 32#include "x86.h"
e495606d 33
6aa8b732 34#include <asm/io.h>
3b3be0d1 35#include <asm/desc.h>
13673a90 36#include <asm/vmx.h>
6210e37b 37#include <asm/virtext.h>
a0861c02 38#include <asm/mce.h>
6aa8b732 39
229456fc
MT		 40#include "trace.h"
41
4ecac3fd
AK		 42#define __ex(x) __kvm_handle_fault_on_reboot(x)
43
6aa8b732
AK		 44MODULE_AUTHOR("Qumranet");
45MODULE_LICENSE("GPL");
46
4462d21a 47static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 48module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 49
4462d21a 50static int __read_mostly enable_vpid = 1;
736caefe 51module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 52
4462d21a 53static int __read_mostly flexpriority_enabled = 1;
736caefe 54module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 55
4462d21a 56static int __read_mostly enable_ept = 1;
736caefe 57module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 58
3a624e29
NK		 59static int __read_mostly enable_unrestricted_guest = 1;
60module_param_named(unrestricted_guest,
61 enable_unrestricted_guest, bool, S_IRUGO);
62
4462d21a 63static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 64module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 65
cdc0e244
AK		 66#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
67 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
68#define KVM_GUEST_CR0_MASK \
69 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
70#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 71 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 72#define KVM_VM_CR0_ALWAYS_ON \
73 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 74#define KVM_CR4_GUEST_OWNED_BITS \
75 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
76 | X86_CR4_OSXMMEXCPT)
77
cdc0e244
AK		 78#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
79#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80
78ac8b47
AK		 81#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
82
4b8d54f9
ZE		 83/*
84 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
85 * ple_gap: upper bound on the amount of time between two successive
86 * executions of PAUSE in a loop. Also indicate if ple enabled.
87 * According to test, this time is usually small than 41 cycles.
88 * ple_window: upper bound on the amount of time a guest is allowed to execute
89 * in a PAUSE loop. Tests indicate that most spinlocks are held for
90 * less than 2^12 cycles
91 * Time is measured based on a counter that runs at the same rate as the TSC,
92 * refer SDM volume 3b section 21.6.13 & 22.1.3.
93 */
94#define KVM_VMX_DEFAULT_PLE_GAP 41
95#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
96static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
97module_param(ple_gap, int, S_IRUGO);
98
99static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
100module_param(ple_window, int, S_IRUGO);
101
61d2ef2c
AK		 102#define NR_AUTOLOAD_MSRS 1
103
a2fa3e9f
GH		 104struct vmcs {
105 u32 revision_id;
106 u32 abort;
107 char data[0];
108};
109
26bb0981
AK		 110struct shared_msr_entry {
111 unsigned index;
112 u64 data;
d5696725 113 u64 mask;
26bb0981
AK		 114};
115
a2fa3e9f 116struct vcpu_vmx {
fb3f0f51 117 struct kvm_vcpu vcpu;
543e4243 118 struct list_head local_vcpus_link;
313dbd49 119 unsigned long host_rsp;
a2fa3e9f 120 int launched;
29bd8a78 121 u8 fail;
1155f76a 122 u32 idt_vectoring_info;
26bb0981 123 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 124 int nmsrs;
125 int save_nmsrs;
a2fa3e9f 126#ifdef CONFIG_X86_64
44ea2b17
AK		 127 u64 msr_host_kernel_gs_base;
128 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 129#endif
130 struct vmcs *vmcs;
61d2ef2c
AK		 131 struct msr_autoload {
132 unsigned nr;
133 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
134 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
135 } msr_autoload;
a2fa3e9f
GH		 136 struct {
137 int loaded;
138 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 139 int gs_ldt_reload_needed;
140 int fs_reload_needed;
d77c26fc 141 } host_state;
9c8cba37 142 struct {
7ffd92c5 143 int vm86_active;
78ac8b47 144 ulong save_rflags;
7ffd92c5
AK		 145 struct kvm_save_segment {
146 u16 selector;
147 unsigned long base;
148 u32 limit;
149 u32 ar;
150 } tr, es, ds, fs, gs;
9c8cba37
AK		 151 struct {
152 bool pending;
153 u8 vector;
154 unsigned rip;
155 } irq;
156 } rmode;
2384d2b3 157 int vpid;
04fa4d32 158 bool emulation_required;
3b86cd99
JK		 159
160 /* Support for vnmi-less CPUs */
161 int soft_vnmi_blocked;
162 ktime_t entry_time;
163 s64 vnmi_blocked_time;
a0861c02 164 u32 exit_reason;
4e47c7a6
SY		 165
166 bool rdtscp_enabled;
a2fa3e9f
GH		 167};
168
169static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
170{
fb3f0f51 171 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 172}
173
b7ebfb05 174static int init_rmode(struct kvm *kvm);
4e1096d2 175static u64 construct_eptp(unsigned long root_hpa);
75880a01 176
6aa8b732
AK		 177static DEFINE_PER_CPU(struct vmcs *, vmxarea);
178static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 179static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 180
3e7c73e9
AK		 181static unsigned long *vmx_io_bitmap_a;
182static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 183static unsigned long *vmx_msr_bitmap_legacy;
184static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 185
2384d2b3
SY		 186static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
187static DEFINE_SPINLOCK(vmx_vpid_lock);
188
1c3d14fe 189static struct vmcs_config {
6aa8b732
AK		 190 int size;
191 int order;
192 u32 revision_id;
1c3d14fe
YS		 193 u32 pin_based_exec_ctrl;
194 u32 cpu_based_exec_ctrl;
f78e0e2e 195 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 196 u32 vmexit_ctrl;
197 u32 vmentry_ctrl;
198} vmcs_config;
6aa8b732 199
efff9e53 200static struct vmx_capability {
d56f546d
SY		 201 u32 ept;
202 u32 vpid;
203} vmx_capability;
204
6aa8b732
AK		 205#define VMX_SEGMENT_FIELD(seg) \
206 [VCPU_SREG_##seg] = { \
207 .selector = GUEST_##seg##_SELECTOR, \
208 .base = GUEST_##seg##_BASE, \
209 .limit = GUEST_##seg##_LIMIT, \
210 .ar_bytes = GUEST_##seg##_AR_BYTES, \
211 }
212
213static struct kvm_vmx_segment_field {
214 unsigned selector;
215 unsigned base;
216 unsigned limit;
217 unsigned ar_bytes;
218} kvm_vmx_segment_fields[] = {
219 VMX_SEGMENT_FIELD(CS),
220 VMX_SEGMENT_FIELD(DS),
221 VMX_SEGMENT_FIELD(ES),
222 VMX_SEGMENT_FIELD(FS),
223 VMX_SEGMENT_FIELD(GS),
224 VMX_SEGMENT_FIELD(SS),
225 VMX_SEGMENT_FIELD(TR),
226 VMX_SEGMENT_FIELD(LDTR),
227};
228
26bb0981
AK		 229static u64 host_efer;
230
6de4f3ad
AK		 231static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
232
4d56c8a7
AK		 233/*
234 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
235 * away by decrementing the array size.
236 */
6aa8b732 237static const u32 vmx_msr_index[] = {
05b3e0c2 238#ifdef CONFIG_X86_64
44ea2b17 239 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 240#endif
4e47c7a6 241 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 242};
9d8f549d 243#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 244
31299944 245static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 246{
247 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
248 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 249 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 250}
251
31299944 252static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 253{
254 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
255 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 256 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 257}
258
31299944 259static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 260{
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 263 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 264}
265
31299944 266static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 267{
268 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
269 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
270}
271
31299944 272static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 273{
274 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
275 INTR_INFO_VALID_MASK)) ==
276 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
277}
278
31299944 279static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 280{
04547156 281 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 282}
283
31299944 284static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 285{
04547156 286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 287}
288
31299944 289static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 290{
04547156 291 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 292}
293
31299944 294static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 295{
04547156
SY		 296 return vmcs_config.cpu_based_exec_ctrl &
297 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 298}
299
774ead3a 300static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 301{
04547156
SY		 302 return vmcs_config.cpu_based_2nd_exec_ctrl &
303 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
304}
305
306static inline bool cpu_has_vmx_flexpriority(void)
307{
308 return cpu_has_vmx_tpr_shadow() &&
309 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 310}
311
e799794e
MT		 312static inline bool cpu_has_vmx_ept_execute_only(void)
313{
31299944 314 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 315}
316
317static inline bool cpu_has_vmx_eptp_uncacheable(void)
318{
31299944 319 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 320}
321
322static inline bool cpu_has_vmx_eptp_writeback(void)
323{
31299944 324 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 325}
326
327static inline bool cpu_has_vmx_ept_2m_page(void)
328{
31299944 329 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 330}
331
878403b7
SY		 332static inline bool cpu_has_vmx_ept_1g_page(void)
333{
31299944 334 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 335}
336
31299944 337static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 338{
31299944 339 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 340}
341
31299944 342static inline bool cpu_has_vmx_invept_context(void)
d56f546d 343{
31299944 344 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 345}
346
31299944 347static inline bool cpu_has_vmx_invept_global(void)
d56f546d 348{
31299944 349 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 350}
351
31299944 352static inline bool cpu_has_vmx_ept(void)
d56f546d 353{
04547156
SY		 354 return vmcs_config.cpu_based_2nd_exec_ctrl &
355 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 359{
360 return vmcs_config.cpu_based_2nd_exec_ctrl &
361 SECONDARY_EXEC_UNRESTRICTED_GUEST;
362}
363
31299944 364static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 365{
366 return vmcs_config.cpu_based_2nd_exec_ctrl &
367 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
368}
369
31299944 370static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 371{
6d3e435e 372 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 373}
374
31299944 375static inline bool cpu_has_vmx_vpid(void)
2384d2b3 376{
04547156
SY		 377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 379}
380
31299944 381static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 382{
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_RDTSCP;
385}
386
31299944 387static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 388{
389 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
390}
391
04547156
SY		 392static inline bool report_flexpriority(void)
393{
394 return flexpriority_enabled;
395}
396
8b9cf98c 397static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 398{
399 int i;
400
a2fa3e9f 401 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 402 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 403 return i;
404 return -1;
405}
406
2384d2b3
SY		 407static inline void __invvpid(int ext, u16 vpid, gva_t gva)
408{
409 struct {
410 u64 vpid : 16;
411 u64 rsvd : 48;
412 u64 gva;
413 } operand = { vpid, 0, gva };
414
4ecac3fd 415 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 416 /* CF==1 or ZF==1 --> rc = -1 */
417 "; ja 1f ; ud2 ; 1:"
418 : : "a"(&operand), "c"(ext) : "cc", "memory");
419}
420
1439442c
SY		 421static inline void __invept(int ext, u64 eptp, gpa_t gpa)
422{
423 struct {
424 u64 eptp, gpa;
425 } operand = {eptp, gpa};
426
4ecac3fd 427 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 428 /* CF==1 or ZF==1 --> rc = -1 */
429 "; ja 1f ; ud2 ; 1:\n"
430 : : "a" (&operand), "c" (ext) : "cc", "memory");
431}
432
26bb0981 433static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 434{
435 int i;
436
8b9cf98c 437 i = __find_msr_index(vmx, msr);
a75beee6 438 if (i >= 0)
a2fa3e9f 439 return &vmx->guest_msrs[i];
8b6d44c7 440 return NULL;
7725f0ba
AK		 441}
442
6aa8b732
AK		 443static void vmcs_clear(struct vmcs *vmcs)
444{
445 u64 phys_addr = __pa(vmcs);
446 u8 error;
447
4ecac3fd 448 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 449 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
450 : "cc", "memory");
451 if (error)
452 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
453 vmcs, phys_addr);
454}
455
7725b894
DX		 456static void vmcs_load(struct vmcs *vmcs)
457{
458 u64 phys_addr = __pa(vmcs);
459 u8 error;
460
461 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
462 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
463 : "cc", "memory");
464 if (error)
465 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
466 vmcs, phys_addr);
467}
468
6aa8b732
AK		 469static void __vcpu_clear(void *arg)
470{
8b9cf98c 471 struct vcpu_vmx *vmx = arg;
d3b2c338 472 int cpu = raw_smp_processor_id();
6aa8b732 473
8b9cf98c 474 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 475 vmcs_clear(vmx->vmcs);
476 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 477 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 478 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 479 list_del(&vmx->local_vcpus_link);
480 vmx->vcpu.cpu = -1;
481 vmx->launched = 0;
6aa8b732
AK		 482}
483
8b9cf98c 484static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 485{
eae5ecb5
AK		 486 if (vmx->vcpu.cpu == -1)
487 return;
8691e5a8 488 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 489}
490
2384d2b3
SY		 491static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
492{
493 if (vmx->vpid == 0)
494 return;
495
496 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
497}
498
1439442c
SY		 499static inline void ept_sync_global(void)
500{
501 if (cpu_has_vmx_invept_global())
502 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
503}
504
505static inline void ept_sync_context(u64 eptp)
506{
089d034e 507 if (enable_ept) {
1439442c
SY		 508 if (cpu_has_vmx_invept_context())
509 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
510 else
511 ept_sync_global();
512 }
513}
514
515static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
516{
089d034e 517 if (enable_ept) {
1439442c
SY		 518 if (cpu_has_vmx_invept_individual_addr())
519 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
520 eptp, gpa);
521 else
522 ept_sync_context(eptp);
523 }
524}
525
6aa8b732
AK		 526static unsigned long vmcs_readl(unsigned long field)
527{
528 unsigned long value;
529
4ecac3fd 530 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 531 : "=a"(value) : "d"(field) : "cc");
532 return value;
533}
534
535static u16 vmcs_read16(unsigned long field)
536{
537 return vmcs_readl(field);
538}
539
540static u32 vmcs_read32(unsigned long field)
541{
542 return vmcs_readl(field);
543}
544
545static u64 vmcs_read64(unsigned long field)
546{
05b3e0c2 547#ifdef CONFIG_X86_64
6aa8b732
AK		 548 return vmcs_readl(field);
549#else
550 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
551#endif
552}
553
e52de1b8
AK		 554static noinline void vmwrite_error(unsigned long field, unsigned long value)
555{
556 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
557 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
558 dump_stack();
559}
560
6aa8b732
AK		 561static void vmcs_writel(unsigned long field, unsigned long value)
562{
563 u8 error;
564
4ecac3fd 565 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 566 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 567 if (unlikely(error))
568 vmwrite_error(field, value);
6aa8b732
AK		 569}
570
571static void vmcs_write16(unsigned long field, u16 value)
572{
573 vmcs_writel(field, value);
574}
575
576static void vmcs_write32(unsigned long field, u32 value)
577{
578 vmcs_writel(field, value);
579}
580
581static void vmcs_write64(unsigned long field, u64 value)
582{
6aa8b732 583 vmcs_writel(field, value);
7682f2d0 584#ifndef CONFIG_X86_64
6aa8b732
AK		 585 asm volatile ("");
586 vmcs_writel(field+1, value >> 32);
587#endif
588}
589
2ab455cc
AL		 590static void vmcs_clear_bits(unsigned long field, u32 mask)
591{
592 vmcs_writel(field, vmcs_readl(field) & ~mask);
593}
594
595static void vmcs_set_bits(unsigned long field, u32 mask)
596{
597 vmcs_writel(field, vmcs_readl(field) | mask);
598}
599
abd3f2d6
AK		 600static void update_exception_bitmap(struct kvm_vcpu *vcpu)
601{
602 u32 eb;
603
fd7373cc
JK		 604 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
605 (1u << NM_VECTOR) | (1u << DB_VECTOR);
606 if ((vcpu->guest_debug &
607 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
608 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
609 eb |= 1u << BP_VECTOR;
7ffd92c5 610 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 611 eb = ~0;
089d034e 612 if (enable_ept)
1439442c 613 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 614 if (vcpu->fpu_active)
615 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 616 vmcs_write32(EXCEPTION_BITMAP, eb);
617}
618
61d2ef2c
AK		 619static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
620{
621 unsigned i;
622 struct msr_autoload *m = &vmx->msr_autoload;
623
624 for (i = 0; i < m->nr; ++i)
625 if (m->guest[i].index == msr)
626 break;
627
628 if (i == m->nr)
629 return;
630 --m->nr;
631 m->guest[i] = m->guest[m->nr];
632 m->host[i] = m->host[m->nr];
633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
635}
636
637static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
638 u64 guest_val, u64 host_val)
639{
640 unsigned i;
641 struct msr_autoload *m = &vmx->msr_autoload;
642
643 for (i = 0; i < m->nr; ++i)
644 if (m->guest[i].index == msr)
645 break;
646
647 if (i == m->nr) {
648 ++m->nr;
649 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
650 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
651 }
652
653 m->guest[i].index = msr;
654 m->guest[i].value = guest_val;
655 m->host[i].index = msr;
656 m->host[i].value = host_val;
657}
658
33ed6329
AK		 659static void reload_tss(void)
660{
33ed6329
AK		 661 /*
662 * VT restores TR but not its size. Useless.
663 */
89a27f4d 664 struct desc_ptr gdt;
a5f61300 665 struct desc_struct *descs;
33ed6329 666
d6ab1ed4 667 native_store_gdt(&gdt);
89a27f4d 668 descs = (void *)gdt.address;
33ed6329
AK		 669 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
670 load_TR_desc();
33ed6329
AK		 671}
672
92c0d900 673static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 674{
3a34a881 675 u64 guest_efer;
51c6cf66
AK		 676 u64 ignore_bits;
677
f6801dff 678 guest_efer = vmx->vcpu.arch.efer;
3a34a881 679
51c6cf66
AK		 680 /*
681 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
682 * outside long mode
683 */
684 ignore_bits = EFER_NX | EFER_SCE;
685#ifdef CONFIG_X86_64
686 ignore_bits |= EFER_LMA | EFER_LME;
687 /* SCE is meaningful only in long mode on Intel */
688 if (guest_efer & EFER_LMA)
689 ignore_bits &= ~(u64)EFER_SCE;
690#endif
51c6cf66
AK		 691 guest_efer &= ~ignore_bits;
692 guest_efer |= host_efer & ignore_bits;
26bb0981 693 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 694 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 695
696 clear_atomic_switch_msr(vmx, MSR_EFER);
697 /* On ept, can't emulate nx, and must switch nx atomically */
698 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
699 guest_efer = vmx->vcpu.arch.efer;
700 if (!(guest_efer & EFER_LMA))
701 guest_efer &= ~EFER_LME;
702 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
703 return false;
704 }
705
26bb0981 706 return true;
51c6cf66
AK		 707}
708
2d49ec72
GN		 709static unsigned long segment_base(u16 selector)
710{
711 struct desc_ptr gdt;
712 struct desc_struct *d;
713 unsigned long table_base;
714 unsigned long v;
715
716 if (!(selector & ~3))
717 return 0;
718
719 native_store_gdt(&gdt);
720 table_base = gdt.address;
721
722 if (selector & 4) { /* from ldt */
723 u16 ldt_selector = kvm_read_ldt();
724
725 if (!(ldt_selector & ~3))
726 return 0;
727
728 table_base = segment_base(ldt_selector);
729 }
730 d = (struct desc_struct *)(table_base + (selector & ~7));
731 v = get_desc_base(d);
732#ifdef CONFIG_X86_64
733 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
734 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
735#endif
736 return v;
737}
738
739static inline unsigned long kvm_read_tr_base(void)
740{
741 u16 tr;
742 asm("str %0" : "=g"(tr));
743 return segment_base(tr);
744}
745
04d2cc77 746static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 747{
04d2cc77 748 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 749 int i;
04d2cc77 750
a2fa3e9f 751 if (vmx->host_state.loaded)
33ed6329
AK		 752 return;
753
a2fa3e9f 754 vmx->host_state.loaded = 1;
33ed6329
AK		 755 /*
756 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
757 * allow segment selectors with cpl > 0 or ti == 1.
758 */
d6e88aec 759 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 760 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 761 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 762 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 763 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 764 vmx->host_state.fs_reload_needed = 0;
765 } else {
33ed6329 766 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 767 vmx->host_state.fs_reload_needed = 1;
33ed6329 768 }
d6e88aec 769 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 770 if (!(vmx->host_state.gs_sel & 7))
771 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 772 else {
773 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 774 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 775 }
776
777#ifdef CONFIG_X86_64
778 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
779 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
780#else
a2fa3e9f
GH		 781 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
782 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 783#endif
707c0874
AK		 784
785#ifdef CONFIG_X86_64
44ea2b17
AK		 786 if (is_long_mode(&vmx->vcpu)) {
787 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
788 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
789 }
707c0874 790#endif
26bb0981
AK		 791 for (i = 0; i < vmx->save_nmsrs; ++i)
792 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 793 vmx->guest_msrs[i].data,
794 vmx->guest_msrs[i].mask);
33ed6329
AK		 795}
796
a9b21b62 797static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 798{
15ad7146 799 unsigned long flags;
33ed6329 800
a2fa3e9f 801 if (!vmx->host_state.loaded)
33ed6329
AK		 802 return;
803
e1beb1d3 804 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 805 vmx->host_state.loaded = 0;
152d3f2f 806 if (vmx->host_state.fs_reload_needed)
d6e88aec 807 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 808 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 809 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 810 /*
811 * If we have to reload gs, we must take care to
812 * preserve our gs base.
813 */
15ad7146 814 local_irq_save(flags);
d6e88aec 815 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 816#ifdef CONFIG_X86_64
817 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
818#endif
15ad7146 819 local_irq_restore(flags);
33ed6329 820 }
152d3f2f 821 reload_tss();
44ea2b17
AK		 822#ifdef CONFIG_X86_64
823 if (is_long_mode(&vmx->vcpu)) {
824 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
825 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
826 }
827#endif
1c11e713
AK		 828 if (current_thread_info()->status & TS_USEDFPU)
829 clts();
33ed6329
AK		 830}
831
a9b21b62
AK		 832static void vmx_load_host_state(struct vcpu_vmx *vmx)
833{
834 preempt_disable();
835 __vmx_load_host_state(vmx);
836 preempt_enable();
837}
838
6aa8b732
AK		 839/*
840 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
841 * vcpu mutex is already taken.
842 */
15ad7146 843static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 844{
a2fa3e9f 845 struct vcpu_vmx *vmx = to_vmx(vcpu);
019960ae 846 u64 tsc_this, delta, new_offset;
6aa8b732 847
a3d7f85f 848 if (vcpu->cpu != cpu) {
8b9cf98c 849 vcpu_clear(vmx);
2f599714 850 kvm_migrate_timers(vcpu);
eb5109e3 851 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 852 local_irq_disable();
853 list_add(&vmx->local_vcpus_link,
854 &per_cpu(vcpus_on_cpu, cpu));
855 local_irq_enable();
a3d7f85f 856 }
6aa8b732 857
a2fa3e9f 858 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 859 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 860 vmcs_load(vmx->vmcs);
6aa8b732
AK		 861 }
862
863 if (vcpu->cpu != cpu) {
89a27f4d 864 struct desc_ptr dt;
6aa8b732
AK		 865 unsigned long sysenter_esp;
866
867 vcpu->cpu = cpu;
868 /*
869 * Linux uses per-cpu TSS and GDT, so set these when switching
870 * processors.
871 */
d6e88aec 872 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 873 native_store_gdt(&dt);
89a27f4d 874 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 875
876 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
877 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 878
879 /*
880 * Make sure the time stamp counter is monotonous.
881 */
882 rdtscll(tsc_this);
019960ae
AK		 883 if (tsc_this < vcpu->arch.host_tsc) {
884 delta = vcpu->arch.host_tsc - tsc_this;
885 new_offset = vmcs_read64(TSC_OFFSET) + delta;
886 vmcs_write64(TSC_OFFSET, new_offset);
887 }
6aa8b732 888 }
6aa8b732
AK		 889}
890
891static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
892{
a9b21b62 893 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 894}
895
5fd86fcf
AK		 896static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
897{
81231c69
AK		 898 ulong cr0;
899
5fd86fcf
AK		 900 if (vcpu->fpu_active)
901 return;
902 vcpu->fpu_active = 1;
81231c69
AK		 903 cr0 = vmcs_readl(GUEST_CR0);
904 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
905 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
906 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 907 update_exception_bitmap(vcpu);
edcafe3c
AK		 908 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
909 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 910}
911
edcafe3c
AK		 912static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
913
5fd86fcf
AK		 914static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
915{
edcafe3c 916 vmx_decache_cr0_guest_bits(vcpu);
81231c69 917 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 918 update_exception_bitmap(vcpu);
edcafe3c
AK		 919 vcpu->arch.cr0_guest_owned_bits = 0;
920 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
921 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 922}
923
6aa8b732
AK		 924static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
925{
78ac8b47 926 unsigned long rflags, save_rflags;
345dcaa8
AK		 927
928 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 929 if (to_vmx(vcpu)->rmode.vm86_active) {
930 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
931 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
932 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
933 }
345dcaa8 934 return rflags;
6aa8b732
AK		 935}
936
937static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
938{
78ac8b47
AK		 939 if (to_vmx(vcpu)->rmode.vm86_active) {
940 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 941 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 942 }
6aa8b732
AK		 943 vmcs_writel(GUEST_RFLAGS, rflags);
944}
945
2809f5d2
GC		 946static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
947{
948 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
949 int ret = 0;
950
951 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 952 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 953 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 954 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 955
956 return ret & mask;
957}
958
959static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
960{
961 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
962 u32 interruptibility = interruptibility_old;
963
964 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
965
48005f64 966 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 967 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 968 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 969 interruptibility |= GUEST_INTR_STATE_STI;
970
971 if ((interruptibility != interruptibility_old))
972 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
973}
974
6aa8b732
AK		 975static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
976{
977 unsigned long rip;
6aa8b732 978
5fdbf976 979 rip = kvm_rip_read(vcpu);
6aa8b732 980 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 981 kvm_rip_write(vcpu, rip);
6aa8b732 982
2809f5d2
GC		 983 /* skipping an emulated instruction also counts */
984 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 985}
986
298101da 987static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 988 bool has_error_code, u32 error_code,
989 bool reinject)
298101da 990{
77ab6db0 991 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 992 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 993
8ab2d2e2 994 if (has_error_code) {
77ab6db0 995 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 996 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
997 }
77ab6db0 998
7ffd92c5 999 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1000 vmx->rmode.irq.pending = true;
1001 vmx->rmode.irq.vector = nr;
1002 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1003 if (kvm_exception_is_soft(nr))
1004 vmx->rmode.irq.rip +=
1005 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1006 intr_info |= INTR_TYPE_SOFT_INTR;
1007 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1008 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1009 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1010 return;
1011 }
1012
66fd3f7f
GN		 1013 if (kvm_exception_is_soft(nr)) {
1014 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1015 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1016 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1017 } else
1018 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1019
1020 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1021}
1022
4e47c7a6
SY		 1023static bool vmx_rdtscp_supported(void)
1024{
1025 return cpu_has_vmx_rdtscp();
1026}
1027
a75beee6
ED		 1028/*
1029 * Swap MSR entry in host/guest MSR entry array.
1030 */
8b9cf98c 1031static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1032{
26bb0981 1033 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1034
1035 tmp = vmx->guest_msrs[to];
1036 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1037 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1038}
1039
e38aea3e
AK		 1040/*
1041 * Set up the vmcs to automatically save and restore system
1042 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1043 * mode, as fiddling with msrs is very expensive.
1044 */
8b9cf98c 1045static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1046{
26bb0981 1047 int save_nmsrs, index;
5897297b 1048 unsigned long *msr_bitmap;
e38aea3e 1049
33f9c505 1050 vmx_load_host_state(vmx);
a75beee6
ED		 1051 save_nmsrs = 0;
1052#ifdef CONFIG_X86_64
8b9cf98c 1053 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1054 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1055 if (index >= 0)
8b9cf98c
RR		 1056 move_msr_up(vmx, index, save_nmsrs++);
1057 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1058 if (index >= 0)
8b9cf98c
RR		 1059 move_msr_up(vmx, index, save_nmsrs++);
1060 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1061 if (index >= 0)
8b9cf98c 1062 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1063 index = __find_msr_index(vmx, MSR_TSC_AUX);
1064 if (index >= 0 && vmx->rdtscp_enabled)
1065 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1066 /*
1067 * MSR_K6_STAR is only needed on long mode guests, and only
1068 * if efer.sce is enabled.
1069 */
8b9cf98c 1070 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1071 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1072 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1073 }
1074#endif
92c0d900
AK		 1075 index = __find_msr_index(vmx, MSR_EFER);
1076 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1077 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1078
26bb0981 1079 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1080
1081 if (cpu_has_vmx_msr_bitmap()) {
1082 if (is_long_mode(&vmx->vcpu))
1083 msr_bitmap = vmx_msr_bitmap_longmode;
1084 else
1085 msr_bitmap = vmx_msr_bitmap_legacy;
1086
1087 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1088 }
e38aea3e
AK		 1089}
1090
6aa8b732
AK		 1091/*
1092 * reads and returns guest's timestamp counter "register"
1093 * guest_tsc = host_tsc + tsc_offset -- 21.3
1094 */
1095static u64 guest_read_tsc(void)
1096{
1097 u64 host_tsc, tsc_offset;
1098
1099 rdtscll(host_tsc);
1100 tsc_offset = vmcs_read64(TSC_OFFSET);
1101 return host_tsc + tsc_offset;
1102}
1103
1104/*
1105 * writes 'guest_tsc' into guest's timestamp counter "register"
1106 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1107 */
53f658b3 1108static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1109{
6aa8b732
AK		 1110 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1111}
1112
6aa8b732
AK		 1113/*
1114 * Reads an msr value (of 'msr_index') into 'pdata'.
1115 * Returns 0 on success, non-0 otherwise.
1116 * Assumes vcpu_load() was already called.
1117 */
1118static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1119{
1120 u64 data;
26bb0981 1121 struct shared_msr_entry *msr;
6aa8b732
AK		 1122
1123 if (!pdata) {
1124 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1125 return -EINVAL;
1126 }
1127
1128 switch (msr_index) {
05b3e0c2 1129#ifdef CONFIG_X86_64
6aa8b732
AK		 1130 case MSR_FS_BASE:
1131 data = vmcs_readl(GUEST_FS_BASE);
1132 break;
1133 case MSR_GS_BASE:
1134 data = vmcs_readl(GUEST_GS_BASE);
1135 break;
44ea2b17
AK		 1136 case MSR_KERNEL_GS_BASE:
1137 vmx_load_host_state(to_vmx(vcpu));
1138 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1139 break;
26bb0981 1140#endif
6aa8b732 1141 case MSR_EFER:
3bab1f5d 1142 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1143 case MSR_IA32_TSC:
6aa8b732
AK		 1144 data = guest_read_tsc();
1145 break;
1146 case MSR_IA32_SYSENTER_CS:
1147 data = vmcs_read32(GUEST_SYSENTER_CS);
1148 break;
1149 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1150 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1151 break;
1152 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1153 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1154 break;
4e47c7a6
SY		 1155 case MSR_TSC_AUX:
1156 if (!to_vmx(vcpu)->rdtscp_enabled)
1157 return 1;
1158 /* Otherwise falls through */
6aa8b732 1159 default:
26bb0981 1160 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1161 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1162 if (msr) {
542423b0 1163 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1164 data = msr->data;
1165 break;
6aa8b732 1166 }
3bab1f5d 1167 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1168 }
1169
1170 *pdata = data;
1171 return 0;
1172}
1173
1174/*
1175 * Writes msr value into into the appropriate "register".
1176 * Returns 0 on success, non-0 otherwise.
1177 * Assumes vcpu_load() was already called.
1178 */
1179static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1180{
a2fa3e9f 1181 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1182 struct shared_msr_entry *msr;
53f658b3 1183 u64 host_tsc;
2cc51560
ED		 1184 int ret = 0;
1185
6aa8b732 1186 switch (msr_index) {
3bab1f5d 1187 case MSR_EFER:
a9b21b62 1188 vmx_load_host_state(vmx);
2cc51560 1189 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1190 break;
16175a79 1191#ifdef CONFIG_X86_64
6aa8b732
AK		 1192 case MSR_FS_BASE:
1193 vmcs_writel(GUEST_FS_BASE, data);
1194 break;
1195 case MSR_GS_BASE:
1196 vmcs_writel(GUEST_GS_BASE, data);
1197 break;
44ea2b17
AK		 1198 case MSR_KERNEL_GS_BASE:
1199 vmx_load_host_state(vmx);
1200 vmx->msr_guest_kernel_gs_base = data;
1201 break;
6aa8b732
AK		 1202#endif
1203 case MSR_IA32_SYSENTER_CS:
1204 vmcs_write32(GUEST_SYSENTER_CS, data);
1205 break;
1206 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1207 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1208 break;
1209 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1210 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1211 break;
af24a4e4 1212 case MSR_IA32_TSC:
53f658b3
MT		 1213 rdtscll(host_tsc);
1214 guest_write_tsc(data, host_tsc);
6aa8b732 1215 break;
468d472f
SY		 1216 case MSR_IA32_CR_PAT:
1217 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1218 vmcs_write64(GUEST_IA32_PAT, data);
1219 vcpu->arch.pat = data;
1220 break;
1221 }
4e47c7a6
SY		 1222 ret = kvm_set_msr_common(vcpu, msr_index, data);
1223 break;
1224 case MSR_TSC_AUX:
1225 if (!vmx->rdtscp_enabled)
1226 return 1;
1227 /* Check reserved bit, higher 32 bits should be zero */
1228 if ((data >> 32) != 0)
1229 return 1;
1230 /* Otherwise falls through */
6aa8b732 1231 default:
8b9cf98c 1232 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1233 if (msr) {
542423b0 1234 vmx_load_host_state(vmx);
3bab1f5d
AK		 1235 msr->data = data;
1236 break;
6aa8b732 1237 }
2cc51560 1238 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1239 }
1240
2cc51560 1241 return ret;
6aa8b732
AK		 1242}
1243
5fdbf976 1244static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1245{
5fdbf976
MT		 1246 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1247 switch (reg) {
1248 case VCPU_REGS_RSP:
1249 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1250 break;
1251 case VCPU_REGS_RIP:
1252 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1253 break;
6de4f3ad
AK		 1254 case VCPU_EXREG_PDPTR:
1255 if (enable_ept)
1256 ept_save_pdptrs(vcpu);
1257 break;
5fdbf976
MT		 1258 default:
1259 break;
1260 }
6aa8b732
AK		 1261}
1262
355be0b9 1263static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1264{
ae675ef0
JK		 1265 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1266 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1267 else
1268 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1269
abd3f2d6 1270 update_exception_bitmap(vcpu);
6aa8b732
AK		 1271}
1272
1273static __init int cpu_has_kvm_support(void)
1274{
6210e37b 1275 return cpu_has_vmx();
6aa8b732
AK		 1276}
1277
1278static __init int vmx_disabled_by_bios(void)
1279{
1280 u64 msr;
1281
1282 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1283 if (msr & FEATURE_CONTROL_LOCKED) {
1284 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1285 && tboot_enabled())
1286 return 1;
1287 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1288 && !tboot_enabled())
1289 return 1;
1290 }
1291
1292 return 0;
62b3ffb8 1293 /* locked but not enabled */
6aa8b732
AK		 1294}
1295
7725b894
DX		 1296static void kvm_cpu_vmxon(u64 addr)
1297{
1298 asm volatile (ASM_VMX_VMXON_RAX
1299 : : "a"(&addr), "m"(addr)
1300 : "memory", "cc");
1301}
1302
10474ae8 1303static int hardware_enable(void *garbage)
6aa8b732
AK		 1304{
1305 int cpu = raw_smp_processor_id();
1306 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1307 u64 old, test_bits;
6aa8b732 1308
10474ae8
AG		 1309 if (read_cr4() & X86_CR4_VMXE)
1310 return -EBUSY;
1311
543e4243 1312 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1313 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1314
1315 test_bits = FEATURE_CONTROL_LOCKED;
1316 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1317 if (tboot_enabled())
1318 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1319
1320 if ((old & test_bits) != test_bits) {
6aa8b732 1321 /* enable and lock */
cafd6659
SW		 1322 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1323 }
66aee91a 1324 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
7725b894 1325 kvm_cpu_vmxon(phys_addr);
10474ae8
AG		 1326
1327 ept_sync_global();
1328
1329 return 0;
6aa8b732
AK		 1330}
1331
543e4243
AK		 1332static void vmclear_local_vcpus(void)
1333{
1334 int cpu = raw_smp_processor_id();
1335 struct vcpu_vmx *vmx, *n;
1336
1337 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1338 local_vcpus_link)
1339 __vcpu_clear(vmx);
1340}
1341
710ff4a8
EH		 1342
1343/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1344 * tricks.
1345 */
1346static void kvm_cpu_vmxoff(void)
6aa8b732 1347{
4ecac3fd 1348 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1349}
1350
710ff4a8
EH		 1351static void hardware_disable(void *garbage)
1352{
1353 vmclear_local_vcpus();
1354 kvm_cpu_vmxoff();
7725b894 1355 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1356}
1357
1c3d14fe 1358static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1359 u32 msr, u32 *result)
1c3d14fe
YS		 1360{
1361 u32 vmx_msr_low, vmx_msr_high;
1362 u32 ctl = ctl_min | ctl_opt;
1363
1364 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1365
1366 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1367 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1368
1369 /* Ensure minimum (required) set of control bits are supported. */
1370 if (ctl_min & ~ctl)
002c7f7c 1371 return -EIO;
1c3d14fe
YS		 1372
1373 *result = ctl;
1374 return 0;
1375}
1376
002c7f7c 1377static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1378{
1379 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1380 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1381 u32 _pin_based_exec_control = 0;
1382 u32 _cpu_based_exec_control = 0;
f78e0e2e 1383 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1384 u32 _vmexit_control = 0;
1385 u32 _vmentry_control = 0;
1386
1387 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1388 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1389 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1390 &_pin_based_exec_control) < 0)
002c7f7c 1391 return -EIO;
1c3d14fe
YS		 1392
1393 min = CPU_BASED_HLT_EXITING |
1394#ifdef CONFIG_X86_64
1395 CPU_BASED_CR8_LOAD_EXITING |
1396 CPU_BASED_CR8_STORE_EXITING |
1397#endif
d56f546d
SY		 1398 CPU_BASED_CR3_LOAD_EXITING |
1399 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1400 CPU_BASED_USE_IO_BITMAPS |
1401 CPU_BASED_MOV_DR_EXITING |
a7052897 1402 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1403 CPU_BASED_MWAIT_EXITING |
1404 CPU_BASED_MONITOR_EXITING |
a7052897 1405 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1406 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1407 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1408 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1409 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1410 &_cpu_based_exec_control) < 0)
002c7f7c 1411 return -EIO;
6e5d865c
YS		 1412#ifdef CONFIG_X86_64
1413 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1414 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1415 ~CPU_BASED_CR8_STORE_EXITING;
1416#endif
f78e0e2e 1417 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1418 min2 = 0;
1419 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1420 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1421 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1422 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1423 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1424 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1425 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1426 if (adjust_vmx_controls(min2, opt2,
1427 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1428 &_cpu_based_2nd_exec_control) < 0)
1429 return -EIO;
1430 }
1431#ifndef CONFIG_X86_64
1432 if (!(_cpu_based_2nd_exec_control &
1433 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1434 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1435#endif
d56f546d 1436 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1437 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1438 enabled */
5fff7d27
GN		 1439 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1440 CPU_BASED_CR3_STORE_EXITING |
1441 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1442 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1443 vmx_capability.ept, vmx_capability.vpid);
1444 }
1c3d14fe
YS		 1445
1446 min = 0;
1447#ifdef CONFIG_X86_64
1448 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1449#endif
468d472f 1450 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1451 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1452 &_vmexit_control) < 0)
002c7f7c 1453 return -EIO;
1c3d14fe 1454
468d472f
SY		 1455 min = 0;
1456 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1458 &_vmentry_control) < 0)
002c7f7c 1459 return -EIO;
6aa8b732 1460
c68876fd 1461 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1462
1463 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1464 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1465 return -EIO;
1c3d14fe
YS		 1466
1467#ifdef CONFIG_X86_64
1468 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1469 if (vmx_msr_high & (1u<<16))
002c7f7c 1470 return -EIO;
1c3d14fe
YS		 1471#endif
1472
1473 /* Require Write-Back (WB) memory type for VMCS accesses. */
1474 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1475 return -EIO;
1c3d14fe 1476
002c7f7c
YS		 1477 vmcs_conf->size = vmx_msr_high & 0x1fff;
1478 vmcs_conf->order = get_order(vmcs_config.size);
1479 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1480
002c7f7c
YS		 1481 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1482 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1483 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1484 vmcs_conf->vmexit_ctrl = _vmexit_control;
1485 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1486
1487 return 0;
c68876fd 1488}
6aa8b732
AK		 1489
1490static struct vmcs *alloc_vmcs_cpu(int cpu)
1491{
1492 int node = cpu_to_node(cpu);
1493 struct page *pages;
1494 struct vmcs *vmcs;
1495
6484eb3e 1496 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1497 if (!pages)
1498 return NULL;
1499 vmcs = page_address(pages);
1c3d14fe
YS		 1500 memset(vmcs, 0, vmcs_config.size);
1501 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1502 return vmcs;
1503}
1504
1505static struct vmcs *alloc_vmcs(void)
1506{
d3b2c338 1507 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1508}
1509
1510static void free_vmcs(struct vmcs *vmcs)
1511{
1c3d14fe 1512 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1513}
1514
39959588 1515static void free_kvm_area(void)
6aa8b732
AK		 1516{
1517 int cpu;
1518
3230bb47 1519 for_each_possible_cpu(cpu) {
6aa8b732 1520 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1521 per_cpu(vmxarea, cpu) = NULL;
1522 }
6aa8b732
AK		 1523}
1524
6aa8b732
AK		 1525static __init int alloc_kvm_area(void)
1526{
1527 int cpu;
1528
3230bb47 1529 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1530 struct vmcs *vmcs;
1531
1532 vmcs = alloc_vmcs_cpu(cpu);
1533 if (!vmcs) {
1534 free_kvm_area();
1535 return -ENOMEM;
1536 }
1537
1538 per_cpu(vmxarea, cpu) = vmcs;
1539 }
1540 return 0;
1541}
1542
1543static __init int hardware_setup(void)
1544{
002c7f7c
YS		 1545 if (setup_vmcs_config(&vmcs_config) < 0)
1546 return -EIO;
50a37eb4
JR		 1547
1548 if (boot_cpu_has(X86_FEATURE_NX))
1549 kvm_enable_efer_bits(EFER_NX);
1550
93ba03c2
SY		 1551 if (!cpu_has_vmx_vpid())
1552 enable_vpid = 0;
1553
3a624e29 1554 if (!cpu_has_vmx_ept()) {
93ba03c2 1555 enable_ept = 0;
3a624e29
NK		 1556 enable_unrestricted_guest = 0;
1557 }
1558
1559 if (!cpu_has_vmx_unrestricted_guest())
1560 enable_unrestricted_guest = 0;
93ba03c2
SY		 1561
1562 if (!cpu_has_vmx_flexpriority())
1563 flexpriority_enabled = 0;
1564
95ba8273
GN		 1565 if (!cpu_has_vmx_tpr_shadow())
1566 kvm_x86_ops->update_cr8_intercept = NULL;
1567
54dee993
MT		 1568 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1569 kvm_disable_largepages();
1570
4b8d54f9
ZE		 1571 if (!cpu_has_vmx_ple())
1572 ple_gap = 0;
1573
6aa8b732
AK		 1574 return alloc_kvm_area();
1575}
1576
1577static __exit void hardware_unsetup(void)
1578{
1579 free_kvm_area();
1580}
1581
6aa8b732
AK		 1582static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1583{
1584 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1585
6af11b9e 1586 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1587 vmcs_write16(sf->selector, save->selector);
1588 vmcs_writel(sf->base, save->base);
1589 vmcs_write32(sf->limit, save->limit);
1590 vmcs_write32(sf->ar_bytes, save->ar);
1591 } else {
1592 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1593 << AR_DPL_SHIFT;
1594 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1595 }
1596}
1597
1598static void enter_pmode(struct kvm_vcpu *vcpu)
1599{
1600 unsigned long flags;
a89a8fb9 1601 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1602
a89a8fb9 1603 vmx->emulation_required = 1;
7ffd92c5 1604 vmx->rmode.vm86_active = 0;
6aa8b732 1605
7ffd92c5
AK		 1606 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1607 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1608 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1609
1610 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1611 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1612 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1613 vmcs_writel(GUEST_RFLAGS, flags);
1614
66aee91a
RR		 1615 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1616 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1617
1618 update_exception_bitmap(vcpu);
1619
a89a8fb9
MG		 1620 if (emulate_invalid_guest_state)
1621 return;
1622
7ffd92c5
AK		 1623 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1624 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1625 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1626 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1627
1628 vmcs_write16(GUEST_SS_SELECTOR, 0);
1629 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1630
1631 vmcs_write16(GUEST_CS_SELECTOR,
1632 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1633 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1634}
1635
d77c26fc 1636static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1637{
bfc6d222 1638 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1639 struct kvm_memslots *slots;
1640 gfn_t base_gfn;
1641
90d83dc3 1642 slots = kvm_memslots(kvm);
bc6678a3 1643 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1644 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1645 return base_gfn << PAGE_SHIFT;
1646 }
bfc6d222 1647 return kvm->arch.tss_addr;
6aa8b732
AK		 1648}
1649
1650static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1651{
1652 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1653
1654 save->selector = vmcs_read16(sf->selector);
1655 save->base = vmcs_readl(sf->base);
1656 save->limit = vmcs_read32(sf->limit);
1657 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1658 vmcs_write16(sf->selector, save->base >> 4);
1659 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1660 vmcs_write32(sf->limit, 0xffff);
1661 vmcs_write32(sf->ar_bytes, 0xf3);
1662}
1663
1664static void enter_rmode(struct kvm_vcpu *vcpu)
1665{
1666 unsigned long flags;
a89a8fb9 1667 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1668
3a624e29
NK		 1669 if (enable_unrestricted_guest)
1670 return;
1671
a89a8fb9 1672 vmx->emulation_required = 1;
7ffd92c5 1673 vmx->rmode.vm86_active = 1;
6aa8b732 1674
7ffd92c5 1675 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1676 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1677
7ffd92c5 1678 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1679 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1680
7ffd92c5 1681 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1682 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1683
1684 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1685 vmx->rmode.save_rflags = flags;
6aa8b732 1686
053de044 1687 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1688
1689 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1690 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1691 update_exception_bitmap(vcpu);
1692
a89a8fb9
MG		 1693 if (emulate_invalid_guest_state)
1694 goto continue_rmode;
1695
6aa8b732
AK		 1696 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1697 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1698 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1699
1700 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1701 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1702 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1703 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1704 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1705
7ffd92c5
AK		 1706 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1707 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1708 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1709 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1710
a89a8fb9 1711continue_rmode:
8668a3c4 1712 kvm_mmu_reset_context(vcpu);
b7ebfb05 1713 init_rmode(vcpu->kvm);
6aa8b732
AK		 1714}
1715
401d10de
AS		 1716static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1717{
1718 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1719 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1720
1721 if (!msr)
1722 return;
401d10de 1723
44ea2b17
AK		 1724 /*
1725 * Force kernel_gs_base reloading before EFER changes, as control
1726 * of this msr depends on is_long_mode().
1727 */
1728 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1729 vcpu->arch.efer = efer;
401d10de
AS		 1730 if (efer & EFER_LMA) {
1731 vmcs_write32(VM_ENTRY_CONTROLS,
1732 vmcs_read32(VM_ENTRY_CONTROLS) |
1733 VM_ENTRY_IA32E_MODE);
1734 msr->data = efer;
1735 } else {
1736 vmcs_write32(VM_ENTRY_CONTROLS,
1737 vmcs_read32(VM_ENTRY_CONTROLS) &
1738 ~VM_ENTRY_IA32E_MODE);
1739
1740 msr->data = efer & ~EFER_LME;
1741 }
1742 setup_msrs(vmx);
1743}
1744
05b3e0c2 1745#ifdef CONFIG_X86_64
6aa8b732
AK		 1746
1747static void enter_lmode(struct kvm_vcpu *vcpu)
1748{
1749 u32 guest_tr_ar;
1750
1751 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1752 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1753 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1754 __func__);
6aa8b732
AK		 1755 vmcs_write32(GUEST_TR_AR_BYTES,
1756 (guest_tr_ar & ~AR_TYPE_MASK)
1757 | AR_TYPE_BUSY_64_TSS);
1758 }
da38f438 1759 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1760}
1761
1762static void exit_lmode(struct kvm_vcpu *vcpu)
1763{
6aa8b732
AK		 1764 vmcs_write32(VM_ENTRY_CONTROLS,
1765 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1766 & ~VM_ENTRY_IA32E_MODE);
da38f438 1767 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1768}
1769
1770#endif
1771
2384d2b3
SY		 1772static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1773{
1774 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1775 if (enable_ept)
4e1096d2 1776 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1777}
1778
e8467fda
AK		 1779static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1780{
1781 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1782
1783 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1784 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1785}
1786
25c4c276 1787static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1788{
fc78f519
AK		 1789 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1790
1791 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1792 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1793}
1794
1439442c
SY		 1795static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1796{
6de4f3ad
AK		 1797 if (!test_bit(VCPU_EXREG_PDPTR,
1798 (unsigned long *)&vcpu->arch.regs_dirty))
1799 return;
1800
1439442c 1801 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1802 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1803 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1804 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1805 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1806 }
1807}
1808
8f5d549f
AK		 1809static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1810{
1811 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1812 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1813 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1814 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1815 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1816 }
6de4f3ad
AK		 1817
1818 __set_bit(VCPU_EXREG_PDPTR,
1819 (unsigned long *)&vcpu->arch.regs_avail);
1820 __set_bit(VCPU_EXREG_PDPTR,
1821 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1822}
1823
1439442c
SY		 1824static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1825
1826static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1827 unsigned long cr0,
1828 struct kvm_vcpu *vcpu)
1829{
1830 if (!(cr0 & X86_CR0_PG)) {
1831 /* From paging/starting to nonpaging */
1832 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1833 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1834 (CPU_BASED_CR3_LOAD_EXITING |
1835 CPU_BASED_CR3_STORE_EXITING));
1836 vcpu->arch.cr0 = cr0;
fc78f519 1837 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1838 } else if (!is_paging(vcpu)) {
1839 /* From nonpaging to paging */
1840 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1841 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1842 ~(CPU_BASED_CR3_LOAD_EXITING |
1843 CPU_BASED_CR3_STORE_EXITING));
1844 vcpu->arch.cr0 = cr0;
fc78f519 1845 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1846 }
95eb84a7
SY		 1847
1848 if (!(cr0 & X86_CR0_WP))
1849 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1850}
1851
6aa8b732
AK		 1852static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1853{
7ffd92c5 1854 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1855 unsigned long hw_cr0;
1856
1857 if (enable_unrestricted_guest)
1858 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1859 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1860 else
1861 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1862
7ffd92c5 1863 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1864 enter_pmode(vcpu);
1865
7ffd92c5 1866 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1867 enter_rmode(vcpu);
1868
05b3e0c2 1869#ifdef CONFIG_X86_64
f6801dff 1870 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1871 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1872 enter_lmode(vcpu);
707d92fa 1873 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1874 exit_lmode(vcpu);
1875 }
1876#endif
1877
089d034e 1878 if (enable_ept)
1439442c
SY		 1879 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1880
02daab21 1881 if (!vcpu->fpu_active)
81231c69 1882 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1883
6aa8b732 1884 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1885 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1886 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1887}
1888
1439442c
SY		 1889static u64 construct_eptp(unsigned long root_hpa)
1890{
1891 u64 eptp;
1892
1893 /* TODO write the value reading from MSR */
1894 eptp = VMX_EPT_DEFAULT_MT |
1895 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1896 eptp |= (root_hpa & PAGE_MASK);
1897
1898 return eptp;
1899}
1900
6aa8b732
AK		 1901static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1902{
1439442c
SY		 1903 unsigned long guest_cr3;
1904 u64 eptp;
1905
1906 guest_cr3 = cr3;
089d034e 1907 if (enable_ept) {
1439442c
SY		 1908 eptp = construct_eptp(cr3);
1909 vmcs_write64(EPT_POINTER, eptp);
1439442c 1910 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1911 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1912 ept_load_pdptrs(vcpu);
1439442c
SY		 1913 }
1914
2384d2b3 1915 vmx_flush_tlb(vcpu);
1439442c 1916 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1917}
1918
1919static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1920{
7ffd92c5 1921 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1922 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1923
ad312c7c 1924 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1925 if (enable_ept) {
1926 if (!is_paging(vcpu)) {
1927 hw_cr4 &= ~X86_CR4_PAE;
1928 hw_cr4 |= X86_CR4_PSE;
1929 } else if (!(cr4 & X86_CR4_PAE)) {
1930 hw_cr4 &= ~X86_CR4_PAE;
1931 }
1932 }
1439442c
SY		 1933
1934 vmcs_writel(CR4_READ_SHADOW, cr4);
1935 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1936}
1937
6aa8b732
AK		 1938static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1939{
1940 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1941
1942 return vmcs_readl(sf->base);
1943}
1944
1945static void vmx_get_segment(struct kvm_vcpu *vcpu,
1946 struct kvm_segment *var, int seg)
1947{
1948 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1949 u32 ar;
1950
1951 var->base = vmcs_readl(sf->base);
1952 var->limit = vmcs_read32(sf->limit);
1953 var->selector = vmcs_read16(sf->selector);
1954 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1955 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1956 ar = 0;
1957 var->type = ar & 15;
1958 var->s = (ar >> 4) & 1;
1959 var->dpl = (ar >> 5) & 3;
1960 var->present = (ar >> 7) & 1;
1961 var->avl = (ar >> 12) & 1;
1962 var->l = (ar >> 13) & 1;
1963 var->db = (ar >> 14) & 1;
1964 var->g = (ar >> 15) & 1;
1965 var->unusable = (ar >> 16) & 1;
1966}
1967
2e4d2653
IE		 1968static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1969{
3eeb3288 1970 if (!is_protmode(vcpu))
2e4d2653
IE		 1971 return 0;
1972
1973 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1974 return 3;
1975
eab4b8aa 1976 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1977}
1978
653e3108 1979static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1980{
6aa8b732
AK		 1981 u32 ar;
1982
653e3108 1983 if (var->unusable)
6aa8b732
AK		 1984 ar = 1 << 16;
1985 else {
1986 ar = var->type & 15;
1987 ar |= (var->s & 1) << 4;
1988 ar |= (var->dpl & 3) << 5;
1989 ar |= (var->present & 1) << 7;
1990 ar |= (var->avl & 1) << 12;
1991 ar |= (var->l & 1) << 13;
1992 ar |= (var->db & 1) << 14;
1993 ar |= (var->g & 1) << 15;
1994 }
f7fbf1fd
UL		 1995 if (ar == 0) /* a 0 value means unusable */
1996 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1997
1998 return ar;
1999}
2000
2001static void vmx_set_segment(struct kvm_vcpu *vcpu,
2002 struct kvm_segment *var, int seg)
2003{
7ffd92c5 2004 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2005 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2006 u32 ar;
2007
7ffd92c5
AK		 2008 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2009 vmx->rmode.tr.selector = var->selector;
2010 vmx->rmode.tr.base = var->base;
2011 vmx->rmode.tr.limit = var->limit;
2012 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2013 return;
2014 }
2015 vmcs_writel(sf->base, var->base);
2016 vmcs_write32(sf->limit, var->limit);
2017 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2018 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2019 /*
2020 * Hack real-mode segments into vm86 compatibility.
2021 */
2022 if (var->base == 0xffff0000 && var->selector == 0xf000)
2023 vmcs_writel(sf->base, 0xf0000);
2024 ar = 0xf3;
2025 } else
2026 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2027
2028 /*
2029 * Fix the "Accessed" bit in AR field of segment registers for older
2030 * qemu binaries.
2031 * IA32 arch specifies that at the time of processor reset the
2032 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2033 * is setting it to 0 in the usedland code. This causes invalid guest
2034 * state vmexit when "unrestricted guest" mode is turned on.
2035 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2036 * tree. Newer qemu binaries with that qemu fix would not need this
2037 * kvm hack.
2038 */
2039 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2040 ar |= 0x1; /* Accessed */
2041
6aa8b732
AK		 2042 vmcs_write32(sf->ar_bytes, ar);
2043}
2044
6aa8b732
AK		 2045static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2046{
2047 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2048
2049 *db = (ar >> 14) & 1;
2050 *l = (ar >> 13) & 1;
2051}
2052
89a27f4d 2053static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2054{
89a27f4d
GN		 2055 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2056 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2057}
2058
89a27f4d 2059static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2060{
89a27f4d
GN		 2061 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2062 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2063}
2064
89a27f4d 2065static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2066{
89a27f4d
GN		 2067 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2068 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2069}
2070
89a27f4d 2071static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2072{
89a27f4d
GN		 2073 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2074 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2075}
2076
648dfaa7
MG		 2077static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2078{
2079 struct kvm_segment var;
2080 u32 ar;
2081
2082 vmx_get_segment(vcpu, &var, seg);
2083 ar = vmx_segment_access_rights(&var);
2084
2085 if (var.base != (var.selector << 4))
2086 return false;
2087 if (var.limit != 0xffff)
2088 return false;
2089 if (ar != 0xf3)
2090 return false;
2091
2092 return true;
2093}
2094
2095static bool code_segment_valid(struct kvm_vcpu *vcpu)
2096{
2097 struct kvm_segment cs;
2098 unsigned int cs_rpl;
2099
2100 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2101 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2102
1872a3f4
AK		 2103 if (cs.unusable)
2104 return false;
648dfaa7
MG		 2105 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2106 return false;
2107 if (!cs.s)
2108 return false;
1872a3f4 2109 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2110 if (cs.dpl > cs_rpl)
2111 return false;
1872a3f4 2112 } else {
648dfaa7
MG		 2113 if (cs.dpl != cs_rpl)
2114 return false;
2115 }
2116 if (!cs.present)
2117 return false;
2118
2119 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2120 return true;
2121}
2122
2123static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2124{
2125 struct kvm_segment ss;
2126 unsigned int ss_rpl;
2127
2128 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2129 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2130
1872a3f4
AK		 2131 if (ss.unusable)
2132 return true;
2133 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2134 return false;
2135 if (!ss.s)
2136 return false;
2137 if (ss.dpl != ss_rpl) /* DPL != RPL */
2138 return false;
2139 if (!ss.present)
2140 return false;
2141
2142 return true;
2143}
2144
2145static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2146{
2147 struct kvm_segment var;
2148 unsigned int rpl;
2149
2150 vmx_get_segment(vcpu, &var, seg);
2151 rpl = var.selector & SELECTOR_RPL_MASK;
2152
1872a3f4
AK		 2153 if (var.unusable)
2154 return true;
648dfaa7
MG		 2155 if (!var.s)
2156 return false;
2157 if (!var.present)
2158 return false;
2159 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2160 if (var.dpl < rpl) /* DPL < RPL */
2161 return false;
2162 }
2163
2164 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2165 * rights flags
2166 */
2167 return true;
2168}
2169
2170static bool tr_valid(struct kvm_vcpu *vcpu)
2171{
2172 struct kvm_segment tr;
2173
2174 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2175
1872a3f4
AK		 2176 if (tr.unusable)
2177 return false;
648dfaa7
MG		 2178 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2179 return false;
1872a3f4 2180 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2181 return false;
2182 if (!tr.present)
2183 return false;
2184
2185 return true;
2186}
2187
2188static bool ldtr_valid(struct kvm_vcpu *vcpu)
2189{
2190 struct kvm_segment ldtr;
2191
2192 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2193
1872a3f4
AK		 2194 if (ldtr.unusable)
2195 return true;
648dfaa7
MG		 2196 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2197 return false;
2198 if (ldtr.type != 2)
2199 return false;
2200 if (!ldtr.present)
2201 return false;
2202
2203 return true;
2204}
2205
2206static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2207{
2208 struct kvm_segment cs, ss;
2209
2210 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2211 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2212
2213 return ((cs.selector & SELECTOR_RPL_MASK) ==
2214 (ss.selector & SELECTOR_RPL_MASK));
2215}
2216
2217/*
2218 * Check if guest state is valid. Returns true if valid, false if
2219 * not.
2220 * We assume that registers are always usable
2221 */
2222static bool guest_state_valid(struct kvm_vcpu *vcpu)
2223{
2224 /* real mode guest state checks */
3eeb3288 2225 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2226 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2227 return false;
2228 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2229 return false;
2230 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2231 return false;
2232 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2233 return false;
2234 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2235 return false;
2236 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2237 return false;
2238 } else {
2239 /* protected mode guest state checks */
2240 if (!cs_ss_rpl_check(vcpu))
2241 return false;
2242 if (!code_segment_valid(vcpu))
2243 return false;
2244 if (!stack_segment_valid(vcpu))
2245 return false;
2246 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2247 return false;
2248 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2249 return false;
2250 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2251 return false;
2252 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2253 return false;
2254 if (!tr_valid(vcpu))
2255 return false;
2256 if (!ldtr_valid(vcpu))
2257 return false;
2258 }
2259 /* TODO:
2260 * - Add checks on RIP
2261 * - Add checks on RFLAGS
2262 */
2263
2264 return true;
2265}
2266
d77c26fc 2267static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2268{
6aa8b732 2269 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2270 u16 data = 0;
10589a46 2271 int ret = 0;
195aefde 2272 int r;
6aa8b732 2273
195aefde
IE		 2274 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2275 if (r < 0)
10589a46 2276 goto out;
195aefde 2277 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2278 r = kvm_write_guest_page(kvm, fn++, &data,
2279 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2280 if (r < 0)
10589a46 2281 goto out;
195aefde
IE		 2282 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2283 if (r < 0)
10589a46 2284 goto out;
195aefde
IE		 2285 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2286 if (r < 0)
10589a46 2287 goto out;
195aefde 2288 data = ~0;
10589a46
MT		 2289 r = kvm_write_guest_page(kvm, fn, &data,
2290 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2291 sizeof(u8));
195aefde 2292 if (r < 0)
10589a46
MT		 2293 goto out;
2294
2295 ret = 1;
2296out:
10589a46 2297 return ret;
6aa8b732
AK		 2298}
2299
b7ebfb05
SY		 2300static int init_rmode_identity_map(struct kvm *kvm)
2301{
2302 int i, r, ret;
2303 pfn_t identity_map_pfn;
2304 u32 tmp;
2305
089d034e 2306 if (!enable_ept)
b7ebfb05
SY		 2307 return 1;
2308 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2309 printk(KERN_ERR "EPT: identity-mapping pagetable "
2310 "haven't been allocated!\n");
2311 return 0;
2312 }
2313 if (likely(kvm->arch.ept_identity_pagetable_done))
2314 return 1;
2315 ret = 0;
b927a3ce 2316 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2317 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2318 if (r < 0)
2319 goto out;
2320 /* Set up identity-mapping pagetable for EPT in real mode */
2321 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2322 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2323 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2324 r = kvm_write_guest_page(kvm, identity_map_pfn,
2325 &tmp, i * sizeof(tmp), sizeof(tmp));
2326 if (r < 0)
2327 goto out;
2328 }
2329 kvm->arch.ept_identity_pagetable_done = true;
2330 ret = 1;
2331out:
2332 return ret;
2333}
2334
6aa8b732
AK		 2335static void seg_setup(int seg)
2336{
2337 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2338 unsigned int ar;
6aa8b732
AK		 2339
2340 vmcs_write16(sf->selector, 0);
2341 vmcs_writel(sf->base, 0);
2342 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2343 if (enable_unrestricted_guest) {
2344 ar = 0x93;
2345 if (seg == VCPU_SREG_CS)
2346 ar |= 0x08; /* code segment */
2347 } else
2348 ar = 0xf3;
2349
2350 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2351}
2352
f78e0e2e
SY		 2353static int alloc_apic_access_page(struct kvm *kvm)
2354{
2355 struct kvm_userspace_memory_region kvm_userspace_mem;
2356 int r = 0;
2357
79fac95e 2358 mutex_lock(&kvm->slots_lock);
bfc6d222 2359 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2360 goto out;
2361 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2362 kvm_userspace_mem.flags = 0;
2363 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2364 kvm_userspace_mem.memory_size = PAGE_SIZE;
2365 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2366 if (r)
2367 goto out;
72dc67a6 2368
bfc6d222 2369 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2370out:
79fac95e 2371 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2372 return r;
2373}
2374
b7ebfb05
SY		 2375static int alloc_identity_pagetable(struct kvm *kvm)
2376{
2377 struct kvm_userspace_memory_region kvm_userspace_mem;
2378 int r = 0;
2379
79fac95e 2380 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2381 if (kvm->arch.ept_identity_pagetable)
2382 goto out;
2383 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2384 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2385 kvm_userspace_mem.guest_phys_addr =
2386 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2387 kvm_userspace_mem.memory_size = PAGE_SIZE;
2388 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2389 if (r)
2390 goto out;
2391
b7ebfb05 2392 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2393 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2394out:
79fac95e 2395 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2396 return r;
2397}
2398
2384d2b3
SY		 2399static void allocate_vpid(struct vcpu_vmx *vmx)
2400{
2401 int vpid;
2402
2403 vmx->vpid = 0;
919818ab 2404 if (!enable_vpid)
2384d2b3
SY		 2405 return;
2406 spin_lock(&vmx_vpid_lock);
2407 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2408 if (vpid < VMX_NR_VPIDS) {
2409 vmx->vpid = vpid;
2410 __set_bit(vpid, vmx_vpid_bitmap);
2411 }
2412 spin_unlock(&vmx_vpid_lock);
2413}
2414
cdbecfc3
LJ		 2415static void free_vpid(struct vcpu_vmx *vmx)
2416{
2417 if (!enable_vpid)
2418 return;
2419 spin_lock(&vmx_vpid_lock);
2420 if (vmx->vpid != 0)
2421 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2422 spin_unlock(&vmx_vpid_lock);
2423}
2424
5897297b 2425static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2426{
3e7c73e9 2427 int f = sizeof(unsigned long);
25c5f225
SY		 2428
2429 if (!cpu_has_vmx_msr_bitmap())
2430 return;
2431
2432 /*
2433 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2434 * have the write-low and read-high bitmap offsets the wrong way round.
2435 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2436 */
25c5f225 2437 if (msr <= 0x1fff) {
3e7c73e9
AK		 2438 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2439 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2440 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2441 msr &= 0x1fff;
3e7c73e9
AK		 2442 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2443 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2444 }
25c5f225
SY		 2445}
2446
5897297b
AK		 2447static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2448{
2449 if (!longmode_only)
2450 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2451 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2452}
2453
6aa8b732
AK		 2454/*
2455 * Sets up the vmcs for emulated real mode.
2456 */
8b9cf98c 2457static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2458{
468d472f 2459 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2460 u32 junk;
53f658b3 2461 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2462 unsigned long a;
89a27f4d 2463 struct desc_ptr dt;
6aa8b732 2464 int i;
cd2276a7 2465 unsigned long kvm_vmx_return;
6e5d865c 2466 u32 exec_control;
6aa8b732 2467
6aa8b732 2468 /* I/O */
3e7c73e9
AK		 2469 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2470 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2471
25c5f225 2472 if (cpu_has_vmx_msr_bitmap())
5897297b 2473 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2474
6aa8b732
AK		 2475 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2476
6aa8b732 2477 /* Control */
1c3d14fe
YS		 2478 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2479 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2480
2481 exec_control = vmcs_config.cpu_based_exec_ctrl;
2482 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2483 exec_control &= ~CPU_BASED_TPR_SHADOW;
2484#ifdef CONFIG_X86_64
2485 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2486 CPU_BASED_CR8_LOAD_EXITING;
2487#endif
2488 }
089d034e 2489 if (!enable_ept)
d56f546d 2490 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2491 CPU_BASED_CR3_LOAD_EXITING |
2492 CPU_BASED_INVLPG_EXITING;
6e5d865c 2493 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2494
83ff3b9d
SY		 2495 if (cpu_has_secondary_exec_ctrls()) {
2496 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2497 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2498 exec_control &=
2499 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2500 if (vmx->vpid == 0)
2501 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2502 if (!enable_ept) {
d56f546d 2503 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2504 enable_unrestricted_guest = 0;
2505 }
3a624e29
NK		 2506 if (!enable_unrestricted_guest)
2507 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2508 if (!ple_gap)
2509 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2510 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2511 }
f78e0e2e 2512
4b8d54f9
ZE		 2513 if (ple_gap) {
2514 vmcs_write32(PLE_GAP, ple_gap);
2515 vmcs_write32(PLE_WINDOW, ple_window);
2516 }
2517
c7addb90
AK		 2518 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2519 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2520 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2521
1c11e713 2522 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2523 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2524 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2525
2526 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2527 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2528 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2529 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2530 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2531 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2532#ifdef CONFIG_X86_64
6aa8b732
AK		 2533 rdmsrl(MSR_FS_BASE, a);
2534 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2535 rdmsrl(MSR_GS_BASE, a);
2536 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2537#else
2538 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2539 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2540#endif
2541
2542 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2543
ec68798c 2544 native_store_idt(&dt);
89a27f4d 2545 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2546
d77c26fc 2547 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2548 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2549 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2550 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2551 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2552 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2553 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2554
2555 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2556 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2557 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2558 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2559 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2560 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2561
468d472f
SY		 2562 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2563 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2564 host_pat = msr_low | ((u64) msr_high << 32);
2565 vmcs_write64(HOST_IA32_PAT, host_pat);
2566 }
2567 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2568 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2569 host_pat = msr_low | ((u64) msr_high << 32);
2570 /* Write the default value follow host pat */
2571 vmcs_write64(GUEST_IA32_PAT, host_pat);
2572 /* Keep arch.pat sync with GUEST_IA32_PAT */
2573 vmx->vcpu.arch.pat = host_pat;
2574 }
2575
6aa8b732
AK		 2576 for (i = 0; i < NR_VMX_MSR; ++i) {
2577 u32 index = vmx_msr_index[i];
2578 u32 data_low, data_high;
a2fa3e9f 2579 int j = vmx->nmsrs;
6aa8b732
AK		 2580
2581 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2582 continue;
432bd6cb
AK		 2583 if (wrmsr_safe(index, data_low, data_high) < 0)
2584 continue;
26bb0981
AK		 2585 vmx->guest_msrs[j].index = i;
2586 vmx->guest_msrs[j].data = 0;
d5696725 2587 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2588 ++vmx->nmsrs;
6aa8b732 2589 }
6aa8b732 2590
1c3d14fe 2591 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2592
2593 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2594 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2595
e00c8cf2 2596 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2597 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2598 if (enable_ept)
2599 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2600 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2601
53f658b3
MT		 2602 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2603 rdtscll(tsc_this);
2604 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2605 tsc_base = tsc_this;
2606
2607 guest_write_tsc(0, tsc_base);
f78e0e2e 2608
e00c8cf2
AK		 2609 return 0;
2610}
2611
b7ebfb05
SY		 2612static int init_rmode(struct kvm *kvm)
2613{
2614 if (!init_rmode_tss(kvm))
2615 return 0;
2616 if (!init_rmode_identity_map(kvm))
2617 return 0;
2618 return 1;
2619}
2620
e00c8cf2
AK		 2621static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2622{
2623 struct vcpu_vmx *vmx = to_vmx(vcpu);
2624 u64 msr;
f656ce01 2625 int ret, idx;
e00c8cf2 2626
5fdbf976 2627 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2628 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2629 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2630 ret = -ENOMEM;
2631 goto out;
2632 }
2633
7ffd92c5 2634 vmx->rmode.vm86_active = 0;
e00c8cf2 2635
3b86cd99
JK		 2636 vmx->soft_vnmi_blocked = 0;
2637
ad312c7c 2638 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2639 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2640 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2641 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2642 msr |= MSR_IA32_APICBASE_BSP;
2643 kvm_set_apic_base(&vmx->vcpu, msr);
2644
2645 fx_init(&vmx->vcpu);
2646
5706be0d 2647 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2648 /*
2649 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2650 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2651 */
c5af89b6 2652 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2653 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2654 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2655 } else {
ad312c7c
ZX		 2656 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2657 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2658 }
e00c8cf2
AK		 2659
2660 seg_setup(VCPU_SREG_DS);
2661 seg_setup(VCPU_SREG_ES);
2662 seg_setup(VCPU_SREG_FS);
2663 seg_setup(VCPU_SREG_GS);
2664 seg_setup(VCPU_SREG_SS);
2665
2666 vmcs_write16(GUEST_TR_SELECTOR, 0);
2667 vmcs_writel(GUEST_TR_BASE, 0);
2668 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2669 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2670
2671 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2672 vmcs_writel(GUEST_LDTR_BASE, 0);
2673 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2674 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2675
2676 vmcs_write32(GUEST_SYSENTER_CS, 0);
2677 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2678 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2679
2680 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2681 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2682 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2683 else
5fdbf976
MT		 2684 kvm_rip_write(vcpu, 0);
2685 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2686
e00c8cf2
AK		 2687 vmcs_writel(GUEST_DR7, 0x400);
2688
2689 vmcs_writel(GUEST_GDTR_BASE, 0);
2690 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2691
2692 vmcs_writel(GUEST_IDTR_BASE, 0);
2693 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2694
2695 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2696 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2697 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2698
e00c8cf2
AK		 2699 /* Special registers */
2700 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2701
2702 setup_msrs(vmx);
2703
6aa8b732
AK		 2704 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2705
f78e0e2e
SY		 2706 if (cpu_has_vmx_tpr_shadow()) {
2707 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2708 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2709 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2710 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2711 vmcs_write32(TPR_THRESHOLD, 0);
2712 }
2713
2714 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2715 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2716 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2717
2384d2b3
SY		 2718 if (vmx->vpid != 0)
2719 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2720
fa40052c 2721 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2722 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2723 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2724 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2725 vmx_fpu_activate(&vmx->vcpu);
2726 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2727
2384d2b3
SY		 2728 vpid_sync_vcpu_all(vmx);
2729
3200f405 2730 ret = 0;
6aa8b732 2731
a89a8fb9
MG		 2732 /* HACK: Don't enable emulation on guest boot/reset */
2733 vmx->emulation_required = 0;
2734
6aa8b732 2735out:
f656ce01 2736 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2737 return ret;
2738}
2739
3b86cd99
JK		 2740static void enable_irq_window(struct kvm_vcpu *vcpu)
2741{
2742 u32 cpu_based_vm_exec_control;
2743
2744 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2745 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2746 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2747}
2748
2749static void enable_nmi_window(struct kvm_vcpu *vcpu)
2750{
2751 u32 cpu_based_vm_exec_control;
2752
2753 if (!cpu_has_virtual_nmis()) {
2754 enable_irq_window(vcpu);
2755 return;
2756 }
2757
2758 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2759 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2760 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2761}
2762
66fd3f7f 2763static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2764{
9c8cba37 2765 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2766 uint32_t intr;
2767 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2768
229456fc 2769 trace_kvm_inj_virq(irq);
2714d1d3 2770
fa89a817 2771 ++vcpu->stat.irq_injections;
7ffd92c5 2772 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2773 vmx->rmode.irq.pending = true;
2774 vmx->rmode.irq.vector = irq;
5fdbf976 2775 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2776 if (vcpu->arch.interrupt.soft)
2777 vmx->rmode.irq.rip +=
2778 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2779 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2780 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2781 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2782 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2783 return;
2784 }
66fd3f7f
GN		 2785 intr = irq | INTR_INFO_VALID_MASK;
2786 if (vcpu->arch.interrupt.soft) {
2787 intr |= INTR_TYPE_SOFT_INTR;
2788 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2789 vmx->vcpu.arch.event_exit_inst_len);
2790 } else
2791 intr |= INTR_TYPE_EXT_INTR;
2792 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2793}
2794
f08864b4
SY		 2795static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2796{
66a5a347
JK		 2797 struct vcpu_vmx *vmx = to_vmx(vcpu);
2798
3b86cd99
JK		 2799 if (!cpu_has_virtual_nmis()) {
2800 /*
2801 * Tracking the NMI-blocked state in software is built upon
2802 * finding the next open IRQ window. This, in turn, depends on
2803 * well-behaving guests: They have to keep IRQs disabled at
2804 * least as long as the NMI handler runs. Otherwise we may
2805 * cause NMI nesting, maybe breaking the guest. But as this is
2806 * highly unlikely, we can live with the residual risk.
2807 */
2808 vmx->soft_vnmi_blocked = 1;
2809 vmx->vnmi_blocked_time = 0;
2810 }
2811
487b391d 2812 ++vcpu->stat.nmi_injections;
7ffd92c5 2813 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2814 vmx->rmode.irq.pending = true;
2815 vmx->rmode.irq.vector = NMI_VECTOR;
2816 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2818 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2819 INTR_INFO_VALID_MASK);
2820 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2821 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2822 return;
2823 }
f08864b4
SY		 2824 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2825 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2826}
2827
c4282df9 2828static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2829{
3b86cd99 2830 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2831 return 0;
33f089ca 2832
c4282df9 2833 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2834 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2835}
2836
3cfc3092
JK		 2837static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2838{
2839 if (!cpu_has_virtual_nmis())
2840 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2841 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2842}
2843
2844static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2845{
2846 struct vcpu_vmx *vmx = to_vmx(vcpu);
2847
2848 if (!cpu_has_virtual_nmis()) {
2849 if (vmx->soft_vnmi_blocked != masked) {
2850 vmx->soft_vnmi_blocked = masked;
2851 vmx->vnmi_blocked_time = 0;
2852 }
2853 } else {
2854 if (masked)
2855 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2856 GUEST_INTR_STATE_NMI);
2857 else
2858 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2859 GUEST_INTR_STATE_NMI);
2860 }
2861}
2862
78646121
GN		 2863static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2864{
c4282df9
GN		 2865 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2866 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2867 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2868}
2869
cbc94022
IE		 2870static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2871{
2872 int ret;
2873 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2874 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2875 .guest_phys_addr = addr,
2876 .memory_size = PAGE_SIZE * 3,
2877 .flags = 0,
2878 };
2879
2880 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2881 if (ret)
2882 return ret;
bfc6d222 2883 kvm->arch.tss_addr = addr;
cbc94022
IE		 2884 return 0;
2885}
2886
6aa8b732
AK		 2887static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2888 int vec, u32 err_code)
2889{
b3f37707
NK		 2890 /*
2891 * Instruction with address size override prefix opcode 0x67
2892 * Cause the #SS fault with 0 error code in VM86 mode.
2893 */
2894 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2895 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2896 return 1;
77ab6db0
JK		 2897 /*
2898 * Forward all other exceptions that are valid in real mode.
2899 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2900 * the required debugging infrastructure rework.
2901 */
2902 switch (vec) {
77ab6db0 2903 case DB_VECTOR:
d0bfb940
JK		 2904 if (vcpu->guest_debug &
2905 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2906 return 0;
2907 kvm_queue_exception(vcpu, vec);
2908 return 1;
77ab6db0 2909 case BP_VECTOR:
c573cd22
JK		 2910 /*
2911 * Update instruction length as we may reinject the exception
2912 * from user space while in guest debugging mode.
2913 */
2914 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2915 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2916 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2917 return 0;
2918 /* fall through */
2919 case DE_VECTOR:
77ab6db0
JK		 2920 case OF_VECTOR:
2921 case BR_VECTOR:
2922 case UD_VECTOR:
2923 case DF_VECTOR:
2924 case SS_VECTOR:
2925 case GP_VECTOR:
2926 case MF_VECTOR:
2927 kvm_queue_exception(vcpu, vec);
2928 return 1;
2929 }
6aa8b732
AK		 2930 return 0;
2931}
2932
a0861c02
AK		 2933/*
2934 * Trigger machine check on the host. We assume all the MSRs are already set up
2935 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2936 * We pass a fake environment to the machine check handler because we want
2937 * the guest to be always treated like user space, no matter what context
2938 * it used internally.
2939 */
2940static void kvm_machine_check(void)
2941{
2942#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2943 struct pt_regs regs = {
2944 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2945 .flags = X86_EFLAGS_IF,
2946 };
2947
2948 do_machine_check(&regs, 0);
2949#endif
2950}
2951
851ba692 2952static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2953{
2954 /* already handled by vcpu_run */
2955 return 1;
2956}
2957
851ba692 2958static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2959{
1155f76a 2960 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2961 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2962 u32 intr_info, ex_no, error_code;
42dbaa5a 2963 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2964 u32 vect_info;
2965 enum emulation_result er;
2966
1155f76a 2967 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2968 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2969
a0861c02 2970 if (is_machine_check(intr_info))
851ba692 2971 return handle_machine_check(vcpu);
a0861c02 2972
6aa8b732 2973 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2974 !is_page_fault(intr_info)) {
2975 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2976 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2977 vcpu->run->internal.ndata = 2;
2978 vcpu->run->internal.data[0] = vect_info;
2979 vcpu->run->internal.data[1] = intr_info;
2980 return 0;
2981 }
6aa8b732 2982
e4a41889 2983 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2984 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2985
2986 if (is_no_device(intr_info)) {
5fd86fcf 2987 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2988 return 1;
2989 }
2990
7aa81cc0 2991 if (is_invalid_opcode(intr_info)) {
851ba692 2992 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2993 if (er != EMULATE_DONE)
7ee5d940 2994 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2995 return 1;
2996 }
2997
6aa8b732 2998 error_code = 0;
5fdbf976 2999 rip = kvm_rip_read(vcpu);
2e11384c 3000 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3001 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3002 if (is_page_fault(intr_info)) {
1439442c 3003 /* EPT won't cause page fault directly */
089d034e 3004 if (enable_ept)
1439442c 3005 BUG();
6aa8b732 3006 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3007 trace_kvm_page_fault(cr2, error_code);
3008
3298b75c 3009 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3010 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3011 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3012 }
3013
7ffd92c5 3014 if (vmx->rmode.vm86_active &&
6aa8b732 3015 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3016 error_code)) {
ad312c7c
ZX		 3017 if (vcpu->arch.halt_request) {
3018 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3019 return kvm_emulate_halt(vcpu);
3020 }
6aa8b732 3021 return 1;
72d6e5a0 3022 }
6aa8b732 3023
d0bfb940 3024 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3025 switch (ex_no) {
3026 case DB_VECTOR:
3027 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3028 if (!(vcpu->guest_debug &
3029 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3030 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3031 kvm_queue_exception(vcpu, DB_VECTOR);
3032 return 1;
3033 }
3034 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3035 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3036 /* fall through */
3037 case BP_VECTOR:
c573cd22
JK		 3038 /*
3039 * Update instruction length as we may reinject #BP from
3040 * user space while in guest debugging mode. Reading it for
3041 * #DB as well causes no harm, it is not used in that case.
3042 */
3043 vmx->vcpu.arch.event_exit_inst_len =
3044 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3045 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3046 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3047 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3048 break;
3049 default:
d0bfb940
JK		 3050 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3051 kvm_run->ex.exception = ex_no;
3052 kvm_run->ex.error_code = error_code;
42dbaa5a 3053 break;
6aa8b732 3054 }
6aa8b732
AK		 3055 return 0;
3056}
3057
851ba692 3058static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3059{
1165f5fe 3060 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3061 return 1;
3062}
3063
851ba692 3064static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3065{
851ba692 3066 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3067 return 0;
3068}
6aa8b732 3069
851ba692 3070static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3071{
bfdaab09 3072 unsigned long exit_qualification;
34c33d16 3073 int size, in, string;
039576c0 3074 unsigned port;
6aa8b732 3075
bfdaab09 3076 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3077 string = (exit_qualification & 16) != 0;
cf8f70bf 3078 in = (exit_qualification & 8) != 0;
e70669ab 3079
cf8f70bf 3080 ++vcpu->stat.io_exits;
e70669ab 3081
cf8f70bf 3082 if (string || in)
6d77dbfc 3083 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3084
cf8f70bf
GN		 3085 port = exit_qualification >> 16;
3086 size = (exit_qualification & 7) + 1;
e93f36bc 3087 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3088
3089 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3090}
3091
102d8325
IM		 3092static void
3093vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3094{
3095 /*
3096 * Patch in the VMCALL instruction:
3097 */
3098 hypercall[0] = 0x0f;
3099 hypercall[1] = 0x01;
3100 hypercall[2] = 0xc1;
102d8325
IM		 3101}
3102
851ba692 3103static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3104{
229456fc 3105 unsigned long exit_qualification, val;
6aa8b732
AK		 3106 int cr;
3107 int reg;
3108
bfdaab09 3109 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3110 cr = exit_qualification & 15;
3111 reg = (exit_qualification >> 8) & 15;
3112 switch ((exit_qualification >> 4) & 3) {
3113 case 0: /* mov to cr */
229456fc
MT		 3114 val = kvm_register_read(vcpu, reg);
3115 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3116 switch (cr) {
3117 case 0:
229456fc 3118 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3119 skip_emulated_instruction(vcpu);
3120 return 1;
3121 case 3:
229456fc 3122 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3123 skip_emulated_instruction(vcpu);
3124 return 1;
3125 case 4:
229456fc 3126 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3127 skip_emulated_instruction(vcpu);
3128 return 1;
0a5fff19
GN		 3129 case 8: {
3130 u8 cr8_prev = kvm_get_cr8(vcpu);
3131 u8 cr8 = kvm_register_read(vcpu, reg);
3132 kvm_set_cr8(vcpu, cr8);
3133 skip_emulated_instruction(vcpu);
3134 if (irqchip_in_kernel(vcpu->kvm))
3135 return 1;
3136 if (cr8_prev <= cr8)
3137 return 1;
851ba692 3138 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3139 return 0;
3140 }
6aa8b732
AK		 3141 };
3142 break;
25c4c276 3143 case 2: /* clts */
edcafe3c 3144 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3145 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3146 skip_emulated_instruction(vcpu);
6b52d186 3147 vmx_fpu_activate(vcpu);
25c4c276 3148 return 1;
6aa8b732
AK		 3149 case 1: /*mov from cr*/
3150 switch (cr) {
3151 case 3:
5fdbf976 3152 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3153 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3154 skip_emulated_instruction(vcpu);
3155 return 1;
3156 case 8:
229456fc
MT		 3157 val = kvm_get_cr8(vcpu);
3158 kvm_register_write(vcpu, reg, val);
3159 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3160 skip_emulated_instruction(vcpu);
3161 return 1;
3162 }
3163 break;
3164 case 3: /* lmsw */
a1f83a74 3165 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3166 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3167 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3168
3169 skip_emulated_instruction(vcpu);
3170 return 1;
3171 default:
3172 break;
3173 }
851ba692 3174 vcpu->run->exit_reason = 0;
f0242478 3175 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3176 (int)(exit_qualification >> 4) & 3, cr);
3177 return 0;
3178}
3179
851ba692 3180static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3181{
bfdaab09 3182 unsigned long exit_qualification;
6aa8b732
AK		 3183 int dr, reg;
3184
f2483415 3185 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3186 if (!kvm_require_cpl(vcpu, 0))
3187 return 1;
42dbaa5a
JK		 3188 dr = vmcs_readl(GUEST_DR7);
3189 if (dr & DR7_GD) {
3190 /*
3191 * As the vm-exit takes precedence over the debug trap, we
3192 * need to emulate the latter, either for the host or the
3193 * guest debugging itself.
3194 */
3195 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3196 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3197 vcpu->run->debug.arch.dr7 = dr;
3198 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3199 vmcs_readl(GUEST_CS_BASE) +
3200 vmcs_readl(GUEST_RIP);
851ba692
AK		 3201 vcpu->run->debug.arch.exception = DB_VECTOR;
3202 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3203 return 0;
3204 } else {
3205 vcpu->arch.dr7 &= ~DR7_GD;
3206 vcpu->arch.dr6 |= DR6_BD;
3207 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3208 kvm_queue_exception(vcpu, DB_VECTOR);
3209 return 1;
3210 }
3211 }
3212
bfdaab09 3213 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3214 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3215 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3216 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3217 unsigned long val;
3218 if (!kvm_get_dr(vcpu, dr, &val))
3219 kvm_register_write(vcpu, reg, val);
3220 } else
3221 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3222 skip_emulated_instruction(vcpu);
3223 return 1;
3224}
3225
020df079
GN		 3226static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3227{
3228 vmcs_writel(GUEST_DR7, val);
3229}
3230
851ba692 3231static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3232{
06465c5a
AK		 3233 kvm_emulate_cpuid(vcpu);
3234 return 1;
6aa8b732
AK		 3235}
3236
851ba692 3237static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3238{
ad312c7c 3239 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3240 u64 data;
3241
3242 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3243 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3244 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3245 return 1;
3246 }
3247
229456fc 3248 trace_kvm_msr_read(ecx, data);
2714d1d3 3249
6aa8b732 3250 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3251 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3252 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3253 skip_emulated_instruction(vcpu);
3254 return 1;
3255}
3256
851ba692 3257static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3258{
ad312c7c
ZX		 3259 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3260 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3261 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3262
3263 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3264 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3265 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3266 return 1;
3267 }
3268
59200273 3269 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3270 skip_emulated_instruction(vcpu);
3271 return 1;
3272}
3273
851ba692 3274static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3275{
3276 return 1;
3277}
3278
851ba692 3279static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3280{
85f455f7
ED		 3281 u32 cpu_based_vm_exec_control;
3282
3283 /* clear pending irq */
3284 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3285 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3286 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3287
a26bf12a 3288 ++vcpu->stat.irq_window_exits;
2714d1d3 3289
c1150d8c
DL		 3290 /*
3291 * If the user space waits to inject interrupts, exit as soon as
3292 * possible
3293 */
8061823a 3294 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3295 vcpu->run->request_interrupt_window &&
8061823a 3296 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3297 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3298 return 0;
3299 }
6aa8b732
AK		 3300 return 1;
3301}
3302
851ba692 3303static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3304{
3305 skip_emulated_instruction(vcpu);
d3bef15f 3306 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3307}
3308
851ba692 3309static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3310{
510043da 3311 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3312 kvm_emulate_hypercall(vcpu);
3313 return 1;
c21415e8
IM		 3314}
3315
851ba692 3316static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3317{
3318 kvm_queue_exception(vcpu, UD_VECTOR);
3319 return 1;
3320}
3321
851ba692 3322static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3323{
f9c617f6 3324 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3325
3326 kvm_mmu_invlpg(vcpu, exit_qualification);
3327 skip_emulated_instruction(vcpu);
3328 return 1;
3329}
3330
851ba692 3331static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3332{
3333 skip_emulated_instruction(vcpu);
3334 /* TODO: Add support for VT-d/pass-through device */
3335 return 1;
3336}
3337
851ba692 3338static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3339{
6d77dbfc 3340 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3341}
3342
851ba692 3343static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3344{
60637aac 3345 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3346 unsigned long exit_qualification;
e269fb21
JK		 3347 bool has_error_code = false;
3348 u32 error_code = 0;
37817f29 3349 u16 tss_selector;
64a7ec06
GN		 3350 int reason, type, idt_v;
3351
3352 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3353 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3354
3355 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3356
3357 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3358 if (reason == TASK_SWITCH_GATE && idt_v) {
3359 switch (type) {
3360 case INTR_TYPE_NMI_INTR:
3361 vcpu->arch.nmi_injected = false;
3362 if (cpu_has_virtual_nmis())
3363 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3364 GUEST_INTR_STATE_NMI);
3365 break;
3366 case INTR_TYPE_EXT_INTR:
66fd3f7f 3367 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3368 kvm_clear_interrupt_queue(vcpu);
3369 break;
3370 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3371 if (vmx->idt_vectoring_info &
3372 VECTORING_INFO_DELIVER_CODE_MASK) {
3373 has_error_code = true;
3374 error_code =
3375 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3376 }
3377 /* fall through */
64a7ec06
GN		 3378 case INTR_TYPE_SOFT_EXCEPTION:
3379 kvm_clear_exception_queue(vcpu);
3380 break;
3381 default:
3382 break;
3383 }
60637aac 3384 }
37817f29
IE		 3385 tss_selector = exit_qualification;
3386
64a7ec06
GN		 3387 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3388 type != INTR_TYPE_EXT_INTR &&
3389 type != INTR_TYPE_NMI_INTR))
3390 skip_emulated_instruction(vcpu);
3391
acb54517
GN		 3392 if (kvm_task_switch(vcpu, tss_selector, reason,
3393 has_error_code, error_code) == EMULATE_FAIL) {
3394 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3395 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3396 vcpu->run->internal.ndata = 0;
42dbaa5a 3397 return 0;
acb54517 3398 }
42dbaa5a
JK		 3399
3400 /* clear all local breakpoint enable flags */
3401 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3402
3403 /*
3404 * TODO: What about debug traps on tss switch?
3405 * Are we supposed to inject them and update dr6?
3406 */
3407
3408 return 1;
37817f29
IE		 3409}
3410
851ba692 3411static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3412{
f9c617f6 3413 unsigned long exit_qualification;
1439442c 3414 gpa_t gpa;
1439442c 3415 int gla_validity;
1439442c 3416
f9c617f6 3417 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3418
3419 if (exit_qualification & (1 << 6)) {
3420 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3421 return -EINVAL;
1439442c
SY		 3422 }
3423
3424 gla_validity = (exit_qualification >> 7) & 0x3;
3425 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3426 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3427 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3428 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3429 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3430 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3431 (long unsigned int)exit_qualification);
851ba692
AK		 3432 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3433 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3434 return 0;
1439442c
SY		 3435 }
3436
3437 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3438 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3439 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3440}
3441
68f89400
MT		 3442static u64 ept_rsvd_mask(u64 spte, int level)
3443{
3444 int i;
3445 u64 mask = 0;
3446
3447 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3448 mask |= (1ULL << i);
3449
3450 if (level > 2)
3451 /* bits 7:3 reserved */
3452 mask |= 0xf8;
3453 else if (level == 2) {
3454 if (spte & (1ULL << 7))
3455 /* 2MB ref, bits 20:12 reserved */
3456 mask |= 0x1ff000;
3457 else
3458 /* bits 6:3 reserved */
3459 mask |= 0x78;
3460 }
3461
3462 return mask;
3463}
3464
3465static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3466 int level)
3467{
3468 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3469
3470 /* 010b (write-only) */
3471 WARN_ON((spte & 0x7) == 0x2);
3472
3473 /* 110b (write/execute) */
3474 WARN_ON((spte & 0x7) == 0x6);
3475
3476 /* 100b (execute-only) and value not supported by logical processor */
3477 if (!cpu_has_vmx_ept_execute_only())
3478 WARN_ON((spte & 0x7) == 0x4);
3479
3480 /* not 000b */
3481 if ((spte & 0x7)) {
3482 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3483
3484 if (rsvd_bits != 0) {
3485 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3486 __func__, rsvd_bits);
3487 WARN_ON(1);
3488 }
3489
3490 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3491 u64 ept_mem_type = (spte & 0x38) >> 3;
3492
3493 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3494 ept_mem_type == 7) {
3495 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3496 __func__, ept_mem_type);
3497 WARN_ON(1);
3498 }
3499 }
3500 }
3501}
3502
851ba692 3503static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3504{
3505 u64 sptes[4];
3506 int nr_sptes, i;
3507 gpa_t gpa;
3508
3509 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3510
3511 printk(KERN_ERR "EPT: Misconfiguration.\n");
3512 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3513
3514 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3515
3516 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3517 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3518
851ba692
AK		 3519 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3520 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3521
3522 return 0;
3523}
3524
851ba692 3525static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3526{
3527 u32 cpu_based_vm_exec_control;
3528
3529 /* clear pending NMI */
3530 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3531 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3532 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3533 ++vcpu->stat.nmi_window_exits;
3534
3535 return 1;
3536}
3537
80ced186 3538static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3539{
8b3079a5
AK		 3540 struct vcpu_vmx *vmx = to_vmx(vcpu);
3541 enum emulation_result err = EMULATE_DONE;
80ced186 3542 int ret = 1;
ea953ef0
MG		 3543
3544 while (!guest_state_valid(vcpu)) {
851ba692 3545 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3546
80ced186
MG		 3547 if (err == EMULATE_DO_MMIO) {
3548 ret = 0;
3549 goto out;
3550 }
1d5a4d9b 3551
6d77dbfc
GN		 3552 if (err != EMULATE_DONE)
3553 return 0;
ea953ef0
MG		 3554
3555 if (signal_pending(current))
80ced186 3556 goto out;
ea953ef0
MG		 3557 if (need_resched())
3558 schedule();
3559 }
3560
80ced186
MG		 3561 vmx->emulation_required = 0;
3562out:
3563 return ret;
ea953ef0
MG		 3564}
3565
4b8d54f9
ZE		 3566/*
3567 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3568 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3569 */
9fb41ba8 3570static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3571{
3572 skip_emulated_instruction(vcpu);
3573 kvm_vcpu_on_spin(vcpu);
3574
3575 return 1;
3576}
3577
59708670
SY		 3578static int handle_invalid_op(struct kvm_vcpu *vcpu)
3579{
3580 kvm_queue_exception(vcpu, UD_VECTOR);
3581 return 1;
3582}
3583
6aa8b732
AK		 3584/*
3585 * The exit handlers return 1 if the exit was handled fully and guest execution
3586 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3587 * to be done to userspace and return 0.
3588 */
851ba692 3589static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3590 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3591 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3592 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3593 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3594 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3595 [EXIT_REASON_CR_ACCESS] = handle_cr,
3596 [EXIT_REASON_DR_ACCESS] = handle_dr,
3597 [EXIT_REASON_CPUID] = handle_cpuid,
3598 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3599 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3600 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3601 [EXIT_REASON_HLT] = handle_halt,
a7052897 3602 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3603 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3604 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3605 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3606 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3607 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3608 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3609 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3610 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3611 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3612 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3613 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3614 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3615 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3616 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3617 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3618 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3619 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3620 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3621 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3622 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3623};
3624
3625static const int kvm_vmx_max_exit_handlers =
50a3485c 3626 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3627
3628/*
3629 * The guest has exited. See if we can fix it or if we need userspace
3630 * assistance.
3631 */
851ba692 3632static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3633{
29bd8a78 3634 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3635 u32 exit_reason = vmx->exit_reason;
1155f76a 3636 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3637
5bfd8b54 3638 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3639
80ced186
MG		 3640 /* If guest state is invalid, start emulating */
3641 if (vmx->emulation_required && emulate_invalid_guest_state)
3642 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3643
1439442c
SY		 3644 /* Access CR3 don't cause VMExit in paging mode, so we need
3645 * to sync with guest real CR3. */
6de4f3ad 3646 if (enable_ept && is_paging(vcpu))
1439442c 3647 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3648
29bd8a78 3649 if (unlikely(vmx->fail)) {
851ba692
AK		 3650 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3651 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3652 = vmcs_read32(VM_INSTRUCTION_ERROR);
3653 return 0;
3654 }
6aa8b732 3655
d77c26fc 3656 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3657 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3658 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3659 exit_reason != EXIT_REASON_TASK_SWITCH))
3660 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3661 "(0x%x) and exit reason is 0x%x\n",
3662 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3663
3664 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3665 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3666 vmx->soft_vnmi_blocked = 0;
3b86cd99 3667 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3668 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3669 /*
3670 * This CPU don't support us in finding the end of an
3671 * NMI-blocked window if the guest runs with IRQs
3672 * disabled. So we pull the trigger after 1 s of
3673 * futile waiting, but inform the user about this.
3674 */
3675 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3676 "state on VCPU %d after 1 s timeout\n",
3677 __func__, vcpu->vcpu_id);
3678 vmx->soft_vnmi_blocked = 0;
3b86cd99 3679 }
3b86cd99
JK		 3680 }
3681
6aa8b732
AK		 3682 if (exit_reason < kvm_vmx_max_exit_handlers
3683 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3684 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3685 else {
851ba692
AK		 3686 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3687 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3688 }
3689 return 0;
3690}
3691
95ba8273 3692static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3693{
95ba8273 3694 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3695 vmcs_write32(TPR_THRESHOLD, 0);
3696 return;
3697 }
3698
95ba8273 3699 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3700}
3701
cf393f75
AK		 3702static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3703{
3704 u32 exit_intr_info;
7b4a25cb 3705 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3706 bool unblock_nmi;
3707 u8 vector;
668f612f
AK		 3708 int type;
3709 bool idtv_info_valid;
cf393f75
AK		 3710
3711 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3712
a0861c02
AK		 3713 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3714
3715 /* Handle machine checks before interrupts are enabled */
3716 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3717 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3718 && is_machine_check(exit_intr_info)))
3719 kvm_machine_check();
3720
20f65983
GN		 3721 /* We need to handle NMIs before interrupts are enabled */
3722 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3723 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3724 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3725 asm("int $2");
ff9d07a0
ZY		 3726 kvm_after_handle_nmi(&vmx->vcpu);
3727 }
20f65983
GN		 3728
3729 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3730
cf393f75
AK		 3731 if (cpu_has_virtual_nmis()) {
3732 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3733 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3734 /*
7b4a25cb 3735 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3736 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3737 * a guest IRET fault.
7b4a25cb
GN		 3738 * SDM 3: 23.2.2 (September 2008)
3739 * Bit 12 is undefined in any of the following cases:
3740 * If the VM exit sets the valid bit in the IDT-vectoring
3741 * information field.
3742 * If the VM exit is due to a double fault.
cf393f75 3743 */
7b4a25cb
GN		 3744 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3745 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3746 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3747 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3748 } else if (unlikely(vmx->soft_vnmi_blocked))
3749 vmx->vnmi_blocked_time +=
3750 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3751
37b96e98
GN		 3752 vmx->vcpu.arch.nmi_injected = false;
3753 kvm_clear_exception_queue(&vmx->vcpu);
3754 kvm_clear_interrupt_queue(&vmx->vcpu);
3755
3756 if (!idtv_info_valid)
3757 return;
3758
668f612f
AK		 3759 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3760 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3761
64a7ec06 3762 switch (type) {
37b96e98
GN		 3763 case INTR_TYPE_NMI_INTR:
3764 vmx->vcpu.arch.nmi_injected = true;
668f612f 3765 /*
7b4a25cb 3766 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3767 * Clear bit "block by NMI" before VM entry if a NMI
3768 * delivery faulted.
668f612f 3769 */
37b96e98
GN		 3770 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3771 GUEST_INTR_STATE_NMI);
3772 break;
37b96e98 3773 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3774 vmx->vcpu.arch.event_exit_inst_len =
3775 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3776 /* fall through */
3777 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3778 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3779 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3780 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3781 } else
3782 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3783 break;
66fd3f7f
GN		 3784 case INTR_TYPE_SOFT_INTR:
3785 vmx->vcpu.arch.event_exit_inst_len =
3786 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3787 /* fall through */
37b96e98 3788 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3789 kvm_queue_interrupt(&vmx->vcpu, vector,
3790 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3791 break;
3792 default:
3793 break;
f7d9238f 3794 }
cf393f75
AK		 3795}
3796
9c8cba37
AK		 3797/*
3798 * Failure to inject an interrupt should give us the information
3799 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3800 * when fetching the interrupt redirection bitmap in the real-mode
3801 * tss, this doesn't happen. So we do it ourselves.
3802 */
3803static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3804{
3805 vmx->rmode.irq.pending = 0;
5fdbf976 3806 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3807 return;
5fdbf976 3808 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3809 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3810 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3811 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3812 return;
3813 }
3814 vmx->idt_vectoring_info =
3815 VECTORING_INFO_VALID_MASK
3816 | INTR_TYPE_EXT_INTR
3817 | vmx->rmode.irq.vector;
3818}
3819
c801949d
AK		 3820#ifdef CONFIG_X86_64
3821#define R "r"
3822#define Q "q"
3823#else
3824#define R "e"
3825#define Q "l"
3826#endif
3827
851ba692 3828static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3829{
a2fa3e9f 3830 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3831
3b86cd99
JK		 3832 /* Record the guest's net vcpu time for enforced NMI injections. */
3833 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3834 vmx->entry_time = ktime_get();
3835
80ced186
MG		 3836 /* Don't enter VMX if guest state is invalid, let the exit handler
3837 start emulation until we arrive back to a valid state */
3838 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3839 return;
a89a8fb9 3840
5fdbf976
MT		 3841 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3842 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3843 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3844 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3845
787ff736
GN		 3846 /* When single-stepping over STI and MOV SS, we must clear the
3847 * corresponding interruptibility bits in the guest state. Otherwise
3848 * vmentry fails as it then expects bit 14 (BS) in pending debug
3849 * exceptions being set, but that's not correct for the guest debugging
3850 * case. */
3851 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3852 vmx_set_interrupt_shadow(vcpu, 0);
3853
d77c26fc 3854 asm(
6aa8b732 3855 /* Store host registers */
c801949d
AK		 3856 "push %%"R"dx; push %%"R"bp;"
3857 "push %%"R"cx \n\t"
313dbd49
AK		 3858 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3859 "je 1f \n\t"
3860 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3861 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3862 "1: \n\t"
d3edefc0
AK		 3863 /* Reload cr2 if changed */
3864 "mov %c[cr2](%0), %%"R"ax \n\t"
3865 "mov %%cr2, %%"R"dx \n\t"
3866 "cmp %%"R"ax, %%"R"dx \n\t"
3867 "je 2f \n\t"
3868 "mov %%"R"ax, %%cr2 \n\t"
3869 "2: \n\t"
6aa8b732 3870 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3871 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3872 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3873 "mov %c[rax](%0), %%"R"ax \n\t"
3874 "mov %c[rbx](%0), %%"R"bx \n\t"
3875 "mov %c[rdx](%0), %%"R"dx \n\t"
3876 "mov %c[rsi](%0), %%"R"si \n\t"
3877 "mov %c[rdi](%0), %%"R"di \n\t"
3878 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3879#ifdef CONFIG_X86_64
e08aa78a
AK		 3880 "mov %c[r8](%0), %%r8 \n\t"
3881 "mov %c[r9](%0), %%r9 \n\t"
3882 "mov %c[r10](%0), %%r10 \n\t"
3883 "mov %c[r11](%0), %%r11 \n\t"
3884 "mov %c[r12](%0), %%r12 \n\t"
3885 "mov %c[r13](%0), %%r13 \n\t"
3886 "mov %c[r14](%0), %%r14 \n\t"
3887 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3888#endif
c801949d
AK		 3889 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3890
6aa8b732 3891 /* Enter guest mode */
cd2276a7 3892 "jne .Llaunched \n\t"
4ecac3fd 3893 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3894 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3895 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3896 ".Lkvm_vmx_return: "
6aa8b732 3897 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3898 "xchg %0, (%%"R"sp) \n\t"
3899 "mov %%"R"ax, %c[rax](%0) \n\t"
3900 "mov %%"R"bx, %c[rbx](%0) \n\t"
3901 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3902 "mov %%"R"dx, %c[rdx](%0) \n\t"
3903 "mov %%"R"si, %c[rsi](%0) \n\t"
3904 "mov %%"R"di, %c[rdi](%0) \n\t"
3905 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3906#ifdef CONFIG_X86_64
e08aa78a
AK		 3907 "mov %%r8, %c[r8](%0) \n\t"
3908 "mov %%r9, %c[r9](%0) \n\t"
3909 "mov %%r10, %c[r10](%0) \n\t"
3910 "mov %%r11, %c[r11](%0) \n\t"
3911 "mov %%r12, %c[r12](%0) \n\t"
3912 "mov %%r13, %c[r13](%0) \n\t"
3913 "mov %%r14, %c[r14](%0) \n\t"
3914 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3915#endif
c801949d
AK		 3916 "mov %%cr2, %%"R"ax \n\t"
3917 "mov %%"R"ax, %c[cr2](%0) \n\t"
3918
3919 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3920 "setbe %c[fail](%0) \n\t"
3921 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3922 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3923 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3924 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3925 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3926 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3927 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3928 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3929 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3930 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3931 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3932#ifdef CONFIG_X86_64
ad312c7c
ZX		 3933 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3934 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3935 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3936 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3937 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3938 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3939 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3940 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3941#endif
ad312c7c 3942 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3943 : "cc", "memory"
c801949d 3944 , R"bx", R"di", R"si"
c2036300 3945#ifdef CONFIG_X86_64
c2036300
LV		 3946 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3947#endif
3948 );
6aa8b732 3949
6de4f3ad
AK		 3950 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3951 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3952 vcpu->arch.regs_dirty = 0;
3953
1155f76a 3954 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3955 if (vmx->rmode.irq.pending)
3956 fixup_rmode_irq(vmx);
1155f76a 3957
d77c26fc 3958 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3959 vmx->launched = 1;
1b6269db 3960
cf393f75 3961 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3962}
3963
c801949d
AK		 3964#undef R
3965#undef Q
3966
6aa8b732
AK		 3967static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3968{
a2fa3e9f
GH		 3969 struct vcpu_vmx *vmx = to_vmx(vcpu);
3970
3971 if (vmx->vmcs) {
543e4243 3972 vcpu_clear(vmx);
a2fa3e9f
GH		 3973 free_vmcs(vmx->vmcs);
3974 vmx->vmcs = NULL;
6aa8b732
AK		 3975 }
3976}
3977
3978static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3979{
fb3f0f51
RR		 3980 struct vcpu_vmx *vmx = to_vmx(vcpu);
3981
cdbecfc3 3982 free_vpid(vmx);
6aa8b732 3983 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3984 kfree(vmx->guest_msrs);
3985 kvm_vcpu_uninit(vcpu);
a4770347 3986 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3987}
3988
fb3f0f51 3989static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3990{
fb3f0f51 3991 int err;
c16f862d 3992 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3993 int cpu;
6aa8b732 3994
a2fa3e9f 3995 if (!vmx)
fb3f0f51
RR		 3996 return ERR_PTR(-ENOMEM);
3997
2384d2b3
SY		 3998 allocate_vpid(vmx);
3999
fb3f0f51
RR		 4000 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4001 if (err)
4002 goto free_vcpu;
965b58a5 4003
a2fa3e9f 4004 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4005 if (!vmx->guest_msrs) {
4006 err = -ENOMEM;
4007 goto uninit_vcpu;
4008 }
965b58a5 4009
a2fa3e9f
GH		 4010 vmx->vmcs = alloc_vmcs();
4011 if (!vmx->vmcs)
fb3f0f51 4012 goto free_msrs;
a2fa3e9f
GH		 4013
4014 vmcs_clear(vmx->vmcs);
4015
15ad7146
AK		 4016 cpu = get_cpu();
4017 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 4018 err = vmx_vcpu_setup(vmx);
fb3f0f51 4019 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4020 put_cpu();
fb3f0f51
RR		 4021 if (err)
4022 goto free_vmcs;
5e4a0b3c
MT		 4023 if (vm_need_virtualize_apic_accesses(kvm))
4024 if (alloc_apic_access_page(kvm) != 0)
4025 goto free_vmcs;
fb3f0f51 4026
b927a3ce
SY		 4027 if (enable_ept) {
4028 if (!kvm->arch.ept_identity_map_addr)
4029 kvm->arch.ept_identity_map_addr =
4030 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4031 if (alloc_identity_pagetable(kvm) != 0)
4032 goto free_vmcs;
b927a3ce 4033 }
b7ebfb05 4034
fb3f0f51
RR		 4035 return &vmx->vcpu;
4036
4037free_vmcs:
4038 free_vmcs(vmx->vmcs);
4039free_msrs:
fb3f0f51
RR		 4040 kfree(vmx->guest_msrs);
4041uninit_vcpu:
4042 kvm_vcpu_uninit(&vmx->vcpu);
4043free_vcpu:
cdbecfc3 4044 free_vpid(vmx);
a4770347 4045 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4046 return ERR_PTR(err);
6aa8b732
AK		 4047}
4048
002c7f7c
YS		 4049static void __init vmx_check_processor_compat(void *rtn)
4050{
4051 struct vmcs_config vmcs_conf;
4052
4053 *(int *)rtn = 0;
4054 if (setup_vmcs_config(&vmcs_conf) < 0)
4055 *(int *)rtn = -EIO;
4056 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4057 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4058 smp_processor_id());
4059 *(int *)rtn = -EIO;
4060 }
4061}
4062
67253af5
SY		 4063static int get_ept_level(void)
4064{
4065 return VMX_EPT_DEFAULT_GAW + 1;
4066}
4067
4b12f0de 4068static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4069{
4b12f0de
SY		 4070 u64 ret;
4071
522c68c4
SY		 4072 /* For VT-d and EPT combination
4073 * 1. MMIO: always map as UC
4074 * 2. EPT with VT-d:
4075 * a. VT-d without snooping control feature: can't guarantee the
4076 * result, try to trust guest.
4077 * b. VT-d with snooping control feature: snooping control feature of
4078 * VT-d engine can guarantee the cache correctness. Just set it
4079 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4080 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4081 * consistent with host MTRR
4082 */
4b12f0de
SY		 4083 if (is_mmio)
4084 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4085 else if (vcpu->kvm->arch.iommu_domain &&
4086 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4087 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4088 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4089 else
522c68c4 4090 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4091 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4092
4093 return ret;
64d4d521
SY		 4094}
4095
f4c9e87c
AK		 4096#define _ER(x) { EXIT_REASON_##x, #x }
4097
229456fc 4098static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4099 _ER(EXCEPTION_NMI),
4100 _ER(EXTERNAL_INTERRUPT),
4101 _ER(TRIPLE_FAULT),
4102 _ER(PENDING_INTERRUPT),
4103 _ER(NMI_WINDOW),
4104 _ER(TASK_SWITCH),
4105 _ER(CPUID),
4106 _ER(HLT),
4107 _ER(INVLPG),
4108 _ER(RDPMC),
4109 _ER(RDTSC),
4110 _ER(VMCALL),
4111 _ER(VMCLEAR),
4112 _ER(VMLAUNCH),
4113 _ER(VMPTRLD),
4114 _ER(VMPTRST),
4115 _ER(VMREAD),
4116 _ER(VMRESUME),
4117 _ER(VMWRITE),
4118 _ER(VMOFF),
4119 _ER(VMON),
4120 _ER(CR_ACCESS),
4121 _ER(DR_ACCESS),
4122 _ER(IO_INSTRUCTION),
4123 _ER(MSR_READ),
4124 _ER(MSR_WRITE),
4125 _ER(MWAIT_INSTRUCTION),
4126 _ER(MONITOR_INSTRUCTION),
4127 _ER(PAUSE_INSTRUCTION),
4128 _ER(MCE_DURING_VMENTRY),
4129 _ER(TPR_BELOW_THRESHOLD),
4130 _ER(APIC_ACCESS),
4131 _ER(EPT_VIOLATION),
4132 _ER(EPT_MISCONFIG),
4133 _ER(WBINVD),
229456fc
MT		 4134 { -1, NULL }
4135};
4136
f4c9e87c
AK		 4137#undef _ER
4138
17cc3935 4139static int vmx_get_lpage_level(void)
344f414f 4140{
878403b7
SY		 4141 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4142 return PT_DIRECTORY_LEVEL;
4143 else
4144 /* For shadow and EPT supported 1GB page */
4145 return PT_PDPE_LEVEL;
344f414f
JR		 4146}
4147
4e47c7a6
SY		 4148static inline u32 bit(int bitno)
4149{
4150 return 1 << (bitno & 31);
4151}
4152
0e851880
SY		 4153static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4154{
4e47c7a6
SY		 4155 struct kvm_cpuid_entry2 *best;
4156 struct vcpu_vmx *vmx = to_vmx(vcpu);
4157 u32 exec_control;
4158
4159 vmx->rdtscp_enabled = false;
4160 if (vmx_rdtscp_supported()) {
4161 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4162 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4163 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4164 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4165 vmx->rdtscp_enabled = true;
4166 else {
4167 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4168 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4169 exec_control);
4170 }
4171 }
4172 }
0e851880
SY		 4173}
4174
d4330ef2
JR		 4175static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4176{
4177}
4178
cbdd1bea 4179static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4180 .cpu_has_kvm_support = cpu_has_kvm_support,
4181 .disabled_by_bios = vmx_disabled_by_bios,
4182 .hardware_setup = hardware_setup,
4183 .hardware_unsetup = hardware_unsetup,
002c7f7c 4184 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4185 .hardware_enable = hardware_enable,
4186 .hardware_disable = hardware_disable,
04547156 4187 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4188
4189 .vcpu_create = vmx_create_vcpu,
4190 .vcpu_free = vmx_free_vcpu,
04d2cc77 4191 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4192
04d2cc77 4193 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4194 .vcpu_load = vmx_vcpu_load,
4195 .vcpu_put = vmx_vcpu_put,
4196
4197 .set_guest_debug = set_guest_debug,
4198 .get_msr = vmx_get_msr,
4199 .set_msr = vmx_set_msr,
4200 .get_segment_base = vmx_get_segment_base,
4201 .get_segment = vmx_get_segment,
4202 .set_segment = vmx_set_segment,
2e4d2653 4203 .get_cpl = vmx_get_cpl,
6aa8b732 4204 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4205 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4206 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4207 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4208 .set_cr3 = vmx_set_cr3,
4209 .set_cr4 = vmx_set_cr4,
6aa8b732 4210 .set_efer = vmx_set_efer,
6aa8b732
AK		 4211 .get_idt = vmx_get_idt,
4212 .set_idt = vmx_set_idt,
4213 .get_gdt = vmx_get_gdt,
4214 .set_gdt = vmx_set_gdt,
020df079 4215 .set_dr7 = vmx_set_dr7,
5fdbf976 4216 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4217 .get_rflags = vmx_get_rflags,
4218 .set_rflags = vmx_set_rflags,
ebcbab4c 4219 .fpu_activate = vmx_fpu_activate,
02daab21 4220 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4221
4222 .tlb_flush = vmx_flush_tlb,
6aa8b732 4223
6aa8b732 4224 .run = vmx_vcpu_run,
6062d012 4225 .handle_exit = vmx_handle_exit,
6aa8b732 4226 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4227 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4228 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4229 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4230 .set_irq = vmx_inject_irq,
95ba8273 4231 .set_nmi = vmx_inject_nmi,
298101da 4232 .queue_exception = vmx_queue_exception,
78646121 4233 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4234 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4235 .get_nmi_mask = vmx_get_nmi_mask,
4236 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4237 .enable_nmi_window = enable_nmi_window,
4238 .enable_irq_window = enable_irq_window,
4239 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4240
cbc94022 4241 .set_tss_addr = vmx_set_tss_addr,
67253af5 4242 .get_tdp_level = get_ept_level,
4b12f0de 4243 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4244
4245 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4246 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4247
4248 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4249
4250 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4251
4252 .set_supported_cpuid = vmx_set_supported_cpuid,
6aa8b732
AK		 4253};
4254
4255static int __init vmx_init(void)
4256{
26bb0981
AK		 4257 int r, i;
4258
4259 rdmsrl_safe(MSR_EFER, &host_efer);
4260
4261 for (i = 0; i < NR_VMX_MSR; ++i)
4262 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4263
3e7c73e9 4264 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4265 if (!vmx_io_bitmap_a)
4266 return -ENOMEM;
4267
3e7c73e9 4268 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4269 if (!vmx_io_bitmap_b) {
4270 r = -ENOMEM;
4271 goto out;
4272 }
4273
5897297b
AK		 4274 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4275 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4276 r = -ENOMEM;
4277 goto out1;
4278 }
4279
5897297b
AK		 4280 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4281 if (!vmx_msr_bitmap_longmode) {
4282 r = -ENOMEM;
4283 goto out2;
4284 }
4285
fdef3ad1
HQ		 4286 /*
4287 * Allow direct access to the PC debug port (it is often used for I/O
4288 * delays, but the vmexits simply slow things down).
4289 */
3e7c73e9
AK		 4290 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4291 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4292
3e7c73e9 4293 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4294
5897297b
AK		 4295 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4296 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4297
2384d2b3
SY		 4298 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4299
0ee75bea
AK		 4300 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4301 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4302 if (r)
5897297b 4303 goto out3;
25c5f225 4304
5897297b
AK		 4305 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4306 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4307 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4308 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4309 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4310 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4311
089d034e 4312 if (enable_ept) {
1439442c 4313 bypass_guest_pf = 0;
5fdbcb9d 4314 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4315 VMX_EPT_WRITABLE_MASK);
534e38b4 4316 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4317 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4318 kvm_enable_tdp();
4319 } else
4320 kvm_disable_tdp();
1439442c 4321
c7addb90
AK		 4322 if (bypass_guest_pf)
4323 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4324
fdef3ad1
HQ		 4325 return 0;
4326
5897297b
AK		 4327out3:
4328 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4329out2:
5897297b 4330 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4331out1:
3e7c73e9 4332 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4333out:
3e7c73e9 4334 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4335 return r;
6aa8b732
AK		 4336}
4337
4338static void __exit vmx_exit(void)
4339{
5897297b
AK		 4340 free_page((unsigned long)vmx_msr_bitmap_legacy);
4341 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4342 free_page((unsigned long)vmx_io_bitmap_b);
4343 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4344
cb498ea2 4345 kvm_exit();
6aa8b732
AK		 4346}
4347
4348module_init(vmx_init)
4349module_exit(vmx_exit)
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