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KVM: PPC: Enable native paired singles
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
5fdbf976 30#include "kvm_cache_regs.h"
35920a35 31#include "x86.h"
e495606d 32
6aa8b732 33#include <asm/io.h>
3b3be0d1 34#include <asm/desc.h>
13673a90 35#include <asm/vmx.h>
6210e37b 36#include <asm/virtext.h>
a0861c02 37#include <asm/mce.h>
6aa8b732 38
229456fc
MT		 39#include "trace.h"
40
4ecac3fd
AK		 41#define __ex(x) __kvm_handle_fault_on_reboot(x)
42
6aa8b732
AK		 43MODULE_AUTHOR("Qumranet");
44MODULE_LICENSE("GPL");
45
4462d21a 46static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 47module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 48
4462d21a 49static int __read_mostly enable_vpid = 1;
736caefe 50module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 51
4462d21a 52static int __read_mostly flexpriority_enabled = 1;
736caefe 53module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 54
4462d21a 55static int __read_mostly enable_ept = 1;
736caefe 56module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 57
3a624e29
NK		 58static int __read_mostly enable_unrestricted_guest = 1;
59module_param_named(unrestricted_guest,
60 enable_unrestricted_guest, bool, S_IRUGO);
61
4462d21a 62static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 63module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 64
cdc0e244
AK		 65#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
66 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
67#define KVM_GUEST_CR0_MASK \
68 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
69#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 70 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 71#define KVM_VM_CR0_ALWAYS_ON \
72 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 73#define KVM_CR4_GUEST_OWNED_BITS \
74 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
75 | X86_CR4_OSXMMEXCPT)
76
cdc0e244
AK		 77#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
78#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
79
78ac8b47
AK		 80#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
81
4b8d54f9
ZE		 82/*
83 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
84 * ple_gap: upper bound on the amount of time between two successive
85 * executions of PAUSE in a loop. Also indicate if ple enabled.
86 * According to test, this time is usually small than 41 cycles.
87 * ple_window: upper bound on the amount of time a guest is allowed to execute
88 * in a PAUSE loop. Tests indicate that most spinlocks are held for
89 * less than 2^12 cycles
90 * Time is measured based on a counter that runs at the same rate as the TSC,
91 * refer SDM volume 3b section 21.6.13 & 22.1.3.
92 */
93#define KVM_VMX_DEFAULT_PLE_GAP 41
94#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
95static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
96module_param(ple_gap, int, S_IRUGO);
97
98static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
99module_param(ple_window, int, S_IRUGO);
100
a2fa3e9f
GH		 101struct vmcs {
102 u32 revision_id;
103 u32 abort;
104 char data[0];
105};
106
26bb0981
AK		 107struct shared_msr_entry {
108 unsigned index;
109 u64 data;
d5696725 110 u64 mask;
26bb0981
AK		 111};
112
a2fa3e9f 113struct vcpu_vmx {
fb3f0f51 114 struct kvm_vcpu vcpu;
543e4243 115 struct list_head local_vcpus_link;
313dbd49 116 unsigned long host_rsp;
a2fa3e9f 117 int launched;
29bd8a78 118 u8 fail;
1155f76a 119 u32 idt_vectoring_info;
26bb0981 120 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 121 int nmsrs;
122 int save_nmsrs;
a2fa3e9f 123#ifdef CONFIG_X86_64
44ea2b17
AK		 124 u64 msr_host_kernel_gs_base;
125 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 126#endif
127 struct vmcs *vmcs;
128 struct {
129 int loaded;
130 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 131 int gs_ldt_reload_needed;
132 int fs_reload_needed;
d77c26fc 133 } host_state;
9c8cba37 134 struct {
7ffd92c5 135 int vm86_active;
78ac8b47 136 ulong save_rflags;
7ffd92c5
AK		 137 struct kvm_save_segment {
138 u16 selector;
139 unsigned long base;
140 u32 limit;
141 u32 ar;
142 } tr, es, ds, fs, gs;
9c8cba37
AK		 143 struct {
144 bool pending;
145 u8 vector;
146 unsigned rip;
147 } irq;
148 } rmode;
2384d2b3 149 int vpid;
04fa4d32 150 bool emulation_required;
3b86cd99
JK		 151
152 /* Support for vnmi-less CPUs */
153 int soft_vnmi_blocked;
154 ktime_t entry_time;
155 s64 vnmi_blocked_time;
a0861c02 156 u32 exit_reason;
4e47c7a6
SY		 157
158 bool rdtscp_enabled;
a2fa3e9f
GH		 159};
160
161static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
162{
fb3f0f51 163 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 164}
165
b7ebfb05 166static int init_rmode(struct kvm *kvm);
4e1096d2 167static u64 construct_eptp(unsigned long root_hpa);
75880a01 168
6aa8b732
AK		 169static DEFINE_PER_CPU(struct vmcs *, vmxarea);
170static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 171static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 172
3e7c73e9
AK		 173static unsigned long *vmx_io_bitmap_a;
174static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 175static unsigned long *vmx_msr_bitmap_legacy;
176static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 177
2384d2b3
SY		 178static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
179static DEFINE_SPINLOCK(vmx_vpid_lock);
180
1c3d14fe 181static struct vmcs_config {
6aa8b732
AK		 182 int size;
183 int order;
184 u32 revision_id;
1c3d14fe
YS		 185 u32 pin_based_exec_ctrl;
186 u32 cpu_based_exec_ctrl;
f78e0e2e 187 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 188 u32 vmexit_ctrl;
189 u32 vmentry_ctrl;
190} vmcs_config;
6aa8b732 191
efff9e53 192static struct vmx_capability {
d56f546d
SY		 193 u32 ept;
194 u32 vpid;
195} vmx_capability;
196
6aa8b732
AK		 197#define VMX_SEGMENT_FIELD(seg) \
198 [VCPU_SREG_##seg] = { \
199 .selector = GUEST_##seg##_SELECTOR, \
200 .base = GUEST_##seg##_BASE, \
201 .limit = GUEST_##seg##_LIMIT, \
202 .ar_bytes = GUEST_##seg##_AR_BYTES, \
203 }
204
205static struct kvm_vmx_segment_field {
206 unsigned selector;
207 unsigned base;
208 unsigned limit;
209 unsigned ar_bytes;
210} kvm_vmx_segment_fields[] = {
211 VMX_SEGMENT_FIELD(CS),
212 VMX_SEGMENT_FIELD(DS),
213 VMX_SEGMENT_FIELD(ES),
214 VMX_SEGMENT_FIELD(FS),
215 VMX_SEGMENT_FIELD(GS),
216 VMX_SEGMENT_FIELD(SS),
217 VMX_SEGMENT_FIELD(TR),
218 VMX_SEGMENT_FIELD(LDTR),
219};
220
26bb0981
AK		 221static u64 host_efer;
222
6de4f3ad
AK		 223static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
224
4d56c8a7
AK		 225/*
226 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
227 * away by decrementing the array size.
228 */
6aa8b732 229static const u32 vmx_msr_index[] = {
05b3e0c2 230#ifdef CONFIG_X86_64
44ea2b17 231 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 232#endif
4e47c7a6 233 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 234};
9d8f549d 235#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 236
31299944 237static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 238{
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
240 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 241 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 242}
243
31299944 244static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 245{
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 248 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 249}
250
31299944 251static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 256}
257
31299944 258static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
261 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
262}
263
31299944 264static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 265{
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
269}
270
31299944 271static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 272{
04547156 273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 274}
275
31299944 276static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 277{
04547156 278 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 279}
280
31299944 281static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 282{
04547156 283 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 284}
285
31299944 286static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 287{
04547156
SY		 288 return vmcs_config.cpu_based_exec_ctrl &
289 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 290}
291
774ead3a 292static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 293{
04547156
SY		 294 return vmcs_config.cpu_based_2nd_exec_ctrl &
295 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
296}
297
298static inline bool cpu_has_vmx_flexpriority(void)
299{
300 return cpu_has_vmx_tpr_shadow() &&
301 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 302}
303
e799794e
MT		 304static inline bool cpu_has_vmx_ept_execute_only(void)
305{
31299944 306 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 307}
308
309static inline bool cpu_has_vmx_eptp_uncacheable(void)
310{
31299944 311 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 312}
313
314static inline bool cpu_has_vmx_eptp_writeback(void)
315{
31299944 316 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 317}
318
319static inline bool cpu_has_vmx_ept_2m_page(void)
320{
31299944 321 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 322}
323
878403b7
SY		 324static inline bool cpu_has_vmx_ept_1g_page(void)
325{
31299944 326 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 327}
328
31299944 329static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 330{
31299944 331 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 332}
333
31299944 334static inline bool cpu_has_vmx_invept_context(void)
d56f546d 335{
31299944 336 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 337}
338
31299944 339static inline bool cpu_has_vmx_invept_global(void)
d56f546d 340{
31299944 341 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 342}
343
31299944 344static inline bool cpu_has_vmx_ept(void)
d56f546d 345{
04547156
SY		 346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 348}
349
31299944 350static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 351{
352 return vmcs_config.cpu_based_2nd_exec_ctrl &
353 SECONDARY_EXEC_UNRESTRICTED_GUEST;
354}
355
31299944 356static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 357{
358 return vmcs_config.cpu_based_2nd_exec_ctrl &
359 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
360}
361
31299944 362static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 363{
6d3e435e 364 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 365}
366
31299944 367static inline bool cpu_has_vmx_vpid(void)
2384d2b3 368{
04547156
SY		 369 return vmcs_config.cpu_based_2nd_exec_ctrl &
370 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 371}
372
31299944 373static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 374{
375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_RDTSCP;
377}
378
31299944 379static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 380{
381 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
382}
383
04547156
SY		 384static inline bool report_flexpriority(void)
385{
386 return flexpriority_enabled;
387}
388
8b9cf98c 389static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 390{
391 int i;
392
a2fa3e9f 393 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 394 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 395 return i;
396 return -1;
397}
398
2384d2b3
SY		 399static inline void __invvpid(int ext, u16 vpid, gva_t gva)
400{
401 struct {
402 u64 vpid : 16;
403 u64 rsvd : 48;
404 u64 gva;
405 } operand = { vpid, 0, gva };
406
4ecac3fd 407 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 408 /* CF==1 or ZF==1 --> rc = -1 */
409 "; ja 1f ; ud2 ; 1:"
410 : : "a"(&operand), "c"(ext) : "cc", "memory");
411}
412
1439442c
SY		 413static inline void __invept(int ext, u64 eptp, gpa_t gpa)
414{
415 struct {
416 u64 eptp, gpa;
417 } operand = {eptp, gpa};
418
4ecac3fd 419 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 420 /* CF==1 or ZF==1 --> rc = -1 */
421 "; ja 1f ; ud2 ; 1:\n"
422 : : "a" (&operand), "c" (ext) : "cc", "memory");
423}
424
26bb0981 425static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 426{
427 int i;
428
8b9cf98c 429 i = __find_msr_index(vmx, msr);
a75beee6 430 if (i >= 0)
a2fa3e9f 431 return &vmx->guest_msrs[i];
8b6d44c7 432 return NULL;
7725f0ba
AK		 433}
434
6aa8b732
AK		 435static void vmcs_clear(struct vmcs *vmcs)
436{
437 u64 phys_addr = __pa(vmcs);
438 u8 error;
439
4ecac3fd 440 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 441 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
442 : "cc", "memory");
443 if (error)
444 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
445 vmcs, phys_addr);
446}
447
448static void __vcpu_clear(void *arg)
449{
8b9cf98c 450 struct vcpu_vmx *vmx = arg;
d3b2c338 451 int cpu = raw_smp_processor_id();
6aa8b732 452
8b9cf98c 453 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 454 vmcs_clear(vmx->vmcs);
455 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 456 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 457 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 458 list_del(&vmx->local_vcpus_link);
459 vmx->vcpu.cpu = -1;
460 vmx->launched = 0;
6aa8b732
AK		 461}
462
8b9cf98c 463static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 464{
eae5ecb5
AK		 465 if (vmx->vcpu.cpu == -1)
466 return;
8691e5a8 467 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 468}
469
2384d2b3
SY		 470static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
471{
472 if (vmx->vpid == 0)
473 return;
474
475 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
476}
477
1439442c
SY		 478static inline void ept_sync_global(void)
479{
480 if (cpu_has_vmx_invept_global())
481 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
482}
483
484static inline void ept_sync_context(u64 eptp)
485{
089d034e 486 if (enable_ept) {
1439442c
SY		 487 if (cpu_has_vmx_invept_context())
488 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
489 else
490 ept_sync_global();
491 }
492}
493
494static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
495{
089d034e 496 if (enable_ept) {
1439442c
SY		 497 if (cpu_has_vmx_invept_individual_addr())
498 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
499 eptp, gpa);
500 else
501 ept_sync_context(eptp);
502 }
503}
504
6aa8b732
AK		 505static unsigned long vmcs_readl(unsigned long field)
506{
507 unsigned long value;
508
4ecac3fd 509 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 510 : "=a"(value) : "d"(field) : "cc");
511 return value;
512}
513
514static u16 vmcs_read16(unsigned long field)
515{
516 return vmcs_readl(field);
517}
518
519static u32 vmcs_read32(unsigned long field)
520{
521 return vmcs_readl(field);
522}
523
524static u64 vmcs_read64(unsigned long field)
525{
05b3e0c2 526#ifdef CONFIG_X86_64
6aa8b732
AK		 527 return vmcs_readl(field);
528#else
529 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
530#endif
531}
532
e52de1b8
AK		 533static noinline void vmwrite_error(unsigned long field, unsigned long value)
534{
535 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
536 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
537 dump_stack();
538}
539
6aa8b732
AK		 540static void vmcs_writel(unsigned long field, unsigned long value)
541{
542 u8 error;
543
4ecac3fd 544 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 545 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 546 if (unlikely(error))
547 vmwrite_error(field, value);
6aa8b732
AK		 548}
549
550static void vmcs_write16(unsigned long field, u16 value)
551{
552 vmcs_writel(field, value);
553}
554
555static void vmcs_write32(unsigned long field, u32 value)
556{
557 vmcs_writel(field, value);
558}
559
560static void vmcs_write64(unsigned long field, u64 value)
561{
6aa8b732 562 vmcs_writel(field, value);
7682f2d0 563#ifndef CONFIG_X86_64
6aa8b732
AK		 564 asm volatile ("");
565 vmcs_writel(field+1, value >> 32);
566#endif
567}
568
2ab455cc
AL		 569static void vmcs_clear_bits(unsigned long field, u32 mask)
570{
571 vmcs_writel(field, vmcs_readl(field) & ~mask);
572}
573
574static void vmcs_set_bits(unsigned long field, u32 mask)
575{
576 vmcs_writel(field, vmcs_readl(field) | mask);
577}
578
abd3f2d6
AK		 579static void update_exception_bitmap(struct kvm_vcpu *vcpu)
580{
581 u32 eb;
582
fd7373cc
JK		 583 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
584 (1u << NM_VECTOR) | (1u << DB_VECTOR);
585 if ((vcpu->guest_debug &
586 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
587 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
588 eb |= 1u << BP_VECTOR;
7ffd92c5 589 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 590 eb = ~0;
089d034e 591 if (enable_ept)
1439442c 592 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 593 if (vcpu->fpu_active)
594 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 595 vmcs_write32(EXCEPTION_BITMAP, eb);
596}
597
33ed6329
AK		 598static void reload_tss(void)
599{
33ed6329
AK		 600 /*
601 * VT restores TR but not its size. Useless.
602 */
89a27f4d 603 struct desc_ptr gdt;
a5f61300 604 struct desc_struct *descs;
33ed6329 605
d6ab1ed4 606 native_store_gdt(&gdt);
89a27f4d 607 descs = (void *)gdt.address;
33ed6329
AK		 608 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
609 load_TR_desc();
33ed6329
AK		 610}
611
92c0d900 612static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 613{
3a34a881 614 u64 guest_efer;
51c6cf66
AK		 615 u64 ignore_bits;
616
f6801dff 617 guest_efer = vmx->vcpu.arch.efer;
3a34a881 618
51c6cf66
AK		 619 /*
620 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
621 * outside long mode
622 */
623 ignore_bits = EFER_NX | EFER_SCE;
624#ifdef CONFIG_X86_64
625 ignore_bits |= EFER_LMA | EFER_LME;
626 /* SCE is meaningful only in long mode on Intel */
627 if (guest_efer & EFER_LMA)
628 ignore_bits &= ~(u64)EFER_SCE;
629#endif
51c6cf66
AK		 630 guest_efer &= ~ignore_bits;
631 guest_efer |= host_efer & ignore_bits;
26bb0981 632 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 633 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 634 return true;
51c6cf66
AK		 635}
636
2d49ec72
GN		 637static unsigned long segment_base(u16 selector)
638{
639 struct desc_ptr gdt;
640 struct desc_struct *d;
641 unsigned long table_base;
642 unsigned long v;
643
644 if (!(selector & ~3))
645 return 0;
646
647 native_store_gdt(&gdt);
648 table_base = gdt.address;
649
650 if (selector & 4) { /* from ldt */
651 u16 ldt_selector = kvm_read_ldt();
652
653 if (!(ldt_selector & ~3))
654 return 0;
655
656 table_base = segment_base(ldt_selector);
657 }
658 d = (struct desc_struct *)(table_base + (selector & ~7));
659 v = get_desc_base(d);
660#ifdef CONFIG_X86_64
661 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
662 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
663#endif
664 return v;
665}
666
667static inline unsigned long kvm_read_tr_base(void)
668{
669 u16 tr;
670 asm("str %0" : "=g"(tr));
671 return segment_base(tr);
672}
673
04d2cc77 674static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 675{
04d2cc77 676 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 677 int i;
04d2cc77 678
a2fa3e9f 679 if (vmx->host_state.loaded)
33ed6329
AK		 680 return;
681
a2fa3e9f 682 vmx->host_state.loaded = 1;
33ed6329
AK		 683 /*
684 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
685 * allow segment selectors with cpl > 0 or ti == 1.
686 */
d6e88aec 687 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 688 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 689 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 690 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 691 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 692 vmx->host_state.fs_reload_needed = 0;
693 } else {
33ed6329 694 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 695 vmx->host_state.fs_reload_needed = 1;
33ed6329 696 }
d6e88aec 697 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 698 if (!(vmx->host_state.gs_sel & 7))
699 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 700 else {
701 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 702 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 703 }
704
705#ifdef CONFIG_X86_64
706 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
707 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
708#else
a2fa3e9f
GH		 709 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
710 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 711#endif
707c0874
AK		 712
713#ifdef CONFIG_X86_64
44ea2b17
AK		 714 if (is_long_mode(&vmx->vcpu)) {
715 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
716 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
717 }
707c0874 718#endif
26bb0981
AK		 719 for (i = 0; i < vmx->save_nmsrs; ++i)
720 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 721 vmx->guest_msrs[i].data,
722 vmx->guest_msrs[i].mask);
33ed6329
AK		 723}
724
a9b21b62 725static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 726{
15ad7146 727 unsigned long flags;
33ed6329 728
a2fa3e9f 729 if (!vmx->host_state.loaded)
33ed6329
AK		 730 return;
731
e1beb1d3 732 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 733 vmx->host_state.loaded = 0;
152d3f2f 734 if (vmx->host_state.fs_reload_needed)
d6e88aec 735 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 736 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 737 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 738 /*
739 * If we have to reload gs, we must take care to
740 * preserve our gs base.
741 */
15ad7146 742 local_irq_save(flags);
d6e88aec 743 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 744#ifdef CONFIG_X86_64
745 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
746#endif
15ad7146 747 local_irq_restore(flags);
33ed6329 748 }
152d3f2f 749 reload_tss();
44ea2b17
AK		 750#ifdef CONFIG_X86_64
751 if (is_long_mode(&vmx->vcpu)) {
752 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
753 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
754 }
755#endif
33ed6329
AK		 756}
757
a9b21b62
AK		 758static void vmx_load_host_state(struct vcpu_vmx *vmx)
759{
760 preempt_disable();
761 __vmx_load_host_state(vmx);
762 preempt_enable();
763}
764
6aa8b732
AK		 765/*
766 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
767 * vcpu mutex is already taken.
768 */
15ad7146 769static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 770{
a2fa3e9f
GH		 771 struct vcpu_vmx *vmx = to_vmx(vcpu);
772 u64 phys_addr = __pa(vmx->vmcs);
019960ae 773 u64 tsc_this, delta, new_offset;
6aa8b732 774
a3d7f85f 775 if (vcpu->cpu != cpu) {
8b9cf98c 776 vcpu_clear(vmx);
2f599714 777 kvm_migrate_timers(vcpu);
eb5109e3 778 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 779 local_irq_disable();
780 list_add(&vmx->local_vcpus_link,
781 &per_cpu(vcpus_on_cpu, cpu));
782 local_irq_enable();
a3d7f85f 783 }
6aa8b732 784
a2fa3e9f 785 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 786 u8 error;
787
a2fa3e9f 788 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 789 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 790 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
791 : "cc");
792 if (error)
793 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 794 vmx->vmcs, phys_addr);
6aa8b732
AK		 795 }
796
797 if (vcpu->cpu != cpu) {
89a27f4d 798 struct desc_ptr dt;
6aa8b732
AK		 799 unsigned long sysenter_esp;
800
801 vcpu->cpu = cpu;
802 /*
803 * Linux uses per-cpu TSS and GDT, so set these when switching
804 * processors.
805 */
d6e88aec 806 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d6ab1ed4 807 native_store_gdt(&dt);
89a27f4d 808 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732
AK		 809
810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 812
813 /*
814 * Make sure the time stamp counter is monotonous.
815 */
816 rdtscll(tsc_this);
019960ae
AK		 817 if (tsc_this < vcpu->arch.host_tsc) {
818 delta = vcpu->arch.host_tsc - tsc_this;
819 new_offset = vmcs_read64(TSC_OFFSET) + delta;
820 vmcs_write64(TSC_OFFSET, new_offset);
821 }
6aa8b732 822 }
6aa8b732
AK		 823}
824
825static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
826{
a9b21b62 827 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 828}
829
5fd86fcf
AK		 830static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
831{
81231c69
AK		 832 ulong cr0;
833
5fd86fcf
AK		 834 if (vcpu->fpu_active)
835 return;
836 vcpu->fpu_active = 1;
81231c69
AK		 837 cr0 = vmcs_readl(GUEST_CR0);
838 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
839 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
840 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 841 update_exception_bitmap(vcpu);
edcafe3c
AK		 842 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
843 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 844}
845
edcafe3c
AK		 846static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
847
5fd86fcf
AK		 848static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
849{
edcafe3c 850 vmx_decache_cr0_guest_bits(vcpu);
81231c69 851 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 852 update_exception_bitmap(vcpu);
edcafe3c
AK		 853 vcpu->arch.cr0_guest_owned_bits = 0;
854 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
855 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 856}
857
6aa8b732
AK		 858static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
859{
78ac8b47 860 unsigned long rflags, save_rflags;
345dcaa8
AK		 861
862 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 863 if (to_vmx(vcpu)->rmode.vm86_active) {
864 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
865 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
866 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
867 }
345dcaa8 868 return rflags;
6aa8b732
AK		 869}
870
871static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
872{
78ac8b47
AK		 873 if (to_vmx(vcpu)->rmode.vm86_active) {
874 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 875 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 876 }
6aa8b732
AK		 877 vmcs_writel(GUEST_RFLAGS, rflags);
878}
879
2809f5d2
GC		 880static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
881{
882 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
883 int ret = 0;
884
885 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 886 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 887 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 888 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 889
890 return ret & mask;
891}
892
893static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
894{
895 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
896 u32 interruptibility = interruptibility_old;
897
898 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
899
48005f64 900 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 901 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 902 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 903 interruptibility |= GUEST_INTR_STATE_STI;
904
905 if ((interruptibility != interruptibility_old))
906 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
907}
908
6aa8b732
AK		 909static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
910{
911 unsigned long rip;
6aa8b732 912
5fdbf976 913 rip = kvm_rip_read(vcpu);
6aa8b732 914 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 915 kvm_rip_write(vcpu, rip);
6aa8b732 916
2809f5d2
GC		 917 /* skipping an emulated instruction also counts */
918 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 919}
920
298101da
AK		 921static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
922 bool has_error_code, u32 error_code)
923{
77ab6db0 924 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 925 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 926
8ab2d2e2 927 if (has_error_code) {
77ab6db0 928 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 929 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
930 }
77ab6db0 931
7ffd92c5 932 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 933 vmx->rmode.irq.pending = true;
934 vmx->rmode.irq.vector = nr;
935 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 936 if (kvm_exception_is_soft(nr))
937 vmx->rmode.irq.rip +=
938 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 939 intr_info |= INTR_TYPE_SOFT_INTR;
940 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 941 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
942 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
943 return;
944 }
945
66fd3f7f
GN		 946 if (kvm_exception_is_soft(nr)) {
947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
948 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 949 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
950 } else
951 intr_info |= INTR_TYPE_HARD_EXCEPTION;
952
953 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 954}
955
4e47c7a6
SY		 956static bool vmx_rdtscp_supported(void)
957{
958 return cpu_has_vmx_rdtscp();
959}
960
a75beee6
ED		 961/*
962 * Swap MSR entry in host/guest MSR entry array.
963 */
8b9cf98c 964static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 965{
26bb0981 966 struct shared_msr_entry tmp;
a2fa3e9f
GH		 967
968 tmp = vmx->guest_msrs[to];
969 vmx->guest_msrs[to] = vmx->guest_msrs[from];
970 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 971}
972
e38aea3e
AK		 973/*
974 * Set up the vmcs to automatically save and restore system
975 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
976 * mode, as fiddling with msrs is very expensive.
977 */
8b9cf98c 978static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 979{
26bb0981 980 int save_nmsrs, index;
5897297b 981 unsigned long *msr_bitmap;
e38aea3e 982
33f9c505 983 vmx_load_host_state(vmx);
a75beee6
ED		 984 save_nmsrs = 0;
985#ifdef CONFIG_X86_64
8b9cf98c 986 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 987 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 988 if (index >= 0)
8b9cf98c
RR		 989 move_msr_up(vmx, index, save_nmsrs++);
990 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 991 if (index >= 0)
8b9cf98c
RR		 992 move_msr_up(vmx, index, save_nmsrs++);
993 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 994 if (index >= 0)
8b9cf98c 995 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 996 index = __find_msr_index(vmx, MSR_TSC_AUX);
997 if (index >= 0 && vmx->rdtscp_enabled)
998 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 999 /*
1000 * MSR_K6_STAR is only needed on long mode guests, and only
1001 * if efer.sce is enabled.
1002 */
8b9cf98c 1003 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 1004 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1005 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1006 }
1007#endif
92c0d900
AK		 1008 index = __find_msr_index(vmx, MSR_EFER);
1009 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1010 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1011
26bb0981 1012 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1013
1014 if (cpu_has_vmx_msr_bitmap()) {
1015 if (is_long_mode(&vmx->vcpu))
1016 msr_bitmap = vmx_msr_bitmap_longmode;
1017 else
1018 msr_bitmap = vmx_msr_bitmap_legacy;
1019
1020 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1021 }
e38aea3e
AK		 1022}
1023
6aa8b732
AK		 1024/*
1025 * reads and returns guest's timestamp counter "register"
1026 * guest_tsc = host_tsc + tsc_offset -- 21.3
1027 */
1028static u64 guest_read_tsc(void)
1029{
1030 u64 host_tsc, tsc_offset;
1031
1032 rdtscll(host_tsc);
1033 tsc_offset = vmcs_read64(TSC_OFFSET);
1034 return host_tsc + tsc_offset;
1035}
1036
1037/*
1038 * writes 'guest_tsc' into guest's timestamp counter "register"
1039 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1040 */
53f658b3 1041static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1042{
6aa8b732
AK		 1043 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1044}
1045
6aa8b732
AK		 1046/*
1047 * Reads an msr value (of 'msr_index') into 'pdata'.
1048 * Returns 0 on success, non-0 otherwise.
1049 * Assumes vcpu_load() was already called.
1050 */
1051static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1052{
1053 u64 data;
26bb0981 1054 struct shared_msr_entry *msr;
6aa8b732
AK		 1055
1056 if (!pdata) {
1057 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1058 return -EINVAL;
1059 }
1060
1061 switch (msr_index) {
05b3e0c2 1062#ifdef CONFIG_X86_64
6aa8b732
AK		 1063 case MSR_FS_BASE:
1064 data = vmcs_readl(GUEST_FS_BASE);
1065 break;
1066 case MSR_GS_BASE:
1067 data = vmcs_readl(GUEST_GS_BASE);
1068 break;
44ea2b17
AK		 1069 case MSR_KERNEL_GS_BASE:
1070 vmx_load_host_state(to_vmx(vcpu));
1071 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1072 break;
26bb0981 1073#endif
6aa8b732 1074 case MSR_EFER:
3bab1f5d 1075 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1076 case MSR_IA32_TSC:
6aa8b732
AK		 1077 data = guest_read_tsc();
1078 break;
1079 case MSR_IA32_SYSENTER_CS:
1080 data = vmcs_read32(GUEST_SYSENTER_CS);
1081 break;
1082 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1083 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1084 break;
1085 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1086 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1087 break;
4e47c7a6
SY		 1088 case MSR_TSC_AUX:
1089 if (!to_vmx(vcpu)->rdtscp_enabled)
1090 return 1;
1091 /* Otherwise falls through */
6aa8b732 1092 default:
26bb0981 1093 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1094 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1095 if (msr) {
542423b0 1096 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1097 data = msr->data;
1098 break;
6aa8b732 1099 }
3bab1f5d 1100 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1101 }
1102
1103 *pdata = data;
1104 return 0;
1105}
1106
1107/*
1108 * Writes msr value into into the appropriate "register".
1109 * Returns 0 on success, non-0 otherwise.
1110 * Assumes vcpu_load() was already called.
1111 */
1112static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1113{
a2fa3e9f 1114 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1115 struct shared_msr_entry *msr;
53f658b3 1116 u64 host_tsc;
2cc51560
ED		 1117 int ret = 0;
1118
6aa8b732 1119 switch (msr_index) {
3bab1f5d 1120 case MSR_EFER:
a9b21b62 1121 vmx_load_host_state(vmx);
2cc51560 1122 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1123 break;
16175a79 1124#ifdef CONFIG_X86_64
6aa8b732
AK		 1125 case MSR_FS_BASE:
1126 vmcs_writel(GUEST_FS_BASE, data);
1127 break;
1128 case MSR_GS_BASE:
1129 vmcs_writel(GUEST_GS_BASE, data);
1130 break;
44ea2b17
AK		 1131 case MSR_KERNEL_GS_BASE:
1132 vmx_load_host_state(vmx);
1133 vmx->msr_guest_kernel_gs_base = data;
1134 break;
6aa8b732
AK		 1135#endif
1136 case MSR_IA32_SYSENTER_CS:
1137 vmcs_write32(GUEST_SYSENTER_CS, data);
1138 break;
1139 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1140 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1141 break;
1142 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1143 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1144 break;
af24a4e4 1145 case MSR_IA32_TSC:
53f658b3
MT		 1146 rdtscll(host_tsc);
1147 guest_write_tsc(data, host_tsc);
6aa8b732 1148 break;
468d472f
SY		 1149 case MSR_IA32_CR_PAT:
1150 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1151 vmcs_write64(GUEST_IA32_PAT, data);
1152 vcpu->arch.pat = data;
1153 break;
1154 }
4e47c7a6
SY		 1155 ret = kvm_set_msr_common(vcpu, msr_index, data);
1156 break;
1157 case MSR_TSC_AUX:
1158 if (!vmx->rdtscp_enabled)
1159 return 1;
1160 /* Check reserved bit, higher 32 bits should be zero */
1161 if ((data >> 32) != 0)
1162 return 1;
1163 /* Otherwise falls through */
6aa8b732 1164 default:
8b9cf98c 1165 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1166 if (msr) {
542423b0 1167 vmx_load_host_state(vmx);
3bab1f5d
AK		 1168 msr->data = data;
1169 break;
6aa8b732 1170 }
2cc51560 1171 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1172 }
1173
2cc51560 1174 return ret;
6aa8b732
AK		 1175}
1176
5fdbf976 1177static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1178{
5fdbf976
MT		 1179 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1180 switch (reg) {
1181 case VCPU_REGS_RSP:
1182 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1183 break;
1184 case VCPU_REGS_RIP:
1185 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1186 break;
6de4f3ad
AK		 1187 case VCPU_EXREG_PDPTR:
1188 if (enable_ept)
1189 ept_save_pdptrs(vcpu);
1190 break;
5fdbf976
MT		 1191 default:
1192 break;
1193 }
6aa8b732
AK		 1194}
1195
355be0b9 1196static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1197{
ae675ef0
JK		 1198 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1199 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1200 else
1201 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1202
abd3f2d6 1203 update_exception_bitmap(vcpu);
6aa8b732
AK		 1204}
1205
1206static __init int cpu_has_kvm_support(void)
1207{
6210e37b 1208 return cpu_has_vmx();
6aa8b732
AK		 1209}
1210
1211static __init int vmx_disabled_by_bios(void)
1212{
1213 u64 msr;
1214
1215 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1216 return (msr & (FEATURE_CONTROL_LOCKED |
1217 FEATURE_CONTROL_VMXON_ENABLED))
1218 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1219 /* locked but not enabled */
6aa8b732
AK		 1220}
1221
10474ae8 1222static int hardware_enable(void *garbage)
6aa8b732
AK		 1223{
1224 int cpu = raw_smp_processor_id();
1225 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1226 u64 old;
1227
10474ae8
AG		 1228 if (read_cr4() & X86_CR4_VMXE)
1229 return -EBUSY;
1230
543e4243 1231 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1232 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1233 if ((old & (FEATURE_CONTROL_LOCKED |
1234 FEATURE_CONTROL_VMXON_ENABLED))
1235 != (FEATURE_CONTROL_LOCKED |
1236 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1237 /* enable and lock */
62b3ffb8 1238 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1239 FEATURE_CONTROL_LOCKED |
1240 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1241 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1242 asm volatile (ASM_VMX_VMXON_RAX
1243 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1244 : "memory", "cc");
10474ae8
AG		 1245
1246 ept_sync_global();
1247
1248 return 0;
6aa8b732
AK		 1249}
1250
543e4243
AK		 1251static void vmclear_local_vcpus(void)
1252{
1253 int cpu = raw_smp_processor_id();
1254 struct vcpu_vmx *vmx, *n;
1255
1256 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1257 local_vcpus_link)
1258 __vcpu_clear(vmx);
1259}
1260
710ff4a8
EH		 1261
1262/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1263 * tricks.
1264 */
1265static void kvm_cpu_vmxoff(void)
6aa8b732 1266{
4ecac3fd 1267 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1268 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1269}
1270
710ff4a8
EH		 1271static void hardware_disable(void *garbage)
1272{
1273 vmclear_local_vcpus();
1274 kvm_cpu_vmxoff();
1275}
1276
1c3d14fe 1277static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1278 u32 msr, u32 *result)
1c3d14fe
YS		 1279{
1280 u32 vmx_msr_low, vmx_msr_high;
1281 u32 ctl = ctl_min | ctl_opt;
1282
1283 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1284
1285 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1286 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1287
1288 /* Ensure minimum (required) set of control bits are supported. */
1289 if (ctl_min & ~ctl)
002c7f7c 1290 return -EIO;
1c3d14fe
YS		 1291
1292 *result = ctl;
1293 return 0;
1294}
1295
002c7f7c 1296static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1297{
1298 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1299 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1300 u32 _pin_based_exec_control = 0;
1301 u32 _cpu_based_exec_control = 0;
f78e0e2e 1302 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1303 u32 _vmexit_control = 0;
1304 u32 _vmentry_control = 0;
1305
1306 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1307 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1308 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1309 &_pin_based_exec_control) < 0)
002c7f7c 1310 return -EIO;
1c3d14fe
YS		 1311
1312 min = CPU_BASED_HLT_EXITING |
1313#ifdef CONFIG_X86_64
1314 CPU_BASED_CR8_LOAD_EXITING |
1315 CPU_BASED_CR8_STORE_EXITING |
1316#endif
d56f546d
SY		 1317 CPU_BASED_CR3_LOAD_EXITING |
1318 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1319 CPU_BASED_USE_IO_BITMAPS |
1320 CPU_BASED_MOV_DR_EXITING |
a7052897 1321 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1322 CPU_BASED_MWAIT_EXITING |
1323 CPU_BASED_MONITOR_EXITING |
a7052897 1324 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1325 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1326 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1327 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1328 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1329 &_cpu_based_exec_control) < 0)
002c7f7c 1330 return -EIO;
6e5d865c
YS		 1331#ifdef CONFIG_X86_64
1332 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1333 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1334 ~CPU_BASED_CR8_STORE_EXITING;
1335#endif
f78e0e2e 1336 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1337 min2 = 0;
1338 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1339 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1340 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1341 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1342 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1343 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1344 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1345 if (adjust_vmx_controls(min2, opt2,
1346 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1347 &_cpu_based_2nd_exec_control) < 0)
1348 return -EIO;
1349 }
1350#ifndef CONFIG_X86_64
1351 if (!(_cpu_based_2nd_exec_control &
1352 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1353 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1354#endif
d56f546d 1355 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1356 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1357 enabled */
5fff7d27
GN		 1358 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1359 CPU_BASED_CR3_STORE_EXITING |
1360 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1361 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1362 vmx_capability.ept, vmx_capability.vpid);
1363 }
1c3d14fe
YS		 1364
1365 min = 0;
1366#ifdef CONFIG_X86_64
1367 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1368#endif
468d472f 1369 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1370 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1371 &_vmexit_control) < 0)
002c7f7c 1372 return -EIO;
1c3d14fe 1373
468d472f
SY		 1374 min = 0;
1375 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1376 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1377 &_vmentry_control) < 0)
002c7f7c 1378 return -EIO;
6aa8b732 1379
c68876fd 1380 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1381
1382 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1383 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1384 return -EIO;
1c3d14fe
YS		 1385
1386#ifdef CONFIG_X86_64
1387 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1388 if (vmx_msr_high & (1u<<16))
002c7f7c 1389 return -EIO;
1c3d14fe
YS		 1390#endif
1391
1392 /* Require Write-Back (WB) memory type for VMCS accesses. */
1393 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1394 return -EIO;
1c3d14fe 1395
002c7f7c
YS		 1396 vmcs_conf->size = vmx_msr_high & 0x1fff;
1397 vmcs_conf->order = get_order(vmcs_config.size);
1398 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1399
002c7f7c
YS		 1400 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1401 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1402 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1403 vmcs_conf->vmexit_ctrl = _vmexit_control;
1404 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1405
1406 return 0;
c68876fd 1407}
6aa8b732
AK		 1408
1409static struct vmcs *alloc_vmcs_cpu(int cpu)
1410{
1411 int node = cpu_to_node(cpu);
1412 struct page *pages;
1413 struct vmcs *vmcs;
1414
6484eb3e 1415 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1416 if (!pages)
1417 return NULL;
1418 vmcs = page_address(pages);
1c3d14fe
YS		 1419 memset(vmcs, 0, vmcs_config.size);
1420 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1421 return vmcs;
1422}
1423
1424static struct vmcs *alloc_vmcs(void)
1425{
d3b2c338 1426 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1427}
1428
1429static void free_vmcs(struct vmcs *vmcs)
1430{
1c3d14fe 1431 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1432}
1433
39959588 1434static void free_kvm_area(void)
6aa8b732
AK		 1435{
1436 int cpu;
1437
3230bb47 1438 for_each_possible_cpu(cpu) {
6aa8b732 1439 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1440 per_cpu(vmxarea, cpu) = NULL;
1441 }
6aa8b732
AK		 1442}
1443
6aa8b732
AK		 1444static __init int alloc_kvm_area(void)
1445{
1446 int cpu;
1447
3230bb47 1448 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1449 struct vmcs *vmcs;
1450
1451 vmcs = alloc_vmcs_cpu(cpu);
1452 if (!vmcs) {
1453 free_kvm_area();
1454 return -ENOMEM;
1455 }
1456
1457 per_cpu(vmxarea, cpu) = vmcs;
1458 }
1459 return 0;
1460}
1461
1462static __init int hardware_setup(void)
1463{
002c7f7c
YS		 1464 if (setup_vmcs_config(&vmcs_config) < 0)
1465 return -EIO;
50a37eb4
JR		 1466
1467 if (boot_cpu_has(X86_FEATURE_NX))
1468 kvm_enable_efer_bits(EFER_NX);
1469
93ba03c2
SY		 1470 if (!cpu_has_vmx_vpid())
1471 enable_vpid = 0;
1472
3a624e29 1473 if (!cpu_has_vmx_ept()) {
93ba03c2 1474 enable_ept = 0;
3a624e29
NK		 1475 enable_unrestricted_guest = 0;
1476 }
1477
1478 if (!cpu_has_vmx_unrestricted_guest())
1479 enable_unrestricted_guest = 0;
93ba03c2
SY		 1480
1481 if (!cpu_has_vmx_flexpriority())
1482 flexpriority_enabled = 0;
1483
95ba8273
GN		 1484 if (!cpu_has_vmx_tpr_shadow())
1485 kvm_x86_ops->update_cr8_intercept = NULL;
1486
54dee993
MT		 1487 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1488 kvm_disable_largepages();
1489
4b8d54f9
ZE		 1490 if (!cpu_has_vmx_ple())
1491 ple_gap = 0;
1492
6aa8b732
AK		 1493 return alloc_kvm_area();
1494}
1495
1496static __exit void hardware_unsetup(void)
1497{
1498 free_kvm_area();
1499}
1500
6aa8b732
AK		 1501static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1502{
1503 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1504
6af11b9e 1505 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1506 vmcs_write16(sf->selector, save->selector);
1507 vmcs_writel(sf->base, save->base);
1508 vmcs_write32(sf->limit, save->limit);
1509 vmcs_write32(sf->ar_bytes, save->ar);
1510 } else {
1511 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1512 << AR_DPL_SHIFT;
1513 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1514 }
1515}
1516
1517static void enter_pmode(struct kvm_vcpu *vcpu)
1518{
1519 unsigned long flags;
a89a8fb9 1520 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1521
a89a8fb9 1522 vmx->emulation_required = 1;
7ffd92c5 1523 vmx->rmode.vm86_active = 0;
6aa8b732 1524
7ffd92c5
AK		 1525 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1526 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1527 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1528
1529 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1530 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1531 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1532 vmcs_writel(GUEST_RFLAGS, flags);
1533
66aee91a
RR		 1534 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1535 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1536
1537 update_exception_bitmap(vcpu);
1538
a89a8fb9
MG		 1539 if (emulate_invalid_guest_state)
1540 return;
1541
7ffd92c5
AK		 1542 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1543 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1544 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1545 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1546
1547 vmcs_write16(GUEST_SS_SELECTOR, 0);
1548 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1549
1550 vmcs_write16(GUEST_CS_SELECTOR,
1551 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1552 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1553}
1554
d77c26fc 1555static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1556{
bfc6d222 1557 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1558 struct kvm_memslots *slots;
1559 gfn_t base_gfn;
1560
90d83dc3 1561 slots = kvm_memslots(kvm);
bc6678a3 1562 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1563 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1564 return base_gfn << PAGE_SHIFT;
1565 }
bfc6d222 1566 return kvm->arch.tss_addr;
6aa8b732
AK		 1567}
1568
1569static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1570{
1571 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1572
1573 save->selector = vmcs_read16(sf->selector);
1574 save->base = vmcs_readl(sf->base);
1575 save->limit = vmcs_read32(sf->limit);
1576 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1577 vmcs_write16(sf->selector, save->base >> 4);
1578 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1579 vmcs_write32(sf->limit, 0xffff);
1580 vmcs_write32(sf->ar_bytes, 0xf3);
1581}
1582
1583static void enter_rmode(struct kvm_vcpu *vcpu)
1584{
1585 unsigned long flags;
a89a8fb9 1586 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1587
3a624e29
NK		 1588 if (enable_unrestricted_guest)
1589 return;
1590
a89a8fb9 1591 vmx->emulation_required = 1;
7ffd92c5 1592 vmx->rmode.vm86_active = 1;
6aa8b732 1593
7ffd92c5 1594 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1595 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1596
7ffd92c5 1597 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1598 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1599
7ffd92c5 1600 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1601 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1602
1603 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1604 vmx->rmode.save_rflags = flags;
6aa8b732 1605
053de044 1606 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1607
1608 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1609 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1610 update_exception_bitmap(vcpu);
1611
a89a8fb9
MG		 1612 if (emulate_invalid_guest_state)
1613 goto continue_rmode;
1614
6aa8b732
AK		 1615 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1616 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1617 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1618
1619 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1620 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1621 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1622 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1623 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1624
7ffd92c5
AK		 1625 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1626 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1627 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1628 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1629
a89a8fb9 1630continue_rmode:
8668a3c4 1631 kvm_mmu_reset_context(vcpu);
b7ebfb05 1632 init_rmode(vcpu->kvm);
6aa8b732
AK		 1633}
1634
401d10de
AS		 1635static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1636{
1637 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1638 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1639
1640 if (!msr)
1641 return;
401d10de 1642
44ea2b17
AK		 1643 /*
1644 * Force kernel_gs_base reloading before EFER changes, as control
1645 * of this msr depends on is_long_mode().
1646 */
1647 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1648 vcpu->arch.efer = efer;
401d10de
AS		 1649 if (efer & EFER_LMA) {
1650 vmcs_write32(VM_ENTRY_CONTROLS,
1651 vmcs_read32(VM_ENTRY_CONTROLS) |
1652 VM_ENTRY_IA32E_MODE);
1653 msr->data = efer;
1654 } else {
1655 vmcs_write32(VM_ENTRY_CONTROLS,
1656 vmcs_read32(VM_ENTRY_CONTROLS) &
1657 ~VM_ENTRY_IA32E_MODE);
1658
1659 msr->data = efer & ~EFER_LME;
1660 }
1661 setup_msrs(vmx);
1662}
1663
05b3e0c2 1664#ifdef CONFIG_X86_64
6aa8b732
AK		 1665
1666static void enter_lmode(struct kvm_vcpu *vcpu)
1667{
1668 u32 guest_tr_ar;
1669
1670 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1671 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1672 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1673 __func__);
6aa8b732
AK		 1674 vmcs_write32(GUEST_TR_AR_BYTES,
1675 (guest_tr_ar & ~AR_TYPE_MASK)
1676 | AR_TYPE_BUSY_64_TSS);
1677 }
f6801dff
AK		 1678 vcpu->arch.efer |= EFER_LMA;
1679 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1680}
1681
1682static void exit_lmode(struct kvm_vcpu *vcpu)
1683{
f6801dff 1684 vcpu->arch.efer &= ~EFER_LMA;
6aa8b732
AK		 1685
1686 vmcs_write32(VM_ENTRY_CONTROLS,
1687 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1688 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1689}
1690
1691#endif
1692
2384d2b3
SY		 1693static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1694{
1695 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1696 if (enable_ept)
4e1096d2 1697 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1698}
1699
e8467fda
AK		 1700static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1701{
1702 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1703
1704 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1705 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1706}
1707
25c4c276 1708static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1709{
fc78f519
AK		 1710 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1711
1712 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1713 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1714}
1715
1439442c
SY		 1716static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1717{
6de4f3ad
AK		 1718 if (!test_bit(VCPU_EXREG_PDPTR,
1719 (unsigned long *)&vcpu->arch.regs_dirty))
1720 return;
1721
1439442c 1722 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1723 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1724 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1725 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1726 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1727 }
1728}
1729
8f5d549f
AK		 1730static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1731{
1732 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1733 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1734 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1735 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1736 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1737 }
6de4f3ad
AK		 1738
1739 __set_bit(VCPU_EXREG_PDPTR,
1740 (unsigned long *)&vcpu->arch.regs_avail);
1741 __set_bit(VCPU_EXREG_PDPTR,
1742 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1743}
1744
1439442c
SY		 1745static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1746
1747static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1748 unsigned long cr0,
1749 struct kvm_vcpu *vcpu)
1750{
1751 if (!(cr0 & X86_CR0_PG)) {
1752 /* From paging/starting to nonpaging */
1753 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1754 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1755 (CPU_BASED_CR3_LOAD_EXITING |
1756 CPU_BASED_CR3_STORE_EXITING));
1757 vcpu->arch.cr0 = cr0;
fc78f519 1758 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1759 } else if (!is_paging(vcpu)) {
1760 /* From nonpaging to paging */
1761 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1762 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1763 ~(CPU_BASED_CR3_LOAD_EXITING |
1764 CPU_BASED_CR3_STORE_EXITING));
1765 vcpu->arch.cr0 = cr0;
fc78f519 1766 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1767 }
95eb84a7
SY		 1768
1769 if (!(cr0 & X86_CR0_WP))
1770 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1771}
1772
6aa8b732
AK		 1773static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1774{
7ffd92c5 1775 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1776 unsigned long hw_cr0;
1777
1778 if (enable_unrestricted_guest)
1779 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1780 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1781 else
1782 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1783
7ffd92c5 1784 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1785 enter_pmode(vcpu);
1786
7ffd92c5 1787 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1788 enter_rmode(vcpu);
1789
05b3e0c2 1790#ifdef CONFIG_X86_64
f6801dff 1791 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1792 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1793 enter_lmode(vcpu);
707d92fa 1794 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1795 exit_lmode(vcpu);
1796 }
1797#endif
1798
089d034e 1799 if (enable_ept)
1439442c
SY		 1800 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1801
02daab21 1802 if (!vcpu->fpu_active)
81231c69 1803 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1804
6aa8b732 1805 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1806 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1807 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1808}
1809
1439442c
SY		 1810static u64 construct_eptp(unsigned long root_hpa)
1811{
1812 u64 eptp;
1813
1814 /* TODO write the value reading from MSR */
1815 eptp = VMX_EPT_DEFAULT_MT |
1816 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1817 eptp |= (root_hpa & PAGE_MASK);
1818
1819 return eptp;
1820}
1821
6aa8b732
AK		 1822static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1823{
1439442c
SY		 1824 unsigned long guest_cr3;
1825 u64 eptp;
1826
1827 guest_cr3 = cr3;
089d034e 1828 if (enable_ept) {
1439442c
SY		 1829 eptp = construct_eptp(cr3);
1830 vmcs_write64(EPT_POINTER, eptp);
1439442c 1831 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1832 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1833 ept_load_pdptrs(vcpu);
1439442c
SY		 1834 }
1835
2384d2b3 1836 vmx_flush_tlb(vcpu);
1439442c 1837 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1838}
1839
1840static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1841{
7ffd92c5 1842 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1843 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1844
ad312c7c 1845 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1846 if (enable_ept) {
1847 if (!is_paging(vcpu)) {
1848 hw_cr4 &= ~X86_CR4_PAE;
1849 hw_cr4 |= X86_CR4_PSE;
1850 } else if (!(cr4 & X86_CR4_PAE)) {
1851 hw_cr4 &= ~X86_CR4_PAE;
1852 }
1853 }
1439442c
SY		 1854
1855 vmcs_writel(CR4_READ_SHADOW, cr4);
1856 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1857}
1858
6aa8b732
AK		 1859static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1860{
1861 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1862
1863 return vmcs_readl(sf->base);
1864}
1865
1866static void vmx_get_segment(struct kvm_vcpu *vcpu,
1867 struct kvm_segment *var, int seg)
1868{
1869 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1870 u32 ar;
1871
1872 var->base = vmcs_readl(sf->base);
1873 var->limit = vmcs_read32(sf->limit);
1874 var->selector = vmcs_read16(sf->selector);
1875 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1876 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1877 ar = 0;
1878 var->type = ar & 15;
1879 var->s = (ar >> 4) & 1;
1880 var->dpl = (ar >> 5) & 3;
1881 var->present = (ar >> 7) & 1;
1882 var->avl = (ar >> 12) & 1;
1883 var->l = (ar >> 13) & 1;
1884 var->db = (ar >> 14) & 1;
1885 var->g = (ar >> 15) & 1;
1886 var->unusable = (ar >> 16) & 1;
1887}
1888
2e4d2653
IE		 1889static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1890{
3eeb3288 1891 if (!is_protmode(vcpu))
2e4d2653
IE		 1892 return 0;
1893
1894 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1895 return 3;
1896
eab4b8aa 1897 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1898}
1899
653e3108 1900static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1901{
6aa8b732
AK		 1902 u32 ar;
1903
653e3108 1904 if (var->unusable)
6aa8b732
AK		 1905 ar = 1 << 16;
1906 else {
1907 ar = var->type & 15;
1908 ar |= (var->s & 1) << 4;
1909 ar |= (var->dpl & 3) << 5;
1910 ar |= (var->present & 1) << 7;
1911 ar |= (var->avl & 1) << 12;
1912 ar |= (var->l & 1) << 13;
1913 ar |= (var->db & 1) << 14;
1914 ar |= (var->g & 1) << 15;
1915 }
f7fbf1fd
UL		 1916 if (ar == 0) /* a 0 value means unusable */
1917 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1918
1919 return ar;
1920}
1921
1922static void vmx_set_segment(struct kvm_vcpu *vcpu,
1923 struct kvm_segment *var, int seg)
1924{
7ffd92c5 1925 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1926 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1927 u32 ar;
1928
7ffd92c5
AK		 1929 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1930 vmx->rmode.tr.selector = var->selector;
1931 vmx->rmode.tr.base = var->base;
1932 vmx->rmode.tr.limit = var->limit;
1933 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1934 return;
1935 }
1936 vmcs_writel(sf->base, var->base);
1937 vmcs_write32(sf->limit, var->limit);
1938 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1939 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1940 /*
1941 * Hack real-mode segments into vm86 compatibility.
1942 */
1943 if (var->base == 0xffff0000 && var->selector == 0xf000)
1944 vmcs_writel(sf->base, 0xf0000);
1945 ar = 0xf3;
1946 } else
1947 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1948
1949 /*
1950 * Fix the "Accessed" bit in AR field of segment registers for older
1951 * qemu binaries.
1952 * IA32 arch specifies that at the time of processor reset the
1953 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1954 * is setting it to 0 in the usedland code. This causes invalid guest
1955 * state vmexit when "unrestricted guest" mode is turned on.
1956 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1957 * tree. Newer qemu binaries with that qemu fix would not need this
1958 * kvm hack.
1959 */
1960 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1961 ar |= 0x1; /* Accessed */
1962
6aa8b732
AK		 1963 vmcs_write32(sf->ar_bytes, ar);
1964}
1965
6aa8b732
AK		 1966static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1967{
1968 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1969
1970 *db = (ar >> 14) & 1;
1971 *l = (ar >> 13) & 1;
1972}
1973
89a27f4d 1974static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1975{
89a27f4d
GN		 1976 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
1977 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 1978}
1979
89a27f4d 1980static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1981{
89a27f4d
GN		 1982 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
1983 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 1984}
1985
89a27f4d 1986static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1987{
89a27f4d
GN		 1988 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
1989 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 1990}
1991
89a27f4d 1992static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 1993{
89a27f4d
GN		 1994 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
1995 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 1996}
1997
648dfaa7
MG		 1998static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1999{
2000 struct kvm_segment var;
2001 u32 ar;
2002
2003 vmx_get_segment(vcpu, &var, seg);
2004 ar = vmx_segment_access_rights(&var);
2005
2006 if (var.base != (var.selector << 4))
2007 return false;
2008 if (var.limit != 0xffff)
2009 return false;
2010 if (ar != 0xf3)
2011 return false;
2012
2013 return true;
2014}
2015
2016static bool code_segment_valid(struct kvm_vcpu *vcpu)
2017{
2018 struct kvm_segment cs;
2019 unsigned int cs_rpl;
2020
2021 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2022 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2023
1872a3f4
AK		 2024 if (cs.unusable)
2025 return false;
648dfaa7
MG		 2026 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2027 return false;
2028 if (!cs.s)
2029 return false;
1872a3f4 2030 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2031 if (cs.dpl > cs_rpl)
2032 return false;
1872a3f4 2033 } else {
648dfaa7
MG		 2034 if (cs.dpl != cs_rpl)
2035 return false;
2036 }
2037 if (!cs.present)
2038 return false;
2039
2040 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2041 return true;
2042}
2043
2044static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2045{
2046 struct kvm_segment ss;
2047 unsigned int ss_rpl;
2048
2049 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2050 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2051
1872a3f4
AK		 2052 if (ss.unusable)
2053 return true;
2054 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2055 return false;
2056 if (!ss.s)
2057 return false;
2058 if (ss.dpl != ss_rpl) /* DPL != RPL */
2059 return false;
2060 if (!ss.present)
2061 return false;
2062
2063 return true;
2064}
2065
2066static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2067{
2068 struct kvm_segment var;
2069 unsigned int rpl;
2070
2071 vmx_get_segment(vcpu, &var, seg);
2072 rpl = var.selector & SELECTOR_RPL_MASK;
2073
1872a3f4
AK		 2074 if (var.unusable)
2075 return true;
648dfaa7
MG		 2076 if (!var.s)
2077 return false;
2078 if (!var.present)
2079 return false;
2080 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2081 if (var.dpl < rpl) /* DPL < RPL */
2082 return false;
2083 }
2084
2085 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2086 * rights flags
2087 */
2088 return true;
2089}
2090
2091static bool tr_valid(struct kvm_vcpu *vcpu)
2092{
2093 struct kvm_segment tr;
2094
2095 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2096
1872a3f4
AK		 2097 if (tr.unusable)
2098 return false;
648dfaa7
MG		 2099 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2100 return false;
1872a3f4 2101 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2102 return false;
2103 if (!tr.present)
2104 return false;
2105
2106 return true;
2107}
2108
2109static bool ldtr_valid(struct kvm_vcpu *vcpu)
2110{
2111 struct kvm_segment ldtr;
2112
2113 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2114
1872a3f4
AK		 2115 if (ldtr.unusable)
2116 return true;
648dfaa7
MG		 2117 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2118 return false;
2119 if (ldtr.type != 2)
2120 return false;
2121 if (!ldtr.present)
2122 return false;
2123
2124 return true;
2125}
2126
2127static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2128{
2129 struct kvm_segment cs, ss;
2130
2131 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2132 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2133
2134 return ((cs.selector & SELECTOR_RPL_MASK) ==
2135 (ss.selector & SELECTOR_RPL_MASK));
2136}
2137
2138/*
2139 * Check if guest state is valid. Returns true if valid, false if
2140 * not.
2141 * We assume that registers are always usable
2142 */
2143static bool guest_state_valid(struct kvm_vcpu *vcpu)
2144{
2145 /* real mode guest state checks */
3eeb3288 2146 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2147 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2148 return false;
2149 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2150 return false;
2151 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2152 return false;
2153 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2154 return false;
2155 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2156 return false;
2157 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2158 return false;
2159 } else {
2160 /* protected mode guest state checks */
2161 if (!cs_ss_rpl_check(vcpu))
2162 return false;
2163 if (!code_segment_valid(vcpu))
2164 return false;
2165 if (!stack_segment_valid(vcpu))
2166 return false;
2167 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2168 return false;
2169 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2170 return false;
2171 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2172 return false;
2173 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2174 return false;
2175 if (!tr_valid(vcpu))
2176 return false;
2177 if (!ldtr_valid(vcpu))
2178 return false;
2179 }
2180 /* TODO:
2181 * - Add checks on RIP
2182 * - Add checks on RFLAGS
2183 */
2184
2185 return true;
2186}
2187
d77c26fc 2188static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2189{
6aa8b732 2190 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2191 u16 data = 0;
10589a46 2192 int ret = 0;
195aefde 2193 int r;
6aa8b732 2194
195aefde
IE		 2195 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2196 if (r < 0)
10589a46 2197 goto out;
195aefde 2198 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2199 r = kvm_write_guest_page(kvm, fn++, &data,
2200 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2201 if (r < 0)
10589a46 2202 goto out;
195aefde
IE		 2203 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2204 if (r < 0)
10589a46 2205 goto out;
195aefde
IE		 2206 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2207 if (r < 0)
10589a46 2208 goto out;
195aefde 2209 data = ~0;
10589a46
MT		 2210 r = kvm_write_guest_page(kvm, fn, &data,
2211 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2212 sizeof(u8));
195aefde 2213 if (r < 0)
10589a46
MT		 2214 goto out;
2215
2216 ret = 1;
2217out:
10589a46 2218 return ret;
6aa8b732
AK		 2219}
2220
b7ebfb05
SY		 2221static int init_rmode_identity_map(struct kvm *kvm)
2222{
2223 int i, r, ret;
2224 pfn_t identity_map_pfn;
2225 u32 tmp;
2226
089d034e 2227 if (!enable_ept)
b7ebfb05
SY		 2228 return 1;
2229 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2230 printk(KERN_ERR "EPT: identity-mapping pagetable "
2231 "haven't been allocated!\n");
2232 return 0;
2233 }
2234 if (likely(kvm->arch.ept_identity_pagetable_done))
2235 return 1;
2236 ret = 0;
b927a3ce 2237 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2238 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2239 if (r < 0)
2240 goto out;
2241 /* Set up identity-mapping pagetable for EPT in real mode */
2242 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2243 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2244 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2245 r = kvm_write_guest_page(kvm, identity_map_pfn,
2246 &tmp, i * sizeof(tmp), sizeof(tmp));
2247 if (r < 0)
2248 goto out;
2249 }
2250 kvm->arch.ept_identity_pagetable_done = true;
2251 ret = 1;
2252out:
2253 return ret;
2254}
2255
6aa8b732
AK		 2256static void seg_setup(int seg)
2257{
2258 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2259 unsigned int ar;
6aa8b732
AK		 2260
2261 vmcs_write16(sf->selector, 0);
2262 vmcs_writel(sf->base, 0);
2263 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2264 if (enable_unrestricted_guest) {
2265 ar = 0x93;
2266 if (seg == VCPU_SREG_CS)
2267 ar |= 0x08; /* code segment */
2268 } else
2269 ar = 0xf3;
2270
2271 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2272}
2273
f78e0e2e
SY		 2274static int alloc_apic_access_page(struct kvm *kvm)
2275{
2276 struct kvm_userspace_memory_region kvm_userspace_mem;
2277 int r = 0;
2278
79fac95e 2279 mutex_lock(&kvm->slots_lock);
bfc6d222 2280 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2281 goto out;
2282 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2283 kvm_userspace_mem.flags = 0;
2284 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2285 kvm_userspace_mem.memory_size = PAGE_SIZE;
2286 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2287 if (r)
2288 goto out;
72dc67a6 2289
bfc6d222 2290 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2291out:
79fac95e 2292 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2293 return r;
2294}
2295
b7ebfb05
SY		 2296static int alloc_identity_pagetable(struct kvm *kvm)
2297{
2298 struct kvm_userspace_memory_region kvm_userspace_mem;
2299 int r = 0;
2300
79fac95e 2301 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2302 if (kvm->arch.ept_identity_pagetable)
2303 goto out;
2304 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2305 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2306 kvm_userspace_mem.guest_phys_addr =
2307 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2308 kvm_userspace_mem.memory_size = PAGE_SIZE;
2309 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2310 if (r)
2311 goto out;
2312
b7ebfb05 2313 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2314 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2315out:
79fac95e 2316 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2317 return r;
2318}
2319
2384d2b3
SY		 2320static void allocate_vpid(struct vcpu_vmx *vmx)
2321{
2322 int vpid;
2323
2324 vmx->vpid = 0;
919818ab 2325 if (!enable_vpid)
2384d2b3
SY		 2326 return;
2327 spin_lock(&vmx_vpid_lock);
2328 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2329 if (vpid < VMX_NR_VPIDS) {
2330 vmx->vpid = vpid;
2331 __set_bit(vpid, vmx_vpid_bitmap);
2332 }
2333 spin_unlock(&vmx_vpid_lock);
2334}
2335
5897297b 2336static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2337{
3e7c73e9 2338 int f = sizeof(unsigned long);
25c5f225
SY		 2339
2340 if (!cpu_has_vmx_msr_bitmap())
2341 return;
2342
2343 /*
2344 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2345 * have the write-low and read-high bitmap offsets the wrong way round.
2346 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2347 */
25c5f225 2348 if (msr <= 0x1fff) {
3e7c73e9
AK		 2349 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2350 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2351 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2352 msr &= 0x1fff;
3e7c73e9
AK		 2353 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2354 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2355 }
25c5f225
SY		 2356}
2357
5897297b
AK		 2358static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2359{
2360 if (!longmode_only)
2361 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2362 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2363}
2364
6aa8b732
AK		 2365/*
2366 * Sets up the vmcs for emulated real mode.
2367 */
8b9cf98c 2368static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2369{
468d472f 2370 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2371 u32 junk;
53f658b3 2372 u64 host_pat, tsc_this, tsc_base;
6aa8b732 2373 unsigned long a;
89a27f4d 2374 struct desc_ptr dt;
6aa8b732 2375 int i;
cd2276a7 2376 unsigned long kvm_vmx_return;
6e5d865c 2377 u32 exec_control;
6aa8b732 2378
6aa8b732 2379 /* I/O */
3e7c73e9
AK		 2380 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2381 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2382
25c5f225 2383 if (cpu_has_vmx_msr_bitmap())
5897297b 2384 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2385
6aa8b732
AK		 2386 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2387
6aa8b732 2388 /* Control */
1c3d14fe
YS		 2389 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2390 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2391
2392 exec_control = vmcs_config.cpu_based_exec_ctrl;
2393 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2394 exec_control &= ~CPU_BASED_TPR_SHADOW;
2395#ifdef CONFIG_X86_64
2396 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2397 CPU_BASED_CR8_LOAD_EXITING;
2398#endif
2399 }
089d034e 2400 if (!enable_ept)
d56f546d 2401 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2402 CPU_BASED_CR3_LOAD_EXITING |
2403 CPU_BASED_INVLPG_EXITING;
6e5d865c 2404 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2405
83ff3b9d
SY		 2406 if (cpu_has_secondary_exec_ctrls()) {
2407 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2408 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2409 exec_control &=
2410 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2411 if (vmx->vpid == 0)
2412 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2413 if (!enable_ept) {
d56f546d 2414 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2415 enable_unrestricted_guest = 0;
2416 }
3a624e29
NK		 2417 if (!enable_unrestricted_guest)
2418 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2419 if (!ple_gap)
2420 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2421 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2422 }
f78e0e2e 2423
4b8d54f9
ZE		 2424 if (ple_gap) {
2425 vmcs_write32(PLE_GAP, ple_gap);
2426 vmcs_write32(PLE_WINDOW, ple_window);
2427 }
2428
c7addb90
AK		 2429 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2430 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2431 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2432
2433 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2434 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2435 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2436
2437 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2438 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2439 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2440 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2441 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2442 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2443#ifdef CONFIG_X86_64
6aa8b732
AK		 2444 rdmsrl(MSR_FS_BASE, a);
2445 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2446 rdmsrl(MSR_GS_BASE, a);
2447 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2448#else
2449 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2450 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2451#endif
2452
2453 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2454
ec68798c 2455 native_store_idt(&dt);
89a27f4d 2456 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2457
d77c26fc 2458 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2459 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2460 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2461 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2462 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2463
2464 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2465 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2466 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2467 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2468 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2469 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2470
468d472f
SY		 2471 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2472 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2473 host_pat = msr_low | ((u64) msr_high << 32);
2474 vmcs_write64(HOST_IA32_PAT, host_pat);
2475 }
2476 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2477 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2478 host_pat = msr_low | ((u64) msr_high << 32);
2479 /* Write the default value follow host pat */
2480 vmcs_write64(GUEST_IA32_PAT, host_pat);
2481 /* Keep arch.pat sync with GUEST_IA32_PAT */
2482 vmx->vcpu.arch.pat = host_pat;
2483 }
2484
6aa8b732
AK		 2485 for (i = 0; i < NR_VMX_MSR; ++i) {
2486 u32 index = vmx_msr_index[i];
2487 u32 data_low, data_high;
a2fa3e9f 2488 int j = vmx->nmsrs;
6aa8b732
AK		 2489
2490 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2491 continue;
432bd6cb
AK		 2492 if (wrmsr_safe(index, data_low, data_high) < 0)
2493 continue;
26bb0981
AK		 2494 vmx->guest_msrs[j].index = i;
2495 vmx->guest_msrs[j].data = 0;
d5696725 2496 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2497 ++vmx->nmsrs;
6aa8b732 2498 }
6aa8b732 2499
1c3d14fe 2500 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2501
2502 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2503 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2504
e00c8cf2 2505 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2506 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2507 if (enable_ept)
2508 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2509 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2510
53f658b3
MT		 2511 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2512 rdtscll(tsc_this);
2513 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2514 tsc_base = tsc_this;
2515
2516 guest_write_tsc(0, tsc_base);
f78e0e2e 2517
e00c8cf2
AK		 2518 return 0;
2519}
2520
b7ebfb05
SY		 2521static int init_rmode(struct kvm *kvm)
2522{
2523 if (!init_rmode_tss(kvm))
2524 return 0;
2525 if (!init_rmode_identity_map(kvm))
2526 return 0;
2527 return 1;
2528}
2529
e00c8cf2
AK		 2530static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2531{
2532 struct vcpu_vmx *vmx = to_vmx(vcpu);
2533 u64 msr;
f656ce01 2534 int ret, idx;
e00c8cf2 2535
5fdbf976 2536 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2537 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2538 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2539 ret = -ENOMEM;
2540 goto out;
2541 }
2542
7ffd92c5 2543 vmx->rmode.vm86_active = 0;
e00c8cf2 2544
3b86cd99
JK		 2545 vmx->soft_vnmi_blocked = 0;
2546
ad312c7c 2547 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2548 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2549 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2550 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2551 msr |= MSR_IA32_APICBASE_BSP;
2552 kvm_set_apic_base(&vmx->vcpu, msr);
2553
2554 fx_init(&vmx->vcpu);
2555
5706be0d 2556 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2557 /*
2558 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2559 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2560 */
c5af89b6 2561 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2562 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2563 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2564 } else {
ad312c7c
ZX		 2565 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2566 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2567 }
e00c8cf2
AK		 2568
2569 seg_setup(VCPU_SREG_DS);
2570 seg_setup(VCPU_SREG_ES);
2571 seg_setup(VCPU_SREG_FS);
2572 seg_setup(VCPU_SREG_GS);
2573 seg_setup(VCPU_SREG_SS);
2574
2575 vmcs_write16(GUEST_TR_SELECTOR, 0);
2576 vmcs_writel(GUEST_TR_BASE, 0);
2577 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2578 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2579
2580 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2581 vmcs_writel(GUEST_LDTR_BASE, 0);
2582 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2583 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2584
2585 vmcs_write32(GUEST_SYSENTER_CS, 0);
2586 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2587 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2588
2589 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2590 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2591 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2592 else
5fdbf976
MT		 2593 kvm_rip_write(vcpu, 0);
2594 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2595
e00c8cf2
AK		 2596 vmcs_writel(GUEST_DR7, 0x400);
2597
2598 vmcs_writel(GUEST_GDTR_BASE, 0);
2599 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2600
2601 vmcs_writel(GUEST_IDTR_BASE, 0);
2602 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2603
2604 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2605 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2606 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2607
e00c8cf2
AK		 2608 /* Special registers */
2609 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2610
2611 setup_msrs(vmx);
2612
6aa8b732
AK		 2613 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2614
f78e0e2e
SY		 2615 if (cpu_has_vmx_tpr_shadow()) {
2616 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2617 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2618 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2619 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2620 vmcs_write32(TPR_THRESHOLD, 0);
2621 }
2622
2623 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2624 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2625 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2626
2384d2b3
SY		 2627 if (vmx->vpid != 0)
2628 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2629
fa40052c 2630 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2631 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2632 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2633 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2634 vmx_fpu_activate(&vmx->vcpu);
2635 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2636
2384d2b3
SY		 2637 vpid_sync_vcpu_all(vmx);
2638
3200f405 2639 ret = 0;
6aa8b732 2640
a89a8fb9
MG		 2641 /* HACK: Don't enable emulation on guest boot/reset */
2642 vmx->emulation_required = 0;
2643
6aa8b732 2644out:
f656ce01 2645 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2646 return ret;
2647}
2648
3b86cd99
JK		 2649static void enable_irq_window(struct kvm_vcpu *vcpu)
2650{
2651 u32 cpu_based_vm_exec_control;
2652
2653 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2654 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2655 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2656}
2657
2658static void enable_nmi_window(struct kvm_vcpu *vcpu)
2659{
2660 u32 cpu_based_vm_exec_control;
2661
2662 if (!cpu_has_virtual_nmis()) {
2663 enable_irq_window(vcpu);
2664 return;
2665 }
2666
2667 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2668 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2669 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2670}
2671
66fd3f7f 2672static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2673{
9c8cba37 2674 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2675 uint32_t intr;
2676 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2677
229456fc 2678 trace_kvm_inj_virq(irq);
2714d1d3 2679
fa89a817 2680 ++vcpu->stat.irq_injections;
7ffd92c5 2681 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2682 vmx->rmode.irq.pending = true;
2683 vmx->rmode.irq.vector = irq;
5fdbf976 2684 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2685 if (vcpu->arch.interrupt.soft)
2686 vmx->rmode.irq.rip +=
2687 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2688 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2689 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2690 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2691 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2692 return;
2693 }
66fd3f7f
GN		 2694 intr = irq | INTR_INFO_VALID_MASK;
2695 if (vcpu->arch.interrupt.soft) {
2696 intr |= INTR_TYPE_SOFT_INTR;
2697 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2698 vmx->vcpu.arch.event_exit_inst_len);
2699 } else
2700 intr |= INTR_TYPE_EXT_INTR;
2701 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2702}
2703
f08864b4
SY		 2704static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2705{
66a5a347
JK		 2706 struct vcpu_vmx *vmx = to_vmx(vcpu);
2707
3b86cd99
JK		 2708 if (!cpu_has_virtual_nmis()) {
2709 /*
2710 * Tracking the NMI-blocked state in software is built upon
2711 * finding the next open IRQ window. This, in turn, depends on
2712 * well-behaving guests: They have to keep IRQs disabled at
2713 * least as long as the NMI handler runs. Otherwise we may
2714 * cause NMI nesting, maybe breaking the guest. But as this is
2715 * highly unlikely, we can live with the residual risk.
2716 */
2717 vmx->soft_vnmi_blocked = 1;
2718 vmx->vnmi_blocked_time = 0;
2719 }
2720
487b391d 2721 ++vcpu->stat.nmi_injections;
7ffd92c5 2722 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2723 vmx->rmode.irq.pending = true;
2724 vmx->rmode.irq.vector = NMI_VECTOR;
2725 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2726 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2727 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2728 INTR_INFO_VALID_MASK);
2729 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2730 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2731 return;
2732 }
f08864b4
SY		 2733 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2734 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2735}
2736
c4282df9 2737static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2738{
3b86cd99 2739 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2740 return 0;
33f089ca 2741
c4282df9
GN		 2742 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2743 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2744 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2745}
2746
3cfc3092
JK		 2747static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2748{
2749 if (!cpu_has_virtual_nmis())
2750 return to_vmx(vcpu)->soft_vnmi_blocked;
2751 else
2752 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2753 GUEST_INTR_STATE_NMI);
2754}
2755
2756static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2757{
2758 struct vcpu_vmx *vmx = to_vmx(vcpu);
2759
2760 if (!cpu_has_virtual_nmis()) {
2761 if (vmx->soft_vnmi_blocked != masked) {
2762 vmx->soft_vnmi_blocked = masked;
2763 vmx->vnmi_blocked_time = 0;
2764 }
2765 } else {
2766 if (masked)
2767 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2768 GUEST_INTR_STATE_NMI);
2769 else
2770 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2771 GUEST_INTR_STATE_NMI);
2772 }
2773}
2774
78646121
GN		 2775static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2776{
c4282df9
GN		 2777 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2778 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2779 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2780}
2781
cbc94022
IE		 2782static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2783{
2784 int ret;
2785 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2786 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2787 .guest_phys_addr = addr,
2788 .memory_size = PAGE_SIZE * 3,
2789 .flags = 0,
2790 };
2791
2792 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2793 if (ret)
2794 return ret;
bfc6d222 2795 kvm->arch.tss_addr = addr;
cbc94022
IE		 2796 return 0;
2797}
2798
6aa8b732
AK		 2799static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2800 int vec, u32 err_code)
2801{
b3f37707
NK		 2802 /*
2803 * Instruction with address size override prefix opcode 0x67
2804 * Cause the #SS fault with 0 error code in VM86 mode.
2805 */
2806 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2807 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2808 return 1;
77ab6db0
JK		 2809 /*
2810 * Forward all other exceptions that are valid in real mode.
2811 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2812 * the required debugging infrastructure rework.
2813 */
2814 switch (vec) {
77ab6db0 2815 case DB_VECTOR:
d0bfb940
JK		 2816 if (vcpu->guest_debug &
2817 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2818 return 0;
2819 kvm_queue_exception(vcpu, vec);
2820 return 1;
77ab6db0 2821 case BP_VECTOR:
c573cd22
JK		 2822 /*
2823 * Update instruction length as we may reinject the exception
2824 * from user space while in guest debugging mode.
2825 */
2826 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2827 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2829 return 0;
2830 /* fall through */
2831 case DE_VECTOR:
77ab6db0
JK		 2832 case OF_VECTOR:
2833 case BR_VECTOR:
2834 case UD_VECTOR:
2835 case DF_VECTOR:
2836 case SS_VECTOR:
2837 case GP_VECTOR:
2838 case MF_VECTOR:
2839 kvm_queue_exception(vcpu, vec);
2840 return 1;
2841 }
6aa8b732
AK		 2842 return 0;
2843}
2844
a0861c02
AK		 2845/*
2846 * Trigger machine check on the host. We assume all the MSRs are already set up
2847 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2848 * We pass a fake environment to the machine check handler because we want
2849 * the guest to be always treated like user space, no matter what context
2850 * it used internally.
2851 */
2852static void kvm_machine_check(void)
2853{
2854#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2855 struct pt_regs regs = {
2856 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2857 .flags = X86_EFLAGS_IF,
2858 };
2859
2860 do_machine_check(&regs, 0);
2861#endif
2862}
2863
851ba692 2864static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2865{
2866 /* already handled by vcpu_run */
2867 return 1;
2868}
2869
851ba692 2870static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2871{
1155f76a 2872 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2873 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2874 u32 intr_info, ex_no, error_code;
42dbaa5a 2875 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2876 u32 vect_info;
2877 enum emulation_result er;
2878
1155f76a 2879 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2880 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2881
a0861c02 2882 if (is_machine_check(intr_info))
851ba692 2883 return handle_machine_check(vcpu);
a0861c02 2884
6aa8b732 2885 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2886 !is_page_fault(intr_info)) {
2887 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2888 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2889 vcpu->run->internal.ndata = 2;
2890 vcpu->run->internal.data[0] = vect_info;
2891 vcpu->run->internal.data[1] = intr_info;
2892 return 0;
2893 }
6aa8b732 2894
e4a41889 2895 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2896 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2897
2898 if (is_no_device(intr_info)) {
5fd86fcf 2899 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2900 return 1;
2901 }
2902
7aa81cc0 2903 if (is_invalid_opcode(intr_info)) {
851ba692 2904 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2905 if (er != EMULATE_DONE)
7ee5d940 2906 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2907 return 1;
2908 }
2909
6aa8b732 2910 error_code = 0;
5fdbf976 2911 rip = kvm_rip_read(vcpu);
2e11384c 2912 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2913 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2914 if (is_page_fault(intr_info)) {
1439442c 2915 /* EPT won't cause page fault directly */
089d034e 2916 if (enable_ept)
1439442c 2917 BUG();
6aa8b732 2918 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2919 trace_kvm_page_fault(cr2, error_code);
2920
3298b75c 2921 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2922 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2923 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2924 }
2925
7ffd92c5 2926 if (vmx->rmode.vm86_active &&
6aa8b732 2927 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2928 error_code)) {
ad312c7c
ZX		 2929 if (vcpu->arch.halt_request) {
2930 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2931 return kvm_emulate_halt(vcpu);
2932 }
6aa8b732 2933 return 1;
72d6e5a0 2934 }
6aa8b732 2935
d0bfb940 2936 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2937 switch (ex_no) {
2938 case DB_VECTOR:
2939 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2940 if (!(vcpu->guest_debug &
2941 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2942 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2943 kvm_queue_exception(vcpu, DB_VECTOR);
2944 return 1;
2945 }
2946 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2947 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2948 /* fall through */
2949 case BP_VECTOR:
c573cd22
JK		 2950 /*
2951 * Update instruction length as we may reinject #BP from
2952 * user space while in guest debugging mode. Reading it for
2953 * #DB as well causes no harm, it is not used in that case.
2954 */
2955 vmx->vcpu.arch.event_exit_inst_len =
2956 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 2957 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2958 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2959 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2960 break;
2961 default:
d0bfb940
JK		 2962 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2963 kvm_run->ex.exception = ex_no;
2964 kvm_run->ex.error_code = error_code;
42dbaa5a 2965 break;
6aa8b732 2966 }
6aa8b732
AK		 2967 return 0;
2968}
2969
851ba692 2970static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2971{
1165f5fe 2972 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2973 return 1;
2974}
2975
851ba692 2976static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2977{
851ba692 2978 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2979 return 0;
2980}
6aa8b732 2981
851ba692 2982static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2983{
bfdaab09 2984 unsigned long exit_qualification;
34c33d16 2985 int size, in, string;
039576c0 2986 unsigned port;
6aa8b732 2987
bfdaab09 2988 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2989 string = (exit_qualification & 16) != 0;
cf8f70bf 2990 in = (exit_qualification & 8) != 0;
e70669ab 2991
cf8f70bf 2992 ++vcpu->stat.io_exits;
e70669ab 2993
cf8f70bf
GN		 2994 if (string || in)
2995 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
e70669ab 2996
cf8f70bf
GN		 2997 port = exit_qualification >> 16;
2998 size = (exit_qualification & 7) + 1;
e93f36bc 2999 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3000
3001 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3002}
3003
102d8325
IM		 3004static void
3005vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3006{
3007 /*
3008 * Patch in the VMCALL instruction:
3009 */
3010 hypercall[0] = 0x0f;
3011 hypercall[1] = 0x01;
3012 hypercall[2] = 0xc1;
102d8325
IM		 3013}
3014
851ba692 3015static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3016{
229456fc 3017 unsigned long exit_qualification, val;
6aa8b732
AK		 3018 int cr;
3019 int reg;
3020
bfdaab09 3021 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3022 cr = exit_qualification & 15;
3023 reg = (exit_qualification >> 8) & 15;
3024 switch ((exit_qualification >> 4) & 3) {
3025 case 0: /* mov to cr */
229456fc
MT		 3026 val = kvm_register_read(vcpu, reg);
3027 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3028 switch (cr) {
3029 case 0:
229456fc 3030 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 3031 skip_emulated_instruction(vcpu);
3032 return 1;
3033 case 3:
229456fc 3034 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3035 skip_emulated_instruction(vcpu);
3036 return 1;
3037 case 4:
229456fc 3038 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3039 skip_emulated_instruction(vcpu);
3040 return 1;
0a5fff19
GN		 3041 case 8: {
3042 u8 cr8_prev = kvm_get_cr8(vcpu);
3043 u8 cr8 = kvm_register_read(vcpu, reg);
3044 kvm_set_cr8(vcpu, cr8);
3045 skip_emulated_instruction(vcpu);
3046 if (irqchip_in_kernel(vcpu->kvm))
3047 return 1;
3048 if (cr8_prev <= cr8)
3049 return 1;
851ba692 3050 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3051 return 0;
3052 }
6aa8b732
AK		 3053 };
3054 break;
25c4c276 3055 case 2: /* clts */
edcafe3c 3056 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3057 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3058 skip_emulated_instruction(vcpu);
6b52d186 3059 vmx_fpu_activate(vcpu);
25c4c276 3060 return 1;
6aa8b732
AK		 3061 case 1: /*mov from cr*/
3062 switch (cr) {
3063 case 3:
5fdbf976 3064 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3065 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3066 skip_emulated_instruction(vcpu);
3067 return 1;
3068 case 8:
229456fc
MT		 3069 val = kvm_get_cr8(vcpu);
3070 kvm_register_write(vcpu, reg, val);
3071 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3072 skip_emulated_instruction(vcpu);
3073 return 1;
3074 }
3075 break;
3076 case 3: /* lmsw */
a1f83a74 3077 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3078 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3079 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3080
3081 skip_emulated_instruction(vcpu);
3082 return 1;
3083 default:
3084 break;
3085 }
851ba692 3086 vcpu->run->exit_reason = 0;
f0242478 3087 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3088 (int)(exit_qualification >> 4) & 3, cr);
3089 return 0;
3090}
3091
851ba692 3092static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3093{
bfdaab09 3094 unsigned long exit_qualification;
6aa8b732
AK		 3095 int dr, reg;
3096
f2483415 3097 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3098 if (!kvm_require_cpl(vcpu, 0))
3099 return 1;
42dbaa5a
JK		 3100 dr = vmcs_readl(GUEST_DR7);
3101 if (dr & DR7_GD) {
3102 /*
3103 * As the vm-exit takes precedence over the debug trap, we
3104 * need to emulate the latter, either for the host or the
3105 * guest debugging itself.
3106 */
3107 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3108 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3109 vcpu->run->debug.arch.dr7 = dr;
3110 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3111 vmcs_readl(GUEST_CS_BASE) +
3112 vmcs_readl(GUEST_RIP);
851ba692
AK		 3113 vcpu->run->debug.arch.exception = DB_VECTOR;
3114 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3115 return 0;
3116 } else {
3117 vcpu->arch.dr7 &= ~DR7_GD;
3118 vcpu->arch.dr6 |= DR6_BD;
3119 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3120 kvm_queue_exception(vcpu, DB_VECTOR);
3121 return 1;
3122 }
3123 }
3124
bfdaab09 3125 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3126 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3127 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3128 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3129 unsigned long val;
3130 if (!kvm_get_dr(vcpu, dr, &val))
3131 kvm_register_write(vcpu, reg, val);
3132 } else
3133 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3134 skip_emulated_instruction(vcpu);
3135 return 1;
3136}
3137
020df079
GN		 3138static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3139{
3140 vmcs_writel(GUEST_DR7, val);
3141}
3142
851ba692 3143static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3144{
06465c5a
AK		 3145 kvm_emulate_cpuid(vcpu);
3146 return 1;
6aa8b732
AK		 3147}
3148
851ba692 3149static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3150{
ad312c7c 3151 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3152 u64 data;
3153
3154 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3155 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3156 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3157 return 1;
3158 }
3159
229456fc 3160 trace_kvm_msr_read(ecx, data);
2714d1d3 3161
6aa8b732 3162 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3163 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3164 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3165 skip_emulated_instruction(vcpu);
3166 return 1;
3167}
3168
851ba692 3169static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3170{
ad312c7c
ZX		 3171 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3172 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3173 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3174
3175 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3176 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3177 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3178 return 1;
3179 }
3180
59200273 3181 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3182 skip_emulated_instruction(vcpu);
3183 return 1;
3184}
3185
851ba692 3186static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3187{
3188 return 1;
3189}
3190
851ba692 3191static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3192{
85f455f7
ED		 3193 u32 cpu_based_vm_exec_control;
3194
3195 /* clear pending irq */
3196 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3197 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3198 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3199
a26bf12a 3200 ++vcpu->stat.irq_window_exits;
2714d1d3 3201
c1150d8c
DL		 3202 /*
3203 * If the user space waits to inject interrupts, exit as soon as
3204 * possible
3205 */
8061823a 3206 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3207 vcpu->run->request_interrupt_window &&
8061823a 3208 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3209 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3210 return 0;
3211 }
6aa8b732
AK		 3212 return 1;
3213}
3214
851ba692 3215static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3216{
3217 skip_emulated_instruction(vcpu);
d3bef15f 3218 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3219}
3220
851ba692 3221static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3222{
510043da 3223 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3224 kvm_emulate_hypercall(vcpu);
3225 return 1;
c21415e8
IM		 3226}
3227
851ba692 3228static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3229{
3230 kvm_queue_exception(vcpu, UD_VECTOR);
3231 return 1;
3232}
3233
851ba692 3234static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3235{
f9c617f6 3236 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3237
3238 kvm_mmu_invlpg(vcpu, exit_qualification);
3239 skip_emulated_instruction(vcpu);
3240 return 1;
3241}
3242
851ba692 3243static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3244{
3245 skip_emulated_instruction(vcpu);
3246 /* TODO: Add support for VT-d/pass-through device */
3247 return 1;
3248}
3249
851ba692 3250static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3251{
f9c617f6 3252 unsigned long exit_qualification;
f78e0e2e
SY		 3253 enum emulation_result er;
3254 unsigned long offset;
3255
f9c617f6 3256 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3257 offset = exit_qualification & 0xffful;
3258
851ba692 3259 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3260
3261 if (er != EMULATE_DONE) {
3262 printk(KERN_ERR
3263 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3264 offset);
7f582ab6 3265 return -ENOEXEC;
f78e0e2e
SY		 3266 }
3267 return 1;
3268}
3269
851ba692 3270static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3271{
60637aac 3272 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3273 unsigned long exit_qualification;
e269fb21
JK		 3274 bool has_error_code = false;
3275 u32 error_code = 0;
37817f29 3276 u16 tss_selector;
64a7ec06
GN		 3277 int reason, type, idt_v;
3278
3279 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3280 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3281
3282 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3283
3284 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3285 if (reason == TASK_SWITCH_GATE && idt_v) {
3286 switch (type) {
3287 case INTR_TYPE_NMI_INTR:
3288 vcpu->arch.nmi_injected = false;
3289 if (cpu_has_virtual_nmis())
3290 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3291 GUEST_INTR_STATE_NMI);
3292 break;
3293 case INTR_TYPE_EXT_INTR:
66fd3f7f 3294 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3295 kvm_clear_interrupt_queue(vcpu);
3296 break;
3297 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3298 if (vmx->idt_vectoring_info &
3299 VECTORING_INFO_DELIVER_CODE_MASK) {
3300 has_error_code = true;
3301 error_code =
3302 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3303 }
3304 /* fall through */
64a7ec06
GN		 3305 case INTR_TYPE_SOFT_EXCEPTION:
3306 kvm_clear_exception_queue(vcpu);
3307 break;
3308 default:
3309 break;
3310 }
60637aac 3311 }
37817f29
IE		 3312 tss_selector = exit_qualification;
3313
64a7ec06
GN		 3314 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3315 type != INTR_TYPE_EXT_INTR &&
3316 type != INTR_TYPE_NMI_INTR))
3317 skip_emulated_instruction(vcpu);
3318
acb54517
GN		 3319 if (kvm_task_switch(vcpu, tss_selector, reason,
3320 has_error_code, error_code) == EMULATE_FAIL) {
3321 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3322 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3323 vcpu->run->internal.ndata = 0;
42dbaa5a 3324 return 0;
acb54517 3325 }
42dbaa5a
JK		 3326
3327 /* clear all local breakpoint enable flags */
3328 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3329
3330 /*
3331 * TODO: What about debug traps on tss switch?
3332 * Are we supposed to inject them and update dr6?
3333 */
3334
3335 return 1;
37817f29
IE		 3336}
3337
851ba692 3338static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3339{
f9c617f6 3340 unsigned long exit_qualification;
1439442c 3341 gpa_t gpa;
1439442c 3342 int gla_validity;
1439442c 3343
f9c617f6 3344 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3345
3346 if (exit_qualification & (1 << 6)) {
3347 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3348 return -EINVAL;
1439442c
SY		 3349 }
3350
3351 gla_validity = (exit_qualification >> 7) & 0x3;
3352 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3353 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3354 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3355 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3356 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3357 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3358 (long unsigned int)exit_qualification);
851ba692
AK		 3359 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3360 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3361 return 0;
1439442c
SY		 3362 }
3363
3364 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3365 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3366 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3367}
3368
68f89400
MT		 3369static u64 ept_rsvd_mask(u64 spte, int level)
3370{
3371 int i;
3372 u64 mask = 0;
3373
3374 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3375 mask |= (1ULL << i);
3376
3377 if (level > 2)
3378 /* bits 7:3 reserved */
3379 mask |= 0xf8;
3380 else if (level == 2) {
3381 if (spte & (1ULL << 7))
3382 /* 2MB ref, bits 20:12 reserved */
3383 mask |= 0x1ff000;
3384 else
3385 /* bits 6:3 reserved */
3386 mask |= 0x78;
3387 }
3388
3389 return mask;
3390}
3391
3392static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3393 int level)
3394{
3395 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3396
3397 /* 010b (write-only) */
3398 WARN_ON((spte & 0x7) == 0x2);
3399
3400 /* 110b (write/execute) */
3401 WARN_ON((spte & 0x7) == 0x6);
3402
3403 /* 100b (execute-only) and value not supported by logical processor */
3404 if (!cpu_has_vmx_ept_execute_only())
3405 WARN_ON((spte & 0x7) == 0x4);
3406
3407 /* not 000b */
3408 if ((spte & 0x7)) {
3409 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3410
3411 if (rsvd_bits != 0) {
3412 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3413 __func__, rsvd_bits);
3414 WARN_ON(1);
3415 }
3416
3417 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3418 u64 ept_mem_type = (spte & 0x38) >> 3;
3419
3420 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3421 ept_mem_type == 7) {
3422 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3423 __func__, ept_mem_type);
3424 WARN_ON(1);
3425 }
3426 }
3427 }
3428}
3429
851ba692 3430static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3431{
3432 u64 sptes[4];
3433 int nr_sptes, i;
3434 gpa_t gpa;
3435
3436 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3437
3438 printk(KERN_ERR "EPT: Misconfiguration.\n");
3439 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3440
3441 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3442
3443 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3444 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3445
851ba692
AK		 3446 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3447 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3448
3449 return 0;
3450}
3451
851ba692 3452static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3453{
3454 u32 cpu_based_vm_exec_control;
3455
3456 /* clear pending NMI */
3457 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3458 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3459 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3460 ++vcpu->stat.nmi_window_exits;
3461
3462 return 1;
3463}
3464
80ced186 3465static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3466{
8b3079a5
AK		 3467 struct vcpu_vmx *vmx = to_vmx(vcpu);
3468 enum emulation_result err = EMULATE_DONE;
80ced186 3469 int ret = 1;
ea953ef0
MG		 3470
3471 while (!guest_state_valid(vcpu)) {
851ba692 3472 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3473
80ced186
MG		 3474 if (err == EMULATE_DO_MMIO) {
3475 ret = 0;
3476 goto out;
3477 }
1d5a4d9b
GT		 3478
3479 if (err != EMULATE_DONE) {
80ced186
MG		 3480 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3481 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3482 vcpu->run->internal.ndata = 0;
80ced186
MG		 3483 ret = 0;
3484 goto out;
ea953ef0
MG		 3485 }
3486
3487 if (signal_pending(current))
80ced186 3488 goto out;
ea953ef0
MG		 3489 if (need_resched())
3490 schedule();
3491 }
3492
80ced186
MG		 3493 vmx->emulation_required = 0;
3494out:
3495 return ret;
ea953ef0
MG		 3496}
3497
4b8d54f9
ZE		 3498/*
3499 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3500 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3501 */
9fb41ba8 3502static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3503{
3504 skip_emulated_instruction(vcpu);
3505 kvm_vcpu_on_spin(vcpu);
3506
3507 return 1;
3508}
3509
59708670
SY		 3510static int handle_invalid_op(struct kvm_vcpu *vcpu)
3511{
3512 kvm_queue_exception(vcpu, UD_VECTOR);
3513 return 1;
3514}
3515
6aa8b732
AK		 3516/*
3517 * The exit handlers return 1 if the exit was handled fully and guest execution
3518 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3519 * to be done to userspace and return 0.
3520 */
851ba692 3521static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3522 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3523 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3524 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3525 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3526 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3527 [EXIT_REASON_CR_ACCESS] = handle_cr,
3528 [EXIT_REASON_DR_ACCESS] = handle_dr,
3529 [EXIT_REASON_CPUID] = handle_cpuid,
3530 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3531 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3532 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3533 [EXIT_REASON_HLT] = handle_halt,
a7052897 3534 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3535 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3536 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3537 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3538 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3539 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3540 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3541 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3542 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3543 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3544 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3545 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3546 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3547 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3548 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3549 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3550 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3551 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3552 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3553 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3554 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3555};
3556
3557static const int kvm_vmx_max_exit_handlers =
50a3485c 3558 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3559
3560/*
3561 * The guest has exited. See if we can fix it or if we need userspace
3562 * assistance.
3563 */
851ba692 3564static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3565{
29bd8a78 3566 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3567 u32 exit_reason = vmx->exit_reason;
1155f76a 3568 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3569
5bfd8b54 3570 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3571
80ced186
MG		 3572 /* If guest state is invalid, start emulating */
3573 if (vmx->emulation_required && emulate_invalid_guest_state)
3574 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3575
1439442c
SY		 3576 /* Access CR3 don't cause VMExit in paging mode, so we need
3577 * to sync with guest real CR3. */
6de4f3ad 3578 if (enable_ept && is_paging(vcpu))
1439442c 3579 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3580
29bd8a78 3581 if (unlikely(vmx->fail)) {
851ba692
AK		 3582 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3583 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3584 = vmcs_read32(VM_INSTRUCTION_ERROR);
3585 return 0;
3586 }
6aa8b732 3587
d77c26fc 3588 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3589 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3590 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3591 exit_reason != EXIT_REASON_TASK_SWITCH))
3592 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3593 "(0x%x) and exit reason is 0x%x\n",
3594 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3595
3596 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3597 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3598 vmx->soft_vnmi_blocked = 0;
3b86cd99 3599 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3600 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3601 /*
3602 * This CPU don't support us in finding the end of an
3603 * NMI-blocked window if the guest runs with IRQs
3604 * disabled. So we pull the trigger after 1 s of
3605 * futile waiting, but inform the user about this.
3606 */
3607 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3608 "state on VCPU %d after 1 s timeout\n",
3609 __func__, vcpu->vcpu_id);
3610 vmx->soft_vnmi_blocked = 0;
3b86cd99 3611 }
3b86cd99
JK		 3612 }
3613
6aa8b732
AK		 3614 if (exit_reason < kvm_vmx_max_exit_handlers
3615 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3616 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3617 else {
851ba692
AK		 3618 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3619 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3620 }
3621 return 0;
3622}
3623
95ba8273 3624static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3625{
95ba8273 3626 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3627 vmcs_write32(TPR_THRESHOLD, 0);
3628 return;
3629 }
3630
95ba8273 3631 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3632}
3633
cf393f75
AK		 3634static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3635{
3636 u32 exit_intr_info;
7b4a25cb 3637 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3638 bool unblock_nmi;
3639 u8 vector;
668f612f
AK		 3640 int type;
3641 bool idtv_info_valid;
cf393f75
AK		 3642
3643 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3644
a0861c02
AK		 3645 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3646
3647 /* Handle machine checks before interrupts are enabled */
3648 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3649 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3650 && is_machine_check(exit_intr_info)))
3651 kvm_machine_check();
3652
20f65983
GN		 3653 /* We need to handle NMIs before interrupts are enabled */
3654 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3655 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3656 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3657 asm("int $2");
ff9d07a0
ZY		 3658 kvm_after_handle_nmi(&vmx->vcpu);
3659 }
20f65983
GN		 3660
3661 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3662
cf393f75
AK		 3663 if (cpu_has_virtual_nmis()) {
3664 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3665 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3666 /*
7b4a25cb 3667 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3668 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3669 * a guest IRET fault.
7b4a25cb
GN		 3670 * SDM 3: 23.2.2 (September 2008)
3671 * Bit 12 is undefined in any of the following cases:
3672 * If the VM exit sets the valid bit in the IDT-vectoring
3673 * information field.
3674 * If the VM exit is due to a double fault.
cf393f75 3675 */
7b4a25cb
GN		 3676 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3677 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3678 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3679 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3680 } else if (unlikely(vmx->soft_vnmi_blocked))
3681 vmx->vnmi_blocked_time +=
3682 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3683
37b96e98
GN		 3684 vmx->vcpu.arch.nmi_injected = false;
3685 kvm_clear_exception_queue(&vmx->vcpu);
3686 kvm_clear_interrupt_queue(&vmx->vcpu);
3687
3688 if (!idtv_info_valid)
3689 return;
3690
668f612f
AK		 3691 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3692 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3693
64a7ec06 3694 switch (type) {
37b96e98
GN		 3695 case INTR_TYPE_NMI_INTR:
3696 vmx->vcpu.arch.nmi_injected = true;
668f612f 3697 /*
7b4a25cb 3698 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3699 * Clear bit "block by NMI" before VM entry if a NMI
3700 * delivery faulted.
668f612f 3701 */
37b96e98
GN		 3702 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3703 GUEST_INTR_STATE_NMI);
3704 break;
37b96e98 3705 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3706 vmx->vcpu.arch.event_exit_inst_len =
3707 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3708 /* fall through */
3709 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3710 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3711 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3712 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3713 } else
3714 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3715 break;
66fd3f7f
GN		 3716 case INTR_TYPE_SOFT_INTR:
3717 vmx->vcpu.arch.event_exit_inst_len =
3718 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3719 /* fall through */
37b96e98 3720 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3721 kvm_queue_interrupt(&vmx->vcpu, vector,
3722 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3723 break;
3724 default:
3725 break;
f7d9238f 3726 }
cf393f75
AK		 3727}
3728
9c8cba37
AK		 3729/*
3730 * Failure to inject an interrupt should give us the information
3731 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3732 * when fetching the interrupt redirection bitmap in the real-mode
3733 * tss, this doesn't happen. So we do it ourselves.
3734 */
3735static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3736{
3737 vmx->rmode.irq.pending = 0;
5fdbf976 3738 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3739 return;
5fdbf976 3740 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3741 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3742 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3743 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3744 return;
3745 }
3746 vmx->idt_vectoring_info =
3747 VECTORING_INFO_VALID_MASK
3748 | INTR_TYPE_EXT_INTR
3749 | vmx->rmode.irq.vector;
3750}
3751
c801949d
AK		 3752#ifdef CONFIG_X86_64
3753#define R "r"
3754#define Q "q"
3755#else
3756#define R "e"
3757#define Q "l"
3758#endif
3759
851ba692 3760static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3761{
a2fa3e9f 3762 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3763
3b86cd99
JK		 3764 /* Record the guest's net vcpu time for enforced NMI injections. */
3765 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3766 vmx->entry_time = ktime_get();
3767
80ced186
MG		 3768 /* Don't enter VMX if guest state is invalid, let the exit handler
3769 start emulation until we arrive back to a valid state */
3770 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3771 return;
a89a8fb9 3772
5fdbf976
MT		 3773 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3774 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3775 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3776 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3777
787ff736
GN		 3778 /* When single-stepping over STI and MOV SS, we must clear the
3779 * corresponding interruptibility bits in the guest state. Otherwise
3780 * vmentry fails as it then expects bit 14 (BS) in pending debug
3781 * exceptions being set, but that's not correct for the guest debugging
3782 * case. */
3783 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3784 vmx_set_interrupt_shadow(vcpu, 0);
3785
e6adf283
AK		 3786 /*
3787 * Loading guest fpu may have cleared host cr0.ts
3788 */
3789 vmcs_writel(HOST_CR0, read_cr0());
3790
d77c26fc 3791 asm(
6aa8b732 3792 /* Store host registers */
c801949d
AK		 3793 "push %%"R"dx; push %%"R"bp;"
3794 "push %%"R"cx \n\t"
313dbd49
AK		 3795 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3796 "je 1f \n\t"
3797 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3798 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3799 "1: \n\t"
d3edefc0
AK		 3800 /* Reload cr2 if changed */
3801 "mov %c[cr2](%0), %%"R"ax \n\t"
3802 "mov %%cr2, %%"R"dx \n\t"
3803 "cmp %%"R"ax, %%"R"dx \n\t"
3804 "je 2f \n\t"
3805 "mov %%"R"ax, %%cr2 \n\t"
3806 "2: \n\t"
6aa8b732 3807 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3808 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3809 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3810 "mov %c[rax](%0), %%"R"ax \n\t"
3811 "mov %c[rbx](%0), %%"R"bx \n\t"
3812 "mov %c[rdx](%0), %%"R"dx \n\t"
3813 "mov %c[rsi](%0), %%"R"si \n\t"
3814 "mov %c[rdi](%0), %%"R"di \n\t"
3815 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3816#ifdef CONFIG_X86_64
e08aa78a
AK		 3817 "mov %c[r8](%0), %%r8 \n\t"
3818 "mov %c[r9](%0), %%r9 \n\t"
3819 "mov %c[r10](%0), %%r10 \n\t"
3820 "mov %c[r11](%0), %%r11 \n\t"
3821 "mov %c[r12](%0), %%r12 \n\t"
3822 "mov %c[r13](%0), %%r13 \n\t"
3823 "mov %c[r14](%0), %%r14 \n\t"
3824 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3825#endif
c801949d
AK		 3826 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3827
6aa8b732 3828 /* Enter guest mode */
cd2276a7 3829 "jne .Llaunched \n\t"
4ecac3fd 3830 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3831 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3832 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3833 ".Lkvm_vmx_return: "
6aa8b732 3834 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3835 "xchg %0, (%%"R"sp) \n\t"
3836 "mov %%"R"ax, %c[rax](%0) \n\t"
3837 "mov %%"R"bx, %c[rbx](%0) \n\t"
3838 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3839 "mov %%"R"dx, %c[rdx](%0) \n\t"
3840 "mov %%"R"si, %c[rsi](%0) \n\t"
3841 "mov %%"R"di, %c[rdi](%0) \n\t"
3842 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3843#ifdef CONFIG_X86_64
e08aa78a
AK		 3844 "mov %%r8, %c[r8](%0) \n\t"
3845 "mov %%r9, %c[r9](%0) \n\t"
3846 "mov %%r10, %c[r10](%0) \n\t"
3847 "mov %%r11, %c[r11](%0) \n\t"
3848 "mov %%r12, %c[r12](%0) \n\t"
3849 "mov %%r13, %c[r13](%0) \n\t"
3850 "mov %%r14, %c[r14](%0) \n\t"
3851 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3852#endif
c801949d
AK		 3853 "mov %%cr2, %%"R"ax \n\t"
3854 "mov %%"R"ax, %c[cr2](%0) \n\t"
3855
3856 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3857 "setbe %c[fail](%0) \n\t"
3858 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3859 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3860 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3861 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3862 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3863 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3864 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3865 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3866 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3867 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3868 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3869#ifdef CONFIG_X86_64
ad312c7c
ZX		 3870 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3871 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3872 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3873 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3874 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3875 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3876 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3877 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3878#endif
ad312c7c 3879 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3880 : "cc", "memory"
c801949d 3881 , R"bx", R"di", R"si"
c2036300 3882#ifdef CONFIG_X86_64
c2036300
LV		 3883 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3884#endif
3885 );
6aa8b732 3886
6de4f3ad
AK		 3887 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3888 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3889 vcpu->arch.regs_dirty = 0;
3890
1155f76a 3891 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3892 if (vmx->rmode.irq.pending)
3893 fixup_rmode_irq(vmx);
1155f76a 3894
d77c26fc 3895 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3896 vmx->launched = 1;
1b6269db 3897
cf393f75 3898 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3899}
3900
c801949d
AK		 3901#undef R
3902#undef Q
3903
6aa8b732
AK		 3904static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3905{
a2fa3e9f
GH		 3906 struct vcpu_vmx *vmx = to_vmx(vcpu);
3907
3908 if (vmx->vmcs) {
543e4243 3909 vcpu_clear(vmx);
a2fa3e9f
GH		 3910 free_vmcs(vmx->vmcs);
3911 vmx->vmcs = NULL;
6aa8b732
AK		 3912 }
3913}
3914
3915static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3916{
fb3f0f51
RR		 3917 struct vcpu_vmx *vmx = to_vmx(vcpu);
3918
2384d2b3
SY		 3919 spin_lock(&vmx_vpid_lock);
3920 if (vmx->vpid != 0)
3921 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3922 spin_unlock(&vmx_vpid_lock);
6aa8b732 3923 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3924 kfree(vmx->guest_msrs);
3925 kvm_vcpu_uninit(vcpu);
a4770347 3926 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3927}
3928
fb3f0f51 3929static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3930{
fb3f0f51 3931 int err;
c16f862d 3932 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3933 int cpu;
6aa8b732 3934
a2fa3e9f 3935 if (!vmx)
fb3f0f51
RR		 3936 return ERR_PTR(-ENOMEM);
3937
2384d2b3
SY		 3938 allocate_vpid(vmx);
3939
fb3f0f51
RR		 3940 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3941 if (err)
3942 goto free_vcpu;
965b58a5 3943
a2fa3e9f 3944 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3945 if (!vmx->guest_msrs) {
3946 err = -ENOMEM;
3947 goto uninit_vcpu;
3948 }
965b58a5 3949
a2fa3e9f
GH		 3950 vmx->vmcs = alloc_vmcs();
3951 if (!vmx->vmcs)
fb3f0f51 3952 goto free_msrs;
a2fa3e9f
GH		 3953
3954 vmcs_clear(vmx->vmcs);
3955
15ad7146
AK		 3956 cpu = get_cpu();
3957 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3958 err = vmx_vcpu_setup(vmx);
fb3f0f51 3959 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3960 put_cpu();
fb3f0f51
RR		 3961 if (err)
3962 goto free_vmcs;
5e4a0b3c
MT		 3963 if (vm_need_virtualize_apic_accesses(kvm))
3964 if (alloc_apic_access_page(kvm) != 0)
3965 goto free_vmcs;
fb3f0f51 3966
b927a3ce
SY		 3967 if (enable_ept) {
3968 if (!kvm->arch.ept_identity_map_addr)
3969 kvm->arch.ept_identity_map_addr =
3970 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3971 if (alloc_identity_pagetable(kvm) != 0)
3972 goto free_vmcs;
b927a3ce 3973 }
b7ebfb05 3974
fb3f0f51
RR		 3975 return &vmx->vcpu;
3976
3977free_vmcs:
3978 free_vmcs(vmx->vmcs);
3979free_msrs:
fb3f0f51
RR		 3980 kfree(vmx->guest_msrs);
3981uninit_vcpu:
3982 kvm_vcpu_uninit(&vmx->vcpu);
3983free_vcpu:
a4770347 3984 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3985 return ERR_PTR(err);
6aa8b732
AK		 3986}
3987
002c7f7c
YS		 3988static void __init vmx_check_processor_compat(void *rtn)
3989{
3990 struct vmcs_config vmcs_conf;
3991
3992 *(int *)rtn = 0;
3993 if (setup_vmcs_config(&vmcs_conf) < 0)
3994 *(int *)rtn = -EIO;
3995 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3996 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3997 smp_processor_id());
3998 *(int *)rtn = -EIO;
3999 }
4000}
4001
67253af5
SY		 4002static int get_ept_level(void)
4003{
4004 return VMX_EPT_DEFAULT_GAW + 1;
4005}
4006
4b12f0de 4007static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4008{
4b12f0de
SY		 4009 u64 ret;
4010
522c68c4
SY		 4011 /* For VT-d and EPT combination
4012 * 1. MMIO: always map as UC
4013 * 2. EPT with VT-d:
4014 * a. VT-d without snooping control feature: can't guarantee the
4015 * result, try to trust guest.
4016 * b. VT-d with snooping control feature: snooping control feature of
4017 * VT-d engine can guarantee the cache correctness. Just set it
4018 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4019 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4020 * consistent with host MTRR
4021 */
4b12f0de
SY		 4022 if (is_mmio)
4023 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4024 else if (vcpu->kvm->arch.iommu_domain &&
4025 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4026 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4027 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4028 else
522c68c4 4029 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4030 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4031
4032 return ret;
64d4d521
SY		 4033}
4034
f4c9e87c
AK		 4035#define _ER(x) { EXIT_REASON_##x, #x }
4036
229456fc 4037static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4038 _ER(EXCEPTION_NMI),
4039 _ER(EXTERNAL_INTERRUPT),
4040 _ER(TRIPLE_FAULT),
4041 _ER(PENDING_INTERRUPT),
4042 _ER(NMI_WINDOW),
4043 _ER(TASK_SWITCH),
4044 _ER(CPUID),
4045 _ER(HLT),
4046 _ER(INVLPG),
4047 _ER(RDPMC),
4048 _ER(RDTSC),
4049 _ER(VMCALL),
4050 _ER(VMCLEAR),
4051 _ER(VMLAUNCH),
4052 _ER(VMPTRLD),
4053 _ER(VMPTRST),
4054 _ER(VMREAD),
4055 _ER(VMRESUME),
4056 _ER(VMWRITE),
4057 _ER(VMOFF),
4058 _ER(VMON),
4059 _ER(CR_ACCESS),
4060 _ER(DR_ACCESS),
4061 _ER(IO_INSTRUCTION),
4062 _ER(MSR_READ),
4063 _ER(MSR_WRITE),
4064 _ER(MWAIT_INSTRUCTION),
4065 _ER(MONITOR_INSTRUCTION),
4066 _ER(PAUSE_INSTRUCTION),
4067 _ER(MCE_DURING_VMENTRY),
4068 _ER(TPR_BELOW_THRESHOLD),
4069 _ER(APIC_ACCESS),
4070 _ER(EPT_VIOLATION),
4071 _ER(EPT_MISCONFIG),
4072 _ER(WBINVD),
229456fc
MT		 4073 { -1, NULL }
4074};
4075
f4c9e87c
AK		 4076#undef _ER
4077
17cc3935 4078static int vmx_get_lpage_level(void)
344f414f 4079{
878403b7
SY		 4080 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4081 return PT_DIRECTORY_LEVEL;
4082 else
4083 /* For shadow and EPT supported 1GB page */
4084 return PT_PDPE_LEVEL;
344f414f
JR		 4085}
4086
4e47c7a6
SY		 4087static inline u32 bit(int bitno)
4088{
4089 return 1 << (bitno & 31);
4090}
4091
0e851880
SY		 4092static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4093{
4e47c7a6
SY		 4094 struct kvm_cpuid_entry2 *best;
4095 struct vcpu_vmx *vmx = to_vmx(vcpu);
4096 u32 exec_control;
4097
4098 vmx->rdtscp_enabled = false;
4099 if (vmx_rdtscp_supported()) {
4100 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4101 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4102 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4103 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4104 vmx->rdtscp_enabled = true;
4105 else {
4106 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4107 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4108 exec_control);
4109 }
4110 }
4111 }
0e851880
SY		 4112}
4113
cbdd1bea 4114static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4115 .cpu_has_kvm_support = cpu_has_kvm_support,
4116 .disabled_by_bios = vmx_disabled_by_bios,
4117 .hardware_setup = hardware_setup,
4118 .hardware_unsetup = hardware_unsetup,
002c7f7c 4119 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4120 .hardware_enable = hardware_enable,
4121 .hardware_disable = hardware_disable,
04547156 4122 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4123
4124 .vcpu_create = vmx_create_vcpu,
4125 .vcpu_free = vmx_free_vcpu,
04d2cc77 4126 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4127
04d2cc77 4128 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4129 .vcpu_load = vmx_vcpu_load,
4130 .vcpu_put = vmx_vcpu_put,
4131
4132 .set_guest_debug = set_guest_debug,
4133 .get_msr = vmx_get_msr,
4134 .set_msr = vmx_set_msr,
4135 .get_segment_base = vmx_get_segment_base,
4136 .get_segment = vmx_get_segment,
4137 .set_segment = vmx_set_segment,
2e4d2653 4138 .get_cpl = vmx_get_cpl,
6aa8b732 4139 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4140 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4141 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4142 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4143 .set_cr3 = vmx_set_cr3,
4144 .set_cr4 = vmx_set_cr4,
6aa8b732 4145 .set_efer = vmx_set_efer,
6aa8b732
AK		 4146 .get_idt = vmx_get_idt,
4147 .set_idt = vmx_set_idt,
4148 .get_gdt = vmx_get_gdt,
4149 .set_gdt = vmx_set_gdt,
020df079 4150 .set_dr7 = vmx_set_dr7,
5fdbf976 4151 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4152 .get_rflags = vmx_get_rflags,
4153 .set_rflags = vmx_set_rflags,
ebcbab4c 4154 .fpu_activate = vmx_fpu_activate,
02daab21 4155 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4156
4157 .tlb_flush = vmx_flush_tlb,
6aa8b732 4158
6aa8b732 4159 .run = vmx_vcpu_run,
6062d012 4160 .handle_exit = vmx_handle_exit,
6aa8b732 4161 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4162 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4163 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4164 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4165 .set_irq = vmx_inject_irq,
95ba8273 4166 .set_nmi = vmx_inject_nmi,
298101da 4167 .queue_exception = vmx_queue_exception,
78646121 4168 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4169 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4170 .get_nmi_mask = vmx_get_nmi_mask,
4171 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4172 .enable_nmi_window = enable_nmi_window,
4173 .enable_irq_window = enable_irq_window,
4174 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4175
cbc94022 4176 .set_tss_addr = vmx_set_tss_addr,
67253af5 4177 .get_tdp_level = get_ept_level,
4b12f0de 4178 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4179
4180 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4181 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4182
4183 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4184
4185 .rdtscp_supported = vmx_rdtscp_supported,
6aa8b732
AK		 4186};
4187
4188static int __init vmx_init(void)
4189{
26bb0981
AK		 4190 int r, i;
4191
4192 rdmsrl_safe(MSR_EFER, &host_efer);
4193
4194 for (i = 0; i < NR_VMX_MSR; ++i)
4195 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4196
3e7c73e9 4197 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4198 if (!vmx_io_bitmap_a)
4199 return -ENOMEM;
4200
3e7c73e9 4201 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4202 if (!vmx_io_bitmap_b) {
4203 r = -ENOMEM;
4204 goto out;
4205 }
4206
5897297b
AK		 4207 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4208 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4209 r = -ENOMEM;
4210 goto out1;
4211 }
4212
5897297b
AK		 4213 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4214 if (!vmx_msr_bitmap_longmode) {
4215 r = -ENOMEM;
4216 goto out2;
4217 }
4218
fdef3ad1
HQ		 4219 /*
4220 * Allow direct access to the PC debug port (it is often used for I/O
4221 * delays, but the vmexits simply slow things down).
4222 */
3e7c73e9
AK		 4223 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4224 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4225
3e7c73e9 4226 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4227
5897297b
AK		 4228 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4229 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4230
2384d2b3
SY		 4231 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4232
cb498ea2 4233 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4234 if (r)
5897297b 4235 goto out3;
25c5f225 4236
5897297b
AK		 4237 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4238 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4239 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4240 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4241 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4242 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4243
089d034e 4244 if (enable_ept) {
1439442c 4245 bypass_guest_pf = 0;
5fdbcb9d 4246 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4247 VMX_EPT_WRITABLE_MASK);
534e38b4 4248 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4249 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4250 kvm_enable_tdp();
4251 } else
4252 kvm_disable_tdp();
1439442c 4253
c7addb90
AK		 4254 if (bypass_guest_pf)
4255 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4256
fdef3ad1
HQ		 4257 return 0;
4258
5897297b
AK		 4259out3:
4260 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4261out2:
5897297b 4262 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4263out1:
3e7c73e9 4264 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4265out:
3e7c73e9 4266 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4267 return r;
6aa8b732
AK		 4268}
4269
4270static void __exit vmx_exit(void)
4271{
5897297b
AK		 4272 free_page((unsigned long)vmx_msr_bitmap_legacy);
4273 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4274 free_page((unsigned long)vmx_io_bitmap_b);
4275 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4276
cb498ea2 4277 kvm_exit();
6aa8b732
AK		 4278}
4279
4280module_init(vmx_init)
4281module_exit(vmx_exit)
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