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module_param: make bool parameters really bool (core code)
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
229456fc 30#include <linux/ftrace_event.h>
5a0e3ad6 31#include <linux/slab.h>
cafd6659 32#include <linux/tboot.h>
5fdbf976 33#include "kvm_cache_regs.h"
35920a35 34#include "x86.h"
e495606d 35
6aa8b732 36#include <asm/io.h>
3b3be0d1 37#include <asm/desc.h>
13673a90 38#include <asm/vmx.h>
6210e37b 39#include <asm/virtext.h>
a0861c02 40#include <asm/mce.h>
2acf923e
DC		 41#include <asm/i387.h>
42#include <asm/xcr.h>
d7cd9796 43#include <asm/perf_event.h>
6aa8b732 44
229456fc
MT		 45#include "trace.h"
46
4ecac3fd 47#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 48#define __ex_clear(x, reg) \
49 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 50
6aa8b732
AK		 51MODULE_AUTHOR("Qumranet");
52MODULE_LICENSE("GPL");
53
4462d21a 54static int __read_mostly enable_vpid = 1;
736caefe 55module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 56
4462d21a 57static int __read_mostly flexpriority_enabled = 1;
736caefe 58module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 59
4462d21a 60static int __read_mostly enable_ept = 1;
736caefe 61module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 62
3a624e29
NK		 63static int __read_mostly enable_unrestricted_guest = 1;
64module_param_named(unrestricted_guest,
65 enable_unrestricted_guest, bool, S_IRUGO);
66
4462d21a 67static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 68module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 69
b923e62e
DX		 70static int __read_mostly vmm_exclusive = 1;
71module_param(vmm_exclusive, bool, S_IRUGO);
72
443381a8
AL		 73static int __read_mostly yield_on_hlt = 1;
74module_param(yield_on_hlt, bool, S_IRUGO);
75
58fbbf26
KT		 76static int __read_mostly fasteoi = 1;
77module_param(fasteoi, bool, S_IRUGO);
78
801d3424
NHE		 79/*
80 * If nested=1, nested virtualization is supported, i.e., guests may use
81 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
82 * use VMX instructions.
83 */
84static int __read_mostly nested = 0;
85module_param(nested, bool, S_IRUGO);
86
cdc0e244
AK		 87#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
88 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
89#define KVM_GUEST_CR0_MASK \
90 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
91#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 92 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 93#define KVM_VM_CR0_ALWAYS_ON \
94 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 95#define KVM_CR4_GUEST_OWNED_BITS \
96 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 | X86_CR4_OSXMMEXCPT)
98
cdc0e244
AK		 99#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
100#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
101
78ac8b47
AK		 102#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103
4b8d54f9
ZE		 104/*
105 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
106 * ple_gap: upper bound on the amount of time between two successive
107 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 108 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 109 * ple_window: upper bound on the amount of time a guest is allowed to execute
110 * in a PAUSE loop. Tests indicate that most spinlocks are held for
111 * less than 2^12 cycles
112 * Time is measured based on a counter that runs at the same rate as the TSC,
113 * refer SDM volume 3b section 21.6.13 & 22.1.3.
114 */
00c25bce 115#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 116#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
117static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
118module_param(ple_gap, int, S_IRUGO);
119
120static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
121module_param(ple_window, int, S_IRUGO);
122
8bf00a52 123#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 124#define VMCS02_POOL_SIZE 1
61d2ef2c 125
a2fa3e9f
GH		 126struct vmcs {
127 u32 revision_id;
128 u32 abort;
129 char data[0];
130};
131
d462b819
NHE		 132/*
133 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
134 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
135 * loaded on this CPU (so we can clear them if the CPU goes down).
136 */
137struct loaded_vmcs {
138 struct vmcs *vmcs;
139 int cpu;
140 int launched;
141 struct list_head loaded_vmcss_on_cpu_link;
142};
143
26bb0981
AK		 144struct shared_msr_entry {
145 unsigned index;
146 u64 data;
d5696725 147 u64 mask;
26bb0981
AK		 148};
149
a9d30f33
NHE		 150/*
151 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
152 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
153 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
154 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
155 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
156 * More than one of these structures may exist, if L1 runs multiple L2 guests.
157 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
158 * underlying hardware which will be used to run L2.
159 * This structure is packed to ensure that its layout is identical across
160 * machines (necessary for live migration).
161 * If there are changes in this struct, VMCS12_REVISION must be changed.
162 */
22bd0358 163typedef u64 natural_width;
a9d30f33
NHE		 164struct __packed vmcs12 {
165 /* According to the Intel spec, a VMCS region must start with the
166 * following two fields. Then follow implementation-specific data.
167 */
168 u32 revision_id;
169 u32 abort;
22bd0358 170
27d6c865
NHE		 171 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
172 u32 padding[7]; /* room for future expansion */
173
22bd0358
NHE		 174 u64 io_bitmap_a;
175 u64 io_bitmap_b;
176 u64 msr_bitmap;
177 u64 vm_exit_msr_store_addr;
178 u64 vm_exit_msr_load_addr;
179 u64 vm_entry_msr_load_addr;
180 u64 tsc_offset;
181 u64 virtual_apic_page_addr;
182 u64 apic_access_addr;
183 u64 ept_pointer;
184 u64 guest_physical_address;
185 u64 vmcs_link_pointer;
186 u64 guest_ia32_debugctl;
187 u64 guest_ia32_pat;
188 u64 guest_ia32_efer;
189 u64 guest_ia32_perf_global_ctrl;
190 u64 guest_pdptr0;
191 u64 guest_pdptr1;
192 u64 guest_pdptr2;
193 u64 guest_pdptr3;
194 u64 host_ia32_pat;
195 u64 host_ia32_efer;
196 u64 host_ia32_perf_global_ctrl;
197 u64 padding64[8]; /* room for future expansion */
198 /*
199 * To allow migration of L1 (complete with its L2 guests) between
200 * machines of different natural widths (32 or 64 bit), we cannot have
201 * unsigned long fields with no explict size. We use u64 (aliased
202 * natural_width) instead. Luckily, x86 is little-endian.
203 */
204 natural_width cr0_guest_host_mask;
205 natural_width cr4_guest_host_mask;
206 natural_width cr0_read_shadow;
207 natural_width cr4_read_shadow;
208 natural_width cr3_target_value0;
209 natural_width cr3_target_value1;
210 natural_width cr3_target_value2;
211 natural_width cr3_target_value3;
212 natural_width exit_qualification;
213 natural_width guest_linear_address;
214 natural_width guest_cr0;
215 natural_width guest_cr3;
216 natural_width guest_cr4;
217 natural_width guest_es_base;
218 natural_width guest_cs_base;
219 natural_width guest_ss_base;
220 natural_width guest_ds_base;
221 natural_width guest_fs_base;
222 natural_width guest_gs_base;
223 natural_width guest_ldtr_base;
224 natural_width guest_tr_base;
225 natural_width guest_gdtr_base;
226 natural_width guest_idtr_base;
227 natural_width guest_dr7;
228 natural_width guest_rsp;
229 natural_width guest_rip;
230 natural_width guest_rflags;
231 natural_width guest_pending_dbg_exceptions;
232 natural_width guest_sysenter_esp;
233 natural_width guest_sysenter_eip;
234 natural_width host_cr0;
235 natural_width host_cr3;
236 natural_width host_cr4;
237 natural_width host_fs_base;
238 natural_width host_gs_base;
239 natural_width host_tr_base;
240 natural_width host_gdtr_base;
241 natural_width host_idtr_base;
242 natural_width host_ia32_sysenter_esp;
243 natural_width host_ia32_sysenter_eip;
244 natural_width host_rsp;
245 natural_width host_rip;
246 natural_width paddingl[8]; /* room for future expansion */
247 u32 pin_based_vm_exec_control;
248 u32 cpu_based_vm_exec_control;
249 u32 exception_bitmap;
250 u32 page_fault_error_code_mask;
251 u32 page_fault_error_code_match;
252 u32 cr3_target_count;
253 u32 vm_exit_controls;
254 u32 vm_exit_msr_store_count;
255 u32 vm_exit_msr_load_count;
256 u32 vm_entry_controls;
257 u32 vm_entry_msr_load_count;
258 u32 vm_entry_intr_info_field;
259 u32 vm_entry_exception_error_code;
260 u32 vm_entry_instruction_len;
261 u32 tpr_threshold;
262 u32 secondary_vm_exec_control;
263 u32 vm_instruction_error;
264 u32 vm_exit_reason;
265 u32 vm_exit_intr_info;
266 u32 vm_exit_intr_error_code;
267 u32 idt_vectoring_info_field;
268 u32 idt_vectoring_error_code;
269 u32 vm_exit_instruction_len;
270 u32 vmx_instruction_info;
271 u32 guest_es_limit;
272 u32 guest_cs_limit;
273 u32 guest_ss_limit;
274 u32 guest_ds_limit;
275 u32 guest_fs_limit;
276 u32 guest_gs_limit;
277 u32 guest_ldtr_limit;
278 u32 guest_tr_limit;
279 u32 guest_gdtr_limit;
280 u32 guest_idtr_limit;
281 u32 guest_es_ar_bytes;
282 u32 guest_cs_ar_bytes;
283 u32 guest_ss_ar_bytes;
284 u32 guest_ds_ar_bytes;
285 u32 guest_fs_ar_bytes;
286 u32 guest_gs_ar_bytes;
287 u32 guest_ldtr_ar_bytes;
288 u32 guest_tr_ar_bytes;
289 u32 guest_interruptibility_info;
290 u32 guest_activity_state;
291 u32 guest_sysenter_cs;
292 u32 host_ia32_sysenter_cs;
293 u32 padding32[8]; /* room for future expansion */
294 u16 virtual_processor_id;
295 u16 guest_es_selector;
296 u16 guest_cs_selector;
297 u16 guest_ss_selector;
298 u16 guest_ds_selector;
299 u16 guest_fs_selector;
300 u16 guest_gs_selector;
301 u16 guest_ldtr_selector;
302 u16 guest_tr_selector;
303 u16 host_es_selector;
304 u16 host_cs_selector;
305 u16 host_ss_selector;
306 u16 host_ds_selector;
307 u16 host_fs_selector;
308 u16 host_gs_selector;
309 u16 host_tr_selector;
a9d30f33
NHE		 310};
311
312/*
313 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
314 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
315 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
316 */
317#define VMCS12_REVISION 0x11e57ed0
318
319/*
320 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
321 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
322 * current implementation, 4K are reserved to avoid future complications.
323 */
324#define VMCS12_SIZE 0x1000
325
ff2f6fe9
NHE		 326/* Used to remember the last vmcs02 used for some recently used vmcs12s */
327struct vmcs02_list {
328 struct list_head list;
329 gpa_t vmptr;
330 struct loaded_vmcs vmcs02;
331};
332
ec378aee
NHE		 333/*
334 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
335 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 */
337struct nested_vmx {
338 /* Has the level1 guest done vmxon? */
339 bool vmxon;
a9d30f33
NHE		 340
341 /* The guest-physical address of the current VMCS L1 keeps for L2 */
342 gpa_t current_vmptr;
343 /* The host-usable pointer to the above */
344 struct page *current_vmcs12_page;
345 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 346
347 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
348 struct list_head vmcs02_pool;
349 int vmcs02_num;
fe3ef05c 350 u64 vmcs01_tsc_offset;
644d711a
NHE		 351 /* L2 must run next, and mustn't decide to exit to L1. */
352 bool nested_run_pending;
fe3ef05c
NHE		 353 /*
354 * Guest pages referred to in vmcs02 with host-physical pointers, so
355 * we must keep them pinned while L2 runs.
356 */
357 struct page *apic_access_page;
ec378aee
NHE		 358};
359
a2fa3e9f 360struct vcpu_vmx {
fb3f0f51 361 struct kvm_vcpu vcpu;
313dbd49 362 unsigned long host_rsp;
29bd8a78 363 u8 fail;
69c73028 364 u8 cpl;
9d58b931 365 bool nmi_known_unmasked;
51aa01d1 366 u32 exit_intr_info;
1155f76a 367 u32 idt_vectoring_info;
6de12732 368 ulong rflags;
26bb0981 369 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 370 int nmsrs;
371 int save_nmsrs;
a2fa3e9f 372#ifdef CONFIG_X86_64
44ea2b17
AK		 373 u64 msr_host_kernel_gs_base;
374 u64 msr_guest_kernel_gs_base;
a2fa3e9f 375#endif
d462b819
NHE		 376 /*
377 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
378 * non-nested (L1) guest, it always points to vmcs01. For a nested
379 * guest (L2), it points to a different VMCS.
380 */
381 struct loaded_vmcs vmcs01;
382 struct loaded_vmcs *loaded_vmcs;
383 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 384 struct msr_autoload {
385 unsigned nr;
386 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
387 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
388 } msr_autoload;
a2fa3e9f
GH		 389 struct {
390 int loaded;
391 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 392 int gs_ldt_reload_needed;
393 int fs_reload_needed;
d77c26fc 394 } host_state;
9c8cba37 395 struct {
7ffd92c5 396 int vm86_active;
78ac8b47 397 ulong save_rflags;
7ffd92c5
AK		 398 struct kvm_save_segment {
399 u16 selector;
400 unsigned long base;
401 u32 limit;
402 u32 ar;
403 } tr, es, ds, fs, gs;
9c8cba37 404 } rmode;
2fb92db1
AK		 405 struct {
406 u32 bitmask; /* 4 bits per segment (1 bit per field) */
407 struct kvm_save_segment seg[8];
408 } segment_cache;
2384d2b3 409 int vpid;
04fa4d32 410 bool emulation_required;
3b86cd99
JK		 411
412 /* Support for vnmi-less CPUs */
413 int soft_vnmi_blocked;
414 ktime_t entry_time;
415 s64 vnmi_blocked_time;
a0861c02 416 u32 exit_reason;
4e47c7a6
SY		 417
418 bool rdtscp_enabled;
ec378aee
NHE		 419
420 /* Support for a guest hypervisor (nested VMX) */
421 struct nested_vmx nested;
a2fa3e9f
GH		 422};
423
2fb92db1
AK		 424enum segment_cache_field {
425 SEG_FIELD_SEL = 0,
426 SEG_FIELD_BASE = 1,
427 SEG_FIELD_LIMIT = 2,
428 SEG_FIELD_AR = 3,
429
430 SEG_FIELD_NR = 4
431};
432
a2fa3e9f
GH		 433static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
434{
fb3f0f51 435 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 436}
437
22bd0358
NHE		 438#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
439#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
440#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
441 [number##_HIGH] = VMCS12_OFFSET(name)+4
442
443static unsigned short vmcs_field_to_offset_table[] = {
444 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
445 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
446 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
447 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
448 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
449 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
450 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
451 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
452 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
453 FIELD(HOST_ES_SELECTOR, host_es_selector),
454 FIELD(HOST_CS_SELECTOR, host_cs_selector),
455 FIELD(HOST_SS_SELECTOR, host_ss_selector),
456 FIELD(HOST_DS_SELECTOR, host_ds_selector),
457 FIELD(HOST_FS_SELECTOR, host_fs_selector),
458 FIELD(HOST_GS_SELECTOR, host_gs_selector),
459 FIELD(HOST_TR_SELECTOR, host_tr_selector),
460 FIELD64(IO_BITMAP_A, io_bitmap_a),
461 FIELD64(IO_BITMAP_B, io_bitmap_b),
462 FIELD64(MSR_BITMAP, msr_bitmap),
463 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
464 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
465 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
466 FIELD64(TSC_OFFSET, tsc_offset),
467 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
468 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
469 FIELD64(EPT_POINTER, ept_pointer),
470 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
471 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
472 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
473 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
474 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
475 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
476 FIELD64(GUEST_PDPTR0, guest_pdptr0),
477 FIELD64(GUEST_PDPTR1, guest_pdptr1),
478 FIELD64(GUEST_PDPTR2, guest_pdptr2),
479 FIELD64(GUEST_PDPTR3, guest_pdptr3),
480 FIELD64(HOST_IA32_PAT, host_ia32_pat),
481 FIELD64(HOST_IA32_EFER, host_ia32_efer),
482 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
483 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
484 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
485 FIELD(EXCEPTION_BITMAP, exception_bitmap),
486 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
487 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
488 FIELD(CR3_TARGET_COUNT, cr3_target_count),
489 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
490 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
491 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
492 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
493 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
494 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
495 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
496 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
497 FIELD(TPR_THRESHOLD, tpr_threshold),
498 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
499 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
500 FIELD(VM_EXIT_REASON, vm_exit_reason),
501 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
502 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
503 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
504 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
505 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
506 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
507 FIELD(GUEST_ES_LIMIT, guest_es_limit),
508 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
509 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
510 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
511 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
512 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
513 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
514 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
515 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
516 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
517 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
518 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
519 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
520 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
521 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
522 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
523 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
524 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
525 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
526 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
527 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
528 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
529 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
530 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
531 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
532 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
533 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
534 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
535 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
536 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
537 FIELD(EXIT_QUALIFICATION, exit_qualification),
538 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
539 FIELD(GUEST_CR0, guest_cr0),
540 FIELD(GUEST_CR3, guest_cr3),
541 FIELD(GUEST_CR4, guest_cr4),
542 FIELD(GUEST_ES_BASE, guest_es_base),
543 FIELD(GUEST_CS_BASE, guest_cs_base),
544 FIELD(GUEST_SS_BASE, guest_ss_base),
545 FIELD(GUEST_DS_BASE, guest_ds_base),
546 FIELD(GUEST_FS_BASE, guest_fs_base),
547 FIELD(GUEST_GS_BASE, guest_gs_base),
548 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
549 FIELD(GUEST_TR_BASE, guest_tr_base),
550 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
551 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
552 FIELD(GUEST_DR7, guest_dr7),
553 FIELD(GUEST_RSP, guest_rsp),
554 FIELD(GUEST_RIP, guest_rip),
555 FIELD(GUEST_RFLAGS, guest_rflags),
556 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
557 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
558 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
559 FIELD(HOST_CR0, host_cr0),
560 FIELD(HOST_CR3, host_cr3),
561 FIELD(HOST_CR4, host_cr4),
562 FIELD(HOST_FS_BASE, host_fs_base),
563 FIELD(HOST_GS_BASE, host_gs_base),
564 FIELD(HOST_TR_BASE, host_tr_base),
565 FIELD(HOST_GDTR_BASE, host_gdtr_base),
566 FIELD(HOST_IDTR_BASE, host_idtr_base),
567 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
568 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
569 FIELD(HOST_RSP, host_rsp),
570 FIELD(HOST_RIP, host_rip),
571};
572static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
573
574static inline short vmcs_field_to_offset(unsigned long field)
575{
576 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
577 return -1;
578 return vmcs_field_to_offset_table[field];
579}
580
a9d30f33
NHE		 581static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
582{
583 return to_vmx(vcpu)->nested.current_vmcs12;
584}
585
586static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
587{
588 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
589 if (is_error_page(page)) {
590 kvm_release_page_clean(page);
591 return NULL;
592 }
593 return page;
594}
595
596static void nested_release_page(struct page *page)
597{
598 kvm_release_page_dirty(page);
599}
600
601static void nested_release_page_clean(struct page *page)
602{
603 kvm_release_page_clean(page);
604}
605
4e1096d2 606static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 607static void kvm_cpu_vmxon(u64 addr);
608static void kvm_cpu_vmxoff(void);
aff48baa 609static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 610static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 611
6aa8b732
AK		 612static DEFINE_PER_CPU(struct vmcs *, vmxarea);
613static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 614/*
615 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
616 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
617 */
618static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 619static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 620
3e7c73e9
AK		 621static unsigned long *vmx_io_bitmap_a;
622static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 623static unsigned long *vmx_msr_bitmap_legacy;
624static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 625
110312c8 626static bool cpu_has_load_ia32_efer;
8bf00a52 627static bool cpu_has_load_perf_global_ctrl;
110312c8 628
2384d2b3
SY		 629static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
630static DEFINE_SPINLOCK(vmx_vpid_lock);
631
1c3d14fe 632static struct vmcs_config {
6aa8b732
AK		 633 int size;
634 int order;
635 u32 revision_id;
1c3d14fe
YS		 636 u32 pin_based_exec_ctrl;
637 u32 cpu_based_exec_ctrl;
f78e0e2e 638 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 639 u32 vmexit_ctrl;
640 u32 vmentry_ctrl;
641} vmcs_config;
6aa8b732 642
efff9e53 643static struct vmx_capability {
d56f546d
SY		 644 u32 ept;
645 u32 vpid;
646} vmx_capability;
647
6aa8b732
AK		 648#define VMX_SEGMENT_FIELD(seg) \
649 [VCPU_SREG_##seg] = { \
650 .selector = GUEST_##seg##_SELECTOR, \
651 .base = GUEST_##seg##_BASE, \
652 .limit = GUEST_##seg##_LIMIT, \
653 .ar_bytes = GUEST_##seg##_AR_BYTES, \
654 }
655
656static struct kvm_vmx_segment_field {
657 unsigned selector;
658 unsigned base;
659 unsigned limit;
660 unsigned ar_bytes;
661} kvm_vmx_segment_fields[] = {
662 VMX_SEGMENT_FIELD(CS),
663 VMX_SEGMENT_FIELD(DS),
664 VMX_SEGMENT_FIELD(ES),
665 VMX_SEGMENT_FIELD(FS),
666 VMX_SEGMENT_FIELD(GS),
667 VMX_SEGMENT_FIELD(SS),
668 VMX_SEGMENT_FIELD(TR),
669 VMX_SEGMENT_FIELD(LDTR),
670};
671
26bb0981
AK		 672static u64 host_efer;
673
6de4f3ad
AK		 674static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
675
4d56c8a7 676/*
8c06585d 677 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 678 * away by decrementing the array size.
679 */
6aa8b732 680static const u32 vmx_msr_index[] = {
05b3e0c2 681#ifdef CONFIG_X86_64
44ea2b17 682 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 683#endif
8c06585d 684 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 685};
9d8f549d 686#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 687
31299944 688static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 689{
690 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
691 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 692 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 693}
694
31299944 695static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 696{
697 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
698 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 699 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 700}
701
31299944 702static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 703{
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 706 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 707}
708
31299944 709static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
712 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
713}
714
31299944 715static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 716{
717 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
718 INTR_INFO_VALID_MASK)) ==
719 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
720}
721
31299944 722static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 723{
04547156 724 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 725}
726
31299944 727static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 728{
04547156 729 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 730}
731
31299944 732static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 733{
04547156 734 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 735}
736
31299944 737static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 738{
04547156
SY		 739 return vmcs_config.cpu_based_exec_ctrl &
740 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 741}
742
774ead3a 743static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 744{
04547156
SY		 745 return vmcs_config.cpu_based_2nd_exec_ctrl &
746 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
747}
748
749static inline bool cpu_has_vmx_flexpriority(void)
750{
751 return cpu_has_vmx_tpr_shadow() &&
752 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 753}
754
e799794e
MT		 755static inline bool cpu_has_vmx_ept_execute_only(void)
756{
31299944 757 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 758}
759
760static inline bool cpu_has_vmx_eptp_uncacheable(void)
761{
31299944 762 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 763}
764
765static inline bool cpu_has_vmx_eptp_writeback(void)
766{
31299944 767 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 768}
769
770static inline bool cpu_has_vmx_ept_2m_page(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 773}
774
878403b7
SY		 775static inline bool cpu_has_vmx_ept_1g_page(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 778}
779
4bc9b982
SY		 780static inline bool cpu_has_vmx_ept_4levels(void)
781{
782 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
783}
784
31299944 785static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 786{
31299944 787 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 788}
789
31299944 790static inline bool cpu_has_vmx_invept_context(void)
d56f546d 791{
31299944 792 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 793}
794
31299944 795static inline bool cpu_has_vmx_invept_global(void)
d56f546d 796{
31299944 797 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 798}
799
518c8aee
GJ		 800static inline bool cpu_has_vmx_invvpid_single(void)
801{
802 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
803}
804
b9d762fa
GJ		 805static inline bool cpu_has_vmx_invvpid_global(void)
806{
807 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
808}
809
31299944 810static inline bool cpu_has_vmx_ept(void)
d56f546d 811{
04547156
SY		 812 return vmcs_config.cpu_based_2nd_exec_ctrl &
813 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 814}
815
31299944 816static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 817{
818 return vmcs_config.cpu_based_2nd_exec_ctrl &
819 SECONDARY_EXEC_UNRESTRICTED_GUEST;
820}
821
31299944 822static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 823{
824 return vmcs_config.cpu_based_2nd_exec_ctrl &
825 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
826}
827
31299944 828static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 829{
6d3e435e 830 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 831}
832
31299944 833static inline bool cpu_has_vmx_vpid(void)
2384d2b3 834{
04547156
SY		 835 return vmcs_config.cpu_based_2nd_exec_ctrl &
836 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 837}
838
31299944 839static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 840{
841 return vmcs_config.cpu_based_2nd_exec_ctrl &
842 SECONDARY_EXEC_RDTSCP;
843}
844
31299944 845static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 846{
847 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
848}
849
f5f48ee1
SY		 850static inline bool cpu_has_vmx_wbinvd_exit(void)
851{
852 return vmcs_config.cpu_based_2nd_exec_ctrl &
853 SECONDARY_EXEC_WBINVD_EXITING;
854}
855
04547156
SY		 856static inline bool report_flexpriority(void)
857{
858 return flexpriority_enabled;
859}
860
fe3ef05c
NHE		 861static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
862{
863 return vmcs12->cpu_based_vm_exec_control & bit;
864}
865
866static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
867{
868 return (vmcs12->cpu_based_vm_exec_control &
869 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
870 (vmcs12->secondary_vm_exec_control & bit);
871}
872
644d711a
NHE		 873static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
874 struct kvm_vcpu *vcpu)
875{
876 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
877}
878
879static inline bool is_exception(u32 intr_info)
880{
881 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
882 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
883}
884
885static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 886static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
887 struct vmcs12 *vmcs12,
888 u32 reason, unsigned long qualification);
889
8b9cf98c 890static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 891{
892 int i;
893
a2fa3e9f 894 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 895 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 896 return i;
897 return -1;
898}
899
2384d2b3
SY		 900static inline void __invvpid(int ext, u16 vpid, gva_t gva)
901{
902 struct {
903 u64 vpid : 16;
904 u64 rsvd : 48;
905 u64 gva;
906 } operand = { vpid, 0, gva };
907
4ecac3fd 908 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 909 /* CF==1 or ZF==1 --> rc = -1 */
910 "; ja 1f ; ud2 ; 1:"
911 : : "a"(&operand), "c"(ext) : "cc", "memory");
912}
913
1439442c
SY		 914static inline void __invept(int ext, u64 eptp, gpa_t gpa)
915{
916 struct {
917 u64 eptp, gpa;
918 } operand = {eptp, gpa};
919
4ecac3fd 920 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 921 /* CF==1 or ZF==1 --> rc = -1 */
922 "; ja 1f ; ud2 ; 1:\n"
923 : : "a" (&operand), "c" (ext) : "cc", "memory");
924}
925
26bb0981 926static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 927{
928 int i;
929
8b9cf98c 930 i = __find_msr_index(vmx, msr);
a75beee6 931 if (i >= 0)
a2fa3e9f 932 return &vmx->guest_msrs[i];
8b6d44c7 933 return NULL;
7725f0ba
AK		 934}
935
6aa8b732
AK		 936static void vmcs_clear(struct vmcs *vmcs)
937{
938 u64 phys_addr = __pa(vmcs);
939 u8 error;
940
4ecac3fd 941 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 942 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 943 : "cc", "memory");
944 if (error)
945 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
946 vmcs, phys_addr);
947}
948
d462b819
NHE		 949static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
950{
951 vmcs_clear(loaded_vmcs->vmcs);
952 loaded_vmcs->cpu = -1;
953 loaded_vmcs->launched = 0;
954}
955
7725b894
DX		 956static void vmcs_load(struct vmcs *vmcs)
957{
958 u64 phys_addr = __pa(vmcs);
959 u8 error;
960
961 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 962 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 963 : "cc", "memory");
964 if (error)
2844d849 965 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 966 vmcs, phys_addr);
967}
968
d462b819 969static void __loaded_vmcs_clear(void *arg)
6aa8b732 970{
d462b819 971 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 972 int cpu = raw_smp_processor_id();
6aa8b732 973
d462b819
NHE		 974 if (loaded_vmcs->cpu != cpu)
975 return; /* vcpu migration can race with cpu offline */
976 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 977 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 978 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
979 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 980}
981
d462b819 982static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 983{
d462b819
NHE		 984 if (loaded_vmcs->cpu != -1)
985 smp_call_function_single(
986 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 987}
988
1760dd49 989static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 990{
991 if (vmx->vpid == 0)
992 return;
993
518c8aee
GJ		 994 if (cpu_has_vmx_invvpid_single())
995 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 996}
997
b9d762fa
GJ		 998static inline void vpid_sync_vcpu_global(void)
999{
1000 if (cpu_has_vmx_invvpid_global())
1001 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1002}
1003
1004static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1005{
1006 if (cpu_has_vmx_invvpid_single())
1760dd49 1007 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1008 else
1009 vpid_sync_vcpu_global();
1010}
1011
1439442c
SY		 1012static inline void ept_sync_global(void)
1013{
1014 if (cpu_has_vmx_invept_global())
1015 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1016}
1017
1018static inline void ept_sync_context(u64 eptp)
1019{
089d034e 1020 if (enable_ept) {
1439442c
SY		 1021 if (cpu_has_vmx_invept_context())
1022 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1023 else
1024 ept_sync_global();
1025 }
1026}
1027
1028static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1029{
089d034e 1030 if (enable_ept) {
1439442c
SY		 1031 if (cpu_has_vmx_invept_individual_addr())
1032 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1033 eptp, gpa);
1034 else
1035 ept_sync_context(eptp);
1036 }
1037}
1038
96304217 1039static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1040{
5e520e62 1041 unsigned long value;
6aa8b732 1042
5e520e62
AK		 1043 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1044 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1045 return value;
1046}
1047
96304217 1048static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1049{
1050 return vmcs_readl(field);
1051}
1052
96304217 1053static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1054{
1055 return vmcs_readl(field);
1056}
1057
96304217 1058static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1059{
05b3e0c2 1060#ifdef CONFIG_X86_64
6aa8b732
AK		 1061 return vmcs_readl(field);
1062#else
1063 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1064#endif
1065}
1066
e52de1b8
AK		 1067static noinline void vmwrite_error(unsigned long field, unsigned long value)
1068{
1069 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1070 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1071 dump_stack();
1072}
1073
6aa8b732
AK		 1074static void vmcs_writel(unsigned long field, unsigned long value)
1075{
1076 u8 error;
1077
4ecac3fd 1078 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1079 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1080 if (unlikely(error))
1081 vmwrite_error(field, value);
6aa8b732
AK		 1082}
1083
1084static void vmcs_write16(unsigned long field, u16 value)
1085{
1086 vmcs_writel(field, value);
1087}
1088
1089static void vmcs_write32(unsigned long field, u32 value)
1090{
1091 vmcs_writel(field, value);
1092}
1093
1094static void vmcs_write64(unsigned long field, u64 value)
1095{
6aa8b732 1096 vmcs_writel(field, value);
7682f2d0 1097#ifndef CONFIG_X86_64
6aa8b732
AK		 1098 asm volatile ("");
1099 vmcs_writel(field+1, value >> 32);
1100#endif
1101}
1102
2ab455cc
AL		 1103static void vmcs_clear_bits(unsigned long field, u32 mask)
1104{
1105 vmcs_writel(field, vmcs_readl(field) & ~mask);
1106}
1107
1108static void vmcs_set_bits(unsigned long field, u32 mask)
1109{
1110 vmcs_writel(field, vmcs_readl(field) | mask);
1111}
1112
2fb92db1
AK		 1113static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1114{
1115 vmx->segment_cache.bitmask = 0;
1116}
1117
1118static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1119 unsigned field)
1120{
1121 bool ret;
1122 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1123
1124 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1125 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1126 vmx->segment_cache.bitmask = 0;
1127 }
1128 ret = vmx->segment_cache.bitmask & mask;
1129 vmx->segment_cache.bitmask |= mask;
1130 return ret;
1131}
1132
1133static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1134{
1135 u16 *p = &vmx->segment_cache.seg[seg].selector;
1136
1137 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1138 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1139 return *p;
1140}
1141
1142static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1143{
1144 ulong *p = &vmx->segment_cache.seg[seg].base;
1145
1146 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1147 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1148 return *p;
1149}
1150
1151static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1152{
1153 u32 *p = &vmx->segment_cache.seg[seg].limit;
1154
1155 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1156 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1157 return *p;
1158}
1159
1160static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1161{
1162 u32 *p = &vmx->segment_cache.seg[seg].ar;
1163
1164 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1165 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1166 return *p;
1167}
1168
abd3f2d6
AK		 1169static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1170{
1171 u32 eb;
1172
fd7373cc
JK		 1173 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1174 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1175 if ((vcpu->guest_debug &
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1177 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1178 eb |= 1u << BP_VECTOR;
7ffd92c5 1179 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1180 eb = ~0;
089d034e 1181 if (enable_ept)
1439442c 1182 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1183 if (vcpu->fpu_active)
1184 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1185
1186 /* When we are running a nested L2 guest and L1 specified for it a
1187 * certain exception bitmap, we must trap the same exceptions and pass
1188 * them to L1. When running L2, we will only handle the exceptions
1189 * specified above if L1 did not want them.
1190 */
1191 if (is_guest_mode(vcpu))
1192 eb |= get_vmcs12(vcpu)->exception_bitmap;
1193
abd3f2d6
AK		 1194 vmcs_write32(EXCEPTION_BITMAP, eb);
1195}
1196
8bf00a52
GN		 1197static void clear_atomic_switch_msr_special(unsigned long entry,
1198 unsigned long exit)
1199{
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1202}
1203
61d2ef2c
AK		 1204static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1205{
1206 unsigned i;
1207 struct msr_autoload *m = &vmx->msr_autoload;
1208
8bf00a52
GN		 1209 switch (msr) {
1210 case MSR_EFER:
1211 if (cpu_has_load_ia32_efer) {
1212 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1213 VM_EXIT_LOAD_IA32_EFER);
1214 return;
1215 }
1216 break;
1217 case MSR_CORE_PERF_GLOBAL_CTRL:
1218 if (cpu_has_load_perf_global_ctrl) {
1219 clear_atomic_switch_msr_special(
1220 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1221 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1222 return;
1223 }
1224 break;
110312c8
AK		 1225 }
1226
61d2ef2c
AK		 1227 for (i = 0; i < m->nr; ++i)
1228 if (m->guest[i].index == msr)
1229 break;
1230
1231 if (i == m->nr)
1232 return;
1233 --m->nr;
1234 m->guest[i] = m->guest[m->nr];
1235 m->host[i] = m->host[m->nr];
1236 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1237 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1238}
1239
8bf00a52
GN		 1240static void add_atomic_switch_msr_special(unsigned long entry,
1241 unsigned long exit, unsigned long guest_val_vmcs,
1242 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1243{
1244 vmcs_write64(guest_val_vmcs, guest_val);
1245 vmcs_write64(host_val_vmcs, host_val);
1246 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1247 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1248}
1249
61d2ef2c
AK		 1250static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1251 u64 guest_val, u64 host_val)
1252{
1253 unsigned i;
1254 struct msr_autoload *m = &vmx->msr_autoload;
1255
8bf00a52
GN		 1256 switch (msr) {
1257 case MSR_EFER:
1258 if (cpu_has_load_ia32_efer) {
1259 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1260 VM_EXIT_LOAD_IA32_EFER,
1261 GUEST_IA32_EFER,
1262 HOST_IA32_EFER,
1263 guest_val, host_val);
1264 return;
1265 }
1266 break;
1267 case MSR_CORE_PERF_GLOBAL_CTRL:
1268 if (cpu_has_load_perf_global_ctrl) {
1269 add_atomic_switch_msr_special(
1270 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1272 GUEST_IA32_PERF_GLOBAL_CTRL,
1273 HOST_IA32_PERF_GLOBAL_CTRL,
1274 guest_val, host_val);
1275 return;
1276 }
1277 break;
110312c8
AK		 1278 }
1279
61d2ef2c
AK		 1280 for (i = 0; i < m->nr; ++i)
1281 if (m->guest[i].index == msr)
1282 break;
1283
e7fc6f93
GN		 1284 if (i == NR_AUTOLOAD_MSRS) {
1285 printk_once(KERN_WARNING"Not enough mst switch entries. "
1286 "Can't add msr %x\n", msr);
1287 return;
1288 } else if (i == m->nr) {
61d2ef2c
AK		 1289 ++m->nr;
1290 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1291 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1292 }
1293
1294 m->guest[i].index = msr;
1295 m->guest[i].value = guest_val;
1296 m->host[i].index = msr;
1297 m->host[i].value = host_val;
1298}
1299
33ed6329
AK		 1300static void reload_tss(void)
1301{
33ed6329
AK		 1302 /*
1303 * VT restores TR but not its size. Useless.
1304 */
d359192f 1305 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1306 struct desc_struct *descs;
33ed6329 1307
d359192f 1308 descs = (void *)gdt->address;
33ed6329
AK		 1309 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1310 load_TR_desc();
33ed6329
AK		 1311}
1312
92c0d900 1313static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1314{
3a34a881 1315 u64 guest_efer;
51c6cf66
AK		 1316 u64 ignore_bits;
1317
f6801dff 1318 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1319
51c6cf66
AK		 1320 /*
1321 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1322 * outside long mode
1323 */
1324 ignore_bits = EFER_NX | EFER_SCE;
1325#ifdef CONFIG_X86_64
1326 ignore_bits |= EFER_LMA | EFER_LME;
1327 /* SCE is meaningful only in long mode on Intel */
1328 if (guest_efer & EFER_LMA)
1329 ignore_bits &= ~(u64)EFER_SCE;
1330#endif
51c6cf66
AK		 1331 guest_efer &= ~ignore_bits;
1332 guest_efer |= host_efer & ignore_bits;
26bb0981 1333 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1334 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1335
1336 clear_atomic_switch_msr(vmx, MSR_EFER);
1337 /* On ept, can't emulate nx, and must switch nx atomically */
1338 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1339 guest_efer = vmx->vcpu.arch.efer;
1340 if (!(guest_efer & EFER_LMA))
1341 guest_efer &= ~EFER_LME;
1342 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1343 return false;
1344 }
1345
26bb0981 1346 return true;
51c6cf66
AK		 1347}
1348
2d49ec72
GN		 1349static unsigned long segment_base(u16 selector)
1350{
d359192f 1351 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1352 struct desc_struct *d;
1353 unsigned long table_base;
1354 unsigned long v;
1355
1356 if (!(selector & ~3))
1357 return 0;
1358
d359192f 1359 table_base = gdt->address;
2d49ec72
GN		 1360
1361 if (selector & 4) { /* from ldt */
1362 u16 ldt_selector = kvm_read_ldt();
1363
1364 if (!(ldt_selector & ~3))
1365 return 0;
1366
1367 table_base = segment_base(ldt_selector);
1368 }
1369 d = (struct desc_struct *)(table_base + (selector & ~7));
1370 v = get_desc_base(d);
1371#ifdef CONFIG_X86_64
1372 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1373 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1374#endif
1375 return v;
1376}
1377
1378static inline unsigned long kvm_read_tr_base(void)
1379{
1380 u16 tr;
1381 asm("str %0" : "=g"(tr));
1382 return segment_base(tr);
1383}
1384
04d2cc77 1385static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1386{
04d2cc77 1387 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1388 int i;
04d2cc77 1389
a2fa3e9f 1390 if (vmx->host_state.loaded)
33ed6329
AK		 1391 return;
1392
a2fa3e9f 1393 vmx->host_state.loaded = 1;
33ed6329
AK		 1394 /*
1395 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1396 * allow segment selectors with cpl > 0 or ti == 1.
1397 */
d6e88aec 1398 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1399 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1400 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1401 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1402 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1403 vmx->host_state.fs_reload_needed = 0;
1404 } else {
33ed6329 1405 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1406 vmx->host_state.fs_reload_needed = 1;
33ed6329 1407 }
9581d442 1408 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1409 if (!(vmx->host_state.gs_sel & 7))
1410 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1411 else {
1412 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1413 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1414 }
1415
1416#ifdef CONFIG_X86_64
1417 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1418 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1419#else
a2fa3e9f
GH		 1420 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1421 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1422#endif
707c0874
AK		 1423
1424#ifdef CONFIG_X86_64
c8770e7b
AK		 1425 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1426 if (is_long_mode(&vmx->vcpu))
44ea2b17 1427 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1428#endif
26bb0981
AK		 1429 for (i = 0; i < vmx->save_nmsrs; ++i)
1430 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1431 vmx->guest_msrs[i].data,
1432 vmx->guest_msrs[i].mask);
33ed6329
AK		 1433}
1434
a9b21b62 1435static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1436{
a2fa3e9f 1437 if (!vmx->host_state.loaded)
33ed6329
AK		 1438 return;
1439
e1beb1d3 1440 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1441 vmx->host_state.loaded = 0;
c8770e7b
AK		 1442#ifdef CONFIG_X86_64
1443 if (is_long_mode(&vmx->vcpu))
1444 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1445#endif
152d3f2f 1446 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1447 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1448#ifdef CONFIG_X86_64
9581d442 1449 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1450#else
1451 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1452#endif
33ed6329 1453 }
0a77fe4c
AK		 1454 if (vmx->host_state.fs_reload_needed)
1455 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1456 reload_tss();
44ea2b17 1457#ifdef CONFIG_X86_64
c8770e7b 1458 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1459#endif
1c11e713
AK		 1460 if (current_thread_info()->status & TS_USEDFPU)
1461 clts();
3444d7da 1462 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1463}
1464
a9b21b62
AK		 1465static void vmx_load_host_state(struct vcpu_vmx *vmx)
1466{
1467 preempt_disable();
1468 __vmx_load_host_state(vmx);
1469 preempt_enable();
1470}
1471
6aa8b732
AK		 1472/*
1473 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1474 * vcpu mutex is already taken.
1475 */
15ad7146 1476static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1477{
a2fa3e9f 1478 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1479 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1480
4610c9cc
DX		 1481 if (!vmm_exclusive)
1482 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1483 else if (vmx->loaded_vmcs->cpu != cpu)
1484 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1485
d462b819
NHE		 1486 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1487 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1488 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1489 }
1490
d462b819 1491 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1492 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1493 unsigned long sysenter_esp;
1494
a8eeb04a 1495 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1496 local_irq_disable();
d462b819
NHE		 1497 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1498 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1499 local_irq_enable();
1500
6aa8b732
AK		 1501 /*
1502 * Linux uses per-cpu TSS and GDT, so set these when switching
1503 * processors.
1504 */
d6e88aec 1505 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1506 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1507
1508 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1509 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1510 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1511 }
6aa8b732
AK		 1512}
1513
1514static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1515{
a9b21b62 1516 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1517 if (!vmm_exclusive) {
d462b819
NHE		 1518 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1519 vcpu->cpu = -1;
4610c9cc
DX		 1520 kvm_cpu_vmxoff();
1521 }
6aa8b732
AK		 1522}
1523
5fd86fcf
AK		 1524static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1525{
81231c69
AK		 1526 ulong cr0;
1527
5fd86fcf
AK		 1528 if (vcpu->fpu_active)
1529 return;
1530 vcpu->fpu_active = 1;
81231c69
AK		 1531 cr0 = vmcs_readl(GUEST_CR0);
1532 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1533 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1534 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1535 update_exception_bitmap(vcpu);
edcafe3c 1536 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1537 if (is_guest_mode(vcpu))
1538 vcpu->arch.cr0_guest_owned_bits &=
1539 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1540 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1541}
1542
edcafe3c
AK		 1543static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1544
fe3ef05c
NHE		 1545/*
1546 * Return the cr0 value that a nested guest would read. This is a combination
1547 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1548 * its hypervisor (cr0_read_shadow).
1549 */
1550static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1551{
1552 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1553 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1554}
1555static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1556{
1557 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1558 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1559}
1560
5fd86fcf
AK		 1561static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1562{
36cf24e0
NHE		 1563 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1564 * set this *before* calling this function.
1565 */
edcafe3c 1566 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1567 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1568 update_exception_bitmap(vcpu);
edcafe3c
AK		 1569 vcpu->arch.cr0_guest_owned_bits = 0;
1570 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1571 if (is_guest_mode(vcpu)) {
1572 /*
1573 * L1's specified read shadow might not contain the TS bit,
1574 * so now that we turned on shadowing of this bit, we need to
1575 * set this bit of the shadow. Like in nested_vmx_run we need
1576 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1577 * up-to-date here because we just decached cr0.TS (and we'll
1578 * only update vmcs12->guest_cr0 on nested exit).
1579 */
1580 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1581 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1582 (vcpu->arch.cr0 & X86_CR0_TS);
1583 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1584 } else
1585 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1586}
1587
6aa8b732
AK		 1588static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1589{
78ac8b47 1590 unsigned long rflags, save_rflags;
345dcaa8 1591
6de12732
AK		 1592 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1593 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1594 rflags = vmcs_readl(GUEST_RFLAGS);
1595 if (to_vmx(vcpu)->rmode.vm86_active) {
1596 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1597 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1598 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1599 }
1600 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1601 }
6de12732 1602 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1603}
1604
1605static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1606{
6de12732 1607 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1608 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1609 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1610 if (to_vmx(vcpu)->rmode.vm86_active) {
1611 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1612 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1613 }
6aa8b732
AK		 1614 vmcs_writel(GUEST_RFLAGS, rflags);
1615}
1616
2809f5d2
GC		 1617static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1618{
1619 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1620 int ret = 0;
1621
1622 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1623 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1624 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1625 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1626
1627 return ret & mask;
1628}
1629
1630static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1631{
1632 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1633 u32 interruptibility = interruptibility_old;
1634
1635 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1636
48005f64 1637 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1638 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1639 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1640 interruptibility |= GUEST_INTR_STATE_STI;
1641
1642 if ((interruptibility != interruptibility_old))
1643 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1644}
1645
6aa8b732
AK		 1646static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1647{
1648 unsigned long rip;
6aa8b732 1649
5fdbf976 1650 rip = kvm_rip_read(vcpu);
6aa8b732 1651 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1652 kvm_rip_write(vcpu, rip);
6aa8b732 1653
2809f5d2
GC		 1654 /* skipping an emulated instruction also counts */
1655 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1656}
1657
443381a8
AL		 1658static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1659{
1660 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1661 * explicitly skip the instruction because if the HLT state is set, then
1662 * the instruction is already executing and RIP has already been
1663 * advanced. */
1664 if (!yield_on_hlt &&
1665 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1666 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1667}
1668
0b6ac343
NHE		 1669/*
1670 * KVM wants to inject page-faults which it got to the guest. This function
1671 * checks whether in a nested guest, we need to inject them to L1 or L2.
1672 * This function assumes it is called with the exit reason in vmcs02 being
1673 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1674 * is running).
1675 */
1676static int nested_pf_handled(struct kvm_vcpu *vcpu)
1677{
1678 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1679
1680 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1681 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1682 return 0;
1683
1684 nested_vmx_vmexit(vcpu);
1685 return 1;
1686}
1687
298101da 1688static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1689 bool has_error_code, u32 error_code,
1690 bool reinject)
298101da 1691{
77ab6db0 1692 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1693 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1694
0b6ac343
NHE		 1695 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1696 nested_pf_handled(vcpu))
1697 return;
1698
8ab2d2e2 1699 if (has_error_code) {
77ab6db0 1700 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1701 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1702 }
77ab6db0 1703
7ffd92c5 1704 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1705 int inc_eip = 0;
1706 if (kvm_exception_is_soft(nr))
1707 inc_eip = vcpu->arch.event_exit_inst_len;
1708 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1709 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1710 return;
1711 }
1712
66fd3f7f
GN		 1713 if (kvm_exception_is_soft(nr)) {
1714 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1715 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1716 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1717 } else
1718 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1719
1720 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1721 vmx_clear_hlt(vcpu);
298101da
AK		 1722}
1723
4e47c7a6
SY		 1724static bool vmx_rdtscp_supported(void)
1725{
1726 return cpu_has_vmx_rdtscp();
1727}
1728
a75beee6
ED		 1729/*
1730 * Swap MSR entry in host/guest MSR entry array.
1731 */
8b9cf98c 1732static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1733{
26bb0981 1734 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1735
1736 tmp = vmx->guest_msrs[to];
1737 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1738 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1739}
1740
e38aea3e
AK		 1741/*
1742 * Set up the vmcs to automatically save and restore system
1743 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1744 * mode, as fiddling with msrs is very expensive.
1745 */
8b9cf98c 1746static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1747{
26bb0981 1748 int save_nmsrs, index;
5897297b 1749 unsigned long *msr_bitmap;
e38aea3e 1750
a75beee6
ED		 1751 save_nmsrs = 0;
1752#ifdef CONFIG_X86_64
8b9cf98c 1753 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1754 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1755 if (index >= 0)
8b9cf98c
RR		 1756 move_msr_up(vmx, index, save_nmsrs++);
1757 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1758 if (index >= 0)
8b9cf98c
RR		 1759 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1761 if (index >= 0)
8b9cf98c 1762 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1763 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764 if (index >= 0 && vmx->rdtscp_enabled)
1765 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1766 /*
8c06585d 1767 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1768 * if efer.sce is enabled.
1769 */
8c06585d 1770 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1771 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1772 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1773 }
1774#endif
92c0d900
AK		 1775 index = __find_msr_index(vmx, MSR_EFER);
1776 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1777 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1778
26bb0981 1779 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1780
1781 if (cpu_has_vmx_msr_bitmap()) {
1782 if (is_long_mode(&vmx->vcpu))
1783 msr_bitmap = vmx_msr_bitmap_longmode;
1784 else
1785 msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788 }
e38aea3e
AK		 1789}
1790
6aa8b732
AK		 1791/*
1792 * reads and returns guest's timestamp counter "register"
1793 * guest_tsc = host_tsc + tsc_offset -- 21.3
1794 */
1795static u64 guest_read_tsc(void)
1796{
1797 u64 host_tsc, tsc_offset;
1798
1799 rdtscll(host_tsc);
1800 tsc_offset = vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1802}
1803
d5c1785d
NHE		 1804/*
1805 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806 * counter, even if a nested guest (L2) is currently running.
1807 */
1808u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809{
1810 u64 host_tsc, tsc_offset;
1811
1812 rdtscll(host_tsc);
1813 tsc_offset = is_guest_mode(vcpu) ?
1814 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815 vmcs_read64(TSC_OFFSET);
1816 return host_tsc + tsc_offset;
1817}
1818
4051b188
JR		 1819/*
1820 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821 * ioctl. In this case the call-back should update internal vmx state to make
1822 * the changes effective.
1823 */
1824static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1825{
1826 /* Nothing to do here */
1827}
1828
6aa8b732 1829/*
99e3e30a 1830 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1831 */
99e3e30a 1832static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1833{
27fc51b2 1834 if (is_guest_mode(vcpu)) {
7991825b 1835 /*
27fc51b2
NHE		 1836 * We're here if L1 chose not to trap WRMSR to TSC. According
1837 * to the spec, this should set L1's TSC; The offset that L1
1838 * set for L2 remains unchanged, and still needs to be added
1839 * to the newly set TSC to get L2's TSC.
7991825b 1840 */
27fc51b2
NHE		 1841 struct vmcs12 *vmcs12;
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843 /* recalculate vmcs02.TSC_OFFSET: */
1844 vmcs12 = get_vmcs12(vcpu);
1845 vmcs_write64(TSC_OFFSET, offset +
1846 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847 vmcs12->tsc_offset : 0));
1848 } else {
1849 vmcs_write64(TSC_OFFSET, offset);
1850 }
6aa8b732
AK		 1851}
1852
e48672fa
ZA		 1853static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1854{
1855 u64 offset = vmcs_read64(TSC_OFFSET);
1856 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1857 if (is_guest_mode(vcpu)) {
1858 /* Even when running L2, the adjustment needs to apply to L1 */
1859 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1860 }
e48672fa
ZA		 1861}
1862
857e4099
JR		 1863static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1864{
1865 return target_tsc - native_read_tsc();
1866}
1867
801d3424
NHE		 1868static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1869{
1870 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1872}
1873
1874/*
1875 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877 * all guests if the "nested" module option is off, and can also be disabled
1878 * for a single guest by disabling its VMX cpuid bit.
1879 */
1880static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1881{
1882 return nested && guest_cpuid_has_vmx(vcpu);
1883}
1884
b87a51ae
NHE		 1885/*
1886 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887 * returned for the various VMX controls MSRs when nested VMX is enabled.
1888 * The same values should also be used to verify that vmcs12 control fields are
1889 * valid during nested entry from L1 to L2.
1890 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892 * bit in the high half is on if the corresponding bit in the control field
1893 * may be on. See also vmx_control_verify().
1894 * TODO: allow these variables to be modified (downgraded) by module options
1895 * or other means.
1896 */
1897static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902static __init void nested_vmx_setup_ctls_msrs(void)
1903{
1904 /*
1905 * Note that as a general rule, the high half of the MSRs (bits in
1906 * the control fields which may be 1) should be initialized by the
1907 * intersection of the underlying hardware's MSR (i.e., features which
1908 * can be supported) and the list of features we want to expose -
1909 * because they are known to be properly supported in our code.
1910 * Also, usually, the low half of the MSRs (bits which must be 1) can
1911 * be set to 0, meaning that L1 may turn off any of these bits. The
1912 * reason is that if one of these bits is necessary, it will appear
1913 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914 * fields of vmcs01 and vmcs02, will turn these bits off - and
1915 * nested_vmx_exit_handled() will not pass related exits to L1.
1916 * These rules have exceptions below.
1917 */
1918
1919 /* pin-based controls */
1920 /*
1921 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1923 */
1924 nested_vmx_pinbased_ctls_low = 0x16 ;
1925 nested_vmx_pinbased_ctls_high = 0x16 |
1926 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927 PIN_BASED_VIRTUAL_NMIS;
1928
1929 /* exit controls */
1930 nested_vmx_exit_ctls_low = 0;
b6f1250e 1931 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1932#ifdef CONFIG_X86_64
1933 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1934#else
1935 nested_vmx_exit_ctls_high = 0;
1936#endif
1937
1938 /* entry controls */
1939 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941 nested_vmx_entry_ctls_low = 0;
1942 nested_vmx_entry_ctls_high &=
1943 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1944
1945 /* cpu-based controls */
1946 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948 nested_vmx_procbased_ctls_low = 0;
1949 nested_vmx_procbased_ctls_high &=
1950 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953 CPU_BASED_CR3_STORE_EXITING |
1954#ifdef CONFIG_X86_64
1955 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1956#endif
1957 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 1959 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 1960 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1961 /*
1962 * We can allow some features even when not supported by the
1963 * hardware. For example, L1 can specify an MSR bitmap - and we
1964 * can use it to avoid exits to L1 - even when L0 runs L2
1965 * without MSR bitmaps.
1966 */
1967 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1968
1969 /* secondary cpu-based controls */
1970 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1971 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1972 nested_vmx_secondary_ctls_low = 0;
1973 nested_vmx_secondary_ctls_high &=
1974 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1975}
1976
1977static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1978{
1979 /*
1980 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1981 */
1982 return ((control & high) | low) == control;
1983}
1984
1985static inline u64 vmx_control_msr(u32 low, u32 high)
1986{
1987 return low | ((u64)high << 32);
1988}
1989
1990/*
1991 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1992 * also let it use VMX-specific MSRs.
1993 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1994 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1995 * like all other MSRs).
1996 */
1997static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1998{
1999 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2000 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2001 /*
2002 * According to the spec, processors which do not support VMX
2003 * should throw a #GP(0) when VMX capability MSRs are read.
2004 */
2005 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2006 return 1;
2007 }
2008
2009 switch (msr_index) {
2010 case MSR_IA32_FEATURE_CONTROL:
2011 *pdata = 0;
2012 break;
2013 case MSR_IA32_VMX_BASIC:
2014 /*
2015 * This MSR reports some information about VMX support. We
2016 * should return information about the VMX we emulate for the
2017 * guest, and the VMCS structure we give it - not about the
2018 * VMX support of the underlying hardware.
2019 */
2020 *pdata = VMCS12_REVISION |
2021 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2022 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2023 break;
2024 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2025 case MSR_IA32_VMX_PINBASED_CTLS:
2026 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2027 nested_vmx_pinbased_ctls_high);
2028 break;
2029 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2030 case MSR_IA32_VMX_PROCBASED_CTLS:
2031 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2032 nested_vmx_procbased_ctls_high);
2033 break;
2034 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2035 case MSR_IA32_VMX_EXIT_CTLS:
2036 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2037 nested_vmx_exit_ctls_high);
2038 break;
2039 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2040 case MSR_IA32_VMX_ENTRY_CTLS:
2041 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2042 nested_vmx_entry_ctls_high);
2043 break;
2044 case MSR_IA32_VMX_MISC:
2045 *pdata = 0;
2046 break;
2047 /*
2048 * These MSRs specify bits which the guest must keep fixed (on or off)
2049 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2050 * We picked the standard core2 setting.
2051 */
2052#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2053#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2054 case MSR_IA32_VMX_CR0_FIXED0:
2055 *pdata = VMXON_CR0_ALWAYSON;
2056 break;
2057 case MSR_IA32_VMX_CR0_FIXED1:
2058 *pdata = -1ULL;
2059 break;
2060 case MSR_IA32_VMX_CR4_FIXED0:
2061 *pdata = VMXON_CR4_ALWAYSON;
2062 break;
2063 case MSR_IA32_VMX_CR4_FIXED1:
2064 *pdata = -1ULL;
2065 break;
2066 case MSR_IA32_VMX_VMCS_ENUM:
2067 *pdata = 0x1f;
2068 break;
2069 case MSR_IA32_VMX_PROCBASED_CTLS2:
2070 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2071 nested_vmx_secondary_ctls_high);
2072 break;
2073 case MSR_IA32_VMX_EPT_VPID_CAP:
2074 /* Currently, no nested ept or nested vpid */
2075 *pdata = 0;
2076 break;
2077 default:
2078 return 0;
2079 }
2080
2081 return 1;
2082}
2083
2084static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2085{
2086 if (!nested_vmx_allowed(vcpu))
2087 return 0;
2088
2089 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2090 /* TODO: the right thing. */
2091 return 1;
2092 /*
2093 * No need to treat VMX capability MSRs specially: If we don't handle
2094 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2095 */
2096 return 0;
2097}
2098
6aa8b732
AK		 2099/*
2100 * Reads an msr value (of 'msr_index') into 'pdata'.
2101 * Returns 0 on success, non-0 otherwise.
2102 * Assumes vcpu_load() was already called.
2103 */
2104static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2105{
2106 u64 data;
26bb0981 2107 struct shared_msr_entry *msr;
6aa8b732
AK		 2108
2109 if (!pdata) {
2110 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2111 return -EINVAL;
2112 }
2113
2114 switch (msr_index) {
05b3e0c2 2115#ifdef CONFIG_X86_64
6aa8b732
AK		 2116 case MSR_FS_BASE:
2117 data = vmcs_readl(GUEST_FS_BASE);
2118 break;
2119 case MSR_GS_BASE:
2120 data = vmcs_readl(GUEST_GS_BASE);
2121 break;
44ea2b17
AK		 2122 case MSR_KERNEL_GS_BASE:
2123 vmx_load_host_state(to_vmx(vcpu));
2124 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2125 break;
26bb0981 2126#endif
6aa8b732 2127 case MSR_EFER:
3bab1f5d 2128 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2129 case MSR_IA32_TSC:
6aa8b732
AK		 2130 data = guest_read_tsc();
2131 break;
2132 case MSR_IA32_SYSENTER_CS:
2133 data = vmcs_read32(GUEST_SYSENTER_CS);
2134 break;
2135 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2136 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2137 break;
2138 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2139 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2140 break;
4e47c7a6
SY		 2141 case MSR_TSC_AUX:
2142 if (!to_vmx(vcpu)->rdtscp_enabled)
2143 return 1;
2144 /* Otherwise falls through */
6aa8b732 2145 default:
b87a51ae
NHE		 2146 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2147 return 0;
8b9cf98c 2148 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2149 if (msr) {
2150 data = msr->data;
2151 break;
6aa8b732 2152 }
3bab1f5d 2153 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2154 }
2155
2156 *pdata = data;
2157 return 0;
2158}
2159
2160/*
2161 * Writes msr value into into the appropriate "register".
2162 * Returns 0 on success, non-0 otherwise.
2163 * Assumes vcpu_load() was already called.
2164 */
2165static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2166{
a2fa3e9f 2167 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2168 struct shared_msr_entry *msr;
2cc51560
ED		 2169 int ret = 0;
2170
6aa8b732 2171 switch (msr_index) {
3bab1f5d 2172 case MSR_EFER:
2cc51560 2173 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2174 break;
16175a79 2175#ifdef CONFIG_X86_64
6aa8b732 2176 case MSR_FS_BASE:
2fb92db1 2177 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2178 vmcs_writel(GUEST_FS_BASE, data);
2179 break;
2180 case MSR_GS_BASE:
2fb92db1 2181 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2182 vmcs_writel(GUEST_GS_BASE, data);
2183 break;
44ea2b17
AK		 2184 case MSR_KERNEL_GS_BASE:
2185 vmx_load_host_state(vmx);
2186 vmx->msr_guest_kernel_gs_base = data;
2187 break;
6aa8b732
AK		 2188#endif
2189 case MSR_IA32_SYSENTER_CS:
2190 vmcs_write32(GUEST_SYSENTER_CS, data);
2191 break;
2192 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2193 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2194 break;
2195 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2196 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2197 break;
af24a4e4 2198 case MSR_IA32_TSC:
99e3e30a 2199 kvm_write_tsc(vcpu, data);
6aa8b732 2200 break;
468d472f
SY		 2201 case MSR_IA32_CR_PAT:
2202 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2203 vmcs_write64(GUEST_IA32_PAT, data);
2204 vcpu->arch.pat = data;
2205 break;
2206 }
4e47c7a6
SY		 2207 ret = kvm_set_msr_common(vcpu, msr_index, data);
2208 break;
2209 case MSR_TSC_AUX:
2210 if (!vmx->rdtscp_enabled)
2211 return 1;
2212 /* Check reserved bit, higher 32 bits should be zero */
2213 if ((data >> 32) != 0)
2214 return 1;
2215 /* Otherwise falls through */
6aa8b732 2216 default:
b87a51ae
NHE		 2217 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2218 break;
8b9cf98c 2219 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2220 if (msr) {
2221 msr->data = data;
2222 break;
6aa8b732 2223 }
2cc51560 2224 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2225 }
2226
2cc51560 2227 return ret;
6aa8b732
AK		 2228}
2229
5fdbf976 2230static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2231{
5fdbf976
MT		 2232 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2233 switch (reg) {
2234 case VCPU_REGS_RSP:
2235 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2236 break;
2237 case VCPU_REGS_RIP:
2238 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2239 break;
6de4f3ad
AK		 2240 case VCPU_EXREG_PDPTR:
2241 if (enable_ept)
2242 ept_save_pdptrs(vcpu);
2243 break;
5fdbf976
MT		 2244 default:
2245 break;
2246 }
6aa8b732
AK		 2247}
2248
355be0b9 2249static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2250{
ae675ef0
JK		 2251 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2252 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2253 else
2254 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2255
abd3f2d6 2256 update_exception_bitmap(vcpu);
6aa8b732
AK		 2257}
2258
2259static __init int cpu_has_kvm_support(void)
2260{
6210e37b 2261 return cpu_has_vmx();
6aa8b732
AK		 2262}
2263
2264static __init int vmx_disabled_by_bios(void)
2265{
2266 u64 msr;
2267
2268 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2269 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2270 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2271 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2272 && tboot_enabled())
2273 return 1;
23f3e991 2274 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2275 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2276 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2277 && !tboot_enabled()) {
2278 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2279 "activate TXT before enabling KVM\n");
cafd6659 2280 return 1;
f9335afe 2281 }
23f3e991
JC		 2282 /* launched w/o TXT and VMX disabled */
2283 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2284 && !tboot_enabled())
2285 return 1;
cafd6659
SW		 2286 }
2287
2288 return 0;
6aa8b732
AK		 2289}
2290
7725b894
DX		 2291static void kvm_cpu_vmxon(u64 addr)
2292{
2293 asm volatile (ASM_VMX_VMXON_RAX
2294 : : "a"(&addr), "m"(addr)
2295 : "memory", "cc");
2296}
2297
10474ae8 2298static int hardware_enable(void *garbage)
6aa8b732
AK		 2299{
2300 int cpu = raw_smp_processor_id();
2301 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2302 u64 old, test_bits;
6aa8b732 2303
10474ae8
AG		 2304 if (read_cr4() & X86_CR4_VMXE)
2305 return -EBUSY;
2306
d462b819 2307 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2308 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2309
2310 test_bits = FEATURE_CONTROL_LOCKED;
2311 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2312 if (tboot_enabled())
2313 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2314
2315 if ((old & test_bits) != test_bits) {
6aa8b732 2316 /* enable and lock */
cafd6659
SW		 2317 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2318 }
66aee91a 2319 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2320
4610c9cc
DX		 2321 if (vmm_exclusive) {
2322 kvm_cpu_vmxon(phys_addr);
2323 ept_sync_global();
2324 }
10474ae8 2325
3444d7da
AK		 2326 store_gdt(&__get_cpu_var(host_gdt));
2327
10474ae8 2328 return 0;
6aa8b732
AK		 2329}
2330
d462b819 2331static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2332{
2333 int cpu = raw_smp_processor_id();
d462b819 2334 struct loaded_vmcs *v, *n;
543e4243 2335
d462b819
NHE		 2336 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2337 loaded_vmcss_on_cpu_link)
2338 __loaded_vmcs_clear(v);
543e4243
AK		 2339}
2340
710ff4a8
EH		 2341
2342/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2343 * tricks.
2344 */
2345static void kvm_cpu_vmxoff(void)
6aa8b732 2346{
4ecac3fd 2347 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2348}
2349
710ff4a8
EH		 2350static void hardware_disable(void *garbage)
2351{
4610c9cc 2352 if (vmm_exclusive) {
d462b819 2353 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2354 kvm_cpu_vmxoff();
2355 }
7725b894 2356 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2357}
2358
1c3d14fe 2359static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2360 u32 msr, u32 *result)
1c3d14fe
YS		 2361{
2362 u32 vmx_msr_low, vmx_msr_high;
2363 u32 ctl = ctl_min | ctl_opt;
2364
2365 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2366
2367 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2368 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2369
2370 /* Ensure minimum (required) set of control bits are supported. */
2371 if (ctl_min & ~ctl)
002c7f7c 2372 return -EIO;
1c3d14fe
YS		 2373
2374 *result = ctl;
2375 return 0;
2376}
2377
110312c8
AK		 2378static __init bool allow_1_setting(u32 msr, u32 ctl)
2379{
2380 u32 vmx_msr_low, vmx_msr_high;
2381
2382 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2383 return vmx_msr_high & ctl;
2384}
2385
002c7f7c 2386static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2387{
2388 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2389 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2390 u32 _pin_based_exec_control = 0;
2391 u32 _cpu_based_exec_control = 0;
f78e0e2e 2392 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2393 u32 _vmexit_control = 0;
2394 u32 _vmentry_control = 0;
2395
2396 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2397 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2398 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2399 &_pin_based_exec_control) < 0)
002c7f7c 2400 return -EIO;
1c3d14fe 2401
443381a8 2402 min =
1c3d14fe
YS		 2403#ifdef CONFIG_X86_64
2404 CPU_BASED_CR8_LOAD_EXITING |
2405 CPU_BASED_CR8_STORE_EXITING |
2406#endif
d56f546d
SY		 2407 CPU_BASED_CR3_LOAD_EXITING |
2408 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2409 CPU_BASED_USE_IO_BITMAPS |
2410 CPU_BASED_MOV_DR_EXITING |
a7052897 2411 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2412 CPU_BASED_MWAIT_EXITING |
2413 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2414 CPU_BASED_INVLPG_EXITING |
2415 CPU_BASED_RDPMC_EXITING;
443381a8
AL		 2416
2417 if (yield_on_hlt)
2418 min |= CPU_BASED_HLT_EXITING;
2419
f78e0e2e 2420 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2421 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2422 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2423 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2424 &_cpu_based_exec_control) < 0)
002c7f7c 2425 return -EIO;
6e5d865c
YS		 2426#ifdef CONFIG_X86_64
2427 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2428 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2429 ~CPU_BASED_CR8_STORE_EXITING;
2430#endif
f78e0e2e 2431 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2432 min2 = 0;
2433 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2434 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2435 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2436 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2437 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2438 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2439 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2440 if (adjust_vmx_controls(min2, opt2,
2441 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2442 &_cpu_based_2nd_exec_control) < 0)
2443 return -EIO;
2444 }
2445#ifndef CONFIG_X86_64
2446 if (!(_cpu_based_2nd_exec_control &
2447 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2448 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2449#endif
d56f546d 2450 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2451 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2452 enabled */
5fff7d27
GN		 2453 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2454 CPU_BASED_CR3_STORE_EXITING |
2455 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2456 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2457 vmx_capability.ept, vmx_capability.vpid);
2458 }
1c3d14fe
YS		 2459
2460 min = 0;
2461#ifdef CONFIG_X86_64
2462 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2463#endif
468d472f 2464 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2465 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2466 &_vmexit_control) < 0)
002c7f7c 2467 return -EIO;
1c3d14fe 2468
468d472f
SY		 2469 min = 0;
2470 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2471 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2472 &_vmentry_control) < 0)
002c7f7c 2473 return -EIO;
6aa8b732 2474
c68876fd 2475 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2476
2477 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2478 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2479 return -EIO;
1c3d14fe
YS		 2480
2481#ifdef CONFIG_X86_64
2482 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2483 if (vmx_msr_high & (1u<<16))
002c7f7c 2484 return -EIO;
1c3d14fe
YS		 2485#endif
2486
2487 /* Require Write-Back (WB) memory type for VMCS accesses. */
2488 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2489 return -EIO;
1c3d14fe 2490
002c7f7c
YS		 2491 vmcs_conf->size = vmx_msr_high & 0x1fff;
2492 vmcs_conf->order = get_order(vmcs_config.size);
2493 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2494
002c7f7c
YS		 2495 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2496 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2497 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2498 vmcs_conf->vmexit_ctrl = _vmexit_control;
2499 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2500
110312c8
AK		 2501 cpu_has_load_ia32_efer =
2502 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2503 VM_ENTRY_LOAD_IA32_EFER)
2504 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2505 VM_EXIT_LOAD_IA32_EFER);
2506
8bf00a52
GN		 2507 cpu_has_load_perf_global_ctrl =
2508 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2509 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2510 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2511 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2512
2513 /*
2514 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2515 * but due to arrata below it can't be used. Workaround is to use
2516 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2517 *
2518 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2519 *
2520 * AAK155 (model 26)
2521 * AAP115 (model 30)
2522 * AAT100 (model 37)
2523 * BC86,AAY89,BD102 (model 44)
2524 * BA97 (model 46)
2525 *
2526 */
2527 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2528 switch (boot_cpu_data.x86_model) {
2529 case 26:
2530 case 30:
2531 case 37:
2532 case 44:
2533 case 46:
2534 cpu_has_load_perf_global_ctrl = false;
2535 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2536 "does not work properly. Using workaround\n");
2537 break;
2538 default:
2539 break;
2540 }
2541 }
2542
1c3d14fe 2543 return 0;
c68876fd 2544}
6aa8b732
AK		 2545
2546static struct vmcs *alloc_vmcs_cpu(int cpu)
2547{
2548 int node = cpu_to_node(cpu);
2549 struct page *pages;
2550 struct vmcs *vmcs;
2551
6484eb3e 2552 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2553 if (!pages)
2554 return NULL;
2555 vmcs = page_address(pages);
1c3d14fe
YS		 2556 memset(vmcs, 0, vmcs_config.size);
2557 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2558 return vmcs;
2559}
2560
2561static struct vmcs *alloc_vmcs(void)
2562{
d3b2c338 2563 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2564}
2565
2566static void free_vmcs(struct vmcs *vmcs)
2567{
1c3d14fe 2568 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2569}
2570
d462b819
NHE		 2571/*
2572 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2573 */
2574static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2575{
2576 if (!loaded_vmcs->vmcs)
2577 return;
2578 loaded_vmcs_clear(loaded_vmcs);
2579 free_vmcs(loaded_vmcs->vmcs);
2580 loaded_vmcs->vmcs = NULL;
2581}
2582
39959588 2583static void free_kvm_area(void)
6aa8b732
AK		 2584{
2585 int cpu;
2586
3230bb47 2587 for_each_possible_cpu(cpu) {
6aa8b732 2588 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2589 per_cpu(vmxarea, cpu) = NULL;
2590 }
6aa8b732
AK		 2591}
2592
6aa8b732
AK		 2593static __init int alloc_kvm_area(void)
2594{
2595 int cpu;
2596
3230bb47 2597 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2598 struct vmcs *vmcs;
2599
2600 vmcs = alloc_vmcs_cpu(cpu);
2601 if (!vmcs) {
2602 free_kvm_area();
2603 return -ENOMEM;
2604 }
2605
2606 per_cpu(vmxarea, cpu) = vmcs;
2607 }
2608 return 0;
2609}
2610
2611static __init int hardware_setup(void)
2612{
002c7f7c
YS		 2613 if (setup_vmcs_config(&vmcs_config) < 0)
2614 return -EIO;
50a37eb4
JR		 2615
2616 if (boot_cpu_has(X86_FEATURE_NX))
2617 kvm_enable_efer_bits(EFER_NX);
2618
93ba03c2
SY		 2619 if (!cpu_has_vmx_vpid())
2620 enable_vpid = 0;
2621
4bc9b982
SY		 2622 if (!cpu_has_vmx_ept() ||
2623 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2624 enable_ept = 0;
3a624e29
NK		 2625 enable_unrestricted_guest = 0;
2626 }
2627
2628 if (!cpu_has_vmx_unrestricted_guest())
2629 enable_unrestricted_guest = 0;
93ba03c2
SY		 2630
2631 if (!cpu_has_vmx_flexpriority())
2632 flexpriority_enabled = 0;
2633
95ba8273
GN		 2634 if (!cpu_has_vmx_tpr_shadow())
2635 kvm_x86_ops->update_cr8_intercept = NULL;
2636
54dee993
MT		 2637 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2638 kvm_disable_largepages();
2639
4b8d54f9
ZE		 2640 if (!cpu_has_vmx_ple())
2641 ple_gap = 0;
2642
b87a51ae
NHE		 2643 if (nested)
2644 nested_vmx_setup_ctls_msrs();
2645
6aa8b732
AK		 2646 return alloc_kvm_area();
2647}
2648
2649static __exit void hardware_unsetup(void)
2650{
2651 free_kvm_area();
2652}
2653
6aa8b732
AK		 2654static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2655{
2656 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2657
6af11b9e 2658 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2659 vmcs_write16(sf->selector, save->selector);
2660 vmcs_writel(sf->base, save->base);
2661 vmcs_write32(sf->limit, save->limit);
2662 vmcs_write32(sf->ar_bytes, save->ar);
2663 } else {
2664 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2665 << AR_DPL_SHIFT;
2666 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2667 }
2668}
2669
2670static void enter_pmode(struct kvm_vcpu *vcpu)
2671{
2672 unsigned long flags;
a89a8fb9 2673 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2674
a89a8fb9 2675 vmx->emulation_required = 1;
7ffd92c5 2676 vmx->rmode.vm86_active = 0;
6aa8b732 2677
2fb92db1
AK		 2678 vmx_segment_cache_clear(vmx);
2679
d0ba64f9 2680 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2681 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2682 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2683 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2684
2685 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2686 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2687 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2688 vmcs_writel(GUEST_RFLAGS, flags);
2689
66aee91a
RR		 2690 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2691 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2692
2693 update_exception_bitmap(vcpu);
2694
a89a8fb9
MG		 2695 if (emulate_invalid_guest_state)
2696 return;
2697
7ffd92c5
AK		 2698 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2699 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2700 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2701 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2702
2fb92db1
AK		 2703 vmx_segment_cache_clear(vmx);
2704
6aa8b732
AK		 2705 vmcs_write16(GUEST_SS_SELECTOR, 0);
2706 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2707
2708 vmcs_write16(GUEST_CS_SELECTOR,
2709 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2710 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2711}
2712
d77c26fc 2713static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2714{
bfc6d222 2715 if (!kvm->arch.tss_addr) {
bc6678a3 2716 struct kvm_memslots *slots;
28a37544 2717 struct kvm_memory_slot *slot;
bc6678a3
MT		 2718 gfn_t base_gfn;
2719
90d83dc3 2720 slots = kvm_memslots(kvm);
28a37544
XG		 2721 slot = id_to_memslot(slots, 0);
2722 base_gfn = slot->base_gfn + slot->npages - 3;
2723
cbc94022
IE		 2724 return base_gfn << PAGE_SHIFT;
2725 }
bfc6d222 2726 return kvm->arch.tss_addr;
6aa8b732
AK		 2727}
2728
2729static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2730{
2731 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2732
2733 save->selector = vmcs_read16(sf->selector);
2734 save->base = vmcs_readl(sf->base);
2735 save->limit = vmcs_read32(sf->limit);
2736 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2737 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2738 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2739 vmcs_write32(sf->limit, 0xffff);
2740 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2741 if (save->base & 0xf)
2742 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2743 " aligned when entering protected mode (seg=%d)",
2744 seg);
6aa8b732
AK		 2745}
2746
2747static void enter_rmode(struct kvm_vcpu *vcpu)
2748{
2749 unsigned long flags;
a89a8fb9 2750 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2751
3a624e29
NK		 2752 if (enable_unrestricted_guest)
2753 return;
2754
a89a8fb9 2755 vmx->emulation_required = 1;
7ffd92c5 2756 vmx->rmode.vm86_active = 1;
6aa8b732 2757
776e58ea
GN		 2758 /*
2759 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2760 * vcpu. Call it here with phys address pointing 16M below 4G.
2761 */
2762 if (!vcpu->kvm->arch.tss_addr) {
2763 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2764 "called before entering vcpu\n");
2765 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2766 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2767 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2768 }
2769
2fb92db1
AK		 2770 vmx_segment_cache_clear(vmx);
2771
d0ba64f9 2772 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2773 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2774 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2775
7ffd92c5 2776 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2777 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2778
7ffd92c5 2779 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2780 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2781
2782 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2783 vmx->rmode.save_rflags = flags;
6aa8b732 2784
053de044 2785 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2786
2787 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2788 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2789 update_exception_bitmap(vcpu);
2790
a89a8fb9
MG		 2791 if (emulate_invalid_guest_state)
2792 goto continue_rmode;
2793
6aa8b732
AK		 2794 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2795 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2796 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2797
2798 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2799 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2800 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2801 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2802 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2803
7ffd92c5
AK		 2804 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2805 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2806 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2807 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2808
a89a8fb9 2809continue_rmode:
8668a3c4 2810 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2811}
2812
401d10de
AS		 2813static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2814{
2815 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2816 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2817
2818 if (!msr)
2819 return;
401d10de 2820
44ea2b17
AK		 2821 /*
2822 * Force kernel_gs_base reloading before EFER changes, as control
2823 * of this msr depends on is_long_mode().
2824 */
2825 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2826 vcpu->arch.efer = efer;
401d10de
AS		 2827 if (efer & EFER_LMA) {
2828 vmcs_write32(VM_ENTRY_CONTROLS,
2829 vmcs_read32(VM_ENTRY_CONTROLS) |
2830 VM_ENTRY_IA32E_MODE);
2831 msr->data = efer;
2832 } else {
2833 vmcs_write32(VM_ENTRY_CONTROLS,
2834 vmcs_read32(VM_ENTRY_CONTROLS) &
2835 ~VM_ENTRY_IA32E_MODE);
2836
2837 msr->data = efer & ~EFER_LME;
2838 }
2839 setup_msrs(vmx);
2840}
2841
05b3e0c2 2842#ifdef CONFIG_X86_64
6aa8b732
AK		 2843
2844static void enter_lmode(struct kvm_vcpu *vcpu)
2845{
2846 u32 guest_tr_ar;
2847
2fb92db1
AK		 2848 vmx_segment_cache_clear(to_vmx(vcpu));
2849
6aa8b732
AK		 2850 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2851 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2852 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2853 __func__);
6aa8b732
AK		 2854 vmcs_write32(GUEST_TR_AR_BYTES,
2855 (guest_tr_ar & ~AR_TYPE_MASK)
2856 | AR_TYPE_BUSY_64_TSS);
2857 }
da38f438 2858 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2859}
2860
2861static void exit_lmode(struct kvm_vcpu *vcpu)
2862{
6aa8b732
AK		 2863 vmcs_write32(VM_ENTRY_CONTROLS,
2864 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2865 & ~VM_ENTRY_IA32E_MODE);
da38f438 2866 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2867}
2868
2869#endif
2870
2384d2b3
SY		 2871static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2872{
b9d762fa 2873 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2874 if (enable_ept) {
2875 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2876 return;
4e1096d2 2877 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2878 }
2384d2b3
SY		 2879}
2880
e8467fda
AK		 2881static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2882{
2883 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2884
2885 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2886 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2887}
2888
aff48baa
AK		 2889static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2890{
2891 if (enable_ept && is_paging(vcpu))
2892 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2893 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2894}
2895
25c4c276 2896static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2897{
fc78f519
AK		 2898 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2899
2900 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2901 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2902}
2903
1439442c
SY		 2904static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2905{
6de4f3ad
AK		 2906 if (!test_bit(VCPU_EXREG_PDPTR,
2907 (unsigned long *)&vcpu->arch.regs_dirty))
2908 return;
2909
1439442c 2910 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2911 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2912 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2913 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2914 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2915 }
2916}
2917
8f5d549f
AK		 2918static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2919{
2920 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2921 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2922 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2923 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2924 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2925 }
6de4f3ad
AK		 2926
2927 __set_bit(VCPU_EXREG_PDPTR,
2928 (unsigned long *)&vcpu->arch.regs_avail);
2929 __set_bit(VCPU_EXREG_PDPTR,
2930 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2931}
2932
5e1746d6 2933static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2934
2935static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2936 unsigned long cr0,
2937 struct kvm_vcpu *vcpu)
2938{
5233dd51
MT		 2939 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2940 vmx_decache_cr3(vcpu);
1439442c
SY		 2941 if (!(cr0 & X86_CR0_PG)) {
2942 /* From paging/starting to nonpaging */
2943 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2944 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2945 (CPU_BASED_CR3_LOAD_EXITING |
2946 CPU_BASED_CR3_STORE_EXITING));
2947 vcpu->arch.cr0 = cr0;
fc78f519 2948 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2949 } else if (!is_paging(vcpu)) {
2950 /* From nonpaging to paging */
2951 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2952 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2953 ~(CPU_BASED_CR3_LOAD_EXITING |
2954 CPU_BASED_CR3_STORE_EXITING));
2955 vcpu->arch.cr0 = cr0;
fc78f519 2956 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2957 }
95eb84a7
SY		 2958
2959 if (!(cr0 & X86_CR0_WP))
2960 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2961}
2962
6aa8b732
AK		 2963static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2964{
7ffd92c5 2965 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2966 unsigned long hw_cr0;
2967
2968 if (enable_unrestricted_guest)
2969 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2970 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2971 else
2972 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2973
7ffd92c5 2974 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2975 enter_pmode(vcpu);
2976
7ffd92c5 2977 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2978 enter_rmode(vcpu);
2979
05b3e0c2 2980#ifdef CONFIG_X86_64
f6801dff 2981 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2982 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2983 enter_lmode(vcpu);
707d92fa 2984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2985 exit_lmode(vcpu);
2986 }
2987#endif
2988
089d034e 2989 if (enable_ept)
1439442c
SY		 2990 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2991
02daab21 2992 if (!vcpu->fpu_active)
81231c69 2993 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2994
6aa8b732 2995 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2996 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2997 vcpu->arch.cr0 = cr0;
69c73028 2998 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2999}
3000
1439442c
SY		 3001static u64 construct_eptp(unsigned long root_hpa)
3002{
3003 u64 eptp;
3004
3005 /* TODO write the value reading from MSR */
3006 eptp = VMX_EPT_DEFAULT_MT |
3007 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3008 eptp |= (root_hpa & PAGE_MASK);
3009
3010 return eptp;
3011}
3012
6aa8b732
AK		 3013static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3014{
1439442c
SY		 3015 unsigned long guest_cr3;
3016 u64 eptp;
3017
3018 guest_cr3 = cr3;
089d034e 3019 if (enable_ept) {
1439442c
SY		 3020 eptp = construct_eptp(cr3);
3021 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3022 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3023 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3024 ept_load_pdptrs(vcpu);
1439442c
SY		 3025 }
3026
2384d2b3 3027 vmx_flush_tlb(vcpu);
1439442c 3028 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3029}
3030
5e1746d6 3031static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3032{
7ffd92c5 3033 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3034 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3035
5e1746d6
NHE		 3036 if (cr4 & X86_CR4_VMXE) {
3037 /*
3038 * To use VMXON (and later other VMX instructions), a guest
3039 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3040 * So basically the check on whether to allow nested VMX
3041 * is here.
3042 */
3043 if (!nested_vmx_allowed(vcpu))
3044 return 1;
3045 } else if (to_vmx(vcpu)->nested.vmxon)
3046 return 1;
3047
ad312c7c 3048 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3049 if (enable_ept) {
3050 if (!is_paging(vcpu)) {
3051 hw_cr4 &= ~X86_CR4_PAE;
3052 hw_cr4 |= X86_CR4_PSE;
3053 } else if (!(cr4 & X86_CR4_PAE)) {
3054 hw_cr4 &= ~X86_CR4_PAE;
3055 }
3056 }
1439442c
SY		 3057
3058 vmcs_writel(CR4_READ_SHADOW, cr4);
3059 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3060 return 0;
6aa8b732
AK		 3061}
3062
6aa8b732
AK		 3063static void vmx_get_segment(struct kvm_vcpu *vcpu,
3064 struct kvm_segment *var, int seg)
3065{
a9179499 3066 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3067 struct kvm_save_segment *save;
6aa8b732
AK		 3068 u32 ar;
3069
a9179499
AK		 3070 if (vmx->rmode.vm86_active
3071 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3072 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3073 || seg == VCPU_SREG_GS)
3074 && !emulate_invalid_guest_state) {
3075 switch (seg) {
3076 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3077 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3078 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3079 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3080 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3081 default: BUG();
3082 }
3083 var->selector = save->selector;
3084 var->base = save->base;
3085 var->limit = save->limit;
3086 ar = save->ar;
3087 if (seg == VCPU_SREG_TR
2fb92db1 3088 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3089 goto use_saved_rmode_seg;
3090 }
2fb92db1
AK		 3091 var->base = vmx_read_guest_seg_base(vmx, seg);
3092 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3093 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3094 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3095use_saved_rmode_seg:
9fd4a3b7 3096 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3097 ar = 0;
3098 var->type = ar & 15;
3099 var->s = (ar >> 4) & 1;
3100 var->dpl = (ar >> 5) & 3;
3101 var->present = (ar >> 7) & 1;
3102 var->avl = (ar >> 12) & 1;
3103 var->l = (ar >> 13) & 1;
3104 var->db = (ar >> 14) & 1;
3105 var->g = (ar >> 15) & 1;
3106 var->unusable = (ar >> 16) & 1;
3107}
3108
a9179499
AK		 3109static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3110{
a9179499
AK		 3111 struct kvm_segment s;
3112
3113 if (to_vmx(vcpu)->rmode.vm86_active) {
3114 vmx_get_segment(vcpu, &s, seg);
3115 return s.base;
3116 }
2fb92db1 3117 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3118}
3119
69c73028 3120static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3121{
3eeb3288 3122 if (!is_protmode(vcpu))
2e4d2653
IE		 3123 return 0;
3124
f4c63e5d
AK		 3125 if (!is_long_mode(vcpu)
3126 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3127 return 3;
3128
2fb92db1 3129 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3130}
3131
69c73028
AK		 3132static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3133{
3134 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3135 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3136 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3137 }
3138 return to_vmx(vcpu)->cpl;
3139}
3140
3141
653e3108 3142static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3143{
6aa8b732
AK		 3144 u32 ar;
3145
653e3108 3146 if (var->unusable)
6aa8b732
AK		 3147 ar = 1 << 16;
3148 else {
3149 ar = var->type & 15;
3150 ar |= (var->s & 1) << 4;
3151 ar |= (var->dpl & 3) << 5;
3152 ar |= (var->present & 1) << 7;
3153 ar |= (var->avl & 1) << 12;
3154 ar |= (var->l & 1) << 13;
3155 ar |= (var->db & 1) << 14;
3156 ar |= (var->g & 1) << 15;
3157 }
f7fbf1fd
UL		 3158 if (ar == 0) /* a 0 value means unusable */
3159 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3160
3161 return ar;
3162}
3163
3164static void vmx_set_segment(struct kvm_vcpu *vcpu,
3165 struct kvm_segment *var, int seg)
3166{
7ffd92c5 3167 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3168 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3169 u32 ar;
3170
2fb92db1
AK		 3171 vmx_segment_cache_clear(vmx);
3172
7ffd92c5 3173 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3174 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3175 vmx->rmode.tr.selector = var->selector;
3176 vmx->rmode.tr.base = var->base;
3177 vmx->rmode.tr.limit = var->limit;
3178 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3179 return;
3180 }
3181 vmcs_writel(sf->base, var->base);
3182 vmcs_write32(sf->limit, var->limit);
3183 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3184 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3185 /*
3186 * Hack real-mode segments into vm86 compatibility.
3187 */
3188 if (var->base == 0xffff0000 && var->selector == 0xf000)
3189 vmcs_writel(sf->base, 0xf0000);
3190 ar = 0xf3;
3191 } else
3192 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3193
3194 /*
3195 * Fix the "Accessed" bit in AR field of segment registers for older
3196 * qemu binaries.
3197 * IA32 arch specifies that at the time of processor reset the
3198 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3199 * is setting it to 0 in the usedland code. This causes invalid guest
3200 * state vmexit when "unrestricted guest" mode is turned on.
3201 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3202 * tree. Newer qemu binaries with that qemu fix would not need this
3203 * kvm hack.
3204 */
3205 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3206 ar |= 0x1; /* Accessed */
3207
6aa8b732 3208 vmcs_write32(sf->ar_bytes, ar);
69c73028 3209 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3210}
3211
6aa8b732
AK		 3212static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3213{
2fb92db1 3214 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3215
3216 *db = (ar >> 14) & 1;
3217 *l = (ar >> 13) & 1;
3218}
3219
89a27f4d 3220static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3221{
89a27f4d
GN		 3222 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3223 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3224}
3225
89a27f4d 3226static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3227{
89a27f4d
GN		 3228 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3229 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3230}
3231
89a27f4d 3232static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3233{
89a27f4d
GN		 3234 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3235 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3236}
3237
89a27f4d 3238static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3239{
89a27f4d
GN		 3240 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3241 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3242}
3243
648dfaa7
MG		 3244static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3245{
3246 struct kvm_segment var;
3247 u32 ar;
3248
3249 vmx_get_segment(vcpu, &var, seg);
3250 ar = vmx_segment_access_rights(&var);
3251
3252 if (var.base != (var.selector << 4))
3253 return false;
3254 if (var.limit != 0xffff)
3255 return false;
3256 if (ar != 0xf3)
3257 return false;
3258
3259 return true;
3260}
3261
3262static bool code_segment_valid(struct kvm_vcpu *vcpu)
3263{
3264 struct kvm_segment cs;
3265 unsigned int cs_rpl;
3266
3267 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3269
1872a3f4
AK		 3270 if (cs.unusable)
3271 return false;
648dfaa7
MG		 3272 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3273 return false;
3274 if (!cs.s)
3275 return false;
1872a3f4 3276 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3277 if (cs.dpl > cs_rpl)
3278 return false;
1872a3f4 3279 } else {
648dfaa7
MG		 3280 if (cs.dpl != cs_rpl)
3281 return false;
3282 }
3283 if (!cs.present)
3284 return false;
3285
3286 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3287 return true;
3288}
3289
3290static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3291{
3292 struct kvm_segment ss;
3293 unsigned int ss_rpl;
3294
3295 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3296 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3297
1872a3f4
AK		 3298 if (ss.unusable)
3299 return true;
3300 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3301 return false;
3302 if (!ss.s)
3303 return false;
3304 if (ss.dpl != ss_rpl) /* DPL != RPL */
3305 return false;
3306 if (!ss.present)
3307 return false;
3308
3309 return true;
3310}
3311
3312static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3313{
3314 struct kvm_segment var;
3315 unsigned int rpl;
3316
3317 vmx_get_segment(vcpu, &var, seg);
3318 rpl = var.selector & SELECTOR_RPL_MASK;
3319
1872a3f4
AK		 3320 if (var.unusable)
3321 return true;
648dfaa7
MG		 3322 if (!var.s)
3323 return false;
3324 if (!var.present)
3325 return false;
3326 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3327 if (var.dpl < rpl) /* DPL < RPL */
3328 return false;
3329 }
3330
3331 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3332 * rights flags
3333 */
3334 return true;
3335}
3336
3337static bool tr_valid(struct kvm_vcpu *vcpu)
3338{
3339 struct kvm_segment tr;
3340
3341 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3342
1872a3f4
AK		 3343 if (tr.unusable)
3344 return false;
648dfaa7
MG		 3345 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3346 return false;
1872a3f4 3347 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3348 return false;
3349 if (!tr.present)
3350 return false;
3351
3352 return true;
3353}
3354
3355static bool ldtr_valid(struct kvm_vcpu *vcpu)
3356{
3357 struct kvm_segment ldtr;
3358
3359 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3360
1872a3f4
AK		 3361 if (ldtr.unusable)
3362 return true;
648dfaa7
MG		 3363 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3364 return false;
3365 if (ldtr.type != 2)
3366 return false;
3367 if (!ldtr.present)
3368 return false;
3369
3370 return true;
3371}
3372
3373static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3374{
3375 struct kvm_segment cs, ss;
3376
3377 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3378 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3379
3380 return ((cs.selector & SELECTOR_RPL_MASK) ==
3381 (ss.selector & SELECTOR_RPL_MASK));
3382}
3383
3384/*
3385 * Check if guest state is valid. Returns true if valid, false if
3386 * not.
3387 * We assume that registers are always usable
3388 */
3389static bool guest_state_valid(struct kvm_vcpu *vcpu)
3390{
3391 /* real mode guest state checks */
3eeb3288 3392 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3394 return false;
3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3396 return false;
3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3398 return false;
3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3400 return false;
3401 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3402 return false;
3403 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3404 return false;
3405 } else {
3406 /* protected mode guest state checks */
3407 if (!cs_ss_rpl_check(vcpu))
3408 return false;
3409 if (!code_segment_valid(vcpu))
3410 return false;
3411 if (!stack_segment_valid(vcpu))
3412 return false;
3413 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3414 return false;
3415 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3416 return false;
3417 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3418 return false;
3419 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3420 return false;
3421 if (!tr_valid(vcpu))
3422 return false;
3423 if (!ldtr_valid(vcpu))
3424 return false;
3425 }
3426 /* TODO:
3427 * - Add checks on RIP
3428 * - Add checks on RFLAGS
3429 */
3430
3431 return true;
3432}
3433
d77c26fc 3434static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3435{
40dcaa9f 3436 gfn_t fn;
195aefde 3437 u16 data = 0;
40dcaa9f 3438 int r, idx, ret = 0;
6aa8b732 3439
40dcaa9f
XG		 3440 idx = srcu_read_lock(&kvm->srcu);
3441 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3442 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3443 if (r < 0)
10589a46 3444 goto out;
195aefde 3445 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3446 r = kvm_write_guest_page(kvm, fn++, &data,
3447 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3448 if (r < 0)
10589a46 3449 goto out;
195aefde
IE		 3450 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3451 if (r < 0)
10589a46 3452 goto out;
195aefde
IE		 3453 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454 if (r < 0)
10589a46 3455 goto out;
195aefde 3456 data = ~0;
10589a46
MT		 3457 r = kvm_write_guest_page(kvm, fn, &data,
3458 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3459 sizeof(u8));
195aefde 3460 if (r < 0)
10589a46
MT		 3461 goto out;
3462
3463 ret = 1;
3464out:
40dcaa9f 3465 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3466 return ret;
6aa8b732
AK		 3467}
3468
b7ebfb05
SY		 3469static int init_rmode_identity_map(struct kvm *kvm)
3470{
40dcaa9f 3471 int i, idx, r, ret;
b7ebfb05
SY		 3472 pfn_t identity_map_pfn;
3473 u32 tmp;
3474
089d034e 3475 if (!enable_ept)
b7ebfb05
SY		 3476 return 1;
3477 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3478 printk(KERN_ERR "EPT: identity-mapping pagetable "
3479 "haven't been allocated!\n");
3480 return 0;
3481 }
3482 if (likely(kvm->arch.ept_identity_pagetable_done))
3483 return 1;
3484 ret = 0;
b927a3ce 3485 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3486 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3487 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3488 if (r < 0)
3489 goto out;
3490 /* Set up identity-mapping pagetable for EPT in real mode */
3491 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3492 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3493 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3494 r = kvm_write_guest_page(kvm, identity_map_pfn,
3495 &tmp, i * sizeof(tmp), sizeof(tmp));
3496 if (r < 0)
3497 goto out;
3498 }
3499 kvm->arch.ept_identity_pagetable_done = true;
3500 ret = 1;
3501out:
40dcaa9f 3502 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3503 return ret;
3504}
3505
6aa8b732
AK		 3506static void seg_setup(int seg)
3507{
3508 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3509 unsigned int ar;
6aa8b732
AK		 3510
3511 vmcs_write16(sf->selector, 0);
3512 vmcs_writel(sf->base, 0);
3513 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3514 if (enable_unrestricted_guest) {
3515 ar = 0x93;
3516 if (seg == VCPU_SREG_CS)
3517 ar |= 0x08; /* code segment */
3518 } else
3519 ar = 0xf3;
3520
3521 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3522}
3523
f78e0e2e
SY		 3524static int alloc_apic_access_page(struct kvm *kvm)
3525{
3526 struct kvm_userspace_memory_region kvm_userspace_mem;
3527 int r = 0;
3528
79fac95e 3529 mutex_lock(&kvm->slots_lock);
bfc6d222 3530 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3531 goto out;
3532 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3533 kvm_userspace_mem.flags = 0;
3534 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3535 kvm_userspace_mem.memory_size = PAGE_SIZE;
3536 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3537 if (r)
3538 goto out;
72dc67a6 3539
bfc6d222 3540 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3541out:
79fac95e 3542 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3543 return r;
3544}
3545
b7ebfb05
SY		 3546static int alloc_identity_pagetable(struct kvm *kvm)
3547{
3548 struct kvm_userspace_memory_region kvm_userspace_mem;
3549 int r = 0;
3550
79fac95e 3551 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3552 if (kvm->arch.ept_identity_pagetable)
3553 goto out;
3554 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3555 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3556 kvm_userspace_mem.guest_phys_addr =
3557 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3558 kvm_userspace_mem.memory_size = PAGE_SIZE;
3559 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3560 if (r)
3561 goto out;
3562
b7ebfb05 3563 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3564 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3565out:
79fac95e 3566 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3567 return r;
3568}
3569
2384d2b3
SY		 3570static void allocate_vpid(struct vcpu_vmx *vmx)
3571{
3572 int vpid;
3573
3574 vmx->vpid = 0;
919818ab 3575 if (!enable_vpid)
2384d2b3
SY		 3576 return;
3577 spin_lock(&vmx_vpid_lock);
3578 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3579 if (vpid < VMX_NR_VPIDS) {
3580 vmx->vpid = vpid;
3581 __set_bit(vpid, vmx_vpid_bitmap);
3582 }
3583 spin_unlock(&vmx_vpid_lock);
3584}
3585
cdbecfc3
LJ		 3586static void free_vpid(struct vcpu_vmx *vmx)
3587{
3588 if (!enable_vpid)
3589 return;
3590 spin_lock(&vmx_vpid_lock);
3591 if (vmx->vpid != 0)
3592 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3593 spin_unlock(&vmx_vpid_lock);
3594}
3595
5897297b 3596static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3597{
3e7c73e9 3598 int f = sizeof(unsigned long);
25c5f225
SY		 3599
3600 if (!cpu_has_vmx_msr_bitmap())
3601 return;
3602
3603 /*
3604 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3605 * have the write-low and read-high bitmap offsets the wrong way round.
3606 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3607 */
25c5f225 3608 if (msr <= 0x1fff) {
3e7c73e9
AK		 3609 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3610 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3611 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3612 msr &= 0x1fff;
3e7c73e9
AK		 3613 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3614 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3615 }
25c5f225
SY		 3616}
3617
5897297b
AK		 3618static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3619{
3620 if (!longmode_only)
3621 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3622 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3623}
3624
a3a8ff8e
NHE		 3625/*
3626 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3627 * will not change in the lifetime of the guest.
3628 * Note that host-state that does change is set elsewhere. E.g., host-state
3629 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3630 */
3631static void vmx_set_constant_host_state(void)
3632{
3633 u32 low32, high32;
3634 unsigned long tmpl;
3635 struct desc_ptr dt;
3636
3637 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3638 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3639 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3640
3641 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3642 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3643 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3644 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3645 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3646
3647 native_store_idt(&dt);
3648 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3649
3650 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3651 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3652
3653 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3654 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3655 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3656 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3657
3658 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3659 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3660 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3661 }
3662}
3663
bf8179a0
NHE		 3664static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3665{
3666 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3667 if (enable_ept)
3668 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3669 if (is_guest_mode(&vmx->vcpu))
3670 vmx->vcpu.arch.cr4_guest_owned_bits &=
3671 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3672 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3673}
3674
3675static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3676{
3677 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3678 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3679 exec_control &= ~CPU_BASED_TPR_SHADOW;
3680#ifdef CONFIG_X86_64
3681 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3682 CPU_BASED_CR8_LOAD_EXITING;
3683#endif
3684 }
3685 if (!enable_ept)
3686 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3687 CPU_BASED_CR3_LOAD_EXITING |
3688 CPU_BASED_INVLPG_EXITING;
3689 return exec_control;
3690}
3691
3692static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3693{
3694 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3695 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3696 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3697 if (vmx->vpid == 0)
3698 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3699 if (!enable_ept) {
3700 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3701 enable_unrestricted_guest = 0;
3702 }
3703 if (!enable_unrestricted_guest)
3704 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3705 if (!ple_gap)
3706 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3707 return exec_control;
3708}
3709
ce88decf
XG		 3710static void ept_set_mmio_spte_mask(void)
3711{
3712 /*
3713 * EPT Misconfigurations can be generated if the value of bits 2:0
3714 * of an EPT paging-structure entry is 110b (write/execute).
3715 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3716 * spte.
3717 */
3718 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3719}
3720
6aa8b732
AK		 3721/*
3722 * Sets up the vmcs for emulated real mode.
3723 */
8b9cf98c 3724static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3725{
2e4ce7f5 3726#ifdef CONFIG_X86_64
6aa8b732 3727 unsigned long a;
2e4ce7f5 3728#endif
6aa8b732 3729 int i;
6aa8b732 3730
6aa8b732 3731 /* I/O */
3e7c73e9
AK		 3732 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3733 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3734
25c5f225 3735 if (cpu_has_vmx_msr_bitmap())
5897297b 3736 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3737
6aa8b732
AK		 3738 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3739
6aa8b732 3740 /* Control */
1c3d14fe
YS		 3741 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3742 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3743
bf8179a0 3744 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3745
83ff3b9d 3746 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3747 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3748 vmx_secondary_exec_control(vmx));
83ff3b9d 3749 }
f78e0e2e 3750
4b8d54f9
ZE		 3751 if (ple_gap) {
3752 vmcs_write32(PLE_GAP, ple_gap);
3753 vmcs_write32(PLE_WINDOW, ple_window);
3754 }
3755
c3707958
XG		 3756 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3757 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3758 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3759
9581d442
AK		 3760 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3761 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3762 vmx_set_constant_host_state();
05b3e0c2 3763#ifdef CONFIG_X86_64
6aa8b732
AK		 3764 rdmsrl(MSR_FS_BASE, a);
3765 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3766 rdmsrl(MSR_GS_BASE, a);
3767 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3768#else
3769 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3770 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3771#endif
3772
2cc51560
ED		 3773 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3774 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3775 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3776 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3777 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3778
468d472f 3779 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3780 u32 msr_low, msr_high;
3781 u64 host_pat;
468d472f
SY		 3782 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3783 host_pat = msr_low | ((u64) msr_high << 32);
3784 /* Write the default value follow host pat */
3785 vmcs_write64(GUEST_IA32_PAT, host_pat);
3786 /* Keep arch.pat sync with GUEST_IA32_PAT */
3787 vmx->vcpu.arch.pat = host_pat;
3788 }
3789
6aa8b732
AK		 3790 for (i = 0; i < NR_VMX_MSR; ++i) {
3791 u32 index = vmx_msr_index[i];
3792 u32 data_low, data_high;
a2fa3e9f 3793 int j = vmx->nmsrs;
6aa8b732
AK		 3794
3795 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3796 continue;
432bd6cb
AK		 3797 if (wrmsr_safe(index, data_low, data_high) < 0)
3798 continue;
26bb0981
AK		 3799 vmx->guest_msrs[j].index = i;
3800 vmx->guest_msrs[j].data = 0;
d5696725 3801 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3802 ++vmx->nmsrs;
6aa8b732 3803 }
6aa8b732 3804
1c3d14fe 3805 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3806
3807 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3808 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3809
e00c8cf2 3810 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3811 set_cr4_guest_host_mask(vmx);
e00c8cf2 3812
99e3e30a 3813 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3814
e00c8cf2
AK		 3815 return 0;
3816}
3817
3818static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3819{
3820 struct vcpu_vmx *vmx = to_vmx(vcpu);
3821 u64 msr;
4b9d3a04 3822 int ret;
e00c8cf2 3823
5fdbf976 3824 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3825
7ffd92c5 3826 vmx->rmode.vm86_active = 0;
e00c8cf2 3827
3b86cd99
JK		 3828 vmx->soft_vnmi_blocked = 0;
3829
ad312c7c 3830 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3831 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3832 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3833 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3834 msr |= MSR_IA32_APICBASE_BSP;
3835 kvm_set_apic_base(&vmx->vcpu, msr);
3836
10ab25cd
JK		 3837 ret = fx_init(&vmx->vcpu);
3838 if (ret != 0)
3839 goto out;
e00c8cf2 3840
2fb92db1
AK		 3841 vmx_segment_cache_clear(vmx);
3842
5706be0d 3843 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3844 /*
3845 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3846 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3847 */
c5af89b6 3848 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3849 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3850 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3851 } else {
ad312c7c
ZX		 3852 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3853 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3854 }
e00c8cf2
AK		 3855
3856 seg_setup(VCPU_SREG_DS);
3857 seg_setup(VCPU_SREG_ES);
3858 seg_setup(VCPU_SREG_FS);
3859 seg_setup(VCPU_SREG_GS);
3860 seg_setup(VCPU_SREG_SS);
3861
3862 vmcs_write16(GUEST_TR_SELECTOR, 0);
3863 vmcs_writel(GUEST_TR_BASE, 0);
3864 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3865 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3866
3867 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3868 vmcs_writel(GUEST_LDTR_BASE, 0);
3869 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3870 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3871
3872 vmcs_write32(GUEST_SYSENTER_CS, 0);
3873 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3874 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3875
3876 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3877 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3878 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3879 else
5fdbf976
MT		 3880 kvm_rip_write(vcpu, 0);
3881 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3882
e00c8cf2
AK		 3883 vmcs_writel(GUEST_DR7, 0x400);
3884
3885 vmcs_writel(GUEST_GDTR_BASE, 0);
3886 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3887
3888 vmcs_writel(GUEST_IDTR_BASE, 0);
3889 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3890
443381a8 3891 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3892 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3893 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3894
e00c8cf2
AK		 3895 /* Special registers */
3896 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3897
3898 setup_msrs(vmx);
3899
6aa8b732
AK		 3900 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3901
f78e0e2e
SY		 3902 if (cpu_has_vmx_tpr_shadow()) {
3903 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3904 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3905 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3906 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3907 vmcs_write32(TPR_THRESHOLD, 0);
3908 }
3909
3910 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3911 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3912 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3913
2384d2b3
SY		 3914 if (vmx->vpid != 0)
3915 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3916
fa40052c 3917 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3918 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3919 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3920 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3921 vmx_fpu_activate(&vmx->vcpu);
3922 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3923
b9d762fa 3924 vpid_sync_context(vmx);
2384d2b3 3925
3200f405 3926 ret = 0;
6aa8b732 3927
a89a8fb9
MG		 3928 /* HACK: Don't enable emulation on guest boot/reset */
3929 vmx->emulation_required = 0;
3930
6aa8b732
AK		 3931out:
3932 return ret;
3933}
3934
b6f1250e
NHE		 3935/*
3936 * In nested virtualization, check if L1 asked to exit on external interrupts.
3937 * For most existing hypervisors, this will always return true.
3938 */
3939static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3940{
3941 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3942 PIN_BASED_EXT_INTR_MASK;
3943}
3944
3b86cd99
JK		 3945static void enable_irq_window(struct kvm_vcpu *vcpu)
3946{
3947 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 3948 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3949 /*
3950 * We get here if vmx_interrupt_allowed() said we can't
3951 * inject to L1 now because L2 must run. Ask L2 to exit
3952 * right after entry, so we can inject to L1 more promptly.
b6f1250e 3953 */
d6185f20 3954 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 3955 return;
d6185f20 3956 }
3b86cd99
JK		 3957
3958 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3959 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3960 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3961}
3962
3963static void enable_nmi_window(struct kvm_vcpu *vcpu)
3964{
3965 u32 cpu_based_vm_exec_control;
3966
3967 if (!cpu_has_virtual_nmis()) {
3968 enable_irq_window(vcpu);
3969 return;
3970 }
3971
30bd0c4c
AK		 3972 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3973 enable_irq_window(vcpu);
3974 return;
3975 }
3b86cd99
JK		 3976 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3977 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3978 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3979}
3980
66fd3f7f 3981static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3982{
9c8cba37 3983 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3984 uint32_t intr;
3985 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3986
229456fc 3987 trace_kvm_inj_virq(irq);
2714d1d3 3988
fa89a817 3989 ++vcpu->stat.irq_injections;
7ffd92c5 3990 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3991 int inc_eip = 0;
3992 if (vcpu->arch.interrupt.soft)
3993 inc_eip = vcpu->arch.event_exit_inst_len;
3994 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3996 return;
3997 }
66fd3f7f
GN		 3998 intr = irq | INTR_INFO_VALID_MASK;
3999 if (vcpu->arch.interrupt.soft) {
4000 intr |= INTR_TYPE_SOFT_INTR;
4001 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4002 vmx->vcpu.arch.event_exit_inst_len);
4003 } else
4004 intr |= INTR_TYPE_EXT_INTR;
4005 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 4006 vmx_clear_hlt(vcpu);
85f455f7
ED		 4007}
4008
f08864b4
SY		 4009static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4010{
66a5a347
JK		 4011 struct vcpu_vmx *vmx = to_vmx(vcpu);
4012
0b6ac343
NHE		 4013 if (is_guest_mode(vcpu))
4014 return;
4015
3b86cd99
JK		 4016 if (!cpu_has_virtual_nmis()) {
4017 /*
4018 * Tracking the NMI-blocked state in software is built upon
4019 * finding the next open IRQ window. This, in turn, depends on
4020 * well-behaving guests: They have to keep IRQs disabled at
4021 * least as long as the NMI handler runs. Otherwise we may
4022 * cause NMI nesting, maybe breaking the guest. But as this is
4023 * highly unlikely, we can live with the residual risk.
4024 */
4025 vmx->soft_vnmi_blocked = 1;
4026 vmx->vnmi_blocked_time = 0;
4027 }
4028
487b391d 4029 ++vcpu->stat.nmi_injections;
9d58b931 4030 vmx->nmi_known_unmasked = false;
7ffd92c5 4031 if (vmx->rmode.vm86_active) {
71f9833b 4032 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4033 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4034 return;
4035 }
f08864b4
SY		 4036 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4037 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 4038 vmx_clear_hlt(vcpu);
f08864b4
SY		 4039}
4040
c4282df9 4041static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4042{
3b86cd99 4043 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4044 return 0;
33f089ca 4045
c4282df9 4046 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4047 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4048 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4049}
4050
3cfc3092
JK		 4051static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4052{
4053 if (!cpu_has_virtual_nmis())
4054 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4055 if (to_vmx(vcpu)->nmi_known_unmasked)
4056 return false;
c332c83a 4057 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4058}
4059
4060static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4061{
4062 struct vcpu_vmx *vmx = to_vmx(vcpu);
4063
4064 if (!cpu_has_virtual_nmis()) {
4065 if (vmx->soft_vnmi_blocked != masked) {
4066 vmx->soft_vnmi_blocked = masked;
4067 vmx->vnmi_blocked_time = 0;
4068 }
4069 } else {
9d58b931 4070 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4071 if (masked)
4072 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4073 GUEST_INTR_STATE_NMI);
4074 else
4075 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4076 GUEST_INTR_STATE_NMI);
4077 }
4078}
4079
78646121
GN		 4080static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4081{
b6f1250e 4082 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4083 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4084 if (to_vmx(vcpu)->nested.nested_run_pending ||
4085 (vmcs12->idt_vectoring_info_field &
4086 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4087 return 0;
4088 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4089 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4090 vmcs12->vm_exit_intr_info = 0;
4091 /* fall through to normal code, but now in L1, not L2 */
4092 }
4093
c4282df9
GN		 4094 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4095 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4096 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4097}
4098
cbc94022
IE		 4099static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4100{
4101 int ret;
4102 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4103 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4104 .guest_phys_addr = addr,
4105 .memory_size = PAGE_SIZE * 3,
4106 .flags = 0,
4107 };
4108
4109 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4110 if (ret)
4111 return ret;
bfc6d222 4112 kvm->arch.tss_addr = addr;
93ea5388
GN		 4113 if (!init_rmode_tss(kvm))
4114 return -ENOMEM;
4115
cbc94022
IE		 4116 return 0;
4117}
4118
6aa8b732
AK		 4119static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4120 int vec, u32 err_code)
4121{
b3f37707
NK		 4122 /*
4123 * Instruction with address size override prefix opcode 0x67
4124 * Cause the #SS fault with 0 error code in VM86 mode.
4125 */
4126 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4127 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4128 return 1;
77ab6db0
JK		 4129 /*
4130 * Forward all other exceptions that are valid in real mode.
4131 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4132 * the required debugging infrastructure rework.
4133 */
4134 switch (vec) {
77ab6db0 4135 case DB_VECTOR:
d0bfb940
JK		 4136 if (vcpu->guest_debug &
4137 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4138 return 0;
4139 kvm_queue_exception(vcpu, vec);
4140 return 1;
77ab6db0 4141 case BP_VECTOR:
c573cd22
JK		 4142 /*
4143 * Update instruction length as we may reinject the exception
4144 * from user space while in guest debugging mode.
4145 */
4146 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4147 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4148 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4149 return 0;
4150 /* fall through */
4151 case DE_VECTOR:
77ab6db0
JK		 4152 case OF_VECTOR:
4153 case BR_VECTOR:
4154 case UD_VECTOR:
4155 case DF_VECTOR:
4156 case SS_VECTOR:
4157 case GP_VECTOR:
4158 case MF_VECTOR:
4159 kvm_queue_exception(vcpu, vec);
4160 return 1;
4161 }
6aa8b732
AK		 4162 return 0;
4163}
4164
a0861c02
AK		 4165/*
4166 * Trigger machine check on the host. We assume all the MSRs are already set up
4167 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4168 * We pass a fake environment to the machine check handler because we want
4169 * the guest to be always treated like user space, no matter what context
4170 * it used internally.
4171 */
4172static void kvm_machine_check(void)
4173{
4174#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4175 struct pt_regs regs = {
4176 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4177 .flags = X86_EFLAGS_IF,
4178 };
4179
4180 do_machine_check(&regs, 0);
4181#endif
4182}
4183
851ba692 4184static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4185{
4186 /* already handled by vcpu_run */
4187 return 1;
4188}
4189
851ba692 4190static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4191{
1155f76a 4192 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4193 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4194 u32 intr_info, ex_no, error_code;
42dbaa5a 4195 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4196 u32 vect_info;
4197 enum emulation_result er;
4198
1155f76a 4199 vect_info = vmx->idt_vectoring_info;
88786475 4200 intr_info = vmx->exit_intr_info;
6aa8b732 4201
a0861c02 4202 if (is_machine_check(intr_info))
851ba692 4203 return handle_machine_check(vcpu);
a0861c02 4204
6aa8b732 4205 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4206 !is_page_fault(intr_info)) {
4207 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4208 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4209 vcpu->run->internal.ndata = 2;
4210 vcpu->run->internal.data[0] = vect_info;
4211 vcpu->run->internal.data[1] = intr_info;
4212 return 0;
4213 }
6aa8b732 4214
e4a41889 4215 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4216 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4217
4218 if (is_no_device(intr_info)) {
5fd86fcf 4219 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4220 return 1;
4221 }
4222
7aa81cc0 4223 if (is_invalid_opcode(intr_info)) {
51d8b661 4224 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4225 if (er != EMULATE_DONE)
7ee5d940 4226 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4227 return 1;
4228 }
4229
6aa8b732 4230 error_code = 0;
2e11384c 4231 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4232 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4233 if (is_page_fault(intr_info)) {
1439442c 4234 /* EPT won't cause page fault directly */
cf3ace79 4235 BUG_ON(enable_ept);
6aa8b732 4236 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4237 trace_kvm_page_fault(cr2, error_code);
4238
3298b75c 4239 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4240 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4241 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4242 }
4243
7ffd92c5 4244 if (vmx->rmode.vm86_active &&
6aa8b732 4245 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4246 error_code)) {
ad312c7c
ZX		 4247 if (vcpu->arch.halt_request) {
4248 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4249 return kvm_emulate_halt(vcpu);
4250 }
6aa8b732 4251 return 1;
72d6e5a0 4252 }
6aa8b732 4253
d0bfb940 4254 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4255 switch (ex_no) {
4256 case DB_VECTOR:
4257 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4258 if (!(vcpu->guest_debug &
4259 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4260 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4261 kvm_queue_exception(vcpu, DB_VECTOR);
4262 return 1;
4263 }
4264 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4265 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4266 /* fall through */
4267 case BP_VECTOR:
c573cd22
JK		 4268 /*
4269 * Update instruction length as we may reinject #BP from
4270 * user space while in guest debugging mode. Reading it for
4271 * #DB as well causes no harm, it is not used in that case.
4272 */
4273 vmx->vcpu.arch.event_exit_inst_len =
4274 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4275 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4276 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4277 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4278 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4279 break;
4280 default:
d0bfb940
JK		 4281 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4282 kvm_run->ex.exception = ex_no;
4283 kvm_run->ex.error_code = error_code;
42dbaa5a 4284 break;
6aa8b732 4285 }
6aa8b732
AK		 4286 return 0;
4287}
4288
851ba692 4289static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4290{
1165f5fe 4291 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4292 return 1;
4293}
4294
851ba692 4295static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4296{
851ba692 4297 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4298 return 0;
4299}
6aa8b732 4300
851ba692 4301static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4302{
bfdaab09 4303 unsigned long exit_qualification;
34c33d16 4304 int size, in, string;
039576c0 4305 unsigned port;
6aa8b732 4306
bfdaab09 4307 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4308 string = (exit_qualification & 16) != 0;
cf8f70bf 4309 in = (exit_qualification & 8) != 0;
e70669ab 4310
cf8f70bf 4311 ++vcpu->stat.io_exits;
e70669ab 4312
cf8f70bf 4313 if (string || in)
51d8b661 4314 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4315
cf8f70bf
GN		 4316 port = exit_qualification >> 16;
4317 size = (exit_qualification & 7) + 1;
e93f36bc 4318 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4319
4320 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4321}
4322
102d8325
IM		 4323static void
4324vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4325{
4326 /*
4327 * Patch in the VMCALL instruction:
4328 */
4329 hypercall[0] = 0x0f;
4330 hypercall[1] = 0x01;
4331 hypercall[2] = 0xc1;
102d8325
IM		 4332}
4333
eeadf9e7
NHE		 4334/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4335static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4336{
4337 if (to_vmx(vcpu)->nested.vmxon &&
4338 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4339 return 1;
4340
4341 if (is_guest_mode(vcpu)) {
4342 /*
4343 * We get here when L2 changed cr0 in a way that did not change
4344 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4345 * but did change L0 shadowed bits. This can currently happen
4346 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4347 * loading) while pretending to allow the guest to change it.
4348 */
4349 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4350 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4351 return 1;
4352 vmcs_writel(CR0_READ_SHADOW, val);
4353 return 0;
4354 } else
4355 return kvm_set_cr0(vcpu, val);
4356}
4357
4358static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4359{
4360 if (is_guest_mode(vcpu)) {
4361 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4362 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4363 return 1;
4364 vmcs_writel(CR4_READ_SHADOW, val);
4365 return 0;
4366 } else
4367 return kvm_set_cr4(vcpu, val);
4368}
4369
4370/* called to set cr0 as approriate for clts instruction exit. */
4371static void handle_clts(struct kvm_vcpu *vcpu)
4372{
4373 if (is_guest_mode(vcpu)) {
4374 /*
4375 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4376 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4377 * just pretend it's off (also in arch.cr0 for fpu_activate).
4378 */
4379 vmcs_writel(CR0_READ_SHADOW,
4380 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4381 vcpu->arch.cr0 &= ~X86_CR0_TS;
4382 } else
4383 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4384}
4385
851ba692 4386static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4387{
229456fc 4388 unsigned long exit_qualification, val;
6aa8b732
AK		 4389 int cr;
4390 int reg;
49a9b07e 4391 int err;
6aa8b732 4392
bfdaab09 4393 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4394 cr = exit_qualification & 15;
4395 reg = (exit_qualification >> 8) & 15;
4396 switch ((exit_qualification >> 4) & 3) {
4397 case 0: /* mov to cr */
229456fc
MT		 4398 val = kvm_register_read(vcpu, reg);
4399 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4400 switch (cr) {
4401 case 0:
eeadf9e7 4402 err = handle_set_cr0(vcpu, val);
db8fcefa 4403 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4404 return 1;
4405 case 3:
2390218b 4406 err = kvm_set_cr3(vcpu, val);
db8fcefa 4407 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4408 return 1;
4409 case 4:
eeadf9e7 4410 err = handle_set_cr4(vcpu, val);
db8fcefa 4411 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4412 return 1;
0a5fff19
GN		 4413 case 8: {
4414 u8 cr8_prev = kvm_get_cr8(vcpu);
4415 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4416 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4417 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4418 if (irqchip_in_kernel(vcpu->kvm))
4419 return 1;
4420 if (cr8_prev <= cr8)
4421 return 1;
851ba692 4422 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4423 return 0;
4424 }
6aa8b732
AK		 4425 };
4426 break;
25c4c276 4427 case 2: /* clts */
eeadf9e7 4428 handle_clts(vcpu);
4d4ec087 4429 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4430 skip_emulated_instruction(vcpu);
6b52d186 4431 vmx_fpu_activate(vcpu);
25c4c276 4432 return 1;
6aa8b732
AK		 4433 case 1: /*mov from cr*/
4434 switch (cr) {
4435 case 3:
9f8fe504
AK		 4436 val = kvm_read_cr3(vcpu);
4437 kvm_register_write(vcpu, reg, val);
4438 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4439 skip_emulated_instruction(vcpu);
4440 return 1;
4441 case 8:
229456fc
MT		 4442 val = kvm_get_cr8(vcpu);
4443 kvm_register_write(vcpu, reg, val);
4444 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4445 skip_emulated_instruction(vcpu);
4446 return 1;
4447 }
4448 break;
4449 case 3: /* lmsw */
a1f83a74 4450 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4451 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4452 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4453
4454 skip_emulated_instruction(vcpu);
4455 return 1;
4456 default:
4457 break;
4458 }
851ba692 4459 vcpu->run->exit_reason = 0;
f0242478 4460 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4461 (int)(exit_qualification >> 4) & 3, cr);
4462 return 0;
4463}
4464
851ba692 4465static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4466{
bfdaab09 4467 unsigned long exit_qualification;
6aa8b732
AK		 4468 int dr, reg;
4469
f2483415 4470 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4471 if (!kvm_require_cpl(vcpu, 0))
4472 return 1;
42dbaa5a
JK		 4473 dr = vmcs_readl(GUEST_DR7);
4474 if (dr & DR7_GD) {
4475 /*
4476 * As the vm-exit takes precedence over the debug trap, we
4477 * need to emulate the latter, either for the host or the
4478 * guest debugging itself.
4479 */
4480 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4481 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4482 vcpu->run->debug.arch.dr7 = dr;
4483 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4484 vmcs_readl(GUEST_CS_BASE) +
4485 vmcs_readl(GUEST_RIP);
851ba692
AK		 4486 vcpu->run->debug.arch.exception = DB_VECTOR;
4487 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4488 return 0;
4489 } else {
4490 vcpu->arch.dr7 &= ~DR7_GD;
4491 vcpu->arch.dr6 |= DR6_BD;
4492 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4493 kvm_queue_exception(vcpu, DB_VECTOR);
4494 return 1;
4495 }
4496 }
4497
bfdaab09 4498 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4499 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4500 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4501 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4502 unsigned long val;
4503 if (!kvm_get_dr(vcpu, dr, &val))
4504 kvm_register_write(vcpu, reg, val);
4505 } else
4506 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4507 skip_emulated_instruction(vcpu);
4508 return 1;
4509}
4510
020df079
GN		 4511static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4512{
4513 vmcs_writel(GUEST_DR7, val);
4514}
4515
851ba692 4516static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4517{
06465c5a
AK		 4518 kvm_emulate_cpuid(vcpu);
4519 return 1;
6aa8b732
AK		 4520}
4521
851ba692 4522static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4523{
ad312c7c 4524 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4525 u64 data;
4526
4527 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4528 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4529 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4530 return 1;
4531 }
4532
229456fc 4533 trace_kvm_msr_read(ecx, data);
2714d1d3 4534
6aa8b732 4535 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4536 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4537 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4538 skip_emulated_instruction(vcpu);
4539 return 1;
4540}
4541
851ba692 4542static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4543{
ad312c7c
ZX		 4544 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4545 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4546 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4547
4548 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4549 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4550 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4551 return 1;
4552 }
4553
59200273 4554 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4555 skip_emulated_instruction(vcpu);
4556 return 1;
4557}
4558
851ba692 4559static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4560{
3842d135 4561 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4562 return 1;
4563}
4564
851ba692 4565static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4566{
85f455f7
ED		 4567 u32 cpu_based_vm_exec_control;
4568
4569 /* clear pending irq */
4570 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4571 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4572 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4573
3842d135
AK		 4574 kvm_make_request(KVM_REQ_EVENT, vcpu);
4575
a26bf12a 4576 ++vcpu->stat.irq_window_exits;
2714d1d3 4577
c1150d8c
DL		 4578 /*
4579 * If the user space waits to inject interrupts, exit as soon as
4580 * possible
4581 */
8061823a 4582 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4583 vcpu->run->request_interrupt_window &&
8061823a 4584 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4585 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4586 return 0;
4587 }
6aa8b732
AK		 4588 return 1;
4589}
4590
851ba692 4591static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4592{
4593 skip_emulated_instruction(vcpu);
d3bef15f 4594 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4595}
4596
851ba692 4597static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4598{
510043da 4599 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4600 kvm_emulate_hypercall(vcpu);
4601 return 1;
c21415e8
IM		 4602}
4603
ec25d5e6
GN		 4604static int handle_invd(struct kvm_vcpu *vcpu)
4605{
51d8b661 4606 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4607}
4608
851ba692 4609static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4610{
f9c617f6 4611 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4612
4613 kvm_mmu_invlpg(vcpu, exit_qualification);
4614 skip_emulated_instruction(vcpu);
4615 return 1;
4616}
4617
fee84b07
AK		 4618static int handle_rdpmc(struct kvm_vcpu *vcpu)
4619{
4620 int err;
4621
4622 err = kvm_rdpmc(vcpu);
4623 kvm_complete_insn_gp(vcpu, err);
4624
4625 return 1;
4626}
4627
851ba692 4628static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4629{
4630 skip_emulated_instruction(vcpu);
f5f48ee1 4631 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4632 return 1;
4633}
4634
2acf923e
DC		 4635static int handle_xsetbv(struct kvm_vcpu *vcpu)
4636{
4637 u64 new_bv = kvm_read_edx_eax(vcpu);
4638 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4639
4640 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4641 skip_emulated_instruction(vcpu);
4642 return 1;
4643}
4644
851ba692 4645static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4646{
58fbbf26
KT		 4647 if (likely(fasteoi)) {
4648 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4649 int access_type, offset;
4650
4651 access_type = exit_qualification & APIC_ACCESS_TYPE;
4652 offset = exit_qualification & APIC_ACCESS_OFFSET;
4653 /*
4654 * Sane guest uses MOV to write EOI, with written value
4655 * not cared. So make a short-circuit here by avoiding
4656 * heavy instruction emulation.
4657 */
4658 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4659 (offset == APIC_EOI)) {
4660 kvm_lapic_set_eoi(vcpu);
4661 skip_emulated_instruction(vcpu);
4662 return 1;
4663 }
4664 }
51d8b661 4665 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4666}
4667
851ba692 4668static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4669{
60637aac 4670 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4671 unsigned long exit_qualification;
e269fb21
JK		 4672 bool has_error_code = false;
4673 u32 error_code = 0;
37817f29 4674 u16 tss_selector;
64a7ec06
GN		 4675 int reason, type, idt_v;
4676
4677 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4678 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4679
4680 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4681
4682 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4683 if (reason == TASK_SWITCH_GATE && idt_v) {
4684 switch (type) {
4685 case INTR_TYPE_NMI_INTR:
4686 vcpu->arch.nmi_injected = false;
654f06fc 4687 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4688 break;
4689 case INTR_TYPE_EXT_INTR:
66fd3f7f 4690 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4691 kvm_clear_interrupt_queue(vcpu);
4692 break;
4693 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4694 if (vmx->idt_vectoring_info &
4695 VECTORING_INFO_DELIVER_CODE_MASK) {
4696 has_error_code = true;
4697 error_code =
4698 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4699 }
4700 /* fall through */
64a7ec06
GN		 4701 case INTR_TYPE_SOFT_EXCEPTION:
4702 kvm_clear_exception_queue(vcpu);
4703 break;
4704 default:
4705 break;
4706 }
60637aac 4707 }
37817f29
IE		 4708 tss_selector = exit_qualification;
4709
64a7ec06
GN		 4710 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4711 type != INTR_TYPE_EXT_INTR &&
4712 type != INTR_TYPE_NMI_INTR))
4713 skip_emulated_instruction(vcpu);
4714
acb54517
GN		 4715 if (kvm_task_switch(vcpu, tss_selector, reason,
4716 has_error_code, error_code) == EMULATE_FAIL) {
4717 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4718 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4719 vcpu->run->internal.ndata = 0;
42dbaa5a 4720 return 0;
acb54517 4721 }
42dbaa5a
JK		 4722
4723 /* clear all local breakpoint enable flags */
4724 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4725
4726 /*
4727 * TODO: What about debug traps on tss switch?
4728 * Are we supposed to inject them and update dr6?
4729 */
4730
4731 return 1;
37817f29
IE		 4732}
4733
851ba692 4734static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4735{
f9c617f6 4736 unsigned long exit_qualification;
1439442c 4737 gpa_t gpa;
1439442c 4738 int gla_validity;
1439442c 4739
f9c617f6 4740 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4741
4742 if (exit_qualification & (1 << 6)) {
4743 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4744 return -EINVAL;
1439442c
SY		 4745 }
4746
4747 gla_validity = (exit_qualification >> 7) & 0x3;
4748 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4749 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4750 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4751 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4752 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4753 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4754 (long unsigned int)exit_qualification);
851ba692
AK		 4755 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4756 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4757 return 0;
1439442c
SY		 4758 }
4759
4760 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4761 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4762 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4763}
4764
68f89400
MT		 4765static u64 ept_rsvd_mask(u64 spte, int level)
4766{
4767 int i;
4768 u64 mask = 0;
4769
4770 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4771 mask |= (1ULL << i);
4772
4773 if (level > 2)
4774 /* bits 7:3 reserved */
4775 mask |= 0xf8;
4776 else if (level == 2) {
4777 if (spte & (1ULL << 7))
4778 /* 2MB ref, bits 20:12 reserved */
4779 mask |= 0x1ff000;
4780 else
4781 /* bits 6:3 reserved */
4782 mask |= 0x78;
4783 }
4784
4785 return mask;
4786}
4787
4788static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4789 int level)
4790{
4791 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4792
4793 /* 010b (write-only) */
4794 WARN_ON((spte & 0x7) == 0x2);
4795
4796 /* 110b (write/execute) */
4797 WARN_ON((spte & 0x7) == 0x6);
4798
4799 /* 100b (execute-only) and value not supported by logical processor */
4800 if (!cpu_has_vmx_ept_execute_only())
4801 WARN_ON((spte & 0x7) == 0x4);
4802
4803 /* not 000b */
4804 if ((spte & 0x7)) {
4805 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4806
4807 if (rsvd_bits != 0) {
4808 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4809 __func__, rsvd_bits);
4810 WARN_ON(1);
4811 }
4812
4813 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4814 u64 ept_mem_type = (spte & 0x38) >> 3;
4815
4816 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4817 ept_mem_type == 7) {
4818 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4819 __func__, ept_mem_type);
4820 WARN_ON(1);
4821 }
4822 }
4823 }
4824}
4825
851ba692 4826static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4827{
4828 u64 sptes[4];
ce88decf 4829 int nr_sptes, i, ret;
68f89400
MT		 4830 gpa_t gpa;
4831
4832 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4833
ce88decf
XG		 4834 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4835 if (likely(ret == 1))
4836 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4837 EMULATE_DONE;
4838 if (unlikely(!ret))
4839 return 1;
4840
4841 /* It is the real ept misconfig */
68f89400
MT		 4842 printk(KERN_ERR "EPT: Misconfiguration.\n");
4843 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4844
4845 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4846
4847 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4848 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4849
851ba692
AK		 4850 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4851 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4852
4853 return 0;
4854}
4855
851ba692 4856static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4857{
4858 u32 cpu_based_vm_exec_control;
4859
4860 /* clear pending NMI */
4861 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4862 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4864 ++vcpu->stat.nmi_window_exits;
3842d135 4865 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4866
4867 return 1;
4868}
4869
80ced186 4870static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4871{
8b3079a5
AK		 4872 struct vcpu_vmx *vmx = to_vmx(vcpu);
4873 enum emulation_result err = EMULATE_DONE;
80ced186 4874 int ret = 1;
49e9d557
AK		 4875 u32 cpu_exec_ctrl;
4876 bool intr_window_requested;
4877
4878 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4879 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4880
4881 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4882 if (intr_window_requested
4883 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4884 return handle_interrupt_window(&vmx->vcpu);
4885
51d8b661 4886 err = emulate_instruction(vcpu, 0);
ea953ef0 4887
80ced186
MG		 4888 if (err == EMULATE_DO_MMIO) {
4889 ret = 0;
4890 goto out;
4891 }
1d5a4d9b 4892
6d77dbfc
GN		 4893 if (err != EMULATE_DONE)
4894 return 0;
ea953ef0
MG		 4895
4896 if (signal_pending(current))
80ced186 4897 goto out;
ea953ef0
MG		 4898 if (need_resched())
4899 schedule();
4900 }
4901
80ced186
MG		 4902 vmx->emulation_required = 0;
4903out:
4904 return ret;
ea953ef0
MG		 4905}
4906
4b8d54f9
ZE		 4907/*
4908 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4909 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4910 */
9fb41ba8 4911static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4912{
4913 skip_emulated_instruction(vcpu);
4914 kvm_vcpu_on_spin(vcpu);
4915
4916 return 1;
4917}
4918
59708670
SY		 4919static int handle_invalid_op(struct kvm_vcpu *vcpu)
4920{
4921 kvm_queue_exception(vcpu, UD_VECTOR);
4922 return 1;
4923}
4924
ff2f6fe9
NHE		 4925/*
4926 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4927 * We could reuse a single VMCS for all the L2 guests, but we also want the
4928 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4929 * allows keeping them loaded on the processor, and in the future will allow
4930 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4931 * every entry if they never change.
4932 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4933 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4934 *
4935 * The following functions allocate and free a vmcs02 in this pool.
4936 */
4937
4938/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4939static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4940{
4941 struct vmcs02_list *item;
4942 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4943 if (item->vmptr == vmx->nested.current_vmptr) {
4944 list_move(&item->list, &vmx->nested.vmcs02_pool);
4945 return &item->vmcs02;
4946 }
4947
4948 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4949 /* Recycle the least recently used VMCS. */
4950 item = list_entry(vmx->nested.vmcs02_pool.prev,
4951 struct vmcs02_list, list);
4952 item->vmptr = vmx->nested.current_vmptr;
4953 list_move(&item->list, &vmx->nested.vmcs02_pool);
4954 return &item->vmcs02;
4955 }
4956
4957 /* Create a new VMCS */
4958 item = (struct vmcs02_list *)
4959 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4960 if (!item)
4961 return NULL;
4962 item->vmcs02.vmcs = alloc_vmcs();
4963 if (!item->vmcs02.vmcs) {
4964 kfree(item);
4965 return NULL;
4966 }
4967 loaded_vmcs_init(&item->vmcs02);
4968 item->vmptr = vmx->nested.current_vmptr;
4969 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4970 vmx->nested.vmcs02_num++;
4971 return &item->vmcs02;
4972}
4973
4974/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4975static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4976{
4977 struct vmcs02_list *item;
4978 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4979 if (item->vmptr == vmptr) {
4980 free_loaded_vmcs(&item->vmcs02);
4981 list_del(&item->list);
4982 kfree(item);
4983 vmx->nested.vmcs02_num--;
4984 return;
4985 }
4986}
4987
4988/*
4989 * Free all VMCSs saved for this vcpu, except the one pointed by
4990 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4991 * currently used, if running L2), and vmcs01 when running L2.
4992 */
4993static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4994{
4995 struct vmcs02_list *item, *n;
4996 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4997 if (vmx->loaded_vmcs != &item->vmcs02)
4998 free_loaded_vmcs(&item->vmcs02);
4999 list_del(&item->list);
5000 kfree(item);
5001 }
5002 vmx->nested.vmcs02_num = 0;
5003
5004 if (vmx->loaded_vmcs != &vmx->vmcs01)
5005 free_loaded_vmcs(&vmx->vmcs01);
5006}
5007
ec378aee
NHE		 5008/*
5009 * Emulate the VMXON instruction.
5010 * Currently, we just remember that VMX is active, and do not save or even
5011 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5012 * do not currently need to store anything in that guest-allocated memory
5013 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5014 * argument is different from the VMXON pointer (which the spec says they do).
5015 */
5016static int handle_vmon(struct kvm_vcpu *vcpu)
5017{
5018 struct kvm_segment cs;
5019 struct vcpu_vmx *vmx = to_vmx(vcpu);
5020
5021 /* The Intel VMX Instruction Reference lists a bunch of bits that
5022 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5023 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5024 * Otherwise, we should fail with #UD. We test these now:
5025 */
5026 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5027 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5028 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5029 kvm_queue_exception(vcpu, UD_VECTOR);
5030 return 1;
5031 }
5032
5033 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5034 if (is_long_mode(vcpu) && !cs.l) {
5035 kvm_queue_exception(vcpu, UD_VECTOR);
5036 return 1;
5037 }
5038
5039 if (vmx_get_cpl(vcpu)) {
5040 kvm_inject_gp(vcpu, 0);
5041 return 1;
5042 }
5043
ff2f6fe9
NHE		 5044 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5045 vmx->nested.vmcs02_num = 0;
5046
ec378aee
NHE		 5047 vmx->nested.vmxon = true;
5048
5049 skip_emulated_instruction(vcpu);
5050 return 1;
5051}
5052
5053/*
5054 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5055 * for running VMX instructions (except VMXON, whose prerequisites are
5056 * slightly different). It also specifies what exception to inject otherwise.
5057 */
5058static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5059{
5060 struct kvm_segment cs;
5061 struct vcpu_vmx *vmx = to_vmx(vcpu);
5062
5063 if (!vmx->nested.vmxon) {
5064 kvm_queue_exception(vcpu, UD_VECTOR);
5065 return 0;
5066 }
5067
5068 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5069 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5070 (is_long_mode(vcpu) && !cs.l)) {
5071 kvm_queue_exception(vcpu, UD_VECTOR);
5072 return 0;
5073 }
5074
5075 if (vmx_get_cpl(vcpu)) {
5076 kvm_inject_gp(vcpu, 0);
5077 return 0;
5078 }
5079
5080 return 1;
5081}
5082
5083/*
5084 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5085 * just stops using VMX.
5086 */
5087static void free_nested(struct vcpu_vmx *vmx)
5088{
5089 if (!vmx->nested.vmxon)
5090 return;
5091 vmx->nested.vmxon = false;
a9d30f33
NHE		 5092 if (vmx->nested.current_vmptr != -1ull) {
5093 kunmap(vmx->nested.current_vmcs12_page);
5094 nested_release_page(vmx->nested.current_vmcs12_page);
5095 vmx->nested.current_vmptr = -1ull;
5096 vmx->nested.current_vmcs12 = NULL;
5097 }
fe3ef05c
NHE		 5098 /* Unpin physical memory we referred to in current vmcs02 */
5099 if (vmx->nested.apic_access_page) {
5100 nested_release_page(vmx->nested.apic_access_page);
5101 vmx->nested.apic_access_page = 0;
5102 }
ff2f6fe9
NHE		 5103
5104 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5105}
5106
5107/* Emulate the VMXOFF instruction */
5108static int handle_vmoff(struct kvm_vcpu *vcpu)
5109{
5110 if (!nested_vmx_check_permission(vcpu))
5111 return 1;
5112 free_nested(to_vmx(vcpu));
5113 skip_emulated_instruction(vcpu);
5114 return 1;
5115}
5116
064aea77
NHE		 5117/*
5118 * Decode the memory-address operand of a vmx instruction, as recorded on an
5119 * exit caused by such an instruction (run by a guest hypervisor).
5120 * On success, returns 0. When the operand is invalid, returns 1 and throws
5121 * #UD or #GP.
5122 */
5123static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5124 unsigned long exit_qualification,
5125 u32 vmx_instruction_info, gva_t *ret)
5126{
5127 /*
5128 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5129 * Execution", on an exit, vmx_instruction_info holds most of the
5130 * addressing components of the operand. Only the displacement part
5131 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5132 * For how an actual address is calculated from all these components,
5133 * refer to Vol. 1, "Operand Addressing".
5134 */
5135 int scaling = vmx_instruction_info & 3;
5136 int addr_size = (vmx_instruction_info >> 7) & 7;
5137 bool is_reg = vmx_instruction_info & (1u << 10);
5138 int seg_reg = (vmx_instruction_info >> 15) & 7;
5139 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5140 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5141 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5142 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5143
5144 if (is_reg) {
5145 kvm_queue_exception(vcpu, UD_VECTOR);
5146 return 1;
5147 }
5148
5149 /* Addr = segment_base + offset */
5150 /* offset = base + [index * scale] + displacement */
5151 *ret = vmx_get_segment_base(vcpu, seg_reg);
5152 if (base_is_valid)
5153 *ret += kvm_register_read(vcpu, base_reg);
5154 if (index_is_valid)
5155 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5156 *ret += exit_qualification; /* holds the displacement */
5157
5158 if (addr_size == 1) /* 32 bit */
5159 *ret &= 0xffffffff;
5160
5161 /*
5162 * TODO: throw #GP (and return 1) in various cases that the VM*
5163 * instructions require it - e.g., offset beyond segment limit,
5164 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5165 * address, and so on. Currently these are not checked.
5166 */
5167 return 0;
5168}
5169
0140caea
NHE		 5170/*
5171 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5172 * set the success or error code of an emulated VMX instruction, as specified
5173 * by Vol 2B, VMX Instruction Reference, "Conventions".
5174 */
5175static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5176{
5177 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5178 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5179 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5180}
5181
5182static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5183{
5184 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5185 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5186 X86_EFLAGS_SF | X86_EFLAGS_OF))
5187 | X86_EFLAGS_CF);
5188}
5189
5190static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5191 u32 vm_instruction_error)
5192{
5193 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5194 /*
5195 * failValid writes the error number to the current VMCS, which
5196 * can't be done there isn't a current VMCS.
5197 */
5198 nested_vmx_failInvalid(vcpu);
5199 return;
5200 }
5201 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5202 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5203 X86_EFLAGS_SF | X86_EFLAGS_OF))
5204 | X86_EFLAGS_ZF);
5205 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5206}
5207
27d6c865
NHE		 5208/* Emulate the VMCLEAR instruction */
5209static int handle_vmclear(struct kvm_vcpu *vcpu)
5210{
5211 struct vcpu_vmx *vmx = to_vmx(vcpu);
5212 gva_t gva;
5213 gpa_t vmptr;
5214 struct vmcs12 *vmcs12;
5215 struct page *page;
5216 struct x86_exception e;
5217
5218 if (!nested_vmx_check_permission(vcpu))
5219 return 1;
5220
5221 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5222 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5223 return 1;
5224
5225 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5226 sizeof(vmptr), &e)) {
5227 kvm_inject_page_fault(vcpu, &e);
5228 return 1;
5229 }
5230
5231 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5232 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5233 skip_emulated_instruction(vcpu);
5234 return 1;
5235 }
5236
5237 if (vmptr == vmx->nested.current_vmptr) {
5238 kunmap(vmx->nested.current_vmcs12_page);
5239 nested_release_page(vmx->nested.current_vmcs12_page);
5240 vmx->nested.current_vmptr = -1ull;
5241 vmx->nested.current_vmcs12 = NULL;
5242 }
5243
5244 page = nested_get_page(vcpu, vmptr);
5245 if (page == NULL) {
5246 /*
5247 * For accurate processor emulation, VMCLEAR beyond available
5248 * physical memory should do nothing at all. However, it is
5249 * possible that a nested vmx bug, not a guest hypervisor bug,
5250 * resulted in this case, so let's shut down before doing any
5251 * more damage:
5252 */
5253 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5254 return 1;
5255 }
5256 vmcs12 = kmap(page);
5257 vmcs12->launch_state = 0;
5258 kunmap(page);
5259 nested_release_page(page);
5260
5261 nested_free_vmcs02(vmx, vmptr);
5262
5263 skip_emulated_instruction(vcpu);
5264 nested_vmx_succeed(vcpu);
5265 return 1;
5266}
5267
cd232ad0
NHE		 5268static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5269
5270/* Emulate the VMLAUNCH instruction */
5271static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5272{
5273 return nested_vmx_run(vcpu, true);
5274}
5275
5276/* Emulate the VMRESUME instruction */
5277static int handle_vmresume(struct kvm_vcpu *vcpu)
5278{
5279
5280 return nested_vmx_run(vcpu, false);
5281}
5282
49f705c5
NHE		 5283enum vmcs_field_type {
5284 VMCS_FIELD_TYPE_U16 = 0,
5285 VMCS_FIELD_TYPE_U64 = 1,
5286 VMCS_FIELD_TYPE_U32 = 2,
5287 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5288};
5289
5290static inline int vmcs_field_type(unsigned long field)
5291{
5292 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5293 return VMCS_FIELD_TYPE_U32;
5294 return (field >> 13) & 0x3 ;
5295}
5296
5297static inline int vmcs_field_readonly(unsigned long field)
5298{
5299 return (((field >> 10) & 0x3) == 1);
5300}
5301
5302/*
5303 * Read a vmcs12 field. Since these can have varying lengths and we return
5304 * one type, we chose the biggest type (u64) and zero-extend the return value
5305 * to that size. Note that the caller, handle_vmread, might need to use only
5306 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5307 * 64-bit fields are to be returned).
5308 */
5309static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5310 unsigned long field, u64 *ret)
5311{
5312 short offset = vmcs_field_to_offset(field);
5313 char *p;
5314
5315 if (offset < 0)
5316 return 0;
5317
5318 p = ((char *)(get_vmcs12(vcpu))) + offset;
5319
5320 switch (vmcs_field_type(field)) {
5321 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5322 *ret = *((natural_width *)p);
5323 return 1;
5324 case VMCS_FIELD_TYPE_U16:
5325 *ret = *((u16 *)p);
5326 return 1;
5327 case VMCS_FIELD_TYPE_U32:
5328 *ret = *((u32 *)p);
5329 return 1;
5330 case VMCS_FIELD_TYPE_U64:
5331 *ret = *((u64 *)p);
5332 return 1;
5333 default:
5334 return 0; /* can never happen. */
5335 }
5336}
5337
5338/*
5339 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5340 * used before) all generate the same failure when it is missing.
5341 */
5342static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5343{
5344 struct vcpu_vmx *vmx = to_vmx(vcpu);
5345 if (vmx->nested.current_vmptr == -1ull) {
5346 nested_vmx_failInvalid(vcpu);
5347 skip_emulated_instruction(vcpu);
5348 return 0;
5349 }
5350 return 1;
5351}
5352
5353static int handle_vmread(struct kvm_vcpu *vcpu)
5354{
5355 unsigned long field;
5356 u64 field_value;
5357 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5358 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5359 gva_t gva = 0;
5360
5361 if (!nested_vmx_check_permission(vcpu) ||
5362 !nested_vmx_check_vmcs12(vcpu))
5363 return 1;
5364
5365 /* Decode instruction info and find the field to read */
5366 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5367 /* Read the field, zero-extended to a u64 field_value */
5368 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5369 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5370 skip_emulated_instruction(vcpu);
5371 return 1;
5372 }
5373 /*
5374 * Now copy part of this value to register or memory, as requested.
5375 * Note that the number of bits actually copied is 32 or 64 depending
5376 * on the guest's mode (32 or 64 bit), not on the given field's length.
5377 */
5378 if (vmx_instruction_info & (1u << 10)) {
5379 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5380 field_value);
5381 } else {
5382 if (get_vmx_mem_address(vcpu, exit_qualification,
5383 vmx_instruction_info, &gva))
5384 return 1;
5385 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5386 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5387 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5388 }
5389
5390 nested_vmx_succeed(vcpu);
5391 skip_emulated_instruction(vcpu);
5392 return 1;
5393}
5394
5395
5396static int handle_vmwrite(struct kvm_vcpu *vcpu)
5397{
5398 unsigned long field;
5399 gva_t gva;
5400 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5401 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5402 char *p;
5403 short offset;
5404 /* The value to write might be 32 or 64 bits, depending on L1's long
5405 * mode, and eventually we need to write that into a field of several
5406 * possible lengths. The code below first zero-extends the value to 64
5407 * bit (field_value), and then copies only the approriate number of
5408 * bits into the vmcs12 field.
5409 */
5410 u64 field_value = 0;
5411 struct x86_exception e;
5412
5413 if (!nested_vmx_check_permission(vcpu) ||
5414 !nested_vmx_check_vmcs12(vcpu))
5415 return 1;
5416
5417 if (vmx_instruction_info & (1u << 10))
5418 field_value = kvm_register_read(vcpu,
5419 (((vmx_instruction_info) >> 3) & 0xf));
5420 else {
5421 if (get_vmx_mem_address(vcpu, exit_qualification,
5422 vmx_instruction_info, &gva))
5423 return 1;
5424 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5425 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5426 kvm_inject_page_fault(vcpu, &e);
5427 return 1;
5428 }
5429 }
5430
5431
5432 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5433 if (vmcs_field_readonly(field)) {
5434 nested_vmx_failValid(vcpu,
5435 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5436 skip_emulated_instruction(vcpu);
5437 return 1;
5438 }
5439
5440 offset = vmcs_field_to_offset(field);
5441 if (offset < 0) {
5442 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5443 skip_emulated_instruction(vcpu);
5444 return 1;
5445 }
5446 p = ((char *) get_vmcs12(vcpu)) + offset;
5447
5448 switch (vmcs_field_type(field)) {
5449 case VMCS_FIELD_TYPE_U16:
5450 *(u16 *)p = field_value;
5451 break;
5452 case VMCS_FIELD_TYPE_U32:
5453 *(u32 *)p = field_value;
5454 break;
5455 case VMCS_FIELD_TYPE_U64:
5456 *(u64 *)p = field_value;
5457 break;
5458 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5459 *(natural_width *)p = field_value;
5460 break;
5461 default:
5462 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5463 skip_emulated_instruction(vcpu);
5464 return 1;
5465 }
5466
5467 nested_vmx_succeed(vcpu);
5468 skip_emulated_instruction(vcpu);
5469 return 1;
5470}
5471
63846663
NHE		 5472/* Emulate the VMPTRLD instruction */
5473static int handle_vmptrld(struct kvm_vcpu *vcpu)
5474{
5475 struct vcpu_vmx *vmx = to_vmx(vcpu);
5476 gva_t gva;
5477 gpa_t vmptr;
5478 struct x86_exception e;
5479
5480 if (!nested_vmx_check_permission(vcpu))
5481 return 1;
5482
5483 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5484 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5485 return 1;
5486
5487 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5488 sizeof(vmptr), &e)) {
5489 kvm_inject_page_fault(vcpu, &e);
5490 return 1;
5491 }
5492
5493 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5494 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5495 skip_emulated_instruction(vcpu);
5496 return 1;
5497 }
5498
5499 if (vmx->nested.current_vmptr != vmptr) {
5500 struct vmcs12 *new_vmcs12;
5501 struct page *page;
5502 page = nested_get_page(vcpu, vmptr);
5503 if (page == NULL) {
5504 nested_vmx_failInvalid(vcpu);
5505 skip_emulated_instruction(vcpu);
5506 return 1;
5507 }
5508 new_vmcs12 = kmap(page);
5509 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5510 kunmap(page);
5511 nested_release_page_clean(page);
5512 nested_vmx_failValid(vcpu,
5513 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5514 skip_emulated_instruction(vcpu);
5515 return 1;
5516 }
5517 if (vmx->nested.current_vmptr != -1ull) {
5518 kunmap(vmx->nested.current_vmcs12_page);
5519 nested_release_page(vmx->nested.current_vmcs12_page);
5520 }
5521
5522 vmx->nested.current_vmptr = vmptr;
5523 vmx->nested.current_vmcs12 = new_vmcs12;
5524 vmx->nested.current_vmcs12_page = page;
5525 }
5526
5527 nested_vmx_succeed(vcpu);
5528 skip_emulated_instruction(vcpu);
5529 return 1;
5530}
5531
6a4d7550
NHE		 5532/* Emulate the VMPTRST instruction */
5533static int handle_vmptrst(struct kvm_vcpu *vcpu)
5534{
5535 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5536 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5537 gva_t vmcs_gva;
5538 struct x86_exception e;
5539
5540 if (!nested_vmx_check_permission(vcpu))
5541 return 1;
5542
5543 if (get_vmx_mem_address(vcpu, exit_qualification,
5544 vmx_instruction_info, &vmcs_gva))
5545 return 1;
5546 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5547 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5548 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5549 sizeof(u64), &e)) {
5550 kvm_inject_page_fault(vcpu, &e);
5551 return 1;
5552 }
5553 nested_vmx_succeed(vcpu);
5554 skip_emulated_instruction(vcpu);
5555 return 1;
5556}
5557
6aa8b732
AK		 5558/*
5559 * The exit handlers return 1 if the exit was handled fully and guest execution
5560 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5561 * to be done to userspace and return 0.
5562 */
851ba692 5563static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5564 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5565 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5566 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5567 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5568 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5569 [EXIT_REASON_CR_ACCESS] = handle_cr,
5570 [EXIT_REASON_DR_ACCESS] = handle_dr,
5571 [EXIT_REASON_CPUID] = handle_cpuid,
5572 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5573 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5574 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5575 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5576 [EXIT_REASON_INVD] = handle_invd,
a7052897 5577 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5578 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5579 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5580 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5581 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5582 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5583 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5584 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5585 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5586 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5587 [EXIT_REASON_VMOFF] = handle_vmoff,
5588 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5589 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5590 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5591 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5592 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5593 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5594 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5595 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5596 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5597 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5598 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5599 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5600};
5601
5602static const int kvm_vmx_max_exit_handlers =
50a3485c 5603 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5604
644d711a
NHE		 5605/*
5606 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5607 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5608 * disinterest in the current event (read or write a specific MSR) by using an
5609 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5610 */
5611static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5612 struct vmcs12 *vmcs12, u32 exit_reason)
5613{
5614 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5615 gpa_t bitmap;
5616
5617 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5618 return 1;
5619
5620 /*
5621 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5622 * for the four combinations of read/write and low/high MSR numbers.
5623 * First we need to figure out which of the four to use:
5624 */
5625 bitmap = vmcs12->msr_bitmap;
5626 if (exit_reason == EXIT_REASON_MSR_WRITE)
5627 bitmap += 2048;
5628 if (msr_index >= 0xc0000000) {
5629 msr_index -= 0xc0000000;
5630 bitmap += 1024;
5631 }
5632
5633 /* Then read the msr_index'th bit from this bitmap: */
5634 if (msr_index < 1024*8) {
5635 unsigned char b;
5636 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5637 return 1 & (b >> (msr_index & 7));
5638 } else
5639 return 1; /* let L1 handle the wrong parameter */
5640}
5641
5642/*
5643 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5644 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5645 * intercept (via guest_host_mask etc.) the current event.
5646 */
5647static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5648 struct vmcs12 *vmcs12)
5649{
5650 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5651 int cr = exit_qualification & 15;
5652 int reg = (exit_qualification >> 8) & 15;
5653 unsigned long val = kvm_register_read(vcpu, reg);
5654
5655 switch ((exit_qualification >> 4) & 3) {
5656 case 0: /* mov to cr */
5657 switch (cr) {
5658 case 0:
5659 if (vmcs12->cr0_guest_host_mask &
5660 (val ^ vmcs12->cr0_read_shadow))
5661 return 1;
5662 break;
5663 case 3:
5664 if ((vmcs12->cr3_target_count >= 1 &&
5665 vmcs12->cr3_target_value0 == val) ||
5666 (vmcs12->cr3_target_count >= 2 &&
5667 vmcs12->cr3_target_value1 == val) ||
5668 (vmcs12->cr3_target_count >= 3 &&
5669 vmcs12->cr3_target_value2 == val) ||
5670 (vmcs12->cr3_target_count >= 4 &&
5671 vmcs12->cr3_target_value3 == val))
5672 return 0;
5673 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5674 return 1;
5675 break;
5676 case 4:
5677 if (vmcs12->cr4_guest_host_mask &
5678 (vmcs12->cr4_read_shadow ^ val))
5679 return 1;
5680 break;
5681 case 8:
5682 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5683 return 1;
5684 break;
5685 }
5686 break;
5687 case 2: /* clts */
5688 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5689 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5690 return 1;
5691 break;
5692 case 1: /* mov from cr */
5693 switch (cr) {
5694 case 3:
5695 if (vmcs12->cpu_based_vm_exec_control &
5696 CPU_BASED_CR3_STORE_EXITING)
5697 return 1;
5698 break;
5699 case 8:
5700 if (vmcs12->cpu_based_vm_exec_control &
5701 CPU_BASED_CR8_STORE_EXITING)
5702 return 1;
5703 break;
5704 }
5705 break;
5706 case 3: /* lmsw */
5707 /*
5708 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5709 * cr0. Other attempted changes are ignored, with no exit.
5710 */
5711 if (vmcs12->cr0_guest_host_mask & 0xe &
5712 (val ^ vmcs12->cr0_read_shadow))
5713 return 1;
5714 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5715 !(vmcs12->cr0_read_shadow & 0x1) &&
5716 (val & 0x1))
5717 return 1;
5718 break;
5719 }
5720 return 0;
5721}
5722
5723/*
5724 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5725 * should handle it ourselves in L0 (and then continue L2). Only call this
5726 * when in is_guest_mode (L2).
5727 */
5728static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5729{
5730 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5731 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5732 struct vcpu_vmx *vmx = to_vmx(vcpu);
5733 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5734
5735 if (vmx->nested.nested_run_pending)
5736 return 0;
5737
5738 if (unlikely(vmx->fail)) {
bd80158a
JK		 5739 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5740 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5741 return 1;
5742 }
5743
5744 switch (exit_reason) {
5745 case EXIT_REASON_EXCEPTION_NMI:
5746 if (!is_exception(intr_info))
5747 return 0;
5748 else if (is_page_fault(intr_info))
5749 return enable_ept;
5750 return vmcs12->exception_bitmap &
5751 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5752 case EXIT_REASON_EXTERNAL_INTERRUPT:
5753 return 0;
5754 case EXIT_REASON_TRIPLE_FAULT:
5755 return 1;
5756 case EXIT_REASON_PENDING_INTERRUPT:
5757 case EXIT_REASON_NMI_WINDOW:
5758 /*
5759 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5760 * (aka Interrupt Window Exiting) only when L1 turned it on,
5761 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5762 * Same for NMI Window Exiting.
5763 */
5764 return 1;
5765 case EXIT_REASON_TASK_SWITCH:
5766 return 1;
5767 case EXIT_REASON_CPUID:
5768 return 1;
5769 case EXIT_REASON_HLT:
5770 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5771 case EXIT_REASON_INVD:
5772 return 1;
5773 case EXIT_REASON_INVLPG:
5774 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5775 case EXIT_REASON_RDPMC:
5776 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5777 case EXIT_REASON_RDTSC:
5778 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5779 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5780 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5781 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5782 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5783 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5784 /*
5785 * VMX instructions trap unconditionally. This allows L1 to
5786 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5787 */
5788 return 1;
5789 case EXIT_REASON_CR_ACCESS:
5790 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5791 case EXIT_REASON_DR_ACCESS:
5792 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5793 case EXIT_REASON_IO_INSTRUCTION:
5794 /* TODO: support IO bitmaps */
5795 return 1;
5796 case EXIT_REASON_MSR_READ:
5797 case EXIT_REASON_MSR_WRITE:
5798 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5799 case EXIT_REASON_INVALID_STATE:
5800 return 1;
5801 case EXIT_REASON_MWAIT_INSTRUCTION:
5802 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5803 case EXIT_REASON_MONITOR_INSTRUCTION:
5804 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5805 case EXIT_REASON_PAUSE_INSTRUCTION:
5806 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5807 nested_cpu_has2(vmcs12,
5808 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5809 case EXIT_REASON_MCE_DURING_VMENTRY:
5810 return 0;
5811 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5812 return 1;
5813 case EXIT_REASON_APIC_ACCESS:
5814 return nested_cpu_has2(vmcs12,
5815 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5816 case EXIT_REASON_EPT_VIOLATION:
5817 case EXIT_REASON_EPT_MISCONFIG:
5818 return 0;
5819 case EXIT_REASON_WBINVD:
5820 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5821 case EXIT_REASON_XSETBV:
5822 return 1;
5823 default:
5824 return 1;
5825 }
5826}
5827
586f9607
AK		 5828static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5829{
5830 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5831 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5832}
5833
6aa8b732
AK		 5834/*
5835 * The guest has exited. See if we can fix it or if we need userspace
5836 * assistance.
5837 */
851ba692 5838static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5839{
29bd8a78 5840 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5841 u32 exit_reason = vmx->exit_reason;
1155f76a 5842 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5843
80ced186
MG		 5844 /* If guest state is invalid, start emulating */
5845 if (vmx->emulation_required && emulate_invalid_guest_state)
5846 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5847
b6f1250e
NHE		 5848 /*
5849 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5850 * we did not inject a still-pending event to L1 now because of
5851 * nested_run_pending, we need to re-enable this bit.
5852 */
5853 if (vmx->nested.nested_run_pending)
5854 kvm_make_request(KVM_REQ_EVENT, vcpu);
5855
509c75ea
NHE		 5856 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5857 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5858 vmx->nested.nested_run_pending = 1;
5859 else
5860 vmx->nested.nested_run_pending = 0;
5861
5862 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5863 nested_vmx_vmexit(vcpu);
5864 return 1;
5865 }
5866
5120702e
MG		 5867 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5868 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5869 vcpu->run->fail_entry.hardware_entry_failure_reason
5870 = exit_reason;
5871 return 0;
5872 }
5873
29bd8a78 5874 if (unlikely(vmx->fail)) {
851ba692
AK		 5875 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5876 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5877 = vmcs_read32(VM_INSTRUCTION_ERROR);
5878 return 0;
5879 }
6aa8b732 5880
d77c26fc 5881 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5882 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5883 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5884 exit_reason != EXIT_REASON_TASK_SWITCH))
5885 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5886 "(0x%x) and exit reason is 0x%x\n",
5887 __func__, vectoring_info, exit_reason);
3b86cd99 5888
644d711a
NHE		 5889 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5890 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5891 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5892 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5893 vmx->soft_vnmi_blocked = 0;
3b86cd99 5894 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5895 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5896 /*
5897 * This CPU don't support us in finding the end of an
5898 * NMI-blocked window if the guest runs with IRQs
5899 * disabled. So we pull the trigger after 1 s of
5900 * futile waiting, but inform the user about this.
5901 */
5902 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5903 "state on VCPU %d after 1 s timeout\n",
5904 __func__, vcpu->vcpu_id);
5905 vmx->soft_vnmi_blocked = 0;
3b86cd99 5906 }
3b86cd99
JK		 5907 }
5908
6aa8b732
AK		 5909 if (exit_reason < kvm_vmx_max_exit_handlers
5910 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5911 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5912 else {
851ba692
AK		 5913 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5914 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5915 }
5916 return 0;
5917}
5918
95ba8273 5919static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5920{
95ba8273 5921 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5922 vmcs_write32(TPR_THRESHOLD, 0);
5923 return;
5924 }
5925
95ba8273 5926 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5927}
5928
51aa01d1 5929static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5930{
00eba012
AK		 5931 u32 exit_intr_info;
5932
5933 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5934 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5935 return;
5936
c5ca8e57 5937 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5938 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5939
5940 /* Handle machine checks before interrupts are enabled */
00eba012 5941 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5942 kvm_machine_check();
5943
20f65983 5944 /* We need to handle NMIs before interrupts are enabled */
00eba012 5945 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5946 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5947 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5948 asm("int $2");
ff9d07a0
ZY		 5949 kvm_after_handle_nmi(&vmx->vcpu);
5950 }
51aa01d1 5951}
20f65983 5952
51aa01d1
AK		 5953static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5954{
c5ca8e57 5955 u32 exit_intr_info;
51aa01d1
AK		 5956 bool unblock_nmi;
5957 u8 vector;
5958 bool idtv_info_valid;
5959
5960 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5961
cf393f75 5962 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5963 if (vmx->nmi_known_unmasked)
5964 return;
c5ca8e57
AK		 5965 /*
5966 * Can't use vmx->exit_intr_info since we're not sure what
5967 * the exit reason is.
5968 */
5969 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5970 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5971 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5972 /*
7b4a25cb 5973 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5974 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5975 * a guest IRET fault.
7b4a25cb
GN		 5976 * SDM 3: 23.2.2 (September 2008)
5977 * Bit 12 is undefined in any of the following cases:
5978 * If the VM exit sets the valid bit in the IDT-vectoring
5979 * information field.
5980 * If the VM exit is due to a double fault.
cf393f75 5981 */
7b4a25cb
GN		 5982 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5983 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5984 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5985 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5986 else
5987 vmx->nmi_known_unmasked =
5988 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5989 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5990 } else if (unlikely(vmx->soft_vnmi_blocked))
5991 vmx->vnmi_blocked_time +=
5992 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5993}
5994
83422e17
AK		 5995static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5996 u32 idt_vectoring_info,
5997 int instr_len_field,
5998 int error_code_field)
51aa01d1 5999{
51aa01d1
AK		 6000 u8 vector;
6001 int type;
6002 bool idtv_info_valid;
6003
6004 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6005
37b96e98
GN		 6006 vmx->vcpu.arch.nmi_injected = false;
6007 kvm_clear_exception_queue(&vmx->vcpu);
6008 kvm_clear_interrupt_queue(&vmx->vcpu);
6009
6010 if (!idtv_info_valid)
6011 return;
6012
3842d135
AK		 6013 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6014
668f612f
AK		 6015 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6016 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6017
64a7ec06 6018 switch (type) {
37b96e98
GN		 6019 case INTR_TYPE_NMI_INTR:
6020 vmx->vcpu.arch.nmi_injected = true;
668f612f 6021 /*
7b4a25cb 6022 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6023 * Clear bit "block by NMI" before VM entry if a NMI
6024 * delivery faulted.
668f612f 6025 */
654f06fc 6026 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6027 break;
37b96e98 6028 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6029 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6030 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6031 /* fall through */
6032 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6033 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6034 u32 err = vmcs_read32(error_code_field);
37b96e98 6035 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6036 } else
6037 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6038 break;
66fd3f7f
GN		 6039 case INTR_TYPE_SOFT_INTR:
6040 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6041 vmcs_read32(instr_len_field);
66fd3f7f 6042 /* fall through */
37b96e98 6043 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6044 kvm_queue_interrupt(&vmx->vcpu, vector,
6045 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6046 break;
6047 default:
6048 break;
f7d9238f 6049 }
cf393f75
AK		 6050}
6051
83422e17
AK		 6052static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6053{
66c78ae4
NHE		 6054 if (is_guest_mode(&vmx->vcpu))
6055 return;
83422e17
AK		 6056 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6057 VM_EXIT_INSTRUCTION_LEN,
6058 IDT_VECTORING_ERROR_CODE);
6059}
6060
b463a6f7
AK		 6061static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6062{
66c78ae4
NHE		 6063 if (is_guest_mode(vcpu))
6064 return;
b463a6f7
AK		 6065 __vmx_complete_interrupts(to_vmx(vcpu),
6066 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6067 VM_ENTRY_INSTRUCTION_LEN,
6068 VM_ENTRY_EXCEPTION_ERROR_CODE);
6069
6070 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6071}
6072
d7cd9796
GN		 6073static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6074{
6075 int i, nr_msrs;
6076 struct perf_guest_switch_msr *msrs;
6077
6078 msrs = perf_guest_get_msrs(&nr_msrs);
6079
6080 if (!msrs)
6081 return;
6082
6083 for (i = 0; i < nr_msrs; i++)
6084 if (msrs[i].host == msrs[i].guest)
6085 clear_atomic_switch_msr(vmx, msrs[i].msr);
6086 else
6087 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6088 msrs[i].host);
6089}
6090
c801949d
AK		 6091#ifdef CONFIG_X86_64
6092#define R "r"
6093#define Q "q"
6094#else
6095#define R "e"
6096#define Q "l"
6097#endif
6098
a3b5ba49 6099static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6100{
a2fa3e9f 6101 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6102
66c78ae4
NHE		 6103 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6104 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6105 if (vmcs12->idt_vectoring_info_field &
6106 VECTORING_INFO_VALID_MASK) {
6107 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6108 vmcs12->idt_vectoring_info_field);
6109 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6110 vmcs12->vm_exit_instruction_len);
6111 if (vmcs12->idt_vectoring_info_field &
6112 VECTORING_INFO_DELIVER_CODE_MASK)
6113 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6114 vmcs12->idt_vectoring_error_code);
6115 }
6116 }
6117
104f226b
AK		 6118 /* Record the guest's net vcpu time for enforced NMI injections. */
6119 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6120 vmx->entry_time = ktime_get();
6121
6122 /* Don't enter VMX if guest state is invalid, let the exit handler
6123 start emulation until we arrive back to a valid state */
6124 if (vmx->emulation_required && emulate_invalid_guest_state)
6125 return;
6126
6127 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6128 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6129 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6130 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6131
6132 /* When single-stepping over STI and MOV SS, we must clear the
6133 * corresponding interruptibility bits in the guest state. Otherwise
6134 * vmentry fails as it then expects bit 14 (BS) in pending debug
6135 * exceptions being set, but that's not correct for the guest debugging
6136 * case. */
6137 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6138 vmx_set_interrupt_shadow(vcpu, 0);
6139
d7cd9796
GN		 6140 atomic_switch_perf_msrs(vmx);
6141
d462b819 6142 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6143 asm(
6aa8b732 6144 /* Store host registers */
c801949d 6145 "push %%"R"dx; push %%"R"bp;"
40712fae 6146 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6147 "push %%"R"cx \n\t"
313dbd49
AK		 6148 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6149 "je 1f \n\t"
6150 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6151 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6152 "1: \n\t"
d3edefc0
AK		 6153 /* Reload cr2 if changed */
6154 "mov %c[cr2](%0), %%"R"ax \n\t"
6155 "mov %%cr2, %%"R"dx \n\t"
6156 "cmp %%"R"ax, %%"R"dx \n\t"
6157 "je 2f \n\t"
6158 "mov %%"R"ax, %%cr2 \n\t"
6159 "2: \n\t"
6aa8b732 6160 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6161 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6162 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6163 "mov %c[rax](%0), %%"R"ax \n\t"
6164 "mov %c[rbx](%0), %%"R"bx \n\t"
6165 "mov %c[rdx](%0), %%"R"dx \n\t"
6166 "mov %c[rsi](%0), %%"R"si \n\t"
6167 "mov %c[rdi](%0), %%"R"di \n\t"
6168 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6169#ifdef CONFIG_X86_64
e08aa78a
AK		 6170 "mov %c[r8](%0), %%r8 \n\t"
6171 "mov %c[r9](%0), %%r9 \n\t"
6172 "mov %c[r10](%0), %%r10 \n\t"
6173 "mov %c[r11](%0), %%r11 \n\t"
6174 "mov %c[r12](%0), %%r12 \n\t"
6175 "mov %c[r13](%0), %%r13 \n\t"
6176 "mov %c[r14](%0), %%r14 \n\t"
6177 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6178#endif
c801949d
AK		 6179 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6180
6aa8b732 6181 /* Enter guest mode */
cd2276a7 6182 "jne .Llaunched \n\t"
4ecac3fd 6183 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6184 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6185 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6186 ".Lkvm_vmx_return: "
6aa8b732 6187 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6188 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6189 "pop %0 \n\t"
c801949d
AK		 6190 "mov %%"R"ax, %c[rax](%0) \n\t"
6191 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6192 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6193 "mov %%"R"dx, %c[rdx](%0) \n\t"
6194 "mov %%"R"si, %c[rsi](%0) \n\t"
6195 "mov %%"R"di, %c[rdi](%0) \n\t"
6196 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6197#ifdef CONFIG_X86_64
e08aa78a
AK		 6198 "mov %%r8, %c[r8](%0) \n\t"
6199 "mov %%r9, %c[r9](%0) \n\t"
6200 "mov %%r10, %c[r10](%0) \n\t"
6201 "mov %%r11, %c[r11](%0) \n\t"
6202 "mov %%r12, %c[r12](%0) \n\t"
6203 "mov %%r13, %c[r13](%0) \n\t"
6204 "mov %%r14, %c[r14](%0) \n\t"
6205 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6206#endif
c801949d
AK		 6207 "mov %%cr2, %%"R"ax \n\t"
6208 "mov %%"R"ax, %c[cr2](%0) \n\t"
6209
1c696d0e 6210 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6211 "setbe %c[fail](%0) \n\t"
6212 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6213 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6214 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6215 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6216 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6217 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6218 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6219 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6220 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6221 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6222 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6223#ifdef CONFIG_X86_64
ad312c7c
ZX		 6224 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6225 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6226 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6227 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6228 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6229 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6230 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6231 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6232#endif
40712fae
AK		 6233 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6234 [wordsize]"i"(sizeof(ulong))
c2036300 6235 : "cc", "memory"
07d6f555 6236 , R"ax", R"bx", R"di", R"si"
c2036300 6237#ifdef CONFIG_X86_64
c2036300
LV		 6238 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6239#endif
6240 );
6aa8b732 6241
6de4f3ad 6242 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6243 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6244 | (1 << VCPU_EXREG_CPL)
aff48baa 6245 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6246 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6247 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6248 vcpu->arch.regs_dirty = 0;
6249
1155f76a
AK		 6250 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6251
66c78ae4
NHE		 6252 if (is_guest_mode(vcpu)) {
6253 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6254 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6255 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6256 vmcs12->idt_vectoring_error_code =
6257 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6258 vmcs12->vm_exit_instruction_len =
6259 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6260 }
6261 }
6262
d77c26fc 6263 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6264 vmx->loaded_vmcs->launched = 1;
1b6269db 6265
51aa01d1 6266 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6267 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6268
6269 vmx_complete_atomic_exit(vmx);
6270 vmx_recover_nmi_blocking(vmx);
cf393f75 6271 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6272}
6273
c801949d
AK		 6274#undef R
6275#undef Q
6276
6aa8b732
AK		 6277static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6278{
fb3f0f51
RR		 6279 struct vcpu_vmx *vmx = to_vmx(vcpu);
6280
cdbecfc3 6281 free_vpid(vmx);
ec378aee 6282 free_nested(vmx);
d462b819 6283 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6284 kfree(vmx->guest_msrs);
6285 kvm_vcpu_uninit(vcpu);
a4770347 6286 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6287}
6288
fb3f0f51 6289static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6290{
fb3f0f51 6291 int err;
c16f862d 6292 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6293 int cpu;
6aa8b732 6294
a2fa3e9f 6295 if (!vmx)
fb3f0f51
RR		 6296 return ERR_PTR(-ENOMEM);
6297
2384d2b3
SY		 6298 allocate_vpid(vmx);
6299
fb3f0f51
RR		 6300 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6301 if (err)
6302 goto free_vcpu;
965b58a5 6303
a2fa3e9f 6304 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6305 err = -ENOMEM;
fb3f0f51 6306 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6307 goto uninit_vcpu;
6308 }
965b58a5 6309
d462b819
NHE		 6310 vmx->loaded_vmcs = &vmx->vmcs01;
6311 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6312 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6313 goto free_msrs;
d462b819
NHE		 6314 if (!vmm_exclusive)
6315 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6316 loaded_vmcs_init(vmx->loaded_vmcs);
6317 if (!vmm_exclusive)
6318 kvm_cpu_vmxoff();
a2fa3e9f 6319
15ad7146
AK		 6320 cpu = get_cpu();
6321 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6322 vmx->vcpu.cpu = cpu;
8b9cf98c 6323 err = vmx_vcpu_setup(vmx);
fb3f0f51 6324 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6325 put_cpu();
fb3f0f51
RR		 6326 if (err)
6327 goto free_vmcs;
5e4a0b3c 6328 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6329 err = alloc_apic_access_page(kvm);
6330 if (err)
5e4a0b3c 6331 goto free_vmcs;
fb3f0f51 6332
b927a3ce
SY		 6333 if (enable_ept) {
6334 if (!kvm->arch.ept_identity_map_addr)
6335 kvm->arch.ept_identity_map_addr =
6336 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6337 err = -ENOMEM;
b7ebfb05
SY		 6338 if (alloc_identity_pagetable(kvm) != 0)
6339 goto free_vmcs;
93ea5388
GN		 6340 if (!init_rmode_identity_map(kvm))
6341 goto free_vmcs;
b927a3ce 6342 }
b7ebfb05 6343
a9d30f33
NHE		 6344 vmx->nested.current_vmptr = -1ull;
6345 vmx->nested.current_vmcs12 = NULL;
6346
fb3f0f51
RR		 6347 return &vmx->vcpu;
6348
6349free_vmcs:
d462b819 6350 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6351free_msrs:
fb3f0f51
RR		 6352 kfree(vmx->guest_msrs);
6353uninit_vcpu:
6354 kvm_vcpu_uninit(&vmx->vcpu);
6355free_vcpu:
cdbecfc3 6356 free_vpid(vmx);
a4770347 6357 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6358 return ERR_PTR(err);
6aa8b732
AK		 6359}
6360
002c7f7c
YS		 6361static void __init vmx_check_processor_compat(void *rtn)
6362{
6363 struct vmcs_config vmcs_conf;
6364
6365 *(int *)rtn = 0;
6366 if (setup_vmcs_config(&vmcs_conf) < 0)
6367 *(int *)rtn = -EIO;
6368 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6369 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6370 smp_processor_id());
6371 *(int *)rtn = -EIO;
6372 }
6373}
6374
67253af5
SY		 6375static int get_ept_level(void)
6376{
6377 return VMX_EPT_DEFAULT_GAW + 1;
6378}
6379
4b12f0de 6380static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6381{
4b12f0de
SY		 6382 u64 ret;
6383
522c68c4
SY		 6384 /* For VT-d and EPT combination
6385 * 1. MMIO: always map as UC
6386 * 2. EPT with VT-d:
6387 * a. VT-d without snooping control feature: can't guarantee the
6388 * result, try to trust guest.
6389 * b. VT-d with snooping control feature: snooping control feature of
6390 * VT-d engine can guarantee the cache correctness. Just set it
6391 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6392 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6393 * consistent with host MTRR
6394 */
4b12f0de
SY		 6395 if (is_mmio)
6396 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6397 else if (vcpu->kvm->arch.iommu_domain &&
6398 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6399 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6400 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6401 else
522c68c4 6402 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6403 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6404
6405 return ret;
64d4d521
SY		 6406}
6407
17cc3935 6408static int vmx_get_lpage_level(void)
344f414f 6409{
878403b7
SY		 6410 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6411 return PT_DIRECTORY_LEVEL;
6412 else
6413 /* For shadow and EPT supported 1GB page */
6414 return PT_PDPE_LEVEL;
344f414f
JR		 6415}
6416
0e851880
SY		 6417static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6418{
4e47c7a6
SY		 6419 struct kvm_cpuid_entry2 *best;
6420 struct vcpu_vmx *vmx = to_vmx(vcpu);
6421 u32 exec_control;
6422
6423 vmx->rdtscp_enabled = false;
6424 if (vmx_rdtscp_supported()) {
6425 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6426 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6427 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6428 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6429 vmx->rdtscp_enabled = true;
6430 else {
6431 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6432 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6433 exec_control);
6434 }
6435 }
6436 }
0e851880
SY		 6437}
6438
d4330ef2
JR		 6439static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6440{
7b8050f5
NHE		 6441 if (func == 1 && nested)
6442 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6443}
6444
fe3ef05c
NHE		 6445/*
6446 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6447 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6448 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6449 * guest in a way that will both be appropriate to L1's requests, and our
6450 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6451 * function also has additional necessary side-effects, like setting various
6452 * vcpu->arch fields.
6453 */
6454static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6455{
6456 struct vcpu_vmx *vmx = to_vmx(vcpu);
6457 u32 exec_control;
6458
6459 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6460 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6461 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6462 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6463 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6464 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6465 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6466 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6467 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6468 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6469 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6470 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6471 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6472 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6473 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6474 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6475 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6476 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6477 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6478 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6479 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6480 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6481 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6482 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6483 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6484 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6485 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6486 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6487 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6488 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6489 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6490 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6491 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6492 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6493 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6494 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6495
6496 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6497 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6498 vmcs12->vm_entry_intr_info_field);
6499 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6500 vmcs12->vm_entry_exception_error_code);
6501 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6502 vmcs12->vm_entry_instruction_len);
6503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6504 vmcs12->guest_interruptibility_info);
6505 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6506 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6507 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6508 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6509 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6510 vmcs12->guest_pending_dbg_exceptions);
6511 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6512 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6513
6514 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6515
6516 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6517 (vmcs_config.pin_based_exec_ctrl |
6518 vmcs12->pin_based_vm_exec_control));
6519
6520 /*
6521 * Whether page-faults are trapped is determined by a combination of
6522 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6523 * If enable_ept, L0 doesn't care about page faults and we should
6524 * set all of these to L1's desires. However, if !enable_ept, L0 does
6525 * care about (at least some) page faults, and because it is not easy
6526 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6527 * to exit on each and every L2 page fault. This is done by setting
6528 * MASK=MATCH=0 and (see below) EB.PF=1.
6529 * Note that below we don't need special code to set EB.PF beyond the
6530 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6531 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6532 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6533 *
6534 * A problem with this approach (when !enable_ept) is that L1 may be
6535 * injected with more page faults than it asked for. This could have
6536 * caused problems, but in practice existing hypervisors don't care.
6537 * To fix this, we will need to emulate the PFEC checking (on the L1
6538 * page tables), using walk_addr(), when injecting PFs to L1.
6539 */
6540 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6541 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6542 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6543 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6544
6545 if (cpu_has_secondary_exec_ctrls()) {
6546 u32 exec_control = vmx_secondary_exec_control(vmx);
6547 if (!vmx->rdtscp_enabled)
6548 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6549 /* Take the following fields only from vmcs12 */
6550 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6551 if (nested_cpu_has(vmcs12,
6552 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6553 exec_control |= vmcs12->secondary_vm_exec_control;
6554
6555 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6556 /*
6557 * Translate L1 physical address to host physical
6558 * address for vmcs02. Keep the page pinned, so this
6559 * physical address remains valid. We keep a reference
6560 * to it so we can release it later.
6561 */
6562 if (vmx->nested.apic_access_page) /* shouldn't happen */
6563 nested_release_page(vmx->nested.apic_access_page);
6564 vmx->nested.apic_access_page =
6565 nested_get_page(vcpu, vmcs12->apic_access_addr);
6566 /*
6567 * If translation failed, no matter: This feature asks
6568 * to exit when accessing the given address, and if it
6569 * can never be accessed, this feature won't do
6570 * anything anyway.
6571 */
6572 if (!vmx->nested.apic_access_page)
6573 exec_control &=
6574 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6575 else
6576 vmcs_write64(APIC_ACCESS_ADDR,
6577 page_to_phys(vmx->nested.apic_access_page));
6578 }
6579
6580 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6581 }
6582
6583
6584 /*
6585 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6586 * Some constant fields are set here by vmx_set_constant_host_state().
6587 * Other fields are different per CPU, and will be set later when
6588 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6589 */
6590 vmx_set_constant_host_state();
6591
6592 /*
6593 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6594 * entry, but only if the current (host) sp changed from the value
6595 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6596 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6597 * here we just force the write to happen on entry.
6598 */
6599 vmx->host_rsp = 0;
6600
6601 exec_control = vmx_exec_control(vmx); /* L0's desires */
6602 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6603 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6604 exec_control &= ~CPU_BASED_TPR_SHADOW;
6605 exec_control |= vmcs12->cpu_based_vm_exec_control;
6606 /*
6607 * Merging of IO and MSR bitmaps not currently supported.
6608 * Rather, exit every time.
6609 */
6610 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6611 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6612 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6613
6614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6615
6616 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6617 * bitwise-or of what L1 wants to trap for L2, and what we want to
6618 * trap. Note that CR0.TS also needs updating - we do this later.
6619 */
6620 update_exception_bitmap(vcpu);
6621 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6622 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6623
6624 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6625 vmcs_write32(VM_EXIT_CONTROLS,
6626 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6627 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6628 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6629
6630 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6631 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6632 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6633 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6634
6635
6636 set_cr4_guest_host_mask(vmx);
6637
27fc51b2
NHE		 6638 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6639 vmcs_write64(TSC_OFFSET,
6640 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6641 else
6642 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6643
6644 if (enable_vpid) {
6645 /*
6646 * Trivially support vpid by letting L2s share their parent
6647 * L1's vpid. TODO: move to a more elaborate solution, giving
6648 * each L2 its own vpid and exposing the vpid feature to L1.
6649 */
6650 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6651 vmx_flush_tlb(vcpu);
6652 }
6653
6654 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6655 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6656 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6657 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6658 else
6659 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6660 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6661 vmx_set_efer(vcpu, vcpu->arch.efer);
6662
6663 /*
6664 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6665 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6666 * The CR0_READ_SHADOW is what L2 should have expected to read given
6667 * the specifications by L1; It's not enough to take
6668 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6669 * have more bits than L1 expected.
6670 */
6671 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6672 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6673
6674 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6675 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6676
6677 /* shadow page tables on either EPT or shadow page tables */
6678 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6679 kvm_mmu_reset_context(vcpu);
6680
6681 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6682 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6683}
6684
cd232ad0
NHE		 6685/*
6686 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6687 * for running an L2 nested guest.
6688 */
6689static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6690{
6691 struct vmcs12 *vmcs12;
6692 struct vcpu_vmx *vmx = to_vmx(vcpu);
6693 int cpu;
6694 struct loaded_vmcs *vmcs02;
6695
6696 if (!nested_vmx_check_permission(vcpu) ||
6697 !nested_vmx_check_vmcs12(vcpu))
6698 return 1;
6699
6700 skip_emulated_instruction(vcpu);
6701 vmcs12 = get_vmcs12(vcpu);
6702
7c177938
NHE		 6703 /*
6704 * The nested entry process starts with enforcing various prerequisites
6705 * on vmcs12 as required by the Intel SDM, and act appropriately when
6706 * they fail: As the SDM explains, some conditions should cause the
6707 * instruction to fail, while others will cause the instruction to seem
6708 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6709 * To speed up the normal (success) code path, we should avoid checking
6710 * for misconfigurations which will anyway be caught by the processor
6711 * when using the merged vmcs02.
6712 */
6713 if (vmcs12->launch_state == launch) {
6714 nested_vmx_failValid(vcpu,
6715 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6716 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6717 return 1;
6718 }
6719
6720 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6721 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6722 /*TODO: Also verify bits beyond physical address width are 0*/
6723 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6724 return 1;
6725 }
6726
6727 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6728 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6729 /*TODO: Also verify bits beyond physical address width are 0*/
6730 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6731 return 1;
6732 }
6733
6734 if (vmcs12->vm_entry_msr_load_count > 0 ||
6735 vmcs12->vm_exit_msr_load_count > 0 ||
6736 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6737 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6738 __func__);
7c177938
NHE		 6739 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6740 return 1;
6741 }
6742
6743 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6744 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6745 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6746 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6747 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6748 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6749 !vmx_control_verify(vmcs12->vm_exit_controls,
6750 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6751 !vmx_control_verify(vmcs12->vm_entry_controls,
6752 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6753 {
6754 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6755 return 1;
6756 }
6757
6758 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6759 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6760 nested_vmx_failValid(vcpu,
6761 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6762 return 1;
6763 }
6764
6765 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6766 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6767 nested_vmx_entry_failure(vcpu, vmcs12,
6768 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6769 return 1;
6770 }
6771 if (vmcs12->vmcs_link_pointer != -1ull) {
6772 nested_vmx_entry_failure(vcpu, vmcs12,
6773 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6774 return 1;
6775 }
6776
6777 /*
6778 * We're finally done with prerequisite checking, and can start with
6779 * the nested entry.
6780 */
6781
cd232ad0
NHE		 6782 vmcs02 = nested_get_current_vmcs02(vmx);
6783 if (!vmcs02)
6784 return -ENOMEM;
6785
6786 enter_guest_mode(vcpu);
6787
6788 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6789
6790 cpu = get_cpu();
6791 vmx->loaded_vmcs = vmcs02;
6792 vmx_vcpu_put(vcpu);
6793 vmx_vcpu_load(vcpu, cpu);
6794 vcpu->cpu = cpu;
6795 put_cpu();
6796
6797 vmcs12->launch_state = 1;
6798
6799 prepare_vmcs02(vcpu, vmcs12);
6800
6801 /*
6802 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6803 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6804 * returned as far as L1 is concerned. It will only return (and set
6805 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6806 */
6807 return 1;
6808}
6809
4704d0be
NHE		 6810/*
6811 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6812 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6813 * This function returns the new value we should put in vmcs12.guest_cr0.
6814 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6815 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6816 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6817 * didn't trap the bit, because if L1 did, so would L0).
6818 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6819 * been modified by L2, and L1 knows it. So just leave the old value of
6820 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6821 * isn't relevant, because if L0 traps this bit it can set it to anything.
6822 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6823 * changed these bits, and therefore they need to be updated, but L0
6824 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6825 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6826 */
6827static inline unsigned long
6828vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6829{
6830 return
6831 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6832 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6833 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6834 vcpu->arch.cr0_guest_owned_bits));
6835}
6836
6837static inline unsigned long
6838vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6839{
6840 return
6841 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6842 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6843 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6844 vcpu->arch.cr4_guest_owned_bits));
6845}
6846
6847/*
6848 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6849 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6850 * and this function updates it to reflect the changes to the guest state while
6851 * L2 was running (and perhaps made some exits which were handled directly by L0
6852 * without going back to L1), and to reflect the exit reason.
6853 * Note that we do not have to copy here all VMCS fields, just those that
6854 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6855 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6856 * which already writes to vmcs12 directly.
6857 */
6858void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6859{
6860 /* update guest state fields: */
6861 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6862 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6863
6864 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6865 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6866 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6867 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6868
6869 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6870 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6871 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6872 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6873 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6874 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6875 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6876 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6877 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6878 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6879 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6880 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6881 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6882 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6883 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6884 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6885 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6886 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6887 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6888 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6889 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6890 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6891 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6892 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6893 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6894 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6895 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6896 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6897 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6898 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6899 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6900 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6901 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6902 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6903 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6904 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6905
6906 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6907 vmcs12->guest_interruptibility_info =
6908 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6909 vmcs12->guest_pending_dbg_exceptions =
6910 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6911
6912 /* TODO: These cannot have changed unless we have MSR bitmaps and
6913 * the relevant bit asks not to trap the change */
6914 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6915 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6916 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6917 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6918 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6919 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6920
6921 /* update exit information fields: */
6922
6923 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6924 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6925
6926 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6927 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6928 vmcs12->idt_vectoring_info_field =
6929 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6930 vmcs12->idt_vectoring_error_code =
6931 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6932 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6933 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6934
6935 /* clear vm-entry fields which are to be cleared on exit */
6936 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6937 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6938}
6939
6940/*
6941 * A part of what we need to when the nested L2 guest exits and we want to
6942 * run its L1 parent, is to reset L1's guest state to the host state specified
6943 * in vmcs12.
6944 * This function is to be called not only on normal nested exit, but also on
6945 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6946 * Failures During or After Loading Guest State").
6947 * This function should be called when the active VMCS is L1's (vmcs01).
6948 */
6949void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6950{
6951 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6952 vcpu->arch.efer = vmcs12->host_ia32_efer;
6953 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6954 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6955 else
6956 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6957 vmx_set_efer(vcpu, vcpu->arch.efer);
6958
6959 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6960 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6961 /*
6962 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6963 * actually changed, because it depends on the current state of
6964 * fpu_active (which may have changed).
6965 * Note that vmx_set_cr0 refers to efer set above.
6966 */
6967 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6968 /*
6969 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6970 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6971 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6972 */
6973 update_exception_bitmap(vcpu);
6974 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6975 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6976
6977 /*
6978 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6979 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6980 */
6981 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6982 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6983
6984 /* shadow page tables on either EPT or shadow page tables */
6985 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6986 kvm_mmu_reset_context(vcpu);
6987
6988 if (enable_vpid) {
6989 /*
6990 * Trivially support vpid by letting L2s share their parent
6991 * L1's vpid. TODO: move to a more elaborate solution, giving
6992 * each L2 its own vpid and exposing the vpid feature to L1.
6993 */
6994 vmx_flush_tlb(vcpu);
6995 }
6996
6997
6998 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6999 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7000 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7001 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7002 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7003 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7004 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7005 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7006 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7007 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7008 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7009 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7010 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7011 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7012 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7013
7014 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7015 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7016 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7017 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7018 vmcs12->host_ia32_perf_global_ctrl);
7019}
7020
7021/*
7022 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7023 * and modify vmcs12 to make it see what it would expect to see there if
7024 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7025 */
7026static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7027{
7028 struct vcpu_vmx *vmx = to_vmx(vcpu);
7029 int cpu;
7030 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7031
7032 leave_guest_mode(vcpu);
7033 prepare_vmcs12(vcpu, vmcs12);
7034
7035 cpu = get_cpu();
7036 vmx->loaded_vmcs = &vmx->vmcs01;
7037 vmx_vcpu_put(vcpu);
7038 vmx_vcpu_load(vcpu, cpu);
7039 vcpu->cpu = cpu;
7040 put_cpu();
7041
7042 /* if no vmcs02 cache requested, remove the one we used */
7043 if (VMCS02_POOL_SIZE == 0)
7044 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7045
7046 load_vmcs12_host_state(vcpu, vmcs12);
7047
27fc51b2 7048 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7049 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7050
7051 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7052 vmx->host_rsp = 0;
7053
7054 /* Unpin physical memory we referred to in vmcs02 */
7055 if (vmx->nested.apic_access_page) {
7056 nested_release_page(vmx->nested.apic_access_page);
7057 vmx->nested.apic_access_page = 0;
7058 }
7059
7060 /*
7061 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7062 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7063 * success or failure flag accordingly.
7064 */
7065 if (unlikely(vmx->fail)) {
7066 vmx->fail = 0;
7067 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7068 } else
7069 nested_vmx_succeed(vcpu);
7070}
7071
7c177938
NHE		 7072/*
7073 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7074 * 23.7 "VM-entry failures during or after loading guest state" (this also
7075 * lists the acceptable exit-reason and exit-qualification parameters).
7076 * It should only be called before L2 actually succeeded to run, and when
7077 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7078 */
7079static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7080 struct vmcs12 *vmcs12,
7081 u32 reason, unsigned long qualification)
7082{
7083 load_vmcs12_host_state(vcpu, vmcs12);
7084 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7085 vmcs12->exit_qualification = qualification;
7086 nested_vmx_succeed(vcpu);
7087}
7088
8a76d7f2
JR		 7089static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7090 struct x86_instruction_info *info,
7091 enum x86_intercept_stage stage)
7092{
7093 return X86EMUL_CONTINUE;
7094}
7095
cbdd1bea 7096static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7097 .cpu_has_kvm_support = cpu_has_kvm_support,
7098 .disabled_by_bios = vmx_disabled_by_bios,
7099 .hardware_setup = hardware_setup,
7100 .hardware_unsetup = hardware_unsetup,
002c7f7c 7101 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7102 .hardware_enable = hardware_enable,
7103 .hardware_disable = hardware_disable,
04547156 7104 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7105
7106 .vcpu_create = vmx_create_vcpu,
7107 .vcpu_free = vmx_free_vcpu,
04d2cc77 7108 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7109
04d2cc77 7110 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7111 .vcpu_load = vmx_vcpu_load,
7112 .vcpu_put = vmx_vcpu_put,
7113
7114 .set_guest_debug = set_guest_debug,
7115 .get_msr = vmx_get_msr,
7116 .set_msr = vmx_set_msr,
7117 .get_segment_base = vmx_get_segment_base,
7118 .get_segment = vmx_get_segment,
7119 .set_segment = vmx_set_segment,
2e4d2653 7120 .get_cpl = vmx_get_cpl,
6aa8b732 7121 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7122 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7123 .decache_cr3 = vmx_decache_cr3,
25c4c276 7124 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7125 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7126 .set_cr3 = vmx_set_cr3,
7127 .set_cr4 = vmx_set_cr4,
6aa8b732 7128 .set_efer = vmx_set_efer,
6aa8b732
AK		 7129 .get_idt = vmx_get_idt,
7130 .set_idt = vmx_set_idt,
7131 .get_gdt = vmx_get_gdt,
7132 .set_gdt = vmx_set_gdt,
020df079 7133 .set_dr7 = vmx_set_dr7,
5fdbf976 7134 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7135 .get_rflags = vmx_get_rflags,
7136 .set_rflags = vmx_set_rflags,
ebcbab4c 7137 .fpu_activate = vmx_fpu_activate,
02daab21 7138 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7139
7140 .tlb_flush = vmx_flush_tlb,
6aa8b732 7141
6aa8b732 7142 .run = vmx_vcpu_run,
6062d012 7143 .handle_exit = vmx_handle_exit,
6aa8b732 7144 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7145 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7146 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7147 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7148 .set_irq = vmx_inject_irq,
95ba8273 7149 .set_nmi = vmx_inject_nmi,
298101da 7150 .queue_exception = vmx_queue_exception,
b463a6f7 7151 .cancel_injection = vmx_cancel_injection,
78646121 7152 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7153 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7154 .get_nmi_mask = vmx_get_nmi_mask,
7155 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7156 .enable_nmi_window = enable_nmi_window,
7157 .enable_irq_window = enable_irq_window,
7158 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7159
cbc94022 7160 .set_tss_addr = vmx_set_tss_addr,
67253af5 7161 .get_tdp_level = get_ept_level,
4b12f0de 7162 .get_mt_mask = vmx_get_mt_mask,
229456fc 7163
586f9607 7164 .get_exit_info = vmx_get_exit_info,
586f9607 7165
17cc3935 7166 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7167
7168 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7169
7170 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7171
7172 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7173
7174 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7175
4051b188 7176 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7177 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7178 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7179 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7180 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7181
7182 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7183
7184 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7185};
7186
7187static int __init vmx_init(void)
7188{
26bb0981
AK		 7189 int r, i;
7190
7191 rdmsrl_safe(MSR_EFER, &host_efer);
7192
7193 for (i = 0; i < NR_VMX_MSR; ++i)
7194 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7195
3e7c73e9 7196 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7197 if (!vmx_io_bitmap_a)
7198 return -ENOMEM;
7199
3e7c73e9 7200 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7201 if (!vmx_io_bitmap_b) {
7202 r = -ENOMEM;
7203 goto out;
7204 }
7205
5897297b
AK		 7206 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7207 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7208 r = -ENOMEM;
7209 goto out1;
7210 }
7211
5897297b
AK		 7212 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7213 if (!vmx_msr_bitmap_longmode) {
7214 r = -ENOMEM;
7215 goto out2;
7216 }
7217
fdef3ad1
HQ		 7218 /*
7219 * Allow direct access to the PC debug port (it is often used for I/O
7220 * delays, but the vmexits simply slow things down).
7221 */
3e7c73e9
AK		 7222 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7223 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7224
3e7c73e9 7225 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7226
5897297b
AK		 7227 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7228 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7229
2384d2b3
SY		 7230 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7231
0ee75bea
AK		 7232 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7233 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7234 if (r)
5897297b 7235 goto out3;
25c5f225 7236
5897297b
AK		 7237 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7238 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7239 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7240 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7241 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7242 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7243
089d034e 7244 if (enable_ept) {
534e38b4 7245 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7246 VMX_EPT_EXECUTABLE_MASK);
ce88decf 7247 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7248 kvm_enable_tdp();
7249 } else
7250 kvm_disable_tdp();
1439442c 7251
fdef3ad1
HQ		 7252 return 0;
7253
5897297b
AK		 7254out3:
7255 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7256out2:
5897297b 7257 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7258out1:
3e7c73e9 7259 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7260out:
3e7c73e9 7261 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7262 return r;
6aa8b732
AK		 7263}
7264
7265static void __exit vmx_exit(void)
7266{
5897297b
AK		 7267 free_page((unsigned long)vmx_msr_bitmap_legacy);
7268 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7269 free_page((unsigned long)vmx_io_bitmap_b);
7270 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7271
cb498ea2 7272 kvm_exit();
6aa8b732
AK		 7273}
7274
7275module_init(vmx_init)
7276module_exit(vmx_exit)
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