]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: add support for switching of PERF_GLOBAL_CTRL
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly enable_vpid = 1;
736caefe 53module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 54
4462d21a 55static int __read_mostly flexpriority_enabled = 1;
736caefe 56module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 57
4462d21a 58static int __read_mostly enable_ept = 1;
736caefe 59module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 60
3a624e29
NK		 61static int __read_mostly enable_unrestricted_guest = 1;
62module_param_named(unrestricted_guest,
63 enable_unrestricted_guest, bool, S_IRUGO);
64
4462d21a 65static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 66module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 67
b923e62e
DX		 68static int __read_mostly vmm_exclusive = 1;
69module_param(vmm_exclusive, bool, S_IRUGO);
70
443381a8
AL		 71static int __read_mostly yield_on_hlt = 1;
72module_param(yield_on_hlt, bool, S_IRUGO);
73
58fbbf26
KT		 74static int __read_mostly fasteoi = 1;
75module_param(fasteoi, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
8bf00a52 121#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
fe3ef05c 348 u64 vmcs01_tsc_offset;
644d711a
NHE		 349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
fe3ef05c
NHE		 351 /*
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
354 */
355 struct page *apic_access_page;
ec378aee
NHE		 356};
357
a2fa3e9f 358struct vcpu_vmx {
fb3f0f51 359 struct kvm_vcpu vcpu;
313dbd49 360 unsigned long host_rsp;
29bd8a78 361 u8 fail;
69c73028 362 u8 cpl;
9d58b931 363 bool nmi_known_unmasked;
51aa01d1 364 u32 exit_intr_info;
1155f76a 365 u32 idt_vectoring_info;
6de12732 366 ulong rflags;
26bb0981 367 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 368 int nmsrs;
369 int save_nmsrs;
a2fa3e9f 370#ifdef CONFIG_X86_64
44ea2b17
AK		 371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
a2fa3e9f 373#endif
d462b819
NHE		 374 /*
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
378 */
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 382 struct msr_autoload {
383 unsigned nr;
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386 } msr_autoload;
a2fa3e9f
GH		 387 struct {
388 int loaded;
389 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
d77c26fc 392 } host_state;
9c8cba37 393 struct {
7ffd92c5 394 int vm86_active;
78ac8b47 395 ulong save_rflags;
7ffd92c5
AK		 396 struct kvm_save_segment {
397 u16 selector;
398 unsigned long base;
399 u32 limit;
400 u32 ar;
401 } tr, es, ds, fs, gs;
9c8cba37 402 } rmode;
2fb92db1
AK		 403 struct {
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
406 } segment_cache;
2384d2b3 407 int vpid;
04fa4d32 408 bool emulation_required;
3b86cd99
JK		 409
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
412 ktime_t entry_time;
413 s64 vnmi_blocked_time;
a0861c02 414 u32 exit_reason;
4e47c7a6
SY		 415
416 bool rdtscp_enabled;
ec378aee
NHE		 417
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
a2fa3e9f
GH		 420};
421
2fb92db1
AK		 422enum segment_cache_field {
423 SEG_FIELD_SEL = 0,
424 SEG_FIELD_BASE = 1,
425 SEG_FIELD_LIMIT = 2,
426 SEG_FIELD_AR = 3,
427
428 SEG_FIELD_NR = 4
429};
430
a2fa3e9f
GH		 431static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432{
fb3f0f51 433 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 434}
435
22bd0358
NHE		 436#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
569};
570static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572static inline short vmcs_field_to_offset(unsigned long field)
573{
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return -1;
576 return vmcs_field_to_offset_table[field];
577}
578
a9d30f33
NHE		 579static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580{
581 return to_vmx(vcpu)->nested.current_vmcs12;
582}
583
584static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585{
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
589 return NULL;
590 }
591 return page;
592}
593
594static void nested_release_page(struct page *page)
595{
596 kvm_release_page_dirty(page);
597}
598
599static void nested_release_page_clean(struct page *page)
600{
601 kvm_release_page_clean(page);
602}
603
4e1096d2 604static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 605static void kvm_cpu_vmxon(u64 addr);
606static void kvm_cpu_vmxoff(void);
aff48baa 607static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 609
6aa8b732
AK		 610static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 612/*
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 */
616static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 617static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 618
3e7c73e9
AK		 619static unsigned long *vmx_io_bitmap_a;
620static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 621static unsigned long *vmx_msr_bitmap_legacy;
622static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 623
110312c8 624static bool cpu_has_load_ia32_efer;
8bf00a52 625static bool cpu_has_load_perf_global_ctrl;
110312c8 626
2384d2b3
SY		 627static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
628static DEFINE_SPINLOCK(vmx_vpid_lock);
629
1c3d14fe 630static struct vmcs_config {
6aa8b732
AK		 631 int size;
632 int order;
633 u32 revision_id;
1c3d14fe
YS		 634 u32 pin_based_exec_ctrl;
635 u32 cpu_based_exec_ctrl;
f78e0e2e 636 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 637 u32 vmexit_ctrl;
638 u32 vmentry_ctrl;
639} vmcs_config;
6aa8b732 640
efff9e53 641static struct vmx_capability {
d56f546d
SY		 642 u32 ept;
643 u32 vpid;
644} vmx_capability;
645
6aa8b732
AK		 646#define VMX_SEGMENT_FIELD(seg) \
647 [VCPU_SREG_##seg] = { \
648 .selector = GUEST_##seg##_SELECTOR, \
649 .base = GUEST_##seg##_BASE, \
650 .limit = GUEST_##seg##_LIMIT, \
651 .ar_bytes = GUEST_##seg##_AR_BYTES, \
652 }
653
654static struct kvm_vmx_segment_field {
655 unsigned selector;
656 unsigned base;
657 unsigned limit;
658 unsigned ar_bytes;
659} kvm_vmx_segment_fields[] = {
660 VMX_SEGMENT_FIELD(CS),
661 VMX_SEGMENT_FIELD(DS),
662 VMX_SEGMENT_FIELD(ES),
663 VMX_SEGMENT_FIELD(FS),
664 VMX_SEGMENT_FIELD(GS),
665 VMX_SEGMENT_FIELD(SS),
666 VMX_SEGMENT_FIELD(TR),
667 VMX_SEGMENT_FIELD(LDTR),
668};
669
26bb0981
AK		 670static u64 host_efer;
671
6de4f3ad
AK		 672static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
673
4d56c8a7 674/*
8c06585d 675 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 676 * away by decrementing the array size.
677 */
6aa8b732 678static const u32 vmx_msr_index[] = {
05b3e0c2 679#ifdef CONFIG_X86_64
44ea2b17 680 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 681#endif
8c06585d 682 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 683};
9d8f549d 684#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 685
31299944 686static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 687{
688 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
689 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 690 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 691}
692
31299944 693static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 694{
695 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
696 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 697 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 698}
699
31299944 700static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 701{
702 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
703 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 704 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 705}
706
31299944 707static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 708{
709 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
710 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
711}
712
31299944 713static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 714{
715 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
716 INTR_INFO_VALID_MASK)) ==
717 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
718}
719
31299944 720static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 721{
04547156 722 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 723}
724
31299944 725static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 726{
04547156 727 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 728}
729
31299944 730static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 731{
04547156 732 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 733}
734
31299944 735static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 736{
04547156
SY		 737 return vmcs_config.cpu_based_exec_ctrl &
738 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 739}
740
774ead3a 741static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 742{
04547156
SY		 743 return vmcs_config.cpu_based_2nd_exec_ctrl &
744 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
745}
746
747static inline bool cpu_has_vmx_flexpriority(void)
748{
749 return cpu_has_vmx_tpr_shadow() &&
750 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 751}
752
e799794e
MT		 753static inline bool cpu_has_vmx_ept_execute_only(void)
754{
31299944 755 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 756}
757
758static inline bool cpu_has_vmx_eptp_uncacheable(void)
759{
31299944 760 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 761}
762
763static inline bool cpu_has_vmx_eptp_writeback(void)
764{
31299944 765 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 766}
767
768static inline bool cpu_has_vmx_ept_2m_page(void)
769{
31299944 770 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 771}
772
878403b7
SY		 773static inline bool cpu_has_vmx_ept_1g_page(void)
774{
31299944 775 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 776}
777
4bc9b982
SY		 778static inline bool cpu_has_vmx_ept_4levels(void)
779{
780 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
781}
782
31299944 783static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 784{
31299944 785 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 786}
787
31299944 788static inline bool cpu_has_vmx_invept_context(void)
d56f546d 789{
31299944 790 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 791}
792
31299944 793static inline bool cpu_has_vmx_invept_global(void)
d56f546d 794{
31299944 795 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 796}
797
518c8aee
GJ		 798static inline bool cpu_has_vmx_invvpid_single(void)
799{
800 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
801}
802
b9d762fa
GJ		 803static inline bool cpu_has_vmx_invvpid_global(void)
804{
805 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
806}
807
31299944 808static inline bool cpu_has_vmx_ept(void)
d56f546d 809{
04547156
SY		 810 return vmcs_config.cpu_based_2nd_exec_ctrl &
811 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 812}
813
31299944 814static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 815{
816 return vmcs_config.cpu_based_2nd_exec_ctrl &
817 SECONDARY_EXEC_UNRESTRICTED_GUEST;
818}
819
31299944 820static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 821{
822 return vmcs_config.cpu_based_2nd_exec_ctrl &
823 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
824}
825
31299944 826static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 827{
6d3e435e 828 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 829}
830
31299944 831static inline bool cpu_has_vmx_vpid(void)
2384d2b3 832{
04547156
SY		 833 return vmcs_config.cpu_based_2nd_exec_ctrl &
834 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 835}
836
31299944 837static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 838{
839 return vmcs_config.cpu_based_2nd_exec_ctrl &
840 SECONDARY_EXEC_RDTSCP;
841}
842
31299944 843static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 844{
845 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
846}
847
f5f48ee1
SY		 848static inline bool cpu_has_vmx_wbinvd_exit(void)
849{
850 return vmcs_config.cpu_based_2nd_exec_ctrl &
851 SECONDARY_EXEC_WBINVD_EXITING;
852}
853
04547156
SY		 854static inline bool report_flexpriority(void)
855{
856 return flexpriority_enabled;
857}
858
fe3ef05c
NHE		 859static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
860{
861 return vmcs12->cpu_based_vm_exec_control & bit;
862}
863
864static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
865{
866 return (vmcs12->cpu_based_vm_exec_control &
867 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
868 (vmcs12->secondary_vm_exec_control & bit);
869}
870
644d711a
NHE		 871static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
872 struct kvm_vcpu *vcpu)
873{
874 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
875}
876
877static inline bool is_exception(u32 intr_info)
878{
879 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
880 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
881}
882
883static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 884static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
885 struct vmcs12 *vmcs12,
886 u32 reason, unsigned long qualification);
887
8b9cf98c 888static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 889{
890 int i;
891
a2fa3e9f 892 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 893 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 894 return i;
895 return -1;
896}
897
2384d2b3
SY		 898static inline void __invvpid(int ext, u16 vpid, gva_t gva)
899{
900 struct {
901 u64 vpid : 16;
902 u64 rsvd : 48;
903 u64 gva;
904 } operand = { vpid, 0, gva };
905
4ecac3fd 906 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 907 /* CF==1 or ZF==1 --> rc = -1 */
908 "; ja 1f ; ud2 ; 1:"
909 : : "a"(&operand), "c"(ext) : "cc", "memory");
910}
911
1439442c
SY		 912static inline void __invept(int ext, u64 eptp, gpa_t gpa)
913{
914 struct {
915 u64 eptp, gpa;
916 } operand = {eptp, gpa};
917
4ecac3fd 918 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 919 /* CF==1 or ZF==1 --> rc = -1 */
920 "; ja 1f ; ud2 ; 1:\n"
921 : : "a" (&operand), "c" (ext) : "cc", "memory");
922}
923
26bb0981 924static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 925{
926 int i;
927
8b9cf98c 928 i = __find_msr_index(vmx, msr);
a75beee6 929 if (i >= 0)
a2fa3e9f 930 return &vmx->guest_msrs[i];
8b6d44c7 931 return NULL;
7725f0ba
AK		 932}
933
6aa8b732
AK		 934static void vmcs_clear(struct vmcs *vmcs)
935{
936 u64 phys_addr = __pa(vmcs);
937 u8 error;
938
4ecac3fd 939 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 940 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 941 : "cc", "memory");
942 if (error)
943 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
944 vmcs, phys_addr);
945}
946
d462b819
NHE		 947static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
948{
949 vmcs_clear(loaded_vmcs->vmcs);
950 loaded_vmcs->cpu = -1;
951 loaded_vmcs->launched = 0;
952}
953
7725b894
DX		 954static void vmcs_load(struct vmcs *vmcs)
955{
956 u64 phys_addr = __pa(vmcs);
957 u8 error;
958
959 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 960 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 961 : "cc", "memory");
962 if (error)
2844d849 963 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 964 vmcs, phys_addr);
965}
966
d462b819 967static void __loaded_vmcs_clear(void *arg)
6aa8b732 968{
d462b819 969 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 970 int cpu = raw_smp_processor_id();
6aa8b732 971
d462b819
NHE		 972 if (loaded_vmcs->cpu != cpu)
973 return; /* vcpu migration can race with cpu offline */
974 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 975 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 976 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
977 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 978}
979
d462b819 980static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 981{
d462b819
NHE		 982 if (loaded_vmcs->cpu != -1)
983 smp_call_function_single(
984 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 985}
986
1760dd49 987static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 988{
989 if (vmx->vpid == 0)
990 return;
991
518c8aee
GJ		 992 if (cpu_has_vmx_invvpid_single())
993 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 994}
995
b9d762fa
GJ		 996static inline void vpid_sync_vcpu_global(void)
997{
998 if (cpu_has_vmx_invvpid_global())
999 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1000}
1001
1002static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1003{
1004 if (cpu_has_vmx_invvpid_single())
1760dd49 1005 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1006 else
1007 vpid_sync_vcpu_global();
1008}
1009
1439442c
SY		 1010static inline void ept_sync_global(void)
1011{
1012 if (cpu_has_vmx_invept_global())
1013 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1014}
1015
1016static inline void ept_sync_context(u64 eptp)
1017{
089d034e 1018 if (enable_ept) {
1439442c
SY		 1019 if (cpu_has_vmx_invept_context())
1020 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1021 else
1022 ept_sync_global();
1023 }
1024}
1025
1026static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1027{
089d034e 1028 if (enable_ept) {
1439442c
SY		 1029 if (cpu_has_vmx_invept_individual_addr())
1030 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1031 eptp, gpa);
1032 else
1033 ept_sync_context(eptp);
1034 }
1035}
1036
96304217 1037static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1038{
5e520e62 1039 unsigned long value;
6aa8b732 1040
5e520e62
AK		 1041 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1042 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1043 return value;
1044}
1045
96304217 1046static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1047{
1048 return vmcs_readl(field);
1049}
1050
96304217 1051static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1052{
1053 return vmcs_readl(field);
1054}
1055
96304217 1056static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1057{
05b3e0c2 1058#ifdef CONFIG_X86_64
6aa8b732
AK		 1059 return vmcs_readl(field);
1060#else
1061 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1062#endif
1063}
1064
e52de1b8
AK		 1065static noinline void vmwrite_error(unsigned long field, unsigned long value)
1066{
1067 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1068 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1069 dump_stack();
1070}
1071
6aa8b732
AK		 1072static void vmcs_writel(unsigned long field, unsigned long value)
1073{
1074 u8 error;
1075
4ecac3fd 1076 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1077 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1078 if (unlikely(error))
1079 vmwrite_error(field, value);
6aa8b732
AK		 1080}
1081
1082static void vmcs_write16(unsigned long field, u16 value)
1083{
1084 vmcs_writel(field, value);
1085}
1086
1087static void vmcs_write32(unsigned long field, u32 value)
1088{
1089 vmcs_writel(field, value);
1090}
1091
1092static void vmcs_write64(unsigned long field, u64 value)
1093{
6aa8b732 1094 vmcs_writel(field, value);
7682f2d0 1095#ifndef CONFIG_X86_64
6aa8b732
AK		 1096 asm volatile ("");
1097 vmcs_writel(field+1, value >> 32);
1098#endif
1099}
1100
2ab455cc
AL		 1101static void vmcs_clear_bits(unsigned long field, u32 mask)
1102{
1103 vmcs_writel(field, vmcs_readl(field) & ~mask);
1104}
1105
1106static void vmcs_set_bits(unsigned long field, u32 mask)
1107{
1108 vmcs_writel(field, vmcs_readl(field) | mask);
1109}
1110
2fb92db1
AK		 1111static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1112{
1113 vmx->segment_cache.bitmask = 0;
1114}
1115
1116static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1117 unsigned field)
1118{
1119 bool ret;
1120 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1121
1122 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1123 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1124 vmx->segment_cache.bitmask = 0;
1125 }
1126 ret = vmx->segment_cache.bitmask & mask;
1127 vmx->segment_cache.bitmask |= mask;
1128 return ret;
1129}
1130
1131static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1132{
1133 u16 *p = &vmx->segment_cache.seg[seg].selector;
1134
1135 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1136 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1137 return *p;
1138}
1139
1140static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1141{
1142 ulong *p = &vmx->segment_cache.seg[seg].base;
1143
1144 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1145 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1146 return *p;
1147}
1148
1149static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1150{
1151 u32 *p = &vmx->segment_cache.seg[seg].limit;
1152
1153 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1154 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1155 return *p;
1156}
1157
1158static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1159{
1160 u32 *p = &vmx->segment_cache.seg[seg].ar;
1161
1162 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1163 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1164 return *p;
1165}
1166
abd3f2d6
AK		 1167static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1168{
1169 u32 eb;
1170
fd7373cc
JK		 1171 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1172 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1173 if ((vcpu->guest_debug &
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1175 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1176 eb |= 1u << BP_VECTOR;
7ffd92c5 1177 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1178 eb = ~0;
089d034e 1179 if (enable_ept)
1439442c 1180 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1181 if (vcpu->fpu_active)
1182 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1183
1184 /* When we are running a nested L2 guest and L1 specified for it a
1185 * certain exception bitmap, we must trap the same exceptions and pass
1186 * them to L1. When running L2, we will only handle the exceptions
1187 * specified above if L1 did not want them.
1188 */
1189 if (is_guest_mode(vcpu))
1190 eb |= get_vmcs12(vcpu)->exception_bitmap;
1191
abd3f2d6
AK		 1192 vmcs_write32(EXCEPTION_BITMAP, eb);
1193}
1194
8bf00a52
GN		 1195static void clear_atomic_switch_msr_special(unsigned long entry,
1196 unsigned long exit)
1197{
1198 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1199 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1200}
1201
61d2ef2c
AK		 1202static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1203{
1204 unsigned i;
1205 struct msr_autoload *m = &vmx->msr_autoload;
1206
8bf00a52
GN		 1207 switch (msr) {
1208 case MSR_EFER:
1209 if (cpu_has_load_ia32_efer) {
1210 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1211 VM_EXIT_LOAD_IA32_EFER);
1212 return;
1213 }
1214 break;
1215 case MSR_CORE_PERF_GLOBAL_CTRL:
1216 if (cpu_has_load_perf_global_ctrl) {
1217 clear_atomic_switch_msr_special(
1218 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1219 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1220 return;
1221 }
1222 break;
110312c8
AK		 1223 }
1224
61d2ef2c
AK		 1225 for (i = 0; i < m->nr; ++i)
1226 if (m->guest[i].index == msr)
1227 break;
1228
1229 if (i == m->nr)
1230 return;
1231 --m->nr;
1232 m->guest[i] = m->guest[m->nr];
1233 m->host[i] = m->host[m->nr];
1234 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1235 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1236}
1237
8bf00a52
GN		 1238static void add_atomic_switch_msr_special(unsigned long entry,
1239 unsigned long exit, unsigned long guest_val_vmcs,
1240 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1241{
1242 vmcs_write64(guest_val_vmcs, guest_val);
1243 vmcs_write64(host_val_vmcs, host_val);
1244 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1245 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1246}
1247
61d2ef2c
AK		 1248static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1249 u64 guest_val, u64 host_val)
1250{
1251 unsigned i;
1252 struct msr_autoload *m = &vmx->msr_autoload;
1253
8bf00a52
GN		 1254 switch (msr) {
1255 case MSR_EFER:
1256 if (cpu_has_load_ia32_efer) {
1257 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1258 VM_EXIT_LOAD_IA32_EFER,
1259 GUEST_IA32_EFER,
1260 HOST_IA32_EFER,
1261 guest_val, host_val);
1262 return;
1263 }
1264 break;
1265 case MSR_CORE_PERF_GLOBAL_CTRL:
1266 if (cpu_has_load_perf_global_ctrl) {
1267 add_atomic_switch_msr_special(
1268 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1269 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1270 GUEST_IA32_PERF_GLOBAL_CTRL,
1271 HOST_IA32_PERF_GLOBAL_CTRL,
1272 guest_val, host_val);
1273 return;
1274 }
1275 break;
110312c8
AK		 1276 }
1277
61d2ef2c
AK		 1278 for (i = 0; i < m->nr; ++i)
1279 if (m->guest[i].index == msr)
1280 break;
1281
1282 if (i == m->nr) {
1283 ++m->nr;
1284 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1285 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1286 }
1287
1288 m->guest[i].index = msr;
1289 m->guest[i].value = guest_val;
1290 m->host[i].index = msr;
1291 m->host[i].value = host_val;
1292}
1293
33ed6329
AK		 1294static void reload_tss(void)
1295{
33ed6329
AK		 1296 /*
1297 * VT restores TR but not its size. Useless.
1298 */
d359192f 1299 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1300 struct desc_struct *descs;
33ed6329 1301
d359192f 1302 descs = (void *)gdt->address;
33ed6329
AK		 1303 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1304 load_TR_desc();
33ed6329
AK		 1305}
1306
92c0d900 1307static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1308{
3a34a881 1309 u64 guest_efer;
51c6cf66
AK		 1310 u64 ignore_bits;
1311
f6801dff 1312 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1313
51c6cf66
AK		 1314 /*
1315 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1316 * outside long mode
1317 */
1318 ignore_bits = EFER_NX | EFER_SCE;
1319#ifdef CONFIG_X86_64
1320 ignore_bits |= EFER_LMA | EFER_LME;
1321 /* SCE is meaningful only in long mode on Intel */
1322 if (guest_efer & EFER_LMA)
1323 ignore_bits &= ~(u64)EFER_SCE;
1324#endif
51c6cf66
AK		 1325 guest_efer &= ~ignore_bits;
1326 guest_efer |= host_efer & ignore_bits;
26bb0981 1327 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1328 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1329
1330 clear_atomic_switch_msr(vmx, MSR_EFER);
1331 /* On ept, can't emulate nx, and must switch nx atomically */
1332 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1333 guest_efer = vmx->vcpu.arch.efer;
1334 if (!(guest_efer & EFER_LMA))
1335 guest_efer &= ~EFER_LME;
1336 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1337 return false;
1338 }
1339
26bb0981 1340 return true;
51c6cf66
AK		 1341}
1342
2d49ec72
GN		 1343static unsigned long segment_base(u16 selector)
1344{
d359192f 1345 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1346 struct desc_struct *d;
1347 unsigned long table_base;
1348 unsigned long v;
1349
1350 if (!(selector & ~3))
1351 return 0;
1352
d359192f 1353 table_base = gdt->address;
2d49ec72
GN		 1354
1355 if (selector & 4) { /* from ldt */
1356 u16 ldt_selector = kvm_read_ldt();
1357
1358 if (!(ldt_selector & ~3))
1359 return 0;
1360
1361 table_base = segment_base(ldt_selector);
1362 }
1363 d = (struct desc_struct *)(table_base + (selector & ~7));
1364 v = get_desc_base(d);
1365#ifdef CONFIG_X86_64
1366 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1367 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1368#endif
1369 return v;
1370}
1371
1372static inline unsigned long kvm_read_tr_base(void)
1373{
1374 u16 tr;
1375 asm("str %0" : "=g"(tr));
1376 return segment_base(tr);
1377}
1378
04d2cc77 1379static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1380{
04d2cc77 1381 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1382 int i;
04d2cc77 1383
a2fa3e9f 1384 if (vmx->host_state.loaded)
33ed6329
AK		 1385 return;
1386
a2fa3e9f 1387 vmx->host_state.loaded = 1;
33ed6329
AK		 1388 /*
1389 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1390 * allow segment selectors with cpl > 0 or ti == 1.
1391 */
d6e88aec 1392 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1393 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1394 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1395 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1396 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1397 vmx->host_state.fs_reload_needed = 0;
1398 } else {
33ed6329 1399 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1400 vmx->host_state.fs_reload_needed = 1;
33ed6329 1401 }
9581d442 1402 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1403 if (!(vmx->host_state.gs_sel & 7))
1404 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1405 else {
1406 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1407 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1408 }
1409
1410#ifdef CONFIG_X86_64
1411 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1412 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1413#else
a2fa3e9f
GH		 1414 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1415 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1416#endif
707c0874
AK		 1417
1418#ifdef CONFIG_X86_64
c8770e7b
AK		 1419 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1420 if (is_long_mode(&vmx->vcpu))
44ea2b17 1421 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1422#endif
26bb0981
AK		 1423 for (i = 0; i < vmx->save_nmsrs; ++i)
1424 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1425 vmx->guest_msrs[i].data,
1426 vmx->guest_msrs[i].mask);
33ed6329
AK		 1427}
1428
a9b21b62 1429static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1430{
a2fa3e9f 1431 if (!vmx->host_state.loaded)
33ed6329
AK		 1432 return;
1433
e1beb1d3 1434 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1435 vmx->host_state.loaded = 0;
c8770e7b
AK		 1436#ifdef CONFIG_X86_64
1437 if (is_long_mode(&vmx->vcpu))
1438 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1439#endif
152d3f2f 1440 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1441 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1442#ifdef CONFIG_X86_64
9581d442 1443 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1444#else
1445 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1446#endif
33ed6329 1447 }
0a77fe4c
AK		 1448 if (vmx->host_state.fs_reload_needed)
1449 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1450 reload_tss();
44ea2b17 1451#ifdef CONFIG_X86_64
c8770e7b 1452 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1453#endif
1c11e713
AK		 1454 if (current_thread_info()->status & TS_USEDFPU)
1455 clts();
3444d7da 1456 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1457}
1458
a9b21b62
AK		 1459static void vmx_load_host_state(struct vcpu_vmx *vmx)
1460{
1461 preempt_disable();
1462 __vmx_load_host_state(vmx);
1463 preempt_enable();
1464}
1465
6aa8b732
AK		 1466/*
1467 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1468 * vcpu mutex is already taken.
1469 */
15ad7146 1470static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1471{
a2fa3e9f 1472 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1473 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1474
4610c9cc
DX		 1475 if (!vmm_exclusive)
1476 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1477 else if (vmx->loaded_vmcs->cpu != cpu)
1478 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1479
d462b819
NHE		 1480 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1481 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1482 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1483 }
1484
d462b819 1485 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1486 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1487 unsigned long sysenter_esp;
1488
a8eeb04a 1489 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1490 local_irq_disable();
d462b819
NHE		 1491 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1492 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1493 local_irq_enable();
1494
6aa8b732
AK		 1495 /*
1496 * Linux uses per-cpu TSS and GDT, so set these when switching
1497 * processors.
1498 */
d6e88aec 1499 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1500 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1501
1502 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1503 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1504 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1505 }
6aa8b732
AK		 1506}
1507
1508static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1509{
a9b21b62 1510 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1511 if (!vmm_exclusive) {
d462b819
NHE		 1512 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1513 vcpu->cpu = -1;
4610c9cc
DX		 1514 kvm_cpu_vmxoff();
1515 }
6aa8b732
AK		 1516}
1517
5fd86fcf
AK		 1518static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1519{
81231c69
AK		 1520 ulong cr0;
1521
5fd86fcf
AK		 1522 if (vcpu->fpu_active)
1523 return;
1524 vcpu->fpu_active = 1;
81231c69
AK		 1525 cr0 = vmcs_readl(GUEST_CR0);
1526 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1527 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1528 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1529 update_exception_bitmap(vcpu);
edcafe3c 1530 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1531 if (is_guest_mode(vcpu))
1532 vcpu->arch.cr0_guest_owned_bits &=
1533 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1534 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1535}
1536
edcafe3c
AK		 1537static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1538
fe3ef05c
NHE		 1539/*
1540 * Return the cr0 value that a nested guest would read. This is a combination
1541 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1542 * its hypervisor (cr0_read_shadow).
1543 */
1544static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1545{
1546 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1547 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1548}
1549static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1550{
1551 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1552 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1553}
1554
5fd86fcf
AK		 1555static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1556{
36cf24e0
NHE		 1557 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1558 * set this *before* calling this function.
1559 */
edcafe3c 1560 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1561 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1562 update_exception_bitmap(vcpu);
edcafe3c
AK		 1563 vcpu->arch.cr0_guest_owned_bits = 0;
1564 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1565 if (is_guest_mode(vcpu)) {
1566 /*
1567 * L1's specified read shadow might not contain the TS bit,
1568 * so now that we turned on shadowing of this bit, we need to
1569 * set this bit of the shadow. Like in nested_vmx_run we need
1570 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1571 * up-to-date here because we just decached cr0.TS (and we'll
1572 * only update vmcs12->guest_cr0 on nested exit).
1573 */
1574 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1575 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1576 (vcpu->arch.cr0 & X86_CR0_TS);
1577 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1578 } else
1579 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1580}
1581
6aa8b732
AK		 1582static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1583{
78ac8b47 1584 unsigned long rflags, save_rflags;
345dcaa8 1585
6de12732
AK		 1586 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1587 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1588 rflags = vmcs_readl(GUEST_RFLAGS);
1589 if (to_vmx(vcpu)->rmode.vm86_active) {
1590 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1591 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1592 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1593 }
1594 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1595 }
6de12732 1596 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1597}
1598
1599static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1600{
6de12732 1601 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1602 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1603 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1604 if (to_vmx(vcpu)->rmode.vm86_active) {
1605 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1606 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1607 }
6aa8b732
AK		 1608 vmcs_writel(GUEST_RFLAGS, rflags);
1609}
1610
2809f5d2
GC		 1611static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1612{
1613 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1614 int ret = 0;
1615
1616 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1617 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1618 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1619 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1620
1621 return ret & mask;
1622}
1623
1624static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1625{
1626 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1627 u32 interruptibility = interruptibility_old;
1628
1629 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1630
48005f64 1631 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1632 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1633 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1634 interruptibility |= GUEST_INTR_STATE_STI;
1635
1636 if ((interruptibility != interruptibility_old))
1637 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1638}
1639
6aa8b732
AK		 1640static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1641{
1642 unsigned long rip;
6aa8b732 1643
5fdbf976 1644 rip = kvm_rip_read(vcpu);
6aa8b732 1645 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1646 kvm_rip_write(vcpu, rip);
6aa8b732 1647
2809f5d2
GC		 1648 /* skipping an emulated instruction also counts */
1649 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1650}
1651
443381a8
AL		 1652static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1653{
1654 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1655 * explicitly skip the instruction because if the HLT state is set, then
1656 * the instruction is already executing and RIP has already been
1657 * advanced. */
1658 if (!yield_on_hlt &&
1659 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1660 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1661}
1662
0b6ac343
NHE		 1663/*
1664 * KVM wants to inject page-faults which it got to the guest. This function
1665 * checks whether in a nested guest, we need to inject them to L1 or L2.
1666 * This function assumes it is called with the exit reason in vmcs02 being
1667 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1668 * is running).
1669 */
1670static int nested_pf_handled(struct kvm_vcpu *vcpu)
1671{
1672 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1673
1674 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1675 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1676 return 0;
1677
1678 nested_vmx_vmexit(vcpu);
1679 return 1;
1680}
1681
298101da 1682static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1683 bool has_error_code, u32 error_code,
1684 bool reinject)
298101da 1685{
77ab6db0 1686 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1687 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1688
0b6ac343
NHE		 1689 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1690 nested_pf_handled(vcpu))
1691 return;
1692
8ab2d2e2 1693 if (has_error_code) {
77ab6db0 1694 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1695 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1696 }
77ab6db0 1697
7ffd92c5 1698 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1699 int inc_eip = 0;
1700 if (kvm_exception_is_soft(nr))
1701 inc_eip = vcpu->arch.event_exit_inst_len;
1702 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1703 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1704 return;
1705 }
1706
66fd3f7f
GN		 1707 if (kvm_exception_is_soft(nr)) {
1708 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1709 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1710 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1711 } else
1712 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1713
1714 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1715 vmx_clear_hlt(vcpu);
298101da
AK		 1716}
1717
4e47c7a6
SY		 1718static bool vmx_rdtscp_supported(void)
1719{
1720 return cpu_has_vmx_rdtscp();
1721}
1722
a75beee6
ED		 1723/*
1724 * Swap MSR entry in host/guest MSR entry array.
1725 */
8b9cf98c 1726static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1727{
26bb0981 1728 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1729
1730 tmp = vmx->guest_msrs[to];
1731 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1732 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1733}
1734
e38aea3e
AK		 1735/*
1736 * Set up the vmcs to automatically save and restore system
1737 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1738 * mode, as fiddling with msrs is very expensive.
1739 */
8b9cf98c 1740static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1741{
26bb0981 1742 int save_nmsrs, index;
5897297b 1743 unsigned long *msr_bitmap;
e38aea3e 1744
33f9c505 1745 vmx_load_host_state(vmx);
a75beee6
ED		 1746 save_nmsrs = 0;
1747#ifdef CONFIG_X86_64
8b9cf98c 1748 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1749 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1750 if (index >= 0)
8b9cf98c
RR		 1751 move_msr_up(vmx, index, save_nmsrs++);
1752 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1753 if (index >= 0)
8b9cf98c
RR		 1754 move_msr_up(vmx, index, save_nmsrs++);
1755 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1756 if (index >= 0)
8b9cf98c 1757 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1758 index = __find_msr_index(vmx, MSR_TSC_AUX);
1759 if (index >= 0 && vmx->rdtscp_enabled)
1760 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1761 /*
8c06585d 1762 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1763 * if efer.sce is enabled.
1764 */
8c06585d 1765 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1766 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1767 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1768 }
1769#endif
92c0d900
AK		 1770 index = __find_msr_index(vmx, MSR_EFER);
1771 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1772 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1773
26bb0981 1774 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1775
1776 if (cpu_has_vmx_msr_bitmap()) {
1777 if (is_long_mode(&vmx->vcpu))
1778 msr_bitmap = vmx_msr_bitmap_longmode;
1779 else
1780 msr_bitmap = vmx_msr_bitmap_legacy;
1781
1782 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1783 }
e38aea3e
AK		 1784}
1785
6aa8b732
AK		 1786/*
1787 * reads and returns guest's timestamp counter "register"
1788 * guest_tsc = host_tsc + tsc_offset -- 21.3
1789 */
1790static u64 guest_read_tsc(void)
1791{
1792 u64 host_tsc, tsc_offset;
1793
1794 rdtscll(host_tsc);
1795 tsc_offset = vmcs_read64(TSC_OFFSET);
1796 return host_tsc + tsc_offset;
1797}
1798
d5c1785d
NHE		 1799/*
1800 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1801 * counter, even if a nested guest (L2) is currently running.
1802 */
1803u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1804{
1805 u64 host_tsc, tsc_offset;
1806
1807 rdtscll(host_tsc);
1808 tsc_offset = is_guest_mode(vcpu) ?
1809 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1810 vmcs_read64(TSC_OFFSET);
1811 return host_tsc + tsc_offset;
1812}
1813
4051b188
JR		 1814/*
1815 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1816 * ioctl. In this case the call-back should update internal vmx state to make
1817 * the changes effective.
1818 */
1819static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1820{
1821 /* Nothing to do here */
1822}
1823
6aa8b732 1824/*
99e3e30a 1825 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1826 */
99e3e30a 1827static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1828{
27fc51b2 1829 if (is_guest_mode(vcpu)) {
7991825b 1830 /*
27fc51b2
NHE		 1831 * We're here if L1 chose not to trap WRMSR to TSC. According
1832 * to the spec, this should set L1's TSC; The offset that L1
1833 * set for L2 remains unchanged, and still needs to be added
1834 * to the newly set TSC to get L2's TSC.
7991825b 1835 */
27fc51b2
NHE		 1836 struct vmcs12 *vmcs12;
1837 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1838 /* recalculate vmcs02.TSC_OFFSET: */
1839 vmcs12 = get_vmcs12(vcpu);
1840 vmcs_write64(TSC_OFFSET, offset +
1841 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1842 vmcs12->tsc_offset : 0));
1843 } else {
1844 vmcs_write64(TSC_OFFSET, offset);
1845 }
6aa8b732
AK		 1846}
1847
e48672fa
ZA		 1848static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1849{
1850 u64 offset = vmcs_read64(TSC_OFFSET);
1851 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1852 if (is_guest_mode(vcpu)) {
1853 /* Even when running L2, the adjustment needs to apply to L1 */
1854 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1855 }
e48672fa
ZA		 1856}
1857
857e4099
JR		 1858static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1859{
1860 return target_tsc - native_read_tsc();
1861}
1862
801d3424
NHE		 1863static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1864{
1865 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1866 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1867}
1868
1869/*
1870 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1871 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1872 * all guests if the "nested" module option is off, and can also be disabled
1873 * for a single guest by disabling its VMX cpuid bit.
1874 */
1875static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1876{
1877 return nested && guest_cpuid_has_vmx(vcpu);
1878}
1879
b87a51ae
NHE		 1880/*
1881 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1882 * returned for the various VMX controls MSRs when nested VMX is enabled.
1883 * The same values should also be used to verify that vmcs12 control fields are
1884 * valid during nested entry from L1 to L2.
1885 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1886 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1887 * bit in the high half is on if the corresponding bit in the control field
1888 * may be on. See also vmx_control_verify().
1889 * TODO: allow these variables to be modified (downgraded) by module options
1890 * or other means.
1891 */
1892static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1893static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1894static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1895static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1896static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1897static __init void nested_vmx_setup_ctls_msrs(void)
1898{
1899 /*
1900 * Note that as a general rule, the high half of the MSRs (bits in
1901 * the control fields which may be 1) should be initialized by the
1902 * intersection of the underlying hardware's MSR (i.e., features which
1903 * can be supported) and the list of features we want to expose -
1904 * because they are known to be properly supported in our code.
1905 * Also, usually, the low half of the MSRs (bits which must be 1) can
1906 * be set to 0, meaning that L1 may turn off any of these bits. The
1907 * reason is that if one of these bits is necessary, it will appear
1908 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1909 * fields of vmcs01 and vmcs02, will turn these bits off - and
1910 * nested_vmx_exit_handled() will not pass related exits to L1.
1911 * These rules have exceptions below.
1912 */
1913
1914 /* pin-based controls */
1915 /*
1916 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1917 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1918 */
1919 nested_vmx_pinbased_ctls_low = 0x16 ;
1920 nested_vmx_pinbased_ctls_high = 0x16 |
1921 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1922 PIN_BASED_VIRTUAL_NMIS;
1923
1924 /* exit controls */
1925 nested_vmx_exit_ctls_low = 0;
b6f1250e 1926 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1927#ifdef CONFIG_X86_64
1928 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1929#else
1930 nested_vmx_exit_ctls_high = 0;
1931#endif
1932
1933 /* entry controls */
1934 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1935 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1936 nested_vmx_entry_ctls_low = 0;
1937 nested_vmx_entry_ctls_high &=
1938 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1939
1940 /* cpu-based controls */
1941 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1942 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1943 nested_vmx_procbased_ctls_low = 0;
1944 nested_vmx_procbased_ctls_high &=
1945 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1946 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1947 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1948 CPU_BASED_CR3_STORE_EXITING |
1949#ifdef CONFIG_X86_64
1950 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1951#endif
1952 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1953 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1954 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1955 /*
1956 * We can allow some features even when not supported by the
1957 * hardware. For example, L1 can specify an MSR bitmap - and we
1958 * can use it to avoid exits to L1 - even when L0 runs L2
1959 * without MSR bitmaps.
1960 */
1961 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1962
1963 /* secondary cpu-based controls */
1964 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1965 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1966 nested_vmx_secondary_ctls_low = 0;
1967 nested_vmx_secondary_ctls_high &=
1968 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1969}
1970
1971static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1972{
1973 /*
1974 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1975 */
1976 return ((control & high) | low) == control;
1977}
1978
1979static inline u64 vmx_control_msr(u32 low, u32 high)
1980{
1981 return low | ((u64)high << 32);
1982}
1983
1984/*
1985 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1986 * also let it use VMX-specific MSRs.
1987 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1988 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1989 * like all other MSRs).
1990 */
1991static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1992{
1993 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1994 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1995 /*
1996 * According to the spec, processors which do not support VMX
1997 * should throw a #GP(0) when VMX capability MSRs are read.
1998 */
1999 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2000 return 1;
2001 }
2002
2003 switch (msr_index) {
2004 case MSR_IA32_FEATURE_CONTROL:
2005 *pdata = 0;
2006 break;
2007 case MSR_IA32_VMX_BASIC:
2008 /*
2009 * This MSR reports some information about VMX support. We
2010 * should return information about the VMX we emulate for the
2011 * guest, and the VMCS structure we give it - not about the
2012 * VMX support of the underlying hardware.
2013 */
2014 *pdata = VMCS12_REVISION |
2015 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2016 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2017 break;
2018 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2019 case MSR_IA32_VMX_PINBASED_CTLS:
2020 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2021 nested_vmx_pinbased_ctls_high);
2022 break;
2023 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2024 case MSR_IA32_VMX_PROCBASED_CTLS:
2025 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2026 nested_vmx_procbased_ctls_high);
2027 break;
2028 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2029 case MSR_IA32_VMX_EXIT_CTLS:
2030 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2031 nested_vmx_exit_ctls_high);
2032 break;
2033 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2034 case MSR_IA32_VMX_ENTRY_CTLS:
2035 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2036 nested_vmx_entry_ctls_high);
2037 break;
2038 case MSR_IA32_VMX_MISC:
2039 *pdata = 0;
2040 break;
2041 /*
2042 * These MSRs specify bits which the guest must keep fixed (on or off)
2043 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2044 * We picked the standard core2 setting.
2045 */
2046#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2047#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2048 case MSR_IA32_VMX_CR0_FIXED0:
2049 *pdata = VMXON_CR0_ALWAYSON;
2050 break;
2051 case MSR_IA32_VMX_CR0_FIXED1:
2052 *pdata = -1ULL;
2053 break;
2054 case MSR_IA32_VMX_CR4_FIXED0:
2055 *pdata = VMXON_CR4_ALWAYSON;
2056 break;
2057 case MSR_IA32_VMX_CR4_FIXED1:
2058 *pdata = -1ULL;
2059 break;
2060 case MSR_IA32_VMX_VMCS_ENUM:
2061 *pdata = 0x1f;
2062 break;
2063 case MSR_IA32_VMX_PROCBASED_CTLS2:
2064 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2065 nested_vmx_secondary_ctls_high);
2066 break;
2067 case MSR_IA32_VMX_EPT_VPID_CAP:
2068 /* Currently, no nested ept or nested vpid */
2069 *pdata = 0;
2070 break;
2071 default:
2072 return 0;
2073 }
2074
2075 return 1;
2076}
2077
2078static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2079{
2080 if (!nested_vmx_allowed(vcpu))
2081 return 0;
2082
2083 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2084 /* TODO: the right thing. */
2085 return 1;
2086 /*
2087 * No need to treat VMX capability MSRs specially: If we don't handle
2088 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2089 */
2090 return 0;
2091}
2092
6aa8b732
AK		 2093/*
2094 * Reads an msr value (of 'msr_index') into 'pdata'.
2095 * Returns 0 on success, non-0 otherwise.
2096 * Assumes vcpu_load() was already called.
2097 */
2098static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2099{
2100 u64 data;
26bb0981 2101 struct shared_msr_entry *msr;
6aa8b732
AK		 2102
2103 if (!pdata) {
2104 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2105 return -EINVAL;
2106 }
2107
2108 switch (msr_index) {
05b3e0c2 2109#ifdef CONFIG_X86_64
6aa8b732
AK		 2110 case MSR_FS_BASE:
2111 data = vmcs_readl(GUEST_FS_BASE);
2112 break;
2113 case MSR_GS_BASE:
2114 data = vmcs_readl(GUEST_GS_BASE);
2115 break;
44ea2b17
AK		 2116 case MSR_KERNEL_GS_BASE:
2117 vmx_load_host_state(to_vmx(vcpu));
2118 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2119 break;
26bb0981 2120#endif
6aa8b732 2121 case MSR_EFER:
3bab1f5d 2122 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2123 case MSR_IA32_TSC:
6aa8b732
AK		 2124 data = guest_read_tsc();
2125 break;
2126 case MSR_IA32_SYSENTER_CS:
2127 data = vmcs_read32(GUEST_SYSENTER_CS);
2128 break;
2129 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2130 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2131 break;
2132 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2133 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2134 break;
4e47c7a6
SY		 2135 case MSR_TSC_AUX:
2136 if (!to_vmx(vcpu)->rdtscp_enabled)
2137 return 1;
2138 /* Otherwise falls through */
6aa8b732 2139 default:
26bb0981 2140 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2141 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2142 return 0;
8b9cf98c 2143 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2144 if (msr) {
542423b0 2145 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2146 data = msr->data;
2147 break;
6aa8b732 2148 }
3bab1f5d 2149 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2150 }
2151
2152 *pdata = data;
2153 return 0;
2154}
2155
2156/*
2157 * Writes msr value into into the appropriate "register".
2158 * Returns 0 on success, non-0 otherwise.
2159 * Assumes vcpu_load() was already called.
2160 */
2161static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2162{
a2fa3e9f 2163 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2164 struct shared_msr_entry *msr;
2cc51560
ED		 2165 int ret = 0;
2166
6aa8b732 2167 switch (msr_index) {
3bab1f5d 2168 case MSR_EFER:
a9b21b62 2169 vmx_load_host_state(vmx);
2cc51560 2170 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2171 break;
16175a79 2172#ifdef CONFIG_X86_64
6aa8b732 2173 case MSR_FS_BASE:
2fb92db1 2174 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2175 vmcs_writel(GUEST_FS_BASE, data);
2176 break;
2177 case MSR_GS_BASE:
2fb92db1 2178 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2179 vmcs_writel(GUEST_GS_BASE, data);
2180 break;
44ea2b17
AK		 2181 case MSR_KERNEL_GS_BASE:
2182 vmx_load_host_state(vmx);
2183 vmx->msr_guest_kernel_gs_base = data;
2184 break;
6aa8b732
AK		 2185#endif
2186 case MSR_IA32_SYSENTER_CS:
2187 vmcs_write32(GUEST_SYSENTER_CS, data);
2188 break;
2189 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2190 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2191 break;
2192 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2193 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2194 break;
af24a4e4 2195 case MSR_IA32_TSC:
99e3e30a 2196 kvm_write_tsc(vcpu, data);
6aa8b732 2197 break;
468d472f
SY		 2198 case MSR_IA32_CR_PAT:
2199 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2200 vmcs_write64(GUEST_IA32_PAT, data);
2201 vcpu->arch.pat = data;
2202 break;
2203 }
4e47c7a6
SY		 2204 ret = kvm_set_msr_common(vcpu, msr_index, data);
2205 break;
2206 case MSR_TSC_AUX:
2207 if (!vmx->rdtscp_enabled)
2208 return 1;
2209 /* Check reserved bit, higher 32 bits should be zero */
2210 if ((data >> 32) != 0)
2211 return 1;
2212 /* Otherwise falls through */
6aa8b732 2213 default:
b87a51ae
NHE		 2214 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2215 break;
8b9cf98c 2216 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2217 if (msr) {
542423b0 2218 vmx_load_host_state(vmx);
3bab1f5d
AK		 2219 msr->data = data;
2220 break;
6aa8b732 2221 }
2cc51560 2222 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2223 }
2224
2cc51560 2225 return ret;
6aa8b732
AK		 2226}
2227
5fdbf976 2228static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2229{
5fdbf976
MT		 2230 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2231 switch (reg) {
2232 case VCPU_REGS_RSP:
2233 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2234 break;
2235 case VCPU_REGS_RIP:
2236 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2237 break;
6de4f3ad
AK		 2238 case VCPU_EXREG_PDPTR:
2239 if (enable_ept)
2240 ept_save_pdptrs(vcpu);
2241 break;
5fdbf976
MT		 2242 default:
2243 break;
2244 }
6aa8b732
AK		 2245}
2246
355be0b9 2247static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2248{
ae675ef0
JK		 2249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2250 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2251 else
2252 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2253
abd3f2d6 2254 update_exception_bitmap(vcpu);
6aa8b732
AK		 2255}
2256
2257static __init int cpu_has_kvm_support(void)
2258{
6210e37b 2259 return cpu_has_vmx();
6aa8b732
AK		 2260}
2261
2262static __init int vmx_disabled_by_bios(void)
2263{
2264 u64 msr;
2265
2266 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2267 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2268 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2269 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2270 && tboot_enabled())
2271 return 1;
23f3e991 2272 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2273 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2274 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2275 && !tboot_enabled()) {
2276 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2277 "activate TXT before enabling KVM\n");
cafd6659 2278 return 1;
f9335afe 2279 }
23f3e991
JC		 2280 /* launched w/o TXT and VMX disabled */
2281 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2282 && !tboot_enabled())
2283 return 1;
cafd6659
SW		 2284 }
2285
2286 return 0;
6aa8b732
AK		 2287}
2288
7725b894
DX		 2289static void kvm_cpu_vmxon(u64 addr)
2290{
2291 asm volatile (ASM_VMX_VMXON_RAX
2292 : : "a"(&addr), "m"(addr)
2293 : "memory", "cc");
2294}
2295
10474ae8 2296static int hardware_enable(void *garbage)
6aa8b732
AK		 2297{
2298 int cpu = raw_smp_processor_id();
2299 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2300 u64 old, test_bits;
6aa8b732 2301
10474ae8
AG		 2302 if (read_cr4() & X86_CR4_VMXE)
2303 return -EBUSY;
2304
d462b819 2305 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2306 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2307
2308 test_bits = FEATURE_CONTROL_LOCKED;
2309 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2310 if (tboot_enabled())
2311 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2312
2313 if ((old & test_bits) != test_bits) {
6aa8b732 2314 /* enable and lock */
cafd6659
SW		 2315 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2316 }
66aee91a 2317 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2318
4610c9cc
DX		 2319 if (vmm_exclusive) {
2320 kvm_cpu_vmxon(phys_addr);
2321 ept_sync_global();
2322 }
10474ae8 2323
3444d7da
AK		 2324 store_gdt(&__get_cpu_var(host_gdt));
2325
10474ae8 2326 return 0;
6aa8b732
AK		 2327}
2328
d462b819 2329static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2330{
2331 int cpu = raw_smp_processor_id();
d462b819 2332 struct loaded_vmcs *v, *n;
543e4243 2333
d462b819
NHE		 2334 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2335 loaded_vmcss_on_cpu_link)
2336 __loaded_vmcs_clear(v);
543e4243
AK		 2337}
2338
710ff4a8
EH		 2339
2340/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2341 * tricks.
2342 */
2343static void kvm_cpu_vmxoff(void)
6aa8b732 2344{
4ecac3fd 2345 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2346}
2347
710ff4a8
EH		 2348static void hardware_disable(void *garbage)
2349{
4610c9cc 2350 if (vmm_exclusive) {
d462b819 2351 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2352 kvm_cpu_vmxoff();
2353 }
7725b894 2354 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2355}
2356
1c3d14fe 2357static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2358 u32 msr, u32 *result)
1c3d14fe
YS		 2359{
2360 u32 vmx_msr_low, vmx_msr_high;
2361 u32 ctl = ctl_min | ctl_opt;
2362
2363 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2364
2365 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2366 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2367
2368 /* Ensure minimum (required) set of control bits are supported. */
2369 if (ctl_min & ~ctl)
002c7f7c 2370 return -EIO;
1c3d14fe
YS		 2371
2372 *result = ctl;
2373 return 0;
2374}
2375
110312c8
AK		 2376static __init bool allow_1_setting(u32 msr, u32 ctl)
2377{
2378 u32 vmx_msr_low, vmx_msr_high;
2379
2380 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2381 return vmx_msr_high & ctl;
2382}
2383
002c7f7c 2384static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2385{
2386 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2387 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2388 u32 _pin_based_exec_control = 0;
2389 u32 _cpu_based_exec_control = 0;
f78e0e2e 2390 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2391 u32 _vmexit_control = 0;
2392 u32 _vmentry_control = 0;
2393
2394 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2395 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2396 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2397 &_pin_based_exec_control) < 0)
002c7f7c 2398 return -EIO;
1c3d14fe 2399
443381a8 2400 min =
1c3d14fe
YS		 2401#ifdef CONFIG_X86_64
2402 CPU_BASED_CR8_LOAD_EXITING |
2403 CPU_BASED_CR8_STORE_EXITING |
2404#endif
d56f546d
SY		 2405 CPU_BASED_CR3_LOAD_EXITING |
2406 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2407 CPU_BASED_USE_IO_BITMAPS |
2408 CPU_BASED_MOV_DR_EXITING |
a7052897 2409 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2410 CPU_BASED_MWAIT_EXITING |
2411 CPU_BASED_MONITOR_EXITING |
a7052897 2412 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2413
2414 if (yield_on_hlt)
2415 min |= CPU_BASED_HLT_EXITING;
2416
f78e0e2e 2417 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2418 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2419 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2420 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2421 &_cpu_based_exec_control) < 0)
002c7f7c 2422 return -EIO;
6e5d865c
YS		 2423#ifdef CONFIG_X86_64
2424 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2425 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2426 ~CPU_BASED_CR8_STORE_EXITING;
2427#endif
f78e0e2e 2428 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2429 min2 = 0;
2430 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2431 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2432 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2433 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2434 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2435 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2436 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2437 if (adjust_vmx_controls(min2, opt2,
2438 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2439 &_cpu_based_2nd_exec_control) < 0)
2440 return -EIO;
2441 }
2442#ifndef CONFIG_X86_64
2443 if (!(_cpu_based_2nd_exec_control &
2444 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2445 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2446#endif
d56f546d 2447 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2448 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2449 enabled */
5fff7d27
GN		 2450 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2451 CPU_BASED_CR3_STORE_EXITING |
2452 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2453 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2454 vmx_capability.ept, vmx_capability.vpid);
2455 }
1c3d14fe
YS		 2456
2457 min = 0;
2458#ifdef CONFIG_X86_64
2459 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2460#endif
468d472f 2461 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2462 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2463 &_vmexit_control) < 0)
002c7f7c 2464 return -EIO;
1c3d14fe 2465
468d472f
SY		 2466 min = 0;
2467 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469 &_vmentry_control) < 0)
002c7f7c 2470 return -EIO;
6aa8b732 2471
c68876fd 2472 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2473
2474 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2475 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2476 return -EIO;
1c3d14fe
YS		 2477
2478#ifdef CONFIG_X86_64
2479 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2480 if (vmx_msr_high & (1u<<16))
002c7f7c 2481 return -EIO;
1c3d14fe
YS		 2482#endif
2483
2484 /* Require Write-Back (WB) memory type for VMCS accesses. */
2485 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2486 return -EIO;
1c3d14fe 2487
002c7f7c
YS		 2488 vmcs_conf->size = vmx_msr_high & 0x1fff;
2489 vmcs_conf->order = get_order(vmcs_config.size);
2490 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2491
002c7f7c
YS		 2492 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2493 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2494 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2495 vmcs_conf->vmexit_ctrl = _vmexit_control;
2496 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2497
110312c8
AK		 2498 cpu_has_load_ia32_efer =
2499 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500 VM_ENTRY_LOAD_IA32_EFER)
2501 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502 VM_EXIT_LOAD_IA32_EFER);
2503
8bf00a52
GN		 2504 cpu_has_load_perf_global_ctrl =
2505 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2506 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2507 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2508 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2509
2510 /*
2511 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2512 * but due to arrata below it can't be used. Workaround is to use
2513 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2514 *
2515 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2516 *
2517 * AAK155 (model 26)
2518 * AAP115 (model 30)
2519 * AAT100 (model 37)
2520 * BC86,AAY89,BD102 (model 44)
2521 * BA97 (model 46)
2522 *
2523 */
2524 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2525 switch (boot_cpu_data.x86_model) {
2526 case 26:
2527 case 30:
2528 case 37:
2529 case 44:
2530 case 46:
2531 cpu_has_load_perf_global_ctrl = false;
2532 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2533 "does not work properly. Using workaround\n");
2534 break;
2535 default:
2536 break;
2537 }
2538 }
2539
1c3d14fe 2540 return 0;
c68876fd 2541}
6aa8b732
AK		 2542
2543static struct vmcs *alloc_vmcs_cpu(int cpu)
2544{
2545 int node = cpu_to_node(cpu);
2546 struct page *pages;
2547 struct vmcs *vmcs;
2548
6484eb3e 2549 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2550 if (!pages)
2551 return NULL;
2552 vmcs = page_address(pages);
1c3d14fe
YS		 2553 memset(vmcs, 0, vmcs_config.size);
2554 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2555 return vmcs;
2556}
2557
2558static struct vmcs *alloc_vmcs(void)
2559{
d3b2c338 2560 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2561}
2562
2563static void free_vmcs(struct vmcs *vmcs)
2564{
1c3d14fe 2565 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2566}
2567
d462b819
NHE		 2568/*
2569 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2570 */
2571static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2572{
2573 if (!loaded_vmcs->vmcs)
2574 return;
2575 loaded_vmcs_clear(loaded_vmcs);
2576 free_vmcs(loaded_vmcs->vmcs);
2577 loaded_vmcs->vmcs = NULL;
2578}
2579
39959588 2580static void free_kvm_area(void)
6aa8b732
AK		 2581{
2582 int cpu;
2583
3230bb47 2584 for_each_possible_cpu(cpu) {
6aa8b732 2585 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2586 per_cpu(vmxarea, cpu) = NULL;
2587 }
6aa8b732
AK		 2588}
2589
6aa8b732
AK		 2590static __init int alloc_kvm_area(void)
2591{
2592 int cpu;
2593
3230bb47 2594 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2595 struct vmcs *vmcs;
2596
2597 vmcs = alloc_vmcs_cpu(cpu);
2598 if (!vmcs) {
2599 free_kvm_area();
2600 return -ENOMEM;
2601 }
2602
2603 per_cpu(vmxarea, cpu) = vmcs;
2604 }
2605 return 0;
2606}
2607
2608static __init int hardware_setup(void)
2609{
002c7f7c
YS		 2610 if (setup_vmcs_config(&vmcs_config) < 0)
2611 return -EIO;
50a37eb4
JR		 2612
2613 if (boot_cpu_has(X86_FEATURE_NX))
2614 kvm_enable_efer_bits(EFER_NX);
2615
93ba03c2
SY		 2616 if (!cpu_has_vmx_vpid())
2617 enable_vpid = 0;
2618
4bc9b982
SY		 2619 if (!cpu_has_vmx_ept() ||
2620 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2621 enable_ept = 0;
3a624e29
NK		 2622 enable_unrestricted_guest = 0;
2623 }
2624
2625 if (!cpu_has_vmx_unrestricted_guest())
2626 enable_unrestricted_guest = 0;
93ba03c2
SY		 2627
2628 if (!cpu_has_vmx_flexpriority())
2629 flexpriority_enabled = 0;
2630
95ba8273
GN		 2631 if (!cpu_has_vmx_tpr_shadow())
2632 kvm_x86_ops->update_cr8_intercept = NULL;
2633
54dee993
MT		 2634 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2635 kvm_disable_largepages();
2636
4b8d54f9
ZE		 2637 if (!cpu_has_vmx_ple())
2638 ple_gap = 0;
2639
b87a51ae
NHE		 2640 if (nested)
2641 nested_vmx_setup_ctls_msrs();
2642
6aa8b732
AK		 2643 return alloc_kvm_area();
2644}
2645
2646static __exit void hardware_unsetup(void)
2647{
2648 free_kvm_area();
2649}
2650
6aa8b732
AK		 2651static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2652{
2653 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2654
6af11b9e 2655 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2656 vmcs_write16(sf->selector, save->selector);
2657 vmcs_writel(sf->base, save->base);
2658 vmcs_write32(sf->limit, save->limit);
2659 vmcs_write32(sf->ar_bytes, save->ar);
2660 } else {
2661 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2662 << AR_DPL_SHIFT;
2663 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2664 }
2665}
2666
2667static void enter_pmode(struct kvm_vcpu *vcpu)
2668{
2669 unsigned long flags;
a89a8fb9 2670 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2671
a89a8fb9 2672 vmx->emulation_required = 1;
7ffd92c5 2673 vmx->rmode.vm86_active = 0;
6aa8b732 2674
2fb92db1
AK		 2675 vmx_segment_cache_clear(vmx);
2676
d0ba64f9 2677 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2678 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2679 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2680 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2681
2682 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2683 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2684 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2685 vmcs_writel(GUEST_RFLAGS, flags);
2686
66aee91a
RR		 2687 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2688 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2689
2690 update_exception_bitmap(vcpu);
2691
a89a8fb9
MG		 2692 if (emulate_invalid_guest_state)
2693 return;
2694
7ffd92c5
AK		 2695 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2696 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2697 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2698 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2699
2fb92db1
AK		 2700 vmx_segment_cache_clear(vmx);
2701
6aa8b732
AK		 2702 vmcs_write16(GUEST_SS_SELECTOR, 0);
2703 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2704
2705 vmcs_write16(GUEST_CS_SELECTOR,
2706 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2707 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2708}
2709
d77c26fc 2710static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2711{
bfc6d222 2712 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2713 struct kvm_memslots *slots;
2714 gfn_t base_gfn;
2715
90d83dc3 2716 slots = kvm_memslots(kvm);
f495c6e5 2717 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2718 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2719 return base_gfn << PAGE_SHIFT;
2720 }
bfc6d222 2721 return kvm->arch.tss_addr;
6aa8b732
AK		 2722}
2723
2724static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2725{
2726 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2727
2728 save->selector = vmcs_read16(sf->selector);
2729 save->base = vmcs_readl(sf->base);
2730 save->limit = vmcs_read32(sf->limit);
2731 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2732 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2733 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2734 vmcs_write32(sf->limit, 0xffff);
2735 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2736 if (save->base & 0xf)
2737 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2738 " aligned when entering protected mode (seg=%d)",
2739 seg);
6aa8b732
AK		 2740}
2741
2742static void enter_rmode(struct kvm_vcpu *vcpu)
2743{
2744 unsigned long flags;
a89a8fb9 2745 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2746
3a624e29
NK		 2747 if (enable_unrestricted_guest)
2748 return;
2749
a89a8fb9 2750 vmx->emulation_required = 1;
7ffd92c5 2751 vmx->rmode.vm86_active = 1;
6aa8b732 2752
776e58ea
GN		 2753 /*
2754 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2755 * vcpu. Call it here with phys address pointing 16M below 4G.
2756 */
2757 if (!vcpu->kvm->arch.tss_addr) {
2758 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2759 "called before entering vcpu\n");
2760 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2761 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2762 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2763 }
2764
2fb92db1
AK		 2765 vmx_segment_cache_clear(vmx);
2766
d0ba64f9 2767 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2768 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2769 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2770
7ffd92c5 2771 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2772 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2773
7ffd92c5 2774 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2775 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2776
2777 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2778 vmx->rmode.save_rflags = flags;
6aa8b732 2779
053de044 2780 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2781
2782 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2783 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2784 update_exception_bitmap(vcpu);
2785
a89a8fb9
MG		 2786 if (emulate_invalid_guest_state)
2787 goto continue_rmode;
2788
6aa8b732
AK		 2789 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2790 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2791 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2792
2793 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2794 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2795 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2796 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2797 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2798
7ffd92c5
AK		 2799 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2800 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2801 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2802 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2803
a89a8fb9 2804continue_rmode:
8668a3c4 2805 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2806}
2807
401d10de
AS		 2808static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2809{
2810 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2811 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2812
2813 if (!msr)
2814 return;
401d10de 2815
44ea2b17
AK		 2816 /*
2817 * Force kernel_gs_base reloading before EFER changes, as control
2818 * of this msr depends on is_long_mode().
2819 */
2820 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2821 vcpu->arch.efer = efer;
401d10de
AS		 2822 if (efer & EFER_LMA) {
2823 vmcs_write32(VM_ENTRY_CONTROLS,
2824 vmcs_read32(VM_ENTRY_CONTROLS) |
2825 VM_ENTRY_IA32E_MODE);
2826 msr->data = efer;
2827 } else {
2828 vmcs_write32(VM_ENTRY_CONTROLS,
2829 vmcs_read32(VM_ENTRY_CONTROLS) &
2830 ~VM_ENTRY_IA32E_MODE);
2831
2832 msr->data = efer & ~EFER_LME;
2833 }
2834 setup_msrs(vmx);
2835}
2836
05b3e0c2 2837#ifdef CONFIG_X86_64
6aa8b732
AK		 2838
2839static void enter_lmode(struct kvm_vcpu *vcpu)
2840{
2841 u32 guest_tr_ar;
2842
2fb92db1
AK		 2843 vmx_segment_cache_clear(to_vmx(vcpu));
2844
6aa8b732
AK		 2845 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2846 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2847 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2848 __func__);
6aa8b732
AK		 2849 vmcs_write32(GUEST_TR_AR_BYTES,
2850 (guest_tr_ar & ~AR_TYPE_MASK)
2851 | AR_TYPE_BUSY_64_TSS);
2852 }
da38f438 2853 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2854}
2855
2856static void exit_lmode(struct kvm_vcpu *vcpu)
2857{
6aa8b732
AK		 2858 vmcs_write32(VM_ENTRY_CONTROLS,
2859 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2860 & ~VM_ENTRY_IA32E_MODE);
da38f438 2861 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2862}
2863
2864#endif
2865
2384d2b3
SY		 2866static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2867{
b9d762fa 2868 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2869 if (enable_ept) {
2870 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2871 return;
4e1096d2 2872 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2873 }
2384d2b3
SY		 2874}
2875
e8467fda
AK		 2876static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2877{
2878 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2879
2880 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2881 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2882}
2883
aff48baa
AK		 2884static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2885{
2886 if (enable_ept && is_paging(vcpu))
2887 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2888 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2889}
2890
25c4c276 2891static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2892{
fc78f519
AK		 2893 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2894
2895 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2896 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2897}
2898
1439442c
SY		 2899static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2900{
6de4f3ad
AK		 2901 if (!test_bit(VCPU_EXREG_PDPTR,
2902 (unsigned long *)&vcpu->arch.regs_dirty))
2903 return;
2904
1439442c 2905 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2906 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2907 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2908 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2909 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2910 }
2911}
2912
8f5d549f
AK		 2913static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2914{
2915 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2916 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2917 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2918 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2919 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2920 }
6de4f3ad
AK		 2921
2922 __set_bit(VCPU_EXREG_PDPTR,
2923 (unsigned long *)&vcpu->arch.regs_avail);
2924 __set_bit(VCPU_EXREG_PDPTR,
2925 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2926}
2927
5e1746d6 2928static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2929
2930static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2931 unsigned long cr0,
2932 struct kvm_vcpu *vcpu)
2933{
5233dd51
MT		 2934 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2935 vmx_decache_cr3(vcpu);
1439442c
SY		 2936 if (!(cr0 & X86_CR0_PG)) {
2937 /* From paging/starting to nonpaging */
2938 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2939 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2940 (CPU_BASED_CR3_LOAD_EXITING |
2941 CPU_BASED_CR3_STORE_EXITING));
2942 vcpu->arch.cr0 = cr0;
fc78f519 2943 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2944 } else if (!is_paging(vcpu)) {
2945 /* From nonpaging to paging */
2946 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2947 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2948 ~(CPU_BASED_CR3_LOAD_EXITING |
2949 CPU_BASED_CR3_STORE_EXITING));
2950 vcpu->arch.cr0 = cr0;
fc78f519 2951 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2952 }
95eb84a7
SY		 2953
2954 if (!(cr0 & X86_CR0_WP))
2955 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2956}
2957
6aa8b732
AK		 2958static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2959{
7ffd92c5 2960 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2961 unsigned long hw_cr0;
2962
2963 if (enable_unrestricted_guest)
2964 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2965 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2966 else
2967 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2968
7ffd92c5 2969 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2970 enter_pmode(vcpu);
2971
7ffd92c5 2972 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2973 enter_rmode(vcpu);
2974
05b3e0c2 2975#ifdef CONFIG_X86_64
f6801dff 2976 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2977 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2978 enter_lmode(vcpu);
707d92fa 2979 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2980 exit_lmode(vcpu);
2981 }
2982#endif
2983
089d034e 2984 if (enable_ept)
1439442c
SY		 2985 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2986
02daab21 2987 if (!vcpu->fpu_active)
81231c69 2988 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2989
6aa8b732 2990 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2991 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2992 vcpu->arch.cr0 = cr0;
69c73028 2993 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2994}
2995
1439442c
SY		 2996static u64 construct_eptp(unsigned long root_hpa)
2997{
2998 u64 eptp;
2999
3000 /* TODO write the value reading from MSR */
3001 eptp = VMX_EPT_DEFAULT_MT |
3002 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3003 eptp |= (root_hpa & PAGE_MASK);
3004
3005 return eptp;
3006}
3007
6aa8b732
AK		 3008static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3009{
1439442c
SY		 3010 unsigned long guest_cr3;
3011 u64 eptp;
3012
3013 guest_cr3 = cr3;
089d034e 3014 if (enable_ept) {
1439442c
SY		 3015 eptp = construct_eptp(cr3);
3016 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3017 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3018 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3019 ept_load_pdptrs(vcpu);
1439442c
SY		 3020 }
3021
2384d2b3 3022 vmx_flush_tlb(vcpu);
1439442c 3023 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3024}
3025
5e1746d6 3026static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3027{
7ffd92c5 3028 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3029 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3030
5e1746d6
NHE		 3031 if (cr4 & X86_CR4_VMXE) {
3032 /*
3033 * To use VMXON (and later other VMX instructions), a guest
3034 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3035 * So basically the check on whether to allow nested VMX
3036 * is here.
3037 */
3038 if (!nested_vmx_allowed(vcpu))
3039 return 1;
3040 } else if (to_vmx(vcpu)->nested.vmxon)
3041 return 1;
3042
ad312c7c 3043 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3044 if (enable_ept) {
3045 if (!is_paging(vcpu)) {
3046 hw_cr4 &= ~X86_CR4_PAE;
3047 hw_cr4 |= X86_CR4_PSE;
3048 } else if (!(cr4 & X86_CR4_PAE)) {
3049 hw_cr4 &= ~X86_CR4_PAE;
3050 }
3051 }
1439442c
SY		 3052
3053 vmcs_writel(CR4_READ_SHADOW, cr4);
3054 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3055 return 0;
6aa8b732
AK		 3056}
3057
6aa8b732
AK		 3058static void vmx_get_segment(struct kvm_vcpu *vcpu,
3059 struct kvm_segment *var, int seg)
3060{
a9179499 3061 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3062 struct kvm_save_segment *save;
6aa8b732
AK		 3063 u32 ar;
3064
a9179499
AK		 3065 if (vmx->rmode.vm86_active
3066 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3067 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3068 || seg == VCPU_SREG_GS)
3069 && !emulate_invalid_guest_state) {
3070 switch (seg) {
3071 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3072 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3073 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3074 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3075 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3076 default: BUG();
3077 }
3078 var->selector = save->selector;
3079 var->base = save->base;
3080 var->limit = save->limit;
3081 ar = save->ar;
3082 if (seg == VCPU_SREG_TR
2fb92db1 3083 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3084 goto use_saved_rmode_seg;
3085 }
2fb92db1
AK		 3086 var->base = vmx_read_guest_seg_base(vmx, seg);
3087 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3088 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3089 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3090use_saved_rmode_seg:
9fd4a3b7 3091 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3092 ar = 0;
3093 var->type = ar & 15;
3094 var->s = (ar >> 4) & 1;
3095 var->dpl = (ar >> 5) & 3;
3096 var->present = (ar >> 7) & 1;
3097 var->avl = (ar >> 12) & 1;
3098 var->l = (ar >> 13) & 1;
3099 var->db = (ar >> 14) & 1;
3100 var->g = (ar >> 15) & 1;
3101 var->unusable = (ar >> 16) & 1;
3102}
3103
a9179499
AK		 3104static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3105{
a9179499
AK		 3106 struct kvm_segment s;
3107
3108 if (to_vmx(vcpu)->rmode.vm86_active) {
3109 vmx_get_segment(vcpu, &s, seg);
3110 return s.base;
3111 }
2fb92db1 3112 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3113}
3114
69c73028 3115static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3116{
3eeb3288 3117 if (!is_protmode(vcpu))
2e4d2653
IE		 3118 return 0;
3119
f4c63e5d
AK		 3120 if (!is_long_mode(vcpu)
3121 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3122 return 3;
3123
2fb92db1 3124 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3125}
3126
69c73028
AK		 3127static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3128{
3129 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3130 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3131 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3132 }
3133 return to_vmx(vcpu)->cpl;
3134}
3135
3136
653e3108 3137static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3138{
6aa8b732
AK		 3139 u32 ar;
3140
653e3108 3141 if (var->unusable)
6aa8b732
AK		 3142 ar = 1 << 16;
3143 else {
3144 ar = var->type & 15;
3145 ar |= (var->s & 1) << 4;
3146 ar |= (var->dpl & 3) << 5;
3147 ar |= (var->present & 1) << 7;
3148 ar |= (var->avl & 1) << 12;
3149 ar |= (var->l & 1) << 13;
3150 ar |= (var->db & 1) << 14;
3151 ar |= (var->g & 1) << 15;
3152 }
f7fbf1fd
UL		 3153 if (ar == 0) /* a 0 value means unusable */
3154 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3155
3156 return ar;
3157}
3158
3159static void vmx_set_segment(struct kvm_vcpu *vcpu,
3160 struct kvm_segment *var, int seg)
3161{
7ffd92c5 3162 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3163 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3164 u32 ar;
3165
2fb92db1
AK		 3166 vmx_segment_cache_clear(vmx);
3167
7ffd92c5 3168 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3169 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3170 vmx->rmode.tr.selector = var->selector;
3171 vmx->rmode.tr.base = var->base;
3172 vmx->rmode.tr.limit = var->limit;
3173 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3174 return;
3175 }
3176 vmcs_writel(sf->base, var->base);
3177 vmcs_write32(sf->limit, var->limit);
3178 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3179 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3180 /*
3181 * Hack real-mode segments into vm86 compatibility.
3182 */
3183 if (var->base == 0xffff0000 && var->selector == 0xf000)
3184 vmcs_writel(sf->base, 0xf0000);
3185 ar = 0xf3;
3186 } else
3187 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3188
3189 /*
3190 * Fix the "Accessed" bit in AR field of segment registers for older
3191 * qemu binaries.
3192 * IA32 arch specifies that at the time of processor reset the
3193 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3194 * is setting it to 0 in the usedland code. This causes invalid guest
3195 * state vmexit when "unrestricted guest" mode is turned on.
3196 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3197 * tree. Newer qemu binaries with that qemu fix would not need this
3198 * kvm hack.
3199 */
3200 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3201 ar |= 0x1; /* Accessed */
3202
6aa8b732 3203 vmcs_write32(sf->ar_bytes, ar);
69c73028 3204 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3205}
3206
6aa8b732
AK		 3207static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3208{
2fb92db1 3209 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3210
3211 *db = (ar >> 14) & 1;
3212 *l = (ar >> 13) & 1;
3213}
3214
89a27f4d 3215static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3216{
89a27f4d
GN		 3217 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3218 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3219}
3220
89a27f4d 3221static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3222{
89a27f4d
GN		 3223 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3224 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3225}
3226
89a27f4d 3227static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3228{
89a27f4d
GN		 3229 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3230 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3231}
3232
89a27f4d 3233static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3234{
89a27f4d
GN		 3235 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3236 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3237}
3238
648dfaa7
MG		 3239static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3240{
3241 struct kvm_segment var;
3242 u32 ar;
3243
3244 vmx_get_segment(vcpu, &var, seg);
3245 ar = vmx_segment_access_rights(&var);
3246
3247 if (var.base != (var.selector << 4))
3248 return false;
3249 if (var.limit != 0xffff)
3250 return false;
3251 if (ar != 0xf3)
3252 return false;
3253
3254 return true;
3255}
3256
3257static bool code_segment_valid(struct kvm_vcpu *vcpu)
3258{
3259 struct kvm_segment cs;
3260 unsigned int cs_rpl;
3261
3262 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3263 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3264
1872a3f4
AK		 3265 if (cs.unusable)
3266 return false;
648dfaa7
MG		 3267 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3268 return false;
3269 if (!cs.s)
3270 return false;
1872a3f4 3271 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3272 if (cs.dpl > cs_rpl)
3273 return false;
1872a3f4 3274 } else {
648dfaa7
MG		 3275 if (cs.dpl != cs_rpl)
3276 return false;
3277 }
3278 if (!cs.present)
3279 return false;
3280
3281 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3282 return true;
3283}
3284
3285static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3286{
3287 struct kvm_segment ss;
3288 unsigned int ss_rpl;
3289
3290 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3291 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3292
1872a3f4
AK		 3293 if (ss.unusable)
3294 return true;
3295 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3296 return false;
3297 if (!ss.s)
3298 return false;
3299 if (ss.dpl != ss_rpl) /* DPL != RPL */
3300 return false;
3301 if (!ss.present)
3302 return false;
3303
3304 return true;
3305}
3306
3307static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3308{
3309 struct kvm_segment var;
3310 unsigned int rpl;
3311
3312 vmx_get_segment(vcpu, &var, seg);
3313 rpl = var.selector & SELECTOR_RPL_MASK;
3314
1872a3f4
AK		 3315 if (var.unusable)
3316 return true;
648dfaa7
MG		 3317 if (!var.s)
3318 return false;
3319 if (!var.present)
3320 return false;
3321 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3322 if (var.dpl < rpl) /* DPL < RPL */
3323 return false;
3324 }
3325
3326 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3327 * rights flags
3328 */
3329 return true;
3330}
3331
3332static bool tr_valid(struct kvm_vcpu *vcpu)
3333{
3334 struct kvm_segment tr;
3335
3336 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3337
1872a3f4
AK		 3338 if (tr.unusable)
3339 return false;
648dfaa7
MG		 3340 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3341 return false;
1872a3f4 3342 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3343 return false;
3344 if (!tr.present)
3345 return false;
3346
3347 return true;
3348}
3349
3350static bool ldtr_valid(struct kvm_vcpu *vcpu)
3351{
3352 struct kvm_segment ldtr;
3353
3354 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3355
1872a3f4
AK		 3356 if (ldtr.unusable)
3357 return true;
648dfaa7
MG		 3358 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3359 return false;
3360 if (ldtr.type != 2)
3361 return false;
3362 if (!ldtr.present)
3363 return false;
3364
3365 return true;
3366}
3367
3368static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3369{
3370 struct kvm_segment cs, ss;
3371
3372 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3373 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3374
3375 return ((cs.selector & SELECTOR_RPL_MASK) ==
3376 (ss.selector & SELECTOR_RPL_MASK));
3377}
3378
3379/*
3380 * Check if guest state is valid. Returns true if valid, false if
3381 * not.
3382 * We assume that registers are always usable
3383 */
3384static bool guest_state_valid(struct kvm_vcpu *vcpu)
3385{
3386 /* real mode guest state checks */
3eeb3288 3387 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3388 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3389 return false;
3390 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3391 return false;
3392 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3393 return false;
3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3395 return false;
3396 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3397 return false;
3398 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3399 return false;
3400 } else {
3401 /* protected mode guest state checks */
3402 if (!cs_ss_rpl_check(vcpu))
3403 return false;
3404 if (!code_segment_valid(vcpu))
3405 return false;
3406 if (!stack_segment_valid(vcpu))
3407 return false;
3408 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3409 return false;
3410 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3411 return false;
3412 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3413 return false;
3414 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3415 return false;
3416 if (!tr_valid(vcpu))
3417 return false;
3418 if (!ldtr_valid(vcpu))
3419 return false;
3420 }
3421 /* TODO:
3422 * - Add checks on RIP
3423 * - Add checks on RFLAGS
3424 */
3425
3426 return true;
3427}
3428
d77c26fc 3429static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3430{
40dcaa9f 3431 gfn_t fn;
195aefde 3432 u16 data = 0;
40dcaa9f 3433 int r, idx, ret = 0;
6aa8b732 3434
40dcaa9f
XG		 3435 idx = srcu_read_lock(&kvm->srcu);
3436 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3437 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3438 if (r < 0)
10589a46 3439 goto out;
195aefde 3440 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3441 r = kvm_write_guest_page(kvm, fn++, &data,
3442 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3443 if (r < 0)
10589a46 3444 goto out;
195aefde
IE		 3445 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3446 if (r < 0)
10589a46 3447 goto out;
195aefde
IE		 3448 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3449 if (r < 0)
10589a46 3450 goto out;
195aefde 3451 data = ~0;
10589a46
MT		 3452 r = kvm_write_guest_page(kvm, fn, &data,
3453 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3454 sizeof(u8));
195aefde 3455 if (r < 0)
10589a46
MT		 3456 goto out;
3457
3458 ret = 1;
3459out:
40dcaa9f 3460 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3461 return ret;
6aa8b732
AK		 3462}
3463
b7ebfb05
SY		 3464static int init_rmode_identity_map(struct kvm *kvm)
3465{
40dcaa9f 3466 int i, idx, r, ret;
b7ebfb05
SY		 3467 pfn_t identity_map_pfn;
3468 u32 tmp;
3469
089d034e 3470 if (!enable_ept)
b7ebfb05
SY		 3471 return 1;
3472 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3473 printk(KERN_ERR "EPT: identity-mapping pagetable "
3474 "haven't been allocated!\n");
3475 return 0;
3476 }
3477 if (likely(kvm->arch.ept_identity_pagetable_done))
3478 return 1;
3479 ret = 0;
b927a3ce 3480 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3481 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3482 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3483 if (r < 0)
3484 goto out;
3485 /* Set up identity-mapping pagetable for EPT in real mode */
3486 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3487 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3488 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3489 r = kvm_write_guest_page(kvm, identity_map_pfn,
3490 &tmp, i * sizeof(tmp), sizeof(tmp));
3491 if (r < 0)
3492 goto out;
3493 }
3494 kvm->arch.ept_identity_pagetable_done = true;
3495 ret = 1;
3496out:
40dcaa9f 3497 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3498 return ret;
3499}
3500
6aa8b732
AK		 3501static void seg_setup(int seg)
3502{
3503 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3504 unsigned int ar;
6aa8b732
AK		 3505
3506 vmcs_write16(sf->selector, 0);
3507 vmcs_writel(sf->base, 0);
3508 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3509 if (enable_unrestricted_guest) {
3510 ar = 0x93;
3511 if (seg == VCPU_SREG_CS)
3512 ar |= 0x08; /* code segment */
3513 } else
3514 ar = 0xf3;
3515
3516 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3517}
3518
f78e0e2e
SY		 3519static int alloc_apic_access_page(struct kvm *kvm)
3520{
3521 struct kvm_userspace_memory_region kvm_userspace_mem;
3522 int r = 0;
3523
79fac95e 3524 mutex_lock(&kvm->slots_lock);
bfc6d222 3525 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3526 goto out;
3527 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3528 kvm_userspace_mem.flags = 0;
3529 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3530 kvm_userspace_mem.memory_size = PAGE_SIZE;
3531 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3532 if (r)
3533 goto out;
72dc67a6 3534
bfc6d222 3535 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3536out:
79fac95e 3537 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3538 return r;
3539}
3540
b7ebfb05
SY		 3541static int alloc_identity_pagetable(struct kvm *kvm)
3542{
3543 struct kvm_userspace_memory_region kvm_userspace_mem;
3544 int r = 0;
3545
79fac95e 3546 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3547 if (kvm->arch.ept_identity_pagetable)
3548 goto out;
3549 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3550 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3551 kvm_userspace_mem.guest_phys_addr =
3552 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3553 kvm_userspace_mem.memory_size = PAGE_SIZE;
3554 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3555 if (r)
3556 goto out;
3557
b7ebfb05 3558 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3559 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3560out:
79fac95e 3561 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3562 return r;
3563}
3564
2384d2b3
SY		 3565static void allocate_vpid(struct vcpu_vmx *vmx)
3566{
3567 int vpid;
3568
3569 vmx->vpid = 0;
919818ab 3570 if (!enable_vpid)
2384d2b3
SY		 3571 return;
3572 spin_lock(&vmx_vpid_lock);
3573 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3574 if (vpid < VMX_NR_VPIDS) {
3575 vmx->vpid = vpid;
3576 __set_bit(vpid, vmx_vpid_bitmap);
3577 }
3578 spin_unlock(&vmx_vpid_lock);
3579}
3580
cdbecfc3
LJ		 3581static void free_vpid(struct vcpu_vmx *vmx)
3582{
3583 if (!enable_vpid)
3584 return;
3585 spin_lock(&vmx_vpid_lock);
3586 if (vmx->vpid != 0)
3587 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3588 spin_unlock(&vmx_vpid_lock);
3589}
3590
5897297b 3591static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3592{
3e7c73e9 3593 int f = sizeof(unsigned long);
25c5f225
SY		 3594
3595 if (!cpu_has_vmx_msr_bitmap())
3596 return;
3597
3598 /*
3599 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3600 * have the write-low and read-high bitmap offsets the wrong way round.
3601 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3602 */
25c5f225 3603 if (msr <= 0x1fff) {
3e7c73e9
AK		 3604 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3605 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3606 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3607 msr &= 0x1fff;
3e7c73e9
AK		 3608 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3609 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3610 }
25c5f225
SY		 3611}
3612
5897297b
AK		 3613static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3614{
3615 if (!longmode_only)
3616 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3617 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3618}
3619
a3a8ff8e
NHE		 3620/*
3621 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3622 * will not change in the lifetime of the guest.
3623 * Note that host-state that does change is set elsewhere. E.g., host-state
3624 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3625 */
3626static void vmx_set_constant_host_state(void)
3627{
3628 u32 low32, high32;
3629 unsigned long tmpl;
3630 struct desc_ptr dt;
3631
3632 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3633 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3634 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3635
3636 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3637 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3638 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3639 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3640 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3641
3642 native_store_idt(&dt);
3643 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3644
3645 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3646 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3647
3648 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3649 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3650 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3651 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3652
3653 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3654 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3655 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3656 }
3657}
3658
bf8179a0
NHE		 3659static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3660{
3661 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3662 if (enable_ept)
3663 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3664 if (is_guest_mode(&vmx->vcpu))
3665 vmx->vcpu.arch.cr4_guest_owned_bits &=
3666 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3667 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3668}
3669
3670static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3671{
3672 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3673 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3674 exec_control &= ~CPU_BASED_TPR_SHADOW;
3675#ifdef CONFIG_X86_64
3676 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3677 CPU_BASED_CR8_LOAD_EXITING;
3678#endif
3679 }
3680 if (!enable_ept)
3681 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3682 CPU_BASED_CR3_LOAD_EXITING |
3683 CPU_BASED_INVLPG_EXITING;
3684 return exec_control;
3685}
3686
3687static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3688{
3689 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3690 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3691 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3692 if (vmx->vpid == 0)
3693 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3694 if (!enable_ept) {
3695 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3696 enable_unrestricted_guest = 0;
3697 }
3698 if (!enable_unrestricted_guest)
3699 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3700 if (!ple_gap)
3701 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3702 return exec_control;
3703}
3704
ce88decf
XG		 3705static void ept_set_mmio_spte_mask(void)
3706{
3707 /*
3708 * EPT Misconfigurations can be generated if the value of bits 2:0
3709 * of an EPT paging-structure entry is 110b (write/execute).
3710 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3711 * spte.
3712 */
3713 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3714}
3715
6aa8b732
AK		 3716/*
3717 * Sets up the vmcs for emulated real mode.
3718 */
8b9cf98c 3719static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3720{
2e4ce7f5 3721#ifdef CONFIG_X86_64
6aa8b732 3722 unsigned long a;
2e4ce7f5 3723#endif
6aa8b732 3724 int i;
6aa8b732 3725
6aa8b732 3726 /* I/O */
3e7c73e9
AK		 3727 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3728 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3729
25c5f225 3730 if (cpu_has_vmx_msr_bitmap())
5897297b 3731 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3732
6aa8b732
AK		 3733 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3734
6aa8b732 3735 /* Control */
1c3d14fe
YS		 3736 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3737 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3738
bf8179a0 3739 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3740
83ff3b9d 3741 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3742 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3743 vmx_secondary_exec_control(vmx));
83ff3b9d 3744 }
f78e0e2e 3745
4b8d54f9
ZE		 3746 if (ple_gap) {
3747 vmcs_write32(PLE_GAP, ple_gap);
3748 vmcs_write32(PLE_WINDOW, ple_window);
3749 }
3750
c3707958
XG		 3751 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3752 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3753 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3754
9581d442
AK		 3755 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3756 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3757 vmx_set_constant_host_state();
05b3e0c2 3758#ifdef CONFIG_X86_64
6aa8b732
AK		 3759 rdmsrl(MSR_FS_BASE, a);
3760 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3761 rdmsrl(MSR_GS_BASE, a);
3762 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3763#else
3764 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3765 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3766#endif
3767
2cc51560
ED		 3768 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3769 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3770 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3771 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3772 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3773
468d472f 3774 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3775 u32 msr_low, msr_high;
3776 u64 host_pat;
468d472f
SY		 3777 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3778 host_pat = msr_low | ((u64) msr_high << 32);
3779 /* Write the default value follow host pat */
3780 vmcs_write64(GUEST_IA32_PAT, host_pat);
3781 /* Keep arch.pat sync with GUEST_IA32_PAT */
3782 vmx->vcpu.arch.pat = host_pat;
3783 }
3784
6aa8b732
AK		 3785 for (i = 0; i < NR_VMX_MSR; ++i) {
3786 u32 index = vmx_msr_index[i];
3787 u32 data_low, data_high;
a2fa3e9f 3788 int j = vmx->nmsrs;
6aa8b732
AK		 3789
3790 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3791 continue;
432bd6cb
AK		 3792 if (wrmsr_safe(index, data_low, data_high) < 0)
3793 continue;
26bb0981
AK		 3794 vmx->guest_msrs[j].index = i;
3795 vmx->guest_msrs[j].data = 0;
d5696725 3796 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3797 ++vmx->nmsrs;
6aa8b732 3798 }
6aa8b732 3799
1c3d14fe 3800 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3801
3802 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3803 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3804
e00c8cf2 3805 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3806 set_cr4_guest_host_mask(vmx);
e00c8cf2 3807
99e3e30a 3808 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3809
e00c8cf2
AK		 3810 return 0;
3811}
3812
3813static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3814{
3815 struct vcpu_vmx *vmx = to_vmx(vcpu);
3816 u64 msr;
4b9d3a04 3817 int ret;
e00c8cf2 3818
5fdbf976 3819 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3820
7ffd92c5 3821 vmx->rmode.vm86_active = 0;
e00c8cf2 3822
3b86cd99
JK		 3823 vmx->soft_vnmi_blocked = 0;
3824
ad312c7c 3825 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3826 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3827 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3828 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3829 msr |= MSR_IA32_APICBASE_BSP;
3830 kvm_set_apic_base(&vmx->vcpu, msr);
3831
10ab25cd
JK		 3832 ret = fx_init(&vmx->vcpu);
3833 if (ret != 0)
3834 goto out;
e00c8cf2 3835
2fb92db1
AK		 3836 vmx_segment_cache_clear(vmx);
3837
5706be0d 3838 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3839 /*
3840 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3841 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3842 */
c5af89b6 3843 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3844 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3845 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3846 } else {
ad312c7c
ZX		 3847 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3848 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3849 }
e00c8cf2
AK		 3850
3851 seg_setup(VCPU_SREG_DS);
3852 seg_setup(VCPU_SREG_ES);
3853 seg_setup(VCPU_SREG_FS);
3854 seg_setup(VCPU_SREG_GS);
3855 seg_setup(VCPU_SREG_SS);
3856
3857 vmcs_write16(GUEST_TR_SELECTOR, 0);
3858 vmcs_writel(GUEST_TR_BASE, 0);
3859 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3860 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3861
3862 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3863 vmcs_writel(GUEST_LDTR_BASE, 0);
3864 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3865 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3866
3867 vmcs_write32(GUEST_SYSENTER_CS, 0);
3868 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3869 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3870
3871 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3872 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3873 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3874 else
5fdbf976
MT		 3875 kvm_rip_write(vcpu, 0);
3876 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3877
e00c8cf2
AK		 3878 vmcs_writel(GUEST_DR7, 0x400);
3879
3880 vmcs_writel(GUEST_GDTR_BASE, 0);
3881 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3882
3883 vmcs_writel(GUEST_IDTR_BASE, 0);
3884 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3885
443381a8 3886 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3887 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3888 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3889
e00c8cf2
AK		 3890 /* Special registers */
3891 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3892
3893 setup_msrs(vmx);
3894
6aa8b732
AK		 3895 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3896
f78e0e2e
SY		 3897 if (cpu_has_vmx_tpr_shadow()) {
3898 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3899 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3900 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3901 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3902 vmcs_write32(TPR_THRESHOLD, 0);
3903 }
3904
3905 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3906 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3907 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3908
2384d2b3
SY		 3909 if (vmx->vpid != 0)
3910 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3911
fa40052c 3912 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3913 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3914 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3915 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3916 vmx_fpu_activate(&vmx->vcpu);
3917 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3918
b9d762fa 3919 vpid_sync_context(vmx);
2384d2b3 3920
3200f405 3921 ret = 0;
6aa8b732 3922
a89a8fb9
MG		 3923 /* HACK: Don't enable emulation on guest boot/reset */
3924 vmx->emulation_required = 0;
3925
6aa8b732
AK		 3926out:
3927 return ret;
3928}
3929
b6f1250e
NHE		 3930/*
3931 * In nested virtualization, check if L1 asked to exit on external interrupts.
3932 * For most existing hypervisors, this will always return true.
3933 */
3934static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3935{
3936 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3937 PIN_BASED_EXT_INTR_MASK;
3938}
3939
3b86cd99
JK		 3940static void enable_irq_window(struct kvm_vcpu *vcpu)
3941{
3942 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3943 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3944 /* We can get here when nested_run_pending caused
3945 * vmx_interrupt_allowed() to return false. In this case, do
3946 * nothing - the interrupt will be injected later.
3947 */
3948 return;
3b86cd99
JK		 3949
3950 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3951 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3952 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3953}
3954
3955static void enable_nmi_window(struct kvm_vcpu *vcpu)
3956{
3957 u32 cpu_based_vm_exec_control;
3958
3959 if (!cpu_has_virtual_nmis()) {
3960 enable_irq_window(vcpu);
3961 return;
3962 }
3963
30bd0c4c
AK		 3964 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3965 enable_irq_window(vcpu);
3966 return;
3967 }
3b86cd99
JK		 3968 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3969 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3970 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3971}
3972
66fd3f7f 3973static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3974{
9c8cba37 3975 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3976 uint32_t intr;
3977 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3978
229456fc 3979 trace_kvm_inj_virq(irq);
2714d1d3 3980
fa89a817 3981 ++vcpu->stat.irq_injections;
7ffd92c5 3982 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3983 int inc_eip = 0;
3984 if (vcpu->arch.interrupt.soft)
3985 inc_eip = vcpu->arch.event_exit_inst_len;
3986 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3987 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3988 return;
3989 }
66fd3f7f
GN		 3990 intr = irq | INTR_INFO_VALID_MASK;
3991 if (vcpu->arch.interrupt.soft) {
3992 intr |= INTR_TYPE_SOFT_INTR;
3993 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3994 vmx->vcpu.arch.event_exit_inst_len);
3995 } else
3996 intr |= INTR_TYPE_EXT_INTR;
3997 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3998 vmx_clear_hlt(vcpu);
85f455f7
ED		 3999}
4000
f08864b4
SY		 4001static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4002{
66a5a347
JK		 4003 struct vcpu_vmx *vmx = to_vmx(vcpu);
4004
0b6ac343
NHE		 4005 if (is_guest_mode(vcpu))
4006 return;
4007
3b86cd99
JK		 4008 if (!cpu_has_virtual_nmis()) {
4009 /*
4010 * Tracking the NMI-blocked state in software is built upon
4011 * finding the next open IRQ window. This, in turn, depends on
4012 * well-behaving guests: They have to keep IRQs disabled at
4013 * least as long as the NMI handler runs. Otherwise we may
4014 * cause NMI nesting, maybe breaking the guest. But as this is
4015 * highly unlikely, we can live with the residual risk.
4016 */
4017 vmx->soft_vnmi_blocked = 1;
4018 vmx->vnmi_blocked_time = 0;
4019 }
4020
487b391d 4021 ++vcpu->stat.nmi_injections;
9d58b931 4022 vmx->nmi_known_unmasked = false;
7ffd92c5 4023 if (vmx->rmode.vm86_active) {
71f9833b 4024 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4025 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4026 return;
4027 }
f08864b4
SY		 4028 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4029 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 4030 vmx_clear_hlt(vcpu);
f08864b4
SY		 4031}
4032
c4282df9 4033static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4034{
3b86cd99 4035 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4036 return 0;
33f089ca 4037
c4282df9 4038 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4039 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4040 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4041}
4042
3cfc3092
JK		 4043static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4044{
4045 if (!cpu_has_virtual_nmis())
4046 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4047 if (to_vmx(vcpu)->nmi_known_unmasked)
4048 return false;
c332c83a 4049 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4050}
4051
4052static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4053{
4054 struct vcpu_vmx *vmx = to_vmx(vcpu);
4055
4056 if (!cpu_has_virtual_nmis()) {
4057 if (vmx->soft_vnmi_blocked != masked) {
4058 vmx->soft_vnmi_blocked = masked;
4059 vmx->vnmi_blocked_time = 0;
4060 }
4061 } else {
9d58b931 4062 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4063 if (masked)
4064 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4065 GUEST_INTR_STATE_NMI);
4066 else
4067 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4068 GUEST_INTR_STATE_NMI);
4069 }
4070}
4071
78646121
GN		 4072static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4073{
b6f1250e
NHE		 4074 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4075 struct vmcs12 *vmcs12;
4076 if (to_vmx(vcpu)->nested.nested_run_pending)
4077 return 0;
4078 nested_vmx_vmexit(vcpu);
4079 vmcs12 = get_vmcs12(vcpu);
4080 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4081 vmcs12->vm_exit_intr_info = 0;
4082 /* fall through to normal code, but now in L1, not L2 */
4083 }
4084
c4282df9
GN		 4085 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4086 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4087 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4088}
4089
cbc94022
IE		 4090static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4091{
4092 int ret;
4093 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4094 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4095 .guest_phys_addr = addr,
4096 .memory_size = PAGE_SIZE * 3,
4097 .flags = 0,
4098 };
4099
4100 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4101 if (ret)
4102 return ret;
bfc6d222 4103 kvm->arch.tss_addr = addr;
93ea5388
GN		 4104 if (!init_rmode_tss(kvm))
4105 return -ENOMEM;
4106
cbc94022
IE		 4107 return 0;
4108}
4109
6aa8b732
AK		 4110static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4111 int vec, u32 err_code)
4112{
b3f37707
NK		 4113 /*
4114 * Instruction with address size override prefix opcode 0x67
4115 * Cause the #SS fault with 0 error code in VM86 mode.
4116 */
4117 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4118 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4119 return 1;
77ab6db0
JK		 4120 /*
4121 * Forward all other exceptions that are valid in real mode.
4122 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4123 * the required debugging infrastructure rework.
4124 */
4125 switch (vec) {
77ab6db0 4126 case DB_VECTOR:
d0bfb940
JK		 4127 if (vcpu->guest_debug &
4128 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4129 return 0;
4130 kvm_queue_exception(vcpu, vec);
4131 return 1;
77ab6db0 4132 case BP_VECTOR:
c573cd22
JK		 4133 /*
4134 * Update instruction length as we may reinject the exception
4135 * from user space while in guest debugging mode.
4136 */
4137 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4138 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4139 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4140 return 0;
4141 /* fall through */
4142 case DE_VECTOR:
77ab6db0
JK		 4143 case OF_VECTOR:
4144 case BR_VECTOR:
4145 case UD_VECTOR:
4146 case DF_VECTOR:
4147 case SS_VECTOR:
4148 case GP_VECTOR:
4149 case MF_VECTOR:
4150 kvm_queue_exception(vcpu, vec);
4151 return 1;
4152 }
6aa8b732
AK		 4153 return 0;
4154}
4155
a0861c02
AK		 4156/*
4157 * Trigger machine check on the host. We assume all the MSRs are already set up
4158 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4159 * We pass a fake environment to the machine check handler because we want
4160 * the guest to be always treated like user space, no matter what context
4161 * it used internally.
4162 */
4163static void kvm_machine_check(void)
4164{
4165#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4166 struct pt_regs regs = {
4167 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4168 .flags = X86_EFLAGS_IF,
4169 };
4170
4171 do_machine_check(&regs, 0);
4172#endif
4173}
4174
851ba692 4175static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4176{
4177 /* already handled by vcpu_run */
4178 return 1;
4179}
4180
851ba692 4181static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4182{
1155f76a 4183 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4184 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4185 u32 intr_info, ex_no, error_code;
42dbaa5a 4186 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4187 u32 vect_info;
4188 enum emulation_result er;
4189
1155f76a 4190 vect_info = vmx->idt_vectoring_info;
88786475 4191 intr_info = vmx->exit_intr_info;
6aa8b732 4192
a0861c02 4193 if (is_machine_check(intr_info))
851ba692 4194 return handle_machine_check(vcpu);
a0861c02 4195
6aa8b732 4196 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4197 !is_page_fault(intr_info)) {
4198 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4199 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4200 vcpu->run->internal.ndata = 2;
4201 vcpu->run->internal.data[0] = vect_info;
4202 vcpu->run->internal.data[1] = intr_info;
4203 return 0;
4204 }
6aa8b732 4205
e4a41889 4206 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4207 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4208
4209 if (is_no_device(intr_info)) {
5fd86fcf 4210 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4211 return 1;
4212 }
4213
7aa81cc0 4214 if (is_invalid_opcode(intr_info)) {
51d8b661 4215 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4216 if (er != EMULATE_DONE)
7ee5d940 4217 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4218 return 1;
4219 }
4220
6aa8b732 4221 error_code = 0;
2e11384c 4222 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4223 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4224 if (is_page_fault(intr_info)) {
1439442c 4225 /* EPT won't cause page fault directly */
cf3ace79 4226 BUG_ON(enable_ept);
6aa8b732 4227 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4228 trace_kvm_page_fault(cr2, error_code);
4229
3298b75c 4230 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4231 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4232 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4233 }
4234
7ffd92c5 4235 if (vmx->rmode.vm86_active &&
6aa8b732 4236 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4237 error_code)) {
ad312c7c
ZX		 4238 if (vcpu->arch.halt_request) {
4239 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4240 return kvm_emulate_halt(vcpu);
4241 }
6aa8b732 4242 return 1;
72d6e5a0 4243 }
6aa8b732 4244
d0bfb940 4245 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4246 switch (ex_no) {
4247 case DB_VECTOR:
4248 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4249 if (!(vcpu->guest_debug &
4250 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4251 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4252 kvm_queue_exception(vcpu, DB_VECTOR);
4253 return 1;
4254 }
4255 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4256 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4257 /* fall through */
4258 case BP_VECTOR:
c573cd22
JK		 4259 /*
4260 * Update instruction length as we may reinject #BP from
4261 * user space while in guest debugging mode. Reading it for
4262 * #DB as well causes no harm, it is not used in that case.
4263 */
4264 vmx->vcpu.arch.event_exit_inst_len =
4265 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4266 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4267 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4268 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4269 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4270 break;
4271 default:
d0bfb940
JK		 4272 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4273 kvm_run->ex.exception = ex_no;
4274 kvm_run->ex.error_code = error_code;
42dbaa5a 4275 break;
6aa8b732 4276 }
6aa8b732
AK		 4277 return 0;
4278}
4279
851ba692 4280static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4281{
1165f5fe 4282 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4283 return 1;
4284}
4285
851ba692 4286static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4287{
851ba692 4288 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4289 return 0;
4290}
6aa8b732 4291
851ba692 4292static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4293{
bfdaab09 4294 unsigned long exit_qualification;
34c33d16 4295 int size, in, string;
039576c0 4296 unsigned port;
6aa8b732 4297
bfdaab09 4298 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4299 string = (exit_qualification & 16) != 0;
cf8f70bf 4300 in = (exit_qualification & 8) != 0;
e70669ab 4301
cf8f70bf 4302 ++vcpu->stat.io_exits;
e70669ab 4303
cf8f70bf 4304 if (string || in)
51d8b661 4305 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4306
cf8f70bf
GN		 4307 port = exit_qualification >> 16;
4308 size = (exit_qualification & 7) + 1;
e93f36bc 4309 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4310
4311 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4312}
4313
102d8325
IM		 4314static void
4315vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4316{
4317 /*
4318 * Patch in the VMCALL instruction:
4319 */
4320 hypercall[0] = 0x0f;
4321 hypercall[1] = 0x01;
4322 hypercall[2] = 0xc1;
102d8325
IM		 4323}
4324
eeadf9e7
NHE		 4325/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4326static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4327{
4328 if (to_vmx(vcpu)->nested.vmxon &&
4329 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4330 return 1;
4331
4332 if (is_guest_mode(vcpu)) {
4333 /*
4334 * We get here when L2 changed cr0 in a way that did not change
4335 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4336 * but did change L0 shadowed bits. This can currently happen
4337 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4338 * loading) while pretending to allow the guest to change it.
4339 */
4340 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4341 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4342 return 1;
4343 vmcs_writel(CR0_READ_SHADOW, val);
4344 return 0;
4345 } else
4346 return kvm_set_cr0(vcpu, val);
4347}
4348
4349static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4350{
4351 if (is_guest_mode(vcpu)) {
4352 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4353 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4354 return 1;
4355 vmcs_writel(CR4_READ_SHADOW, val);
4356 return 0;
4357 } else
4358 return kvm_set_cr4(vcpu, val);
4359}
4360
4361/* called to set cr0 as approriate for clts instruction exit. */
4362static void handle_clts(struct kvm_vcpu *vcpu)
4363{
4364 if (is_guest_mode(vcpu)) {
4365 /*
4366 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4367 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4368 * just pretend it's off (also in arch.cr0 for fpu_activate).
4369 */
4370 vmcs_writel(CR0_READ_SHADOW,
4371 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4372 vcpu->arch.cr0 &= ~X86_CR0_TS;
4373 } else
4374 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4375}
4376
851ba692 4377static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4378{
229456fc 4379 unsigned long exit_qualification, val;
6aa8b732
AK		 4380 int cr;
4381 int reg;
49a9b07e 4382 int err;
6aa8b732 4383
bfdaab09 4384 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4385 cr = exit_qualification & 15;
4386 reg = (exit_qualification >> 8) & 15;
4387 switch ((exit_qualification >> 4) & 3) {
4388 case 0: /* mov to cr */
229456fc
MT		 4389 val = kvm_register_read(vcpu, reg);
4390 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4391 switch (cr) {
4392 case 0:
eeadf9e7 4393 err = handle_set_cr0(vcpu, val);
db8fcefa 4394 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4395 return 1;
4396 case 3:
2390218b 4397 err = kvm_set_cr3(vcpu, val);
db8fcefa 4398 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4399 return 1;
4400 case 4:
eeadf9e7 4401 err = handle_set_cr4(vcpu, val);
db8fcefa 4402 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4403 return 1;
0a5fff19
GN		 4404 case 8: {
4405 u8 cr8_prev = kvm_get_cr8(vcpu);
4406 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4407 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4408 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4409 if (irqchip_in_kernel(vcpu->kvm))
4410 return 1;
4411 if (cr8_prev <= cr8)
4412 return 1;
851ba692 4413 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4414 return 0;
4415 }
6aa8b732
AK		 4416 };
4417 break;
25c4c276 4418 case 2: /* clts */
eeadf9e7 4419 handle_clts(vcpu);
4d4ec087 4420 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4421 skip_emulated_instruction(vcpu);
6b52d186 4422 vmx_fpu_activate(vcpu);
25c4c276 4423 return 1;
6aa8b732
AK		 4424 case 1: /*mov from cr*/
4425 switch (cr) {
4426 case 3:
9f8fe504
AK		 4427 val = kvm_read_cr3(vcpu);
4428 kvm_register_write(vcpu, reg, val);
4429 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4430 skip_emulated_instruction(vcpu);
4431 return 1;
4432 case 8:
229456fc
MT		 4433 val = kvm_get_cr8(vcpu);
4434 kvm_register_write(vcpu, reg, val);
4435 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4436 skip_emulated_instruction(vcpu);
4437 return 1;
4438 }
4439 break;
4440 case 3: /* lmsw */
a1f83a74 4441 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4442 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4443 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4444
4445 skip_emulated_instruction(vcpu);
4446 return 1;
4447 default:
4448 break;
4449 }
851ba692 4450 vcpu->run->exit_reason = 0;
f0242478 4451 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4452 (int)(exit_qualification >> 4) & 3, cr);
4453 return 0;
4454}
4455
851ba692 4456static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4457{
bfdaab09 4458 unsigned long exit_qualification;
6aa8b732
AK		 4459 int dr, reg;
4460
f2483415 4461 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4462 if (!kvm_require_cpl(vcpu, 0))
4463 return 1;
42dbaa5a
JK		 4464 dr = vmcs_readl(GUEST_DR7);
4465 if (dr & DR7_GD) {
4466 /*
4467 * As the vm-exit takes precedence over the debug trap, we
4468 * need to emulate the latter, either for the host or the
4469 * guest debugging itself.
4470 */
4471 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4472 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4473 vcpu->run->debug.arch.dr7 = dr;
4474 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4475 vmcs_readl(GUEST_CS_BASE) +
4476 vmcs_readl(GUEST_RIP);
851ba692
AK		 4477 vcpu->run->debug.arch.exception = DB_VECTOR;
4478 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4479 return 0;
4480 } else {
4481 vcpu->arch.dr7 &= ~DR7_GD;
4482 vcpu->arch.dr6 |= DR6_BD;
4483 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4484 kvm_queue_exception(vcpu, DB_VECTOR);
4485 return 1;
4486 }
4487 }
4488
bfdaab09 4489 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4490 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4491 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4492 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4493 unsigned long val;
4494 if (!kvm_get_dr(vcpu, dr, &val))
4495 kvm_register_write(vcpu, reg, val);
4496 } else
4497 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4498 skip_emulated_instruction(vcpu);
4499 return 1;
4500}
4501
020df079
GN		 4502static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4503{
4504 vmcs_writel(GUEST_DR7, val);
4505}
4506
851ba692 4507static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4508{
06465c5a
AK		 4509 kvm_emulate_cpuid(vcpu);
4510 return 1;
6aa8b732
AK		 4511}
4512
851ba692 4513static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4514{
ad312c7c 4515 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4516 u64 data;
4517
4518 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4519 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4520 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4521 return 1;
4522 }
4523
229456fc 4524 trace_kvm_msr_read(ecx, data);
2714d1d3 4525
6aa8b732 4526 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4527 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4528 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4529 skip_emulated_instruction(vcpu);
4530 return 1;
4531}
4532
851ba692 4533static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4534{
ad312c7c
ZX		 4535 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4536 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4537 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4538
4539 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4540 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4541 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4542 return 1;
4543 }
4544
59200273 4545 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4546 skip_emulated_instruction(vcpu);
4547 return 1;
4548}
4549
851ba692 4550static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4551{
3842d135 4552 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4553 return 1;
4554}
4555
851ba692 4556static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4557{
85f455f7
ED		 4558 u32 cpu_based_vm_exec_control;
4559
4560 /* clear pending irq */
4561 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4562 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4563 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4564
3842d135
AK		 4565 kvm_make_request(KVM_REQ_EVENT, vcpu);
4566
a26bf12a 4567 ++vcpu->stat.irq_window_exits;
2714d1d3 4568
c1150d8c
DL		 4569 /*
4570 * If the user space waits to inject interrupts, exit as soon as
4571 * possible
4572 */
8061823a 4573 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4574 vcpu->run->request_interrupt_window &&
8061823a 4575 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4576 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4577 return 0;
4578 }
6aa8b732
AK		 4579 return 1;
4580}
4581
851ba692 4582static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4583{
4584 skip_emulated_instruction(vcpu);
d3bef15f 4585 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4586}
4587
851ba692 4588static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4589{
510043da 4590 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4591 kvm_emulate_hypercall(vcpu);
4592 return 1;
c21415e8
IM		 4593}
4594
ec25d5e6
GN		 4595static int handle_invd(struct kvm_vcpu *vcpu)
4596{
51d8b661 4597 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4598}
4599
851ba692 4600static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4601{
f9c617f6 4602 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4603
4604 kvm_mmu_invlpg(vcpu, exit_qualification);
4605 skip_emulated_instruction(vcpu);
4606 return 1;
4607}
4608
851ba692 4609static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4610{
4611 skip_emulated_instruction(vcpu);
f5f48ee1 4612 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4613 return 1;
4614}
4615
2acf923e
DC		 4616static int handle_xsetbv(struct kvm_vcpu *vcpu)
4617{
4618 u64 new_bv = kvm_read_edx_eax(vcpu);
4619 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4620
4621 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4622 skip_emulated_instruction(vcpu);
4623 return 1;
4624}
4625
851ba692 4626static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4627{
58fbbf26
KT		 4628 if (likely(fasteoi)) {
4629 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4630 int access_type, offset;
4631
4632 access_type = exit_qualification & APIC_ACCESS_TYPE;
4633 offset = exit_qualification & APIC_ACCESS_OFFSET;
4634 /*
4635 * Sane guest uses MOV to write EOI, with written value
4636 * not cared. So make a short-circuit here by avoiding
4637 * heavy instruction emulation.
4638 */
4639 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4640 (offset == APIC_EOI)) {
4641 kvm_lapic_set_eoi(vcpu);
4642 skip_emulated_instruction(vcpu);
4643 return 1;
4644 }
4645 }
51d8b661 4646 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4647}
4648
851ba692 4649static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4650{
60637aac 4651 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4652 unsigned long exit_qualification;
e269fb21
JK		 4653 bool has_error_code = false;
4654 u32 error_code = 0;
37817f29 4655 u16 tss_selector;
64a7ec06
GN		 4656 int reason, type, idt_v;
4657
4658 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4659 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4660
4661 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4662
4663 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4664 if (reason == TASK_SWITCH_GATE && idt_v) {
4665 switch (type) {
4666 case INTR_TYPE_NMI_INTR:
4667 vcpu->arch.nmi_injected = false;
654f06fc 4668 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4669 break;
4670 case INTR_TYPE_EXT_INTR:
66fd3f7f 4671 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4672 kvm_clear_interrupt_queue(vcpu);
4673 break;
4674 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4675 if (vmx->idt_vectoring_info &
4676 VECTORING_INFO_DELIVER_CODE_MASK) {
4677 has_error_code = true;
4678 error_code =
4679 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4680 }
4681 /* fall through */
64a7ec06
GN		 4682 case INTR_TYPE_SOFT_EXCEPTION:
4683 kvm_clear_exception_queue(vcpu);
4684 break;
4685 default:
4686 break;
4687 }
60637aac 4688 }
37817f29
IE		 4689 tss_selector = exit_qualification;
4690
64a7ec06
GN		 4691 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4692 type != INTR_TYPE_EXT_INTR &&
4693 type != INTR_TYPE_NMI_INTR))
4694 skip_emulated_instruction(vcpu);
4695
acb54517
GN		 4696 if (kvm_task_switch(vcpu, tss_selector, reason,
4697 has_error_code, error_code) == EMULATE_FAIL) {
4698 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4699 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4700 vcpu->run->internal.ndata = 0;
42dbaa5a 4701 return 0;
acb54517 4702 }
42dbaa5a
JK		 4703
4704 /* clear all local breakpoint enable flags */
4705 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4706
4707 /*
4708 * TODO: What about debug traps on tss switch?
4709 * Are we supposed to inject them and update dr6?
4710 */
4711
4712 return 1;
37817f29
IE		 4713}
4714
851ba692 4715static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4716{
f9c617f6 4717 unsigned long exit_qualification;
1439442c 4718 gpa_t gpa;
1439442c 4719 int gla_validity;
1439442c 4720
f9c617f6 4721 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4722
4723 if (exit_qualification & (1 << 6)) {
4724 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4725 return -EINVAL;
1439442c
SY		 4726 }
4727
4728 gla_validity = (exit_qualification >> 7) & 0x3;
4729 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4730 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4731 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4732 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4733 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4734 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4735 (long unsigned int)exit_qualification);
851ba692
AK		 4736 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4737 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4738 return 0;
1439442c
SY		 4739 }
4740
4741 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4742 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4743 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4744}
4745
68f89400
MT		 4746static u64 ept_rsvd_mask(u64 spte, int level)
4747{
4748 int i;
4749 u64 mask = 0;
4750
4751 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4752 mask |= (1ULL << i);
4753
4754 if (level > 2)
4755 /* bits 7:3 reserved */
4756 mask |= 0xf8;
4757 else if (level == 2) {
4758 if (spte & (1ULL << 7))
4759 /* 2MB ref, bits 20:12 reserved */
4760 mask |= 0x1ff000;
4761 else
4762 /* bits 6:3 reserved */
4763 mask |= 0x78;
4764 }
4765
4766 return mask;
4767}
4768
4769static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4770 int level)
4771{
4772 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4773
4774 /* 010b (write-only) */
4775 WARN_ON((spte & 0x7) == 0x2);
4776
4777 /* 110b (write/execute) */
4778 WARN_ON((spte & 0x7) == 0x6);
4779
4780 /* 100b (execute-only) and value not supported by logical processor */
4781 if (!cpu_has_vmx_ept_execute_only())
4782 WARN_ON((spte & 0x7) == 0x4);
4783
4784 /* not 000b */
4785 if ((spte & 0x7)) {
4786 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4787
4788 if (rsvd_bits != 0) {
4789 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4790 __func__, rsvd_bits);
4791 WARN_ON(1);
4792 }
4793
4794 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4795 u64 ept_mem_type = (spte & 0x38) >> 3;
4796
4797 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4798 ept_mem_type == 7) {
4799 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4800 __func__, ept_mem_type);
4801 WARN_ON(1);
4802 }
4803 }
4804 }
4805}
4806
851ba692 4807static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4808{
4809 u64 sptes[4];
ce88decf 4810 int nr_sptes, i, ret;
68f89400
MT		 4811 gpa_t gpa;
4812
4813 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4814
ce88decf
XG		 4815 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4816 if (likely(ret == 1))
4817 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4818 EMULATE_DONE;
4819 if (unlikely(!ret))
4820 return 1;
4821
4822 /* It is the real ept misconfig */
68f89400
MT		 4823 printk(KERN_ERR "EPT: Misconfiguration.\n");
4824 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4825
4826 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4827
4828 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4829 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4830
851ba692
AK		 4831 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4832 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4833
4834 return 0;
4835}
4836
851ba692 4837static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4838{
4839 u32 cpu_based_vm_exec_control;
4840
4841 /* clear pending NMI */
4842 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4843 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4845 ++vcpu->stat.nmi_window_exits;
3842d135 4846 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4847
4848 return 1;
4849}
4850
80ced186 4851static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4852{
8b3079a5
AK		 4853 struct vcpu_vmx *vmx = to_vmx(vcpu);
4854 enum emulation_result err = EMULATE_DONE;
80ced186 4855 int ret = 1;
49e9d557
AK		 4856 u32 cpu_exec_ctrl;
4857 bool intr_window_requested;
4858
4859 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4860 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4861
4862 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4863 if (intr_window_requested
4864 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4865 return handle_interrupt_window(&vmx->vcpu);
4866
51d8b661 4867 err = emulate_instruction(vcpu, 0);
ea953ef0 4868
80ced186
MG		 4869 if (err == EMULATE_DO_MMIO) {
4870 ret = 0;
4871 goto out;
4872 }
1d5a4d9b 4873
6d77dbfc
GN		 4874 if (err != EMULATE_DONE)
4875 return 0;
ea953ef0
MG		 4876
4877 if (signal_pending(current))
80ced186 4878 goto out;
ea953ef0
MG		 4879 if (need_resched())
4880 schedule();
4881 }
4882
80ced186
MG		 4883 vmx->emulation_required = 0;
4884out:
4885 return ret;
ea953ef0
MG		 4886}
4887
4b8d54f9
ZE		 4888/*
4889 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4890 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4891 */
9fb41ba8 4892static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4893{
4894 skip_emulated_instruction(vcpu);
4895 kvm_vcpu_on_spin(vcpu);
4896
4897 return 1;
4898}
4899
59708670
SY		 4900static int handle_invalid_op(struct kvm_vcpu *vcpu)
4901{
4902 kvm_queue_exception(vcpu, UD_VECTOR);
4903 return 1;
4904}
4905
ff2f6fe9
NHE		 4906/*
4907 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4908 * We could reuse a single VMCS for all the L2 guests, but we also want the
4909 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4910 * allows keeping them loaded on the processor, and in the future will allow
4911 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4912 * every entry if they never change.
4913 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4914 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4915 *
4916 * The following functions allocate and free a vmcs02 in this pool.
4917 */
4918
4919/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4920static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4921{
4922 struct vmcs02_list *item;
4923 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4924 if (item->vmptr == vmx->nested.current_vmptr) {
4925 list_move(&item->list, &vmx->nested.vmcs02_pool);
4926 return &item->vmcs02;
4927 }
4928
4929 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4930 /* Recycle the least recently used VMCS. */
4931 item = list_entry(vmx->nested.vmcs02_pool.prev,
4932 struct vmcs02_list, list);
4933 item->vmptr = vmx->nested.current_vmptr;
4934 list_move(&item->list, &vmx->nested.vmcs02_pool);
4935 return &item->vmcs02;
4936 }
4937
4938 /* Create a new VMCS */
4939 item = (struct vmcs02_list *)
4940 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4941 if (!item)
4942 return NULL;
4943 item->vmcs02.vmcs = alloc_vmcs();
4944 if (!item->vmcs02.vmcs) {
4945 kfree(item);
4946 return NULL;
4947 }
4948 loaded_vmcs_init(&item->vmcs02);
4949 item->vmptr = vmx->nested.current_vmptr;
4950 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4951 vmx->nested.vmcs02_num++;
4952 return &item->vmcs02;
4953}
4954
4955/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4956static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4957{
4958 struct vmcs02_list *item;
4959 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4960 if (item->vmptr == vmptr) {
4961 free_loaded_vmcs(&item->vmcs02);
4962 list_del(&item->list);
4963 kfree(item);
4964 vmx->nested.vmcs02_num--;
4965 return;
4966 }
4967}
4968
4969/*
4970 * Free all VMCSs saved for this vcpu, except the one pointed by
4971 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4972 * currently used, if running L2), and vmcs01 when running L2.
4973 */
4974static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4975{
4976 struct vmcs02_list *item, *n;
4977 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4978 if (vmx->loaded_vmcs != &item->vmcs02)
4979 free_loaded_vmcs(&item->vmcs02);
4980 list_del(&item->list);
4981 kfree(item);
4982 }
4983 vmx->nested.vmcs02_num = 0;
4984
4985 if (vmx->loaded_vmcs != &vmx->vmcs01)
4986 free_loaded_vmcs(&vmx->vmcs01);
4987}
4988
ec378aee
NHE		 4989/*
4990 * Emulate the VMXON instruction.
4991 * Currently, we just remember that VMX is active, and do not save or even
4992 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4993 * do not currently need to store anything in that guest-allocated memory
4994 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4995 * argument is different from the VMXON pointer (which the spec says they do).
4996 */
4997static int handle_vmon(struct kvm_vcpu *vcpu)
4998{
4999 struct kvm_segment cs;
5000 struct vcpu_vmx *vmx = to_vmx(vcpu);
5001
5002 /* The Intel VMX Instruction Reference lists a bunch of bits that
5003 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5004 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5005 * Otherwise, we should fail with #UD. We test these now:
5006 */
5007 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5008 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5009 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5010 kvm_queue_exception(vcpu, UD_VECTOR);
5011 return 1;
5012 }
5013
5014 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5015 if (is_long_mode(vcpu) && !cs.l) {
5016 kvm_queue_exception(vcpu, UD_VECTOR);
5017 return 1;
5018 }
5019
5020 if (vmx_get_cpl(vcpu)) {
5021 kvm_inject_gp(vcpu, 0);
5022 return 1;
5023 }
5024
ff2f6fe9
NHE		 5025 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5026 vmx->nested.vmcs02_num = 0;
5027
ec378aee
NHE		 5028 vmx->nested.vmxon = true;
5029
5030 skip_emulated_instruction(vcpu);
5031 return 1;
5032}
5033
5034/*
5035 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5036 * for running VMX instructions (except VMXON, whose prerequisites are
5037 * slightly different). It also specifies what exception to inject otherwise.
5038 */
5039static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5040{
5041 struct kvm_segment cs;
5042 struct vcpu_vmx *vmx = to_vmx(vcpu);
5043
5044 if (!vmx->nested.vmxon) {
5045 kvm_queue_exception(vcpu, UD_VECTOR);
5046 return 0;
5047 }
5048
5049 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5050 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5051 (is_long_mode(vcpu) && !cs.l)) {
5052 kvm_queue_exception(vcpu, UD_VECTOR);
5053 return 0;
5054 }
5055
5056 if (vmx_get_cpl(vcpu)) {
5057 kvm_inject_gp(vcpu, 0);
5058 return 0;
5059 }
5060
5061 return 1;
5062}
5063
5064/*
5065 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5066 * just stops using VMX.
5067 */
5068static void free_nested(struct vcpu_vmx *vmx)
5069{
5070 if (!vmx->nested.vmxon)
5071 return;
5072 vmx->nested.vmxon = false;
a9d30f33
NHE		 5073 if (vmx->nested.current_vmptr != -1ull) {
5074 kunmap(vmx->nested.current_vmcs12_page);
5075 nested_release_page(vmx->nested.current_vmcs12_page);
5076 vmx->nested.current_vmptr = -1ull;
5077 vmx->nested.current_vmcs12 = NULL;
5078 }
fe3ef05c
NHE		 5079 /* Unpin physical memory we referred to in current vmcs02 */
5080 if (vmx->nested.apic_access_page) {
5081 nested_release_page(vmx->nested.apic_access_page);
5082 vmx->nested.apic_access_page = 0;
5083 }
ff2f6fe9
NHE		 5084
5085 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5086}
5087
5088/* Emulate the VMXOFF instruction */
5089static int handle_vmoff(struct kvm_vcpu *vcpu)
5090{
5091 if (!nested_vmx_check_permission(vcpu))
5092 return 1;
5093 free_nested(to_vmx(vcpu));
5094 skip_emulated_instruction(vcpu);
5095 return 1;
5096}
5097
064aea77
NHE		 5098/*
5099 * Decode the memory-address operand of a vmx instruction, as recorded on an
5100 * exit caused by such an instruction (run by a guest hypervisor).
5101 * On success, returns 0. When the operand is invalid, returns 1 and throws
5102 * #UD or #GP.
5103 */
5104static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5105 unsigned long exit_qualification,
5106 u32 vmx_instruction_info, gva_t *ret)
5107{
5108 /*
5109 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5110 * Execution", on an exit, vmx_instruction_info holds most of the
5111 * addressing components of the operand. Only the displacement part
5112 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5113 * For how an actual address is calculated from all these components,
5114 * refer to Vol. 1, "Operand Addressing".
5115 */
5116 int scaling = vmx_instruction_info & 3;
5117 int addr_size = (vmx_instruction_info >> 7) & 7;
5118 bool is_reg = vmx_instruction_info & (1u << 10);
5119 int seg_reg = (vmx_instruction_info >> 15) & 7;
5120 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5121 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5122 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5123 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5124
5125 if (is_reg) {
5126 kvm_queue_exception(vcpu, UD_VECTOR);
5127 return 1;
5128 }
5129
5130 /* Addr = segment_base + offset */
5131 /* offset = base + [index * scale] + displacement */
5132 *ret = vmx_get_segment_base(vcpu, seg_reg);
5133 if (base_is_valid)
5134 *ret += kvm_register_read(vcpu, base_reg);
5135 if (index_is_valid)
5136 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5137 *ret += exit_qualification; /* holds the displacement */
5138
5139 if (addr_size == 1) /* 32 bit */
5140 *ret &= 0xffffffff;
5141
5142 /*
5143 * TODO: throw #GP (and return 1) in various cases that the VM*
5144 * instructions require it - e.g., offset beyond segment limit,
5145 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5146 * address, and so on. Currently these are not checked.
5147 */
5148 return 0;
5149}
5150
0140caea
NHE		 5151/*
5152 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5153 * set the success or error code of an emulated VMX instruction, as specified
5154 * by Vol 2B, VMX Instruction Reference, "Conventions".
5155 */
5156static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5157{
5158 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5159 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5160 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5161}
5162
5163static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5164{
5165 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5166 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5167 X86_EFLAGS_SF | X86_EFLAGS_OF))
5168 | X86_EFLAGS_CF);
5169}
5170
5171static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5172 u32 vm_instruction_error)
5173{
5174 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5175 /*
5176 * failValid writes the error number to the current VMCS, which
5177 * can't be done there isn't a current VMCS.
5178 */
5179 nested_vmx_failInvalid(vcpu);
5180 return;
5181 }
5182 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5183 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5184 X86_EFLAGS_SF | X86_EFLAGS_OF))
5185 | X86_EFLAGS_ZF);
5186 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5187}
5188
27d6c865
NHE		 5189/* Emulate the VMCLEAR instruction */
5190static int handle_vmclear(struct kvm_vcpu *vcpu)
5191{
5192 struct vcpu_vmx *vmx = to_vmx(vcpu);
5193 gva_t gva;
5194 gpa_t vmptr;
5195 struct vmcs12 *vmcs12;
5196 struct page *page;
5197 struct x86_exception e;
5198
5199 if (!nested_vmx_check_permission(vcpu))
5200 return 1;
5201
5202 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5203 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5204 return 1;
5205
5206 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5207 sizeof(vmptr), &e)) {
5208 kvm_inject_page_fault(vcpu, &e);
5209 return 1;
5210 }
5211
5212 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5213 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5214 skip_emulated_instruction(vcpu);
5215 return 1;
5216 }
5217
5218 if (vmptr == vmx->nested.current_vmptr) {
5219 kunmap(vmx->nested.current_vmcs12_page);
5220 nested_release_page(vmx->nested.current_vmcs12_page);
5221 vmx->nested.current_vmptr = -1ull;
5222 vmx->nested.current_vmcs12 = NULL;
5223 }
5224
5225 page = nested_get_page(vcpu, vmptr);
5226 if (page == NULL) {
5227 /*
5228 * For accurate processor emulation, VMCLEAR beyond available
5229 * physical memory should do nothing at all. However, it is
5230 * possible that a nested vmx bug, not a guest hypervisor bug,
5231 * resulted in this case, so let's shut down before doing any
5232 * more damage:
5233 */
5234 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5235 return 1;
5236 }
5237 vmcs12 = kmap(page);
5238 vmcs12->launch_state = 0;
5239 kunmap(page);
5240 nested_release_page(page);
5241
5242 nested_free_vmcs02(vmx, vmptr);
5243
5244 skip_emulated_instruction(vcpu);
5245 nested_vmx_succeed(vcpu);
5246 return 1;
5247}
5248
cd232ad0
NHE		 5249static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5250
5251/* Emulate the VMLAUNCH instruction */
5252static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5253{
5254 return nested_vmx_run(vcpu, true);
5255}
5256
5257/* Emulate the VMRESUME instruction */
5258static int handle_vmresume(struct kvm_vcpu *vcpu)
5259{
5260
5261 return nested_vmx_run(vcpu, false);
5262}
5263
49f705c5
NHE		 5264enum vmcs_field_type {
5265 VMCS_FIELD_TYPE_U16 = 0,
5266 VMCS_FIELD_TYPE_U64 = 1,
5267 VMCS_FIELD_TYPE_U32 = 2,
5268 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5269};
5270
5271static inline int vmcs_field_type(unsigned long field)
5272{
5273 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5274 return VMCS_FIELD_TYPE_U32;
5275 return (field >> 13) & 0x3 ;
5276}
5277
5278static inline int vmcs_field_readonly(unsigned long field)
5279{
5280 return (((field >> 10) & 0x3) == 1);
5281}
5282
5283/*
5284 * Read a vmcs12 field. Since these can have varying lengths and we return
5285 * one type, we chose the biggest type (u64) and zero-extend the return value
5286 * to that size. Note that the caller, handle_vmread, might need to use only
5287 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5288 * 64-bit fields are to be returned).
5289 */
5290static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5291 unsigned long field, u64 *ret)
5292{
5293 short offset = vmcs_field_to_offset(field);
5294 char *p;
5295
5296 if (offset < 0)
5297 return 0;
5298
5299 p = ((char *)(get_vmcs12(vcpu))) + offset;
5300
5301 switch (vmcs_field_type(field)) {
5302 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5303 *ret = *((natural_width *)p);
5304 return 1;
5305 case VMCS_FIELD_TYPE_U16:
5306 *ret = *((u16 *)p);
5307 return 1;
5308 case VMCS_FIELD_TYPE_U32:
5309 *ret = *((u32 *)p);
5310 return 1;
5311 case VMCS_FIELD_TYPE_U64:
5312 *ret = *((u64 *)p);
5313 return 1;
5314 default:
5315 return 0; /* can never happen. */
5316 }
5317}
5318
5319/*
5320 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5321 * used before) all generate the same failure when it is missing.
5322 */
5323static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5324{
5325 struct vcpu_vmx *vmx = to_vmx(vcpu);
5326 if (vmx->nested.current_vmptr == -1ull) {
5327 nested_vmx_failInvalid(vcpu);
5328 skip_emulated_instruction(vcpu);
5329 return 0;
5330 }
5331 return 1;
5332}
5333
5334static int handle_vmread(struct kvm_vcpu *vcpu)
5335{
5336 unsigned long field;
5337 u64 field_value;
5338 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5339 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5340 gva_t gva = 0;
5341
5342 if (!nested_vmx_check_permission(vcpu) ||
5343 !nested_vmx_check_vmcs12(vcpu))
5344 return 1;
5345
5346 /* Decode instruction info and find the field to read */
5347 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5348 /* Read the field, zero-extended to a u64 field_value */
5349 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5350 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5351 skip_emulated_instruction(vcpu);
5352 return 1;
5353 }
5354 /*
5355 * Now copy part of this value to register or memory, as requested.
5356 * Note that the number of bits actually copied is 32 or 64 depending
5357 * on the guest's mode (32 or 64 bit), not on the given field's length.
5358 */
5359 if (vmx_instruction_info & (1u << 10)) {
5360 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5361 field_value);
5362 } else {
5363 if (get_vmx_mem_address(vcpu, exit_qualification,
5364 vmx_instruction_info, &gva))
5365 return 1;
5366 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5367 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5368 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5369 }
5370
5371 nested_vmx_succeed(vcpu);
5372 skip_emulated_instruction(vcpu);
5373 return 1;
5374}
5375
5376
5377static int handle_vmwrite(struct kvm_vcpu *vcpu)
5378{
5379 unsigned long field;
5380 gva_t gva;
5381 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5382 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5383 char *p;
5384 short offset;
5385 /* The value to write might be 32 or 64 bits, depending on L1's long
5386 * mode, and eventually we need to write that into a field of several
5387 * possible lengths. The code below first zero-extends the value to 64
5388 * bit (field_value), and then copies only the approriate number of
5389 * bits into the vmcs12 field.
5390 */
5391 u64 field_value = 0;
5392 struct x86_exception e;
5393
5394 if (!nested_vmx_check_permission(vcpu) ||
5395 !nested_vmx_check_vmcs12(vcpu))
5396 return 1;
5397
5398 if (vmx_instruction_info & (1u << 10))
5399 field_value = kvm_register_read(vcpu,
5400 (((vmx_instruction_info) >> 3) & 0xf));
5401 else {
5402 if (get_vmx_mem_address(vcpu, exit_qualification,
5403 vmx_instruction_info, &gva))
5404 return 1;
5405 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5406 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5407 kvm_inject_page_fault(vcpu, &e);
5408 return 1;
5409 }
5410 }
5411
5412
5413 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5414 if (vmcs_field_readonly(field)) {
5415 nested_vmx_failValid(vcpu,
5416 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5417 skip_emulated_instruction(vcpu);
5418 return 1;
5419 }
5420
5421 offset = vmcs_field_to_offset(field);
5422 if (offset < 0) {
5423 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5424 skip_emulated_instruction(vcpu);
5425 return 1;
5426 }
5427 p = ((char *) get_vmcs12(vcpu)) + offset;
5428
5429 switch (vmcs_field_type(field)) {
5430 case VMCS_FIELD_TYPE_U16:
5431 *(u16 *)p = field_value;
5432 break;
5433 case VMCS_FIELD_TYPE_U32:
5434 *(u32 *)p = field_value;
5435 break;
5436 case VMCS_FIELD_TYPE_U64:
5437 *(u64 *)p = field_value;
5438 break;
5439 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5440 *(natural_width *)p = field_value;
5441 break;
5442 default:
5443 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5444 skip_emulated_instruction(vcpu);
5445 return 1;
5446 }
5447
5448 nested_vmx_succeed(vcpu);
5449 skip_emulated_instruction(vcpu);
5450 return 1;
5451}
5452
63846663
NHE		 5453/* Emulate the VMPTRLD instruction */
5454static int handle_vmptrld(struct kvm_vcpu *vcpu)
5455{
5456 struct vcpu_vmx *vmx = to_vmx(vcpu);
5457 gva_t gva;
5458 gpa_t vmptr;
5459 struct x86_exception e;
5460
5461 if (!nested_vmx_check_permission(vcpu))
5462 return 1;
5463
5464 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5465 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5466 return 1;
5467
5468 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5469 sizeof(vmptr), &e)) {
5470 kvm_inject_page_fault(vcpu, &e);
5471 return 1;
5472 }
5473
5474 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5475 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5476 skip_emulated_instruction(vcpu);
5477 return 1;
5478 }
5479
5480 if (vmx->nested.current_vmptr != vmptr) {
5481 struct vmcs12 *new_vmcs12;
5482 struct page *page;
5483 page = nested_get_page(vcpu, vmptr);
5484 if (page == NULL) {
5485 nested_vmx_failInvalid(vcpu);
5486 skip_emulated_instruction(vcpu);
5487 return 1;
5488 }
5489 new_vmcs12 = kmap(page);
5490 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5491 kunmap(page);
5492 nested_release_page_clean(page);
5493 nested_vmx_failValid(vcpu,
5494 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5495 skip_emulated_instruction(vcpu);
5496 return 1;
5497 }
5498 if (vmx->nested.current_vmptr != -1ull) {
5499 kunmap(vmx->nested.current_vmcs12_page);
5500 nested_release_page(vmx->nested.current_vmcs12_page);
5501 }
5502
5503 vmx->nested.current_vmptr = vmptr;
5504 vmx->nested.current_vmcs12 = new_vmcs12;
5505 vmx->nested.current_vmcs12_page = page;
5506 }
5507
5508 nested_vmx_succeed(vcpu);
5509 skip_emulated_instruction(vcpu);
5510 return 1;
5511}
5512
6a4d7550
NHE		 5513/* Emulate the VMPTRST instruction */
5514static int handle_vmptrst(struct kvm_vcpu *vcpu)
5515{
5516 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5517 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5518 gva_t vmcs_gva;
5519 struct x86_exception e;
5520
5521 if (!nested_vmx_check_permission(vcpu))
5522 return 1;
5523
5524 if (get_vmx_mem_address(vcpu, exit_qualification,
5525 vmx_instruction_info, &vmcs_gva))
5526 return 1;
5527 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5528 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5529 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5530 sizeof(u64), &e)) {
5531 kvm_inject_page_fault(vcpu, &e);
5532 return 1;
5533 }
5534 nested_vmx_succeed(vcpu);
5535 skip_emulated_instruction(vcpu);
5536 return 1;
5537}
5538
6aa8b732
AK		 5539/*
5540 * The exit handlers return 1 if the exit was handled fully and guest execution
5541 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5542 * to be done to userspace and return 0.
5543 */
851ba692 5544static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5545 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5546 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5547 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5548 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5549 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5550 [EXIT_REASON_CR_ACCESS] = handle_cr,
5551 [EXIT_REASON_DR_ACCESS] = handle_dr,
5552 [EXIT_REASON_CPUID] = handle_cpuid,
5553 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5554 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5555 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5556 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5557 [EXIT_REASON_INVD] = handle_invd,
a7052897 5558 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5559 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5560 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5561 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5562 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5563 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5564 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5565 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5566 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5567 [EXIT_REASON_VMOFF] = handle_vmoff,
5568 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5569 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5570 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5571 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5572 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5573 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5574 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5575 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5576 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5577 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5578 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5579 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5580};
5581
5582static const int kvm_vmx_max_exit_handlers =
50a3485c 5583 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5584
644d711a
NHE		 5585/*
5586 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5587 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5588 * disinterest in the current event (read or write a specific MSR) by using an
5589 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5590 */
5591static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5592 struct vmcs12 *vmcs12, u32 exit_reason)
5593{
5594 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5595 gpa_t bitmap;
5596
5597 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5598 return 1;
5599
5600 /*
5601 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5602 * for the four combinations of read/write and low/high MSR numbers.
5603 * First we need to figure out which of the four to use:
5604 */
5605 bitmap = vmcs12->msr_bitmap;
5606 if (exit_reason == EXIT_REASON_MSR_WRITE)
5607 bitmap += 2048;
5608 if (msr_index >= 0xc0000000) {
5609 msr_index -= 0xc0000000;
5610 bitmap += 1024;
5611 }
5612
5613 /* Then read the msr_index'th bit from this bitmap: */
5614 if (msr_index < 1024*8) {
5615 unsigned char b;
5616 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5617 return 1 & (b >> (msr_index & 7));
5618 } else
5619 return 1; /* let L1 handle the wrong parameter */
5620}
5621
5622/*
5623 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5624 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5625 * intercept (via guest_host_mask etc.) the current event.
5626 */
5627static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5628 struct vmcs12 *vmcs12)
5629{
5630 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5631 int cr = exit_qualification & 15;
5632 int reg = (exit_qualification >> 8) & 15;
5633 unsigned long val = kvm_register_read(vcpu, reg);
5634
5635 switch ((exit_qualification >> 4) & 3) {
5636 case 0: /* mov to cr */
5637 switch (cr) {
5638 case 0:
5639 if (vmcs12->cr0_guest_host_mask &
5640 (val ^ vmcs12->cr0_read_shadow))
5641 return 1;
5642 break;
5643 case 3:
5644 if ((vmcs12->cr3_target_count >= 1 &&
5645 vmcs12->cr3_target_value0 == val) ||
5646 (vmcs12->cr3_target_count >= 2 &&
5647 vmcs12->cr3_target_value1 == val) ||
5648 (vmcs12->cr3_target_count >= 3 &&
5649 vmcs12->cr3_target_value2 == val) ||
5650 (vmcs12->cr3_target_count >= 4 &&
5651 vmcs12->cr3_target_value3 == val))
5652 return 0;
5653 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5654 return 1;
5655 break;
5656 case 4:
5657 if (vmcs12->cr4_guest_host_mask &
5658 (vmcs12->cr4_read_shadow ^ val))
5659 return 1;
5660 break;
5661 case 8:
5662 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5663 return 1;
5664 break;
5665 }
5666 break;
5667 case 2: /* clts */
5668 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5669 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5670 return 1;
5671 break;
5672 case 1: /* mov from cr */
5673 switch (cr) {
5674 case 3:
5675 if (vmcs12->cpu_based_vm_exec_control &
5676 CPU_BASED_CR3_STORE_EXITING)
5677 return 1;
5678 break;
5679 case 8:
5680 if (vmcs12->cpu_based_vm_exec_control &
5681 CPU_BASED_CR8_STORE_EXITING)
5682 return 1;
5683 break;
5684 }
5685 break;
5686 case 3: /* lmsw */
5687 /*
5688 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5689 * cr0. Other attempted changes are ignored, with no exit.
5690 */
5691 if (vmcs12->cr0_guest_host_mask & 0xe &
5692 (val ^ vmcs12->cr0_read_shadow))
5693 return 1;
5694 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5695 !(vmcs12->cr0_read_shadow & 0x1) &&
5696 (val & 0x1))
5697 return 1;
5698 break;
5699 }
5700 return 0;
5701}
5702
5703/*
5704 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5705 * should handle it ourselves in L0 (and then continue L2). Only call this
5706 * when in is_guest_mode (L2).
5707 */
5708static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5709{
5710 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5711 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5712 struct vcpu_vmx *vmx = to_vmx(vcpu);
5713 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5714
5715 if (vmx->nested.nested_run_pending)
5716 return 0;
5717
5718 if (unlikely(vmx->fail)) {
bd80158a
JK		 5719 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5720 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5721 return 1;
5722 }
5723
5724 switch (exit_reason) {
5725 case EXIT_REASON_EXCEPTION_NMI:
5726 if (!is_exception(intr_info))
5727 return 0;
5728 else if (is_page_fault(intr_info))
5729 return enable_ept;
5730 return vmcs12->exception_bitmap &
5731 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5732 case EXIT_REASON_EXTERNAL_INTERRUPT:
5733 return 0;
5734 case EXIT_REASON_TRIPLE_FAULT:
5735 return 1;
5736 case EXIT_REASON_PENDING_INTERRUPT:
5737 case EXIT_REASON_NMI_WINDOW:
5738 /*
5739 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5740 * (aka Interrupt Window Exiting) only when L1 turned it on,
5741 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5742 * Same for NMI Window Exiting.
5743 */
5744 return 1;
5745 case EXIT_REASON_TASK_SWITCH:
5746 return 1;
5747 case EXIT_REASON_CPUID:
5748 return 1;
5749 case EXIT_REASON_HLT:
5750 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5751 case EXIT_REASON_INVD:
5752 return 1;
5753 case EXIT_REASON_INVLPG:
5754 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5755 case EXIT_REASON_RDPMC:
5756 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5757 case EXIT_REASON_RDTSC:
5758 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5759 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5760 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5761 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5762 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5763 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5764 /*
5765 * VMX instructions trap unconditionally. This allows L1 to
5766 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5767 */
5768 return 1;
5769 case EXIT_REASON_CR_ACCESS:
5770 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5771 case EXIT_REASON_DR_ACCESS:
5772 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5773 case EXIT_REASON_IO_INSTRUCTION:
5774 /* TODO: support IO bitmaps */
5775 return 1;
5776 case EXIT_REASON_MSR_READ:
5777 case EXIT_REASON_MSR_WRITE:
5778 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5779 case EXIT_REASON_INVALID_STATE:
5780 return 1;
5781 case EXIT_REASON_MWAIT_INSTRUCTION:
5782 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5783 case EXIT_REASON_MONITOR_INSTRUCTION:
5784 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5785 case EXIT_REASON_PAUSE_INSTRUCTION:
5786 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5787 nested_cpu_has2(vmcs12,
5788 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5789 case EXIT_REASON_MCE_DURING_VMENTRY:
5790 return 0;
5791 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5792 return 1;
5793 case EXIT_REASON_APIC_ACCESS:
5794 return nested_cpu_has2(vmcs12,
5795 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5796 case EXIT_REASON_EPT_VIOLATION:
5797 case EXIT_REASON_EPT_MISCONFIG:
5798 return 0;
5799 case EXIT_REASON_WBINVD:
5800 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5801 case EXIT_REASON_XSETBV:
5802 return 1;
5803 default:
5804 return 1;
5805 }
5806}
5807
586f9607
AK		 5808static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5809{
5810 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5811 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5812}
5813
6aa8b732
AK		 5814/*
5815 * The guest has exited. See if we can fix it or if we need userspace
5816 * assistance.
5817 */
851ba692 5818static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5819{
29bd8a78 5820 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5821 u32 exit_reason = vmx->exit_reason;
1155f76a 5822 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5823
80ced186
MG		 5824 /* If guest state is invalid, start emulating */
5825 if (vmx->emulation_required && emulate_invalid_guest_state)
5826 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5827
b6f1250e
NHE		 5828 /*
5829 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5830 * we did not inject a still-pending event to L1 now because of
5831 * nested_run_pending, we need to re-enable this bit.
5832 */
5833 if (vmx->nested.nested_run_pending)
5834 kvm_make_request(KVM_REQ_EVENT, vcpu);
5835
509c75ea
NHE		 5836 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5837 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5838 vmx->nested.nested_run_pending = 1;
5839 else
5840 vmx->nested.nested_run_pending = 0;
5841
5842 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5843 nested_vmx_vmexit(vcpu);
5844 return 1;
5845 }
5846
5120702e
MG		 5847 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5848 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5849 vcpu->run->fail_entry.hardware_entry_failure_reason
5850 = exit_reason;
5851 return 0;
5852 }
5853
29bd8a78 5854 if (unlikely(vmx->fail)) {
851ba692
AK		 5855 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5856 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5857 = vmcs_read32(VM_INSTRUCTION_ERROR);
5858 return 0;
5859 }
6aa8b732 5860
d77c26fc 5861 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5862 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5863 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5864 exit_reason != EXIT_REASON_TASK_SWITCH))
5865 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5866 "(0x%x) and exit reason is 0x%x\n",
5867 __func__, vectoring_info, exit_reason);
3b86cd99 5868
644d711a
NHE		 5869 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5870 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5871 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5872 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5873 vmx->soft_vnmi_blocked = 0;
3b86cd99 5874 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5875 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5876 /*
5877 * This CPU don't support us in finding the end of an
5878 * NMI-blocked window if the guest runs with IRQs
5879 * disabled. So we pull the trigger after 1 s of
5880 * futile waiting, but inform the user about this.
5881 */
5882 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5883 "state on VCPU %d after 1 s timeout\n",
5884 __func__, vcpu->vcpu_id);
5885 vmx->soft_vnmi_blocked = 0;
3b86cd99 5886 }
3b86cd99
JK		 5887 }
5888
6aa8b732
AK		 5889 if (exit_reason < kvm_vmx_max_exit_handlers
5890 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5891 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5892 else {
851ba692
AK		 5893 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5894 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5895 }
5896 return 0;
5897}
5898
95ba8273 5899static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5900{
95ba8273 5901 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5902 vmcs_write32(TPR_THRESHOLD, 0);
5903 return;
5904 }
5905
95ba8273 5906 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5907}
5908
51aa01d1 5909static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5910{
00eba012
AK		 5911 u32 exit_intr_info;
5912
5913 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5914 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5915 return;
5916
c5ca8e57 5917 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5918 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5919
5920 /* Handle machine checks before interrupts are enabled */
00eba012 5921 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5922 kvm_machine_check();
5923
20f65983 5924 /* We need to handle NMIs before interrupts are enabled */
00eba012 5925 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5926 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5927 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5928 asm("int $2");
ff9d07a0
ZY		 5929 kvm_after_handle_nmi(&vmx->vcpu);
5930 }
51aa01d1 5931}
20f65983 5932
51aa01d1
AK		 5933static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5934{
c5ca8e57 5935 u32 exit_intr_info;
51aa01d1
AK		 5936 bool unblock_nmi;
5937 u8 vector;
5938 bool idtv_info_valid;
5939
5940 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5941
cf393f75 5942 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5943 if (vmx->nmi_known_unmasked)
5944 return;
c5ca8e57
AK		 5945 /*
5946 * Can't use vmx->exit_intr_info since we're not sure what
5947 * the exit reason is.
5948 */
5949 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5950 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5951 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5952 /*
7b4a25cb 5953 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5954 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5955 * a guest IRET fault.
7b4a25cb
GN		 5956 * SDM 3: 23.2.2 (September 2008)
5957 * Bit 12 is undefined in any of the following cases:
5958 * If the VM exit sets the valid bit in the IDT-vectoring
5959 * information field.
5960 * If the VM exit is due to a double fault.
cf393f75 5961 */
7b4a25cb
GN		 5962 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5963 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5964 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5965 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5966 else
5967 vmx->nmi_known_unmasked =
5968 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5969 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5970 } else if (unlikely(vmx->soft_vnmi_blocked))
5971 vmx->vnmi_blocked_time +=
5972 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5973}
5974
83422e17
AK		 5975static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5976 u32 idt_vectoring_info,
5977 int instr_len_field,
5978 int error_code_field)
51aa01d1 5979{
51aa01d1
AK		 5980 u8 vector;
5981 int type;
5982 bool idtv_info_valid;
5983
5984 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5985
37b96e98
GN		 5986 vmx->vcpu.arch.nmi_injected = false;
5987 kvm_clear_exception_queue(&vmx->vcpu);
5988 kvm_clear_interrupt_queue(&vmx->vcpu);
5989
5990 if (!idtv_info_valid)
5991 return;
5992
3842d135
AK		 5993 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5994
668f612f
AK		 5995 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5996 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5997
64a7ec06 5998 switch (type) {
37b96e98
GN		 5999 case INTR_TYPE_NMI_INTR:
6000 vmx->vcpu.arch.nmi_injected = true;
668f612f 6001 /*
7b4a25cb 6002 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6003 * Clear bit "block by NMI" before VM entry if a NMI
6004 * delivery faulted.
668f612f 6005 */
654f06fc 6006 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6007 break;
37b96e98 6008 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6009 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6010 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6011 /* fall through */
6012 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6013 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6014 u32 err = vmcs_read32(error_code_field);
37b96e98 6015 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6016 } else
6017 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6018 break;
66fd3f7f
GN		 6019 case INTR_TYPE_SOFT_INTR:
6020 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6021 vmcs_read32(instr_len_field);
66fd3f7f 6022 /* fall through */
37b96e98 6023 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6024 kvm_queue_interrupt(&vmx->vcpu, vector,
6025 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6026 break;
6027 default:
6028 break;
f7d9238f 6029 }
cf393f75
AK		 6030}
6031
83422e17
AK		 6032static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6033{
66c78ae4
NHE		 6034 if (is_guest_mode(&vmx->vcpu))
6035 return;
83422e17
AK		 6036 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6037 VM_EXIT_INSTRUCTION_LEN,
6038 IDT_VECTORING_ERROR_CODE);
6039}
6040
b463a6f7
AK		 6041static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6042{
66c78ae4
NHE		 6043 if (is_guest_mode(vcpu))
6044 return;
b463a6f7
AK		 6045 __vmx_complete_interrupts(to_vmx(vcpu),
6046 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6047 VM_ENTRY_INSTRUCTION_LEN,
6048 VM_ENTRY_EXCEPTION_ERROR_CODE);
6049
6050 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6051}
6052
c801949d
AK		 6053#ifdef CONFIG_X86_64
6054#define R "r"
6055#define Q "q"
6056#else
6057#define R "e"
6058#define Q "l"
6059#endif
6060
a3b5ba49 6061static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6062{
a2fa3e9f 6063 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6064
66c78ae4
NHE		 6065 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6066 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6067 if (vmcs12->idt_vectoring_info_field &
6068 VECTORING_INFO_VALID_MASK) {
6069 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6070 vmcs12->idt_vectoring_info_field);
6071 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6072 vmcs12->vm_exit_instruction_len);
6073 if (vmcs12->idt_vectoring_info_field &
6074 VECTORING_INFO_DELIVER_CODE_MASK)
6075 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6076 vmcs12->idt_vectoring_error_code);
6077 }
6078 }
6079
104f226b
AK		 6080 /* Record the guest's net vcpu time for enforced NMI injections. */
6081 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6082 vmx->entry_time = ktime_get();
6083
6084 /* Don't enter VMX if guest state is invalid, let the exit handler
6085 start emulation until we arrive back to a valid state */
6086 if (vmx->emulation_required && emulate_invalid_guest_state)
6087 return;
6088
6089 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6090 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6091 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6092 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6093
6094 /* When single-stepping over STI and MOV SS, we must clear the
6095 * corresponding interruptibility bits in the guest state. Otherwise
6096 * vmentry fails as it then expects bit 14 (BS) in pending debug
6097 * exceptions being set, but that's not correct for the guest debugging
6098 * case. */
6099 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6100 vmx_set_interrupt_shadow(vcpu, 0);
6101
d462b819 6102 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6103 asm(
6aa8b732 6104 /* Store host registers */
c801949d 6105 "push %%"R"dx; push %%"R"bp;"
40712fae 6106 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6107 "push %%"R"cx \n\t"
313dbd49
AK		 6108 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6109 "je 1f \n\t"
6110 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6111 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6112 "1: \n\t"
d3edefc0
AK		 6113 /* Reload cr2 if changed */
6114 "mov %c[cr2](%0), %%"R"ax \n\t"
6115 "mov %%cr2, %%"R"dx \n\t"
6116 "cmp %%"R"ax, %%"R"dx \n\t"
6117 "je 2f \n\t"
6118 "mov %%"R"ax, %%cr2 \n\t"
6119 "2: \n\t"
6aa8b732 6120 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6121 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6122 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6123 "mov %c[rax](%0), %%"R"ax \n\t"
6124 "mov %c[rbx](%0), %%"R"bx \n\t"
6125 "mov %c[rdx](%0), %%"R"dx \n\t"
6126 "mov %c[rsi](%0), %%"R"si \n\t"
6127 "mov %c[rdi](%0), %%"R"di \n\t"
6128 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6129#ifdef CONFIG_X86_64
e08aa78a
AK		 6130 "mov %c[r8](%0), %%r8 \n\t"
6131 "mov %c[r9](%0), %%r9 \n\t"
6132 "mov %c[r10](%0), %%r10 \n\t"
6133 "mov %c[r11](%0), %%r11 \n\t"
6134 "mov %c[r12](%0), %%r12 \n\t"
6135 "mov %c[r13](%0), %%r13 \n\t"
6136 "mov %c[r14](%0), %%r14 \n\t"
6137 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6138#endif
c801949d
AK		 6139 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6140
6aa8b732 6141 /* Enter guest mode */
cd2276a7 6142 "jne .Llaunched \n\t"
4ecac3fd 6143 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6144 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6145 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6146 ".Lkvm_vmx_return: "
6aa8b732 6147 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6148 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6149 "pop %0 \n\t"
c801949d
AK		 6150 "mov %%"R"ax, %c[rax](%0) \n\t"
6151 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6152 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6153 "mov %%"R"dx, %c[rdx](%0) \n\t"
6154 "mov %%"R"si, %c[rsi](%0) \n\t"
6155 "mov %%"R"di, %c[rdi](%0) \n\t"
6156 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6157#ifdef CONFIG_X86_64
e08aa78a
AK		 6158 "mov %%r8, %c[r8](%0) \n\t"
6159 "mov %%r9, %c[r9](%0) \n\t"
6160 "mov %%r10, %c[r10](%0) \n\t"
6161 "mov %%r11, %c[r11](%0) \n\t"
6162 "mov %%r12, %c[r12](%0) \n\t"
6163 "mov %%r13, %c[r13](%0) \n\t"
6164 "mov %%r14, %c[r14](%0) \n\t"
6165 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6166#endif
c801949d
AK		 6167 "mov %%cr2, %%"R"ax \n\t"
6168 "mov %%"R"ax, %c[cr2](%0) \n\t"
6169
1c696d0e 6170 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6171 "setbe %c[fail](%0) \n\t"
6172 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6173 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6174 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6175 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6176 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6177 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6178 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6179 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6180 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6181 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6182 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6183#ifdef CONFIG_X86_64
ad312c7c
ZX		 6184 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6185 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6186 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6187 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6188 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6189 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6190 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6191 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6192#endif
40712fae
AK		 6193 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6194 [wordsize]"i"(sizeof(ulong))
c2036300 6195 : "cc", "memory"
07d6f555 6196 , R"ax", R"bx", R"di", R"si"
c2036300 6197#ifdef CONFIG_X86_64
c2036300
LV		 6198 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6199#endif
6200 );
6aa8b732 6201
6de4f3ad 6202 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6203 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6204 | (1 << VCPU_EXREG_CPL)
aff48baa 6205 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6206 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6207 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6208 vcpu->arch.regs_dirty = 0;
6209
1155f76a
AK		 6210 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6211
66c78ae4
NHE		 6212 if (is_guest_mode(vcpu)) {
6213 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6214 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6215 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6216 vmcs12->idt_vectoring_error_code =
6217 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6218 vmcs12->vm_exit_instruction_len =
6219 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6220 }
6221 }
6222
d77c26fc 6223 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6224 vmx->loaded_vmcs->launched = 1;
1b6269db 6225
51aa01d1 6226 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6227 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6228
6229 vmx_complete_atomic_exit(vmx);
6230 vmx_recover_nmi_blocking(vmx);
cf393f75 6231 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6232}
6233
c801949d
AK		 6234#undef R
6235#undef Q
6236
6aa8b732
AK		 6237static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6238{
fb3f0f51
RR		 6239 struct vcpu_vmx *vmx = to_vmx(vcpu);
6240
cdbecfc3 6241 free_vpid(vmx);
ec378aee 6242 free_nested(vmx);
d462b819 6243 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6244 kfree(vmx->guest_msrs);
6245 kvm_vcpu_uninit(vcpu);
a4770347 6246 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6247}
6248
fb3f0f51 6249static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6250{
fb3f0f51 6251 int err;
c16f862d 6252 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6253 int cpu;
6aa8b732 6254
a2fa3e9f 6255 if (!vmx)
fb3f0f51
RR		 6256 return ERR_PTR(-ENOMEM);
6257
2384d2b3
SY		 6258 allocate_vpid(vmx);
6259
fb3f0f51
RR		 6260 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6261 if (err)
6262 goto free_vcpu;
965b58a5 6263
a2fa3e9f 6264 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6265 err = -ENOMEM;
fb3f0f51 6266 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6267 goto uninit_vcpu;
6268 }
965b58a5 6269
d462b819
NHE		 6270 vmx->loaded_vmcs = &vmx->vmcs01;
6271 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6272 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6273 goto free_msrs;
d462b819
NHE		 6274 if (!vmm_exclusive)
6275 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6276 loaded_vmcs_init(vmx->loaded_vmcs);
6277 if (!vmm_exclusive)
6278 kvm_cpu_vmxoff();
a2fa3e9f 6279
15ad7146
AK		 6280 cpu = get_cpu();
6281 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6282 vmx->vcpu.cpu = cpu;
8b9cf98c 6283 err = vmx_vcpu_setup(vmx);
fb3f0f51 6284 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6285 put_cpu();
fb3f0f51
RR		 6286 if (err)
6287 goto free_vmcs;
5e4a0b3c 6288 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6289 err = alloc_apic_access_page(kvm);
6290 if (err)
5e4a0b3c 6291 goto free_vmcs;
fb3f0f51 6292
b927a3ce
SY		 6293 if (enable_ept) {
6294 if (!kvm->arch.ept_identity_map_addr)
6295 kvm->arch.ept_identity_map_addr =
6296 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6297 err = -ENOMEM;
b7ebfb05
SY		 6298 if (alloc_identity_pagetable(kvm) != 0)
6299 goto free_vmcs;
93ea5388
GN		 6300 if (!init_rmode_identity_map(kvm))
6301 goto free_vmcs;
b927a3ce 6302 }
b7ebfb05 6303
a9d30f33
NHE		 6304 vmx->nested.current_vmptr = -1ull;
6305 vmx->nested.current_vmcs12 = NULL;
6306
fb3f0f51
RR		 6307 return &vmx->vcpu;
6308
6309free_vmcs:
d462b819 6310 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6311free_msrs:
fb3f0f51
RR		 6312 kfree(vmx->guest_msrs);
6313uninit_vcpu:
6314 kvm_vcpu_uninit(&vmx->vcpu);
6315free_vcpu:
cdbecfc3 6316 free_vpid(vmx);
a4770347 6317 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6318 return ERR_PTR(err);
6aa8b732
AK		 6319}
6320
002c7f7c
YS		 6321static void __init vmx_check_processor_compat(void *rtn)
6322{
6323 struct vmcs_config vmcs_conf;
6324
6325 *(int *)rtn = 0;
6326 if (setup_vmcs_config(&vmcs_conf) < 0)
6327 *(int *)rtn = -EIO;
6328 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6329 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6330 smp_processor_id());
6331 *(int *)rtn = -EIO;
6332 }
6333}
6334
67253af5
SY		 6335static int get_ept_level(void)
6336{
6337 return VMX_EPT_DEFAULT_GAW + 1;
6338}
6339
4b12f0de 6340static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6341{
4b12f0de
SY		 6342 u64 ret;
6343
522c68c4
SY		 6344 /* For VT-d and EPT combination
6345 * 1. MMIO: always map as UC
6346 * 2. EPT with VT-d:
6347 * a. VT-d without snooping control feature: can't guarantee the
6348 * result, try to trust guest.
6349 * b. VT-d with snooping control feature: snooping control feature of
6350 * VT-d engine can guarantee the cache correctness. Just set it
6351 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6352 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6353 * consistent with host MTRR
6354 */
4b12f0de
SY		 6355 if (is_mmio)
6356 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6357 else if (vcpu->kvm->arch.iommu_domain &&
6358 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6359 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6360 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6361 else
522c68c4 6362 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6363 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6364
6365 return ret;
64d4d521
SY		 6366}
6367
17cc3935 6368static int vmx_get_lpage_level(void)
344f414f 6369{
878403b7
SY		 6370 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6371 return PT_DIRECTORY_LEVEL;
6372 else
6373 /* For shadow and EPT supported 1GB page */
6374 return PT_PDPE_LEVEL;
344f414f
JR		 6375}
6376
0e851880
SY		 6377static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6378{
4e47c7a6
SY		 6379 struct kvm_cpuid_entry2 *best;
6380 struct vcpu_vmx *vmx = to_vmx(vcpu);
6381 u32 exec_control;
6382
6383 vmx->rdtscp_enabled = false;
6384 if (vmx_rdtscp_supported()) {
6385 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6386 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6387 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6388 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6389 vmx->rdtscp_enabled = true;
6390 else {
6391 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6392 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6393 exec_control);
6394 }
6395 }
6396 }
0e851880
SY		 6397}
6398
d4330ef2
JR		 6399static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6400{
7b8050f5
NHE		 6401 if (func == 1 && nested)
6402 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6403}
6404
fe3ef05c
NHE		 6405/*
6406 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6407 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6408 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6409 * guest in a way that will both be appropriate to L1's requests, and our
6410 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6411 * function also has additional necessary side-effects, like setting various
6412 * vcpu->arch fields.
6413 */
6414static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6415{
6416 struct vcpu_vmx *vmx = to_vmx(vcpu);
6417 u32 exec_control;
6418
6419 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6420 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6421 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6422 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6423 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6424 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6425 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6426 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6427 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6428 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6429 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6430 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6431 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6432 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6433 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6434 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6435 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6436 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6437 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6438 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6439 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6440 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6441 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6442 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6443 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6444 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6445 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6446 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6447 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6448 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6449 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6450 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6451 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6452 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6453 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6454 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6455
6456 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6457 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6458 vmcs12->vm_entry_intr_info_field);
6459 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6460 vmcs12->vm_entry_exception_error_code);
6461 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6462 vmcs12->vm_entry_instruction_len);
6463 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6464 vmcs12->guest_interruptibility_info);
6465 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6466 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6467 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6468 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6469 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6470 vmcs12->guest_pending_dbg_exceptions);
6471 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6472 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6473
6474 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6475
6476 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6477 (vmcs_config.pin_based_exec_ctrl |
6478 vmcs12->pin_based_vm_exec_control));
6479
6480 /*
6481 * Whether page-faults are trapped is determined by a combination of
6482 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6483 * If enable_ept, L0 doesn't care about page faults and we should
6484 * set all of these to L1's desires. However, if !enable_ept, L0 does
6485 * care about (at least some) page faults, and because it is not easy
6486 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6487 * to exit on each and every L2 page fault. This is done by setting
6488 * MASK=MATCH=0 and (see below) EB.PF=1.
6489 * Note that below we don't need special code to set EB.PF beyond the
6490 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6491 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6492 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6493 *
6494 * A problem with this approach (when !enable_ept) is that L1 may be
6495 * injected with more page faults than it asked for. This could have
6496 * caused problems, but in practice existing hypervisors don't care.
6497 * To fix this, we will need to emulate the PFEC checking (on the L1
6498 * page tables), using walk_addr(), when injecting PFs to L1.
6499 */
6500 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6501 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6502 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6503 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6504
6505 if (cpu_has_secondary_exec_ctrls()) {
6506 u32 exec_control = vmx_secondary_exec_control(vmx);
6507 if (!vmx->rdtscp_enabled)
6508 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6509 /* Take the following fields only from vmcs12 */
6510 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6511 if (nested_cpu_has(vmcs12,
6512 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6513 exec_control |= vmcs12->secondary_vm_exec_control;
6514
6515 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6516 /*
6517 * Translate L1 physical address to host physical
6518 * address for vmcs02. Keep the page pinned, so this
6519 * physical address remains valid. We keep a reference
6520 * to it so we can release it later.
6521 */
6522 if (vmx->nested.apic_access_page) /* shouldn't happen */
6523 nested_release_page(vmx->nested.apic_access_page);
6524 vmx->nested.apic_access_page =
6525 nested_get_page(vcpu, vmcs12->apic_access_addr);
6526 /*
6527 * If translation failed, no matter: This feature asks
6528 * to exit when accessing the given address, and if it
6529 * can never be accessed, this feature won't do
6530 * anything anyway.
6531 */
6532 if (!vmx->nested.apic_access_page)
6533 exec_control &=
6534 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6535 else
6536 vmcs_write64(APIC_ACCESS_ADDR,
6537 page_to_phys(vmx->nested.apic_access_page));
6538 }
6539
6540 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6541 }
6542
6543
6544 /*
6545 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6546 * Some constant fields are set here by vmx_set_constant_host_state().
6547 * Other fields are different per CPU, and will be set later when
6548 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6549 */
6550 vmx_set_constant_host_state();
6551
6552 /*
6553 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6554 * entry, but only if the current (host) sp changed from the value
6555 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6556 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6557 * here we just force the write to happen on entry.
6558 */
6559 vmx->host_rsp = 0;
6560
6561 exec_control = vmx_exec_control(vmx); /* L0's desires */
6562 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6563 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6564 exec_control &= ~CPU_BASED_TPR_SHADOW;
6565 exec_control |= vmcs12->cpu_based_vm_exec_control;
6566 /*
6567 * Merging of IO and MSR bitmaps not currently supported.
6568 * Rather, exit every time.
6569 */
6570 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6571 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6572 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6573
6574 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6575
6576 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6577 * bitwise-or of what L1 wants to trap for L2, and what we want to
6578 * trap. Note that CR0.TS also needs updating - we do this later.
6579 */
6580 update_exception_bitmap(vcpu);
6581 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6582 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6583
6584 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6585 vmcs_write32(VM_EXIT_CONTROLS,
6586 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6587 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6588 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6589
6590 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6591 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6592 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6593 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6594
6595
6596 set_cr4_guest_host_mask(vmx);
6597
27fc51b2
NHE		 6598 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6599 vmcs_write64(TSC_OFFSET,
6600 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6601 else
6602 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6603
6604 if (enable_vpid) {
6605 /*
6606 * Trivially support vpid by letting L2s share their parent
6607 * L1's vpid. TODO: move to a more elaborate solution, giving
6608 * each L2 its own vpid and exposing the vpid feature to L1.
6609 */
6610 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6611 vmx_flush_tlb(vcpu);
6612 }
6613
6614 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6615 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6616 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6617 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6618 else
6619 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6620 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6621 vmx_set_efer(vcpu, vcpu->arch.efer);
6622
6623 /*
6624 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6625 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6626 * The CR0_READ_SHADOW is what L2 should have expected to read given
6627 * the specifications by L1; It's not enough to take
6628 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6629 * have more bits than L1 expected.
6630 */
6631 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6632 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6633
6634 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6635 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6636
6637 /* shadow page tables on either EPT or shadow page tables */
6638 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6639 kvm_mmu_reset_context(vcpu);
6640
6641 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6642 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6643}
6644
cd232ad0
NHE		 6645/*
6646 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6647 * for running an L2 nested guest.
6648 */
6649static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6650{
6651 struct vmcs12 *vmcs12;
6652 struct vcpu_vmx *vmx = to_vmx(vcpu);
6653 int cpu;
6654 struct loaded_vmcs *vmcs02;
6655
6656 if (!nested_vmx_check_permission(vcpu) ||
6657 !nested_vmx_check_vmcs12(vcpu))
6658 return 1;
6659
6660 skip_emulated_instruction(vcpu);
6661 vmcs12 = get_vmcs12(vcpu);
6662
7c177938
NHE		 6663 /*
6664 * The nested entry process starts with enforcing various prerequisites
6665 * on vmcs12 as required by the Intel SDM, and act appropriately when
6666 * they fail: As the SDM explains, some conditions should cause the
6667 * instruction to fail, while others will cause the instruction to seem
6668 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6669 * To speed up the normal (success) code path, we should avoid checking
6670 * for misconfigurations which will anyway be caught by the processor
6671 * when using the merged vmcs02.
6672 */
6673 if (vmcs12->launch_state == launch) {
6674 nested_vmx_failValid(vcpu,
6675 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6676 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6677 return 1;
6678 }
6679
6680 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6681 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6682 /*TODO: Also verify bits beyond physical address width are 0*/
6683 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6684 return 1;
6685 }
6686
6687 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6688 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6689 /*TODO: Also verify bits beyond physical address width are 0*/
6690 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6691 return 1;
6692 }
6693
6694 if (vmcs12->vm_entry_msr_load_count > 0 ||
6695 vmcs12->vm_exit_msr_load_count > 0 ||
6696 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6697 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6698 __func__);
7c177938
NHE		 6699 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6700 return 1;
6701 }
6702
6703 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6704 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6705 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6706 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6707 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6708 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6709 !vmx_control_verify(vmcs12->vm_exit_controls,
6710 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6711 !vmx_control_verify(vmcs12->vm_entry_controls,
6712 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6713 {
6714 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6715 return 1;
6716 }
6717
6718 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6719 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6720 nested_vmx_failValid(vcpu,
6721 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6722 return 1;
6723 }
6724
6725 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6726 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6727 nested_vmx_entry_failure(vcpu, vmcs12,
6728 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6729 return 1;
6730 }
6731 if (vmcs12->vmcs_link_pointer != -1ull) {
6732 nested_vmx_entry_failure(vcpu, vmcs12,
6733 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6734 return 1;
6735 }
6736
6737 /*
6738 * We're finally done with prerequisite checking, and can start with
6739 * the nested entry.
6740 */
6741
cd232ad0
NHE		 6742 vmcs02 = nested_get_current_vmcs02(vmx);
6743 if (!vmcs02)
6744 return -ENOMEM;
6745
6746 enter_guest_mode(vcpu);
6747
6748 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6749
6750 cpu = get_cpu();
6751 vmx->loaded_vmcs = vmcs02;
6752 vmx_vcpu_put(vcpu);
6753 vmx_vcpu_load(vcpu, cpu);
6754 vcpu->cpu = cpu;
6755 put_cpu();
6756
6757 vmcs12->launch_state = 1;
6758
6759 prepare_vmcs02(vcpu, vmcs12);
6760
6761 /*
6762 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6763 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6764 * returned as far as L1 is concerned. It will only return (and set
6765 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6766 */
6767 return 1;
6768}
6769
4704d0be
NHE		 6770/*
6771 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6772 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6773 * This function returns the new value we should put in vmcs12.guest_cr0.
6774 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6775 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6776 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6777 * didn't trap the bit, because if L1 did, so would L0).
6778 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6779 * been modified by L2, and L1 knows it. So just leave the old value of
6780 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6781 * isn't relevant, because if L0 traps this bit it can set it to anything.
6782 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6783 * changed these bits, and therefore they need to be updated, but L0
6784 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6785 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6786 */
6787static inline unsigned long
6788vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6789{
6790 return
6791 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6792 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6793 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6794 vcpu->arch.cr0_guest_owned_bits));
6795}
6796
6797static inline unsigned long
6798vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6799{
6800 return
6801 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6802 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6803 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6804 vcpu->arch.cr4_guest_owned_bits));
6805}
6806
6807/*
6808 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6809 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6810 * and this function updates it to reflect the changes to the guest state while
6811 * L2 was running (and perhaps made some exits which were handled directly by L0
6812 * without going back to L1), and to reflect the exit reason.
6813 * Note that we do not have to copy here all VMCS fields, just those that
6814 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6815 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6816 * which already writes to vmcs12 directly.
6817 */
6818void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6819{
6820 /* update guest state fields: */
6821 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6822 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6823
6824 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6825 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6826 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6827 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6828
6829 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6830 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6831 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6832 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6833 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6834 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6835 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6836 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6837 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6838 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6839 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6840 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6841 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6842 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6843 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6844 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6845 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6846 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6847 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6848 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6849 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6850 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6851 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6852 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6853 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6854 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6855 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6856 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6857 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6858 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6859 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6860 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6861 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6862 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6863 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6864 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6865
6866 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6867 vmcs12->guest_interruptibility_info =
6868 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6869 vmcs12->guest_pending_dbg_exceptions =
6870 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6871
6872 /* TODO: These cannot have changed unless we have MSR bitmaps and
6873 * the relevant bit asks not to trap the change */
6874 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6875 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6876 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6877 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6878 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6879 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6880
6881 /* update exit information fields: */
6882
6883 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6884 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6885
6886 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6887 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6888 vmcs12->idt_vectoring_info_field =
6889 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6890 vmcs12->idt_vectoring_error_code =
6891 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6892 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6893 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6894
6895 /* clear vm-entry fields which are to be cleared on exit */
6896 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6897 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6898}
6899
6900/*
6901 * A part of what we need to when the nested L2 guest exits and we want to
6902 * run its L1 parent, is to reset L1's guest state to the host state specified
6903 * in vmcs12.
6904 * This function is to be called not only on normal nested exit, but also on
6905 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6906 * Failures During or After Loading Guest State").
6907 * This function should be called when the active VMCS is L1's (vmcs01).
6908 */
6909void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6910{
6911 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6912 vcpu->arch.efer = vmcs12->host_ia32_efer;
6913 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6914 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6915 else
6916 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6917 vmx_set_efer(vcpu, vcpu->arch.efer);
6918
6919 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6920 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6921 /*
6922 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6923 * actually changed, because it depends on the current state of
6924 * fpu_active (which may have changed).
6925 * Note that vmx_set_cr0 refers to efer set above.
6926 */
6927 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6928 /*
6929 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6930 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6931 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6932 */
6933 update_exception_bitmap(vcpu);
6934 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6935 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6936
6937 /*
6938 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6939 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6940 */
6941 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6942 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6943
6944 /* shadow page tables on either EPT or shadow page tables */
6945 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6946 kvm_mmu_reset_context(vcpu);
6947
6948 if (enable_vpid) {
6949 /*
6950 * Trivially support vpid by letting L2s share their parent
6951 * L1's vpid. TODO: move to a more elaborate solution, giving
6952 * each L2 its own vpid and exposing the vpid feature to L1.
6953 */
6954 vmx_flush_tlb(vcpu);
6955 }
6956
6957
6958 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6959 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6960 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6961 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6962 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6963 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6964 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6965 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6966 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6967 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6968 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6969 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6970 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6971 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6972 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6973
6974 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6975 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6976 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6977 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6978 vmcs12->host_ia32_perf_global_ctrl);
6979}
6980
6981/*
6982 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6983 * and modify vmcs12 to make it see what it would expect to see there if
6984 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6985 */
6986static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6987{
6988 struct vcpu_vmx *vmx = to_vmx(vcpu);
6989 int cpu;
6990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6991
6992 leave_guest_mode(vcpu);
6993 prepare_vmcs12(vcpu, vmcs12);
6994
6995 cpu = get_cpu();
6996 vmx->loaded_vmcs = &vmx->vmcs01;
6997 vmx_vcpu_put(vcpu);
6998 vmx_vcpu_load(vcpu, cpu);
6999 vcpu->cpu = cpu;
7000 put_cpu();
7001
7002 /* if no vmcs02 cache requested, remove the one we used */
7003 if (VMCS02_POOL_SIZE == 0)
7004 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7005
7006 load_vmcs12_host_state(vcpu, vmcs12);
7007
27fc51b2 7008 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7009 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7010
7011 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7012 vmx->host_rsp = 0;
7013
7014 /* Unpin physical memory we referred to in vmcs02 */
7015 if (vmx->nested.apic_access_page) {
7016 nested_release_page(vmx->nested.apic_access_page);
7017 vmx->nested.apic_access_page = 0;
7018 }
7019
7020 /*
7021 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7022 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7023 * success or failure flag accordingly.
7024 */
7025 if (unlikely(vmx->fail)) {
7026 vmx->fail = 0;
7027 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7028 } else
7029 nested_vmx_succeed(vcpu);
7030}
7031
7c177938
NHE		 7032/*
7033 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7034 * 23.7 "VM-entry failures during or after loading guest state" (this also
7035 * lists the acceptable exit-reason and exit-qualification parameters).
7036 * It should only be called before L2 actually succeeded to run, and when
7037 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7038 */
7039static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7040 struct vmcs12 *vmcs12,
7041 u32 reason, unsigned long qualification)
7042{
7043 load_vmcs12_host_state(vcpu, vmcs12);
7044 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7045 vmcs12->exit_qualification = qualification;
7046 nested_vmx_succeed(vcpu);
7047}
7048
8a76d7f2
JR		 7049static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7050 struct x86_instruction_info *info,
7051 enum x86_intercept_stage stage)
7052{
7053 return X86EMUL_CONTINUE;
7054}
7055
cbdd1bea 7056static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7057 .cpu_has_kvm_support = cpu_has_kvm_support,
7058 .disabled_by_bios = vmx_disabled_by_bios,
7059 .hardware_setup = hardware_setup,
7060 .hardware_unsetup = hardware_unsetup,
002c7f7c 7061 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7062 .hardware_enable = hardware_enable,
7063 .hardware_disable = hardware_disable,
04547156 7064 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7065
7066 .vcpu_create = vmx_create_vcpu,
7067 .vcpu_free = vmx_free_vcpu,
04d2cc77 7068 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7069
04d2cc77 7070 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7071 .vcpu_load = vmx_vcpu_load,
7072 .vcpu_put = vmx_vcpu_put,
7073
7074 .set_guest_debug = set_guest_debug,
7075 .get_msr = vmx_get_msr,
7076 .set_msr = vmx_set_msr,
7077 .get_segment_base = vmx_get_segment_base,
7078 .get_segment = vmx_get_segment,
7079 .set_segment = vmx_set_segment,
2e4d2653 7080 .get_cpl = vmx_get_cpl,
6aa8b732 7081 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7082 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7083 .decache_cr3 = vmx_decache_cr3,
25c4c276 7084 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7085 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7086 .set_cr3 = vmx_set_cr3,
7087 .set_cr4 = vmx_set_cr4,
6aa8b732 7088 .set_efer = vmx_set_efer,
6aa8b732
AK		 7089 .get_idt = vmx_get_idt,
7090 .set_idt = vmx_set_idt,
7091 .get_gdt = vmx_get_gdt,
7092 .set_gdt = vmx_set_gdt,
020df079 7093 .set_dr7 = vmx_set_dr7,
5fdbf976 7094 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7095 .get_rflags = vmx_get_rflags,
7096 .set_rflags = vmx_set_rflags,
ebcbab4c 7097 .fpu_activate = vmx_fpu_activate,
02daab21 7098 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7099
7100 .tlb_flush = vmx_flush_tlb,
6aa8b732 7101
6aa8b732 7102 .run = vmx_vcpu_run,
6062d012 7103 .handle_exit = vmx_handle_exit,
6aa8b732 7104 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7105 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7106 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7107 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7108 .set_irq = vmx_inject_irq,
95ba8273 7109 .set_nmi = vmx_inject_nmi,
298101da 7110 .queue_exception = vmx_queue_exception,
b463a6f7 7111 .cancel_injection = vmx_cancel_injection,
78646121 7112 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7113 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7114 .get_nmi_mask = vmx_get_nmi_mask,
7115 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7116 .enable_nmi_window = enable_nmi_window,
7117 .enable_irq_window = enable_irq_window,
7118 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7119
cbc94022 7120 .set_tss_addr = vmx_set_tss_addr,
67253af5 7121 .get_tdp_level = get_ept_level,
4b12f0de 7122 .get_mt_mask = vmx_get_mt_mask,
229456fc 7123
586f9607 7124 .get_exit_info = vmx_get_exit_info,
586f9607 7125
17cc3935 7126 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7127
7128 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7129
7130 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7131
7132 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7133
7134 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7135
4051b188 7136 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7137 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7138 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7139 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7140 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7141
7142 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7143
7144 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7145};
7146
7147static int __init vmx_init(void)
7148{
26bb0981
AK		 7149 int r, i;
7150
7151 rdmsrl_safe(MSR_EFER, &host_efer);
7152
7153 for (i = 0; i < NR_VMX_MSR; ++i)
7154 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7155
3e7c73e9 7156 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7157 if (!vmx_io_bitmap_a)
7158 return -ENOMEM;
7159
3e7c73e9 7160 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7161 if (!vmx_io_bitmap_b) {
7162 r = -ENOMEM;
7163 goto out;
7164 }
7165
5897297b
AK		 7166 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7167 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7168 r = -ENOMEM;
7169 goto out1;
7170 }
7171
5897297b
AK		 7172 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7173 if (!vmx_msr_bitmap_longmode) {
7174 r = -ENOMEM;
7175 goto out2;
7176 }
7177
fdef3ad1
HQ		 7178 /*
7179 * Allow direct access to the PC debug port (it is often used for I/O
7180 * delays, but the vmexits simply slow things down).
7181 */
3e7c73e9
AK		 7182 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7183 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7184
3e7c73e9 7185 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7186
5897297b
AK		 7187 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7188 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7189
2384d2b3
SY		 7190 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7191
0ee75bea
AK		 7192 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7193 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7194 if (r)
5897297b 7195 goto out3;
25c5f225 7196
5897297b
AK		 7197 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7198 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7199 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7200 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7201 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7202 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7203
089d034e 7204 if (enable_ept) {
534e38b4 7205 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7206 VMX_EPT_EXECUTABLE_MASK);
ce88decf 7207 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7208 kvm_enable_tdp();
7209 } else
7210 kvm_disable_tdp();
1439442c 7211
fdef3ad1
HQ		 7212 return 0;
7213
5897297b
AK		 7214out3:
7215 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7216out2:
5897297b 7217 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7218out1:
3e7c73e9 7219 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7220out:
3e7c73e9 7221 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7222 return r;
6aa8b732
AK		 7223}
7224
7225static void __exit vmx_exit(void)
7226{
5897297b
AK		 7227 free_page((unsigned long)vmx_msr_bitmap_legacy);
7228 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7229 free_page((unsigned long)vmx_io_bitmap_b);
7230 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7231
cb498ea2 7232 kvm_exit();
6aa8b732
AK		 7233}
7234
7235module_init(vmx_init)
7236module_exit(vmx_exit)
Ubuntu Artful kernel mirror