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KVM: SVM: Intercept RDPMC
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
229456fc 30#include <linux/ftrace_event.h>
5a0e3ad6 31#include <linux/slab.h>
cafd6659 32#include <linux/tboot.h>
5fdbf976 33#include "kvm_cache_regs.h"
35920a35 34#include "x86.h"
e495606d 35
6aa8b732 36#include <asm/io.h>
3b3be0d1 37#include <asm/desc.h>
13673a90 38#include <asm/vmx.h>
6210e37b 39#include <asm/virtext.h>
a0861c02 40#include <asm/mce.h>
2acf923e
DC		 41#include <asm/i387.h>
42#include <asm/xcr.h>
d7cd9796 43#include <asm/perf_event.h>
6aa8b732 44
229456fc
MT		 45#include "trace.h"
46
4ecac3fd 47#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 48#define __ex_clear(x, reg) \
49 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 50
6aa8b732
AK		 51MODULE_AUTHOR("Qumranet");
52MODULE_LICENSE("GPL");
53
4462d21a 54static int __read_mostly enable_vpid = 1;
736caefe 55module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 56
4462d21a 57static int __read_mostly flexpriority_enabled = 1;
736caefe 58module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 59
4462d21a 60static int __read_mostly enable_ept = 1;
736caefe 61module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 62
3a624e29
NK		 63static int __read_mostly enable_unrestricted_guest = 1;
64module_param_named(unrestricted_guest,
65 enable_unrestricted_guest, bool, S_IRUGO);
66
4462d21a 67static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 68module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 69
b923e62e
DX		 70static int __read_mostly vmm_exclusive = 1;
71module_param(vmm_exclusive, bool, S_IRUGO);
72
443381a8
AL		 73static int __read_mostly yield_on_hlt = 1;
74module_param(yield_on_hlt, bool, S_IRUGO);
75
58fbbf26
KT		 76static int __read_mostly fasteoi = 1;
77module_param(fasteoi, bool, S_IRUGO);
78
801d3424
NHE		 79/*
80 * If nested=1, nested virtualization is supported, i.e., guests may use
81 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
82 * use VMX instructions.
83 */
84static int __read_mostly nested = 0;
85module_param(nested, bool, S_IRUGO);
86
cdc0e244
AK		 87#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
88 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
89#define KVM_GUEST_CR0_MASK \
90 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
91#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 92 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 93#define KVM_VM_CR0_ALWAYS_ON \
94 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 95#define KVM_CR4_GUEST_OWNED_BITS \
96 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 | X86_CR4_OSXMMEXCPT)
98
cdc0e244
AK		 99#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
100#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
101
78ac8b47
AK		 102#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103
4b8d54f9
ZE		 104/*
105 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
106 * ple_gap: upper bound on the amount of time between two successive
107 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 108 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 109 * ple_window: upper bound on the amount of time a guest is allowed to execute
110 * in a PAUSE loop. Tests indicate that most spinlocks are held for
111 * less than 2^12 cycles
112 * Time is measured based on a counter that runs at the same rate as the TSC,
113 * refer SDM volume 3b section 21.6.13 & 22.1.3.
114 */
00c25bce 115#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 116#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
117static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
118module_param(ple_gap, int, S_IRUGO);
119
120static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
121module_param(ple_window, int, S_IRUGO);
122
8bf00a52 123#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 124#define VMCS02_POOL_SIZE 1
61d2ef2c 125
a2fa3e9f
GH		 126struct vmcs {
127 u32 revision_id;
128 u32 abort;
129 char data[0];
130};
131
d462b819
NHE		 132/*
133 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
134 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
135 * loaded on this CPU (so we can clear them if the CPU goes down).
136 */
137struct loaded_vmcs {
138 struct vmcs *vmcs;
139 int cpu;
140 int launched;
141 struct list_head loaded_vmcss_on_cpu_link;
142};
143
26bb0981
AK		 144struct shared_msr_entry {
145 unsigned index;
146 u64 data;
d5696725 147 u64 mask;
26bb0981
AK		 148};
149
a9d30f33
NHE		 150/*
151 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
152 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
153 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
154 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
155 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
156 * More than one of these structures may exist, if L1 runs multiple L2 guests.
157 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
158 * underlying hardware which will be used to run L2.
159 * This structure is packed to ensure that its layout is identical across
160 * machines (necessary for live migration).
161 * If there are changes in this struct, VMCS12_REVISION must be changed.
162 */
22bd0358 163typedef u64 natural_width;
a9d30f33
NHE		 164struct __packed vmcs12 {
165 /* According to the Intel spec, a VMCS region must start with the
166 * following two fields. Then follow implementation-specific data.
167 */
168 u32 revision_id;
169 u32 abort;
22bd0358 170
27d6c865
NHE		 171 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
172 u32 padding[7]; /* room for future expansion */
173
22bd0358
NHE		 174 u64 io_bitmap_a;
175 u64 io_bitmap_b;
176 u64 msr_bitmap;
177 u64 vm_exit_msr_store_addr;
178 u64 vm_exit_msr_load_addr;
179 u64 vm_entry_msr_load_addr;
180 u64 tsc_offset;
181 u64 virtual_apic_page_addr;
182 u64 apic_access_addr;
183 u64 ept_pointer;
184 u64 guest_physical_address;
185 u64 vmcs_link_pointer;
186 u64 guest_ia32_debugctl;
187 u64 guest_ia32_pat;
188 u64 guest_ia32_efer;
189 u64 guest_ia32_perf_global_ctrl;
190 u64 guest_pdptr0;
191 u64 guest_pdptr1;
192 u64 guest_pdptr2;
193 u64 guest_pdptr3;
194 u64 host_ia32_pat;
195 u64 host_ia32_efer;
196 u64 host_ia32_perf_global_ctrl;
197 u64 padding64[8]; /* room for future expansion */
198 /*
199 * To allow migration of L1 (complete with its L2 guests) between
200 * machines of different natural widths (32 or 64 bit), we cannot have
201 * unsigned long fields with no explict size. We use u64 (aliased
202 * natural_width) instead. Luckily, x86 is little-endian.
203 */
204 natural_width cr0_guest_host_mask;
205 natural_width cr4_guest_host_mask;
206 natural_width cr0_read_shadow;
207 natural_width cr4_read_shadow;
208 natural_width cr3_target_value0;
209 natural_width cr3_target_value1;
210 natural_width cr3_target_value2;
211 natural_width cr3_target_value3;
212 natural_width exit_qualification;
213 natural_width guest_linear_address;
214 natural_width guest_cr0;
215 natural_width guest_cr3;
216 natural_width guest_cr4;
217 natural_width guest_es_base;
218 natural_width guest_cs_base;
219 natural_width guest_ss_base;
220 natural_width guest_ds_base;
221 natural_width guest_fs_base;
222 natural_width guest_gs_base;
223 natural_width guest_ldtr_base;
224 natural_width guest_tr_base;
225 natural_width guest_gdtr_base;
226 natural_width guest_idtr_base;
227 natural_width guest_dr7;
228 natural_width guest_rsp;
229 natural_width guest_rip;
230 natural_width guest_rflags;
231 natural_width guest_pending_dbg_exceptions;
232 natural_width guest_sysenter_esp;
233 natural_width guest_sysenter_eip;
234 natural_width host_cr0;
235 natural_width host_cr3;
236 natural_width host_cr4;
237 natural_width host_fs_base;
238 natural_width host_gs_base;
239 natural_width host_tr_base;
240 natural_width host_gdtr_base;
241 natural_width host_idtr_base;
242 natural_width host_ia32_sysenter_esp;
243 natural_width host_ia32_sysenter_eip;
244 natural_width host_rsp;
245 natural_width host_rip;
246 natural_width paddingl[8]; /* room for future expansion */
247 u32 pin_based_vm_exec_control;
248 u32 cpu_based_vm_exec_control;
249 u32 exception_bitmap;
250 u32 page_fault_error_code_mask;
251 u32 page_fault_error_code_match;
252 u32 cr3_target_count;
253 u32 vm_exit_controls;
254 u32 vm_exit_msr_store_count;
255 u32 vm_exit_msr_load_count;
256 u32 vm_entry_controls;
257 u32 vm_entry_msr_load_count;
258 u32 vm_entry_intr_info_field;
259 u32 vm_entry_exception_error_code;
260 u32 vm_entry_instruction_len;
261 u32 tpr_threshold;
262 u32 secondary_vm_exec_control;
263 u32 vm_instruction_error;
264 u32 vm_exit_reason;
265 u32 vm_exit_intr_info;
266 u32 vm_exit_intr_error_code;
267 u32 idt_vectoring_info_field;
268 u32 idt_vectoring_error_code;
269 u32 vm_exit_instruction_len;
270 u32 vmx_instruction_info;
271 u32 guest_es_limit;
272 u32 guest_cs_limit;
273 u32 guest_ss_limit;
274 u32 guest_ds_limit;
275 u32 guest_fs_limit;
276 u32 guest_gs_limit;
277 u32 guest_ldtr_limit;
278 u32 guest_tr_limit;
279 u32 guest_gdtr_limit;
280 u32 guest_idtr_limit;
281 u32 guest_es_ar_bytes;
282 u32 guest_cs_ar_bytes;
283 u32 guest_ss_ar_bytes;
284 u32 guest_ds_ar_bytes;
285 u32 guest_fs_ar_bytes;
286 u32 guest_gs_ar_bytes;
287 u32 guest_ldtr_ar_bytes;
288 u32 guest_tr_ar_bytes;
289 u32 guest_interruptibility_info;
290 u32 guest_activity_state;
291 u32 guest_sysenter_cs;
292 u32 host_ia32_sysenter_cs;
293 u32 padding32[8]; /* room for future expansion */
294 u16 virtual_processor_id;
295 u16 guest_es_selector;
296 u16 guest_cs_selector;
297 u16 guest_ss_selector;
298 u16 guest_ds_selector;
299 u16 guest_fs_selector;
300 u16 guest_gs_selector;
301 u16 guest_ldtr_selector;
302 u16 guest_tr_selector;
303 u16 host_es_selector;
304 u16 host_cs_selector;
305 u16 host_ss_selector;
306 u16 host_ds_selector;
307 u16 host_fs_selector;
308 u16 host_gs_selector;
309 u16 host_tr_selector;
a9d30f33
NHE		 310};
311
312/*
313 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
314 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
315 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
316 */
317#define VMCS12_REVISION 0x11e57ed0
318
319/*
320 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
321 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
322 * current implementation, 4K are reserved to avoid future complications.
323 */
324#define VMCS12_SIZE 0x1000
325
ff2f6fe9
NHE		 326/* Used to remember the last vmcs02 used for some recently used vmcs12s */
327struct vmcs02_list {
328 struct list_head list;
329 gpa_t vmptr;
330 struct loaded_vmcs vmcs02;
331};
332
ec378aee
NHE		 333/*
334 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
335 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 */
337struct nested_vmx {
338 /* Has the level1 guest done vmxon? */
339 bool vmxon;
a9d30f33
NHE		 340
341 /* The guest-physical address of the current VMCS L1 keeps for L2 */
342 gpa_t current_vmptr;
343 /* The host-usable pointer to the above */
344 struct page *current_vmcs12_page;
345 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 346
347 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
348 struct list_head vmcs02_pool;
349 int vmcs02_num;
fe3ef05c 350 u64 vmcs01_tsc_offset;
644d711a
NHE		 351 /* L2 must run next, and mustn't decide to exit to L1. */
352 bool nested_run_pending;
fe3ef05c
NHE		 353 /*
354 * Guest pages referred to in vmcs02 with host-physical pointers, so
355 * we must keep them pinned while L2 runs.
356 */
357 struct page *apic_access_page;
ec378aee
NHE		 358};
359
a2fa3e9f 360struct vcpu_vmx {
fb3f0f51 361 struct kvm_vcpu vcpu;
313dbd49 362 unsigned long host_rsp;
29bd8a78 363 u8 fail;
69c73028 364 u8 cpl;
9d58b931 365 bool nmi_known_unmasked;
51aa01d1 366 u32 exit_intr_info;
1155f76a 367 u32 idt_vectoring_info;
6de12732 368 ulong rflags;
26bb0981 369 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 370 int nmsrs;
371 int save_nmsrs;
a2fa3e9f 372#ifdef CONFIG_X86_64
44ea2b17
AK		 373 u64 msr_host_kernel_gs_base;
374 u64 msr_guest_kernel_gs_base;
a2fa3e9f 375#endif
d462b819
NHE		 376 /*
377 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
378 * non-nested (L1) guest, it always points to vmcs01. For a nested
379 * guest (L2), it points to a different VMCS.
380 */
381 struct loaded_vmcs vmcs01;
382 struct loaded_vmcs *loaded_vmcs;
383 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 384 struct msr_autoload {
385 unsigned nr;
386 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
387 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
388 } msr_autoload;
a2fa3e9f
GH		 389 struct {
390 int loaded;
391 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 392 int gs_ldt_reload_needed;
393 int fs_reload_needed;
d77c26fc 394 } host_state;
9c8cba37 395 struct {
7ffd92c5 396 int vm86_active;
78ac8b47 397 ulong save_rflags;
7ffd92c5
AK		 398 struct kvm_save_segment {
399 u16 selector;
400 unsigned long base;
401 u32 limit;
402 u32 ar;
403 } tr, es, ds, fs, gs;
9c8cba37 404 } rmode;
2fb92db1
AK		 405 struct {
406 u32 bitmask; /* 4 bits per segment (1 bit per field) */
407 struct kvm_save_segment seg[8];
408 } segment_cache;
2384d2b3 409 int vpid;
04fa4d32 410 bool emulation_required;
3b86cd99
JK		 411
412 /* Support for vnmi-less CPUs */
413 int soft_vnmi_blocked;
414 ktime_t entry_time;
415 s64 vnmi_blocked_time;
a0861c02 416 u32 exit_reason;
4e47c7a6
SY		 417
418 bool rdtscp_enabled;
ec378aee
NHE		 419
420 /* Support for a guest hypervisor (nested VMX) */
421 struct nested_vmx nested;
a2fa3e9f
GH		 422};
423
2fb92db1
AK		 424enum segment_cache_field {
425 SEG_FIELD_SEL = 0,
426 SEG_FIELD_BASE = 1,
427 SEG_FIELD_LIMIT = 2,
428 SEG_FIELD_AR = 3,
429
430 SEG_FIELD_NR = 4
431};
432
a2fa3e9f
GH		 433static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
434{
fb3f0f51 435 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 436}
437
22bd0358
NHE		 438#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
439#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
440#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
441 [number##_HIGH] = VMCS12_OFFSET(name)+4
442
443static unsigned short vmcs_field_to_offset_table[] = {
444 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
445 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
446 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
447 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
448 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
449 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
450 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
451 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
452 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
453 FIELD(HOST_ES_SELECTOR, host_es_selector),
454 FIELD(HOST_CS_SELECTOR, host_cs_selector),
455 FIELD(HOST_SS_SELECTOR, host_ss_selector),
456 FIELD(HOST_DS_SELECTOR, host_ds_selector),
457 FIELD(HOST_FS_SELECTOR, host_fs_selector),
458 FIELD(HOST_GS_SELECTOR, host_gs_selector),
459 FIELD(HOST_TR_SELECTOR, host_tr_selector),
460 FIELD64(IO_BITMAP_A, io_bitmap_a),
461 FIELD64(IO_BITMAP_B, io_bitmap_b),
462 FIELD64(MSR_BITMAP, msr_bitmap),
463 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
464 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
465 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
466 FIELD64(TSC_OFFSET, tsc_offset),
467 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
468 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
469 FIELD64(EPT_POINTER, ept_pointer),
470 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
471 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
472 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
473 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
474 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
475 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
476 FIELD64(GUEST_PDPTR0, guest_pdptr0),
477 FIELD64(GUEST_PDPTR1, guest_pdptr1),
478 FIELD64(GUEST_PDPTR2, guest_pdptr2),
479 FIELD64(GUEST_PDPTR3, guest_pdptr3),
480 FIELD64(HOST_IA32_PAT, host_ia32_pat),
481 FIELD64(HOST_IA32_EFER, host_ia32_efer),
482 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
483 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
484 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
485 FIELD(EXCEPTION_BITMAP, exception_bitmap),
486 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
487 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
488 FIELD(CR3_TARGET_COUNT, cr3_target_count),
489 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
490 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
491 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
492 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
493 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
494 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
495 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
496 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
497 FIELD(TPR_THRESHOLD, tpr_threshold),
498 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
499 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
500 FIELD(VM_EXIT_REASON, vm_exit_reason),
501 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
502 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
503 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
504 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
505 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
506 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
507 FIELD(GUEST_ES_LIMIT, guest_es_limit),
508 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
509 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
510 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
511 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
512 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
513 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
514 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
515 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
516 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
517 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
518 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
519 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
520 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
521 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
522 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
523 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
524 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
525 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
526 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
527 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
528 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
529 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
530 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
531 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
532 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
533 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
534 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
535 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
536 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
537 FIELD(EXIT_QUALIFICATION, exit_qualification),
538 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
539 FIELD(GUEST_CR0, guest_cr0),
540 FIELD(GUEST_CR3, guest_cr3),
541 FIELD(GUEST_CR4, guest_cr4),
542 FIELD(GUEST_ES_BASE, guest_es_base),
543 FIELD(GUEST_CS_BASE, guest_cs_base),
544 FIELD(GUEST_SS_BASE, guest_ss_base),
545 FIELD(GUEST_DS_BASE, guest_ds_base),
546 FIELD(GUEST_FS_BASE, guest_fs_base),
547 FIELD(GUEST_GS_BASE, guest_gs_base),
548 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
549 FIELD(GUEST_TR_BASE, guest_tr_base),
550 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
551 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
552 FIELD(GUEST_DR7, guest_dr7),
553 FIELD(GUEST_RSP, guest_rsp),
554 FIELD(GUEST_RIP, guest_rip),
555 FIELD(GUEST_RFLAGS, guest_rflags),
556 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
557 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
558 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
559 FIELD(HOST_CR0, host_cr0),
560 FIELD(HOST_CR3, host_cr3),
561 FIELD(HOST_CR4, host_cr4),
562 FIELD(HOST_FS_BASE, host_fs_base),
563 FIELD(HOST_GS_BASE, host_gs_base),
564 FIELD(HOST_TR_BASE, host_tr_base),
565 FIELD(HOST_GDTR_BASE, host_gdtr_base),
566 FIELD(HOST_IDTR_BASE, host_idtr_base),
567 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
568 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
569 FIELD(HOST_RSP, host_rsp),
570 FIELD(HOST_RIP, host_rip),
571};
572static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
573
574static inline short vmcs_field_to_offset(unsigned long field)
575{
576 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
577 return -1;
578 return vmcs_field_to_offset_table[field];
579}
580
a9d30f33
NHE		 581static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
582{
583 return to_vmx(vcpu)->nested.current_vmcs12;
584}
585
586static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
587{
588 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
589 if (is_error_page(page)) {
590 kvm_release_page_clean(page);
591 return NULL;
592 }
593 return page;
594}
595
596static void nested_release_page(struct page *page)
597{
598 kvm_release_page_dirty(page);
599}
600
601static void nested_release_page_clean(struct page *page)
602{
603 kvm_release_page_clean(page);
604}
605
4e1096d2 606static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 607static void kvm_cpu_vmxon(u64 addr);
608static void kvm_cpu_vmxoff(void);
aff48baa 609static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 610static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 611
6aa8b732
AK		 612static DEFINE_PER_CPU(struct vmcs *, vmxarea);
613static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 614/*
615 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
616 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
617 */
618static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 619static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 620
3e7c73e9
AK		 621static unsigned long *vmx_io_bitmap_a;
622static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 623static unsigned long *vmx_msr_bitmap_legacy;
624static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 625
110312c8 626static bool cpu_has_load_ia32_efer;
8bf00a52 627static bool cpu_has_load_perf_global_ctrl;
110312c8 628
2384d2b3
SY		 629static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
630static DEFINE_SPINLOCK(vmx_vpid_lock);
631
1c3d14fe 632static struct vmcs_config {
6aa8b732
AK		 633 int size;
634 int order;
635 u32 revision_id;
1c3d14fe
YS		 636 u32 pin_based_exec_ctrl;
637 u32 cpu_based_exec_ctrl;
f78e0e2e 638 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 639 u32 vmexit_ctrl;
640 u32 vmentry_ctrl;
641} vmcs_config;
6aa8b732 642
efff9e53 643static struct vmx_capability {
d56f546d
SY		 644 u32 ept;
645 u32 vpid;
646} vmx_capability;
647
6aa8b732
AK		 648#define VMX_SEGMENT_FIELD(seg) \
649 [VCPU_SREG_##seg] = { \
650 .selector = GUEST_##seg##_SELECTOR, \
651 .base = GUEST_##seg##_BASE, \
652 .limit = GUEST_##seg##_LIMIT, \
653 .ar_bytes = GUEST_##seg##_AR_BYTES, \
654 }
655
656static struct kvm_vmx_segment_field {
657 unsigned selector;
658 unsigned base;
659 unsigned limit;
660 unsigned ar_bytes;
661} kvm_vmx_segment_fields[] = {
662 VMX_SEGMENT_FIELD(CS),
663 VMX_SEGMENT_FIELD(DS),
664 VMX_SEGMENT_FIELD(ES),
665 VMX_SEGMENT_FIELD(FS),
666 VMX_SEGMENT_FIELD(GS),
667 VMX_SEGMENT_FIELD(SS),
668 VMX_SEGMENT_FIELD(TR),
669 VMX_SEGMENT_FIELD(LDTR),
670};
671
26bb0981
AK		 672static u64 host_efer;
673
6de4f3ad
AK		 674static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
675
4d56c8a7 676/*
8c06585d 677 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 678 * away by decrementing the array size.
679 */
6aa8b732 680static const u32 vmx_msr_index[] = {
05b3e0c2 681#ifdef CONFIG_X86_64
44ea2b17 682 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 683#endif
8c06585d 684 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 685};
9d8f549d 686#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 687
31299944 688static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 689{
690 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
691 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 692 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 693}
694
31299944 695static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 696{
697 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
698 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 699 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 700}
701
31299944 702static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 703{
704 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
705 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 706 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 707}
708
31299944 709static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
712 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
713}
714
31299944 715static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 716{
717 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
718 INTR_INFO_VALID_MASK)) ==
719 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
720}
721
31299944 722static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 723{
04547156 724 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 725}
726
31299944 727static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 728{
04547156 729 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 730}
731
31299944 732static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 733{
04547156 734 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 735}
736
31299944 737static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 738{
04547156
SY		 739 return vmcs_config.cpu_based_exec_ctrl &
740 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 741}
742
774ead3a 743static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 744{
04547156
SY		 745 return vmcs_config.cpu_based_2nd_exec_ctrl &
746 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
747}
748
749static inline bool cpu_has_vmx_flexpriority(void)
750{
751 return cpu_has_vmx_tpr_shadow() &&
752 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 753}
754
e799794e
MT		 755static inline bool cpu_has_vmx_ept_execute_only(void)
756{
31299944 757 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 758}
759
760static inline bool cpu_has_vmx_eptp_uncacheable(void)
761{
31299944 762 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 763}
764
765static inline bool cpu_has_vmx_eptp_writeback(void)
766{
31299944 767 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 768}
769
770static inline bool cpu_has_vmx_ept_2m_page(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 773}
774
878403b7
SY		 775static inline bool cpu_has_vmx_ept_1g_page(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 778}
779
4bc9b982
SY		 780static inline bool cpu_has_vmx_ept_4levels(void)
781{
782 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
783}
784
31299944 785static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 786{
31299944 787 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 788}
789
31299944 790static inline bool cpu_has_vmx_invept_context(void)
d56f546d 791{
31299944 792 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 793}
794
31299944 795static inline bool cpu_has_vmx_invept_global(void)
d56f546d 796{
31299944 797 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 798}
799
518c8aee
GJ		 800static inline bool cpu_has_vmx_invvpid_single(void)
801{
802 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
803}
804
b9d762fa
GJ		 805static inline bool cpu_has_vmx_invvpid_global(void)
806{
807 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
808}
809
31299944 810static inline bool cpu_has_vmx_ept(void)
d56f546d 811{
04547156
SY		 812 return vmcs_config.cpu_based_2nd_exec_ctrl &
813 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 814}
815
31299944 816static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 817{
818 return vmcs_config.cpu_based_2nd_exec_ctrl &
819 SECONDARY_EXEC_UNRESTRICTED_GUEST;
820}
821
31299944 822static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 823{
824 return vmcs_config.cpu_based_2nd_exec_ctrl &
825 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
826}
827
31299944 828static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 829{
6d3e435e 830 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 831}
832
31299944 833static inline bool cpu_has_vmx_vpid(void)
2384d2b3 834{
04547156
SY		 835 return vmcs_config.cpu_based_2nd_exec_ctrl &
836 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 837}
838
31299944 839static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 840{
841 return vmcs_config.cpu_based_2nd_exec_ctrl &
842 SECONDARY_EXEC_RDTSCP;
843}
844
31299944 845static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 846{
847 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
848}
849
f5f48ee1
SY		 850static inline bool cpu_has_vmx_wbinvd_exit(void)
851{
852 return vmcs_config.cpu_based_2nd_exec_ctrl &
853 SECONDARY_EXEC_WBINVD_EXITING;
854}
855
04547156
SY		 856static inline bool report_flexpriority(void)
857{
858 return flexpriority_enabled;
859}
860
fe3ef05c
NHE		 861static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
862{
863 return vmcs12->cpu_based_vm_exec_control & bit;
864}
865
866static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
867{
868 return (vmcs12->cpu_based_vm_exec_control &
869 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
870 (vmcs12->secondary_vm_exec_control & bit);
871}
872
644d711a
NHE		 873static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
874 struct kvm_vcpu *vcpu)
875{
876 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
877}
878
879static inline bool is_exception(u32 intr_info)
880{
881 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
882 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
883}
884
885static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 886static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
887 struct vmcs12 *vmcs12,
888 u32 reason, unsigned long qualification);
889
8b9cf98c 890static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 891{
892 int i;
893
a2fa3e9f 894 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 895 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 896 return i;
897 return -1;
898}
899
2384d2b3
SY		 900static inline void __invvpid(int ext, u16 vpid, gva_t gva)
901{
902 struct {
903 u64 vpid : 16;
904 u64 rsvd : 48;
905 u64 gva;
906 } operand = { vpid, 0, gva };
907
4ecac3fd 908 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 909 /* CF==1 or ZF==1 --> rc = -1 */
910 "; ja 1f ; ud2 ; 1:"
911 : : "a"(&operand), "c"(ext) : "cc", "memory");
912}
913
1439442c
SY		 914static inline void __invept(int ext, u64 eptp, gpa_t gpa)
915{
916 struct {
917 u64 eptp, gpa;
918 } operand = {eptp, gpa};
919
4ecac3fd 920 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 921 /* CF==1 or ZF==1 --> rc = -1 */
922 "; ja 1f ; ud2 ; 1:\n"
923 : : "a" (&operand), "c" (ext) : "cc", "memory");
924}
925
26bb0981 926static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 927{
928 int i;
929
8b9cf98c 930 i = __find_msr_index(vmx, msr);
a75beee6 931 if (i >= 0)
a2fa3e9f 932 return &vmx->guest_msrs[i];
8b6d44c7 933 return NULL;
7725f0ba
AK		 934}
935
6aa8b732
AK		 936static void vmcs_clear(struct vmcs *vmcs)
937{
938 u64 phys_addr = __pa(vmcs);
939 u8 error;
940
4ecac3fd 941 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 942 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 943 : "cc", "memory");
944 if (error)
945 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
946 vmcs, phys_addr);
947}
948
d462b819
NHE		 949static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
950{
951 vmcs_clear(loaded_vmcs->vmcs);
952 loaded_vmcs->cpu = -1;
953 loaded_vmcs->launched = 0;
954}
955
7725b894
DX		 956static void vmcs_load(struct vmcs *vmcs)
957{
958 u64 phys_addr = __pa(vmcs);
959 u8 error;
960
961 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 962 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 963 : "cc", "memory");
964 if (error)
2844d849 965 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 966 vmcs, phys_addr);
967}
968
d462b819 969static void __loaded_vmcs_clear(void *arg)
6aa8b732 970{
d462b819 971 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 972 int cpu = raw_smp_processor_id();
6aa8b732 973
d462b819
NHE		 974 if (loaded_vmcs->cpu != cpu)
975 return; /* vcpu migration can race with cpu offline */
976 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 977 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 978 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
979 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 980}
981
d462b819 982static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 983{
d462b819
NHE		 984 if (loaded_vmcs->cpu != -1)
985 smp_call_function_single(
986 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 987}
988
1760dd49 989static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 990{
991 if (vmx->vpid == 0)
992 return;
993
518c8aee
GJ		 994 if (cpu_has_vmx_invvpid_single())
995 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 996}
997
b9d762fa
GJ		 998static inline void vpid_sync_vcpu_global(void)
999{
1000 if (cpu_has_vmx_invvpid_global())
1001 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1002}
1003
1004static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1005{
1006 if (cpu_has_vmx_invvpid_single())
1760dd49 1007 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1008 else
1009 vpid_sync_vcpu_global();
1010}
1011
1439442c
SY		 1012static inline void ept_sync_global(void)
1013{
1014 if (cpu_has_vmx_invept_global())
1015 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1016}
1017
1018static inline void ept_sync_context(u64 eptp)
1019{
089d034e 1020 if (enable_ept) {
1439442c
SY		 1021 if (cpu_has_vmx_invept_context())
1022 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1023 else
1024 ept_sync_global();
1025 }
1026}
1027
1028static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1029{
089d034e 1030 if (enable_ept) {
1439442c
SY		 1031 if (cpu_has_vmx_invept_individual_addr())
1032 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1033 eptp, gpa);
1034 else
1035 ept_sync_context(eptp);
1036 }
1037}
1038
96304217 1039static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1040{
5e520e62 1041 unsigned long value;
6aa8b732 1042
5e520e62
AK		 1043 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1044 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1045 return value;
1046}
1047
96304217 1048static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1049{
1050 return vmcs_readl(field);
1051}
1052
96304217 1053static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1054{
1055 return vmcs_readl(field);
1056}
1057
96304217 1058static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1059{
05b3e0c2 1060#ifdef CONFIG_X86_64
6aa8b732
AK		 1061 return vmcs_readl(field);
1062#else
1063 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1064#endif
1065}
1066
e52de1b8
AK		 1067static noinline void vmwrite_error(unsigned long field, unsigned long value)
1068{
1069 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1070 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1071 dump_stack();
1072}
1073
6aa8b732
AK		 1074static void vmcs_writel(unsigned long field, unsigned long value)
1075{
1076 u8 error;
1077
4ecac3fd 1078 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1079 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1080 if (unlikely(error))
1081 vmwrite_error(field, value);
6aa8b732
AK		 1082}
1083
1084static void vmcs_write16(unsigned long field, u16 value)
1085{
1086 vmcs_writel(field, value);
1087}
1088
1089static void vmcs_write32(unsigned long field, u32 value)
1090{
1091 vmcs_writel(field, value);
1092}
1093
1094static void vmcs_write64(unsigned long field, u64 value)
1095{
6aa8b732 1096 vmcs_writel(field, value);
7682f2d0 1097#ifndef CONFIG_X86_64
6aa8b732
AK		 1098 asm volatile ("");
1099 vmcs_writel(field+1, value >> 32);
1100#endif
1101}
1102
2ab455cc
AL		 1103static void vmcs_clear_bits(unsigned long field, u32 mask)
1104{
1105 vmcs_writel(field, vmcs_readl(field) & ~mask);
1106}
1107
1108static void vmcs_set_bits(unsigned long field, u32 mask)
1109{
1110 vmcs_writel(field, vmcs_readl(field) | mask);
1111}
1112
2fb92db1
AK		 1113static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1114{
1115 vmx->segment_cache.bitmask = 0;
1116}
1117
1118static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1119 unsigned field)
1120{
1121 bool ret;
1122 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1123
1124 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1125 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1126 vmx->segment_cache.bitmask = 0;
1127 }
1128 ret = vmx->segment_cache.bitmask & mask;
1129 vmx->segment_cache.bitmask |= mask;
1130 return ret;
1131}
1132
1133static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1134{
1135 u16 *p = &vmx->segment_cache.seg[seg].selector;
1136
1137 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1138 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1139 return *p;
1140}
1141
1142static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1143{
1144 ulong *p = &vmx->segment_cache.seg[seg].base;
1145
1146 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1147 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1148 return *p;
1149}
1150
1151static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1152{
1153 u32 *p = &vmx->segment_cache.seg[seg].limit;
1154
1155 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1156 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1157 return *p;
1158}
1159
1160static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1161{
1162 u32 *p = &vmx->segment_cache.seg[seg].ar;
1163
1164 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1165 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1166 return *p;
1167}
1168
abd3f2d6
AK		 1169static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1170{
1171 u32 eb;
1172
fd7373cc
JK		 1173 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1174 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1175 if ((vcpu->guest_debug &
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1177 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1178 eb |= 1u << BP_VECTOR;
7ffd92c5 1179 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1180 eb = ~0;
089d034e 1181 if (enable_ept)
1439442c 1182 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1183 if (vcpu->fpu_active)
1184 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1185
1186 /* When we are running a nested L2 guest and L1 specified for it a
1187 * certain exception bitmap, we must trap the same exceptions and pass
1188 * them to L1. When running L2, we will only handle the exceptions
1189 * specified above if L1 did not want them.
1190 */
1191 if (is_guest_mode(vcpu))
1192 eb |= get_vmcs12(vcpu)->exception_bitmap;
1193
abd3f2d6
AK		 1194 vmcs_write32(EXCEPTION_BITMAP, eb);
1195}
1196
8bf00a52
GN		 1197static void clear_atomic_switch_msr_special(unsigned long entry,
1198 unsigned long exit)
1199{
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1202}
1203
61d2ef2c
AK		 1204static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1205{
1206 unsigned i;
1207 struct msr_autoload *m = &vmx->msr_autoload;
1208
8bf00a52
GN		 1209 switch (msr) {
1210 case MSR_EFER:
1211 if (cpu_has_load_ia32_efer) {
1212 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1213 VM_EXIT_LOAD_IA32_EFER);
1214 return;
1215 }
1216 break;
1217 case MSR_CORE_PERF_GLOBAL_CTRL:
1218 if (cpu_has_load_perf_global_ctrl) {
1219 clear_atomic_switch_msr_special(
1220 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1221 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1222 return;
1223 }
1224 break;
110312c8
AK		 1225 }
1226
61d2ef2c
AK		 1227 for (i = 0; i < m->nr; ++i)
1228 if (m->guest[i].index == msr)
1229 break;
1230
1231 if (i == m->nr)
1232 return;
1233 --m->nr;
1234 m->guest[i] = m->guest[m->nr];
1235 m->host[i] = m->host[m->nr];
1236 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1237 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1238}
1239
8bf00a52
GN		 1240static void add_atomic_switch_msr_special(unsigned long entry,
1241 unsigned long exit, unsigned long guest_val_vmcs,
1242 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1243{
1244 vmcs_write64(guest_val_vmcs, guest_val);
1245 vmcs_write64(host_val_vmcs, host_val);
1246 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1247 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1248}
1249
61d2ef2c
AK		 1250static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1251 u64 guest_val, u64 host_val)
1252{
1253 unsigned i;
1254 struct msr_autoload *m = &vmx->msr_autoload;
1255
8bf00a52
GN		 1256 switch (msr) {
1257 case MSR_EFER:
1258 if (cpu_has_load_ia32_efer) {
1259 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1260 VM_EXIT_LOAD_IA32_EFER,
1261 GUEST_IA32_EFER,
1262 HOST_IA32_EFER,
1263 guest_val, host_val);
1264 return;
1265 }
1266 break;
1267 case MSR_CORE_PERF_GLOBAL_CTRL:
1268 if (cpu_has_load_perf_global_ctrl) {
1269 add_atomic_switch_msr_special(
1270 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1272 GUEST_IA32_PERF_GLOBAL_CTRL,
1273 HOST_IA32_PERF_GLOBAL_CTRL,
1274 guest_val, host_val);
1275 return;
1276 }
1277 break;
110312c8
AK		 1278 }
1279
61d2ef2c
AK		 1280 for (i = 0; i < m->nr; ++i)
1281 if (m->guest[i].index == msr)
1282 break;
1283
e7fc6f93
GN		 1284 if (i == NR_AUTOLOAD_MSRS) {
1285 printk_once(KERN_WARNING"Not enough mst switch entries. "
1286 "Can't add msr %x\n", msr);
1287 return;
1288 } else if (i == m->nr) {
61d2ef2c
AK		 1289 ++m->nr;
1290 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1291 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1292 }
1293
1294 m->guest[i].index = msr;
1295 m->guest[i].value = guest_val;
1296 m->host[i].index = msr;
1297 m->host[i].value = host_val;
1298}
1299
33ed6329
AK		 1300static void reload_tss(void)
1301{
33ed6329
AK		 1302 /*
1303 * VT restores TR but not its size. Useless.
1304 */
d359192f 1305 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1306 struct desc_struct *descs;
33ed6329 1307
d359192f 1308 descs = (void *)gdt->address;
33ed6329
AK		 1309 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1310 load_TR_desc();
33ed6329
AK		 1311}
1312
92c0d900 1313static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1314{
3a34a881 1315 u64 guest_efer;
51c6cf66
AK		 1316 u64 ignore_bits;
1317
f6801dff 1318 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1319
51c6cf66
AK		 1320 /*
1321 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1322 * outside long mode
1323 */
1324 ignore_bits = EFER_NX | EFER_SCE;
1325#ifdef CONFIG_X86_64
1326 ignore_bits |= EFER_LMA | EFER_LME;
1327 /* SCE is meaningful only in long mode on Intel */
1328 if (guest_efer & EFER_LMA)
1329 ignore_bits &= ~(u64)EFER_SCE;
1330#endif
51c6cf66
AK		 1331 guest_efer &= ~ignore_bits;
1332 guest_efer |= host_efer & ignore_bits;
26bb0981 1333 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1334 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1335
1336 clear_atomic_switch_msr(vmx, MSR_EFER);
1337 /* On ept, can't emulate nx, and must switch nx atomically */
1338 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1339 guest_efer = vmx->vcpu.arch.efer;
1340 if (!(guest_efer & EFER_LMA))
1341 guest_efer &= ~EFER_LME;
1342 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1343 return false;
1344 }
1345
26bb0981 1346 return true;
51c6cf66
AK		 1347}
1348
2d49ec72
GN		 1349static unsigned long segment_base(u16 selector)
1350{
d359192f 1351 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1352 struct desc_struct *d;
1353 unsigned long table_base;
1354 unsigned long v;
1355
1356 if (!(selector & ~3))
1357 return 0;
1358
d359192f 1359 table_base = gdt->address;
2d49ec72
GN		 1360
1361 if (selector & 4) { /* from ldt */
1362 u16 ldt_selector = kvm_read_ldt();
1363
1364 if (!(ldt_selector & ~3))
1365 return 0;
1366
1367 table_base = segment_base(ldt_selector);
1368 }
1369 d = (struct desc_struct *)(table_base + (selector & ~7));
1370 v = get_desc_base(d);
1371#ifdef CONFIG_X86_64
1372 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1373 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1374#endif
1375 return v;
1376}
1377
1378static inline unsigned long kvm_read_tr_base(void)
1379{
1380 u16 tr;
1381 asm("str %0" : "=g"(tr));
1382 return segment_base(tr);
1383}
1384
04d2cc77 1385static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1386{
04d2cc77 1387 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1388 int i;
04d2cc77 1389
a2fa3e9f 1390 if (vmx->host_state.loaded)
33ed6329
AK		 1391 return;
1392
a2fa3e9f 1393 vmx->host_state.loaded = 1;
33ed6329
AK		 1394 /*
1395 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1396 * allow segment selectors with cpl > 0 or ti == 1.
1397 */
d6e88aec 1398 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1399 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1400 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1401 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1402 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1403 vmx->host_state.fs_reload_needed = 0;
1404 } else {
33ed6329 1405 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1406 vmx->host_state.fs_reload_needed = 1;
33ed6329 1407 }
9581d442 1408 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1409 if (!(vmx->host_state.gs_sel & 7))
1410 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1411 else {
1412 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1413 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1414 }
1415
1416#ifdef CONFIG_X86_64
1417 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1418 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1419#else
a2fa3e9f
GH		 1420 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1421 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1422#endif
707c0874
AK		 1423
1424#ifdef CONFIG_X86_64
c8770e7b
AK		 1425 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1426 if (is_long_mode(&vmx->vcpu))
44ea2b17 1427 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1428#endif
26bb0981
AK		 1429 for (i = 0; i < vmx->save_nmsrs; ++i)
1430 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1431 vmx->guest_msrs[i].data,
1432 vmx->guest_msrs[i].mask);
33ed6329
AK		 1433}
1434
a9b21b62 1435static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1436{
a2fa3e9f 1437 if (!vmx->host_state.loaded)
33ed6329
AK		 1438 return;
1439
e1beb1d3 1440 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1441 vmx->host_state.loaded = 0;
c8770e7b
AK		 1442#ifdef CONFIG_X86_64
1443 if (is_long_mode(&vmx->vcpu))
1444 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1445#endif
152d3f2f 1446 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1447 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1448#ifdef CONFIG_X86_64
9581d442 1449 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1450#else
1451 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1452#endif
33ed6329 1453 }
0a77fe4c
AK		 1454 if (vmx->host_state.fs_reload_needed)
1455 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1456 reload_tss();
44ea2b17 1457#ifdef CONFIG_X86_64
c8770e7b 1458 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1459#endif
1c11e713
AK		 1460 if (current_thread_info()->status & TS_USEDFPU)
1461 clts();
3444d7da 1462 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1463}
1464
a9b21b62
AK		 1465static void vmx_load_host_state(struct vcpu_vmx *vmx)
1466{
1467 preempt_disable();
1468 __vmx_load_host_state(vmx);
1469 preempt_enable();
1470}
1471
6aa8b732
AK		 1472/*
1473 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1474 * vcpu mutex is already taken.
1475 */
15ad7146 1476static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1477{
a2fa3e9f 1478 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1479 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1480
4610c9cc
DX		 1481 if (!vmm_exclusive)
1482 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1483 else if (vmx->loaded_vmcs->cpu != cpu)
1484 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1485
d462b819
NHE		 1486 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1487 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1488 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1489 }
1490
d462b819 1491 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1492 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1493 unsigned long sysenter_esp;
1494
a8eeb04a 1495 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1496 local_irq_disable();
d462b819
NHE		 1497 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1498 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1499 local_irq_enable();
1500
6aa8b732
AK		 1501 /*
1502 * Linux uses per-cpu TSS and GDT, so set these when switching
1503 * processors.
1504 */
d6e88aec 1505 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1506 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1507
1508 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1509 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1510 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1511 }
6aa8b732
AK		 1512}
1513
1514static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1515{
a9b21b62 1516 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1517 if (!vmm_exclusive) {
d462b819
NHE		 1518 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1519 vcpu->cpu = -1;
4610c9cc
DX		 1520 kvm_cpu_vmxoff();
1521 }
6aa8b732
AK		 1522}
1523
5fd86fcf
AK		 1524static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1525{
81231c69
AK		 1526 ulong cr0;
1527
5fd86fcf
AK		 1528 if (vcpu->fpu_active)
1529 return;
1530 vcpu->fpu_active = 1;
81231c69
AK		 1531 cr0 = vmcs_readl(GUEST_CR0);
1532 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1533 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1534 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1535 update_exception_bitmap(vcpu);
edcafe3c 1536 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1537 if (is_guest_mode(vcpu))
1538 vcpu->arch.cr0_guest_owned_bits &=
1539 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1540 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1541}
1542
edcafe3c
AK		 1543static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1544
fe3ef05c
NHE		 1545/*
1546 * Return the cr0 value that a nested guest would read. This is a combination
1547 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1548 * its hypervisor (cr0_read_shadow).
1549 */
1550static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1551{
1552 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1553 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1554}
1555static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1556{
1557 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1558 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1559}
1560
5fd86fcf
AK		 1561static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1562{
36cf24e0
NHE		 1563 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1564 * set this *before* calling this function.
1565 */
edcafe3c 1566 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1567 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1568 update_exception_bitmap(vcpu);
edcafe3c
AK		 1569 vcpu->arch.cr0_guest_owned_bits = 0;
1570 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1571 if (is_guest_mode(vcpu)) {
1572 /*
1573 * L1's specified read shadow might not contain the TS bit,
1574 * so now that we turned on shadowing of this bit, we need to
1575 * set this bit of the shadow. Like in nested_vmx_run we need
1576 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1577 * up-to-date here because we just decached cr0.TS (and we'll
1578 * only update vmcs12->guest_cr0 on nested exit).
1579 */
1580 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1581 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1582 (vcpu->arch.cr0 & X86_CR0_TS);
1583 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1584 } else
1585 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1586}
1587
6aa8b732
AK		 1588static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1589{
78ac8b47 1590 unsigned long rflags, save_rflags;
345dcaa8 1591
6de12732
AK		 1592 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1593 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1594 rflags = vmcs_readl(GUEST_RFLAGS);
1595 if (to_vmx(vcpu)->rmode.vm86_active) {
1596 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1597 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1598 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1599 }
1600 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1601 }
6de12732 1602 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1603}
1604
1605static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1606{
6de12732 1607 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1608 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1609 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1610 if (to_vmx(vcpu)->rmode.vm86_active) {
1611 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1612 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1613 }
6aa8b732
AK		 1614 vmcs_writel(GUEST_RFLAGS, rflags);
1615}
1616
2809f5d2
GC		 1617static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1618{
1619 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1620 int ret = 0;
1621
1622 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1623 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1624 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1625 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1626
1627 return ret & mask;
1628}
1629
1630static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1631{
1632 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1633 u32 interruptibility = interruptibility_old;
1634
1635 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1636
48005f64 1637 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1638 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1639 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1640 interruptibility |= GUEST_INTR_STATE_STI;
1641
1642 if ((interruptibility != interruptibility_old))
1643 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1644}
1645
6aa8b732
AK		 1646static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1647{
1648 unsigned long rip;
6aa8b732 1649
5fdbf976 1650 rip = kvm_rip_read(vcpu);
6aa8b732 1651 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1652 kvm_rip_write(vcpu, rip);
6aa8b732 1653
2809f5d2
GC		 1654 /* skipping an emulated instruction also counts */
1655 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1656}
1657
443381a8
AL		 1658static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1659{
1660 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1661 * explicitly skip the instruction because if the HLT state is set, then
1662 * the instruction is already executing and RIP has already been
1663 * advanced. */
1664 if (!yield_on_hlt &&
1665 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1666 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1667}
1668
0b6ac343
NHE		 1669/*
1670 * KVM wants to inject page-faults which it got to the guest. This function
1671 * checks whether in a nested guest, we need to inject them to L1 or L2.
1672 * This function assumes it is called with the exit reason in vmcs02 being
1673 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1674 * is running).
1675 */
1676static int nested_pf_handled(struct kvm_vcpu *vcpu)
1677{
1678 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1679
1680 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1681 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1682 return 0;
1683
1684 nested_vmx_vmexit(vcpu);
1685 return 1;
1686}
1687
298101da 1688static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1689 bool has_error_code, u32 error_code,
1690 bool reinject)
298101da 1691{
77ab6db0 1692 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1693 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1694
0b6ac343
NHE		 1695 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1696 nested_pf_handled(vcpu))
1697 return;
1698
8ab2d2e2 1699 if (has_error_code) {
77ab6db0 1700 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1701 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1702 }
77ab6db0 1703
7ffd92c5 1704 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1705 int inc_eip = 0;
1706 if (kvm_exception_is_soft(nr))
1707 inc_eip = vcpu->arch.event_exit_inst_len;
1708 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1709 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1710 return;
1711 }
1712
66fd3f7f
GN		 1713 if (kvm_exception_is_soft(nr)) {
1714 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1715 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1716 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1717 } else
1718 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1719
1720 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1721 vmx_clear_hlt(vcpu);
298101da
AK		 1722}
1723
4e47c7a6
SY		 1724static bool vmx_rdtscp_supported(void)
1725{
1726 return cpu_has_vmx_rdtscp();
1727}
1728
a75beee6
ED		 1729/*
1730 * Swap MSR entry in host/guest MSR entry array.
1731 */
8b9cf98c 1732static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1733{
26bb0981 1734 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1735
1736 tmp = vmx->guest_msrs[to];
1737 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1738 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1739}
1740
e38aea3e
AK		 1741/*
1742 * Set up the vmcs to automatically save and restore system
1743 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1744 * mode, as fiddling with msrs is very expensive.
1745 */
8b9cf98c 1746static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1747{
26bb0981 1748 int save_nmsrs, index;
5897297b 1749 unsigned long *msr_bitmap;
e38aea3e 1750
a75beee6
ED		 1751 save_nmsrs = 0;
1752#ifdef CONFIG_X86_64
8b9cf98c 1753 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1754 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1755 if (index >= 0)
8b9cf98c
RR		 1756 move_msr_up(vmx, index, save_nmsrs++);
1757 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1758 if (index >= 0)
8b9cf98c
RR		 1759 move_msr_up(vmx, index, save_nmsrs++);
1760 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1761 if (index >= 0)
8b9cf98c 1762 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1763 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764 if (index >= 0 && vmx->rdtscp_enabled)
1765 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1766 /*
8c06585d 1767 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1768 * if efer.sce is enabled.
1769 */
8c06585d 1770 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1771 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1772 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1773 }
1774#endif
92c0d900
AK		 1775 index = __find_msr_index(vmx, MSR_EFER);
1776 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1777 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1778
26bb0981 1779 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1780
1781 if (cpu_has_vmx_msr_bitmap()) {
1782 if (is_long_mode(&vmx->vcpu))
1783 msr_bitmap = vmx_msr_bitmap_longmode;
1784 else
1785 msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788 }
e38aea3e
AK		 1789}
1790
6aa8b732
AK		 1791/*
1792 * reads and returns guest's timestamp counter "register"
1793 * guest_tsc = host_tsc + tsc_offset -- 21.3
1794 */
1795static u64 guest_read_tsc(void)
1796{
1797 u64 host_tsc, tsc_offset;
1798
1799 rdtscll(host_tsc);
1800 tsc_offset = vmcs_read64(TSC_OFFSET);
1801 return host_tsc + tsc_offset;
1802}
1803
d5c1785d
NHE		 1804/*
1805 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806 * counter, even if a nested guest (L2) is currently running.
1807 */
1808u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809{
1810 u64 host_tsc, tsc_offset;
1811
1812 rdtscll(host_tsc);
1813 tsc_offset = is_guest_mode(vcpu) ?
1814 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815 vmcs_read64(TSC_OFFSET);
1816 return host_tsc + tsc_offset;
1817}
1818
4051b188
JR		 1819/*
1820 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821 * ioctl. In this case the call-back should update internal vmx state to make
1822 * the changes effective.
1823 */
1824static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1825{
1826 /* Nothing to do here */
1827}
1828
6aa8b732 1829/*
99e3e30a 1830 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1831 */
99e3e30a 1832static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1833{
27fc51b2 1834 if (is_guest_mode(vcpu)) {
7991825b 1835 /*
27fc51b2
NHE		 1836 * We're here if L1 chose not to trap WRMSR to TSC. According
1837 * to the spec, this should set L1's TSC; The offset that L1
1838 * set for L2 remains unchanged, and still needs to be added
1839 * to the newly set TSC to get L2's TSC.
7991825b 1840 */
27fc51b2
NHE		 1841 struct vmcs12 *vmcs12;
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843 /* recalculate vmcs02.TSC_OFFSET: */
1844 vmcs12 = get_vmcs12(vcpu);
1845 vmcs_write64(TSC_OFFSET, offset +
1846 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847 vmcs12->tsc_offset : 0));
1848 } else {
1849 vmcs_write64(TSC_OFFSET, offset);
1850 }
6aa8b732
AK		 1851}
1852
e48672fa
ZA		 1853static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1854{
1855 u64 offset = vmcs_read64(TSC_OFFSET);
1856 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1857 if (is_guest_mode(vcpu)) {
1858 /* Even when running L2, the adjustment needs to apply to L1 */
1859 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1860 }
e48672fa
ZA		 1861}
1862
857e4099
JR		 1863static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1864{
1865 return target_tsc - native_read_tsc();
1866}
1867
801d3424
NHE		 1868static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1869{
1870 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1872}
1873
1874/*
1875 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877 * all guests if the "nested" module option is off, and can also be disabled
1878 * for a single guest by disabling its VMX cpuid bit.
1879 */
1880static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1881{
1882 return nested && guest_cpuid_has_vmx(vcpu);
1883}
1884
b87a51ae
NHE		 1885/*
1886 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887 * returned for the various VMX controls MSRs when nested VMX is enabled.
1888 * The same values should also be used to verify that vmcs12 control fields are
1889 * valid during nested entry from L1 to L2.
1890 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892 * bit in the high half is on if the corresponding bit in the control field
1893 * may be on. See also vmx_control_verify().
1894 * TODO: allow these variables to be modified (downgraded) by module options
1895 * or other means.
1896 */
1897static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902static __init void nested_vmx_setup_ctls_msrs(void)
1903{
1904 /*
1905 * Note that as a general rule, the high half of the MSRs (bits in
1906 * the control fields which may be 1) should be initialized by the
1907 * intersection of the underlying hardware's MSR (i.e., features which
1908 * can be supported) and the list of features we want to expose -
1909 * because they are known to be properly supported in our code.
1910 * Also, usually, the low half of the MSRs (bits which must be 1) can
1911 * be set to 0, meaning that L1 may turn off any of these bits. The
1912 * reason is that if one of these bits is necessary, it will appear
1913 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914 * fields of vmcs01 and vmcs02, will turn these bits off - and
1915 * nested_vmx_exit_handled() will not pass related exits to L1.
1916 * These rules have exceptions below.
1917 */
1918
1919 /* pin-based controls */
1920 /*
1921 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1923 */
1924 nested_vmx_pinbased_ctls_low = 0x16 ;
1925 nested_vmx_pinbased_ctls_high = 0x16 |
1926 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927 PIN_BASED_VIRTUAL_NMIS;
1928
1929 /* exit controls */
1930 nested_vmx_exit_ctls_low = 0;
b6f1250e 1931 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1932#ifdef CONFIG_X86_64
1933 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1934#else
1935 nested_vmx_exit_ctls_high = 0;
1936#endif
1937
1938 /* entry controls */
1939 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941 nested_vmx_entry_ctls_low = 0;
1942 nested_vmx_entry_ctls_high &=
1943 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1944
1945 /* cpu-based controls */
1946 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948 nested_vmx_procbased_ctls_low = 0;
1949 nested_vmx_procbased_ctls_high &=
1950 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953 CPU_BASED_CR3_STORE_EXITING |
1954#ifdef CONFIG_X86_64
1955 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1956#endif
1957 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1959 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1960 /*
1961 * We can allow some features even when not supported by the
1962 * hardware. For example, L1 can specify an MSR bitmap - and we
1963 * can use it to avoid exits to L1 - even when L0 runs L2
1964 * without MSR bitmaps.
1965 */
1966 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1967
1968 /* secondary cpu-based controls */
1969 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1970 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1971 nested_vmx_secondary_ctls_low = 0;
1972 nested_vmx_secondary_ctls_high &=
1973 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1974}
1975
1976static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1977{
1978 /*
1979 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1980 */
1981 return ((control & high) | low) == control;
1982}
1983
1984static inline u64 vmx_control_msr(u32 low, u32 high)
1985{
1986 return low | ((u64)high << 32);
1987}
1988
1989/*
1990 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1991 * also let it use VMX-specific MSRs.
1992 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1993 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1994 * like all other MSRs).
1995 */
1996static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1997{
1998 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1999 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2000 /*
2001 * According to the spec, processors which do not support VMX
2002 * should throw a #GP(0) when VMX capability MSRs are read.
2003 */
2004 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2005 return 1;
2006 }
2007
2008 switch (msr_index) {
2009 case MSR_IA32_FEATURE_CONTROL:
2010 *pdata = 0;
2011 break;
2012 case MSR_IA32_VMX_BASIC:
2013 /*
2014 * This MSR reports some information about VMX support. We
2015 * should return information about the VMX we emulate for the
2016 * guest, and the VMCS structure we give it - not about the
2017 * VMX support of the underlying hardware.
2018 */
2019 *pdata = VMCS12_REVISION |
2020 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2021 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2022 break;
2023 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2024 case MSR_IA32_VMX_PINBASED_CTLS:
2025 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2026 nested_vmx_pinbased_ctls_high);
2027 break;
2028 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2029 case MSR_IA32_VMX_PROCBASED_CTLS:
2030 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2031 nested_vmx_procbased_ctls_high);
2032 break;
2033 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2034 case MSR_IA32_VMX_EXIT_CTLS:
2035 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2036 nested_vmx_exit_ctls_high);
2037 break;
2038 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2039 case MSR_IA32_VMX_ENTRY_CTLS:
2040 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2041 nested_vmx_entry_ctls_high);
2042 break;
2043 case MSR_IA32_VMX_MISC:
2044 *pdata = 0;
2045 break;
2046 /*
2047 * These MSRs specify bits which the guest must keep fixed (on or off)
2048 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2049 * We picked the standard core2 setting.
2050 */
2051#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2052#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2053 case MSR_IA32_VMX_CR0_FIXED0:
2054 *pdata = VMXON_CR0_ALWAYSON;
2055 break;
2056 case MSR_IA32_VMX_CR0_FIXED1:
2057 *pdata = -1ULL;
2058 break;
2059 case MSR_IA32_VMX_CR4_FIXED0:
2060 *pdata = VMXON_CR4_ALWAYSON;
2061 break;
2062 case MSR_IA32_VMX_CR4_FIXED1:
2063 *pdata = -1ULL;
2064 break;
2065 case MSR_IA32_VMX_VMCS_ENUM:
2066 *pdata = 0x1f;
2067 break;
2068 case MSR_IA32_VMX_PROCBASED_CTLS2:
2069 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2070 nested_vmx_secondary_ctls_high);
2071 break;
2072 case MSR_IA32_VMX_EPT_VPID_CAP:
2073 /* Currently, no nested ept or nested vpid */
2074 *pdata = 0;
2075 break;
2076 default:
2077 return 0;
2078 }
2079
2080 return 1;
2081}
2082
2083static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2084{
2085 if (!nested_vmx_allowed(vcpu))
2086 return 0;
2087
2088 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2089 /* TODO: the right thing. */
2090 return 1;
2091 /*
2092 * No need to treat VMX capability MSRs specially: If we don't handle
2093 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2094 */
2095 return 0;
2096}
2097
6aa8b732
AK		 2098/*
2099 * Reads an msr value (of 'msr_index') into 'pdata'.
2100 * Returns 0 on success, non-0 otherwise.
2101 * Assumes vcpu_load() was already called.
2102 */
2103static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2104{
2105 u64 data;
26bb0981 2106 struct shared_msr_entry *msr;
6aa8b732
AK		 2107
2108 if (!pdata) {
2109 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2110 return -EINVAL;
2111 }
2112
2113 switch (msr_index) {
05b3e0c2 2114#ifdef CONFIG_X86_64
6aa8b732
AK		 2115 case MSR_FS_BASE:
2116 data = vmcs_readl(GUEST_FS_BASE);
2117 break;
2118 case MSR_GS_BASE:
2119 data = vmcs_readl(GUEST_GS_BASE);
2120 break;
44ea2b17
AK		 2121 case MSR_KERNEL_GS_BASE:
2122 vmx_load_host_state(to_vmx(vcpu));
2123 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2124 break;
26bb0981 2125#endif
6aa8b732 2126 case MSR_EFER:
3bab1f5d 2127 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2128 case MSR_IA32_TSC:
6aa8b732
AK		 2129 data = guest_read_tsc();
2130 break;
2131 case MSR_IA32_SYSENTER_CS:
2132 data = vmcs_read32(GUEST_SYSENTER_CS);
2133 break;
2134 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2135 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2136 break;
2137 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2138 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2139 break;
4e47c7a6
SY		 2140 case MSR_TSC_AUX:
2141 if (!to_vmx(vcpu)->rdtscp_enabled)
2142 return 1;
2143 /* Otherwise falls through */
6aa8b732 2144 default:
b87a51ae
NHE		 2145 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2146 return 0;
8b9cf98c 2147 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2148 if (msr) {
2149 data = msr->data;
2150 break;
6aa8b732 2151 }
3bab1f5d 2152 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2153 }
2154
2155 *pdata = data;
2156 return 0;
2157}
2158
2159/*
2160 * Writes msr value into into the appropriate "register".
2161 * Returns 0 on success, non-0 otherwise.
2162 * Assumes vcpu_load() was already called.
2163 */
2164static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2165{
a2fa3e9f 2166 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2167 struct shared_msr_entry *msr;
2cc51560
ED		 2168 int ret = 0;
2169
6aa8b732 2170 switch (msr_index) {
3bab1f5d 2171 case MSR_EFER:
2cc51560 2172 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2173 break;
16175a79 2174#ifdef CONFIG_X86_64
6aa8b732 2175 case MSR_FS_BASE:
2fb92db1 2176 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2177 vmcs_writel(GUEST_FS_BASE, data);
2178 break;
2179 case MSR_GS_BASE:
2fb92db1 2180 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2181 vmcs_writel(GUEST_GS_BASE, data);
2182 break;
44ea2b17
AK		 2183 case MSR_KERNEL_GS_BASE:
2184 vmx_load_host_state(vmx);
2185 vmx->msr_guest_kernel_gs_base = data;
2186 break;
6aa8b732
AK		 2187#endif
2188 case MSR_IA32_SYSENTER_CS:
2189 vmcs_write32(GUEST_SYSENTER_CS, data);
2190 break;
2191 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2192 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2193 break;
2194 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2195 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2196 break;
af24a4e4 2197 case MSR_IA32_TSC:
99e3e30a 2198 kvm_write_tsc(vcpu, data);
6aa8b732 2199 break;
468d472f
SY		 2200 case MSR_IA32_CR_PAT:
2201 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2202 vmcs_write64(GUEST_IA32_PAT, data);
2203 vcpu->arch.pat = data;
2204 break;
2205 }
4e47c7a6
SY		 2206 ret = kvm_set_msr_common(vcpu, msr_index, data);
2207 break;
2208 case MSR_TSC_AUX:
2209 if (!vmx->rdtscp_enabled)
2210 return 1;
2211 /* Check reserved bit, higher 32 bits should be zero */
2212 if ((data >> 32) != 0)
2213 return 1;
2214 /* Otherwise falls through */
6aa8b732 2215 default:
b87a51ae
NHE		 2216 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2217 break;
8b9cf98c 2218 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2219 if (msr) {
2220 msr->data = data;
2221 break;
6aa8b732 2222 }
2cc51560 2223 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2224 }
2225
2cc51560 2226 return ret;
6aa8b732
AK		 2227}
2228
5fdbf976 2229static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2230{
5fdbf976
MT		 2231 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2232 switch (reg) {
2233 case VCPU_REGS_RSP:
2234 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2235 break;
2236 case VCPU_REGS_RIP:
2237 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2238 break;
6de4f3ad
AK		 2239 case VCPU_EXREG_PDPTR:
2240 if (enable_ept)
2241 ept_save_pdptrs(vcpu);
2242 break;
5fdbf976
MT		 2243 default:
2244 break;
2245 }
6aa8b732
AK		 2246}
2247
355be0b9 2248static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2249{
ae675ef0
JK		 2250 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2251 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2252 else
2253 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2254
abd3f2d6 2255 update_exception_bitmap(vcpu);
6aa8b732
AK		 2256}
2257
2258static __init int cpu_has_kvm_support(void)
2259{
6210e37b 2260 return cpu_has_vmx();
6aa8b732
AK		 2261}
2262
2263static __init int vmx_disabled_by_bios(void)
2264{
2265 u64 msr;
2266
2267 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2268 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2269 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2270 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2271 && tboot_enabled())
2272 return 1;
23f3e991 2273 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2274 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2275 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2276 && !tboot_enabled()) {
2277 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2278 "activate TXT before enabling KVM\n");
cafd6659 2279 return 1;
f9335afe 2280 }
23f3e991
JC		 2281 /* launched w/o TXT and VMX disabled */
2282 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2283 && !tboot_enabled())
2284 return 1;
cafd6659
SW		 2285 }
2286
2287 return 0;
6aa8b732
AK		 2288}
2289
7725b894
DX		 2290static void kvm_cpu_vmxon(u64 addr)
2291{
2292 asm volatile (ASM_VMX_VMXON_RAX
2293 : : "a"(&addr), "m"(addr)
2294 : "memory", "cc");
2295}
2296
10474ae8 2297static int hardware_enable(void *garbage)
6aa8b732
AK		 2298{
2299 int cpu = raw_smp_processor_id();
2300 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2301 u64 old, test_bits;
6aa8b732 2302
10474ae8
AG		 2303 if (read_cr4() & X86_CR4_VMXE)
2304 return -EBUSY;
2305
d462b819 2306 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2307 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2308
2309 test_bits = FEATURE_CONTROL_LOCKED;
2310 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2311 if (tboot_enabled())
2312 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2313
2314 if ((old & test_bits) != test_bits) {
6aa8b732 2315 /* enable and lock */
cafd6659
SW		 2316 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2317 }
66aee91a 2318 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2319
4610c9cc
DX		 2320 if (vmm_exclusive) {
2321 kvm_cpu_vmxon(phys_addr);
2322 ept_sync_global();
2323 }
10474ae8 2324
3444d7da
AK		 2325 store_gdt(&__get_cpu_var(host_gdt));
2326
10474ae8 2327 return 0;
6aa8b732
AK		 2328}
2329
d462b819 2330static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2331{
2332 int cpu = raw_smp_processor_id();
d462b819 2333 struct loaded_vmcs *v, *n;
543e4243 2334
d462b819
NHE		 2335 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2336 loaded_vmcss_on_cpu_link)
2337 __loaded_vmcs_clear(v);
543e4243
AK		 2338}
2339
710ff4a8
EH		 2340
2341/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2342 * tricks.
2343 */
2344static void kvm_cpu_vmxoff(void)
6aa8b732 2345{
4ecac3fd 2346 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2347}
2348
710ff4a8
EH		 2349static void hardware_disable(void *garbage)
2350{
4610c9cc 2351 if (vmm_exclusive) {
d462b819 2352 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2353 kvm_cpu_vmxoff();
2354 }
7725b894 2355 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2356}
2357
1c3d14fe 2358static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2359 u32 msr, u32 *result)
1c3d14fe
YS		 2360{
2361 u32 vmx_msr_low, vmx_msr_high;
2362 u32 ctl = ctl_min | ctl_opt;
2363
2364 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2365
2366 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2367 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2368
2369 /* Ensure minimum (required) set of control bits are supported. */
2370 if (ctl_min & ~ctl)
002c7f7c 2371 return -EIO;
1c3d14fe
YS		 2372
2373 *result = ctl;
2374 return 0;
2375}
2376
110312c8
AK		 2377static __init bool allow_1_setting(u32 msr, u32 ctl)
2378{
2379 u32 vmx_msr_low, vmx_msr_high;
2380
2381 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2382 return vmx_msr_high & ctl;
2383}
2384
002c7f7c 2385static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2386{
2387 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2388 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2389 u32 _pin_based_exec_control = 0;
2390 u32 _cpu_based_exec_control = 0;
f78e0e2e 2391 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2392 u32 _vmexit_control = 0;
2393 u32 _vmentry_control = 0;
2394
2395 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2396 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2397 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2398 &_pin_based_exec_control) < 0)
002c7f7c 2399 return -EIO;
1c3d14fe 2400
443381a8 2401 min =
1c3d14fe
YS		 2402#ifdef CONFIG_X86_64
2403 CPU_BASED_CR8_LOAD_EXITING |
2404 CPU_BASED_CR8_STORE_EXITING |
2405#endif
d56f546d
SY		 2406 CPU_BASED_CR3_LOAD_EXITING |
2407 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2408 CPU_BASED_USE_IO_BITMAPS |
2409 CPU_BASED_MOV_DR_EXITING |
a7052897 2410 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2411 CPU_BASED_MWAIT_EXITING |
2412 CPU_BASED_MONITOR_EXITING |
a7052897 2413 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2414
2415 if (yield_on_hlt)
2416 min |= CPU_BASED_HLT_EXITING;
2417
f78e0e2e 2418 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2419 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2420 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2421 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2422 &_cpu_based_exec_control) < 0)
002c7f7c 2423 return -EIO;
6e5d865c
YS		 2424#ifdef CONFIG_X86_64
2425 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2426 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2427 ~CPU_BASED_CR8_STORE_EXITING;
2428#endif
f78e0e2e 2429 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2430 min2 = 0;
2431 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2432 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2433 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2434 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2435 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2436 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2437 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2438 if (adjust_vmx_controls(min2, opt2,
2439 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2440 &_cpu_based_2nd_exec_control) < 0)
2441 return -EIO;
2442 }
2443#ifndef CONFIG_X86_64
2444 if (!(_cpu_based_2nd_exec_control &
2445 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2446 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2447#endif
d56f546d 2448 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2449 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2450 enabled */
5fff7d27
GN		 2451 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2452 CPU_BASED_CR3_STORE_EXITING |
2453 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2454 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2455 vmx_capability.ept, vmx_capability.vpid);
2456 }
1c3d14fe
YS		 2457
2458 min = 0;
2459#ifdef CONFIG_X86_64
2460 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2461#endif
468d472f 2462 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2463 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2464 &_vmexit_control) < 0)
002c7f7c 2465 return -EIO;
1c3d14fe 2466
468d472f
SY		 2467 min = 0;
2468 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2469 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2470 &_vmentry_control) < 0)
002c7f7c 2471 return -EIO;
6aa8b732 2472
c68876fd 2473 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2474
2475 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2476 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2477 return -EIO;
1c3d14fe
YS		 2478
2479#ifdef CONFIG_X86_64
2480 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2481 if (vmx_msr_high & (1u<<16))
002c7f7c 2482 return -EIO;
1c3d14fe
YS		 2483#endif
2484
2485 /* Require Write-Back (WB) memory type for VMCS accesses. */
2486 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2487 return -EIO;
1c3d14fe 2488
002c7f7c
YS		 2489 vmcs_conf->size = vmx_msr_high & 0x1fff;
2490 vmcs_conf->order = get_order(vmcs_config.size);
2491 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2492
002c7f7c
YS		 2493 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2494 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2495 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2496 vmcs_conf->vmexit_ctrl = _vmexit_control;
2497 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2498
110312c8
AK		 2499 cpu_has_load_ia32_efer =
2500 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2501 VM_ENTRY_LOAD_IA32_EFER)
2502 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2503 VM_EXIT_LOAD_IA32_EFER);
2504
8bf00a52
GN		 2505 cpu_has_load_perf_global_ctrl =
2506 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2507 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2508 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2509 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2510
2511 /*
2512 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2513 * but due to arrata below it can't be used. Workaround is to use
2514 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2515 *
2516 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2517 *
2518 * AAK155 (model 26)
2519 * AAP115 (model 30)
2520 * AAT100 (model 37)
2521 * BC86,AAY89,BD102 (model 44)
2522 * BA97 (model 46)
2523 *
2524 */
2525 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2526 switch (boot_cpu_data.x86_model) {
2527 case 26:
2528 case 30:
2529 case 37:
2530 case 44:
2531 case 46:
2532 cpu_has_load_perf_global_ctrl = false;
2533 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2534 "does not work properly. Using workaround\n");
2535 break;
2536 default:
2537 break;
2538 }
2539 }
2540
1c3d14fe 2541 return 0;
c68876fd 2542}
6aa8b732
AK		 2543
2544static struct vmcs *alloc_vmcs_cpu(int cpu)
2545{
2546 int node = cpu_to_node(cpu);
2547 struct page *pages;
2548 struct vmcs *vmcs;
2549
6484eb3e 2550 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2551 if (!pages)
2552 return NULL;
2553 vmcs = page_address(pages);
1c3d14fe
YS		 2554 memset(vmcs, 0, vmcs_config.size);
2555 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2556 return vmcs;
2557}
2558
2559static struct vmcs *alloc_vmcs(void)
2560{
d3b2c338 2561 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2562}
2563
2564static void free_vmcs(struct vmcs *vmcs)
2565{
1c3d14fe 2566 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2567}
2568
d462b819
NHE		 2569/*
2570 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2571 */
2572static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2573{
2574 if (!loaded_vmcs->vmcs)
2575 return;
2576 loaded_vmcs_clear(loaded_vmcs);
2577 free_vmcs(loaded_vmcs->vmcs);
2578 loaded_vmcs->vmcs = NULL;
2579}
2580
39959588 2581static void free_kvm_area(void)
6aa8b732
AK		 2582{
2583 int cpu;
2584
3230bb47 2585 for_each_possible_cpu(cpu) {
6aa8b732 2586 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2587 per_cpu(vmxarea, cpu) = NULL;
2588 }
6aa8b732
AK		 2589}
2590
6aa8b732
AK		 2591static __init int alloc_kvm_area(void)
2592{
2593 int cpu;
2594
3230bb47 2595 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2596 struct vmcs *vmcs;
2597
2598 vmcs = alloc_vmcs_cpu(cpu);
2599 if (!vmcs) {
2600 free_kvm_area();
2601 return -ENOMEM;
2602 }
2603
2604 per_cpu(vmxarea, cpu) = vmcs;
2605 }
2606 return 0;
2607}
2608
2609static __init int hardware_setup(void)
2610{
002c7f7c
YS		 2611 if (setup_vmcs_config(&vmcs_config) < 0)
2612 return -EIO;
50a37eb4
JR		 2613
2614 if (boot_cpu_has(X86_FEATURE_NX))
2615 kvm_enable_efer_bits(EFER_NX);
2616
93ba03c2
SY		 2617 if (!cpu_has_vmx_vpid())
2618 enable_vpid = 0;
2619
4bc9b982
SY		 2620 if (!cpu_has_vmx_ept() ||
2621 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2622 enable_ept = 0;
3a624e29
NK		 2623 enable_unrestricted_guest = 0;
2624 }
2625
2626 if (!cpu_has_vmx_unrestricted_guest())
2627 enable_unrestricted_guest = 0;
93ba03c2
SY		 2628
2629 if (!cpu_has_vmx_flexpriority())
2630 flexpriority_enabled = 0;
2631
95ba8273
GN		 2632 if (!cpu_has_vmx_tpr_shadow())
2633 kvm_x86_ops->update_cr8_intercept = NULL;
2634
54dee993
MT		 2635 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2636 kvm_disable_largepages();
2637
4b8d54f9
ZE		 2638 if (!cpu_has_vmx_ple())
2639 ple_gap = 0;
2640
b87a51ae
NHE		 2641 if (nested)
2642 nested_vmx_setup_ctls_msrs();
2643
6aa8b732
AK		 2644 return alloc_kvm_area();
2645}
2646
2647static __exit void hardware_unsetup(void)
2648{
2649 free_kvm_area();
2650}
2651
6aa8b732
AK		 2652static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2653{
2654 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2655
6af11b9e 2656 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2657 vmcs_write16(sf->selector, save->selector);
2658 vmcs_writel(sf->base, save->base);
2659 vmcs_write32(sf->limit, save->limit);
2660 vmcs_write32(sf->ar_bytes, save->ar);
2661 } else {
2662 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2663 << AR_DPL_SHIFT;
2664 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2665 }
2666}
2667
2668static void enter_pmode(struct kvm_vcpu *vcpu)
2669{
2670 unsigned long flags;
a89a8fb9 2671 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2672
a89a8fb9 2673 vmx->emulation_required = 1;
7ffd92c5 2674 vmx->rmode.vm86_active = 0;
6aa8b732 2675
2fb92db1
AK		 2676 vmx_segment_cache_clear(vmx);
2677
d0ba64f9 2678 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2679 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2680 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2681 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2682
2683 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2684 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2685 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2686 vmcs_writel(GUEST_RFLAGS, flags);
2687
66aee91a
RR		 2688 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2689 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2690
2691 update_exception_bitmap(vcpu);
2692
a89a8fb9
MG		 2693 if (emulate_invalid_guest_state)
2694 return;
2695
7ffd92c5
AK		 2696 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2697 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2698 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2699 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2700
2fb92db1
AK		 2701 vmx_segment_cache_clear(vmx);
2702
6aa8b732
AK		 2703 vmcs_write16(GUEST_SS_SELECTOR, 0);
2704 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2705
2706 vmcs_write16(GUEST_CS_SELECTOR,
2707 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2708 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2709}
2710
d77c26fc 2711static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2712{
bfc6d222 2713 if (!kvm->arch.tss_addr) {
bc6678a3 2714 struct kvm_memslots *slots;
28a37544 2715 struct kvm_memory_slot *slot;
bc6678a3
MT		 2716 gfn_t base_gfn;
2717
90d83dc3 2718 slots = kvm_memslots(kvm);
28a37544
XG		 2719 slot = id_to_memslot(slots, 0);
2720 base_gfn = slot->base_gfn + slot->npages - 3;
2721
cbc94022
IE		 2722 return base_gfn << PAGE_SHIFT;
2723 }
bfc6d222 2724 return kvm->arch.tss_addr;
6aa8b732
AK		 2725}
2726
2727static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2728{
2729 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2730
2731 save->selector = vmcs_read16(sf->selector);
2732 save->base = vmcs_readl(sf->base);
2733 save->limit = vmcs_read32(sf->limit);
2734 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2735 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2736 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2737 vmcs_write32(sf->limit, 0xffff);
2738 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2739 if (save->base & 0xf)
2740 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2741 " aligned when entering protected mode (seg=%d)",
2742 seg);
6aa8b732
AK		 2743}
2744
2745static void enter_rmode(struct kvm_vcpu *vcpu)
2746{
2747 unsigned long flags;
a89a8fb9 2748 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2749
3a624e29
NK		 2750 if (enable_unrestricted_guest)
2751 return;
2752
a89a8fb9 2753 vmx->emulation_required = 1;
7ffd92c5 2754 vmx->rmode.vm86_active = 1;
6aa8b732 2755
776e58ea
GN		 2756 /*
2757 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2758 * vcpu. Call it here with phys address pointing 16M below 4G.
2759 */
2760 if (!vcpu->kvm->arch.tss_addr) {
2761 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2762 "called before entering vcpu\n");
2763 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2764 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2765 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2766 }
2767
2fb92db1
AK		 2768 vmx_segment_cache_clear(vmx);
2769
d0ba64f9 2770 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2771 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2772 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2773
7ffd92c5 2774 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2775 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2776
7ffd92c5 2777 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2778 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2779
2780 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2781 vmx->rmode.save_rflags = flags;
6aa8b732 2782
053de044 2783 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2784
2785 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2786 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2787 update_exception_bitmap(vcpu);
2788
a89a8fb9
MG		 2789 if (emulate_invalid_guest_state)
2790 goto continue_rmode;
2791
6aa8b732
AK		 2792 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2793 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2794 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2795
2796 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2797 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2798 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2799 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2800 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2801
7ffd92c5
AK		 2802 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2803 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2804 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2805 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2806
a89a8fb9 2807continue_rmode:
8668a3c4 2808 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2809}
2810
401d10de
AS		 2811static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2812{
2813 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2814 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2815
2816 if (!msr)
2817 return;
401d10de 2818
44ea2b17
AK		 2819 /*
2820 * Force kernel_gs_base reloading before EFER changes, as control
2821 * of this msr depends on is_long_mode().
2822 */
2823 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2824 vcpu->arch.efer = efer;
401d10de
AS		 2825 if (efer & EFER_LMA) {
2826 vmcs_write32(VM_ENTRY_CONTROLS,
2827 vmcs_read32(VM_ENTRY_CONTROLS) |
2828 VM_ENTRY_IA32E_MODE);
2829 msr->data = efer;
2830 } else {
2831 vmcs_write32(VM_ENTRY_CONTROLS,
2832 vmcs_read32(VM_ENTRY_CONTROLS) &
2833 ~VM_ENTRY_IA32E_MODE);
2834
2835 msr->data = efer & ~EFER_LME;
2836 }
2837 setup_msrs(vmx);
2838}
2839
05b3e0c2 2840#ifdef CONFIG_X86_64
6aa8b732
AK		 2841
2842static void enter_lmode(struct kvm_vcpu *vcpu)
2843{
2844 u32 guest_tr_ar;
2845
2fb92db1
AK		 2846 vmx_segment_cache_clear(to_vmx(vcpu));
2847
6aa8b732
AK		 2848 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2849 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2850 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2851 __func__);
6aa8b732
AK		 2852 vmcs_write32(GUEST_TR_AR_BYTES,
2853 (guest_tr_ar & ~AR_TYPE_MASK)
2854 | AR_TYPE_BUSY_64_TSS);
2855 }
da38f438 2856 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2857}
2858
2859static void exit_lmode(struct kvm_vcpu *vcpu)
2860{
6aa8b732
AK		 2861 vmcs_write32(VM_ENTRY_CONTROLS,
2862 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2863 & ~VM_ENTRY_IA32E_MODE);
da38f438 2864 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2865}
2866
2867#endif
2868
2384d2b3
SY		 2869static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2870{
b9d762fa 2871 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2872 if (enable_ept) {
2873 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2874 return;
4e1096d2 2875 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2876 }
2384d2b3
SY		 2877}
2878
e8467fda
AK		 2879static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2880{
2881 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2882
2883 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2884 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2885}
2886
aff48baa
AK		 2887static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2888{
2889 if (enable_ept && is_paging(vcpu))
2890 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2891 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2892}
2893
25c4c276 2894static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2895{
fc78f519
AK		 2896 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2897
2898 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2899 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2900}
2901
1439442c
SY		 2902static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2903{
6de4f3ad
AK		 2904 if (!test_bit(VCPU_EXREG_PDPTR,
2905 (unsigned long *)&vcpu->arch.regs_dirty))
2906 return;
2907
1439442c 2908 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2909 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2910 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2911 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2912 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2913 }
2914}
2915
8f5d549f
AK		 2916static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2917{
2918 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2919 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2920 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2921 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2922 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2923 }
6de4f3ad
AK		 2924
2925 __set_bit(VCPU_EXREG_PDPTR,
2926 (unsigned long *)&vcpu->arch.regs_avail);
2927 __set_bit(VCPU_EXREG_PDPTR,
2928 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2929}
2930
5e1746d6 2931static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2932
2933static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2934 unsigned long cr0,
2935 struct kvm_vcpu *vcpu)
2936{
5233dd51
MT		 2937 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2938 vmx_decache_cr3(vcpu);
1439442c
SY		 2939 if (!(cr0 & X86_CR0_PG)) {
2940 /* From paging/starting to nonpaging */
2941 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2942 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2943 (CPU_BASED_CR3_LOAD_EXITING |
2944 CPU_BASED_CR3_STORE_EXITING));
2945 vcpu->arch.cr0 = cr0;
fc78f519 2946 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2947 } else if (!is_paging(vcpu)) {
2948 /* From nonpaging to paging */
2949 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2950 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2951 ~(CPU_BASED_CR3_LOAD_EXITING |
2952 CPU_BASED_CR3_STORE_EXITING));
2953 vcpu->arch.cr0 = cr0;
fc78f519 2954 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2955 }
95eb84a7
SY		 2956
2957 if (!(cr0 & X86_CR0_WP))
2958 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2959}
2960
6aa8b732
AK		 2961static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2962{
7ffd92c5 2963 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2964 unsigned long hw_cr0;
2965
2966 if (enable_unrestricted_guest)
2967 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2968 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2969 else
2970 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2971
7ffd92c5 2972 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2973 enter_pmode(vcpu);
2974
7ffd92c5 2975 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2976 enter_rmode(vcpu);
2977
05b3e0c2 2978#ifdef CONFIG_X86_64
f6801dff 2979 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2980 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2981 enter_lmode(vcpu);
707d92fa 2982 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2983 exit_lmode(vcpu);
2984 }
2985#endif
2986
089d034e 2987 if (enable_ept)
1439442c
SY		 2988 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2989
02daab21 2990 if (!vcpu->fpu_active)
81231c69 2991 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2992
6aa8b732 2993 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2994 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2995 vcpu->arch.cr0 = cr0;
69c73028 2996 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2997}
2998
1439442c
SY		 2999static u64 construct_eptp(unsigned long root_hpa)
3000{
3001 u64 eptp;
3002
3003 /* TODO write the value reading from MSR */
3004 eptp = VMX_EPT_DEFAULT_MT |
3005 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3006 eptp |= (root_hpa & PAGE_MASK);
3007
3008 return eptp;
3009}
3010
6aa8b732
AK		 3011static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3012{
1439442c
SY		 3013 unsigned long guest_cr3;
3014 u64 eptp;
3015
3016 guest_cr3 = cr3;
089d034e 3017 if (enable_ept) {
1439442c
SY		 3018 eptp = construct_eptp(cr3);
3019 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3020 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3021 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3022 ept_load_pdptrs(vcpu);
1439442c
SY		 3023 }
3024
2384d2b3 3025 vmx_flush_tlb(vcpu);
1439442c 3026 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3027}
3028
5e1746d6 3029static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3030{
7ffd92c5 3031 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3032 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3033
5e1746d6
NHE		 3034 if (cr4 & X86_CR4_VMXE) {
3035 /*
3036 * To use VMXON (and later other VMX instructions), a guest
3037 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3038 * So basically the check on whether to allow nested VMX
3039 * is here.
3040 */
3041 if (!nested_vmx_allowed(vcpu))
3042 return 1;
3043 } else if (to_vmx(vcpu)->nested.vmxon)
3044 return 1;
3045
ad312c7c 3046 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3047 if (enable_ept) {
3048 if (!is_paging(vcpu)) {
3049 hw_cr4 &= ~X86_CR4_PAE;
3050 hw_cr4 |= X86_CR4_PSE;
3051 } else if (!(cr4 & X86_CR4_PAE)) {
3052 hw_cr4 &= ~X86_CR4_PAE;
3053 }
3054 }
1439442c
SY		 3055
3056 vmcs_writel(CR4_READ_SHADOW, cr4);
3057 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3058 return 0;
6aa8b732
AK		 3059}
3060
6aa8b732
AK		 3061static void vmx_get_segment(struct kvm_vcpu *vcpu,
3062 struct kvm_segment *var, int seg)
3063{
a9179499 3064 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3065 struct kvm_save_segment *save;
6aa8b732
AK		 3066 u32 ar;
3067
a9179499
AK		 3068 if (vmx->rmode.vm86_active
3069 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3070 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3071 || seg == VCPU_SREG_GS)
3072 && !emulate_invalid_guest_state) {
3073 switch (seg) {
3074 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3075 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3076 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3077 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3078 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3079 default: BUG();
3080 }
3081 var->selector = save->selector;
3082 var->base = save->base;
3083 var->limit = save->limit;
3084 ar = save->ar;
3085 if (seg == VCPU_SREG_TR
2fb92db1 3086 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3087 goto use_saved_rmode_seg;
3088 }
2fb92db1
AK		 3089 var->base = vmx_read_guest_seg_base(vmx, seg);
3090 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3091 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3092 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3093use_saved_rmode_seg:
9fd4a3b7 3094 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3095 ar = 0;
3096 var->type = ar & 15;
3097 var->s = (ar >> 4) & 1;
3098 var->dpl = (ar >> 5) & 3;
3099 var->present = (ar >> 7) & 1;
3100 var->avl = (ar >> 12) & 1;
3101 var->l = (ar >> 13) & 1;
3102 var->db = (ar >> 14) & 1;
3103 var->g = (ar >> 15) & 1;
3104 var->unusable = (ar >> 16) & 1;
3105}
3106
a9179499
AK		 3107static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3108{
a9179499
AK		 3109 struct kvm_segment s;
3110
3111 if (to_vmx(vcpu)->rmode.vm86_active) {
3112 vmx_get_segment(vcpu, &s, seg);
3113 return s.base;
3114 }
2fb92db1 3115 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3116}
3117
69c73028 3118static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3119{
3eeb3288 3120 if (!is_protmode(vcpu))
2e4d2653
IE		 3121 return 0;
3122
f4c63e5d
AK		 3123 if (!is_long_mode(vcpu)
3124 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3125 return 3;
3126
2fb92db1 3127 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3128}
3129
69c73028
AK		 3130static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3131{
3132 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3133 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3134 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3135 }
3136 return to_vmx(vcpu)->cpl;
3137}
3138
3139
653e3108 3140static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3141{
6aa8b732
AK		 3142 u32 ar;
3143
653e3108 3144 if (var->unusable)
6aa8b732
AK		 3145 ar = 1 << 16;
3146 else {
3147 ar = var->type & 15;
3148 ar |= (var->s & 1) << 4;
3149 ar |= (var->dpl & 3) << 5;
3150 ar |= (var->present & 1) << 7;
3151 ar |= (var->avl & 1) << 12;
3152 ar |= (var->l & 1) << 13;
3153 ar |= (var->db & 1) << 14;
3154 ar |= (var->g & 1) << 15;
3155 }
f7fbf1fd
UL		 3156 if (ar == 0) /* a 0 value means unusable */
3157 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3158
3159 return ar;
3160}
3161
3162static void vmx_set_segment(struct kvm_vcpu *vcpu,
3163 struct kvm_segment *var, int seg)
3164{
7ffd92c5 3165 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3166 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3167 u32 ar;
3168
2fb92db1
AK		 3169 vmx_segment_cache_clear(vmx);
3170
7ffd92c5 3171 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3172 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3173 vmx->rmode.tr.selector = var->selector;
3174 vmx->rmode.tr.base = var->base;
3175 vmx->rmode.tr.limit = var->limit;
3176 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3177 return;
3178 }
3179 vmcs_writel(sf->base, var->base);
3180 vmcs_write32(sf->limit, var->limit);
3181 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3182 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3183 /*
3184 * Hack real-mode segments into vm86 compatibility.
3185 */
3186 if (var->base == 0xffff0000 && var->selector == 0xf000)
3187 vmcs_writel(sf->base, 0xf0000);
3188 ar = 0xf3;
3189 } else
3190 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3191
3192 /*
3193 * Fix the "Accessed" bit in AR field of segment registers for older
3194 * qemu binaries.
3195 * IA32 arch specifies that at the time of processor reset the
3196 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3197 * is setting it to 0 in the usedland code. This causes invalid guest
3198 * state vmexit when "unrestricted guest" mode is turned on.
3199 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3200 * tree. Newer qemu binaries with that qemu fix would not need this
3201 * kvm hack.
3202 */
3203 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3204 ar |= 0x1; /* Accessed */
3205
6aa8b732 3206 vmcs_write32(sf->ar_bytes, ar);
69c73028 3207 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3208}
3209
6aa8b732
AK		 3210static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3211{
2fb92db1 3212 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3213
3214 *db = (ar >> 14) & 1;
3215 *l = (ar >> 13) & 1;
3216}
3217
89a27f4d 3218static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3219{
89a27f4d
GN		 3220 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3221 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3222}
3223
89a27f4d 3224static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3225{
89a27f4d
GN		 3226 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3227 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3228}
3229
89a27f4d 3230static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3231{
89a27f4d
GN		 3232 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3233 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3234}
3235
89a27f4d 3236static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3237{
89a27f4d
GN		 3238 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3239 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3240}
3241
648dfaa7
MG		 3242static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3243{
3244 struct kvm_segment var;
3245 u32 ar;
3246
3247 vmx_get_segment(vcpu, &var, seg);
3248 ar = vmx_segment_access_rights(&var);
3249
3250 if (var.base != (var.selector << 4))
3251 return false;
3252 if (var.limit != 0xffff)
3253 return false;
3254 if (ar != 0xf3)
3255 return false;
3256
3257 return true;
3258}
3259
3260static bool code_segment_valid(struct kvm_vcpu *vcpu)
3261{
3262 struct kvm_segment cs;
3263 unsigned int cs_rpl;
3264
3265 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3266 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3267
1872a3f4
AK		 3268 if (cs.unusable)
3269 return false;
648dfaa7
MG		 3270 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3271 return false;
3272 if (!cs.s)
3273 return false;
1872a3f4 3274 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3275 if (cs.dpl > cs_rpl)
3276 return false;
1872a3f4 3277 } else {
648dfaa7
MG		 3278 if (cs.dpl != cs_rpl)
3279 return false;
3280 }
3281 if (!cs.present)
3282 return false;
3283
3284 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3285 return true;
3286}
3287
3288static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3289{
3290 struct kvm_segment ss;
3291 unsigned int ss_rpl;
3292
3293 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3294 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3295
1872a3f4
AK		 3296 if (ss.unusable)
3297 return true;
3298 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3299 return false;
3300 if (!ss.s)
3301 return false;
3302 if (ss.dpl != ss_rpl) /* DPL != RPL */
3303 return false;
3304 if (!ss.present)
3305 return false;
3306
3307 return true;
3308}
3309
3310static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3311{
3312 struct kvm_segment var;
3313 unsigned int rpl;
3314
3315 vmx_get_segment(vcpu, &var, seg);
3316 rpl = var.selector & SELECTOR_RPL_MASK;
3317
1872a3f4
AK		 3318 if (var.unusable)
3319 return true;
648dfaa7
MG		 3320 if (!var.s)
3321 return false;
3322 if (!var.present)
3323 return false;
3324 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3325 if (var.dpl < rpl) /* DPL < RPL */
3326 return false;
3327 }
3328
3329 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3330 * rights flags
3331 */
3332 return true;
3333}
3334
3335static bool tr_valid(struct kvm_vcpu *vcpu)
3336{
3337 struct kvm_segment tr;
3338
3339 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3340
1872a3f4
AK		 3341 if (tr.unusable)
3342 return false;
648dfaa7
MG		 3343 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3344 return false;
1872a3f4 3345 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3346 return false;
3347 if (!tr.present)
3348 return false;
3349
3350 return true;
3351}
3352
3353static bool ldtr_valid(struct kvm_vcpu *vcpu)
3354{
3355 struct kvm_segment ldtr;
3356
3357 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3358
1872a3f4
AK		 3359 if (ldtr.unusable)
3360 return true;
648dfaa7
MG		 3361 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3362 return false;
3363 if (ldtr.type != 2)
3364 return false;
3365 if (!ldtr.present)
3366 return false;
3367
3368 return true;
3369}
3370
3371static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3372{
3373 struct kvm_segment cs, ss;
3374
3375 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3376 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3377
3378 return ((cs.selector & SELECTOR_RPL_MASK) ==
3379 (ss.selector & SELECTOR_RPL_MASK));
3380}
3381
3382/*
3383 * Check if guest state is valid. Returns true if valid, false if
3384 * not.
3385 * We assume that registers are always usable
3386 */
3387static bool guest_state_valid(struct kvm_vcpu *vcpu)
3388{
3389 /* real mode guest state checks */
3eeb3288 3390 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3391 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3392 return false;
3393 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3394 return false;
3395 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3396 return false;
3397 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3398 return false;
3399 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3400 return false;
3401 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3402 return false;
3403 } else {
3404 /* protected mode guest state checks */
3405 if (!cs_ss_rpl_check(vcpu))
3406 return false;
3407 if (!code_segment_valid(vcpu))
3408 return false;
3409 if (!stack_segment_valid(vcpu))
3410 return false;
3411 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3412 return false;
3413 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3414 return false;
3415 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3416 return false;
3417 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3418 return false;
3419 if (!tr_valid(vcpu))
3420 return false;
3421 if (!ldtr_valid(vcpu))
3422 return false;
3423 }
3424 /* TODO:
3425 * - Add checks on RIP
3426 * - Add checks on RFLAGS
3427 */
3428
3429 return true;
3430}
3431
d77c26fc 3432static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3433{
40dcaa9f 3434 gfn_t fn;
195aefde 3435 u16 data = 0;
40dcaa9f 3436 int r, idx, ret = 0;
6aa8b732 3437
40dcaa9f
XG		 3438 idx = srcu_read_lock(&kvm->srcu);
3439 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3440 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3441 if (r < 0)
10589a46 3442 goto out;
195aefde 3443 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3444 r = kvm_write_guest_page(kvm, fn++, &data,
3445 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3446 if (r < 0)
10589a46 3447 goto out;
195aefde
IE		 3448 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3449 if (r < 0)
10589a46 3450 goto out;
195aefde
IE		 3451 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3452 if (r < 0)
10589a46 3453 goto out;
195aefde 3454 data = ~0;
10589a46
MT		 3455 r = kvm_write_guest_page(kvm, fn, &data,
3456 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3457 sizeof(u8));
195aefde 3458 if (r < 0)
10589a46
MT		 3459 goto out;
3460
3461 ret = 1;
3462out:
40dcaa9f 3463 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3464 return ret;
6aa8b732
AK		 3465}
3466
b7ebfb05
SY		 3467static int init_rmode_identity_map(struct kvm *kvm)
3468{
40dcaa9f 3469 int i, idx, r, ret;
b7ebfb05
SY		 3470 pfn_t identity_map_pfn;
3471 u32 tmp;
3472
089d034e 3473 if (!enable_ept)
b7ebfb05
SY		 3474 return 1;
3475 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3476 printk(KERN_ERR "EPT: identity-mapping pagetable "
3477 "haven't been allocated!\n");
3478 return 0;
3479 }
3480 if (likely(kvm->arch.ept_identity_pagetable_done))
3481 return 1;
3482 ret = 0;
b927a3ce 3483 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3484 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3485 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3486 if (r < 0)
3487 goto out;
3488 /* Set up identity-mapping pagetable for EPT in real mode */
3489 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3490 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3491 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3492 r = kvm_write_guest_page(kvm, identity_map_pfn,
3493 &tmp, i * sizeof(tmp), sizeof(tmp));
3494 if (r < 0)
3495 goto out;
3496 }
3497 kvm->arch.ept_identity_pagetable_done = true;
3498 ret = 1;
3499out:
40dcaa9f 3500 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3501 return ret;
3502}
3503
6aa8b732
AK		 3504static void seg_setup(int seg)
3505{
3506 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3507 unsigned int ar;
6aa8b732
AK		 3508
3509 vmcs_write16(sf->selector, 0);
3510 vmcs_writel(sf->base, 0);
3511 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3512 if (enable_unrestricted_guest) {
3513 ar = 0x93;
3514 if (seg == VCPU_SREG_CS)
3515 ar |= 0x08; /* code segment */
3516 } else
3517 ar = 0xf3;
3518
3519 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3520}
3521
f78e0e2e
SY		 3522static int alloc_apic_access_page(struct kvm *kvm)
3523{
3524 struct kvm_userspace_memory_region kvm_userspace_mem;
3525 int r = 0;
3526
79fac95e 3527 mutex_lock(&kvm->slots_lock);
bfc6d222 3528 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3529 goto out;
3530 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3531 kvm_userspace_mem.flags = 0;
3532 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3533 kvm_userspace_mem.memory_size = PAGE_SIZE;
3534 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3535 if (r)
3536 goto out;
72dc67a6 3537
bfc6d222 3538 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3539out:
79fac95e 3540 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3541 return r;
3542}
3543
b7ebfb05
SY		 3544static int alloc_identity_pagetable(struct kvm *kvm)
3545{
3546 struct kvm_userspace_memory_region kvm_userspace_mem;
3547 int r = 0;
3548
79fac95e 3549 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3550 if (kvm->arch.ept_identity_pagetable)
3551 goto out;
3552 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3553 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3554 kvm_userspace_mem.guest_phys_addr =
3555 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3556 kvm_userspace_mem.memory_size = PAGE_SIZE;
3557 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3558 if (r)
3559 goto out;
3560
b7ebfb05 3561 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3562 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3563out:
79fac95e 3564 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3565 return r;
3566}
3567
2384d2b3
SY		 3568static void allocate_vpid(struct vcpu_vmx *vmx)
3569{
3570 int vpid;
3571
3572 vmx->vpid = 0;
919818ab 3573 if (!enable_vpid)
2384d2b3
SY		 3574 return;
3575 spin_lock(&vmx_vpid_lock);
3576 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3577 if (vpid < VMX_NR_VPIDS) {
3578 vmx->vpid = vpid;
3579 __set_bit(vpid, vmx_vpid_bitmap);
3580 }
3581 spin_unlock(&vmx_vpid_lock);
3582}
3583
cdbecfc3
LJ		 3584static void free_vpid(struct vcpu_vmx *vmx)
3585{
3586 if (!enable_vpid)
3587 return;
3588 spin_lock(&vmx_vpid_lock);
3589 if (vmx->vpid != 0)
3590 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3591 spin_unlock(&vmx_vpid_lock);
3592}
3593
5897297b 3594static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3595{
3e7c73e9 3596 int f = sizeof(unsigned long);
25c5f225
SY		 3597
3598 if (!cpu_has_vmx_msr_bitmap())
3599 return;
3600
3601 /*
3602 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3603 * have the write-low and read-high bitmap offsets the wrong way round.
3604 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3605 */
25c5f225 3606 if (msr <= 0x1fff) {
3e7c73e9
AK		 3607 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3608 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3609 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3610 msr &= 0x1fff;
3e7c73e9
AK		 3611 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3612 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3613 }
25c5f225
SY		 3614}
3615
5897297b
AK		 3616static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3617{
3618 if (!longmode_only)
3619 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3620 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3621}
3622
a3a8ff8e
NHE		 3623/*
3624 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3625 * will not change in the lifetime of the guest.
3626 * Note that host-state that does change is set elsewhere. E.g., host-state
3627 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3628 */
3629static void vmx_set_constant_host_state(void)
3630{
3631 u32 low32, high32;
3632 unsigned long tmpl;
3633 struct desc_ptr dt;
3634
3635 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3636 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3637 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3638
3639 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3640 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3641 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3642 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3643 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3644
3645 native_store_idt(&dt);
3646 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3647
3648 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3649 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3650
3651 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3652 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3653 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3654 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3655
3656 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3657 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3658 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3659 }
3660}
3661
bf8179a0
NHE		 3662static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3663{
3664 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3665 if (enable_ept)
3666 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3667 if (is_guest_mode(&vmx->vcpu))
3668 vmx->vcpu.arch.cr4_guest_owned_bits &=
3669 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3670 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3671}
3672
3673static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3674{
3675 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3676 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3677 exec_control &= ~CPU_BASED_TPR_SHADOW;
3678#ifdef CONFIG_X86_64
3679 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3680 CPU_BASED_CR8_LOAD_EXITING;
3681#endif
3682 }
3683 if (!enable_ept)
3684 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3685 CPU_BASED_CR3_LOAD_EXITING |
3686 CPU_BASED_INVLPG_EXITING;
3687 return exec_control;
3688}
3689
3690static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3691{
3692 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3693 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3694 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3695 if (vmx->vpid == 0)
3696 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3697 if (!enable_ept) {
3698 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3699 enable_unrestricted_guest = 0;
3700 }
3701 if (!enable_unrestricted_guest)
3702 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3703 if (!ple_gap)
3704 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3705 return exec_control;
3706}
3707
ce88decf
XG		 3708static void ept_set_mmio_spte_mask(void)
3709{
3710 /*
3711 * EPT Misconfigurations can be generated if the value of bits 2:0
3712 * of an EPT paging-structure entry is 110b (write/execute).
3713 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3714 * spte.
3715 */
3716 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3717}
3718
6aa8b732
AK		 3719/*
3720 * Sets up the vmcs for emulated real mode.
3721 */
8b9cf98c 3722static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3723{
2e4ce7f5 3724#ifdef CONFIG_X86_64
6aa8b732 3725 unsigned long a;
2e4ce7f5 3726#endif
6aa8b732 3727 int i;
6aa8b732 3728
6aa8b732 3729 /* I/O */
3e7c73e9
AK		 3730 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3731 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3732
25c5f225 3733 if (cpu_has_vmx_msr_bitmap())
5897297b 3734 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3735
6aa8b732
AK		 3736 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3737
6aa8b732 3738 /* Control */
1c3d14fe
YS		 3739 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3740 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3741
bf8179a0 3742 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3743
83ff3b9d 3744 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3745 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3746 vmx_secondary_exec_control(vmx));
83ff3b9d 3747 }
f78e0e2e 3748
4b8d54f9
ZE		 3749 if (ple_gap) {
3750 vmcs_write32(PLE_GAP, ple_gap);
3751 vmcs_write32(PLE_WINDOW, ple_window);
3752 }
3753
c3707958
XG		 3754 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3755 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3756 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3757
9581d442
AK		 3758 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3759 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3760 vmx_set_constant_host_state();
05b3e0c2 3761#ifdef CONFIG_X86_64
6aa8b732
AK		 3762 rdmsrl(MSR_FS_BASE, a);
3763 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3764 rdmsrl(MSR_GS_BASE, a);
3765 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3766#else
3767 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3768 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3769#endif
3770
2cc51560
ED		 3771 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3772 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3773 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3774 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3775 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3776
468d472f 3777 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3778 u32 msr_low, msr_high;
3779 u64 host_pat;
468d472f
SY		 3780 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3781 host_pat = msr_low | ((u64) msr_high << 32);
3782 /* Write the default value follow host pat */
3783 vmcs_write64(GUEST_IA32_PAT, host_pat);
3784 /* Keep arch.pat sync with GUEST_IA32_PAT */
3785 vmx->vcpu.arch.pat = host_pat;
3786 }
3787
6aa8b732
AK		 3788 for (i = 0; i < NR_VMX_MSR; ++i) {
3789 u32 index = vmx_msr_index[i];
3790 u32 data_low, data_high;
a2fa3e9f 3791 int j = vmx->nmsrs;
6aa8b732
AK		 3792
3793 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3794 continue;
432bd6cb
AK		 3795 if (wrmsr_safe(index, data_low, data_high) < 0)
3796 continue;
26bb0981
AK		 3797 vmx->guest_msrs[j].index = i;
3798 vmx->guest_msrs[j].data = 0;
d5696725 3799 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3800 ++vmx->nmsrs;
6aa8b732 3801 }
6aa8b732 3802
1c3d14fe 3803 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3804
3805 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3806 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3807
e00c8cf2 3808 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3809 set_cr4_guest_host_mask(vmx);
e00c8cf2 3810
99e3e30a 3811 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3812
e00c8cf2
AK		 3813 return 0;
3814}
3815
3816static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3817{
3818 struct vcpu_vmx *vmx = to_vmx(vcpu);
3819 u64 msr;
4b9d3a04 3820 int ret;
e00c8cf2 3821
5fdbf976 3822 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3823
7ffd92c5 3824 vmx->rmode.vm86_active = 0;
e00c8cf2 3825
3b86cd99
JK		 3826 vmx->soft_vnmi_blocked = 0;
3827
ad312c7c 3828 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3829 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3830 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3831 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3832 msr |= MSR_IA32_APICBASE_BSP;
3833 kvm_set_apic_base(&vmx->vcpu, msr);
3834
10ab25cd
JK		 3835 ret = fx_init(&vmx->vcpu);
3836 if (ret != 0)
3837 goto out;
e00c8cf2 3838
2fb92db1
AK		 3839 vmx_segment_cache_clear(vmx);
3840
5706be0d 3841 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3842 /*
3843 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3844 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3845 */
c5af89b6 3846 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3847 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3848 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3849 } else {
ad312c7c
ZX		 3850 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3851 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3852 }
e00c8cf2
AK		 3853
3854 seg_setup(VCPU_SREG_DS);
3855 seg_setup(VCPU_SREG_ES);
3856 seg_setup(VCPU_SREG_FS);
3857 seg_setup(VCPU_SREG_GS);
3858 seg_setup(VCPU_SREG_SS);
3859
3860 vmcs_write16(GUEST_TR_SELECTOR, 0);
3861 vmcs_writel(GUEST_TR_BASE, 0);
3862 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3863 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3864
3865 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3866 vmcs_writel(GUEST_LDTR_BASE, 0);
3867 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3868 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3869
3870 vmcs_write32(GUEST_SYSENTER_CS, 0);
3871 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3872 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3873
3874 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3875 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3876 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3877 else
5fdbf976
MT		 3878 kvm_rip_write(vcpu, 0);
3879 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3880
e00c8cf2
AK		 3881 vmcs_writel(GUEST_DR7, 0x400);
3882
3883 vmcs_writel(GUEST_GDTR_BASE, 0);
3884 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3885
3886 vmcs_writel(GUEST_IDTR_BASE, 0);
3887 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3888
443381a8 3889 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3890 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3891 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3892
e00c8cf2
AK		 3893 /* Special registers */
3894 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3895
3896 setup_msrs(vmx);
3897
6aa8b732
AK		 3898 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3899
f78e0e2e
SY		 3900 if (cpu_has_vmx_tpr_shadow()) {
3901 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3902 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3903 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3904 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3905 vmcs_write32(TPR_THRESHOLD, 0);
3906 }
3907
3908 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3909 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3910 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3911
2384d2b3
SY		 3912 if (vmx->vpid != 0)
3913 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3914
fa40052c 3915 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3916 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3917 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3918 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3919 vmx_fpu_activate(&vmx->vcpu);
3920 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3921
b9d762fa 3922 vpid_sync_context(vmx);
2384d2b3 3923
3200f405 3924 ret = 0;
6aa8b732 3925
a89a8fb9
MG		 3926 /* HACK: Don't enable emulation on guest boot/reset */
3927 vmx->emulation_required = 0;
3928
6aa8b732
AK		 3929out:
3930 return ret;
3931}
3932
b6f1250e
NHE		 3933/*
3934 * In nested virtualization, check if L1 asked to exit on external interrupts.
3935 * For most existing hypervisors, this will always return true.
3936 */
3937static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3938{
3939 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3940 PIN_BASED_EXT_INTR_MASK;
3941}
3942
3b86cd99
JK		 3943static void enable_irq_window(struct kvm_vcpu *vcpu)
3944{
3945 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 3946 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3947 /*
3948 * We get here if vmx_interrupt_allowed() said we can't
3949 * inject to L1 now because L2 must run. Ask L2 to exit
3950 * right after entry, so we can inject to L1 more promptly.
b6f1250e 3951 */
d6185f20 3952 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 3953 return;
d6185f20 3954 }
3b86cd99
JK		 3955
3956 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3957 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3958 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3959}
3960
3961static void enable_nmi_window(struct kvm_vcpu *vcpu)
3962{
3963 u32 cpu_based_vm_exec_control;
3964
3965 if (!cpu_has_virtual_nmis()) {
3966 enable_irq_window(vcpu);
3967 return;
3968 }
3969
30bd0c4c
AK		 3970 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3971 enable_irq_window(vcpu);
3972 return;
3973 }
3b86cd99
JK		 3974 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3975 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3976 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3977}
3978
66fd3f7f 3979static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3980{
9c8cba37 3981 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3982 uint32_t intr;
3983 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3984
229456fc 3985 trace_kvm_inj_virq(irq);
2714d1d3 3986
fa89a817 3987 ++vcpu->stat.irq_injections;
7ffd92c5 3988 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3989 int inc_eip = 0;
3990 if (vcpu->arch.interrupt.soft)
3991 inc_eip = vcpu->arch.event_exit_inst_len;
3992 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3993 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3994 return;
3995 }
66fd3f7f
GN		 3996 intr = irq | INTR_INFO_VALID_MASK;
3997 if (vcpu->arch.interrupt.soft) {
3998 intr |= INTR_TYPE_SOFT_INTR;
3999 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4000 vmx->vcpu.arch.event_exit_inst_len);
4001 } else
4002 intr |= INTR_TYPE_EXT_INTR;
4003 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 4004 vmx_clear_hlt(vcpu);
85f455f7
ED		 4005}
4006
f08864b4
SY		 4007static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4008{
66a5a347
JK		 4009 struct vcpu_vmx *vmx = to_vmx(vcpu);
4010
0b6ac343
NHE		 4011 if (is_guest_mode(vcpu))
4012 return;
4013
3b86cd99
JK		 4014 if (!cpu_has_virtual_nmis()) {
4015 /*
4016 * Tracking the NMI-blocked state in software is built upon
4017 * finding the next open IRQ window. This, in turn, depends on
4018 * well-behaving guests: They have to keep IRQs disabled at
4019 * least as long as the NMI handler runs. Otherwise we may
4020 * cause NMI nesting, maybe breaking the guest. But as this is
4021 * highly unlikely, we can live with the residual risk.
4022 */
4023 vmx->soft_vnmi_blocked = 1;
4024 vmx->vnmi_blocked_time = 0;
4025 }
4026
487b391d 4027 ++vcpu->stat.nmi_injections;
9d58b931 4028 vmx->nmi_known_unmasked = false;
7ffd92c5 4029 if (vmx->rmode.vm86_active) {
71f9833b 4030 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4031 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4032 return;
4033 }
f08864b4
SY		 4034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4035 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 4036 vmx_clear_hlt(vcpu);
f08864b4
SY		 4037}
4038
c4282df9 4039static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4040{
3b86cd99 4041 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4042 return 0;
33f089ca 4043
c4282df9 4044 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4045 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4046 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4047}
4048
3cfc3092
JK		 4049static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4050{
4051 if (!cpu_has_virtual_nmis())
4052 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4053 if (to_vmx(vcpu)->nmi_known_unmasked)
4054 return false;
c332c83a 4055 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4056}
4057
4058static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4059{
4060 struct vcpu_vmx *vmx = to_vmx(vcpu);
4061
4062 if (!cpu_has_virtual_nmis()) {
4063 if (vmx->soft_vnmi_blocked != masked) {
4064 vmx->soft_vnmi_blocked = masked;
4065 vmx->vnmi_blocked_time = 0;
4066 }
4067 } else {
9d58b931 4068 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4069 if (masked)
4070 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4071 GUEST_INTR_STATE_NMI);
4072 else
4073 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4074 GUEST_INTR_STATE_NMI);
4075 }
4076}
4077
78646121
GN		 4078static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4079{
b6f1250e 4080 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4081 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4082 if (to_vmx(vcpu)->nested.nested_run_pending ||
4083 (vmcs12->idt_vectoring_info_field &
4084 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4085 return 0;
4086 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4087 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4088 vmcs12->vm_exit_intr_info = 0;
4089 /* fall through to normal code, but now in L1, not L2 */
4090 }
4091
c4282df9
GN		 4092 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4093 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4094 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4095}
4096
cbc94022
IE		 4097static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4098{
4099 int ret;
4100 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4101 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4102 .guest_phys_addr = addr,
4103 .memory_size = PAGE_SIZE * 3,
4104 .flags = 0,
4105 };
4106
4107 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4108 if (ret)
4109 return ret;
bfc6d222 4110 kvm->arch.tss_addr = addr;
93ea5388
GN		 4111 if (!init_rmode_tss(kvm))
4112 return -ENOMEM;
4113
cbc94022
IE		 4114 return 0;
4115}
4116
6aa8b732
AK		 4117static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4118 int vec, u32 err_code)
4119{
b3f37707
NK		 4120 /*
4121 * Instruction with address size override prefix opcode 0x67
4122 * Cause the #SS fault with 0 error code in VM86 mode.
4123 */
4124 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4125 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4126 return 1;
77ab6db0
JK		 4127 /*
4128 * Forward all other exceptions that are valid in real mode.
4129 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4130 * the required debugging infrastructure rework.
4131 */
4132 switch (vec) {
77ab6db0 4133 case DB_VECTOR:
d0bfb940
JK		 4134 if (vcpu->guest_debug &
4135 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4136 return 0;
4137 kvm_queue_exception(vcpu, vec);
4138 return 1;
77ab6db0 4139 case BP_VECTOR:
c573cd22
JK		 4140 /*
4141 * Update instruction length as we may reinject the exception
4142 * from user space while in guest debugging mode.
4143 */
4144 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4145 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4146 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4147 return 0;
4148 /* fall through */
4149 case DE_VECTOR:
77ab6db0
JK		 4150 case OF_VECTOR:
4151 case BR_VECTOR:
4152 case UD_VECTOR:
4153 case DF_VECTOR:
4154 case SS_VECTOR:
4155 case GP_VECTOR:
4156 case MF_VECTOR:
4157 kvm_queue_exception(vcpu, vec);
4158 return 1;
4159 }
6aa8b732
AK		 4160 return 0;
4161}
4162
a0861c02
AK		 4163/*
4164 * Trigger machine check on the host. We assume all the MSRs are already set up
4165 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4166 * We pass a fake environment to the machine check handler because we want
4167 * the guest to be always treated like user space, no matter what context
4168 * it used internally.
4169 */
4170static void kvm_machine_check(void)
4171{
4172#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4173 struct pt_regs regs = {
4174 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4175 .flags = X86_EFLAGS_IF,
4176 };
4177
4178 do_machine_check(&regs, 0);
4179#endif
4180}
4181
851ba692 4182static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4183{
4184 /* already handled by vcpu_run */
4185 return 1;
4186}
4187
851ba692 4188static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4189{
1155f76a 4190 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4191 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4192 u32 intr_info, ex_no, error_code;
42dbaa5a 4193 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4194 u32 vect_info;
4195 enum emulation_result er;
4196
1155f76a 4197 vect_info = vmx->idt_vectoring_info;
88786475 4198 intr_info = vmx->exit_intr_info;
6aa8b732 4199
a0861c02 4200 if (is_machine_check(intr_info))
851ba692 4201 return handle_machine_check(vcpu);
a0861c02 4202
6aa8b732 4203 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4204 !is_page_fault(intr_info)) {
4205 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4206 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4207 vcpu->run->internal.ndata = 2;
4208 vcpu->run->internal.data[0] = vect_info;
4209 vcpu->run->internal.data[1] = intr_info;
4210 return 0;
4211 }
6aa8b732 4212
e4a41889 4213 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4214 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4215
4216 if (is_no_device(intr_info)) {
5fd86fcf 4217 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4218 return 1;
4219 }
4220
7aa81cc0 4221 if (is_invalid_opcode(intr_info)) {
51d8b661 4222 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4223 if (er != EMULATE_DONE)
7ee5d940 4224 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4225 return 1;
4226 }
4227
6aa8b732 4228 error_code = 0;
2e11384c 4229 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4230 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4231 if (is_page_fault(intr_info)) {
1439442c 4232 /* EPT won't cause page fault directly */
cf3ace79 4233 BUG_ON(enable_ept);
6aa8b732 4234 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4235 trace_kvm_page_fault(cr2, error_code);
4236
3298b75c 4237 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4238 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4239 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4240 }
4241
7ffd92c5 4242 if (vmx->rmode.vm86_active &&
6aa8b732 4243 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4244 error_code)) {
ad312c7c
ZX		 4245 if (vcpu->arch.halt_request) {
4246 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4247 return kvm_emulate_halt(vcpu);
4248 }
6aa8b732 4249 return 1;
72d6e5a0 4250 }
6aa8b732 4251
d0bfb940 4252 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4253 switch (ex_no) {
4254 case DB_VECTOR:
4255 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4256 if (!(vcpu->guest_debug &
4257 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4258 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4259 kvm_queue_exception(vcpu, DB_VECTOR);
4260 return 1;
4261 }
4262 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4263 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4264 /* fall through */
4265 case BP_VECTOR:
c573cd22
JK		 4266 /*
4267 * Update instruction length as we may reinject #BP from
4268 * user space while in guest debugging mode. Reading it for
4269 * #DB as well causes no harm, it is not used in that case.
4270 */
4271 vmx->vcpu.arch.event_exit_inst_len =
4272 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4273 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4274 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4275 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4276 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4277 break;
4278 default:
d0bfb940
JK		 4279 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4280 kvm_run->ex.exception = ex_no;
4281 kvm_run->ex.error_code = error_code;
42dbaa5a 4282 break;
6aa8b732 4283 }
6aa8b732
AK		 4284 return 0;
4285}
4286
851ba692 4287static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4288{
1165f5fe 4289 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4290 return 1;
4291}
4292
851ba692 4293static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4294{
851ba692 4295 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4296 return 0;
4297}
6aa8b732 4298
851ba692 4299static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4300{
bfdaab09 4301 unsigned long exit_qualification;
34c33d16 4302 int size, in, string;
039576c0 4303 unsigned port;
6aa8b732 4304
bfdaab09 4305 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4306 string = (exit_qualification & 16) != 0;
cf8f70bf 4307 in = (exit_qualification & 8) != 0;
e70669ab 4308
cf8f70bf 4309 ++vcpu->stat.io_exits;
e70669ab 4310
cf8f70bf 4311 if (string || in)
51d8b661 4312 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4313
cf8f70bf
GN		 4314 port = exit_qualification >> 16;
4315 size = (exit_qualification & 7) + 1;
e93f36bc 4316 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4317
4318 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4319}
4320
102d8325
IM		 4321static void
4322vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4323{
4324 /*
4325 * Patch in the VMCALL instruction:
4326 */
4327 hypercall[0] = 0x0f;
4328 hypercall[1] = 0x01;
4329 hypercall[2] = 0xc1;
102d8325
IM		 4330}
4331
eeadf9e7
NHE		 4332/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4333static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4334{
4335 if (to_vmx(vcpu)->nested.vmxon &&
4336 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4337 return 1;
4338
4339 if (is_guest_mode(vcpu)) {
4340 /*
4341 * We get here when L2 changed cr0 in a way that did not change
4342 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4343 * but did change L0 shadowed bits. This can currently happen
4344 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4345 * loading) while pretending to allow the guest to change it.
4346 */
4347 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4348 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4349 return 1;
4350 vmcs_writel(CR0_READ_SHADOW, val);
4351 return 0;
4352 } else
4353 return kvm_set_cr0(vcpu, val);
4354}
4355
4356static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4357{
4358 if (is_guest_mode(vcpu)) {
4359 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4360 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4361 return 1;
4362 vmcs_writel(CR4_READ_SHADOW, val);
4363 return 0;
4364 } else
4365 return kvm_set_cr4(vcpu, val);
4366}
4367
4368/* called to set cr0 as approriate for clts instruction exit. */
4369static void handle_clts(struct kvm_vcpu *vcpu)
4370{
4371 if (is_guest_mode(vcpu)) {
4372 /*
4373 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4374 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4375 * just pretend it's off (also in arch.cr0 for fpu_activate).
4376 */
4377 vmcs_writel(CR0_READ_SHADOW,
4378 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4379 vcpu->arch.cr0 &= ~X86_CR0_TS;
4380 } else
4381 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4382}
4383
851ba692 4384static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4385{
229456fc 4386 unsigned long exit_qualification, val;
6aa8b732
AK		 4387 int cr;
4388 int reg;
49a9b07e 4389 int err;
6aa8b732 4390
bfdaab09 4391 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4392 cr = exit_qualification & 15;
4393 reg = (exit_qualification >> 8) & 15;
4394 switch ((exit_qualification >> 4) & 3) {
4395 case 0: /* mov to cr */
229456fc
MT		 4396 val = kvm_register_read(vcpu, reg);
4397 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4398 switch (cr) {
4399 case 0:
eeadf9e7 4400 err = handle_set_cr0(vcpu, val);
db8fcefa 4401 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4402 return 1;
4403 case 3:
2390218b 4404 err = kvm_set_cr3(vcpu, val);
db8fcefa 4405 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4406 return 1;
4407 case 4:
eeadf9e7 4408 err = handle_set_cr4(vcpu, val);
db8fcefa 4409 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4410 return 1;
0a5fff19
GN		 4411 case 8: {
4412 u8 cr8_prev = kvm_get_cr8(vcpu);
4413 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4414 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4415 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4416 if (irqchip_in_kernel(vcpu->kvm))
4417 return 1;
4418 if (cr8_prev <= cr8)
4419 return 1;
851ba692 4420 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4421 return 0;
4422 }
6aa8b732
AK		 4423 };
4424 break;
25c4c276 4425 case 2: /* clts */
eeadf9e7 4426 handle_clts(vcpu);
4d4ec087 4427 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4428 skip_emulated_instruction(vcpu);
6b52d186 4429 vmx_fpu_activate(vcpu);
25c4c276 4430 return 1;
6aa8b732
AK		 4431 case 1: /*mov from cr*/
4432 switch (cr) {
4433 case 3:
9f8fe504
AK		 4434 val = kvm_read_cr3(vcpu);
4435 kvm_register_write(vcpu, reg, val);
4436 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4437 skip_emulated_instruction(vcpu);
4438 return 1;
4439 case 8:
229456fc
MT		 4440 val = kvm_get_cr8(vcpu);
4441 kvm_register_write(vcpu, reg, val);
4442 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4443 skip_emulated_instruction(vcpu);
4444 return 1;
4445 }
4446 break;
4447 case 3: /* lmsw */
a1f83a74 4448 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4449 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4450 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4451
4452 skip_emulated_instruction(vcpu);
4453 return 1;
4454 default:
4455 break;
4456 }
851ba692 4457 vcpu->run->exit_reason = 0;
f0242478 4458 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4459 (int)(exit_qualification >> 4) & 3, cr);
4460 return 0;
4461}
4462
851ba692 4463static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4464{
bfdaab09 4465 unsigned long exit_qualification;
6aa8b732
AK		 4466 int dr, reg;
4467
f2483415 4468 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4469 if (!kvm_require_cpl(vcpu, 0))
4470 return 1;
42dbaa5a
JK		 4471 dr = vmcs_readl(GUEST_DR7);
4472 if (dr & DR7_GD) {
4473 /*
4474 * As the vm-exit takes precedence over the debug trap, we
4475 * need to emulate the latter, either for the host or the
4476 * guest debugging itself.
4477 */
4478 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4479 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4480 vcpu->run->debug.arch.dr7 = dr;
4481 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4482 vmcs_readl(GUEST_CS_BASE) +
4483 vmcs_readl(GUEST_RIP);
851ba692
AK		 4484 vcpu->run->debug.arch.exception = DB_VECTOR;
4485 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4486 return 0;
4487 } else {
4488 vcpu->arch.dr7 &= ~DR7_GD;
4489 vcpu->arch.dr6 |= DR6_BD;
4490 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4491 kvm_queue_exception(vcpu, DB_VECTOR);
4492 return 1;
4493 }
4494 }
4495
bfdaab09 4496 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4497 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4498 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4499 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4500 unsigned long val;
4501 if (!kvm_get_dr(vcpu, dr, &val))
4502 kvm_register_write(vcpu, reg, val);
4503 } else
4504 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4505 skip_emulated_instruction(vcpu);
4506 return 1;
4507}
4508
020df079
GN		 4509static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4510{
4511 vmcs_writel(GUEST_DR7, val);
4512}
4513
851ba692 4514static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4515{
06465c5a
AK		 4516 kvm_emulate_cpuid(vcpu);
4517 return 1;
6aa8b732
AK		 4518}
4519
851ba692 4520static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4521{
ad312c7c 4522 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4523 u64 data;
4524
4525 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4526 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4527 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4528 return 1;
4529 }
4530
229456fc 4531 trace_kvm_msr_read(ecx, data);
2714d1d3 4532
6aa8b732 4533 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4534 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4535 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4536 skip_emulated_instruction(vcpu);
4537 return 1;
4538}
4539
851ba692 4540static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4541{
ad312c7c
ZX		 4542 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4543 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4544 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4545
4546 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4547 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4548 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4549 return 1;
4550 }
4551
59200273 4552 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4553 skip_emulated_instruction(vcpu);
4554 return 1;
4555}
4556
851ba692 4557static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4558{
3842d135 4559 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4560 return 1;
4561}
4562
851ba692 4563static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4564{
85f455f7
ED		 4565 u32 cpu_based_vm_exec_control;
4566
4567 /* clear pending irq */
4568 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4569 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4570 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4571
3842d135
AK		 4572 kvm_make_request(KVM_REQ_EVENT, vcpu);
4573
a26bf12a 4574 ++vcpu->stat.irq_window_exits;
2714d1d3 4575
c1150d8c
DL		 4576 /*
4577 * If the user space waits to inject interrupts, exit as soon as
4578 * possible
4579 */
8061823a 4580 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4581 vcpu->run->request_interrupt_window &&
8061823a 4582 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4583 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4584 return 0;
4585 }
6aa8b732
AK		 4586 return 1;
4587}
4588
851ba692 4589static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4590{
4591 skip_emulated_instruction(vcpu);
d3bef15f 4592 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4593}
4594
851ba692 4595static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4596{
510043da 4597 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4598 kvm_emulate_hypercall(vcpu);
4599 return 1;
c21415e8
IM		 4600}
4601
ec25d5e6
GN		 4602static int handle_invd(struct kvm_vcpu *vcpu)
4603{
51d8b661 4604 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4605}
4606
851ba692 4607static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4608{
f9c617f6 4609 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4610
4611 kvm_mmu_invlpg(vcpu, exit_qualification);
4612 skip_emulated_instruction(vcpu);
4613 return 1;
4614}
4615
851ba692 4616static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4617{
4618 skip_emulated_instruction(vcpu);
f5f48ee1 4619 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4620 return 1;
4621}
4622
2acf923e
DC		 4623static int handle_xsetbv(struct kvm_vcpu *vcpu)
4624{
4625 u64 new_bv = kvm_read_edx_eax(vcpu);
4626 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4627
4628 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4629 skip_emulated_instruction(vcpu);
4630 return 1;
4631}
4632
851ba692 4633static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4634{
58fbbf26
KT		 4635 if (likely(fasteoi)) {
4636 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4637 int access_type, offset;
4638
4639 access_type = exit_qualification & APIC_ACCESS_TYPE;
4640 offset = exit_qualification & APIC_ACCESS_OFFSET;
4641 /*
4642 * Sane guest uses MOV to write EOI, with written value
4643 * not cared. So make a short-circuit here by avoiding
4644 * heavy instruction emulation.
4645 */
4646 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4647 (offset == APIC_EOI)) {
4648 kvm_lapic_set_eoi(vcpu);
4649 skip_emulated_instruction(vcpu);
4650 return 1;
4651 }
4652 }
51d8b661 4653 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4654}
4655
851ba692 4656static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4657{
60637aac 4658 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4659 unsigned long exit_qualification;
e269fb21
JK		 4660 bool has_error_code = false;
4661 u32 error_code = 0;
37817f29 4662 u16 tss_selector;
64a7ec06
GN		 4663 int reason, type, idt_v;
4664
4665 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4666 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4667
4668 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4669
4670 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4671 if (reason == TASK_SWITCH_GATE && idt_v) {
4672 switch (type) {
4673 case INTR_TYPE_NMI_INTR:
4674 vcpu->arch.nmi_injected = false;
654f06fc 4675 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4676 break;
4677 case INTR_TYPE_EXT_INTR:
66fd3f7f 4678 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4679 kvm_clear_interrupt_queue(vcpu);
4680 break;
4681 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4682 if (vmx->idt_vectoring_info &
4683 VECTORING_INFO_DELIVER_CODE_MASK) {
4684 has_error_code = true;
4685 error_code =
4686 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4687 }
4688 /* fall through */
64a7ec06
GN		 4689 case INTR_TYPE_SOFT_EXCEPTION:
4690 kvm_clear_exception_queue(vcpu);
4691 break;
4692 default:
4693 break;
4694 }
60637aac 4695 }
37817f29
IE		 4696 tss_selector = exit_qualification;
4697
64a7ec06
GN		 4698 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4699 type != INTR_TYPE_EXT_INTR &&
4700 type != INTR_TYPE_NMI_INTR))
4701 skip_emulated_instruction(vcpu);
4702
acb54517
GN		 4703 if (kvm_task_switch(vcpu, tss_selector, reason,
4704 has_error_code, error_code) == EMULATE_FAIL) {
4705 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4706 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4707 vcpu->run->internal.ndata = 0;
42dbaa5a 4708 return 0;
acb54517 4709 }
42dbaa5a
JK		 4710
4711 /* clear all local breakpoint enable flags */
4712 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4713
4714 /*
4715 * TODO: What about debug traps on tss switch?
4716 * Are we supposed to inject them and update dr6?
4717 */
4718
4719 return 1;
37817f29
IE		 4720}
4721
851ba692 4722static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4723{
f9c617f6 4724 unsigned long exit_qualification;
1439442c 4725 gpa_t gpa;
1439442c 4726 int gla_validity;
1439442c 4727
f9c617f6 4728 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4729
4730 if (exit_qualification & (1 << 6)) {
4731 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4732 return -EINVAL;
1439442c
SY		 4733 }
4734
4735 gla_validity = (exit_qualification >> 7) & 0x3;
4736 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4737 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4738 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4739 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4740 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4741 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4742 (long unsigned int)exit_qualification);
851ba692
AK		 4743 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4744 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4745 return 0;
1439442c
SY		 4746 }
4747
4748 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4749 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4750 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4751}
4752
68f89400
MT		 4753static u64 ept_rsvd_mask(u64 spte, int level)
4754{
4755 int i;
4756 u64 mask = 0;
4757
4758 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4759 mask |= (1ULL << i);
4760
4761 if (level > 2)
4762 /* bits 7:3 reserved */
4763 mask |= 0xf8;
4764 else if (level == 2) {
4765 if (spte & (1ULL << 7))
4766 /* 2MB ref, bits 20:12 reserved */
4767 mask |= 0x1ff000;
4768 else
4769 /* bits 6:3 reserved */
4770 mask |= 0x78;
4771 }
4772
4773 return mask;
4774}
4775
4776static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4777 int level)
4778{
4779 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4780
4781 /* 010b (write-only) */
4782 WARN_ON((spte & 0x7) == 0x2);
4783
4784 /* 110b (write/execute) */
4785 WARN_ON((spte & 0x7) == 0x6);
4786
4787 /* 100b (execute-only) and value not supported by logical processor */
4788 if (!cpu_has_vmx_ept_execute_only())
4789 WARN_ON((spte & 0x7) == 0x4);
4790
4791 /* not 000b */
4792 if ((spte & 0x7)) {
4793 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4794
4795 if (rsvd_bits != 0) {
4796 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4797 __func__, rsvd_bits);
4798 WARN_ON(1);
4799 }
4800
4801 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4802 u64 ept_mem_type = (spte & 0x38) >> 3;
4803
4804 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4805 ept_mem_type == 7) {
4806 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4807 __func__, ept_mem_type);
4808 WARN_ON(1);
4809 }
4810 }
4811 }
4812}
4813
851ba692 4814static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4815{
4816 u64 sptes[4];
ce88decf 4817 int nr_sptes, i, ret;
68f89400
MT		 4818 gpa_t gpa;
4819
4820 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4821
ce88decf
XG		 4822 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4823 if (likely(ret == 1))
4824 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4825 EMULATE_DONE;
4826 if (unlikely(!ret))
4827 return 1;
4828
4829 /* It is the real ept misconfig */
68f89400
MT		 4830 printk(KERN_ERR "EPT: Misconfiguration.\n");
4831 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4832
4833 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4834
4835 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4836 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4837
851ba692
AK		 4838 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4839 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4840
4841 return 0;
4842}
4843
851ba692 4844static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4845{
4846 u32 cpu_based_vm_exec_control;
4847
4848 /* clear pending NMI */
4849 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4850 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4851 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4852 ++vcpu->stat.nmi_window_exits;
3842d135 4853 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4854
4855 return 1;
4856}
4857
80ced186 4858static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4859{
8b3079a5
AK		 4860 struct vcpu_vmx *vmx = to_vmx(vcpu);
4861 enum emulation_result err = EMULATE_DONE;
80ced186 4862 int ret = 1;
49e9d557
AK		 4863 u32 cpu_exec_ctrl;
4864 bool intr_window_requested;
4865
4866 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4867 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4868
4869 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4870 if (intr_window_requested
4871 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4872 return handle_interrupt_window(&vmx->vcpu);
4873
51d8b661 4874 err = emulate_instruction(vcpu, 0);
ea953ef0 4875
80ced186
MG		 4876 if (err == EMULATE_DO_MMIO) {
4877 ret = 0;
4878 goto out;
4879 }
1d5a4d9b 4880
6d77dbfc
GN		 4881 if (err != EMULATE_DONE)
4882 return 0;
ea953ef0
MG		 4883
4884 if (signal_pending(current))
80ced186 4885 goto out;
ea953ef0
MG		 4886 if (need_resched())
4887 schedule();
4888 }
4889
80ced186
MG		 4890 vmx->emulation_required = 0;
4891out:
4892 return ret;
ea953ef0
MG		 4893}
4894
4b8d54f9
ZE		 4895/*
4896 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4897 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4898 */
9fb41ba8 4899static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4900{
4901 skip_emulated_instruction(vcpu);
4902 kvm_vcpu_on_spin(vcpu);
4903
4904 return 1;
4905}
4906
59708670
SY		 4907static int handle_invalid_op(struct kvm_vcpu *vcpu)
4908{
4909 kvm_queue_exception(vcpu, UD_VECTOR);
4910 return 1;
4911}
4912
ff2f6fe9
NHE		 4913/*
4914 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4915 * We could reuse a single VMCS for all the L2 guests, but we also want the
4916 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4917 * allows keeping them loaded on the processor, and in the future will allow
4918 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4919 * every entry if they never change.
4920 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4921 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4922 *
4923 * The following functions allocate and free a vmcs02 in this pool.
4924 */
4925
4926/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4927static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4928{
4929 struct vmcs02_list *item;
4930 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4931 if (item->vmptr == vmx->nested.current_vmptr) {
4932 list_move(&item->list, &vmx->nested.vmcs02_pool);
4933 return &item->vmcs02;
4934 }
4935
4936 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4937 /* Recycle the least recently used VMCS. */
4938 item = list_entry(vmx->nested.vmcs02_pool.prev,
4939 struct vmcs02_list, list);
4940 item->vmptr = vmx->nested.current_vmptr;
4941 list_move(&item->list, &vmx->nested.vmcs02_pool);
4942 return &item->vmcs02;
4943 }
4944
4945 /* Create a new VMCS */
4946 item = (struct vmcs02_list *)
4947 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4948 if (!item)
4949 return NULL;
4950 item->vmcs02.vmcs = alloc_vmcs();
4951 if (!item->vmcs02.vmcs) {
4952 kfree(item);
4953 return NULL;
4954 }
4955 loaded_vmcs_init(&item->vmcs02);
4956 item->vmptr = vmx->nested.current_vmptr;
4957 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4958 vmx->nested.vmcs02_num++;
4959 return &item->vmcs02;
4960}
4961
4962/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4963static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4964{
4965 struct vmcs02_list *item;
4966 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4967 if (item->vmptr == vmptr) {
4968 free_loaded_vmcs(&item->vmcs02);
4969 list_del(&item->list);
4970 kfree(item);
4971 vmx->nested.vmcs02_num--;
4972 return;
4973 }
4974}
4975
4976/*
4977 * Free all VMCSs saved for this vcpu, except the one pointed by
4978 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4979 * currently used, if running L2), and vmcs01 when running L2.
4980 */
4981static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4982{
4983 struct vmcs02_list *item, *n;
4984 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4985 if (vmx->loaded_vmcs != &item->vmcs02)
4986 free_loaded_vmcs(&item->vmcs02);
4987 list_del(&item->list);
4988 kfree(item);
4989 }
4990 vmx->nested.vmcs02_num = 0;
4991
4992 if (vmx->loaded_vmcs != &vmx->vmcs01)
4993 free_loaded_vmcs(&vmx->vmcs01);
4994}
4995
ec378aee
NHE		 4996/*
4997 * Emulate the VMXON instruction.
4998 * Currently, we just remember that VMX is active, and do not save or even
4999 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5000 * do not currently need to store anything in that guest-allocated memory
5001 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5002 * argument is different from the VMXON pointer (which the spec says they do).
5003 */
5004static int handle_vmon(struct kvm_vcpu *vcpu)
5005{
5006 struct kvm_segment cs;
5007 struct vcpu_vmx *vmx = to_vmx(vcpu);
5008
5009 /* The Intel VMX Instruction Reference lists a bunch of bits that
5010 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5011 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5012 * Otherwise, we should fail with #UD. We test these now:
5013 */
5014 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5015 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5016 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5017 kvm_queue_exception(vcpu, UD_VECTOR);
5018 return 1;
5019 }
5020
5021 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5022 if (is_long_mode(vcpu) && !cs.l) {
5023 kvm_queue_exception(vcpu, UD_VECTOR);
5024 return 1;
5025 }
5026
5027 if (vmx_get_cpl(vcpu)) {
5028 kvm_inject_gp(vcpu, 0);
5029 return 1;
5030 }
5031
ff2f6fe9
NHE		 5032 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5033 vmx->nested.vmcs02_num = 0;
5034
ec378aee
NHE		 5035 vmx->nested.vmxon = true;
5036
5037 skip_emulated_instruction(vcpu);
5038 return 1;
5039}
5040
5041/*
5042 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5043 * for running VMX instructions (except VMXON, whose prerequisites are
5044 * slightly different). It also specifies what exception to inject otherwise.
5045 */
5046static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5047{
5048 struct kvm_segment cs;
5049 struct vcpu_vmx *vmx = to_vmx(vcpu);
5050
5051 if (!vmx->nested.vmxon) {
5052 kvm_queue_exception(vcpu, UD_VECTOR);
5053 return 0;
5054 }
5055
5056 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5057 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5058 (is_long_mode(vcpu) && !cs.l)) {
5059 kvm_queue_exception(vcpu, UD_VECTOR);
5060 return 0;
5061 }
5062
5063 if (vmx_get_cpl(vcpu)) {
5064 kvm_inject_gp(vcpu, 0);
5065 return 0;
5066 }
5067
5068 return 1;
5069}
5070
5071/*
5072 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5073 * just stops using VMX.
5074 */
5075static void free_nested(struct vcpu_vmx *vmx)
5076{
5077 if (!vmx->nested.vmxon)
5078 return;
5079 vmx->nested.vmxon = false;
a9d30f33
NHE		 5080 if (vmx->nested.current_vmptr != -1ull) {
5081 kunmap(vmx->nested.current_vmcs12_page);
5082 nested_release_page(vmx->nested.current_vmcs12_page);
5083 vmx->nested.current_vmptr = -1ull;
5084 vmx->nested.current_vmcs12 = NULL;
5085 }
fe3ef05c
NHE		 5086 /* Unpin physical memory we referred to in current vmcs02 */
5087 if (vmx->nested.apic_access_page) {
5088 nested_release_page(vmx->nested.apic_access_page);
5089 vmx->nested.apic_access_page = 0;
5090 }
ff2f6fe9
NHE		 5091
5092 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5093}
5094
5095/* Emulate the VMXOFF instruction */
5096static int handle_vmoff(struct kvm_vcpu *vcpu)
5097{
5098 if (!nested_vmx_check_permission(vcpu))
5099 return 1;
5100 free_nested(to_vmx(vcpu));
5101 skip_emulated_instruction(vcpu);
5102 return 1;
5103}
5104
064aea77
NHE		 5105/*
5106 * Decode the memory-address operand of a vmx instruction, as recorded on an
5107 * exit caused by such an instruction (run by a guest hypervisor).
5108 * On success, returns 0. When the operand is invalid, returns 1 and throws
5109 * #UD or #GP.
5110 */
5111static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5112 unsigned long exit_qualification,
5113 u32 vmx_instruction_info, gva_t *ret)
5114{
5115 /*
5116 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5117 * Execution", on an exit, vmx_instruction_info holds most of the
5118 * addressing components of the operand. Only the displacement part
5119 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5120 * For how an actual address is calculated from all these components,
5121 * refer to Vol. 1, "Operand Addressing".
5122 */
5123 int scaling = vmx_instruction_info & 3;
5124 int addr_size = (vmx_instruction_info >> 7) & 7;
5125 bool is_reg = vmx_instruction_info & (1u << 10);
5126 int seg_reg = (vmx_instruction_info >> 15) & 7;
5127 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5128 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5129 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5130 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5131
5132 if (is_reg) {
5133 kvm_queue_exception(vcpu, UD_VECTOR);
5134 return 1;
5135 }
5136
5137 /* Addr = segment_base + offset */
5138 /* offset = base + [index * scale] + displacement */
5139 *ret = vmx_get_segment_base(vcpu, seg_reg);
5140 if (base_is_valid)
5141 *ret += kvm_register_read(vcpu, base_reg);
5142 if (index_is_valid)
5143 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5144 *ret += exit_qualification; /* holds the displacement */
5145
5146 if (addr_size == 1) /* 32 bit */
5147 *ret &= 0xffffffff;
5148
5149 /*
5150 * TODO: throw #GP (and return 1) in various cases that the VM*
5151 * instructions require it - e.g., offset beyond segment limit,
5152 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5153 * address, and so on. Currently these are not checked.
5154 */
5155 return 0;
5156}
5157
0140caea
NHE		 5158/*
5159 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5160 * set the success or error code of an emulated VMX instruction, as specified
5161 * by Vol 2B, VMX Instruction Reference, "Conventions".
5162 */
5163static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5164{
5165 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5166 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5167 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5168}
5169
5170static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5171{
5172 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5173 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5174 X86_EFLAGS_SF | X86_EFLAGS_OF))
5175 | X86_EFLAGS_CF);
5176}
5177
5178static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5179 u32 vm_instruction_error)
5180{
5181 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5182 /*
5183 * failValid writes the error number to the current VMCS, which
5184 * can't be done there isn't a current VMCS.
5185 */
5186 nested_vmx_failInvalid(vcpu);
5187 return;
5188 }
5189 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5190 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5191 X86_EFLAGS_SF | X86_EFLAGS_OF))
5192 | X86_EFLAGS_ZF);
5193 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5194}
5195
27d6c865
NHE		 5196/* Emulate the VMCLEAR instruction */
5197static int handle_vmclear(struct kvm_vcpu *vcpu)
5198{
5199 struct vcpu_vmx *vmx = to_vmx(vcpu);
5200 gva_t gva;
5201 gpa_t vmptr;
5202 struct vmcs12 *vmcs12;
5203 struct page *page;
5204 struct x86_exception e;
5205
5206 if (!nested_vmx_check_permission(vcpu))
5207 return 1;
5208
5209 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5210 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5211 return 1;
5212
5213 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5214 sizeof(vmptr), &e)) {
5215 kvm_inject_page_fault(vcpu, &e);
5216 return 1;
5217 }
5218
5219 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5220 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5221 skip_emulated_instruction(vcpu);
5222 return 1;
5223 }
5224
5225 if (vmptr == vmx->nested.current_vmptr) {
5226 kunmap(vmx->nested.current_vmcs12_page);
5227 nested_release_page(vmx->nested.current_vmcs12_page);
5228 vmx->nested.current_vmptr = -1ull;
5229 vmx->nested.current_vmcs12 = NULL;
5230 }
5231
5232 page = nested_get_page(vcpu, vmptr);
5233 if (page == NULL) {
5234 /*
5235 * For accurate processor emulation, VMCLEAR beyond available
5236 * physical memory should do nothing at all. However, it is
5237 * possible that a nested vmx bug, not a guest hypervisor bug,
5238 * resulted in this case, so let's shut down before doing any
5239 * more damage:
5240 */
5241 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5242 return 1;
5243 }
5244 vmcs12 = kmap(page);
5245 vmcs12->launch_state = 0;
5246 kunmap(page);
5247 nested_release_page(page);
5248
5249 nested_free_vmcs02(vmx, vmptr);
5250
5251 skip_emulated_instruction(vcpu);
5252 nested_vmx_succeed(vcpu);
5253 return 1;
5254}
5255
cd232ad0
NHE		 5256static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5257
5258/* Emulate the VMLAUNCH instruction */
5259static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5260{
5261 return nested_vmx_run(vcpu, true);
5262}
5263
5264/* Emulate the VMRESUME instruction */
5265static int handle_vmresume(struct kvm_vcpu *vcpu)
5266{
5267
5268 return nested_vmx_run(vcpu, false);
5269}
5270
49f705c5
NHE		 5271enum vmcs_field_type {
5272 VMCS_FIELD_TYPE_U16 = 0,
5273 VMCS_FIELD_TYPE_U64 = 1,
5274 VMCS_FIELD_TYPE_U32 = 2,
5275 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5276};
5277
5278static inline int vmcs_field_type(unsigned long field)
5279{
5280 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5281 return VMCS_FIELD_TYPE_U32;
5282 return (field >> 13) & 0x3 ;
5283}
5284
5285static inline int vmcs_field_readonly(unsigned long field)
5286{
5287 return (((field >> 10) & 0x3) == 1);
5288}
5289
5290/*
5291 * Read a vmcs12 field. Since these can have varying lengths and we return
5292 * one type, we chose the biggest type (u64) and zero-extend the return value
5293 * to that size. Note that the caller, handle_vmread, might need to use only
5294 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5295 * 64-bit fields are to be returned).
5296 */
5297static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5298 unsigned long field, u64 *ret)
5299{
5300 short offset = vmcs_field_to_offset(field);
5301 char *p;
5302
5303 if (offset < 0)
5304 return 0;
5305
5306 p = ((char *)(get_vmcs12(vcpu))) + offset;
5307
5308 switch (vmcs_field_type(field)) {
5309 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5310 *ret = *((natural_width *)p);
5311 return 1;
5312 case VMCS_FIELD_TYPE_U16:
5313 *ret = *((u16 *)p);
5314 return 1;
5315 case VMCS_FIELD_TYPE_U32:
5316 *ret = *((u32 *)p);
5317 return 1;
5318 case VMCS_FIELD_TYPE_U64:
5319 *ret = *((u64 *)p);
5320 return 1;
5321 default:
5322 return 0; /* can never happen. */
5323 }
5324}
5325
5326/*
5327 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5328 * used before) all generate the same failure when it is missing.
5329 */
5330static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5331{
5332 struct vcpu_vmx *vmx = to_vmx(vcpu);
5333 if (vmx->nested.current_vmptr == -1ull) {
5334 nested_vmx_failInvalid(vcpu);
5335 skip_emulated_instruction(vcpu);
5336 return 0;
5337 }
5338 return 1;
5339}
5340
5341static int handle_vmread(struct kvm_vcpu *vcpu)
5342{
5343 unsigned long field;
5344 u64 field_value;
5345 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5346 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5347 gva_t gva = 0;
5348
5349 if (!nested_vmx_check_permission(vcpu) ||
5350 !nested_vmx_check_vmcs12(vcpu))
5351 return 1;
5352
5353 /* Decode instruction info and find the field to read */
5354 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5355 /* Read the field, zero-extended to a u64 field_value */
5356 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5357 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5358 skip_emulated_instruction(vcpu);
5359 return 1;
5360 }
5361 /*
5362 * Now copy part of this value to register or memory, as requested.
5363 * Note that the number of bits actually copied is 32 or 64 depending
5364 * on the guest's mode (32 or 64 bit), not on the given field's length.
5365 */
5366 if (vmx_instruction_info & (1u << 10)) {
5367 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5368 field_value);
5369 } else {
5370 if (get_vmx_mem_address(vcpu, exit_qualification,
5371 vmx_instruction_info, &gva))
5372 return 1;
5373 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5374 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5375 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5376 }
5377
5378 nested_vmx_succeed(vcpu);
5379 skip_emulated_instruction(vcpu);
5380 return 1;
5381}
5382
5383
5384static int handle_vmwrite(struct kvm_vcpu *vcpu)
5385{
5386 unsigned long field;
5387 gva_t gva;
5388 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5389 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5390 char *p;
5391 short offset;
5392 /* The value to write might be 32 or 64 bits, depending on L1's long
5393 * mode, and eventually we need to write that into a field of several
5394 * possible lengths. The code below first zero-extends the value to 64
5395 * bit (field_value), and then copies only the approriate number of
5396 * bits into the vmcs12 field.
5397 */
5398 u64 field_value = 0;
5399 struct x86_exception e;
5400
5401 if (!nested_vmx_check_permission(vcpu) ||
5402 !nested_vmx_check_vmcs12(vcpu))
5403 return 1;
5404
5405 if (vmx_instruction_info & (1u << 10))
5406 field_value = kvm_register_read(vcpu,
5407 (((vmx_instruction_info) >> 3) & 0xf));
5408 else {
5409 if (get_vmx_mem_address(vcpu, exit_qualification,
5410 vmx_instruction_info, &gva))
5411 return 1;
5412 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5413 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5414 kvm_inject_page_fault(vcpu, &e);
5415 return 1;
5416 }
5417 }
5418
5419
5420 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5421 if (vmcs_field_readonly(field)) {
5422 nested_vmx_failValid(vcpu,
5423 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5424 skip_emulated_instruction(vcpu);
5425 return 1;
5426 }
5427
5428 offset = vmcs_field_to_offset(field);
5429 if (offset < 0) {
5430 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5431 skip_emulated_instruction(vcpu);
5432 return 1;
5433 }
5434 p = ((char *) get_vmcs12(vcpu)) + offset;
5435
5436 switch (vmcs_field_type(field)) {
5437 case VMCS_FIELD_TYPE_U16:
5438 *(u16 *)p = field_value;
5439 break;
5440 case VMCS_FIELD_TYPE_U32:
5441 *(u32 *)p = field_value;
5442 break;
5443 case VMCS_FIELD_TYPE_U64:
5444 *(u64 *)p = field_value;
5445 break;
5446 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5447 *(natural_width *)p = field_value;
5448 break;
5449 default:
5450 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5451 skip_emulated_instruction(vcpu);
5452 return 1;
5453 }
5454
5455 nested_vmx_succeed(vcpu);
5456 skip_emulated_instruction(vcpu);
5457 return 1;
5458}
5459
63846663
NHE		 5460/* Emulate the VMPTRLD instruction */
5461static int handle_vmptrld(struct kvm_vcpu *vcpu)
5462{
5463 struct vcpu_vmx *vmx = to_vmx(vcpu);
5464 gva_t gva;
5465 gpa_t vmptr;
5466 struct x86_exception e;
5467
5468 if (!nested_vmx_check_permission(vcpu))
5469 return 1;
5470
5471 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5472 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5473 return 1;
5474
5475 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5476 sizeof(vmptr), &e)) {
5477 kvm_inject_page_fault(vcpu, &e);
5478 return 1;
5479 }
5480
5481 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5482 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5483 skip_emulated_instruction(vcpu);
5484 return 1;
5485 }
5486
5487 if (vmx->nested.current_vmptr != vmptr) {
5488 struct vmcs12 *new_vmcs12;
5489 struct page *page;
5490 page = nested_get_page(vcpu, vmptr);
5491 if (page == NULL) {
5492 nested_vmx_failInvalid(vcpu);
5493 skip_emulated_instruction(vcpu);
5494 return 1;
5495 }
5496 new_vmcs12 = kmap(page);
5497 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5498 kunmap(page);
5499 nested_release_page_clean(page);
5500 nested_vmx_failValid(vcpu,
5501 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5502 skip_emulated_instruction(vcpu);
5503 return 1;
5504 }
5505 if (vmx->nested.current_vmptr != -1ull) {
5506 kunmap(vmx->nested.current_vmcs12_page);
5507 nested_release_page(vmx->nested.current_vmcs12_page);
5508 }
5509
5510 vmx->nested.current_vmptr = vmptr;
5511 vmx->nested.current_vmcs12 = new_vmcs12;
5512 vmx->nested.current_vmcs12_page = page;
5513 }
5514
5515 nested_vmx_succeed(vcpu);
5516 skip_emulated_instruction(vcpu);
5517 return 1;
5518}
5519
6a4d7550
NHE		 5520/* Emulate the VMPTRST instruction */
5521static int handle_vmptrst(struct kvm_vcpu *vcpu)
5522{
5523 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525 gva_t vmcs_gva;
5526 struct x86_exception e;
5527
5528 if (!nested_vmx_check_permission(vcpu))
5529 return 1;
5530
5531 if (get_vmx_mem_address(vcpu, exit_qualification,
5532 vmx_instruction_info, &vmcs_gva))
5533 return 1;
5534 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5535 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5536 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5537 sizeof(u64), &e)) {
5538 kvm_inject_page_fault(vcpu, &e);
5539 return 1;
5540 }
5541 nested_vmx_succeed(vcpu);
5542 skip_emulated_instruction(vcpu);
5543 return 1;
5544}
5545
6aa8b732
AK		 5546/*
5547 * The exit handlers return 1 if the exit was handled fully and guest execution
5548 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5549 * to be done to userspace and return 0.
5550 */
851ba692 5551static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5552 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5553 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5554 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5555 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5556 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5557 [EXIT_REASON_CR_ACCESS] = handle_cr,
5558 [EXIT_REASON_DR_ACCESS] = handle_dr,
5559 [EXIT_REASON_CPUID] = handle_cpuid,
5560 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5561 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5562 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5563 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5564 [EXIT_REASON_INVD] = handle_invd,
a7052897 5565 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5566 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5567 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5568 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5569 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5570 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5571 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5572 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5573 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5574 [EXIT_REASON_VMOFF] = handle_vmoff,
5575 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5576 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5577 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5578 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5579 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5580 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5581 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5582 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5583 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5584 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5585 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5586 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5587};
5588
5589static const int kvm_vmx_max_exit_handlers =
50a3485c 5590 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5591
644d711a
NHE		 5592/*
5593 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5594 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5595 * disinterest in the current event (read or write a specific MSR) by using an
5596 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5597 */
5598static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5599 struct vmcs12 *vmcs12, u32 exit_reason)
5600{
5601 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5602 gpa_t bitmap;
5603
5604 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5605 return 1;
5606
5607 /*
5608 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5609 * for the four combinations of read/write and low/high MSR numbers.
5610 * First we need to figure out which of the four to use:
5611 */
5612 bitmap = vmcs12->msr_bitmap;
5613 if (exit_reason == EXIT_REASON_MSR_WRITE)
5614 bitmap += 2048;
5615 if (msr_index >= 0xc0000000) {
5616 msr_index -= 0xc0000000;
5617 bitmap += 1024;
5618 }
5619
5620 /* Then read the msr_index'th bit from this bitmap: */
5621 if (msr_index < 1024*8) {
5622 unsigned char b;
5623 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5624 return 1 & (b >> (msr_index & 7));
5625 } else
5626 return 1; /* let L1 handle the wrong parameter */
5627}
5628
5629/*
5630 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5631 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5632 * intercept (via guest_host_mask etc.) the current event.
5633 */
5634static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5635 struct vmcs12 *vmcs12)
5636{
5637 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638 int cr = exit_qualification & 15;
5639 int reg = (exit_qualification >> 8) & 15;
5640 unsigned long val = kvm_register_read(vcpu, reg);
5641
5642 switch ((exit_qualification >> 4) & 3) {
5643 case 0: /* mov to cr */
5644 switch (cr) {
5645 case 0:
5646 if (vmcs12->cr0_guest_host_mask &
5647 (val ^ vmcs12->cr0_read_shadow))
5648 return 1;
5649 break;
5650 case 3:
5651 if ((vmcs12->cr3_target_count >= 1 &&
5652 vmcs12->cr3_target_value0 == val) ||
5653 (vmcs12->cr3_target_count >= 2 &&
5654 vmcs12->cr3_target_value1 == val) ||
5655 (vmcs12->cr3_target_count >= 3 &&
5656 vmcs12->cr3_target_value2 == val) ||
5657 (vmcs12->cr3_target_count >= 4 &&
5658 vmcs12->cr3_target_value3 == val))
5659 return 0;
5660 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5661 return 1;
5662 break;
5663 case 4:
5664 if (vmcs12->cr4_guest_host_mask &
5665 (vmcs12->cr4_read_shadow ^ val))
5666 return 1;
5667 break;
5668 case 8:
5669 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5670 return 1;
5671 break;
5672 }
5673 break;
5674 case 2: /* clts */
5675 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5676 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5677 return 1;
5678 break;
5679 case 1: /* mov from cr */
5680 switch (cr) {
5681 case 3:
5682 if (vmcs12->cpu_based_vm_exec_control &
5683 CPU_BASED_CR3_STORE_EXITING)
5684 return 1;
5685 break;
5686 case 8:
5687 if (vmcs12->cpu_based_vm_exec_control &
5688 CPU_BASED_CR8_STORE_EXITING)
5689 return 1;
5690 break;
5691 }
5692 break;
5693 case 3: /* lmsw */
5694 /*
5695 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5696 * cr0. Other attempted changes are ignored, with no exit.
5697 */
5698 if (vmcs12->cr0_guest_host_mask & 0xe &
5699 (val ^ vmcs12->cr0_read_shadow))
5700 return 1;
5701 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5702 !(vmcs12->cr0_read_shadow & 0x1) &&
5703 (val & 0x1))
5704 return 1;
5705 break;
5706 }
5707 return 0;
5708}
5709
5710/*
5711 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5712 * should handle it ourselves in L0 (and then continue L2). Only call this
5713 * when in is_guest_mode (L2).
5714 */
5715static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5716{
5717 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5718 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5719 struct vcpu_vmx *vmx = to_vmx(vcpu);
5720 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5721
5722 if (vmx->nested.nested_run_pending)
5723 return 0;
5724
5725 if (unlikely(vmx->fail)) {
bd80158a
JK		 5726 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5727 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5728 return 1;
5729 }
5730
5731 switch (exit_reason) {
5732 case EXIT_REASON_EXCEPTION_NMI:
5733 if (!is_exception(intr_info))
5734 return 0;
5735 else if (is_page_fault(intr_info))
5736 return enable_ept;
5737 return vmcs12->exception_bitmap &
5738 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5739 case EXIT_REASON_EXTERNAL_INTERRUPT:
5740 return 0;
5741 case EXIT_REASON_TRIPLE_FAULT:
5742 return 1;
5743 case EXIT_REASON_PENDING_INTERRUPT:
5744 case EXIT_REASON_NMI_WINDOW:
5745 /*
5746 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5747 * (aka Interrupt Window Exiting) only when L1 turned it on,
5748 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5749 * Same for NMI Window Exiting.
5750 */
5751 return 1;
5752 case EXIT_REASON_TASK_SWITCH:
5753 return 1;
5754 case EXIT_REASON_CPUID:
5755 return 1;
5756 case EXIT_REASON_HLT:
5757 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5758 case EXIT_REASON_INVD:
5759 return 1;
5760 case EXIT_REASON_INVLPG:
5761 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5762 case EXIT_REASON_RDPMC:
5763 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5764 case EXIT_REASON_RDTSC:
5765 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5766 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5767 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5768 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5769 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5770 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5771 /*
5772 * VMX instructions trap unconditionally. This allows L1 to
5773 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5774 */
5775 return 1;
5776 case EXIT_REASON_CR_ACCESS:
5777 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5778 case EXIT_REASON_DR_ACCESS:
5779 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5780 case EXIT_REASON_IO_INSTRUCTION:
5781 /* TODO: support IO bitmaps */
5782 return 1;
5783 case EXIT_REASON_MSR_READ:
5784 case EXIT_REASON_MSR_WRITE:
5785 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5786 case EXIT_REASON_INVALID_STATE:
5787 return 1;
5788 case EXIT_REASON_MWAIT_INSTRUCTION:
5789 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5790 case EXIT_REASON_MONITOR_INSTRUCTION:
5791 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5792 case EXIT_REASON_PAUSE_INSTRUCTION:
5793 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5794 nested_cpu_has2(vmcs12,
5795 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5796 case EXIT_REASON_MCE_DURING_VMENTRY:
5797 return 0;
5798 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5799 return 1;
5800 case EXIT_REASON_APIC_ACCESS:
5801 return nested_cpu_has2(vmcs12,
5802 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5803 case EXIT_REASON_EPT_VIOLATION:
5804 case EXIT_REASON_EPT_MISCONFIG:
5805 return 0;
5806 case EXIT_REASON_WBINVD:
5807 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5808 case EXIT_REASON_XSETBV:
5809 return 1;
5810 default:
5811 return 1;
5812 }
5813}
5814
586f9607
AK		 5815static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5816{
5817 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5818 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5819}
5820
6aa8b732
AK		 5821/*
5822 * The guest has exited. See if we can fix it or if we need userspace
5823 * assistance.
5824 */
851ba692 5825static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5826{
29bd8a78 5827 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5828 u32 exit_reason = vmx->exit_reason;
1155f76a 5829 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5830
80ced186
MG		 5831 /* If guest state is invalid, start emulating */
5832 if (vmx->emulation_required && emulate_invalid_guest_state)
5833 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5834
b6f1250e
NHE		 5835 /*
5836 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5837 * we did not inject a still-pending event to L1 now because of
5838 * nested_run_pending, we need to re-enable this bit.
5839 */
5840 if (vmx->nested.nested_run_pending)
5841 kvm_make_request(KVM_REQ_EVENT, vcpu);
5842
509c75ea
NHE		 5843 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5844 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5845 vmx->nested.nested_run_pending = 1;
5846 else
5847 vmx->nested.nested_run_pending = 0;
5848
5849 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5850 nested_vmx_vmexit(vcpu);
5851 return 1;
5852 }
5853
5120702e
MG		 5854 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5855 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5856 vcpu->run->fail_entry.hardware_entry_failure_reason
5857 = exit_reason;
5858 return 0;
5859 }
5860
29bd8a78 5861 if (unlikely(vmx->fail)) {
851ba692
AK		 5862 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5863 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5864 = vmcs_read32(VM_INSTRUCTION_ERROR);
5865 return 0;
5866 }
6aa8b732 5867
d77c26fc 5868 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5869 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5870 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5871 exit_reason != EXIT_REASON_TASK_SWITCH))
5872 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5873 "(0x%x) and exit reason is 0x%x\n",
5874 __func__, vectoring_info, exit_reason);
3b86cd99 5875
644d711a
NHE		 5876 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5877 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5878 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5879 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5880 vmx->soft_vnmi_blocked = 0;
3b86cd99 5881 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5882 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5883 /*
5884 * This CPU don't support us in finding the end of an
5885 * NMI-blocked window if the guest runs with IRQs
5886 * disabled. So we pull the trigger after 1 s of
5887 * futile waiting, but inform the user about this.
5888 */
5889 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5890 "state on VCPU %d after 1 s timeout\n",
5891 __func__, vcpu->vcpu_id);
5892 vmx->soft_vnmi_blocked = 0;
3b86cd99 5893 }
3b86cd99
JK		 5894 }
5895
6aa8b732
AK		 5896 if (exit_reason < kvm_vmx_max_exit_handlers
5897 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5898 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5899 else {
851ba692
AK		 5900 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5901 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5902 }
5903 return 0;
5904}
5905
95ba8273 5906static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5907{
95ba8273 5908 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5909 vmcs_write32(TPR_THRESHOLD, 0);
5910 return;
5911 }
5912
95ba8273 5913 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5914}
5915
51aa01d1 5916static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5917{
00eba012
AK		 5918 u32 exit_intr_info;
5919
5920 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5921 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5922 return;
5923
c5ca8e57 5924 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5925 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5926
5927 /* Handle machine checks before interrupts are enabled */
00eba012 5928 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5929 kvm_machine_check();
5930
20f65983 5931 /* We need to handle NMIs before interrupts are enabled */
00eba012 5932 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5933 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5934 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5935 asm("int $2");
ff9d07a0
ZY		 5936 kvm_after_handle_nmi(&vmx->vcpu);
5937 }
51aa01d1 5938}
20f65983 5939
51aa01d1
AK		 5940static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5941{
c5ca8e57 5942 u32 exit_intr_info;
51aa01d1
AK		 5943 bool unblock_nmi;
5944 u8 vector;
5945 bool idtv_info_valid;
5946
5947 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5948
cf393f75 5949 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5950 if (vmx->nmi_known_unmasked)
5951 return;
c5ca8e57
AK		 5952 /*
5953 * Can't use vmx->exit_intr_info since we're not sure what
5954 * the exit reason is.
5955 */
5956 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5957 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5958 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5959 /*
7b4a25cb 5960 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5961 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5962 * a guest IRET fault.
7b4a25cb
GN		 5963 * SDM 3: 23.2.2 (September 2008)
5964 * Bit 12 is undefined in any of the following cases:
5965 * If the VM exit sets the valid bit in the IDT-vectoring
5966 * information field.
5967 * If the VM exit is due to a double fault.
cf393f75 5968 */
7b4a25cb
GN		 5969 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5970 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5971 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5972 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5973 else
5974 vmx->nmi_known_unmasked =
5975 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5976 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5977 } else if (unlikely(vmx->soft_vnmi_blocked))
5978 vmx->vnmi_blocked_time +=
5979 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5980}
5981
83422e17
AK		 5982static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5983 u32 idt_vectoring_info,
5984 int instr_len_field,
5985 int error_code_field)
51aa01d1 5986{
51aa01d1
AK		 5987 u8 vector;
5988 int type;
5989 bool idtv_info_valid;
5990
5991 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5992
37b96e98
GN		 5993 vmx->vcpu.arch.nmi_injected = false;
5994 kvm_clear_exception_queue(&vmx->vcpu);
5995 kvm_clear_interrupt_queue(&vmx->vcpu);
5996
5997 if (!idtv_info_valid)
5998 return;
5999
3842d135
AK		 6000 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6001
668f612f
AK		 6002 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6003 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6004
64a7ec06 6005 switch (type) {
37b96e98
GN		 6006 case INTR_TYPE_NMI_INTR:
6007 vmx->vcpu.arch.nmi_injected = true;
668f612f 6008 /*
7b4a25cb 6009 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6010 * Clear bit "block by NMI" before VM entry if a NMI
6011 * delivery faulted.
668f612f 6012 */
654f06fc 6013 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6014 break;
37b96e98 6015 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6016 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6017 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6018 /* fall through */
6019 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6020 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6021 u32 err = vmcs_read32(error_code_field);
37b96e98 6022 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6023 } else
6024 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6025 break;
66fd3f7f
GN		 6026 case INTR_TYPE_SOFT_INTR:
6027 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6028 vmcs_read32(instr_len_field);
66fd3f7f 6029 /* fall through */
37b96e98 6030 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6031 kvm_queue_interrupt(&vmx->vcpu, vector,
6032 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6033 break;
6034 default:
6035 break;
f7d9238f 6036 }
cf393f75
AK		 6037}
6038
83422e17
AK		 6039static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6040{
66c78ae4
NHE		 6041 if (is_guest_mode(&vmx->vcpu))
6042 return;
83422e17
AK		 6043 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6044 VM_EXIT_INSTRUCTION_LEN,
6045 IDT_VECTORING_ERROR_CODE);
6046}
6047
b463a6f7
AK		 6048static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6049{
66c78ae4
NHE		 6050 if (is_guest_mode(vcpu))
6051 return;
b463a6f7
AK		 6052 __vmx_complete_interrupts(to_vmx(vcpu),
6053 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6054 VM_ENTRY_INSTRUCTION_LEN,
6055 VM_ENTRY_EXCEPTION_ERROR_CODE);
6056
6057 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6058}
6059
d7cd9796
GN		 6060static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6061{
6062 int i, nr_msrs;
6063 struct perf_guest_switch_msr *msrs;
6064
6065 msrs = perf_guest_get_msrs(&nr_msrs);
6066
6067 if (!msrs)
6068 return;
6069
6070 for (i = 0; i < nr_msrs; i++)
6071 if (msrs[i].host == msrs[i].guest)
6072 clear_atomic_switch_msr(vmx, msrs[i].msr);
6073 else
6074 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6075 msrs[i].host);
6076}
6077
c801949d
AK		 6078#ifdef CONFIG_X86_64
6079#define R "r"
6080#define Q "q"
6081#else
6082#define R "e"
6083#define Q "l"
6084#endif
6085
a3b5ba49 6086static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6087{
a2fa3e9f 6088 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6089
66c78ae4
NHE		 6090 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6091 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6092 if (vmcs12->idt_vectoring_info_field &
6093 VECTORING_INFO_VALID_MASK) {
6094 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6095 vmcs12->idt_vectoring_info_field);
6096 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6097 vmcs12->vm_exit_instruction_len);
6098 if (vmcs12->idt_vectoring_info_field &
6099 VECTORING_INFO_DELIVER_CODE_MASK)
6100 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6101 vmcs12->idt_vectoring_error_code);
6102 }
6103 }
6104
104f226b
AK		 6105 /* Record the guest's net vcpu time for enforced NMI injections. */
6106 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6107 vmx->entry_time = ktime_get();
6108
6109 /* Don't enter VMX if guest state is invalid, let the exit handler
6110 start emulation until we arrive back to a valid state */
6111 if (vmx->emulation_required && emulate_invalid_guest_state)
6112 return;
6113
6114 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6115 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6116 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6117 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6118
6119 /* When single-stepping over STI and MOV SS, we must clear the
6120 * corresponding interruptibility bits in the guest state. Otherwise
6121 * vmentry fails as it then expects bit 14 (BS) in pending debug
6122 * exceptions being set, but that's not correct for the guest debugging
6123 * case. */
6124 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6125 vmx_set_interrupt_shadow(vcpu, 0);
6126
d7cd9796
GN		 6127 atomic_switch_perf_msrs(vmx);
6128
d462b819 6129 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6130 asm(
6aa8b732 6131 /* Store host registers */
c801949d 6132 "push %%"R"dx; push %%"R"bp;"
40712fae 6133 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6134 "push %%"R"cx \n\t"
313dbd49
AK		 6135 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6136 "je 1f \n\t"
6137 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6138 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6139 "1: \n\t"
d3edefc0
AK		 6140 /* Reload cr2 if changed */
6141 "mov %c[cr2](%0), %%"R"ax \n\t"
6142 "mov %%cr2, %%"R"dx \n\t"
6143 "cmp %%"R"ax, %%"R"dx \n\t"
6144 "je 2f \n\t"
6145 "mov %%"R"ax, %%cr2 \n\t"
6146 "2: \n\t"
6aa8b732 6147 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6148 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6149 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6150 "mov %c[rax](%0), %%"R"ax \n\t"
6151 "mov %c[rbx](%0), %%"R"bx \n\t"
6152 "mov %c[rdx](%0), %%"R"dx \n\t"
6153 "mov %c[rsi](%0), %%"R"si \n\t"
6154 "mov %c[rdi](%0), %%"R"di \n\t"
6155 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6156#ifdef CONFIG_X86_64
e08aa78a
AK		 6157 "mov %c[r8](%0), %%r8 \n\t"
6158 "mov %c[r9](%0), %%r9 \n\t"
6159 "mov %c[r10](%0), %%r10 \n\t"
6160 "mov %c[r11](%0), %%r11 \n\t"
6161 "mov %c[r12](%0), %%r12 \n\t"
6162 "mov %c[r13](%0), %%r13 \n\t"
6163 "mov %c[r14](%0), %%r14 \n\t"
6164 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6165#endif
c801949d
AK		 6166 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6167
6aa8b732 6168 /* Enter guest mode */
cd2276a7 6169 "jne .Llaunched \n\t"
4ecac3fd 6170 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6171 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6172 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6173 ".Lkvm_vmx_return: "
6aa8b732 6174 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6175 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6176 "pop %0 \n\t"
c801949d
AK		 6177 "mov %%"R"ax, %c[rax](%0) \n\t"
6178 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6179 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6180 "mov %%"R"dx, %c[rdx](%0) \n\t"
6181 "mov %%"R"si, %c[rsi](%0) \n\t"
6182 "mov %%"R"di, %c[rdi](%0) \n\t"
6183 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6184#ifdef CONFIG_X86_64
e08aa78a
AK		 6185 "mov %%r8, %c[r8](%0) \n\t"
6186 "mov %%r9, %c[r9](%0) \n\t"
6187 "mov %%r10, %c[r10](%0) \n\t"
6188 "mov %%r11, %c[r11](%0) \n\t"
6189 "mov %%r12, %c[r12](%0) \n\t"
6190 "mov %%r13, %c[r13](%0) \n\t"
6191 "mov %%r14, %c[r14](%0) \n\t"
6192 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6193#endif
c801949d
AK		 6194 "mov %%cr2, %%"R"ax \n\t"
6195 "mov %%"R"ax, %c[cr2](%0) \n\t"
6196
1c696d0e 6197 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6198 "setbe %c[fail](%0) \n\t"
6199 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6200 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6201 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6202 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6203 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6204 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6205 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6206 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6207 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6208 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6209 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6210#ifdef CONFIG_X86_64
ad312c7c
ZX		 6211 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6212 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6213 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6214 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6215 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6216 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6217 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6218 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6219#endif
40712fae
AK		 6220 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6221 [wordsize]"i"(sizeof(ulong))
c2036300 6222 : "cc", "memory"
07d6f555 6223 , R"ax", R"bx", R"di", R"si"
c2036300 6224#ifdef CONFIG_X86_64
c2036300
LV		 6225 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6226#endif
6227 );
6aa8b732 6228
6de4f3ad 6229 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6230 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6231 | (1 << VCPU_EXREG_CPL)
aff48baa 6232 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6233 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6234 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6235 vcpu->arch.regs_dirty = 0;
6236
1155f76a
AK		 6237 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6238
66c78ae4
NHE		 6239 if (is_guest_mode(vcpu)) {
6240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6241 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6242 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6243 vmcs12->idt_vectoring_error_code =
6244 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6245 vmcs12->vm_exit_instruction_len =
6246 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6247 }
6248 }
6249
d77c26fc 6250 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6251 vmx->loaded_vmcs->launched = 1;
1b6269db 6252
51aa01d1 6253 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6254 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6255
6256 vmx_complete_atomic_exit(vmx);
6257 vmx_recover_nmi_blocking(vmx);
cf393f75 6258 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6259}
6260
c801949d
AK		 6261#undef R
6262#undef Q
6263
6aa8b732
AK		 6264static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6265{
fb3f0f51
RR		 6266 struct vcpu_vmx *vmx = to_vmx(vcpu);
6267
cdbecfc3 6268 free_vpid(vmx);
ec378aee 6269 free_nested(vmx);
d462b819 6270 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6271 kfree(vmx->guest_msrs);
6272 kvm_vcpu_uninit(vcpu);
a4770347 6273 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6274}
6275
fb3f0f51 6276static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6277{
fb3f0f51 6278 int err;
c16f862d 6279 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6280 int cpu;
6aa8b732 6281
a2fa3e9f 6282 if (!vmx)
fb3f0f51
RR		 6283 return ERR_PTR(-ENOMEM);
6284
2384d2b3
SY		 6285 allocate_vpid(vmx);
6286
fb3f0f51
RR		 6287 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6288 if (err)
6289 goto free_vcpu;
965b58a5 6290
a2fa3e9f 6291 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6292 err = -ENOMEM;
fb3f0f51 6293 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6294 goto uninit_vcpu;
6295 }
965b58a5 6296
d462b819
NHE		 6297 vmx->loaded_vmcs = &vmx->vmcs01;
6298 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6299 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6300 goto free_msrs;
d462b819
NHE		 6301 if (!vmm_exclusive)
6302 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6303 loaded_vmcs_init(vmx->loaded_vmcs);
6304 if (!vmm_exclusive)
6305 kvm_cpu_vmxoff();
a2fa3e9f 6306
15ad7146
AK		 6307 cpu = get_cpu();
6308 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6309 vmx->vcpu.cpu = cpu;
8b9cf98c 6310 err = vmx_vcpu_setup(vmx);
fb3f0f51 6311 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6312 put_cpu();
fb3f0f51
RR		 6313 if (err)
6314 goto free_vmcs;
5e4a0b3c 6315 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6316 err = alloc_apic_access_page(kvm);
6317 if (err)
5e4a0b3c 6318 goto free_vmcs;
fb3f0f51 6319
b927a3ce
SY		 6320 if (enable_ept) {
6321 if (!kvm->arch.ept_identity_map_addr)
6322 kvm->arch.ept_identity_map_addr =
6323 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6324 err = -ENOMEM;
b7ebfb05
SY		 6325 if (alloc_identity_pagetable(kvm) != 0)
6326 goto free_vmcs;
93ea5388
GN		 6327 if (!init_rmode_identity_map(kvm))
6328 goto free_vmcs;
b927a3ce 6329 }
b7ebfb05 6330
a9d30f33
NHE		 6331 vmx->nested.current_vmptr = -1ull;
6332 vmx->nested.current_vmcs12 = NULL;
6333
fb3f0f51
RR		 6334 return &vmx->vcpu;
6335
6336free_vmcs:
d462b819 6337 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6338free_msrs:
fb3f0f51
RR		 6339 kfree(vmx->guest_msrs);
6340uninit_vcpu:
6341 kvm_vcpu_uninit(&vmx->vcpu);
6342free_vcpu:
cdbecfc3 6343 free_vpid(vmx);
a4770347 6344 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6345 return ERR_PTR(err);
6aa8b732
AK		 6346}
6347
002c7f7c
YS		 6348static void __init vmx_check_processor_compat(void *rtn)
6349{
6350 struct vmcs_config vmcs_conf;
6351
6352 *(int *)rtn = 0;
6353 if (setup_vmcs_config(&vmcs_conf) < 0)
6354 *(int *)rtn = -EIO;
6355 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6356 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6357 smp_processor_id());
6358 *(int *)rtn = -EIO;
6359 }
6360}
6361
67253af5
SY		 6362static int get_ept_level(void)
6363{
6364 return VMX_EPT_DEFAULT_GAW + 1;
6365}
6366
4b12f0de 6367static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6368{
4b12f0de
SY		 6369 u64 ret;
6370
522c68c4
SY		 6371 /* For VT-d and EPT combination
6372 * 1. MMIO: always map as UC
6373 * 2. EPT with VT-d:
6374 * a. VT-d without snooping control feature: can't guarantee the
6375 * result, try to trust guest.
6376 * b. VT-d with snooping control feature: snooping control feature of
6377 * VT-d engine can guarantee the cache correctness. Just set it
6378 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6379 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6380 * consistent with host MTRR
6381 */
4b12f0de
SY		 6382 if (is_mmio)
6383 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6384 else if (vcpu->kvm->arch.iommu_domain &&
6385 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6386 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6387 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6388 else
522c68c4 6389 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6390 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6391
6392 return ret;
64d4d521
SY		 6393}
6394
17cc3935 6395static int vmx_get_lpage_level(void)
344f414f 6396{
878403b7
SY		 6397 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6398 return PT_DIRECTORY_LEVEL;
6399 else
6400 /* For shadow and EPT supported 1GB page */
6401 return PT_PDPE_LEVEL;
344f414f
JR		 6402}
6403
0e851880
SY		 6404static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6405{
4e47c7a6
SY		 6406 struct kvm_cpuid_entry2 *best;
6407 struct vcpu_vmx *vmx = to_vmx(vcpu);
6408 u32 exec_control;
6409
6410 vmx->rdtscp_enabled = false;
6411 if (vmx_rdtscp_supported()) {
6412 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6413 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6414 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6415 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6416 vmx->rdtscp_enabled = true;
6417 else {
6418 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6419 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6420 exec_control);
6421 }
6422 }
6423 }
0e851880
SY		 6424}
6425
d4330ef2
JR		 6426static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6427{
7b8050f5
NHE		 6428 if (func == 1 && nested)
6429 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6430}
6431
fe3ef05c
NHE		 6432/*
6433 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6434 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6435 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6436 * guest in a way that will both be appropriate to L1's requests, and our
6437 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6438 * function also has additional necessary side-effects, like setting various
6439 * vcpu->arch fields.
6440 */
6441static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6442{
6443 struct vcpu_vmx *vmx = to_vmx(vcpu);
6444 u32 exec_control;
6445
6446 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6447 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6448 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6449 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6450 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6451 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6452 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6453 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6454 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6455 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6456 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6457 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6458 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6459 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6460 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6461 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6462 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6463 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6464 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6465 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6466 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6467 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6468 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6469 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6470 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6471 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6472 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6473 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6474 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6475 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6476 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6477 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6478 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6479 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6480 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6481 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6482
6483 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6485 vmcs12->vm_entry_intr_info_field);
6486 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6487 vmcs12->vm_entry_exception_error_code);
6488 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6489 vmcs12->vm_entry_instruction_len);
6490 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6491 vmcs12->guest_interruptibility_info);
6492 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6493 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6494 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6495 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6496 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6497 vmcs12->guest_pending_dbg_exceptions);
6498 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6499 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6500
6501 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6502
6503 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6504 (vmcs_config.pin_based_exec_ctrl |
6505 vmcs12->pin_based_vm_exec_control));
6506
6507 /*
6508 * Whether page-faults are trapped is determined by a combination of
6509 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6510 * If enable_ept, L0 doesn't care about page faults and we should
6511 * set all of these to L1's desires. However, if !enable_ept, L0 does
6512 * care about (at least some) page faults, and because it is not easy
6513 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6514 * to exit on each and every L2 page fault. This is done by setting
6515 * MASK=MATCH=0 and (see below) EB.PF=1.
6516 * Note that below we don't need special code to set EB.PF beyond the
6517 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6518 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6519 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6520 *
6521 * A problem with this approach (when !enable_ept) is that L1 may be
6522 * injected with more page faults than it asked for. This could have
6523 * caused problems, but in practice existing hypervisors don't care.
6524 * To fix this, we will need to emulate the PFEC checking (on the L1
6525 * page tables), using walk_addr(), when injecting PFs to L1.
6526 */
6527 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6528 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6529 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6530 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6531
6532 if (cpu_has_secondary_exec_ctrls()) {
6533 u32 exec_control = vmx_secondary_exec_control(vmx);
6534 if (!vmx->rdtscp_enabled)
6535 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6536 /* Take the following fields only from vmcs12 */
6537 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6538 if (nested_cpu_has(vmcs12,
6539 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6540 exec_control |= vmcs12->secondary_vm_exec_control;
6541
6542 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6543 /*
6544 * Translate L1 physical address to host physical
6545 * address for vmcs02. Keep the page pinned, so this
6546 * physical address remains valid. We keep a reference
6547 * to it so we can release it later.
6548 */
6549 if (vmx->nested.apic_access_page) /* shouldn't happen */
6550 nested_release_page(vmx->nested.apic_access_page);
6551 vmx->nested.apic_access_page =
6552 nested_get_page(vcpu, vmcs12->apic_access_addr);
6553 /*
6554 * If translation failed, no matter: This feature asks
6555 * to exit when accessing the given address, and if it
6556 * can never be accessed, this feature won't do
6557 * anything anyway.
6558 */
6559 if (!vmx->nested.apic_access_page)
6560 exec_control &=
6561 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6562 else
6563 vmcs_write64(APIC_ACCESS_ADDR,
6564 page_to_phys(vmx->nested.apic_access_page));
6565 }
6566
6567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6568 }
6569
6570
6571 /*
6572 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6573 * Some constant fields are set here by vmx_set_constant_host_state().
6574 * Other fields are different per CPU, and will be set later when
6575 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6576 */
6577 vmx_set_constant_host_state();
6578
6579 /*
6580 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6581 * entry, but only if the current (host) sp changed from the value
6582 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6583 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6584 * here we just force the write to happen on entry.
6585 */
6586 vmx->host_rsp = 0;
6587
6588 exec_control = vmx_exec_control(vmx); /* L0's desires */
6589 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6590 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6591 exec_control &= ~CPU_BASED_TPR_SHADOW;
6592 exec_control |= vmcs12->cpu_based_vm_exec_control;
6593 /*
6594 * Merging of IO and MSR bitmaps not currently supported.
6595 * Rather, exit every time.
6596 */
6597 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6598 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6599 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6600
6601 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6602
6603 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6604 * bitwise-or of what L1 wants to trap for L2, and what we want to
6605 * trap. Note that CR0.TS also needs updating - we do this later.
6606 */
6607 update_exception_bitmap(vcpu);
6608 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6609 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6610
6611 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6612 vmcs_write32(VM_EXIT_CONTROLS,
6613 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6614 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6615 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6616
6617 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6618 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6619 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6620 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6621
6622
6623 set_cr4_guest_host_mask(vmx);
6624
27fc51b2
NHE		 6625 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6626 vmcs_write64(TSC_OFFSET,
6627 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6628 else
6629 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6630
6631 if (enable_vpid) {
6632 /*
6633 * Trivially support vpid by letting L2s share their parent
6634 * L1's vpid. TODO: move to a more elaborate solution, giving
6635 * each L2 its own vpid and exposing the vpid feature to L1.
6636 */
6637 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6638 vmx_flush_tlb(vcpu);
6639 }
6640
6641 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6642 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6643 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6644 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6645 else
6646 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6647 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6648 vmx_set_efer(vcpu, vcpu->arch.efer);
6649
6650 /*
6651 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6652 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6653 * The CR0_READ_SHADOW is what L2 should have expected to read given
6654 * the specifications by L1; It's not enough to take
6655 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6656 * have more bits than L1 expected.
6657 */
6658 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6659 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6660
6661 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6662 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6663
6664 /* shadow page tables on either EPT or shadow page tables */
6665 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6666 kvm_mmu_reset_context(vcpu);
6667
6668 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6669 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6670}
6671
cd232ad0
NHE		 6672/*
6673 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6674 * for running an L2 nested guest.
6675 */
6676static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6677{
6678 struct vmcs12 *vmcs12;
6679 struct vcpu_vmx *vmx = to_vmx(vcpu);
6680 int cpu;
6681 struct loaded_vmcs *vmcs02;
6682
6683 if (!nested_vmx_check_permission(vcpu) ||
6684 !nested_vmx_check_vmcs12(vcpu))
6685 return 1;
6686
6687 skip_emulated_instruction(vcpu);
6688 vmcs12 = get_vmcs12(vcpu);
6689
7c177938
NHE		 6690 /*
6691 * The nested entry process starts with enforcing various prerequisites
6692 * on vmcs12 as required by the Intel SDM, and act appropriately when
6693 * they fail: As the SDM explains, some conditions should cause the
6694 * instruction to fail, while others will cause the instruction to seem
6695 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6696 * To speed up the normal (success) code path, we should avoid checking
6697 * for misconfigurations which will anyway be caught by the processor
6698 * when using the merged vmcs02.
6699 */
6700 if (vmcs12->launch_state == launch) {
6701 nested_vmx_failValid(vcpu,
6702 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6703 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6704 return 1;
6705 }
6706
6707 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6708 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6709 /*TODO: Also verify bits beyond physical address width are 0*/
6710 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6711 return 1;
6712 }
6713
6714 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6715 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6716 /*TODO: Also verify bits beyond physical address width are 0*/
6717 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6718 return 1;
6719 }
6720
6721 if (vmcs12->vm_entry_msr_load_count > 0 ||
6722 vmcs12->vm_exit_msr_load_count > 0 ||
6723 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6724 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6725 __func__);
7c177938
NHE		 6726 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6727 return 1;
6728 }
6729
6730 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6731 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6732 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6733 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6734 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6735 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6736 !vmx_control_verify(vmcs12->vm_exit_controls,
6737 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6738 !vmx_control_verify(vmcs12->vm_entry_controls,
6739 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6740 {
6741 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6742 return 1;
6743 }
6744
6745 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6746 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6747 nested_vmx_failValid(vcpu,
6748 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6749 return 1;
6750 }
6751
6752 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6753 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6754 nested_vmx_entry_failure(vcpu, vmcs12,
6755 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6756 return 1;
6757 }
6758 if (vmcs12->vmcs_link_pointer != -1ull) {
6759 nested_vmx_entry_failure(vcpu, vmcs12,
6760 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6761 return 1;
6762 }
6763
6764 /*
6765 * We're finally done with prerequisite checking, and can start with
6766 * the nested entry.
6767 */
6768
cd232ad0
NHE		 6769 vmcs02 = nested_get_current_vmcs02(vmx);
6770 if (!vmcs02)
6771 return -ENOMEM;
6772
6773 enter_guest_mode(vcpu);
6774
6775 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6776
6777 cpu = get_cpu();
6778 vmx->loaded_vmcs = vmcs02;
6779 vmx_vcpu_put(vcpu);
6780 vmx_vcpu_load(vcpu, cpu);
6781 vcpu->cpu = cpu;
6782 put_cpu();
6783
6784 vmcs12->launch_state = 1;
6785
6786 prepare_vmcs02(vcpu, vmcs12);
6787
6788 /*
6789 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6790 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6791 * returned as far as L1 is concerned. It will only return (and set
6792 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6793 */
6794 return 1;
6795}
6796
4704d0be
NHE		 6797/*
6798 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6799 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6800 * This function returns the new value we should put in vmcs12.guest_cr0.
6801 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6802 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6803 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6804 * didn't trap the bit, because if L1 did, so would L0).
6805 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6806 * been modified by L2, and L1 knows it. So just leave the old value of
6807 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6808 * isn't relevant, because if L0 traps this bit it can set it to anything.
6809 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6810 * changed these bits, and therefore they need to be updated, but L0
6811 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6812 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6813 */
6814static inline unsigned long
6815vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6816{
6817 return
6818 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6819 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6820 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6821 vcpu->arch.cr0_guest_owned_bits));
6822}
6823
6824static inline unsigned long
6825vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6826{
6827 return
6828 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6829 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6830 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6831 vcpu->arch.cr4_guest_owned_bits));
6832}
6833
6834/*
6835 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6836 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6837 * and this function updates it to reflect the changes to the guest state while
6838 * L2 was running (and perhaps made some exits which were handled directly by L0
6839 * without going back to L1), and to reflect the exit reason.
6840 * Note that we do not have to copy here all VMCS fields, just those that
6841 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6842 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6843 * which already writes to vmcs12 directly.
6844 */
6845void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6846{
6847 /* update guest state fields: */
6848 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6849 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6850
6851 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6852 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6853 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6854 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6855
6856 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6857 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6858 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6859 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6860 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6861 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6862 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6863 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6864 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6865 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6866 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6867 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6868 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6869 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6870 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6871 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6872 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6873 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6874 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6875 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6876 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6877 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6878 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6879 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6880 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6881 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6882 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6883 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6884 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6885 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6886 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6887 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6888 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6889 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6890 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6891 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6892
6893 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6894 vmcs12->guest_interruptibility_info =
6895 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6896 vmcs12->guest_pending_dbg_exceptions =
6897 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6898
6899 /* TODO: These cannot have changed unless we have MSR bitmaps and
6900 * the relevant bit asks not to trap the change */
6901 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6902 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6903 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6904 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6905 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6906 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6907
6908 /* update exit information fields: */
6909
6910 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6911 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6912
6913 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6914 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6915 vmcs12->idt_vectoring_info_field =
6916 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6917 vmcs12->idt_vectoring_error_code =
6918 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6919 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6920 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6921
6922 /* clear vm-entry fields which are to be cleared on exit */
6923 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6924 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6925}
6926
6927/*
6928 * A part of what we need to when the nested L2 guest exits and we want to
6929 * run its L1 parent, is to reset L1's guest state to the host state specified
6930 * in vmcs12.
6931 * This function is to be called not only on normal nested exit, but also on
6932 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6933 * Failures During or After Loading Guest State").
6934 * This function should be called when the active VMCS is L1's (vmcs01).
6935 */
6936void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6937{
6938 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6939 vcpu->arch.efer = vmcs12->host_ia32_efer;
6940 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6941 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6942 else
6943 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6944 vmx_set_efer(vcpu, vcpu->arch.efer);
6945
6946 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6947 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6948 /*
6949 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6950 * actually changed, because it depends on the current state of
6951 * fpu_active (which may have changed).
6952 * Note that vmx_set_cr0 refers to efer set above.
6953 */
6954 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6955 /*
6956 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6957 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6958 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6959 */
6960 update_exception_bitmap(vcpu);
6961 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6962 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6963
6964 /*
6965 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6966 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6967 */
6968 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6969 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6970
6971 /* shadow page tables on either EPT or shadow page tables */
6972 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6973 kvm_mmu_reset_context(vcpu);
6974
6975 if (enable_vpid) {
6976 /*
6977 * Trivially support vpid by letting L2s share their parent
6978 * L1's vpid. TODO: move to a more elaborate solution, giving
6979 * each L2 its own vpid and exposing the vpid feature to L1.
6980 */
6981 vmx_flush_tlb(vcpu);
6982 }
6983
6984
6985 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6986 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6987 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6988 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6989 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6990 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6991 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6992 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6993 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6994 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6995 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6996 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6997 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6998 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6999 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7000
7001 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7002 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7003 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7004 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7005 vmcs12->host_ia32_perf_global_ctrl);
7006}
7007
7008/*
7009 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7010 * and modify vmcs12 to make it see what it would expect to see there if
7011 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7012 */
7013static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7014{
7015 struct vcpu_vmx *vmx = to_vmx(vcpu);
7016 int cpu;
7017 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7018
7019 leave_guest_mode(vcpu);
7020 prepare_vmcs12(vcpu, vmcs12);
7021
7022 cpu = get_cpu();
7023 vmx->loaded_vmcs = &vmx->vmcs01;
7024 vmx_vcpu_put(vcpu);
7025 vmx_vcpu_load(vcpu, cpu);
7026 vcpu->cpu = cpu;
7027 put_cpu();
7028
7029 /* if no vmcs02 cache requested, remove the one we used */
7030 if (VMCS02_POOL_SIZE == 0)
7031 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7032
7033 load_vmcs12_host_state(vcpu, vmcs12);
7034
27fc51b2 7035 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7036 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7037
7038 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7039 vmx->host_rsp = 0;
7040
7041 /* Unpin physical memory we referred to in vmcs02 */
7042 if (vmx->nested.apic_access_page) {
7043 nested_release_page(vmx->nested.apic_access_page);
7044 vmx->nested.apic_access_page = 0;
7045 }
7046
7047 /*
7048 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7049 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7050 * success or failure flag accordingly.
7051 */
7052 if (unlikely(vmx->fail)) {
7053 vmx->fail = 0;
7054 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7055 } else
7056 nested_vmx_succeed(vcpu);
7057}
7058
7c177938
NHE		 7059/*
7060 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7061 * 23.7 "VM-entry failures during or after loading guest state" (this also
7062 * lists the acceptable exit-reason and exit-qualification parameters).
7063 * It should only be called before L2 actually succeeded to run, and when
7064 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7065 */
7066static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7067 struct vmcs12 *vmcs12,
7068 u32 reason, unsigned long qualification)
7069{
7070 load_vmcs12_host_state(vcpu, vmcs12);
7071 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7072 vmcs12->exit_qualification = qualification;
7073 nested_vmx_succeed(vcpu);
7074}
7075
8a76d7f2
JR		 7076static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7077 struct x86_instruction_info *info,
7078 enum x86_intercept_stage stage)
7079{
7080 return X86EMUL_CONTINUE;
7081}
7082
cbdd1bea 7083static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7084 .cpu_has_kvm_support = cpu_has_kvm_support,
7085 .disabled_by_bios = vmx_disabled_by_bios,
7086 .hardware_setup = hardware_setup,
7087 .hardware_unsetup = hardware_unsetup,
002c7f7c 7088 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7089 .hardware_enable = hardware_enable,
7090 .hardware_disable = hardware_disable,
04547156 7091 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7092
7093 .vcpu_create = vmx_create_vcpu,
7094 .vcpu_free = vmx_free_vcpu,
04d2cc77 7095 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7096
04d2cc77 7097 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7098 .vcpu_load = vmx_vcpu_load,
7099 .vcpu_put = vmx_vcpu_put,
7100
7101 .set_guest_debug = set_guest_debug,
7102 .get_msr = vmx_get_msr,
7103 .set_msr = vmx_set_msr,
7104 .get_segment_base = vmx_get_segment_base,
7105 .get_segment = vmx_get_segment,
7106 .set_segment = vmx_set_segment,
2e4d2653 7107 .get_cpl = vmx_get_cpl,
6aa8b732 7108 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7109 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7110 .decache_cr3 = vmx_decache_cr3,
25c4c276 7111 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7112 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7113 .set_cr3 = vmx_set_cr3,
7114 .set_cr4 = vmx_set_cr4,
6aa8b732 7115 .set_efer = vmx_set_efer,
6aa8b732
AK		 7116 .get_idt = vmx_get_idt,
7117 .set_idt = vmx_set_idt,
7118 .get_gdt = vmx_get_gdt,
7119 .set_gdt = vmx_set_gdt,
020df079 7120 .set_dr7 = vmx_set_dr7,
5fdbf976 7121 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7122 .get_rflags = vmx_get_rflags,
7123 .set_rflags = vmx_set_rflags,
ebcbab4c 7124 .fpu_activate = vmx_fpu_activate,
02daab21 7125 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7126
7127 .tlb_flush = vmx_flush_tlb,
6aa8b732 7128
6aa8b732 7129 .run = vmx_vcpu_run,
6062d012 7130 .handle_exit = vmx_handle_exit,
6aa8b732 7131 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7132 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7133 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7134 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7135 .set_irq = vmx_inject_irq,
95ba8273 7136 .set_nmi = vmx_inject_nmi,
298101da 7137 .queue_exception = vmx_queue_exception,
b463a6f7 7138 .cancel_injection = vmx_cancel_injection,
78646121 7139 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7140 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7141 .get_nmi_mask = vmx_get_nmi_mask,
7142 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7143 .enable_nmi_window = enable_nmi_window,
7144 .enable_irq_window = enable_irq_window,
7145 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7146
cbc94022 7147 .set_tss_addr = vmx_set_tss_addr,
67253af5 7148 .get_tdp_level = get_ept_level,
4b12f0de 7149 .get_mt_mask = vmx_get_mt_mask,
229456fc 7150
586f9607 7151 .get_exit_info = vmx_get_exit_info,
586f9607 7152
17cc3935 7153 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7154
7155 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7156
7157 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7158
7159 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7160
7161 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7162
4051b188 7163 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7164 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7165 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7166 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7167 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7168
7169 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7170
7171 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7172};
7173
7174static int __init vmx_init(void)
7175{
26bb0981
AK		 7176 int r, i;
7177
7178 rdmsrl_safe(MSR_EFER, &host_efer);
7179
7180 for (i = 0; i < NR_VMX_MSR; ++i)
7181 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7182
3e7c73e9 7183 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7184 if (!vmx_io_bitmap_a)
7185 return -ENOMEM;
7186
3e7c73e9 7187 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7188 if (!vmx_io_bitmap_b) {
7189 r = -ENOMEM;
7190 goto out;
7191 }
7192
5897297b
AK		 7193 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7194 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7195 r = -ENOMEM;
7196 goto out1;
7197 }
7198
5897297b
AK		 7199 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7200 if (!vmx_msr_bitmap_longmode) {
7201 r = -ENOMEM;
7202 goto out2;
7203 }
7204
fdef3ad1
HQ		 7205 /*
7206 * Allow direct access to the PC debug port (it is often used for I/O
7207 * delays, but the vmexits simply slow things down).
7208 */
3e7c73e9
AK		 7209 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7210 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7211
3e7c73e9 7212 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7213
5897297b
AK		 7214 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7215 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7216
2384d2b3
SY		 7217 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7218
0ee75bea
AK		 7219 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7220 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7221 if (r)
5897297b 7222 goto out3;
25c5f225 7223
5897297b
AK		 7224 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7225 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7226 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7227 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7228 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7229 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7230
089d034e 7231 if (enable_ept) {
534e38b4 7232 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7233 VMX_EPT_EXECUTABLE_MASK);
ce88decf 7234 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7235 kvm_enable_tdp();
7236 } else
7237 kvm_disable_tdp();
1439442c 7238
fdef3ad1
HQ		 7239 return 0;
7240
5897297b
AK		 7241out3:
7242 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7243out2:
5897297b 7244 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7245out1:
3e7c73e9 7246 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7247out:
3e7c73e9 7248 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7249 return r;
6aa8b732
AK		 7250}
7251
7252static void __exit vmx_exit(void)
7253{
5897297b
AK		 7254 free_page((unsigned long)vmx_msr_bitmap_legacy);
7255 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7256 free_page((unsigned long)vmx_io_bitmap_b);
7257 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7258
cb498ea2 7259 kvm_exit();
6aa8b732
AK		 7260}
7261
7262module_init(vmx_init)
7263module_exit(vmx_exit)
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