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KVM: nVMX: Introduce vmread and vmwrite bitmaps
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 358
359 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
360 struct list_head vmcs02_pool;
361 int vmcs02_num;
fe3ef05c 362 u64 vmcs01_tsc_offset;
644d711a
NHE		 363 /* L2 must run next, and mustn't decide to exit to L1. */
364 bool nested_run_pending;
fe3ef05c
NHE		 365 /*
366 * Guest pages referred to in vmcs02 with host-physical pointers, so
367 * we must keep them pinned while L2 runs.
368 */
369 struct page *apic_access_page;
ec378aee
NHE		 370};
371
01e439be
YZ		 372#define POSTED_INTR_ON 0
373/* Posted-Interrupt Descriptor */
374struct pi_desc {
375 u32 pir[8]; /* Posted interrupt requested */
376 u32 control; /* bit 0 of control is outstanding notification bit */
377 u32 rsvd[7];
378} __aligned(64);
379
a20ed54d
YZ		 380static bool pi_test_and_set_on(struct pi_desc *pi_desc)
381{
382 return test_and_set_bit(POSTED_INTR_ON,
383 (unsigned long *)&pi_desc->control);
384}
385
386static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
387{
388 return test_and_clear_bit(POSTED_INTR_ON,
389 (unsigned long *)&pi_desc->control);
390}
391
392static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
393{
394 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
395}
396
a2fa3e9f 397struct vcpu_vmx {
fb3f0f51 398 struct kvm_vcpu vcpu;
313dbd49 399 unsigned long host_rsp;
29bd8a78 400 u8 fail;
69c73028 401 u8 cpl;
9d58b931 402 bool nmi_known_unmasked;
51aa01d1 403 u32 exit_intr_info;
1155f76a 404 u32 idt_vectoring_info;
6de12732 405 ulong rflags;
26bb0981 406 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 407 int nmsrs;
408 int save_nmsrs;
a547c6db 409 unsigned long host_idt_base;
a2fa3e9f 410#ifdef CONFIG_X86_64
44ea2b17
AK		 411 u64 msr_host_kernel_gs_base;
412 u64 msr_guest_kernel_gs_base;
a2fa3e9f 413#endif
d462b819
NHE		 414 /*
415 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
416 * non-nested (L1) guest, it always points to vmcs01. For a nested
417 * guest (L2), it points to a different VMCS.
418 */
419 struct loaded_vmcs vmcs01;
420 struct loaded_vmcs *loaded_vmcs;
421 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 422 struct msr_autoload {
423 unsigned nr;
424 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
425 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
426 } msr_autoload;
a2fa3e9f
GH		 427 struct {
428 int loaded;
429 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 430#ifdef CONFIG_X86_64
431 u16 ds_sel, es_sel;
432#endif
152d3f2f
LV		 433 int gs_ldt_reload_needed;
434 int fs_reload_needed;
d77c26fc 435 } host_state;
9c8cba37 436 struct {
7ffd92c5 437 int vm86_active;
78ac8b47 438 ulong save_rflags;
f5f7b2fe
AK		 439 struct kvm_segment segs[8];
440 } rmode;
441 struct {
442 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 443 struct kvm_save_segment {
444 u16 selector;
445 unsigned long base;
446 u32 limit;
447 u32 ar;
f5f7b2fe 448 } seg[8];
2fb92db1 449 } segment_cache;
2384d2b3 450 int vpid;
04fa4d32 451 bool emulation_required;
3b86cd99
JK		 452
453 /* Support for vnmi-less CPUs */
454 int soft_vnmi_blocked;
455 ktime_t entry_time;
456 s64 vnmi_blocked_time;
a0861c02 457 u32 exit_reason;
4e47c7a6
SY		 458
459 bool rdtscp_enabled;
ec378aee 460
01e439be
YZ		 461 /* Posted interrupt descriptor */
462 struct pi_desc pi_desc;
463
ec378aee
NHE		 464 /* Support for a guest hypervisor (nested VMX) */
465 struct nested_vmx nested;
a2fa3e9f
GH		 466};
467
2fb92db1
AK		 468enum segment_cache_field {
469 SEG_FIELD_SEL = 0,
470 SEG_FIELD_BASE = 1,
471 SEG_FIELD_LIMIT = 2,
472 SEG_FIELD_AR = 3,
473
474 SEG_FIELD_NR = 4
475};
476
a2fa3e9f
GH		 477static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
478{
fb3f0f51 479 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 480}
481
22bd0358
NHE		 482#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
483#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
484#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
485 [number##_HIGH] = VMCS12_OFFSET(name)+4
486
4607c2d7
AG		 487
488static const unsigned long shadow_read_only_fields[] = {
489 /*
490 * We do NOT shadow fields that are modified when L0
491 * traps and emulates any vmx instruction (e.g. VMPTRLD,
492 * VMXON...) executed by L1.
493 * For example, VM_INSTRUCTION_ERROR is read
494 * by L1 if a vmx instruction fails (part of the error path).
495 * Note the code assumes this logic. If for some reason
496 * we start shadowing these fields then we need to
497 * force a shadow sync when L0 emulates vmx instructions
498 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
499 * by nested_vmx_failValid)
500 */
501 VM_EXIT_REASON,
502 VM_EXIT_INTR_INFO,
503 VM_EXIT_INSTRUCTION_LEN,
504 IDT_VECTORING_INFO_FIELD,
505 IDT_VECTORING_ERROR_CODE,
506 VM_EXIT_INTR_ERROR_CODE,
507 EXIT_QUALIFICATION,
508 GUEST_LINEAR_ADDRESS,
509 GUEST_PHYSICAL_ADDRESS
510};
511static const int max_shadow_read_only_fields =
512 ARRAY_SIZE(shadow_read_only_fields);
513
514static const unsigned long shadow_read_write_fields[] = {
515 GUEST_RIP,
516 GUEST_RSP,
517 GUEST_CR0,
518 GUEST_CR3,
519 GUEST_CR4,
520 GUEST_INTERRUPTIBILITY_INFO,
521 GUEST_RFLAGS,
522 GUEST_CS_SELECTOR,
523 GUEST_CS_AR_BYTES,
524 GUEST_CS_LIMIT,
525 GUEST_CS_BASE,
526 GUEST_ES_BASE,
527 CR0_GUEST_HOST_MASK,
528 CR0_READ_SHADOW,
529 CR4_READ_SHADOW,
530 TSC_OFFSET,
531 EXCEPTION_BITMAP,
532 CPU_BASED_VM_EXEC_CONTROL,
533 VM_ENTRY_EXCEPTION_ERROR_CODE,
534 VM_ENTRY_INTR_INFO_FIELD,
535 VM_ENTRY_INSTRUCTION_LEN,
536 VM_ENTRY_EXCEPTION_ERROR_CODE,
537 HOST_FS_BASE,
538 HOST_GS_BASE,
539 HOST_FS_SELECTOR,
540 HOST_GS_SELECTOR
541};
542static const int max_shadow_read_write_fields =
543 ARRAY_SIZE(shadow_read_write_fields);
544
772e0318 545static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 546 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
547 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
548 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
549 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
550 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
551 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
552 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
553 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
554 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
555 FIELD(HOST_ES_SELECTOR, host_es_selector),
556 FIELD(HOST_CS_SELECTOR, host_cs_selector),
557 FIELD(HOST_SS_SELECTOR, host_ss_selector),
558 FIELD(HOST_DS_SELECTOR, host_ds_selector),
559 FIELD(HOST_FS_SELECTOR, host_fs_selector),
560 FIELD(HOST_GS_SELECTOR, host_gs_selector),
561 FIELD(HOST_TR_SELECTOR, host_tr_selector),
562 FIELD64(IO_BITMAP_A, io_bitmap_a),
563 FIELD64(IO_BITMAP_B, io_bitmap_b),
564 FIELD64(MSR_BITMAP, msr_bitmap),
565 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
566 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
567 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
568 FIELD64(TSC_OFFSET, tsc_offset),
569 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
570 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
571 FIELD64(EPT_POINTER, ept_pointer),
572 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
573 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
574 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
575 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
576 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
577 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
578 FIELD64(GUEST_PDPTR0, guest_pdptr0),
579 FIELD64(GUEST_PDPTR1, guest_pdptr1),
580 FIELD64(GUEST_PDPTR2, guest_pdptr2),
581 FIELD64(GUEST_PDPTR3, guest_pdptr3),
582 FIELD64(HOST_IA32_PAT, host_ia32_pat),
583 FIELD64(HOST_IA32_EFER, host_ia32_efer),
584 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
585 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
586 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
587 FIELD(EXCEPTION_BITMAP, exception_bitmap),
588 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
589 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
590 FIELD(CR3_TARGET_COUNT, cr3_target_count),
591 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
592 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
593 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
594 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
595 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
596 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
597 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
598 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
599 FIELD(TPR_THRESHOLD, tpr_threshold),
600 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
601 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
602 FIELD(VM_EXIT_REASON, vm_exit_reason),
603 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
604 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
605 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
606 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
607 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
608 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
609 FIELD(GUEST_ES_LIMIT, guest_es_limit),
610 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
611 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
612 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
613 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
614 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
615 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
616 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
617 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
618 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
619 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
620 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
621 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
622 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
623 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
624 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
625 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
626 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
627 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
628 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
629 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
630 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 631 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 632 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
633 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
634 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
635 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
636 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
637 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
638 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
639 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
640 FIELD(EXIT_QUALIFICATION, exit_qualification),
641 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
642 FIELD(GUEST_CR0, guest_cr0),
643 FIELD(GUEST_CR3, guest_cr3),
644 FIELD(GUEST_CR4, guest_cr4),
645 FIELD(GUEST_ES_BASE, guest_es_base),
646 FIELD(GUEST_CS_BASE, guest_cs_base),
647 FIELD(GUEST_SS_BASE, guest_ss_base),
648 FIELD(GUEST_DS_BASE, guest_ds_base),
649 FIELD(GUEST_FS_BASE, guest_fs_base),
650 FIELD(GUEST_GS_BASE, guest_gs_base),
651 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
652 FIELD(GUEST_TR_BASE, guest_tr_base),
653 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
654 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
655 FIELD(GUEST_DR7, guest_dr7),
656 FIELD(GUEST_RSP, guest_rsp),
657 FIELD(GUEST_RIP, guest_rip),
658 FIELD(GUEST_RFLAGS, guest_rflags),
659 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
660 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
661 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
662 FIELD(HOST_CR0, host_cr0),
663 FIELD(HOST_CR3, host_cr3),
664 FIELD(HOST_CR4, host_cr4),
665 FIELD(HOST_FS_BASE, host_fs_base),
666 FIELD(HOST_GS_BASE, host_gs_base),
667 FIELD(HOST_TR_BASE, host_tr_base),
668 FIELD(HOST_GDTR_BASE, host_gdtr_base),
669 FIELD(HOST_IDTR_BASE, host_idtr_base),
670 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
671 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
672 FIELD(HOST_RSP, host_rsp),
673 FIELD(HOST_RIP, host_rip),
674};
675static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
676
677static inline short vmcs_field_to_offset(unsigned long field)
678{
679 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
680 return -1;
681 return vmcs_field_to_offset_table[field];
682}
683
a9d30f33
NHE		 684static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
685{
686 return to_vmx(vcpu)->nested.current_vmcs12;
687}
688
689static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
690{
691 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 692 if (is_error_page(page))
a9d30f33 693 return NULL;
32cad84f 694
a9d30f33
NHE		 695 return page;
696}
697
698static void nested_release_page(struct page *page)
699{
700 kvm_release_page_dirty(page);
701}
702
703static void nested_release_page_clean(struct page *page)
704{
705 kvm_release_page_clean(page);
706}
707
4e1096d2 708static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 709static void kvm_cpu_vmxon(u64 addr);
710static void kvm_cpu_vmxoff(void);
aff48baa 711static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 712static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 713static void vmx_set_segment(struct kvm_vcpu *vcpu,
714 struct kvm_segment *var, int seg);
715static void vmx_get_segment(struct kvm_vcpu *vcpu,
716 struct kvm_segment *var, int seg);
d99e4152
GN		 717static bool guest_state_valid(struct kvm_vcpu *vcpu);
718static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 719static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
75880a01 720
6aa8b732
AK		 721static DEFINE_PER_CPU(struct vmcs *, vmxarea);
722static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 723/*
724 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
725 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
726 */
727static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 728static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 729
3e7c73e9
AK		 730static unsigned long *vmx_io_bitmap_a;
731static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 732static unsigned long *vmx_msr_bitmap_legacy;
733static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 734static unsigned long *vmx_msr_bitmap_legacy_x2apic;
735static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 736static unsigned long *vmx_vmread_bitmap;
737static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 738
110312c8 739static bool cpu_has_load_ia32_efer;
8bf00a52 740static bool cpu_has_load_perf_global_ctrl;
110312c8 741
2384d2b3
SY		 742static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
743static DEFINE_SPINLOCK(vmx_vpid_lock);
744
1c3d14fe 745static struct vmcs_config {
6aa8b732
AK		 746 int size;
747 int order;
748 u32 revision_id;
1c3d14fe
YS		 749 u32 pin_based_exec_ctrl;
750 u32 cpu_based_exec_ctrl;
f78e0e2e 751 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 752 u32 vmexit_ctrl;
753 u32 vmentry_ctrl;
754} vmcs_config;
6aa8b732 755
efff9e53 756static struct vmx_capability {
d56f546d
SY		 757 u32 ept;
758 u32 vpid;
759} vmx_capability;
760
6aa8b732
AK		 761#define VMX_SEGMENT_FIELD(seg) \
762 [VCPU_SREG_##seg] = { \
763 .selector = GUEST_##seg##_SELECTOR, \
764 .base = GUEST_##seg##_BASE, \
765 .limit = GUEST_##seg##_LIMIT, \
766 .ar_bytes = GUEST_##seg##_AR_BYTES, \
767 }
768
772e0318 769static const struct kvm_vmx_segment_field {
6aa8b732
AK		 770 unsigned selector;
771 unsigned base;
772 unsigned limit;
773 unsigned ar_bytes;
774} kvm_vmx_segment_fields[] = {
775 VMX_SEGMENT_FIELD(CS),
776 VMX_SEGMENT_FIELD(DS),
777 VMX_SEGMENT_FIELD(ES),
778 VMX_SEGMENT_FIELD(FS),
779 VMX_SEGMENT_FIELD(GS),
780 VMX_SEGMENT_FIELD(SS),
781 VMX_SEGMENT_FIELD(TR),
782 VMX_SEGMENT_FIELD(LDTR),
783};
784
26bb0981
AK		 785static u64 host_efer;
786
6de4f3ad
AK		 787static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
788
4d56c8a7 789/*
8c06585d 790 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 791 * away by decrementing the array size.
792 */
6aa8b732 793static const u32 vmx_msr_index[] = {
05b3e0c2 794#ifdef CONFIG_X86_64
44ea2b17 795 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 796#endif
8c06585d 797 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 798};
9d8f549d 799#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 800
31299944 801static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 802{
803 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
804 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 805 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 806}
807
31299944 808static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 809{
810 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
811 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 812 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 813}
814
31299944 815static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 816{
817 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
818 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 819 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 820}
821
31299944 822static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 823{
824 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
825 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
826}
827
31299944 828static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 829{
830 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
831 INTR_INFO_VALID_MASK)) ==
832 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
833}
834
31299944 835static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 836{
04547156 837 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 838}
839
31299944 840static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 841{
04547156 842 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 843}
844
31299944 845static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 846{
04547156 847 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 848}
849
31299944 850static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 851{
04547156
SY		 852 return vmcs_config.cpu_based_exec_ctrl &
853 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 854}
855
774ead3a 856static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 857{
04547156
SY		 858 return vmcs_config.cpu_based_2nd_exec_ctrl &
859 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
860}
861
8d14695f
YZ		 862static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
863{
864 return vmcs_config.cpu_based_2nd_exec_ctrl &
865 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
866}
867
83d4c286
YZ		 868static inline bool cpu_has_vmx_apic_register_virt(void)
869{
870 return vmcs_config.cpu_based_2nd_exec_ctrl &
871 SECONDARY_EXEC_APIC_REGISTER_VIRT;
872}
873
c7c9c56c
YZ		 874static inline bool cpu_has_vmx_virtual_intr_delivery(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
878}
879
01e439be
YZ		 880static inline bool cpu_has_vmx_posted_intr(void)
881{
882 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
883}
884
885static inline bool cpu_has_vmx_apicv(void)
886{
887 return cpu_has_vmx_apic_register_virt() &&
888 cpu_has_vmx_virtual_intr_delivery() &&
889 cpu_has_vmx_posted_intr();
890}
891
04547156
SY		 892static inline bool cpu_has_vmx_flexpriority(void)
893{
894 return cpu_has_vmx_tpr_shadow() &&
895 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 896}
897
e799794e
MT		 898static inline bool cpu_has_vmx_ept_execute_only(void)
899{
31299944 900 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 901}
902
903static inline bool cpu_has_vmx_eptp_uncacheable(void)
904{
31299944 905 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 906}
907
908static inline bool cpu_has_vmx_eptp_writeback(void)
909{
31299944 910 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 911}
912
913static inline bool cpu_has_vmx_ept_2m_page(void)
914{
31299944 915 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 916}
917
878403b7
SY		 918static inline bool cpu_has_vmx_ept_1g_page(void)
919{
31299944 920 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 921}
922
4bc9b982
SY		 923static inline bool cpu_has_vmx_ept_4levels(void)
924{
925 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
926}
927
83c3a331
XH		 928static inline bool cpu_has_vmx_ept_ad_bits(void)
929{
930 return vmx_capability.ept & VMX_EPT_AD_BIT;
931}
932
31299944 933static inline bool cpu_has_vmx_invept_context(void)
d56f546d 934{
31299944 935 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 936}
937
31299944 938static inline bool cpu_has_vmx_invept_global(void)
d56f546d 939{
31299944 940 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 941}
942
518c8aee
GJ		 943static inline bool cpu_has_vmx_invvpid_single(void)
944{
945 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
946}
947
b9d762fa
GJ		 948static inline bool cpu_has_vmx_invvpid_global(void)
949{
950 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
951}
952
31299944 953static inline bool cpu_has_vmx_ept(void)
d56f546d 954{
04547156
SY		 955 return vmcs_config.cpu_based_2nd_exec_ctrl &
956 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 957}
958
31299944 959static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 960{
961 return vmcs_config.cpu_based_2nd_exec_ctrl &
962 SECONDARY_EXEC_UNRESTRICTED_GUEST;
963}
964
31299944 965static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 966{
967 return vmcs_config.cpu_based_2nd_exec_ctrl &
968 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
969}
970
31299944 971static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 972{
6d3e435e 973 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 974}
975
31299944 976static inline bool cpu_has_vmx_vpid(void)
2384d2b3 977{
04547156
SY		 978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 980}
981
31299944 982static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 983{
984 return vmcs_config.cpu_based_2nd_exec_ctrl &
985 SECONDARY_EXEC_RDTSCP;
986}
987
ad756a16
MJ		 988static inline bool cpu_has_vmx_invpcid(void)
989{
990 return vmcs_config.cpu_based_2nd_exec_ctrl &
991 SECONDARY_EXEC_ENABLE_INVPCID;
992}
993
31299944 994static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 995{
996 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
997}
998
f5f48ee1
SY		 999static inline bool cpu_has_vmx_wbinvd_exit(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_WBINVD_EXITING;
1003}
1004
abc4fc58
AG		 1005static inline bool cpu_has_vmx_shadow_vmcs(void)
1006{
1007 u64 vmx_msr;
1008 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1009 /* check if the cpu supports writing r/o exit information fields */
1010 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1011 return false;
1012
1013 return vmcs_config.cpu_based_2nd_exec_ctrl &
1014 SECONDARY_EXEC_SHADOW_VMCS;
1015}
1016
04547156
SY		 1017static inline bool report_flexpriority(void)
1018{
1019 return flexpriority_enabled;
1020}
1021
fe3ef05c
NHE		 1022static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1023{
1024 return vmcs12->cpu_based_vm_exec_control & bit;
1025}
1026
1027static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1028{
1029 return (vmcs12->cpu_based_vm_exec_control &
1030 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1031 (vmcs12->secondary_vm_exec_control & bit);
1032}
1033
644d711a
NHE		 1034static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1035 struct kvm_vcpu *vcpu)
1036{
1037 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1038}
1039
1040static inline bool is_exception(u32 intr_info)
1041{
1042 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1043 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1044}
1045
1046static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1047static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1048 struct vmcs12 *vmcs12,
1049 u32 reason, unsigned long qualification);
1050
8b9cf98c 1051static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1052{
1053 int i;
1054
a2fa3e9f 1055 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1056 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1057 return i;
1058 return -1;
1059}
1060
2384d2b3
SY		 1061static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1062{
1063 struct {
1064 u64 vpid : 16;
1065 u64 rsvd : 48;
1066 u64 gva;
1067 } operand = { vpid, 0, gva };
1068
4ecac3fd 1069 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1070 /* CF==1 or ZF==1 --> rc = -1 */
1071 "; ja 1f ; ud2 ; 1:"
1072 : : "a"(&operand), "c"(ext) : "cc", "memory");
1073}
1074
1439442c
SY		 1075static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1076{
1077 struct {
1078 u64 eptp, gpa;
1079 } operand = {eptp, gpa};
1080
4ecac3fd 1081 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1082 /* CF==1 or ZF==1 --> rc = -1 */
1083 "; ja 1f ; ud2 ; 1:\n"
1084 : : "a" (&operand), "c" (ext) : "cc", "memory");
1085}
1086
26bb0981 1087static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1088{
1089 int i;
1090
8b9cf98c 1091 i = __find_msr_index(vmx, msr);
a75beee6 1092 if (i >= 0)
a2fa3e9f 1093 return &vmx->guest_msrs[i];
8b6d44c7 1094 return NULL;
7725f0ba
AK		 1095}
1096
6aa8b732
AK		 1097static void vmcs_clear(struct vmcs *vmcs)
1098{
1099 u64 phys_addr = __pa(vmcs);
1100 u8 error;
1101
4ecac3fd 1102 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1103 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1104 : "cc", "memory");
1105 if (error)
1106 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1107 vmcs, phys_addr);
1108}
1109
d462b819
NHE		 1110static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1111{
1112 vmcs_clear(loaded_vmcs->vmcs);
1113 loaded_vmcs->cpu = -1;
1114 loaded_vmcs->launched = 0;
1115}
1116
7725b894
DX		 1117static void vmcs_load(struct vmcs *vmcs)
1118{
1119 u64 phys_addr = __pa(vmcs);
1120 u8 error;
1121
1122 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1123 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1124 : "cc", "memory");
1125 if (error)
2844d849 1126 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1127 vmcs, phys_addr);
1128}
1129
8f536b76
ZY		 1130#ifdef CONFIG_KEXEC
1131/*
1132 * This bitmap is used to indicate whether the vmclear
1133 * operation is enabled on all cpus. All disabled by
1134 * default.
1135 */
1136static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1137
1138static inline void crash_enable_local_vmclear(int cpu)
1139{
1140 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1141}
1142
1143static inline void crash_disable_local_vmclear(int cpu)
1144{
1145 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1146}
1147
1148static inline int crash_local_vmclear_enabled(int cpu)
1149{
1150 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1151}
1152
1153static void crash_vmclear_local_loaded_vmcss(void)
1154{
1155 int cpu = raw_smp_processor_id();
1156 struct loaded_vmcs *v;
1157
1158 if (!crash_local_vmclear_enabled(cpu))
1159 return;
1160
1161 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1162 loaded_vmcss_on_cpu_link)
1163 vmcs_clear(v->vmcs);
1164}
1165#else
1166static inline void crash_enable_local_vmclear(int cpu) { }
1167static inline void crash_disable_local_vmclear(int cpu) { }
1168#endif /* CONFIG_KEXEC */
1169
d462b819 1170static void __loaded_vmcs_clear(void *arg)
6aa8b732 1171{
d462b819 1172 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1173 int cpu = raw_smp_processor_id();
6aa8b732 1174
d462b819
NHE		 1175 if (loaded_vmcs->cpu != cpu)
1176 return; /* vcpu migration can race with cpu offline */
1177 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1178 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1179 crash_disable_local_vmclear(cpu);
d462b819 1180 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1181
1182 /*
1183 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1184 * is before setting loaded_vmcs->vcpu to -1 which is done in
1185 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1186 * then adds the vmcs into percpu list before it is deleted.
1187 */
1188 smp_wmb();
1189
d462b819 1190 loaded_vmcs_init(loaded_vmcs);
8f536b76 1191 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1192}
1193
d462b819 1194static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1195{
e6c7d321
XG		 1196 int cpu = loaded_vmcs->cpu;
1197
1198 if (cpu != -1)
1199 smp_call_function_single(cpu,
1200 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1201}
1202
1760dd49 1203static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1204{
1205 if (vmx->vpid == 0)
1206 return;
1207
518c8aee
GJ		 1208 if (cpu_has_vmx_invvpid_single())
1209 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1210}
1211
b9d762fa
GJ		 1212static inline void vpid_sync_vcpu_global(void)
1213{
1214 if (cpu_has_vmx_invvpid_global())
1215 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1216}
1217
1218static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1219{
1220 if (cpu_has_vmx_invvpid_single())
1760dd49 1221 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1222 else
1223 vpid_sync_vcpu_global();
1224}
1225
1439442c
SY		 1226static inline void ept_sync_global(void)
1227{
1228 if (cpu_has_vmx_invept_global())
1229 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1230}
1231
1232static inline void ept_sync_context(u64 eptp)
1233{
089d034e 1234 if (enable_ept) {
1439442c
SY		 1235 if (cpu_has_vmx_invept_context())
1236 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1237 else
1238 ept_sync_global();
1239 }
1240}
1241
96304217 1242static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1243{
5e520e62 1244 unsigned long value;
6aa8b732 1245
5e520e62
AK		 1246 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1247 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1248 return value;
1249}
1250
96304217 1251static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1252{
1253 return vmcs_readl(field);
1254}
1255
96304217 1256static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1257{
1258 return vmcs_readl(field);
1259}
1260
96304217 1261static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1262{
05b3e0c2 1263#ifdef CONFIG_X86_64
6aa8b732
AK		 1264 return vmcs_readl(field);
1265#else
1266 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1267#endif
1268}
1269
e52de1b8
AK		 1270static noinline void vmwrite_error(unsigned long field, unsigned long value)
1271{
1272 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1273 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1274 dump_stack();
1275}
1276
6aa8b732
AK		 1277static void vmcs_writel(unsigned long field, unsigned long value)
1278{
1279 u8 error;
1280
4ecac3fd 1281 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1282 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1283 if (unlikely(error))
1284 vmwrite_error(field, value);
6aa8b732
AK		 1285}
1286
1287static void vmcs_write16(unsigned long field, u16 value)
1288{
1289 vmcs_writel(field, value);
1290}
1291
1292static void vmcs_write32(unsigned long field, u32 value)
1293{
1294 vmcs_writel(field, value);
1295}
1296
1297static void vmcs_write64(unsigned long field, u64 value)
1298{
6aa8b732 1299 vmcs_writel(field, value);
7682f2d0 1300#ifndef CONFIG_X86_64
6aa8b732
AK		 1301 asm volatile ("");
1302 vmcs_writel(field+1, value >> 32);
1303#endif
1304}
1305
2ab455cc
AL		 1306static void vmcs_clear_bits(unsigned long field, u32 mask)
1307{
1308 vmcs_writel(field, vmcs_readl(field) & ~mask);
1309}
1310
1311static void vmcs_set_bits(unsigned long field, u32 mask)
1312{
1313 vmcs_writel(field, vmcs_readl(field) | mask);
1314}
1315
2fb92db1
AK		 1316static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1317{
1318 vmx->segment_cache.bitmask = 0;
1319}
1320
1321static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1322 unsigned field)
1323{
1324 bool ret;
1325 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1326
1327 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1328 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1329 vmx->segment_cache.bitmask = 0;
1330 }
1331 ret = vmx->segment_cache.bitmask & mask;
1332 vmx->segment_cache.bitmask |= mask;
1333 return ret;
1334}
1335
1336static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1337{
1338 u16 *p = &vmx->segment_cache.seg[seg].selector;
1339
1340 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1341 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1342 return *p;
1343}
1344
1345static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1346{
1347 ulong *p = &vmx->segment_cache.seg[seg].base;
1348
1349 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1350 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1351 return *p;
1352}
1353
1354static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1355{
1356 u32 *p = &vmx->segment_cache.seg[seg].limit;
1357
1358 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1359 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1360 return *p;
1361}
1362
1363static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1364{
1365 u32 *p = &vmx->segment_cache.seg[seg].ar;
1366
1367 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1368 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1369 return *p;
1370}
1371
abd3f2d6
AK		 1372static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1373{
1374 u32 eb;
1375
fd7373cc
JK		 1376 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1377 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1378 if ((vcpu->guest_debug &
1379 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1380 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1381 eb |= 1u << BP_VECTOR;
7ffd92c5 1382 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1383 eb = ~0;
089d034e 1384 if (enable_ept)
1439442c 1385 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1386 if (vcpu->fpu_active)
1387 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1388
1389 /* When we are running a nested L2 guest and L1 specified for it a
1390 * certain exception bitmap, we must trap the same exceptions and pass
1391 * them to L1. When running L2, we will only handle the exceptions
1392 * specified above if L1 did not want them.
1393 */
1394 if (is_guest_mode(vcpu))
1395 eb |= get_vmcs12(vcpu)->exception_bitmap;
1396
abd3f2d6
AK		 1397 vmcs_write32(EXCEPTION_BITMAP, eb);
1398}
1399
8bf00a52
GN		 1400static void clear_atomic_switch_msr_special(unsigned long entry,
1401 unsigned long exit)
1402{
1403 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1404 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1405}
1406
61d2ef2c
AK		 1407static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1408{
1409 unsigned i;
1410 struct msr_autoload *m = &vmx->msr_autoload;
1411
8bf00a52
GN		 1412 switch (msr) {
1413 case MSR_EFER:
1414 if (cpu_has_load_ia32_efer) {
1415 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1416 VM_EXIT_LOAD_IA32_EFER);
1417 return;
1418 }
1419 break;
1420 case MSR_CORE_PERF_GLOBAL_CTRL:
1421 if (cpu_has_load_perf_global_ctrl) {
1422 clear_atomic_switch_msr_special(
1423 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1424 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1425 return;
1426 }
1427 break;
110312c8
AK		 1428 }
1429
61d2ef2c
AK		 1430 for (i = 0; i < m->nr; ++i)
1431 if (m->guest[i].index == msr)
1432 break;
1433
1434 if (i == m->nr)
1435 return;
1436 --m->nr;
1437 m->guest[i] = m->guest[m->nr];
1438 m->host[i] = m->host[m->nr];
1439 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1440 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1441}
1442
8bf00a52
GN		 1443static void add_atomic_switch_msr_special(unsigned long entry,
1444 unsigned long exit, unsigned long guest_val_vmcs,
1445 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1446{
1447 vmcs_write64(guest_val_vmcs, guest_val);
1448 vmcs_write64(host_val_vmcs, host_val);
1449 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1450 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1451}
1452
61d2ef2c
AK		 1453static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1454 u64 guest_val, u64 host_val)
1455{
1456 unsigned i;
1457 struct msr_autoload *m = &vmx->msr_autoload;
1458
8bf00a52
GN		 1459 switch (msr) {
1460 case MSR_EFER:
1461 if (cpu_has_load_ia32_efer) {
1462 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1463 VM_EXIT_LOAD_IA32_EFER,
1464 GUEST_IA32_EFER,
1465 HOST_IA32_EFER,
1466 guest_val, host_val);
1467 return;
1468 }
1469 break;
1470 case MSR_CORE_PERF_GLOBAL_CTRL:
1471 if (cpu_has_load_perf_global_ctrl) {
1472 add_atomic_switch_msr_special(
1473 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1474 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1475 GUEST_IA32_PERF_GLOBAL_CTRL,
1476 HOST_IA32_PERF_GLOBAL_CTRL,
1477 guest_val, host_val);
1478 return;
1479 }
1480 break;
110312c8
AK		 1481 }
1482
61d2ef2c
AK		 1483 for (i = 0; i < m->nr; ++i)
1484 if (m->guest[i].index == msr)
1485 break;
1486
e7fc6f93
GN		 1487 if (i == NR_AUTOLOAD_MSRS) {
1488 printk_once(KERN_WARNING"Not enough mst switch entries. "
1489 "Can't add msr %x\n", msr);
1490 return;
1491 } else if (i == m->nr) {
61d2ef2c
AK		 1492 ++m->nr;
1493 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1494 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1495 }
1496
1497 m->guest[i].index = msr;
1498 m->guest[i].value = guest_val;
1499 m->host[i].index = msr;
1500 m->host[i].value = host_val;
1501}
1502
33ed6329
AK		 1503static void reload_tss(void)
1504{
33ed6329
AK		 1505 /*
1506 * VT restores TR but not its size. Useless.
1507 */
d359192f 1508 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1509 struct desc_struct *descs;
33ed6329 1510
d359192f 1511 descs = (void *)gdt->address;
33ed6329
AK		 1512 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1513 load_TR_desc();
33ed6329
AK		 1514}
1515
92c0d900 1516static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1517{
3a34a881 1518 u64 guest_efer;
51c6cf66
AK		 1519 u64 ignore_bits;
1520
f6801dff 1521 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1522
51c6cf66 1523 /*
0fa06071 1524 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1525 * outside long mode
1526 */
1527 ignore_bits = EFER_NX | EFER_SCE;
1528#ifdef CONFIG_X86_64
1529 ignore_bits |= EFER_LMA | EFER_LME;
1530 /* SCE is meaningful only in long mode on Intel */
1531 if (guest_efer & EFER_LMA)
1532 ignore_bits &= ~(u64)EFER_SCE;
1533#endif
51c6cf66
AK		 1534 guest_efer &= ~ignore_bits;
1535 guest_efer |= host_efer & ignore_bits;
26bb0981 1536 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1537 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1538
1539 clear_atomic_switch_msr(vmx, MSR_EFER);
1540 /* On ept, can't emulate nx, and must switch nx atomically */
1541 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1542 guest_efer = vmx->vcpu.arch.efer;
1543 if (!(guest_efer & EFER_LMA))
1544 guest_efer &= ~EFER_LME;
1545 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1546 return false;
1547 }
1548
26bb0981 1549 return true;
51c6cf66
AK		 1550}
1551
2d49ec72
GN		 1552static unsigned long segment_base(u16 selector)
1553{
d359192f 1554 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1555 struct desc_struct *d;
1556 unsigned long table_base;
1557 unsigned long v;
1558
1559 if (!(selector & ~3))
1560 return 0;
1561
d359192f 1562 table_base = gdt->address;
2d49ec72
GN		 1563
1564 if (selector & 4) { /* from ldt */
1565 u16 ldt_selector = kvm_read_ldt();
1566
1567 if (!(ldt_selector & ~3))
1568 return 0;
1569
1570 table_base = segment_base(ldt_selector);
1571 }
1572 d = (struct desc_struct *)(table_base + (selector & ~7));
1573 v = get_desc_base(d);
1574#ifdef CONFIG_X86_64
1575 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1576 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1577#endif
1578 return v;
1579}
1580
1581static inline unsigned long kvm_read_tr_base(void)
1582{
1583 u16 tr;
1584 asm("str %0" : "=g"(tr));
1585 return segment_base(tr);
1586}
1587
04d2cc77 1588static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1589{
04d2cc77 1590 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1591 int i;
04d2cc77 1592
a2fa3e9f 1593 if (vmx->host_state.loaded)
33ed6329
AK		 1594 return;
1595
a2fa3e9f 1596 vmx->host_state.loaded = 1;
33ed6329
AK		 1597 /*
1598 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1599 * allow segment selectors with cpl > 0 or ti == 1.
1600 */
d6e88aec 1601 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1602 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1603 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1604 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1605 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1606 vmx->host_state.fs_reload_needed = 0;
1607 } else {
33ed6329 1608 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1609 vmx->host_state.fs_reload_needed = 1;
33ed6329 1610 }
9581d442 1611 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1612 if (!(vmx->host_state.gs_sel & 7))
1613 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1614 else {
1615 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1616 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1617 }
1618
b2da15ac
AK		 1619#ifdef CONFIG_X86_64
1620 savesegment(ds, vmx->host_state.ds_sel);
1621 savesegment(es, vmx->host_state.es_sel);
1622#endif
1623
33ed6329
AK		 1624#ifdef CONFIG_X86_64
1625 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1626 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1627#else
a2fa3e9f
GH		 1628 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1629 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1630#endif
707c0874
AK		 1631
1632#ifdef CONFIG_X86_64
c8770e7b
AK		 1633 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1634 if (is_long_mode(&vmx->vcpu))
44ea2b17 1635 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1636#endif
26bb0981
AK		 1637 for (i = 0; i < vmx->save_nmsrs; ++i)
1638 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1639 vmx->guest_msrs[i].data,
1640 vmx->guest_msrs[i].mask);
33ed6329
AK		 1641}
1642
a9b21b62 1643static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1644{
a2fa3e9f 1645 if (!vmx->host_state.loaded)
33ed6329
AK		 1646 return;
1647
e1beb1d3 1648 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1649 vmx->host_state.loaded = 0;
c8770e7b
AK		 1650#ifdef CONFIG_X86_64
1651 if (is_long_mode(&vmx->vcpu))
1652 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1653#endif
152d3f2f 1654 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1655 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1656#ifdef CONFIG_X86_64
9581d442 1657 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1658#else
1659 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1660#endif
33ed6329 1661 }
0a77fe4c
AK		 1662 if (vmx->host_state.fs_reload_needed)
1663 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1664#ifdef CONFIG_X86_64
1665 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1666 loadsegment(ds, vmx->host_state.ds_sel);
1667 loadsegment(es, vmx->host_state.es_sel);
1668 }
b2da15ac 1669#endif
152d3f2f 1670 reload_tss();
44ea2b17 1671#ifdef CONFIG_X86_64
c8770e7b 1672 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1673#endif
b1a74bf8
SS		 1674 /*
1675 * If the FPU is not active (through the host task or
1676 * the guest vcpu), then restore the cr0.TS bit.
1677 */
1678 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1679 stts();
3444d7da 1680 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1681}
1682
a9b21b62
AK		 1683static void vmx_load_host_state(struct vcpu_vmx *vmx)
1684{
1685 preempt_disable();
1686 __vmx_load_host_state(vmx);
1687 preempt_enable();
1688}
1689
6aa8b732
AK		 1690/*
1691 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1692 * vcpu mutex is already taken.
1693 */
15ad7146 1694static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1695{
a2fa3e9f 1696 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1697 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1698
4610c9cc
DX		 1699 if (!vmm_exclusive)
1700 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1701 else if (vmx->loaded_vmcs->cpu != cpu)
1702 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1703
d462b819
NHE		 1704 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1705 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1706 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1707 }
1708
d462b819 1709 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1710 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1711 unsigned long sysenter_esp;
1712
a8eeb04a 1713 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1714 local_irq_disable();
8f536b76 1715 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1716
1717 /*
1718 * Read loaded_vmcs->cpu should be before fetching
1719 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1720 * See the comments in __loaded_vmcs_clear().
1721 */
1722 smp_rmb();
1723
d462b819
NHE		 1724 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1725 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1726 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1727 local_irq_enable();
1728
6aa8b732
AK		 1729 /*
1730 * Linux uses per-cpu TSS and GDT, so set these when switching
1731 * processors.
1732 */
d6e88aec 1733 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1734 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1735
1736 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1737 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1738 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1739 }
6aa8b732
AK		 1740}
1741
1742static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1743{
a9b21b62 1744 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1745 if (!vmm_exclusive) {
d462b819
NHE		 1746 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1747 vcpu->cpu = -1;
4610c9cc
DX		 1748 kvm_cpu_vmxoff();
1749 }
6aa8b732
AK		 1750}
1751
5fd86fcf
AK		 1752static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1753{
81231c69
AK		 1754 ulong cr0;
1755
5fd86fcf
AK		 1756 if (vcpu->fpu_active)
1757 return;
1758 vcpu->fpu_active = 1;
81231c69
AK		 1759 cr0 = vmcs_readl(GUEST_CR0);
1760 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1761 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1762 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1763 update_exception_bitmap(vcpu);
edcafe3c 1764 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1765 if (is_guest_mode(vcpu))
1766 vcpu->arch.cr0_guest_owned_bits &=
1767 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1768 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1769}
1770
edcafe3c
AK		 1771static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1772
fe3ef05c
NHE		 1773/*
1774 * Return the cr0 value that a nested guest would read. This is a combination
1775 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1776 * its hypervisor (cr0_read_shadow).
1777 */
1778static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1779{
1780 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1781 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1782}
1783static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1784{
1785 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1786 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1787}
1788
5fd86fcf
AK		 1789static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1790{
36cf24e0
NHE		 1791 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1792 * set this *before* calling this function.
1793 */
edcafe3c 1794 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1795 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1796 update_exception_bitmap(vcpu);
edcafe3c
AK		 1797 vcpu->arch.cr0_guest_owned_bits = 0;
1798 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1799 if (is_guest_mode(vcpu)) {
1800 /*
1801 * L1's specified read shadow might not contain the TS bit,
1802 * so now that we turned on shadowing of this bit, we need to
1803 * set this bit of the shadow. Like in nested_vmx_run we need
1804 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1805 * up-to-date here because we just decached cr0.TS (and we'll
1806 * only update vmcs12->guest_cr0 on nested exit).
1807 */
1808 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1809 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1810 (vcpu->arch.cr0 & X86_CR0_TS);
1811 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1812 } else
1813 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1814}
1815
6aa8b732
AK		 1816static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1817{
78ac8b47 1818 unsigned long rflags, save_rflags;
345dcaa8 1819
6de12732
AK		 1820 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1821 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1822 rflags = vmcs_readl(GUEST_RFLAGS);
1823 if (to_vmx(vcpu)->rmode.vm86_active) {
1824 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1825 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1826 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1827 }
1828 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1829 }
6de12732 1830 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1831}
1832
1833static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1834{
6de12732
AK		 1835 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1836 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1837 if (to_vmx(vcpu)->rmode.vm86_active) {
1838 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1839 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1840 }
6aa8b732
AK		 1841 vmcs_writel(GUEST_RFLAGS, rflags);
1842}
1843
2809f5d2
GC		 1844static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1845{
1846 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1847 int ret = 0;
1848
1849 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1850 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1851 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1852 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1853
1854 return ret & mask;
1855}
1856
1857static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 u32 interruptibility = interruptibility_old;
1861
1862 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1863
48005f64 1864 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1865 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1866 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1867 interruptibility |= GUEST_INTR_STATE_STI;
1868
1869 if ((interruptibility != interruptibility_old))
1870 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1871}
1872
6aa8b732
AK		 1873static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1874{
1875 unsigned long rip;
6aa8b732 1876
5fdbf976 1877 rip = kvm_rip_read(vcpu);
6aa8b732 1878 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1879 kvm_rip_write(vcpu, rip);
6aa8b732 1880
2809f5d2
GC		 1881 /* skipping an emulated instruction also counts */
1882 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1883}
1884
0b6ac343
NHE		 1885/*
1886 * KVM wants to inject page-faults which it got to the guest. This function
1887 * checks whether in a nested guest, we need to inject them to L1 or L2.
1888 * This function assumes it is called with the exit reason in vmcs02 being
1889 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1890 * is running).
1891 */
1892static int nested_pf_handled(struct kvm_vcpu *vcpu)
1893{
1894 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1895
1896 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1897 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1898 return 0;
1899
1900 nested_vmx_vmexit(vcpu);
1901 return 1;
1902}
1903
298101da 1904static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1905 bool has_error_code, u32 error_code,
1906 bool reinject)
298101da 1907{
77ab6db0 1908 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1909 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1910
0b6ac343
NHE		 1911 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1912 nested_pf_handled(vcpu))
1913 return;
1914
8ab2d2e2 1915 if (has_error_code) {
77ab6db0 1916 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1917 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1918 }
77ab6db0 1919
7ffd92c5 1920 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1921 int inc_eip = 0;
1922 if (kvm_exception_is_soft(nr))
1923 inc_eip = vcpu->arch.event_exit_inst_len;
1924 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1925 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1926 return;
1927 }
1928
66fd3f7f
GN		 1929 if (kvm_exception_is_soft(nr)) {
1930 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1931 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1932 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1933 } else
1934 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1935
1936 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1937}
1938
4e47c7a6
SY		 1939static bool vmx_rdtscp_supported(void)
1940{
1941 return cpu_has_vmx_rdtscp();
1942}
1943
ad756a16
MJ		 1944static bool vmx_invpcid_supported(void)
1945{
1946 return cpu_has_vmx_invpcid() && enable_ept;
1947}
1948
a75beee6
ED		 1949/*
1950 * Swap MSR entry in host/guest MSR entry array.
1951 */
8b9cf98c 1952static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1953{
26bb0981 1954 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1955
1956 tmp = vmx->guest_msrs[to];
1957 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1958 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1959}
1960
8d14695f
YZ		 1961static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1962{
1963 unsigned long *msr_bitmap;
1964
1965 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1966 if (is_long_mode(vcpu))
1967 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1968 else
1969 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1970 } else {
1971 if (is_long_mode(vcpu))
1972 msr_bitmap = vmx_msr_bitmap_longmode;
1973 else
1974 msr_bitmap = vmx_msr_bitmap_legacy;
1975 }
1976
1977 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1978}
1979
e38aea3e
AK		 1980/*
1981 * Set up the vmcs to automatically save and restore system
1982 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1983 * mode, as fiddling with msrs is very expensive.
1984 */
8b9cf98c 1985static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1986{
26bb0981 1987 int save_nmsrs, index;
e38aea3e 1988
a75beee6
ED		 1989 save_nmsrs = 0;
1990#ifdef CONFIG_X86_64
8b9cf98c 1991 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1992 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1993 if (index >= 0)
8b9cf98c
RR		 1994 move_msr_up(vmx, index, save_nmsrs++);
1995 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1996 if (index >= 0)
8b9cf98c
RR		 1997 move_msr_up(vmx, index, save_nmsrs++);
1998 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1999 if (index >= 0)
8b9cf98c 2000 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2001 index = __find_msr_index(vmx, MSR_TSC_AUX);
2002 if (index >= 0 && vmx->rdtscp_enabled)
2003 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2004 /*
8c06585d 2005 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2006 * if efer.sce is enabled.
2007 */
8c06585d 2008 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2009 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2010 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2011 }
2012#endif
92c0d900
AK		 2013 index = __find_msr_index(vmx, MSR_EFER);
2014 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2015 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2016
26bb0981 2017 vmx->save_nmsrs = save_nmsrs;
5897297b 2018
8d14695f
YZ		 2019 if (cpu_has_vmx_msr_bitmap())
2020 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2021}
2022
6aa8b732
AK		 2023/*
2024 * reads and returns guest's timestamp counter "register"
2025 * guest_tsc = host_tsc + tsc_offset -- 21.3
2026 */
2027static u64 guest_read_tsc(void)
2028{
2029 u64 host_tsc, tsc_offset;
2030
2031 rdtscll(host_tsc);
2032 tsc_offset = vmcs_read64(TSC_OFFSET);
2033 return host_tsc + tsc_offset;
2034}
2035
d5c1785d
NHE		 2036/*
2037 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2038 * counter, even if a nested guest (L2) is currently running.
2039 */
886b470c 2040u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2041{
886b470c 2042 u64 tsc_offset;
d5c1785d 2043
d5c1785d
NHE		 2044 tsc_offset = is_guest_mode(vcpu) ?
2045 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2046 vmcs_read64(TSC_OFFSET);
2047 return host_tsc + tsc_offset;
2048}
2049
4051b188 2050/*
cc578287
ZA		 2051 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2052 * software catchup for faster rates on slower CPUs.
4051b188 2053 */
cc578287 2054static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2055{
cc578287
ZA		 2056 if (!scale)
2057 return;
2058
2059 if (user_tsc_khz > tsc_khz) {
2060 vcpu->arch.tsc_catchup = 1;
2061 vcpu->arch.tsc_always_catchup = 1;
2062 } else
2063 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2064}
2065
ba904635
WA		 2066static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2067{
2068 return vmcs_read64(TSC_OFFSET);
2069}
2070
6aa8b732 2071/*
99e3e30a 2072 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2073 */
99e3e30a 2074static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2075{
27fc51b2 2076 if (is_guest_mode(vcpu)) {
7991825b 2077 /*
27fc51b2
NHE		 2078 * We're here if L1 chose not to trap WRMSR to TSC. According
2079 * to the spec, this should set L1's TSC; The offset that L1
2080 * set for L2 remains unchanged, and still needs to be added
2081 * to the newly set TSC to get L2's TSC.
7991825b 2082 */
27fc51b2
NHE		 2083 struct vmcs12 *vmcs12;
2084 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2085 /* recalculate vmcs02.TSC_OFFSET: */
2086 vmcs12 = get_vmcs12(vcpu);
2087 vmcs_write64(TSC_OFFSET, offset +
2088 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2089 vmcs12->tsc_offset : 0));
2090 } else {
2091 vmcs_write64(TSC_OFFSET, offset);
2092 }
6aa8b732
AK		 2093}
2094
f1e2b260 2095static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2096{
2097 u64 offset = vmcs_read64(TSC_OFFSET);
2098 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2099 if (is_guest_mode(vcpu)) {
2100 /* Even when running L2, the adjustment needs to apply to L1 */
2101 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2102 }
e48672fa
ZA		 2103}
2104
857e4099
JR		 2105static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2106{
2107 return target_tsc - native_read_tsc();
2108}
2109
801d3424
NHE		 2110static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2111{
2112 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2113 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2114}
2115
2116/*
2117 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2118 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2119 * all guests if the "nested" module option is off, and can also be disabled
2120 * for a single guest by disabling its VMX cpuid bit.
2121 */
2122static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2123{
2124 return nested && guest_cpuid_has_vmx(vcpu);
2125}
2126
b87a51ae
NHE		 2127/*
2128 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2129 * returned for the various VMX controls MSRs when nested VMX is enabled.
2130 * The same values should also be used to verify that vmcs12 control fields are
2131 * valid during nested entry from L1 to L2.
2132 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2133 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2134 * bit in the high half is on if the corresponding bit in the control field
2135 * may be on. See also vmx_control_verify().
2136 * TODO: allow these variables to be modified (downgraded) by module options
2137 * or other means.
2138 */
2139static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2140static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2141static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2142static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2143static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2144static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2145static __init void nested_vmx_setup_ctls_msrs(void)
2146{
2147 /*
2148 * Note that as a general rule, the high half of the MSRs (bits in
2149 * the control fields which may be 1) should be initialized by the
2150 * intersection of the underlying hardware's MSR (i.e., features which
2151 * can be supported) and the list of features we want to expose -
2152 * because they are known to be properly supported in our code.
2153 * Also, usually, the low half of the MSRs (bits which must be 1) can
2154 * be set to 0, meaning that L1 may turn off any of these bits. The
2155 * reason is that if one of these bits is necessary, it will appear
2156 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2157 * fields of vmcs01 and vmcs02, will turn these bits off - and
2158 * nested_vmx_exit_handled() will not pass related exits to L1.
2159 * These rules have exceptions below.
2160 */
2161
2162 /* pin-based controls */
eabeaacc
JK		 2163 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2164 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2165 /*
2166 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2167 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2168 */
eabeaacc
JK		 2169 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2170 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2171 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2172 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2173 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2174
33fb20c3
JK		 2175 /*
2176 * Exit controls
2177 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2178 * 17 must be 1.
2179 */
2180 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2181 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2182#ifdef CONFIG_X86_64
2183 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2184#else
2185 nested_vmx_exit_ctls_high = 0;
2186#endif
33fb20c3 2187 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2188
2189 /* entry controls */
2190 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2191 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2192 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2193 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2194 nested_vmx_entry_ctls_high &=
2195 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2196 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2197
2198 /* cpu-based controls */
2199 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2200 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2201 nested_vmx_procbased_ctls_low = 0;
2202 nested_vmx_procbased_ctls_high &=
2203 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2204 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2205 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2206 CPU_BASED_CR3_STORE_EXITING |
2207#ifdef CONFIG_X86_64
2208 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2209#endif
2210 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2211 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2212 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2213 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2214 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2215 /*
2216 * We can allow some features even when not supported by the
2217 * hardware. For example, L1 can specify an MSR bitmap - and we
2218 * can use it to avoid exits to L1 - even when L0 runs L2
2219 * without MSR bitmaps.
2220 */
2221 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2222
2223 /* secondary cpu-based controls */
2224 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2225 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2226 nested_vmx_secondary_ctls_low = 0;
2227 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2228 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2229 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2230
2231 /* miscellaneous data */
2232 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2233 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2234 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2235 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2236}
2237
2238static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2239{
2240 /*
2241 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2242 */
2243 return ((control & high) | low) == control;
2244}
2245
2246static inline u64 vmx_control_msr(u32 low, u32 high)
2247{
2248 return low | ((u64)high << 32);
2249}
2250
2251/*
2252 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2253 * also let it use VMX-specific MSRs.
2254 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2255 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2256 * like all other MSRs).
2257 */
2258static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2259{
2260 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2261 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2262 /*
2263 * According to the spec, processors which do not support VMX
2264 * should throw a #GP(0) when VMX capability MSRs are read.
2265 */
2266 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2267 return 1;
2268 }
2269
2270 switch (msr_index) {
2271 case MSR_IA32_FEATURE_CONTROL:
2272 *pdata = 0;
2273 break;
2274 case MSR_IA32_VMX_BASIC:
2275 /*
2276 * This MSR reports some information about VMX support. We
2277 * should return information about the VMX we emulate for the
2278 * guest, and the VMCS structure we give it - not about the
2279 * VMX support of the underlying hardware.
2280 */
2281 *pdata = VMCS12_REVISION |
2282 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2283 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2284 break;
2285 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2286 case MSR_IA32_VMX_PINBASED_CTLS:
2287 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2288 nested_vmx_pinbased_ctls_high);
2289 break;
2290 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2291 case MSR_IA32_VMX_PROCBASED_CTLS:
2292 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2293 nested_vmx_procbased_ctls_high);
2294 break;
2295 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2296 case MSR_IA32_VMX_EXIT_CTLS:
2297 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2298 nested_vmx_exit_ctls_high);
2299 break;
2300 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2301 case MSR_IA32_VMX_ENTRY_CTLS:
2302 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2303 nested_vmx_entry_ctls_high);
2304 break;
2305 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2306 *pdata = vmx_control_msr(nested_vmx_misc_low,
2307 nested_vmx_misc_high);
b87a51ae
NHE		 2308 break;
2309 /*
2310 * These MSRs specify bits which the guest must keep fixed (on or off)
2311 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2312 * We picked the standard core2 setting.
2313 */
2314#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2315#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2316 case MSR_IA32_VMX_CR0_FIXED0:
2317 *pdata = VMXON_CR0_ALWAYSON;
2318 break;
2319 case MSR_IA32_VMX_CR0_FIXED1:
2320 *pdata = -1ULL;
2321 break;
2322 case MSR_IA32_VMX_CR4_FIXED0:
2323 *pdata = VMXON_CR4_ALWAYSON;
2324 break;
2325 case MSR_IA32_VMX_CR4_FIXED1:
2326 *pdata = -1ULL;
2327 break;
2328 case MSR_IA32_VMX_VMCS_ENUM:
2329 *pdata = 0x1f;
2330 break;
2331 case MSR_IA32_VMX_PROCBASED_CTLS2:
2332 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2333 nested_vmx_secondary_ctls_high);
2334 break;
2335 case MSR_IA32_VMX_EPT_VPID_CAP:
2336 /* Currently, no nested ept or nested vpid */
2337 *pdata = 0;
2338 break;
2339 default:
2340 return 0;
2341 }
2342
2343 return 1;
2344}
2345
2346static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2347{
2348 if (!nested_vmx_allowed(vcpu))
2349 return 0;
2350
2351 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2352 /* TODO: the right thing. */
2353 return 1;
2354 /*
2355 * No need to treat VMX capability MSRs specially: If we don't handle
2356 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2357 */
2358 return 0;
2359}
2360
6aa8b732
AK		 2361/*
2362 * Reads an msr value (of 'msr_index') into 'pdata'.
2363 * Returns 0 on success, non-0 otherwise.
2364 * Assumes vcpu_load() was already called.
2365 */
2366static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2367{
2368 u64 data;
26bb0981 2369 struct shared_msr_entry *msr;
6aa8b732
AK		 2370
2371 if (!pdata) {
2372 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2373 return -EINVAL;
2374 }
2375
2376 switch (msr_index) {
05b3e0c2 2377#ifdef CONFIG_X86_64
6aa8b732
AK		 2378 case MSR_FS_BASE:
2379 data = vmcs_readl(GUEST_FS_BASE);
2380 break;
2381 case MSR_GS_BASE:
2382 data = vmcs_readl(GUEST_GS_BASE);
2383 break;
44ea2b17
AK		 2384 case MSR_KERNEL_GS_BASE:
2385 vmx_load_host_state(to_vmx(vcpu));
2386 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2387 break;
26bb0981 2388#endif
6aa8b732 2389 case MSR_EFER:
3bab1f5d 2390 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2391 case MSR_IA32_TSC:
6aa8b732
AK		 2392 data = guest_read_tsc();
2393 break;
2394 case MSR_IA32_SYSENTER_CS:
2395 data = vmcs_read32(GUEST_SYSENTER_CS);
2396 break;
2397 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2398 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2399 break;
2400 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2401 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2402 break;
4e47c7a6
SY		 2403 case MSR_TSC_AUX:
2404 if (!to_vmx(vcpu)->rdtscp_enabled)
2405 return 1;
2406 /* Otherwise falls through */
6aa8b732 2407 default:
b87a51ae
NHE		 2408 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2409 return 0;
8b9cf98c 2410 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2411 if (msr) {
2412 data = msr->data;
2413 break;
6aa8b732 2414 }
3bab1f5d 2415 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2416 }
2417
2418 *pdata = data;
2419 return 0;
2420}
2421
2422/*
2423 * Writes msr value into into the appropriate "register".
2424 * Returns 0 on success, non-0 otherwise.
2425 * Assumes vcpu_load() was already called.
2426 */
8fe8ab46 2427static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2428{
a2fa3e9f 2429 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2430 struct shared_msr_entry *msr;
2cc51560 2431 int ret = 0;
8fe8ab46
WA		 2432 u32 msr_index = msr_info->index;
2433 u64 data = msr_info->data;
2cc51560 2434
6aa8b732 2435 switch (msr_index) {
3bab1f5d 2436 case MSR_EFER:
8fe8ab46 2437 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2438 break;
16175a79 2439#ifdef CONFIG_X86_64
6aa8b732 2440 case MSR_FS_BASE:
2fb92db1 2441 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2442 vmcs_writel(GUEST_FS_BASE, data);
2443 break;
2444 case MSR_GS_BASE:
2fb92db1 2445 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2446 vmcs_writel(GUEST_GS_BASE, data);
2447 break;
44ea2b17
AK		 2448 case MSR_KERNEL_GS_BASE:
2449 vmx_load_host_state(vmx);
2450 vmx->msr_guest_kernel_gs_base = data;
2451 break;
6aa8b732
AK		 2452#endif
2453 case MSR_IA32_SYSENTER_CS:
2454 vmcs_write32(GUEST_SYSENTER_CS, data);
2455 break;
2456 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2457 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2458 break;
2459 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2460 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2461 break;
af24a4e4 2462 case MSR_IA32_TSC:
8fe8ab46 2463 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2464 break;
468d472f
SY		 2465 case MSR_IA32_CR_PAT:
2466 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2467 vmcs_write64(GUEST_IA32_PAT, data);
2468 vcpu->arch.pat = data;
2469 break;
2470 }
8fe8ab46 2471 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2472 break;
ba904635
WA		 2473 case MSR_IA32_TSC_ADJUST:
2474 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2475 break;
2476 case MSR_TSC_AUX:
2477 if (!vmx->rdtscp_enabled)
2478 return 1;
2479 /* Check reserved bit, higher 32 bits should be zero */
2480 if ((data >> 32) != 0)
2481 return 1;
2482 /* Otherwise falls through */
6aa8b732 2483 default:
b87a51ae
NHE		 2484 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2485 break;
8b9cf98c 2486 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2487 if (msr) {
2488 msr->data = data;
2225fd56
AK		 2489 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2490 preempt_disable();
9ee73970
AK		 2491 kvm_set_shared_msr(msr->index, msr->data,
2492 msr->mask);
2225fd56
AK		 2493 preempt_enable();
2494 }
3bab1f5d 2495 break;
6aa8b732 2496 }
8fe8ab46 2497 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2498 }
2499
2cc51560 2500 return ret;
6aa8b732
AK		 2501}
2502
5fdbf976 2503static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2504{
5fdbf976
MT		 2505 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2506 switch (reg) {
2507 case VCPU_REGS_RSP:
2508 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2509 break;
2510 case VCPU_REGS_RIP:
2511 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2512 break;
6de4f3ad
AK		 2513 case VCPU_EXREG_PDPTR:
2514 if (enable_ept)
2515 ept_save_pdptrs(vcpu);
2516 break;
5fdbf976
MT		 2517 default:
2518 break;
2519 }
6aa8b732
AK		 2520}
2521
6aa8b732
AK		 2522static __init int cpu_has_kvm_support(void)
2523{
6210e37b 2524 return cpu_has_vmx();
6aa8b732
AK		 2525}
2526
2527static __init int vmx_disabled_by_bios(void)
2528{
2529 u64 msr;
2530
2531 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2532 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2533 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2534 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2535 && tboot_enabled())
2536 return 1;
23f3e991 2537 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2538 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2539 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2540 && !tboot_enabled()) {
2541 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2542 "activate TXT before enabling KVM\n");
cafd6659 2543 return 1;
f9335afe 2544 }
23f3e991
JC		 2545 /* launched w/o TXT and VMX disabled */
2546 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2547 && !tboot_enabled())
2548 return 1;
cafd6659
SW		 2549 }
2550
2551 return 0;
6aa8b732
AK		 2552}
2553
7725b894
DX		 2554static void kvm_cpu_vmxon(u64 addr)
2555{
2556 asm volatile (ASM_VMX_VMXON_RAX
2557 : : "a"(&addr), "m"(addr)
2558 : "memory", "cc");
2559}
2560
10474ae8 2561static int hardware_enable(void *garbage)
6aa8b732
AK		 2562{
2563 int cpu = raw_smp_processor_id();
2564 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2565 u64 old, test_bits;
6aa8b732 2566
10474ae8
AG		 2567 if (read_cr4() & X86_CR4_VMXE)
2568 return -EBUSY;
2569
d462b819 2570 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2571
2572 /*
2573 * Now we can enable the vmclear operation in kdump
2574 * since the loaded_vmcss_on_cpu list on this cpu
2575 * has been initialized.
2576 *
2577 * Though the cpu is not in VMX operation now, there
2578 * is no problem to enable the vmclear operation
2579 * for the loaded_vmcss_on_cpu list is empty!
2580 */
2581 crash_enable_local_vmclear(cpu);
2582
6aa8b732 2583 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2584
2585 test_bits = FEATURE_CONTROL_LOCKED;
2586 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2587 if (tboot_enabled())
2588 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2589
2590 if ((old & test_bits) != test_bits) {
6aa8b732 2591 /* enable and lock */
cafd6659
SW		 2592 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2593 }
66aee91a 2594 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2595
4610c9cc
DX		 2596 if (vmm_exclusive) {
2597 kvm_cpu_vmxon(phys_addr);
2598 ept_sync_global();
2599 }
10474ae8 2600
3444d7da
AK		 2601 store_gdt(&__get_cpu_var(host_gdt));
2602
10474ae8 2603 return 0;
6aa8b732
AK		 2604}
2605
d462b819 2606static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2607{
2608 int cpu = raw_smp_processor_id();
d462b819 2609 struct loaded_vmcs *v, *n;
543e4243 2610
d462b819
NHE		 2611 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2612 loaded_vmcss_on_cpu_link)
2613 __loaded_vmcs_clear(v);
543e4243
AK		 2614}
2615
710ff4a8
EH		 2616
2617/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2618 * tricks.
2619 */
2620static void kvm_cpu_vmxoff(void)
6aa8b732 2621{
4ecac3fd 2622 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2623}
2624
710ff4a8
EH		 2625static void hardware_disable(void *garbage)
2626{
4610c9cc 2627 if (vmm_exclusive) {
d462b819 2628 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2629 kvm_cpu_vmxoff();
2630 }
7725b894 2631 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2632}
2633
1c3d14fe 2634static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2635 u32 msr, u32 *result)
1c3d14fe
YS		 2636{
2637 u32 vmx_msr_low, vmx_msr_high;
2638 u32 ctl = ctl_min | ctl_opt;
2639
2640 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2641
2642 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2643 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2644
2645 /* Ensure minimum (required) set of control bits are supported. */
2646 if (ctl_min & ~ctl)
002c7f7c 2647 return -EIO;
1c3d14fe
YS		 2648
2649 *result = ctl;
2650 return 0;
2651}
2652
110312c8
AK		 2653static __init bool allow_1_setting(u32 msr, u32 ctl)
2654{
2655 u32 vmx_msr_low, vmx_msr_high;
2656
2657 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2658 return vmx_msr_high & ctl;
2659}
2660
002c7f7c 2661static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2662{
2663 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2664 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2665 u32 _pin_based_exec_control = 0;
2666 u32 _cpu_based_exec_control = 0;
f78e0e2e 2667 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2668 u32 _vmexit_control = 0;
2669 u32 _vmentry_control = 0;
2670
10166744 2671 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2672#ifdef CONFIG_X86_64
2673 CPU_BASED_CR8_LOAD_EXITING |
2674 CPU_BASED_CR8_STORE_EXITING |
2675#endif
d56f546d
SY		 2676 CPU_BASED_CR3_LOAD_EXITING |
2677 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2678 CPU_BASED_USE_IO_BITMAPS |
2679 CPU_BASED_MOV_DR_EXITING |
a7052897 2680 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2681 CPU_BASED_MWAIT_EXITING |
2682 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2683 CPU_BASED_INVLPG_EXITING |
2684 CPU_BASED_RDPMC_EXITING;
443381a8 2685
f78e0e2e 2686 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2687 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2688 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2689 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2690 &_cpu_based_exec_control) < 0)
002c7f7c 2691 return -EIO;
6e5d865c
YS		 2692#ifdef CONFIG_X86_64
2693 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2694 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2695 ~CPU_BASED_CR8_STORE_EXITING;
2696#endif
f78e0e2e 2697 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2698 min2 = 0;
2699 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2700 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2701 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2702 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2703 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2704 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2705 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2706 SECONDARY_EXEC_RDTSCP |
83d4c286 2707 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2708 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2709 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2710 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2711 if (adjust_vmx_controls(min2, opt2,
2712 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2713 &_cpu_based_2nd_exec_control) < 0)
2714 return -EIO;
2715 }
2716#ifndef CONFIG_X86_64
2717 if (!(_cpu_based_2nd_exec_control &
2718 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2719 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2720#endif
83d4c286
YZ		 2721
2722 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2723 _cpu_based_2nd_exec_control &= ~(
8d14695f 2724 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2725 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2726 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2727
d56f546d 2728 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2729 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2730 enabled */
5fff7d27
GN		 2731 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2732 CPU_BASED_CR3_STORE_EXITING |
2733 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2734 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2735 vmx_capability.ept, vmx_capability.vpid);
2736 }
1c3d14fe
YS		 2737
2738 min = 0;
2739#ifdef CONFIG_X86_64
2740 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2741#endif
a547c6db
YZ		 2742 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2743 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2744 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2745 &_vmexit_control) < 0)
002c7f7c 2746 return -EIO;
1c3d14fe 2747
01e439be
YZ		 2748 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2749 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2750 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2751 &_pin_based_exec_control) < 0)
2752 return -EIO;
2753
2754 if (!(_cpu_based_2nd_exec_control &
2755 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2756 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2757 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2758
468d472f
SY		 2759 min = 0;
2760 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2761 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2762 &_vmentry_control) < 0)
002c7f7c 2763 return -EIO;
6aa8b732 2764
c68876fd 2765 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2766
2767 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2768 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2769 return -EIO;
1c3d14fe
YS		 2770
2771#ifdef CONFIG_X86_64
2772 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2773 if (vmx_msr_high & (1u<<16))
002c7f7c 2774 return -EIO;
1c3d14fe
YS		 2775#endif
2776
2777 /* Require Write-Back (WB) memory type for VMCS accesses. */
2778 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2779 return -EIO;
1c3d14fe 2780
002c7f7c
YS		 2781 vmcs_conf->size = vmx_msr_high & 0x1fff;
2782 vmcs_conf->order = get_order(vmcs_config.size);
2783 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2784
002c7f7c
YS		 2785 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2786 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2787 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2788 vmcs_conf->vmexit_ctrl = _vmexit_control;
2789 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2790
110312c8
AK		 2791 cpu_has_load_ia32_efer =
2792 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2793 VM_ENTRY_LOAD_IA32_EFER)
2794 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2795 VM_EXIT_LOAD_IA32_EFER);
2796
8bf00a52
GN		 2797 cpu_has_load_perf_global_ctrl =
2798 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2799 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2800 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2801 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2802
2803 /*
2804 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2805 * but due to arrata below it can't be used. Workaround is to use
2806 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2807 *
2808 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2809 *
2810 * AAK155 (model 26)
2811 * AAP115 (model 30)
2812 * AAT100 (model 37)
2813 * BC86,AAY89,BD102 (model 44)
2814 * BA97 (model 46)
2815 *
2816 */
2817 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2818 switch (boot_cpu_data.x86_model) {
2819 case 26:
2820 case 30:
2821 case 37:
2822 case 44:
2823 case 46:
2824 cpu_has_load_perf_global_ctrl = false;
2825 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2826 "does not work properly. Using workaround\n");
2827 break;
2828 default:
2829 break;
2830 }
2831 }
2832
1c3d14fe 2833 return 0;
c68876fd 2834}
6aa8b732
AK		 2835
2836static struct vmcs *alloc_vmcs_cpu(int cpu)
2837{
2838 int node = cpu_to_node(cpu);
2839 struct page *pages;
2840 struct vmcs *vmcs;
2841
6484eb3e 2842 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2843 if (!pages)
2844 return NULL;
2845 vmcs = page_address(pages);
1c3d14fe
YS		 2846 memset(vmcs, 0, vmcs_config.size);
2847 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2848 return vmcs;
2849}
2850
2851static struct vmcs *alloc_vmcs(void)
2852{
d3b2c338 2853 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2854}
2855
2856static void free_vmcs(struct vmcs *vmcs)
2857{
1c3d14fe 2858 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2859}
2860
d462b819
NHE		 2861/*
2862 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2863 */
2864static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2865{
2866 if (!loaded_vmcs->vmcs)
2867 return;
2868 loaded_vmcs_clear(loaded_vmcs);
2869 free_vmcs(loaded_vmcs->vmcs);
2870 loaded_vmcs->vmcs = NULL;
2871}
2872
39959588 2873static void free_kvm_area(void)
6aa8b732
AK		 2874{
2875 int cpu;
2876
3230bb47 2877 for_each_possible_cpu(cpu) {
6aa8b732 2878 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2879 per_cpu(vmxarea, cpu) = NULL;
2880 }
6aa8b732
AK		 2881}
2882
6aa8b732
AK		 2883static __init int alloc_kvm_area(void)
2884{
2885 int cpu;
2886
3230bb47 2887 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2888 struct vmcs *vmcs;
2889
2890 vmcs = alloc_vmcs_cpu(cpu);
2891 if (!vmcs) {
2892 free_kvm_area();
2893 return -ENOMEM;
2894 }
2895
2896 per_cpu(vmxarea, cpu) = vmcs;
2897 }
2898 return 0;
2899}
2900
2901static __init int hardware_setup(void)
2902{
002c7f7c
YS		 2903 if (setup_vmcs_config(&vmcs_config) < 0)
2904 return -EIO;
50a37eb4
JR		 2905
2906 if (boot_cpu_has(X86_FEATURE_NX))
2907 kvm_enable_efer_bits(EFER_NX);
2908
93ba03c2
SY		 2909 if (!cpu_has_vmx_vpid())
2910 enable_vpid = 0;
abc4fc58
AG		 2911 if (!cpu_has_vmx_shadow_vmcs())
2912 enable_shadow_vmcs = 0;
93ba03c2 2913
4bc9b982
SY		 2914 if (!cpu_has_vmx_ept() ||
2915 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2916 enable_ept = 0;
3a624e29 2917 enable_unrestricted_guest = 0;
83c3a331 2918 enable_ept_ad_bits = 0;
3a624e29
NK		 2919 }
2920
83c3a331
XH		 2921 if (!cpu_has_vmx_ept_ad_bits())
2922 enable_ept_ad_bits = 0;
2923
3a624e29
NK		 2924 if (!cpu_has_vmx_unrestricted_guest())
2925 enable_unrestricted_guest = 0;
93ba03c2
SY		 2926
2927 if (!cpu_has_vmx_flexpriority())
2928 flexpriority_enabled = 0;
2929
95ba8273
GN		 2930 if (!cpu_has_vmx_tpr_shadow())
2931 kvm_x86_ops->update_cr8_intercept = NULL;
2932
54dee993
MT		 2933 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2934 kvm_disable_largepages();
2935
4b8d54f9
ZE		 2936 if (!cpu_has_vmx_ple())
2937 ple_gap = 0;
2938
01e439be
YZ		 2939 if (!cpu_has_vmx_apicv())
2940 enable_apicv = 0;
c7c9c56c 2941
01e439be 2942 if (enable_apicv)
c7c9c56c 2943 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2944 else {
c7c9c56c 2945 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2946 kvm_x86_ops->deliver_posted_interrupt = NULL;
2947 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2948 }
83d4c286 2949
b87a51ae
NHE		 2950 if (nested)
2951 nested_vmx_setup_ctls_msrs();
2952
6aa8b732
AK		 2953 return alloc_kvm_area();
2954}
2955
2956static __exit void hardware_unsetup(void)
2957{
2958 free_kvm_area();
2959}
2960
14168786
GN		 2961static bool emulation_required(struct kvm_vcpu *vcpu)
2962{
2963 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2964}
2965
91b0aa2c 2966static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2967 struct kvm_segment *save)
6aa8b732 2968{
d99e4152
GN		 2969 if (!emulate_invalid_guest_state) {
2970 /*
2971 * CS and SS RPL should be equal during guest entry according
2972 * to VMX spec, but in reality it is not always so. Since vcpu
2973 * is in the middle of the transition from real mode to
2974 * protected mode it is safe to assume that RPL 0 is a good
2975 * default value.
2976 */
2977 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2978 save->selector &= ~SELECTOR_RPL_MASK;
2979 save->dpl = save->selector & SELECTOR_RPL_MASK;
2980 save->s = 1;
6aa8b732 2981 }
d99e4152 2982 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2983}
2984
2985static void enter_pmode(struct kvm_vcpu *vcpu)
2986{
2987 unsigned long flags;
a89a8fb9 2988 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2989
d99e4152
GN		 2990 /*
2991 * Update real mode segment cache. It may be not up-to-date if sement
2992 * register was written while vcpu was in a guest mode.
2993 */
2994 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2995 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2996 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2997 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2998 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2999 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3000
7ffd92c5 3001 vmx->rmode.vm86_active = 0;
6aa8b732 3002
2fb92db1
AK		 3003 vmx_segment_cache_clear(vmx);
3004
f5f7b2fe 3005 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3006
3007 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3008 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3009 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3010 vmcs_writel(GUEST_RFLAGS, flags);
3011
66aee91a
RR		 3012 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3013 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3014
3015 update_exception_bitmap(vcpu);
3016
91b0aa2c
GN		 3017 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3018 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3019 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3020 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3021 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3022 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3023
3024 /* CPL is always 0 when CPU enters protected mode */
3025 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3026 vmx->cpl = 0;
6aa8b732
AK		 3027}
3028
f5f7b2fe 3029static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3030{
772e0318 3031 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3032 struct kvm_segment var = *save;
3033
3034 var.dpl = 0x3;
3035 if (seg == VCPU_SREG_CS)
3036 var.type = 0x3;
3037
3038 if (!emulate_invalid_guest_state) {
3039 var.selector = var.base >> 4;
3040 var.base = var.base & 0xffff0;
3041 var.limit = 0xffff;
3042 var.g = 0;
3043 var.db = 0;
3044 var.present = 1;
3045 var.s = 1;
3046 var.l = 0;
3047 var.unusable = 0;
3048 var.type = 0x3;
3049 var.avl = 0;
3050 if (save->base & 0xf)
3051 printk_once(KERN_WARNING "kvm: segment base is not "
3052 "paragraph aligned when entering "
3053 "protected mode (seg=%d)", seg);
3054 }
6aa8b732 3055
d99e4152
GN		 3056 vmcs_write16(sf->selector, var.selector);
3057 vmcs_write32(sf->base, var.base);
3058 vmcs_write32(sf->limit, var.limit);
3059 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3060}
3061
3062static void enter_rmode(struct kvm_vcpu *vcpu)
3063{
3064 unsigned long flags;
a89a8fb9 3065 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3066
f5f7b2fe
AK		 3067 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3068 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3069 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3070 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3071 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3072 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3073 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3074
7ffd92c5 3075 vmx->rmode.vm86_active = 1;
6aa8b732 3076
776e58ea
GN		 3077 /*
3078 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3079 * vcpu. Warn the user that an update is overdue.
776e58ea 3080 */
4918c6ca 3081 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3082 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3083 "called before entering vcpu\n");
776e58ea 3084
2fb92db1
AK		 3085 vmx_segment_cache_clear(vmx);
3086
4918c6ca 3087 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3088 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3089 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3090
3091 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3092 vmx->rmode.save_rflags = flags;
6aa8b732 3093
053de044 3094 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3095
3096 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3097 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3098 update_exception_bitmap(vcpu);
3099
d99e4152
GN		 3100 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3101 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3102 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3103 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3104 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3105 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3106
8668a3c4 3107 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3108}
3109
401d10de
AS		 3110static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3111{
3112 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3113 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3114
3115 if (!msr)
3116 return;
401d10de 3117
44ea2b17
AK		 3118 /*
3119 * Force kernel_gs_base reloading before EFER changes, as control
3120 * of this msr depends on is_long_mode().
3121 */
3122 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3123 vcpu->arch.efer = efer;
401d10de
AS		 3124 if (efer & EFER_LMA) {
3125 vmcs_write32(VM_ENTRY_CONTROLS,
3126 vmcs_read32(VM_ENTRY_CONTROLS) |
3127 VM_ENTRY_IA32E_MODE);
3128 msr->data = efer;
3129 } else {
3130 vmcs_write32(VM_ENTRY_CONTROLS,
3131 vmcs_read32(VM_ENTRY_CONTROLS) &
3132 ~VM_ENTRY_IA32E_MODE);
3133
3134 msr->data = efer & ~EFER_LME;
3135 }
3136 setup_msrs(vmx);
3137}
3138
05b3e0c2 3139#ifdef CONFIG_X86_64
6aa8b732
AK		 3140
3141static void enter_lmode(struct kvm_vcpu *vcpu)
3142{
3143 u32 guest_tr_ar;
3144
2fb92db1
AK		 3145 vmx_segment_cache_clear(to_vmx(vcpu));
3146
6aa8b732
AK		 3147 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3148 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3149 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3150 __func__);
6aa8b732
AK		 3151 vmcs_write32(GUEST_TR_AR_BYTES,
3152 (guest_tr_ar & ~AR_TYPE_MASK)
3153 | AR_TYPE_BUSY_64_TSS);
3154 }
da38f438 3155 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3156}
3157
3158static void exit_lmode(struct kvm_vcpu *vcpu)
3159{
6aa8b732
AK		 3160 vmcs_write32(VM_ENTRY_CONTROLS,
3161 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3162 & ~VM_ENTRY_IA32E_MODE);
da38f438 3163 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3164}
3165
3166#endif
3167
2384d2b3
SY		 3168static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3169{
b9d762fa 3170 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3171 if (enable_ept) {
3172 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3173 return;
4e1096d2 3174 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3175 }
2384d2b3
SY		 3176}
3177
e8467fda
AK		 3178static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3179{
3180 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3181
3182 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3183 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3184}
3185
aff48baa
AK		 3186static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3187{
3188 if (enable_ept && is_paging(vcpu))
3189 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3190 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3191}
3192
25c4c276 3193static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3194{
fc78f519
AK		 3195 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3196
3197 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3198 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3199}
3200
1439442c
SY		 3201static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3202{
6de4f3ad
AK		 3203 if (!test_bit(VCPU_EXREG_PDPTR,
3204 (unsigned long *)&vcpu->arch.regs_dirty))
3205 return;
3206
1439442c 3207 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3208 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3209 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3210 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3211 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3212 }
3213}
3214
8f5d549f
AK		 3215static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3216{
3217 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3218 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3219 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3220 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3221 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3222 }
6de4f3ad
AK		 3223
3224 __set_bit(VCPU_EXREG_PDPTR,
3225 (unsigned long *)&vcpu->arch.regs_avail);
3226 __set_bit(VCPU_EXREG_PDPTR,
3227 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3228}
3229
5e1746d6 3230static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3231
3232static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3233 unsigned long cr0,
3234 struct kvm_vcpu *vcpu)
3235{
5233dd51
MT		 3236 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3237 vmx_decache_cr3(vcpu);
1439442c
SY		 3238 if (!(cr0 & X86_CR0_PG)) {
3239 /* From paging/starting to nonpaging */
3240 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3241 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3242 (CPU_BASED_CR3_LOAD_EXITING |
3243 CPU_BASED_CR3_STORE_EXITING));
3244 vcpu->arch.cr0 = cr0;
fc78f519 3245 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3246 } else if (!is_paging(vcpu)) {
3247 /* From nonpaging to paging */
3248 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3249 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3250 ~(CPU_BASED_CR3_LOAD_EXITING |
3251 CPU_BASED_CR3_STORE_EXITING));
3252 vcpu->arch.cr0 = cr0;
fc78f519 3253 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3254 }
95eb84a7
SY		 3255
3256 if (!(cr0 & X86_CR0_WP))
3257 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3258}
3259
6aa8b732
AK		 3260static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3261{
7ffd92c5 3262 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3263 unsigned long hw_cr0;
3264
5037878e 3265 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3266 if (enable_unrestricted_guest)
5037878e 3267 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3268 else {
5037878e 3269 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3270
218e763f
GN		 3271 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3272 enter_pmode(vcpu);
6aa8b732 3273
218e763f
GN		 3274 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3275 enter_rmode(vcpu);
3276 }
6aa8b732 3277
05b3e0c2 3278#ifdef CONFIG_X86_64
f6801dff 3279 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3280 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3281 enter_lmode(vcpu);
707d92fa 3282 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3283 exit_lmode(vcpu);
3284 }
3285#endif
3286
089d034e 3287 if (enable_ept)
1439442c
SY		 3288 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3289
02daab21 3290 if (!vcpu->fpu_active)
81231c69 3291 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3292
6aa8b732 3293 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3294 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3295 vcpu->arch.cr0 = cr0;
14168786
GN		 3296
3297 /* depends on vcpu->arch.cr0 to be set to a new value */
3298 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3299}
3300
1439442c
SY		 3301static u64 construct_eptp(unsigned long root_hpa)
3302{
3303 u64 eptp;
3304
3305 /* TODO write the value reading from MSR */
3306 eptp = VMX_EPT_DEFAULT_MT |
3307 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3308 if (enable_ept_ad_bits)
3309 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3310 eptp |= (root_hpa & PAGE_MASK);
3311
3312 return eptp;
3313}
3314
6aa8b732
AK		 3315static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3316{
1439442c
SY		 3317 unsigned long guest_cr3;
3318 u64 eptp;
3319
3320 guest_cr3 = cr3;
089d034e 3321 if (enable_ept) {
1439442c
SY		 3322 eptp = construct_eptp(cr3);
3323 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3324 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3325 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3326 ept_load_pdptrs(vcpu);
1439442c
SY		 3327 }
3328
2384d2b3 3329 vmx_flush_tlb(vcpu);
1439442c 3330 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3331}
3332
5e1746d6 3333static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3334{
7ffd92c5 3335 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3336 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3337
5e1746d6
NHE		 3338 if (cr4 & X86_CR4_VMXE) {
3339 /*
3340 * To use VMXON (and later other VMX instructions), a guest
3341 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3342 * So basically the check on whether to allow nested VMX
3343 * is here.
3344 */
3345 if (!nested_vmx_allowed(vcpu))
3346 return 1;
1a0d74e6
JK		 3347 }
3348 if (to_vmx(vcpu)->nested.vmxon &&
3349 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3350 return 1;
3351
ad312c7c 3352 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3353 if (enable_ept) {
3354 if (!is_paging(vcpu)) {
3355 hw_cr4 &= ~X86_CR4_PAE;
3356 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3357 /*
3358 * SMEP is disabled if CPU is in non-paging mode in
3359 * hardware. However KVM always uses paging mode to
3360 * emulate guest non-paging mode with TDP.
3361 * To emulate this behavior, SMEP needs to be manually
3362 * disabled when guest switches to non-paging mode.
3363 */
3364 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3365 } else if (!(cr4 & X86_CR4_PAE)) {
3366 hw_cr4 &= ~X86_CR4_PAE;
3367 }
3368 }
1439442c
SY		 3369
3370 vmcs_writel(CR4_READ_SHADOW, cr4);
3371 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3372 return 0;
6aa8b732
AK		 3373}
3374
6aa8b732
AK		 3375static void vmx_get_segment(struct kvm_vcpu *vcpu,
3376 struct kvm_segment *var, int seg)
3377{
a9179499 3378 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3379 u32 ar;
3380
c6ad1153 3381 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3382 *var = vmx->rmode.segs[seg];
a9179499 3383 if (seg == VCPU_SREG_TR
2fb92db1 3384 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3385 return;
1390a28b
AK		 3386 var->base = vmx_read_guest_seg_base(vmx, seg);
3387 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3388 return;
a9179499 3389 }
2fb92db1
AK		 3390 var->base = vmx_read_guest_seg_base(vmx, seg);
3391 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3392 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3393 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3394 var->type = ar & 15;
3395 var->s = (ar >> 4) & 1;
3396 var->dpl = (ar >> 5) & 3;
3397 var->present = (ar >> 7) & 1;
3398 var->avl = (ar >> 12) & 1;
3399 var->l = (ar >> 13) & 1;
3400 var->db = (ar >> 14) & 1;
3401 var->g = (ar >> 15) & 1;
3402 var->unusable = (ar >> 16) & 1;
3403}
3404
a9179499
AK		 3405static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3406{
a9179499
AK		 3407 struct kvm_segment s;
3408
3409 if (to_vmx(vcpu)->rmode.vm86_active) {
3410 vmx_get_segment(vcpu, &s, seg);
3411 return s.base;
3412 }
2fb92db1 3413 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3414}
3415
b09408d0 3416static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3417{
b09408d0
MT		 3418 struct vcpu_vmx *vmx = to_vmx(vcpu);
3419
3eeb3288 3420 if (!is_protmode(vcpu))
2e4d2653
IE		 3421 return 0;
3422
f4c63e5d
AK		 3423 if (!is_long_mode(vcpu)
3424 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3425 return 3;
3426
69c73028
AK		 3427 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3428 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3429 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3430 }
d881e6f6
AK		 3431
3432 return vmx->cpl;
69c73028
AK		 3433}
3434
3435
653e3108 3436static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3437{
6aa8b732
AK		 3438 u32 ar;
3439
f0495f9b 3440 if (var->unusable || !var->present)
6aa8b732
AK		 3441 ar = 1 << 16;
3442 else {
3443 ar = var->type & 15;
3444 ar |= (var->s & 1) << 4;
3445 ar |= (var->dpl & 3) << 5;
3446 ar |= (var->present & 1) << 7;
3447 ar |= (var->avl & 1) << 12;
3448 ar |= (var->l & 1) << 13;
3449 ar |= (var->db & 1) << 14;
3450 ar |= (var->g & 1) << 15;
3451 }
653e3108
AK		 3452
3453 return ar;
3454}
3455
3456static void vmx_set_segment(struct kvm_vcpu *vcpu,
3457 struct kvm_segment *var, int seg)
3458{
7ffd92c5 3459 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3460 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3461
2fb92db1 3462 vmx_segment_cache_clear(vmx);
2f143240
GN		 3463 if (seg == VCPU_SREG_CS)
3464 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3465
1ecd50a9
GN		 3466 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3467 vmx->rmode.segs[seg] = *var;
3468 if (seg == VCPU_SREG_TR)
3469 vmcs_write16(sf->selector, var->selector);
3470 else if (var->s)
3471 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3472 goto out;
653e3108 3473 }
1ecd50a9 3474
653e3108
AK		 3475 vmcs_writel(sf->base, var->base);
3476 vmcs_write32(sf->limit, var->limit);
3477 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3478
3479 /*
3480 * Fix the "Accessed" bit in AR field of segment registers for older
3481 * qemu binaries.
3482 * IA32 arch specifies that at the time of processor reset the
3483 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3484 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3485 * state vmexit when "unrestricted guest" mode is turned on.
3486 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3487 * tree. Newer qemu binaries with that qemu fix would not need this
3488 * kvm hack.
3489 */
3490 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3491 var->type |= 0x1; /* Accessed */
3a624e29 3492
f924d66d 3493 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3494
3495out:
14168786 3496 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3497}
3498
6aa8b732
AK		 3499static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3500{
2fb92db1 3501 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3502
3503 *db = (ar >> 14) & 1;
3504 *l = (ar >> 13) & 1;
3505}
3506
89a27f4d 3507static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3508{
89a27f4d
GN		 3509 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3510 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3511}
3512
89a27f4d 3513static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3514{
89a27f4d
GN		 3515 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3516 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3517}
3518
89a27f4d 3519static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3520{
89a27f4d
GN		 3521 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3522 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3523}
3524
89a27f4d 3525static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3526{
89a27f4d
GN		 3527 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3528 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3529}
3530
648dfaa7
MG		 3531static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3532{
3533 struct kvm_segment var;
3534 u32 ar;
3535
3536 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3537 var.dpl = 0x3;
0647f4aa
GN		 3538 if (seg == VCPU_SREG_CS)
3539 var.type = 0x3;
648dfaa7
MG		 3540 ar = vmx_segment_access_rights(&var);
3541
3542 if (var.base != (var.selector << 4))
3543 return false;
89efbed0 3544 if (var.limit != 0xffff)
648dfaa7 3545 return false;
07f42f5f 3546 if (ar != 0xf3)
648dfaa7
MG		 3547 return false;
3548
3549 return true;
3550}
3551
3552static bool code_segment_valid(struct kvm_vcpu *vcpu)
3553{
3554 struct kvm_segment cs;
3555 unsigned int cs_rpl;
3556
3557 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3558 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3559
1872a3f4
AK		 3560 if (cs.unusable)
3561 return false;
648dfaa7
MG		 3562 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3563 return false;
3564 if (!cs.s)
3565 return false;
1872a3f4 3566 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3567 if (cs.dpl > cs_rpl)
3568 return false;
1872a3f4 3569 } else {
648dfaa7
MG		 3570 if (cs.dpl != cs_rpl)
3571 return false;
3572 }
3573 if (!cs.present)
3574 return false;
3575
3576 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3577 return true;
3578}
3579
3580static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3581{
3582 struct kvm_segment ss;
3583 unsigned int ss_rpl;
3584
3585 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3586 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3587
1872a3f4
AK		 3588 if (ss.unusable)
3589 return true;
3590 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3591 return false;
3592 if (!ss.s)
3593 return false;
3594 if (ss.dpl != ss_rpl) /* DPL != RPL */
3595 return false;
3596 if (!ss.present)
3597 return false;
3598
3599 return true;
3600}
3601
3602static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3603{
3604 struct kvm_segment var;
3605 unsigned int rpl;
3606
3607 vmx_get_segment(vcpu, &var, seg);
3608 rpl = var.selector & SELECTOR_RPL_MASK;
3609
1872a3f4
AK		 3610 if (var.unusable)
3611 return true;
648dfaa7
MG		 3612 if (!var.s)
3613 return false;
3614 if (!var.present)
3615 return false;
3616 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3617 if (var.dpl < rpl) /* DPL < RPL */
3618 return false;
3619 }
3620
3621 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3622 * rights flags
3623 */
3624 return true;
3625}
3626
3627static bool tr_valid(struct kvm_vcpu *vcpu)
3628{
3629 struct kvm_segment tr;
3630
3631 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3632
1872a3f4
AK		 3633 if (tr.unusable)
3634 return false;
648dfaa7
MG		 3635 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3636 return false;
1872a3f4 3637 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3638 return false;
3639 if (!tr.present)
3640 return false;
3641
3642 return true;
3643}
3644
3645static bool ldtr_valid(struct kvm_vcpu *vcpu)
3646{
3647 struct kvm_segment ldtr;
3648
3649 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3650
1872a3f4
AK		 3651 if (ldtr.unusable)
3652 return true;
648dfaa7
MG		 3653 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3654 return false;
3655 if (ldtr.type != 2)
3656 return false;
3657 if (!ldtr.present)
3658 return false;
3659
3660 return true;
3661}
3662
3663static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3664{
3665 struct kvm_segment cs, ss;
3666
3667 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3668 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3669
3670 return ((cs.selector & SELECTOR_RPL_MASK) ==
3671 (ss.selector & SELECTOR_RPL_MASK));
3672}
3673
3674/*
3675 * Check if guest state is valid. Returns true if valid, false if
3676 * not.
3677 * We assume that registers are always usable
3678 */
3679static bool guest_state_valid(struct kvm_vcpu *vcpu)
3680{
c5e97c80
GN		 3681 if (enable_unrestricted_guest)
3682 return true;
3683
648dfaa7 3684 /* real mode guest state checks */
f13882d8 3685 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3686 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3687 return false;
3688 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3689 return false;
3690 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3691 return false;
3692 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3693 return false;
3694 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3695 return false;
3696 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3697 return false;
3698 } else {
3699 /* protected mode guest state checks */
3700 if (!cs_ss_rpl_check(vcpu))
3701 return false;
3702 if (!code_segment_valid(vcpu))
3703 return false;
3704 if (!stack_segment_valid(vcpu))
3705 return false;
3706 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3707 return false;
3708 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3709 return false;
3710 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3711 return false;
3712 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3713 return false;
3714 if (!tr_valid(vcpu))
3715 return false;
3716 if (!ldtr_valid(vcpu))
3717 return false;
3718 }
3719 /* TODO:
3720 * - Add checks on RIP
3721 * - Add checks on RFLAGS
3722 */
3723
3724 return true;
3725}
3726
d77c26fc 3727static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3728{
40dcaa9f 3729 gfn_t fn;
195aefde 3730 u16 data = 0;
40dcaa9f 3731 int r, idx, ret = 0;
6aa8b732 3732
40dcaa9f 3733 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3734 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3735 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3736 if (r < 0)
10589a46 3737 goto out;
195aefde 3738 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3739 r = kvm_write_guest_page(kvm, fn++, &data,
3740 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3741 if (r < 0)
10589a46 3742 goto out;
195aefde
IE		 3743 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3744 if (r < 0)
10589a46 3745 goto out;
195aefde
IE		 3746 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3747 if (r < 0)
10589a46 3748 goto out;
195aefde 3749 data = ~0;
10589a46
MT		 3750 r = kvm_write_guest_page(kvm, fn, &data,
3751 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3752 sizeof(u8));
195aefde 3753 if (r < 0)
10589a46
MT		 3754 goto out;
3755
3756 ret = 1;
3757out:
40dcaa9f 3758 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3759 return ret;
6aa8b732
AK		 3760}
3761
b7ebfb05
SY		 3762static int init_rmode_identity_map(struct kvm *kvm)
3763{
40dcaa9f 3764 int i, idx, r, ret;
b7ebfb05
SY		 3765 pfn_t identity_map_pfn;
3766 u32 tmp;
3767
089d034e 3768 if (!enable_ept)
b7ebfb05
SY		 3769 return 1;
3770 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3771 printk(KERN_ERR "EPT: identity-mapping pagetable "
3772 "haven't been allocated!\n");
3773 return 0;
3774 }
3775 if (likely(kvm->arch.ept_identity_pagetable_done))
3776 return 1;
3777 ret = 0;
b927a3ce 3778 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3779 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3780 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3781 if (r < 0)
3782 goto out;
3783 /* Set up identity-mapping pagetable for EPT in real mode */
3784 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3785 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3786 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3787 r = kvm_write_guest_page(kvm, identity_map_pfn,
3788 &tmp, i * sizeof(tmp), sizeof(tmp));
3789 if (r < 0)
3790 goto out;
3791 }
3792 kvm->arch.ept_identity_pagetable_done = true;
3793 ret = 1;
3794out:
40dcaa9f 3795 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3796 return ret;
3797}
3798
6aa8b732
AK		 3799static void seg_setup(int seg)
3800{
772e0318 3801 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3802 unsigned int ar;
6aa8b732
AK		 3803
3804 vmcs_write16(sf->selector, 0);
3805 vmcs_writel(sf->base, 0);
3806 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3807 ar = 0x93;
3808 if (seg == VCPU_SREG_CS)
3809 ar |= 0x08; /* code segment */
3a624e29
NK		 3810
3811 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3812}
3813
f78e0e2e
SY		 3814static int alloc_apic_access_page(struct kvm *kvm)
3815{
4484141a 3816 struct page *page;
f78e0e2e
SY		 3817 struct kvm_userspace_memory_region kvm_userspace_mem;
3818 int r = 0;
3819
79fac95e 3820 mutex_lock(&kvm->slots_lock);
bfc6d222 3821 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3822 goto out;
3823 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3824 kvm_userspace_mem.flags = 0;
3825 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3826 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3827 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3828 if (r)
3829 goto out;
72dc67a6 3830
4484141a
XG		 3831 page = gfn_to_page(kvm, 0xfee00);
3832 if (is_error_page(page)) {
3833 r = -EFAULT;
3834 goto out;
3835 }
3836
3837 kvm->arch.apic_access_page = page;
f78e0e2e 3838out:
79fac95e 3839 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3840 return r;
3841}
3842
b7ebfb05
SY		 3843static int alloc_identity_pagetable(struct kvm *kvm)
3844{
4484141a 3845 struct page *page;
b7ebfb05
SY		 3846 struct kvm_userspace_memory_region kvm_userspace_mem;
3847 int r = 0;
3848
79fac95e 3849 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3850 if (kvm->arch.ept_identity_pagetable)
3851 goto out;
3852 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3853 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3854 kvm_userspace_mem.guest_phys_addr =
3855 kvm->arch.ept_identity_map_addr;
b7ebfb05 3856 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3857 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3858 if (r)
3859 goto out;
3860
4484141a
XG		 3861 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3862 if (is_error_page(page)) {
3863 r = -EFAULT;
3864 goto out;
3865 }
3866
3867 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3868out:
79fac95e 3869 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3870 return r;
3871}
3872
2384d2b3
SY		 3873static void allocate_vpid(struct vcpu_vmx *vmx)
3874{
3875 int vpid;
3876
3877 vmx->vpid = 0;
919818ab 3878 if (!enable_vpid)
2384d2b3
SY		 3879 return;
3880 spin_lock(&vmx_vpid_lock);
3881 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3882 if (vpid < VMX_NR_VPIDS) {
3883 vmx->vpid = vpid;
3884 __set_bit(vpid, vmx_vpid_bitmap);
3885 }
3886 spin_unlock(&vmx_vpid_lock);
3887}
3888
cdbecfc3
LJ		 3889static void free_vpid(struct vcpu_vmx *vmx)
3890{
3891 if (!enable_vpid)
3892 return;
3893 spin_lock(&vmx_vpid_lock);
3894 if (vmx->vpid != 0)
3895 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3896 spin_unlock(&vmx_vpid_lock);
3897}
3898
8d14695f
YZ		 3899#define MSR_TYPE_R 1
3900#define MSR_TYPE_W 2
3901static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3902 u32 msr, int type)
25c5f225 3903{
3e7c73e9 3904 int f = sizeof(unsigned long);
25c5f225
SY		 3905
3906 if (!cpu_has_vmx_msr_bitmap())
3907 return;
3908
3909 /*
3910 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3911 * have the write-low and read-high bitmap offsets the wrong way round.
3912 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3913 */
25c5f225 3914 if (msr <= 0x1fff) {
8d14695f
YZ		 3915 if (type & MSR_TYPE_R)
3916 /* read-low */
3917 __clear_bit(msr, msr_bitmap + 0x000 / f);
3918
3919 if (type & MSR_TYPE_W)
3920 /* write-low */
3921 __clear_bit(msr, msr_bitmap + 0x800 / f);
3922
25c5f225
SY		 3923 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3924 msr &= 0x1fff;
8d14695f
YZ		 3925 if (type & MSR_TYPE_R)
3926 /* read-high */
3927 __clear_bit(msr, msr_bitmap + 0x400 / f);
3928
3929 if (type & MSR_TYPE_W)
3930 /* write-high */
3931 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3932
3933 }
3934}
3935
3936static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3937 u32 msr, int type)
3938{
3939 int f = sizeof(unsigned long);
3940
3941 if (!cpu_has_vmx_msr_bitmap())
3942 return;
3943
3944 /*
3945 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3946 * have the write-low and read-high bitmap offsets the wrong way round.
3947 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3948 */
3949 if (msr <= 0x1fff) {
3950 if (type & MSR_TYPE_R)
3951 /* read-low */
3952 __set_bit(msr, msr_bitmap + 0x000 / f);
3953
3954 if (type & MSR_TYPE_W)
3955 /* write-low */
3956 __set_bit(msr, msr_bitmap + 0x800 / f);
3957
3958 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3959 msr &= 0x1fff;
3960 if (type & MSR_TYPE_R)
3961 /* read-high */
3962 __set_bit(msr, msr_bitmap + 0x400 / f);
3963
3964 if (type & MSR_TYPE_W)
3965 /* write-high */
3966 __set_bit(msr, msr_bitmap + 0xc00 / f);
3967
25c5f225 3968 }
25c5f225
SY		 3969}
3970
5897297b
AK		 3971static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3972{
3973 if (!longmode_only)
8d14695f
YZ		 3974 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3975 msr, MSR_TYPE_R | MSR_TYPE_W);
3976 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3977 msr, MSR_TYPE_R | MSR_TYPE_W);
3978}
3979
3980static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3981{
3982 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3983 msr, MSR_TYPE_R);
3984 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3985 msr, MSR_TYPE_R);
3986}
3987
3988static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3989{
3990 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3991 msr, MSR_TYPE_R);
3992 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3993 msr, MSR_TYPE_R);
3994}
3995
3996static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3997{
3998 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3999 msr, MSR_TYPE_W);
4000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4001 msr, MSR_TYPE_W);
5897297b
AK		 4002}
4003
01e439be
YZ		 4004static int vmx_vm_has_apicv(struct kvm *kvm)
4005{
4006 return enable_apicv && irqchip_in_kernel(kvm);
4007}
4008
a20ed54d
YZ		 4009/*
4010 * Send interrupt to vcpu via posted interrupt way.
4011 * 1. If target vcpu is running(non-root mode), send posted interrupt
4012 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4013 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4014 * interrupt from PIR in next vmentry.
4015 */
4016static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4017{
4018 struct vcpu_vmx *vmx = to_vmx(vcpu);
4019 int r;
4020
4021 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4022 return;
4023
4024 r = pi_test_and_set_on(&vmx->pi_desc);
4025 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4026#ifdef CONFIG_SMP
a20ed54d
YZ		 4027 if (!r && (vcpu->mode == IN_GUEST_MODE))
4028 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4029 POSTED_INTR_VECTOR);
4030 else
6ffbbbba 4031#endif
a20ed54d
YZ		 4032 kvm_vcpu_kick(vcpu);
4033}
4034
4035static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4036{
4037 struct vcpu_vmx *vmx = to_vmx(vcpu);
4038
4039 if (!pi_test_and_clear_on(&vmx->pi_desc))
4040 return;
4041
4042 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4043}
4044
4045static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4046{
4047 return;
4048}
4049
a3a8ff8e
NHE		 4050/*
4051 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4052 * will not change in the lifetime of the guest.
4053 * Note that host-state that does change is set elsewhere. E.g., host-state
4054 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4055 */
a547c6db 4056static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4057{
4058 u32 low32, high32;
4059 unsigned long tmpl;
4060 struct desc_ptr dt;
4061
b1a74bf8 4062 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4063 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4064 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4065
4066 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4067#ifdef CONFIG_X86_64
4068 /*
4069 * Load null selectors, so we can avoid reloading them in
4070 * __vmx_load_host_state(), in case userspace uses the null selectors
4071 * too (the expected case).
4072 */
4073 vmcs_write16(HOST_DS_SELECTOR, 0);
4074 vmcs_write16(HOST_ES_SELECTOR, 0);
4075#else
a3a8ff8e
NHE		 4076 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4077 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4078#endif
a3a8ff8e
NHE		 4079 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4080 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4081
4082 native_store_idt(&dt);
4083 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4084 vmx->host_idt_base = dt.address;
a3a8ff8e 4085
83287ea4 4086 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4087
4088 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4089 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4090 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4091 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4092
4093 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4094 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4095 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4096 }
4097}
4098
bf8179a0
NHE		 4099static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4100{
4101 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4102 if (enable_ept)
4103 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4104 if (is_guest_mode(&vmx->vcpu))
4105 vmx->vcpu.arch.cr4_guest_owned_bits &=
4106 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4107 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4108}
4109
01e439be
YZ		 4110static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4111{
4112 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4113
4114 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4115 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4116 return pin_based_exec_ctrl;
4117}
4118
bf8179a0
NHE		 4119static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4120{
4121 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4122 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4123 exec_control &= ~CPU_BASED_TPR_SHADOW;
4124#ifdef CONFIG_X86_64
4125 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4126 CPU_BASED_CR8_LOAD_EXITING;
4127#endif
4128 }
4129 if (!enable_ept)
4130 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4131 CPU_BASED_CR3_LOAD_EXITING |
4132 CPU_BASED_INVLPG_EXITING;
4133 return exec_control;
4134}
4135
4136static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4137{
4138 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4139 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4140 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4141 if (vmx->vpid == 0)
4142 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4143 if (!enable_ept) {
4144 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4145 enable_unrestricted_guest = 0;
ad756a16
MJ		 4146 /* Enable INVPCID for non-ept guests may cause performance regression. */
4147 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4148 }
4149 if (!enable_unrestricted_guest)
4150 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4151 if (!ple_gap)
4152 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4153 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4154 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4155 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4156 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4157 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4158 (handle_vmptrld).
4159 We can NOT enable shadow_vmcs here because we don't have yet
4160 a current VMCS12
4161 */
4162 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4163 return exec_control;
4164}
4165
ce88decf
XG		 4166static void ept_set_mmio_spte_mask(void)
4167{
4168 /*
4169 * EPT Misconfigurations can be generated if the value of bits 2:0
4170 * of an EPT paging-structure entry is 110b (write/execute).
4171 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4172 * spte.
4173 */
4174 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
4175}
4176
6aa8b732
AK		 4177/*
4178 * Sets up the vmcs for emulated real mode.
4179 */
8b9cf98c 4180static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4181{
2e4ce7f5 4182#ifdef CONFIG_X86_64
6aa8b732 4183 unsigned long a;
2e4ce7f5 4184#endif
6aa8b732 4185 int i;
6aa8b732 4186
6aa8b732 4187 /* I/O */
3e7c73e9
AK		 4188 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4189 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4190
4607c2d7
AG		 4191 if (enable_shadow_vmcs) {
4192 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4193 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4194 }
25c5f225 4195 if (cpu_has_vmx_msr_bitmap())
5897297b 4196 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4197
6aa8b732
AK		 4198 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4199
6aa8b732 4200 /* Control */
01e439be 4201 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4202
bf8179a0 4203 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4204
83ff3b9d 4205 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4206 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4207 vmx_secondary_exec_control(vmx));
83ff3b9d 4208 }
f78e0e2e 4209
01e439be 4210 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4211 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4212 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4213 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4214 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4215
4216 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4217
4218 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4219 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4220 }
4221
4b8d54f9
ZE		 4222 if (ple_gap) {
4223 vmcs_write32(PLE_GAP, ple_gap);
4224 vmcs_write32(PLE_WINDOW, ple_window);
4225 }
4226
c3707958
XG		 4227 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4228 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4229 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4230
9581d442
AK		 4231 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4232 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4233 vmx_set_constant_host_state(vmx);
05b3e0c2 4234#ifdef CONFIG_X86_64
6aa8b732
AK		 4235 rdmsrl(MSR_FS_BASE, a);
4236 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4237 rdmsrl(MSR_GS_BASE, a);
4238 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4239#else
4240 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4241 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4242#endif
4243
2cc51560
ED		 4244 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4245 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4246 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4247 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4248 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4249
468d472f 4250 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4251 u32 msr_low, msr_high;
4252 u64 host_pat;
468d472f
SY		 4253 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4254 host_pat = msr_low | ((u64) msr_high << 32);
4255 /* Write the default value follow host pat */
4256 vmcs_write64(GUEST_IA32_PAT, host_pat);
4257 /* Keep arch.pat sync with GUEST_IA32_PAT */
4258 vmx->vcpu.arch.pat = host_pat;
4259 }
4260
6aa8b732
AK		 4261 for (i = 0; i < NR_VMX_MSR; ++i) {
4262 u32 index = vmx_msr_index[i];
4263 u32 data_low, data_high;
a2fa3e9f 4264 int j = vmx->nmsrs;
6aa8b732
AK		 4265
4266 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4267 continue;
432bd6cb
AK		 4268 if (wrmsr_safe(index, data_low, data_high) < 0)
4269 continue;
26bb0981
AK		 4270 vmx->guest_msrs[j].index = i;
4271 vmx->guest_msrs[j].data = 0;
d5696725 4272 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4273 ++vmx->nmsrs;
6aa8b732 4274 }
6aa8b732 4275
1c3d14fe 4276 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4277
4278 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4279 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4280
e00c8cf2 4281 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4282 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4283
4284 return 0;
4285}
4286
57f252f2 4287static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4288{
4289 struct vcpu_vmx *vmx = to_vmx(vcpu);
4290 u64 msr;
e00c8cf2 4291
7ffd92c5 4292 vmx->rmode.vm86_active = 0;
e00c8cf2 4293
3b86cd99
JK		 4294 vmx->soft_vnmi_blocked = 0;
4295
ad312c7c 4296 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4297 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4298 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4299 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4300 msr |= MSR_IA32_APICBASE_BSP;
4301 kvm_set_apic_base(&vmx->vcpu, msr);
4302
2fb92db1
AK		 4303 vmx_segment_cache_clear(vmx);
4304
5706be0d 4305 seg_setup(VCPU_SREG_CS);
66450a21 4306 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4307 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4308
4309 seg_setup(VCPU_SREG_DS);
4310 seg_setup(VCPU_SREG_ES);
4311 seg_setup(VCPU_SREG_FS);
4312 seg_setup(VCPU_SREG_GS);
4313 seg_setup(VCPU_SREG_SS);
4314
4315 vmcs_write16(GUEST_TR_SELECTOR, 0);
4316 vmcs_writel(GUEST_TR_BASE, 0);
4317 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4318 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4319
4320 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4321 vmcs_writel(GUEST_LDTR_BASE, 0);
4322 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4323 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4324
4325 vmcs_write32(GUEST_SYSENTER_CS, 0);
4326 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4327 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4328
4329 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4330 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4331
e00c8cf2
AK		 4332 vmcs_writel(GUEST_GDTR_BASE, 0);
4333 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4334
4335 vmcs_writel(GUEST_IDTR_BASE, 0);
4336 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4337
443381a8 4338 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4339 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4340 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4341
e00c8cf2
AK		 4342 /* Special registers */
4343 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4344
4345 setup_msrs(vmx);
4346
6aa8b732
AK		 4347 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4348
f78e0e2e
SY		 4349 if (cpu_has_vmx_tpr_shadow()) {
4350 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4351 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4352 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4353 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4354 vmcs_write32(TPR_THRESHOLD, 0);
4355 }
4356
4357 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4358 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4359 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4360
01e439be
YZ		 4361 if (vmx_vm_has_apicv(vcpu->kvm))
4362 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4363
2384d2b3
SY		 4364 if (vmx->vpid != 0)
4365 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4366
fa40052c 4367 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4368 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4369 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4370 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4371 vmx_fpu_activate(&vmx->vcpu);
4372 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4373
b9d762fa 4374 vpid_sync_context(vmx);
6aa8b732
AK		 4375}
4376
b6f1250e
NHE		 4377/*
4378 * In nested virtualization, check if L1 asked to exit on external interrupts.
4379 * For most existing hypervisors, this will always return true.
4380 */
4381static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4382{
4383 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4384 PIN_BASED_EXT_INTR_MASK;
4385}
4386
3b86cd99
JK		 4387static void enable_irq_window(struct kvm_vcpu *vcpu)
4388{
4389 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4390 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4391 /*
4392 * We get here if vmx_interrupt_allowed() said we can't
4393 * inject to L1 now because L2 must run. Ask L2 to exit
4394 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4395 */
d6185f20 4396 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4397 return;
d6185f20 4398 }
3b86cd99
JK		 4399
4400 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4401 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4402 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4403}
4404
4405static void enable_nmi_window(struct kvm_vcpu *vcpu)
4406{
4407 u32 cpu_based_vm_exec_control;
4408
4409 if (!cpu_has_virtual_nmis()) {
4410 enable_irq_window(vcpu);
4411 return;
4412 }
4413
30bd0c4c
AK		 4414 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4415 enable_irq_window(vcpu);
4416 return;
4417 }
3b86cd99
JK		 4418 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4419 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4420 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4421}
4422
66fd3f7f 4423static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4424{
9c8cba37 4425 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4426 uint32_t intr;
4427 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4428
229456fc 4429 trace_kvm_inj_virq(irq);
2714d1d3 4430
fa89a817 4431 ++vcpu->stat.irq_injections;
7ffd92c5 4432 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4433 int inc_eip = 0;
4434 if (vcpu->arch.interrupt.soft)
4435 inc_eip = vcpu->arch.event_exit_inst_len;
4436 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4437 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4438 return;
4439 }
66fd3f7f
GN		 4440 intr = irq | INTR_INFO_VALID_MASK;
4441 if (vcpu->arch.interrupt.soft) {
4442 intr |= INTR_TYPE_SOFT_INTR;
4443 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4444 vmx->vcpu.arch.event_exit_inst_len);
4445 } else
4446 intr |= INTR_TYPE_EXT_INTR;
4447 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4448}
4449
f08864b4
SY		 4450static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4451{
66a5a347
JK		 4452 struct vcpu_vmx *vmx = to_vmx(vcpu);
4453
0b6ac343
NHE		 4454 if (is_guest_mode(vcpu))
4455 return;
4456
3b86cd99
JK		 4457 if (!cpu_has_virtual_nmis()) {
4458 /*
4459 * Tracking the NMI-blocked state in software is built upon
4460 * finding the next open IRQ window. This, in turn, depends on
4461 * well-behaving guests: They have to keep IRQs disabled at
4462 * least as long as the NMI handler runs. Otherwise we may
4463 * cause NMI nesting, maybe breaking the guest. But as this is
4464 * highly unlikely, we can live with the residual risk.
4465 */
4466 vmx->soft_vnmi_blocked = 1;
4467 vmx->vnmi_blocked_time = 0;
4468 }
4469
487b391d 4470 ++vcpu->stat.nmi_injections;
9d58b931 4471 vmx->nmi_known_unmasked = false;
7ffd92c5 4472 if (vmx->rmode.vm86_active) {
71f9833b 4473 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4474 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4475 return;
4476 }
f08864b4
SY		 4477 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4478 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4479}
4480
c4282df9 4481static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4482{
3b86cd99 4483 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4484 return 0;
33f089ca 4485
c4282df9 4486 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4487 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4488 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4489}
4490
3cfc3092
JK		 4491static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4492{
4493 if (!cpu_has_virtual_nmis())
4494 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4495 if (to_vmx(vcpu)->nmi_known_unmasked)
4496 return false;
c332c83a 4497 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4498}
4499
4500static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4501{
4502 struct vcpu_vmx *vmx = to_vmx(vcpu);
4503
4504 if (!cpu_has_virtual_nmis()) {
4505 if (vmx->soft_vnmi_blocked != masked) {
4506 vmx->soft_vnmi_blocked = masked;
4507 vmx->vnmi_blocked_time = 0;
4508 }
4509 } else {
9d58b931 4510 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4511 if (masked)
4512 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4513 GUEST_INTR_STATE_NMI);
4514 else
4515 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4516 GUEST_INTR_STATE_NMI);
4517 }
4518}
4519
78646121
GN		 4520static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4521{
e8457c67 4522 if (is_guest_mode(vcpu)) {
51cfe38e 4523 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4524
4525 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4526 return 0;
e8457c67
JK		 4527 if (nested_exit_on_intr(vcpu)) {
4528 nested_vmx_vmexit(vcpu);
4529 vmcs12->vm_exit_reason =
4530 EXIT_REASON_EXTERNAL_INTERRUPT;
4531 vmcs12->vm_exit_intr_info = 0;
4532 /*
4533 * fall through to normal code, but now in L1, not L2
4534 */
4535 }
b6f1250e
NHE		 4536 }
4537
c4282df9
GN		 4538 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4539 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4540 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4541}
4542
cbc94022
IE		 4543static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4544{
4545 int ret;
4546 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4547 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4548 .guest_phys_addr = addr,
4549 .memory_size = PAGE_SIZE * 3,
4550 .flags = 0,
4551 };
4552
47ae31e2 4553 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4554 if (ret)
4555 return ret;
bfc6d222 4556 kvm->arch.tss_addr = addr;
93ea5388
GN		 4557 if (!init_rmode_tss(kvm))
4558 return -ENOMEM;
4559
cbc94022
IE		 4560 return 0;
4561}
4562
0ca1b4f4 4563static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4564{
77ab6db0 4565 switch (vec) {
77ab6db0 4566 case BP_VECTOR:
c573cd22
JK		 4567 /*
4568 * Update instruction length as we may reinject the exception
4569 * from user space while in guest debugging mode.
4570 */
4571 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4572 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4573 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4574 return false;
4575 /* fall through */
4576 case DB_VECTOR:
4577 if (vcpu->guest_debug &
4578 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4579 return false;
d0bfb940
JK		 4580 /* fall through */
4581 case DE_VECTOR:
77ab6db0
JK		 4582 case OF_VECTOR:
4583 case BR_VECTOR:
4584 case UD_VECTOR:
4585 case DF_VECTOR:
4586 case SS_VECTOR:
4587 case GP_VECTOR:
4588 case MF_VECTOR:
0ca1b4f4
GN		 4589 return true;
4590 break;
77ab6db0 4591 }
0ca1b4f4
GN		 4592 return false;
4593}
4594
4595static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4596 int vec, u32 err_code)
4597{
4598 /*
4599 * Instruction with address size override prefix opcode 0x67
4600 * Cause the #SS fault with 0 error code in VM86 mode.
4601 */
4602 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4603 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4604 if (vcpu->arch.halt_request) {
4605 vcpu->arch.halt_request = 0;
4606 return kvm_emulate_halt(vcpu);
4607 }
4608 return 1;
4609 }
4610 return 0;
4611 }
4612
4613 /*
4614 * Forward all other exceptions that are valid in real mode.
4615 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4616 * the required debugging infrastructure rework.
4617 */
4618 kvm_queue_exception(vcpu, vec);
4619 return 1;
6aa8b732
AK		 4620}
4621
a0861c02
AK		 4622/*
4623 * Trigger machine check on the host. We assume all the MSRs are already set up
4624 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4625 * We pass a fake environment to the machine check handler because we want
4626 * the guest to be always treated like user space, no matter what context
4627 * it used internally.
4628 */
4629static void kvm_machine_check(void)
4630{
4631#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4632 struct pt_regs regs = {
4633 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4634 .flags = X86_EFLAGS_IF,
4635 };
4636
4637 do_machine_check(&regs, 0);
4638#endif
4639}
4640
851ba692 4641static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4642{
4643 /* already handled by vcpu_run */
4644 return 1;
4645}
4646
851ba692 4647static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4648{
1155f76a 4649 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4650 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4651 u32 intr_info, ex_no, error_code;
42dbaa5a 4652 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4653 u32 vect_info;
4654 enum emulation_result er;
4655
1155f76a 4656 vect_info = vmx->idt_vectoring_info;
88786475 4657 intr_info = vmx->exit_intr_info;
6aa8b732 4658
a0861c02 4659 if (is_machine_check(intr_info))
851ba692 4660 return handle_machine_check(vcpu);
a0861c02 4661
e4a41889 4662 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4663 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4664
4665 if (is_no_device(intr_info)) {
5fd86fcf 4666 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4667 return 1;
4668 }
4669
7aa81cc0 4670 if (is_invalid_opcode(intr_info)) {
51d8b661 4671 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4672 if (er != EMULATE_DONE)
7ee5d940 4673 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4674 return 1;
4675 }
4676
6aa8b732 4677 error_code = 0;
2e11384c 4678 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4679 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4680
4681 /*
4682 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4683 * MMIO, it is better to report an internal error.
4684 * See the comments in vmx_handle_exit.
4685 */
4686 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4687 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4688 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4689 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4690 vcpu->run->internal.ndata = 2;
4691 vcpu->run->internal.data[0] = vect_info;
4692 vcpu->run->internal.data[1] = intr_info;
4693 return 0;
4694 }
4695
6aa8b732 4696 if (is_page_fault(intr_info)) {
1439442c 4697 /* EPT won't cause page fault directly */
cf3ace79 4698 BUG_ON(enable_ept);
6aa8b732 4699 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4700 trace_kvm_page_fault(cr2, error_code);
4701
3298b75c 4702 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4703 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4704 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4705 }
4706
d0bfb940 4707 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4708
4709 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4710 return handle_rmode_exception(vcpu, ex_no, error_code);
4711
42dbaa5a
JK		 4712 switch (ex_no) {
4713 case DB_VECTOR:
4714 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4715 if (!(vcpu->guest_debug &
4716 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4717 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4718 kvm_queue_exception(vcpu, DB_VECTOR);
4719 return 1;
4720 }
4721 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4722 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4723 /* fall through */
4724 case BP_VECTOR:
c573cd22
JK		 4725 /*
4726 * Update instruction length as we may reinject #BP from
4727 * user space while in guest debugging mode. Reading it for
4728 * #DB as well causes no harm, it is not used in that case.
4729 */
4730 vmx->vcpu.arch.event_exit_inst_len =
4731 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4732 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4733 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4734 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4735 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4736 break;
4737 default:
d0bfb940
JK		 4738 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4739 kvm_run->ex.exception = ex_no;
4740 kvm_run->ex.error_code = error_code;
42dbaa5a 4741 break;
6aa8b732 4742 }
6aa8b732
AK		 4743 return 0;
4744}
4745
851ba692 4746static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4747{
1165f5fe 4748 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4749 return 1;
4750}
4751
851ba692 4752static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4753{
851ba692 4754 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4755 return 0;
4756}
6aa8b732 4757
851ba692 4758static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4759{
bfdaab09 4760 unsigned long exit_qualification;
34c33d16 4761 int size, in, string;
039576c0 4762 unsigned port;
6aa8b732 4763
bfdaab09 4764 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4765 string = (exit_qualification & 16) != 0;
cf8f70bf 4766 in = (exit_qualification & 8) != 0;
e70669ab 4767
cf8f70bf 4768 ++vcpu->stat.io_exits;
e70669ab 4769
cf8f70bf 4770 if (string || in)
51d8b661 4771 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4772
cf8f70bf
GN		 4773 port = exit_qualification >> 16;
4774 size = (exit_qualification & 7) + 1;
e93f36bc 4775 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4776
4777 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4778}
4779
102d8325
IM		 4780static void
4781vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4782{
4783 /*
4784 * Patch in the VMCALL instruction:
4785 */
4786 hypercall[0] = 0x0f;
4787 hypercall[1] = 0x01;
4788 hypercall[2] = 0xc1;
102d8325
IM		 4789}
4790
0fa06071 4791/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4792static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4793{
eeadf9e7 4794 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4795 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4796 unsigned long orig_val = val;
4797
eeadf9e7
NHE		 4798 /*
4799 * We get here when L2 changed cr0 in a way that did not change
4800 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4801 * but did change L0 shadowed bits. So we first calculate the
4802 * effective cr0 value that L1 would like to write into the
4803 * hardware. It consists of the L2-owned bits from the new
4804 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4805 */
1a0d74e6
JK		 4806 val = (val & ~vmcs12->cr0_guest_host_mask) |
4807 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4808
4809 /* TODO: will have to take unrestricted guest mode into
4810 * account */
4811 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4812 return 1;
1a0d74e6
JK		 4813
4814 if (kvm_set_cr0(vcpu, val))
4815 return 1;
4816 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4817 return 0;
1a0d74e6
JK		 4818 } else {
4819 if (to_vmx(vcpu)->nested.vmxon &&
4820 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4821 return 1;
eeadf9e7 4822 return kvm_set_cr0(vcpu, val);
1a0d74e6 4823 }
eeadf9e7
NHE		 4824}
4825
4826static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4827{
4828 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4829 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4830 unsigned long orig_val = val;
4831
4832 /* analogously to handle_set_cr0 */
4833 val = (val & ~vmcs12->cr4_guest_host_mask) |
4834 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4835 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4836 return 1;
1a0d74e6 4837 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4838 return 0;
4839 } else
4840 return kvm_set_cr4(vcpu, val);
4841}
4842
4843/* called to set cr0 as approriate for clts instruction exit. */
4844static void handle_clts(struct kvm_vcpu *vcpu)
4845{
4846 if (is_guest_mode(vcpu)) {
4847 /*
4848 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4849 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4850 * just pretend it's off (also in arch.cr0 for fpu_activate).
4851 */
4852 vmcs_writel(CR0_READ_SHADOW,
4853 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4854 vcpu->arch.cr0 &= ~X86_CR0_TS;
4855 } else
4856 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4857}
4858
851ba692 4859static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4860{
229456fc 4861 unsigned long exit_qualification, val;
6aa8b732
AK		 4862 int cr;
4863 int reg;
49a9b07e 4864 int err;
6aa8b732 4865
bfdaab09 4866 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4867 cr = exit_qualification & 15;
4868 reg = (exit_qualification >> 8) & 15;
4869 switch ((exit_qualification >> 4) & 3) {
4870 case 0: /* mov to cr */
229456fc
MT		 4871 val = kvm_register_read(vcpu, reg);
4872 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4873 switch (cr) {
4874 case 0:
eeadf9e7 4875 err = handle_set_cr0(vcpu, val);
db8fcefa 4876 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4877 return 1;
4878 case 3:
2390218b 4879 err = kvm_set_cr3(vcpu, val);
db8fcefa 4880 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4881 return 1;
4882 case 4:
eeadf9e7 4883 err = handle_set_cr4(vcpu, val);
db8fcefa 4884 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4885 return 1;
0a5fff19
GN		 4886 case 8: {
4887 u8 cr8_prev = kvm_get_cr8(vcpu);
4888 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4889 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4890 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4891 if (irqchip_in_kernel(vcpu->kvm))
4892 return 1;
4893 if (cr8_prev <= cr8)
4894 return 1;
851ba692 4895 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4896 return 0;
4897 }
4b8073e4 4898 }
6aa8b732 4899 break;
25c4c276 4900 case 2: /* clts */
eeadf9e7 4901 handle_clts(vcpu);
4d4ec087 4902 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4903 skip_emulated_instruction(vcpu);
6b52d186 4904 vmx_fpu_activate(vcpu);
25c4c276 4905 return 1;
6aa8b732
AK		 4906 case 1: /*mov from cr*/
4907 switch (cr) {
4908 case 3:
9f8fe504
AK		 4909 val = kvm_read_cr3(vcpu);
4910 kvm_register_write(vcpu, reg, val);
4911 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4912 skip_emulated_instruction(vcpu);
4913 return 1;
4914 case 8:
229456fc
MT		 4915 val = kvm_get_cr8(vcpu);
4916 kvm_register_write(vcpu, reg, val);
4917 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4918 skip_emulated_instruction(vcpu);
4919 return 1;
4920 }
4921 break;
4922 case 3: /* lmsw */
a1f83a74 4923 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4924 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4925 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4926
4927 skip_emulated_instruction(vcpu);
4928 return 1;
4929 default:
4930 break;
4931 }
851ba692 4932 vcpu->run->exit_reason = 0;
a737f256 4933 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4934 (int)(exit_qualification >> 4) & 3, cr);
4935 return 0;
4936}
4937
851ba692 4938static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4939{
bfdaab09 4940 unsigned long exit_qualification;
6aa8b732
AK		 4941 int dr, reg;
4942
f2483415 4943 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4944 if (!kvm_require_cpl(vcpu, 0))
4945 return 1;
42dbaa5a
JK		 4946 dr = vmcs_readl(GUEST_DR7);
4947 if (dr & DR7_GD) {
4948 /*
4949 * As the vm-exit takes precedence over the debug trap, we
4950 * need to emulate the latter, either for the host or the
4951 * guest debugging itself.
4952 */
4953 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4954 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4955 vcpu->run->debug.arch.dr7 = dr;
4956 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4957 vmcs_readl(GUEST_CS_BASE) +
4958 vmcs_readl(GUEST_RIP);
851ba692
AK		 4959 vcpu->run->debug.arch.exception = DB_VECTOR;
4960 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4961 return 0;
4962 } else {
4963 vcpu->arch.dr7 &= ~DR7_GD;
4964 vcpu->arch.dr6 |= DR6_BD;
4965 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4966 kvm_queue_exception(vcpu, DB_VECTOR);
4967 return 1;
4968 }
4969 }
4970
bfdaab09 4971 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4972 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4973 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4974 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4975 unsigned long val;
4976 if (!kvm_get_dr(vcpu, dr, &val))
4977 kvm_register_write(vcpu, reg, val);
4978 } else
4979 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4980 skip_emulated_instruction(vcpu);
4981 return 1;
4982}
4983
020df079
GN		 4984static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4985{
4986 vmcs_writel(GUEST_DR7, val);
4987}
4988
851ba692 4989static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4990{
06465c5a
AK		 4991 kvm_emulate_cpuid(vcpu);
4992 return 1;
6aa8b732
AK		 4993}
4994
851ba692 4995static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4996{
ad312c7c 4997 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4998 u64 data;
4999
5000 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5001 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5002 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5003 return 1;
5004 }
5005
229456fc 5006 trace_kvm_msr_read(ecx, data);
2714d1d3 5007
6aa8b732 5008 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5009 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5010 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5011 skip_emulated_instruction(vcpu);
5012 return 1;
5013}
5014
851ba692 5015static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5016{
8fe8ab46 5017 struct msr_data msr;
ad312c7c
ZX		 5018 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5019 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5020 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5021
8fe8ab46
WA		 5022 msr.data = data;
5023 msr.index = ecx;
5024 msr.host_initiated = false;
5025 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5026 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5027 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5028 return 1;
5029 }
5030
59200273 5031 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5032 skip_emulated_instruction(vcpu);
5033 return 1;
5034}
5035
851ba692 5036static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5037{
3842d135 5038 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5039 return 1;
5040}
5041
851ba692 5042static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5043{
85f455f7
ED		 5044 u32 cpu_based_vm_exec_control;
5045
5046 /* clear pending irq */
5047 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5048 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5049 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5050
3842d135
AK		 5051 kvm_make_request(KVM_REQ_EVENT, vcpu);
5052
a26bf12a 5053 ++vcpu->stat.irq_window_exits;
2714d1d3 5054
c1150d8c
DL		 5055 /*
5056 * If the user space waits to inject interrupts, exit as soon as
5057 * possible
5058 */
8061823a 5059 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5060 vcpu->run->request_interrupt_window &&
8061823a 5061 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5062 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5063 return 0;
5064 }
6aa8b732
AK		 5065 return 1;
5066}
5067
851ba692 5068static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5069{
5070 skip_emulated_instruction(vcpu);
d3bef15f 5071 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5072}
5073
851ba692 5074static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5075{
510043da 5076 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5077 kvm_emulate_hypercall(vcpu);
5078 return 1;
c21415e8
IM		 5079}
5080
ec25d5e6
GN		 5081static int handle_invd(struct kvm_vcpu *vcpu)
5082{
51d8b661 5083 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5084}
5085
851ba692 5086static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5087{
f9c617f6 5088 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5089
5090 kvm_mmu_invlpg(vcpu, exit_qualification);
5091 skip_emulated_instruction(vcpu);
5092 return 1;
5093}
5094
fee84b07
AK		 5095static int handle_rdpmc(struct kvm_vcpu *vcpu)
5096{
5097 int err;
5098
5099 err = kvm_rdpmc(vcpu);
5100 kvm_complete_insn_gp(vcpu, err);
5101
5102 return 1;
5103}
5104
851ba692 5105static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5106{
5107 skip_emulated_instruction(vcpu);
f5f48ee1 5108 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5109 return 1;
5110}
5111
2acf923e
DC		 5112static int handle_xsetbv(struct kvm_vcpu *vcpu)
5113{
5114 u64 new_bv = kvm_read_edx_eax(vcpu);
5115 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5116
5117 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5118 skip_emulated_instruction(vcpu);
5119 return 1;
5120}
5121
851ba692 5122static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5123{
58fbbf26
KT		 5124 if (likely(fasteoi)) {
5125 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5126 int access_type, offset;
5127
5128 access_type = exit_qualification & APIC_ACCESS_TYPE;
5129 offset = exit_qualification & APIC_ACCESS_OFFSET;
5130 /*
5131 * Sane guest uses MOV to write EOI, with written value
5132 * not cared. So make a short-circuit here by avoiding
5133 * heavy instruction emulation.
5134 */
5135 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5136 (offset == APIC_EOI)) {
5137 kvm_lapic_set_eoi(vcpu);
5138 skip_emulated_instruction(vcpu);
5139 return 1;
5140 }
5141 }
51d8b661 5142 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5143}
5144
c7c9c56c
YZ		 5145static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5146{
5147 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5148 int vector = exit_qualification & 0xff;
5149
5150 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5151 kvm_apic_set_eoi_accelerated(vcpu, vector);
5152 return 1;
5153}
5154
83d4c286
YZ		 5155static int handle_apic_write(struct kvm_vcpu *vcpu)
5156{
5157 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5158 u32 offset = exit_qualification & 0xfff;
5159
5160 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5161 kvm_apic_write_nodecode(vcpu, offset);
5162 return 1;
5163}
5164
851ba692 5165static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5166{
60637aac 5167 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5168 unsigned long exit_qualification;
e269fb21
JK		 5169 bool has_error_code = false;
5170 u32 error_code = 0;
37817f29 5171 u16 tss_selector;
7f3d35fd 5172 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5173
5174 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5175 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5176 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5177
5178 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5179
5180 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5181 if (reason == TASK_SWITCH_GATE && idt_v) {
5182 switch (type) {
5183 case INTR_TYPE_NMI_INTR:
5184 vcpu->arch.nmi_injected = false;
654f06fc 5185 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5186 break;
5187 case INTR_TYPE_EXT_INTR:
66fd3f7f 5188 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5189 kvm_clear_interrupt_queue(vcpu);
5190 break;
5191 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5192 if (vmx->idt_vectoring_info &
5193 VECTORING_INFO_DELIVER_CODE_MASK) {
5194 has_error_code = true;
5195 error_code =
5196 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5197 }
5198 /* fall through */
64a7ec06
GN		 5199 case INTR_TYPE_SOFT_EXCEPTION:
5200 kvm_clear_exception_queue(vcpu);
5201 break;
5202 default:
5203 break;
5204 }
60637aac 5205 }
37817f29
IE		 5206 tss_selector = exit_qualification;
5207
64a7ec06
GN		 5208 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5209 type != INTR_TYPE_EXT_INTR &&
5210 type != INTR_TYPE_NMI_INTR))
5211 skip_emulated_instruction(vcpu);
5212
7f3d35fd
KW		 5213 if (kvm_task_switch(vcpu, tss_selector,
5214 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5215 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5216 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5217 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5218 vcpu->run->internal.ndata = 0;
42dbaa5a 5219 return 0;
acb54517 5220 }
42dbaa5a
JK		 5221
5222 /* clear all local breakpoint enable flags */
5223 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5224
5225 /*
5226 * TODO: What about debug traps on tss switch?
5227 * Are we supposed to inject them and update dr6?
5228 */
5229
5230 return 1;
37817f29
IE		 5231}
5232
851ba692 5233static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5234{
f9c617f6 5235 unsigned long exit_qualification;
1439442c 5236 gpa_t gpa;
4f5982a5 5237 u32 error_code;
1439442c 5238 int gla_validity;
1439442c 5239
f9c617f6 5240 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5241
1439442c
SY		 5242 gla_validity = (exit_qualification >> 7) & 0x3;
5243 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5244 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5245 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5246 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5247 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5248 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5249 (long unsigned int)exit_qualification);
851ba692
AK		 5250 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5251 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5252 return 0;
1439442c
SY		 5253 }
5254
5255 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5256 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5257
5258 /* It is a write fault? */
5259 error_code = exit_qualification & (1U << 1);
5260 /* ept page table is present? */
5261 error_code |= (exit_qualification >> 3) & 0x1;
5262
5263 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5264}
5265
68f89400
MT		 5266static u64 ept_rsvd_mask(u64 spte, int level)
5267{
5268 int i;
5269 u64 mask = 0;
5270
5271 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5272 mask |= (1ULL << i);
5273
5274 if (level > 2)
5275 /* bits 7:3 reserved */
5276 mask |= 0xf8;
5277 else if (level == 2) {
5278 if (spte & (1ULL << 7))
5279 /* 2MB ref, bits 20:12 reserved */
5280 mask |= 0x1ff000;
5281 else
5282 /* bits 6:3 reserved */
5283 mask |= 0x78;
5284 }
5285
5286 return mask;
5287}
5288
5289static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5290 int level)
5291{
5292 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5293
5294 /* 010b (write-only) */
5295 WARN_ON((spte & 0x7) == 0x2);
5296
5297 /* 110b (write/execute) */
5298 WARN_ON((spte & 0x7) == 0x6);
5299
5300 /* 100b (execute-only) and value not supported by logical processor */
5301 if (!cpu_has_vmx_ept_execute_only())
5302 WARN_ON((spte & 0x7) == 0x4);
5303
5304 /* not 000b */
5305 if ((spte & 0x7)) {
5306 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5307
5308 if (rsvd_bits != 0) {
5309 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5310 __func__, rsvd_bits);
5311 WARN_ON(1);
5312 }
5313
5314 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5315 u64 ept_mem_type = (spte & 0x38) >> 3;
5316
5317 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5318 ept_mem_type == 7) {
5319 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5320 __func__, ept_mem_type);
5321 WARN_ON(1);
5322 }
5323 }
5324 }
5325}
5326
851ba692 5327static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5328{
5329 u64 sptes[4];
ce88decf 5330 int nr_sptes, i, ret;
68f89400
MT		 5331 gpa_t gpa;
5332
5333 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5334
ce88decf
XG		 5335 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5336 if (likely(ret == 1))
5337 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5338 EMULATE_DONE;
5339 if (unlikely(!ret))
5340 return 1;
5341
5342 /* It is the real ept misconfig */
68f89400
MT		 5343 printk(KERN_ERR "EPT: Misconfiguration.\n");
5344 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5345
5346 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5347
5348 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5349 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5350
851ba692
AK		 5351 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5352 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5353
5354 return 0;
5355}
5356
851ba692 5357static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5358{
5359 u32 cpu_based_vm_exec_control;
5360
5361 /* clear pending NMI */
5362 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5363 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5365 ++vcpu->stat.nmi_window_exits;
3842d135 5366 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5367
5368 return 1;
5369}
5370
80ced186 5371static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5372{
8b3079a5
AK		 5373 struct vcpu_vmx *vmx = to_vmx(vcpu);
5374 enum emulation_result err = EMULATE_DONE;
80ced186 5375 int ret = 1;
49e9d557
AK		 5376 u32 cpu_exec_ctrl;
5377 bool intr_window_requested;
b8405c18 5378 unsigned count = 130;
49e9d557
AK		 5379
5380 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5381 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5382
b8405c18 5383 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5384 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5385 return handle_interrupt_window(&vmx->vcpu);
5386
de87dcdd
AK		 5387 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5388 return 1;
5389
991eebf9 5390 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5391
80ced186
MG		 5392 if (err == EMULATE_DO_MMIO) {
5393 ret = 0;
5394 goto out;
5395 }
1d5a4d9b 5396
de5f70e0
AK		 5397 if (err != EMULATE_DONE) {
5398 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5399 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5400 vcpu->run->internal.ndata = 0;
6d77dbfc 5401 return 0;
de5f70e0 5402 }
ea953ef0
MG		 5403
5404 if (signal_pending(current))
80ced186 5405 goto out;
ea953ef0
MG		 5406 if (need_resched())
5407 schedule();
5408 }
5409
14168786 5410 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5411out:
5412 return ret;
ea953ef0
MG		 5413}
5414
4b8d54f9
ZE		 5415/*
5416 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5417 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5418 */
9fb41ba8 5419static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5420{
5421 skip_emulated_instruction(vcpu);
5422 kvm_vcpu_on_spin(vcpu);
5423
5424 return 1;
5425}
5426
59708670
SY		 5427static int handle_invalid_op(struct kvm_vcpu *vcpu)
5428{
5429 kvm_queue_exception(vcpu, UD_VECTOR);
5430 return 1;
5431}
5432
ff2f6fe9
NHE		 5433/*
5434 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5435 * We could reuse a single VMCS for all the L2 guests, but we also want the
5436 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5437 * allows keeping them loaded on the processor, and in the future will allow
5438 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5439 * every entry if they never change.
5440 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5441 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5442 *
5443 * The following functions allocate and free a vmcs02 in this pool.
5444 */
5445
5446/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5447static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5448{
5449 struct vmcs02_list *item;
5450 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5451 if (item->vmptr == vmx->nested.current_vmptr) {
5452 list_move(&item->list, &vmx->nested.vmcs02_pool);
5453 return &item->vmcs02;
5454 }
5455
5456 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5457 /* Recycle the least recently used VMCS. */
5458 item = list_entry(vmx->nested.vmcs02_pool.prev,
5459 struct vmcs02_list, list);
5460 item->vmptr = vmx->nested.current_vmptr;
5461 list_move(&item->list, &vmx->nested.vmcs02_pool);
5462 return &item->vmcs02;
5463 }
5464
5465 /* Create a new VMCS */
0fa24ce3 5466 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5467 if (!item)
5468 return NULL;
5469 item->vmcs02.vmcs = alloc_vmcs();
5470 if (!item->vmcs02.vmcs) {
5471 kfree(item);
5472 return NULL;
5473 }
5474 loaded_vmcs_init(&item->vmcs02);
5475 item->vmptr = vmx->nested.current_vmptr;
5476 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5477 vmx->nested.vmcs02_num++;
5478 return &item->vmcs02;
5479}
5480
5481/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5482static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5483{
5484 struct vmcs02_list *item;
5485 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5486 if (item->vmptr == vmptr) {
5487 free_loaded_vmcs(&item->vmcs02);
5488 list_del(&item->list);
5489 kfree(item);
5490 vmx->nested.vmcs02_num--;
5491 return;
5492 }
5493}
5494
5495/*
5496 * Free all VMCSs saved for this vcpu, except the one pointed by
5497 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5498 * currently used, if running L2), and vmcs01 when running L2.
5499 */
5500static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5501{
5502 struct vmcs02_list *item, *n;
5503 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5504 if (vmx->loaded_vmcs != &item->vmcs02)
5505 free_loaded_vmcs(&item->vmcs02);
5506 list_del(&item->list);
5507 kfree(item);
5508 }
5509 vmx->nested.vmcs02_num = 0;
5510
5511 if (vmx->loaded_vmcs != &vmx->vmcs01)
5512 free_loaded_vmcs(&vmx->vmcs01);
5513}
5514
ec378aee
NHE		 5515/*
5516 * Emulate the VMXON instruction.
5517 * Currently, we just remember that VMX is active, and do not save or even
5518 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5519 * do not currently need to store anything in that guest-allocated memory
5520 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5521 * argument is different from the VMXON pointer (which the spec says they do).
5522 */
5523static int handle_vmon(struct kvm_vcpu *vcpu)
5524{
5525 struct kvm_segment cs;
5526 struct vcpu_vmx *vmx = to_vmx(vcpu);
5527
5528 /* The Intel VMX Instruction Reference lists a bunch of bits that
5529 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5530 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5531 * Otherwise, we should fail with #UD. We test these now:
5532 */
5533 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5534 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5535 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5536 kvm_queue_exception(vcpu, UD_VECTOR);
5537 return 1;
5538 }
5539
5540 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5541 if (is_long_mode(vcpu) && !cs.l) {
5542 kvm_queue_exception(vcpu, UD_VECTOR);
5543 return 1;
5544 }
5545
5546 if (vmx_get_cpl(vcpu)) {
5547 kvm_inject_gp(vcpu, 0);
5548 return 1;
5549 }
5550
ff2f6fe9
NHE		 5551 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5552 vmx->nested.vmcs02_num = 0;
5553
ec378aee
NHE		 5554 vmx->nested.vmxon = true;
5555
5556 skip_emulated_instruction(vcpu);
5557 return 1;
5558}
5559
5560/*
5561 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5562 * for running VMX instructions (except VMXON, whose prerequisites are
5563 * slightly different). It also specifies what exception to inject otherwise.
5564 */
5565static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5566{
5567 struct kvm_segment cs;
5568 struct vcpu_vmx *vmx = to_vmx(vcpu);
5569
5570 if (!vmx->nested.vmxon) {
5571 kvm_queue_exception(vcpu, UD_VECTOR);
5572 return 0;
5573 }
5574
5575 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5576 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5577 (is_long_mode(vcpu) && !cs.l)) {
5578 kvm_queue_exception(vcpu, UD_VECTOR);
5579 return 0;
5580 }
5581
5582 if (vmx_get_cpl(vcpu)) {
5583 kvm_inject_gp(vcpu, 0);
5584 return 0;
5585 }
5586
5587 return 1;
5588}
5589
5590/*
5591 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5592 * just stops using VMX.
5593 */
5594static void free_nested(struct vcpu_vmx *vmx)
5595{
5596 if (!vmx->nested.vmxon)
5597 return;
5598 vmx->nested.vmxon = false;
a9d30f33
NHE		 5599 if (vmx->nested.current_vmptr != -1ull) {
5600 kunmap(vmx->nested.current_vmcs12_page);
5601 nested_release_page(vmx->nested.current_vmcs12_page);
5602 vmx->nested.current_vmptr = -1ull;
5603 vmx->nested.current_vmcs12 = NULL;
5604 }
fe3ef05c
NHE		 5605 /* Unpin physical memory we referred to in current vmcs02 */
5606 if (vmx->nested.apic_access_page) {
5607 nested_release_page(vmx->nested.apic_access_page);
5608 vmx->nested.apic_access_page = 0;
5609 }
ff2f6fe9
NHE		 5610
5611 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5612}
5613
5614/* Emulate the VMXOFF instruction */
5615static int handle_vmoff(struct kvm_vcpu *vcpu)
5616{
5617 if (!nested_vmx_check_permission(vcpu))
5618 return 1;
5619 free_nested(to_vmx(vcpu));
5620 skip_emulated_instruction(vcpu);
5621 return 1;
5622}
5623
064aea77
NHE		 5624/*
5625 * Decode the memory-address operand of a vmx instruction, as recorded on an
5626 * exit caused by such an instruction (run by a guest hypervisor).
5627 * On success, returns 0. When the operand is invalid, returns 1 and throws
5628 * #UD or #GP.
5629 */
5630static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5631 unsigned long exit_qualification,
5632 u32 vmx_instruction_info, gva_t *ret)
5633{
5634 /*
5635 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5636 * Execution", on an exit, vmx_instruction_info holds most of the
5637 * addressing components of the operand. Only the displacement part
5638 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5639 * For how an actual address is calculated from all these components,
5640 * refer to Vol. 1, "Operand Addressing".
5641 */
5642 int scaling = vmx_instruction_info & 3;
5643 int addr_size = (vmx_instruction_info >> 7) & 7;
5644 bool is_reg = vmx_instruction_info & (1u << 10);
5645 int seg_reg = (vmx_instruction_info >> 15) & 7;
5646 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5647 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5648 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5649 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5650
5651 if (is_reg) {
5652 kvm_queue_exception(vcpu, UD_VECTOR);
5653 return 1;
5654 }
5655
5656 /* Addr = segment_base + offset */
5657 /* offset = base + [index * scale] + displacement */
5658 *ret = vmx_get_segment_base(vcpu, seg_reg);
5659 if (base_is_valid)
5660 *ret += kvm_register_read(vcpu, base_reg);
5661 if (index_is_valid)
5662 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5663 *ret += exit_qualification; /* holds the displacement */
5664
5665 if (addr_size == 1) /* 32 bit */
5666 *ret &= 0xffffffff;
5667
5668 /*
5669 * TODO: throw #GP (and return 1) in various cases that the VM*
5670 * instructions require it - e.g., offset beyond segment limit,
5671 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5672 * address, and so on. Currently these are not checked.
5673 */
5674 return 0;
5675}
5676
0140caea
NHE		 5677/*
5678 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5679 * set the success or error code of an emulated VMX instruction, as specified
5680 * by Vol 2B, VMX Instruction Reference, "Conventions".
5681 */
5682static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5683{
5684 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5685 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5686 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5687}
5688
5689static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5690{
5691 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5692 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5693 X86_EFLAGS_SF | X86_EFLAGS_OF))
5694 | X86_EFLAGS_CF);
5695}
5696
5697static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5698 u32 vm_instruction_error)
5699{
5700 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5701 /*
5702 * failValid writes the error number to the current VMCS, which
5703 * can't be done there isn't a current VMCS.
5704 */
5705 nested_vmx_failInvalid(vcpu);
5706 return;
5707 }
5708 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5709 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5710 X86_EFLAGS_SF | X86_EFLAGS_OF))
5711 | X86_EFLAGS_ZF);
5712 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5713}
5714
27d6c865
NHE		 5715/* Emulate the VMCLEAR instruction */
5716static int handle_vmclear(struct kvm_vcpu *vcpu)
5717{
5718 struct vcpu_vmx *vmx = to_vmx(vcpu);
5719 gva_t gva;
5720 gpa_t vmptr;
5721 struct vmcs12 *vmcs12;
5722 struct page *page;
5723 struct x86_exception e;
5724
5725 if (!nested_vmx_check_permission(vcpu))
5726 return 1;
5727
5728 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5729 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5730 return 1;
5731
5732 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5733 sizeof(vmptr), &e)) {
5734 kvm_inject_page_fault(vcpu, &e);
5735 return 1;
5736 }
5737
5738 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5739 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5740 skip_emulated_instruction(vcpu);
5741 return 1;
5742 }
5743
5744 if (vmptr == vmx->nested.current_vmptr) {
5745 kunmap(vmx->nested.current_vmcs12_page);
5746 nested_release_page(vmx->nested.current_vmcs12_page);
5747 vmx->nested.current_vmptr = -1ull;
5748 vmx->nested.current_vmcs12 = NULL;
5749 }
5750
5751 page = nested_get_page(vcpu, vmptr);
5752 if (page == NULL) {
5753 /*
5754 * For accurate processor emulation, VMCLEAR beyond available
5755 * physical memory should do nothing at all. However, it is
5756 * possible that a nested vmx bug, not a guest hypervisor bug,
5757 * resulted in this case, so let's shut down before doing any
5758 * more damage:
5759 */
5760 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5761 return 1;
5762 }
5763 vmcs12 = kmap(page);
5764 vmcs12->launch_state = 0;
5765 kunmap(page);
5766 nested_release_page(page);
5767
5768 nested_free_vmcs02(vmx, vmptr);
5769
5770 skip_emulated_instruction(vcpu);
5771 nested_vmx_succeed(vcpu);
5772 return 1;
5773}
5774
cd232ad0
NHE		 5775static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5776
5777/* Emulate the VMLAUNCH instruction */
5778static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5779{
5780 return nested_vmx_run(vcpu, true);
5781}
5782
5783/* Emulate the VMRESUME instruction */
5784static int handle_vmresume(struct kvm_vcpu *vcpu)
5785{
5786
5787 return nested_vmx_run(vcpu, false);
5788}
5789
49f705c5
NHE		 5790enum vmcs_field_type {
5791 VMCS_FIELD_TYPE_U16 = 0,
5792 VMCS_FIELD_TYPE_U64 = 1,
5793 VMCS_FIELD_TYPE_U32 = 2,
5794 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5795};
5796
5797static inline int vmcs_field_type(unsigned long field)
5798{
5799 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5800 return VMCS_FIELD_TYPE_U32;
5801 return (field >> 13) & 0x3 ;
5802}
5803
5804static inline int vmcs_field_readonly(unsigned long field)
5805{
5806 return (((field >> 10) & 0x3) == 1);
5807}
5808
5809/*
5810 * Read a vmcs12 field. Since these can have varying lengths and we return
5811 * one type, we chose the biggest type (u64) and zero-extend the return value
5812 * to that size. Note that the caller, handle_vmread, might need to use only
5813 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5814 * 64-bit fields are to be returned).
5815 */
5816static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5817 unsigned long field, u64 *ret)
5818{
5819 short offset = vmcs_field_to_offset(field);
5820 char *p;
5821
5822 if (offset < 0)
5823 return 0;
5824
5825 p = ((char *)(get_vmcs12(vcpu))) + offset;
5826
5827 switch (vmcs_field_type(field)) {
5828 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5829 *ret = *((natural_width *)p);
5830 return 1;
5831 case VMCS_FIELD_TYPE_U16:
5832 *ret = *((u16 *)p);
5833 return 1;
5834 case VMCS_FIELD_TYPE_U32:
5835 *ret = *((u32 *)p);
5836 return 1;
5837 case VMCS_FIELD_TYPE_U64:
5838 *ret = *((u64 *)p);
5839 return 1;
5840 default:
5841 return 0; /* can never happen. */
5842 }
5843}
5844
5845/*
5846 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5847 * used before) all generate the same failure when it is missing.
5848 */
5849static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5850{
5851 struct vcpu_vmx *vmx = to_vmx(vcpu);
5852 if (vmx->nested.current_vmptr == -1ull) {
5853 nested_vmx_failInvalid(vcpu);
5854 skip_emulated_instruction(vcpu);
5855 return 0;
5856 }
5857 return 1;
5858}
5859
5860static int handle_vmread(struct kvm_vcpu *vcpu)
5861{
5862 unsigned long field;
5863 u64 field_value;
5864 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5865 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5866 gva_t gva = 0;
5867
5868 if (!nested_vmx_check_permission(vcpu) ||
5869 !nested_vmx_check_vmcs12(vcpu))
5870 return 1;
5871
5872 /* Decode instruction info and find the field to read */
5873 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5874 /* Read the field, zero-extended to a u64 field_value */
5875 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5876 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5877 skip_emulated_instruction(vcpu);
5878 return 1;
5879 }
5880 /*
5881 * Now copy part of this value to register or memory, as requested.
5882 * Note that the number of bits actually copied is 32 or 64 depending
5883 * on the guest's mode (32 or 64 bit), not on the given field's length.
5884 */
5885 if (vmx_instruction_info & (1u << 10)) {
5886 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5887 field_value);
5888 } else {
5889 if (get_vmx_mem_address(vcpu, exit_qualification,
5890 vmx_instruction_info, &gva))
5891 return 1;
5892 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5893 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5894 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5895 }
5896
5897 nested_vmx_succeed(vcpu);
5898 skip_emulated_instruction(vcpu);
5899 return 1;
5900}
5901
5902
5903static int handle_vmwrite(struct kvm_vcpu *vcpu)
5904{
5905 unsigned long field;
5906 gva_t gva;
5907 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5908 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5909 char *p;
5910 short offset;
5911 /* The value to write might be 32 or 64 bits, depending on L1's long
5912 * mode, and eventually we need to write that into a field of several
5913 * possible lengths. The code below first zero-extends the value to 64
5914 * bit (field_value), and then copies only the approriate number of
5915 * bits into the vmcs12 field.
5916 */
5917 u64 field_value = 0;
5918 struct x86_exception e;
5919
5920 if (!nested_vmx_check_permission(vcpu) ||
5921 !nested_vmx_check_vmcs12(vcpu))
5922 return 1;
5923
5924 if (vmx_instruction_info & (1u << 10))
5925 field_value = kvm_register_read(vcpu,
5926 (((vmx_instruction_info) >> 3) & 0xf));
5927 else {
5928 if (get_vmx_mem_address(vcpu, exit_qualification,
5929 vmx_instruction_info, &gva))
5930 return 1;
5931 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5932 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5933 kvm_inject_page_fault(vcpu, &e);
5934 return 1;
5935 }
5936 }
5937
5938
5939 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5940 if (vmcs_field_readonly(field)) {
5941 nested_vmx_failValid(vcpu,
5942 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5943 skip_emulated_instruction(vcpu);
5944 return 1;
5945 }
5946
5947 offset = vmcs_field_to_offset(field);
5948 if (offset < 0) {
5949 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5950 skip_emulated_instruction(vcpu);
5951 return 1;
5952 }
5953 p = ((char *) get_vmcs12(vcpu)) + offset;
5954
5955 switch (vmcs_field_type(field)) {
5956 case VMCS_FIELD_TYPE_U16:
5957 *(u16 *)p = field_value;
5958 break;
5959 case VMCS_FIELD_TYPE_U32:
5960 *(u32 *)p = field_value;
5961 break;
5962 case VMCS_FIELD_TYPE_U64:
5963 *(u64 *)p = field_value;
5964 break;
5965 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5966 *(natural_width *)p = field_value;
5967 break;
5968 default:
5969 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5970 skip_emulated_instruction(vcpu);
5971 return 1;
5972 }
5973
5974 nested_vmx_succeed(vcpu);
5975 skip_emulated_instruction(vcpu);
5976 return 1;
5977}
5978
63846663
NHE		 5979/* Emulate the VMPTRLD instruction */
5980static int handle_vmptrld(struct kvm_vcpu *vcpu)
5981{
5982 struct vcpu_vmx *vmx = to_vmx(vcpu);
5983 gva_t gva;
5984 gpa_t vmptr;
5985 struct x86_exception e;
5986
5987 if (!nested_vmx_check_permission(vcpu))
5988 return 1;
5989
5990 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5991 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5992 return 1;
5993
5994 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5995 sizeof(vmptr), &e)) {
5996 kvm_inject_page_fault(vcpu, &e);
5997 return 1;
5998 }
5999
6000 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6001 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6002 skip_emulated_instruction(vcpu);
6003 return 1;
6004 }
6005
6006 if (vmx->nested.current_vmptr != vmptr) {
6007 struct vmcs12 *new_vmcs12;
6008 struct page *page;
6009 page = nested_get_page(vcpu, vmptr);
6010 if (page == NULL) {
6011 nested_vmx_failInvalid(vcpu);
6012 skip_emulated_instruction(vcpu);
6013 return 1;
6014 }
6015 new_vmcs12 = kmap(page);
6016 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6017 kunmap(page);
6018 nested_release_page_clean(page);
6019 nested_vmx_failValid(vcpu,
6020 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6021 skip_emulated_instruction(vcpu);
6022 return 1;
6023 }
6024 if (vmx->nested.current_vmptr != -1ull) {
6025 kunmap(vmx->nested.current_vmcs12_page);
6026 nested_release_page(vmx->nested.current_vmcs12_page);
6027 }
6028
6029 vmx->nested.current_vmptr = vmptr;
6030 vmx->nested.current_vmcs12 = new_vmcs12;
6031 vmx->nested.current_vmcs12_page = page;
6032 }
6033
6034 nested_vmx_succeed(vcpu);
6035 skip_emulated_instruction(vcpu);
6036 return 1;
6037}
6038
6a4d7550
NHE		 6039/* Emulate the VMPTRST instruction */
6040static int handle_vmptrst(struct kvm_vcpu *vcpu)
6041{
6042 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6043 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6044 gva_t vmcs_gva;
6045 struct x86_exception e;
6046
6047 if (!nested_vmx_check_permission(vcpu))
6048 return 1;
6049
6050 if (get_vmx_mem_address(vcpu, exit_qualification,
6051 vmx_instruction_info, &vmcs_gva))
6052 return 1;
6053 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6054 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6055 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6056 sizeof(u64), &e)) {
6057 kvm_inject_page_fault(vcpu, &e);
6058 return 1;
6059 }
6060 nested_vmx_succeed(vcpu);
6061 skip_emulated_instruction(vcpu);
6062 return 1;
6063}
6064
6aa8b732
AK		 6065/*
6066 * The exit handlers return 1 if the exit was handled fully and guest execution
6067 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6068 * to be done to userspace and return 0.
6069 */
772e0318 6070static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6071 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6072 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6073 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6074 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6075 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6076 [EXIT_REASON_CR_ACCESS] = handle_cr,
6077 [EXIT_REASON_DR_ACCESS] = handle_dr,
6078 [EXIT_REASON_CPUID] = handle_cpuid,
6079 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6080 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6081 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6082 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6083 [EXIT_REASON_INVD] = handle_invd,
a7052897 6084 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6085 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6086 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6087 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6088 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6089 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6090 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6091 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6092 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6093 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6094 [EXIT_REASON_VMOFF] = handle_vmoff,
6095 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6096 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6097 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6098 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6099 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6100 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6101 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6102 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6103 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6104 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6105 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6106 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6107 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6108 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6109};
6110
6111static const int kvm_vmx_max_exit_handlers =
50a3485c 6112 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6113
908a7bdd
JK		 6114static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6115 struct vmcs12 *vmcs12)
6116{
6117 unsigned long exit_qualification;
6118 gpa_t bitmap, last_bitmap;
6119 unsigned int port;
6120 int size;
6121 u8 b;
6122
6123 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6124 return 1;
6125
6126 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6127 return 0;
6128
6129 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6130
6131 port = exit_qualification >> 16;
6132 size = (exit_qualification & 7) + 1;
6133
6134 last_bitmap = (gpa_t)-1;
6135 b = -1;
6136
6137 while (size > 0) {
6138 if (port < 0x8000)
6139 bitmap = vmcs12->io_bitmap_a;
6140 else if (port < 0x10000)
6141 bitmap = vmcs12->io_bitmap_b;
6142 else
6143 return 1;
6144 bitmap += (port & 0x7fff) / 8;
6145
6146 if (last_bitmap != bitmap)
6147 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6148 return 1;
6149 if (b & (1 << (port & 7)))
6150 return 1;
6151
6152 port++;
6153 size--;
6154 last_bitmap = bitmap;
6155 }
6156
6157 return 0;
6158}
6159
644d711a
NHE		 6160/*
6161 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6162 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6163 * disinterest in the current event (read or write a specific MSR) by using an
6164 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6165 */
6166static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6167 struct vmcs12 *vmcs12, u32 exit_reason)
6168{
6169 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6170 gpa_t bitmap;
6171
cbd29cb6 6172 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6173 return 1;
6174
6175 /*
6176 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6177 * for the four combinations of read/write and low/high MSR numbers.
6178 * First we need to figure out which of the four to use:
6179 */
6180 bitmap = vmcs12->msr_bitmap;
6181 if (exit_reason == EXIT_REASON_MSR_WRITE)
6182 bitmap += 2048;
6183 if (msr_index >= 0xc0000000) {
6184 msr_index -= 0xc0000000;
6185 bitmap += 1024;
6186 }
6187
6188 /* Then read the msr_index'th bit from this bitmap: */
6189 if (msr_index < 1024*8) {
6190 unsigned char b;
bd31a7f5
JK		 6191 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6192 return 1;
644d711a
NHE		 6193 return 1 & (b >> (msr_index & 7));
6194 } else
6195 return 1; /* let L1 handle the wrong parameter */
6196}
6197
6198/*
6199 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6200 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6201 * intercept (via guest_host_mask etc.) the current event.
6202 */
6203static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6204 struct vmcs12 *vmcs12)
6205{
6206 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6207 int cr = exit_qualification & 15;
6208 int reg = (exit_qualification >> 8) & 15;
6209 unsigned long val = kvm_register_read(vcpu, reg);
6210
6211 switch ((exit_qualification >> 4) & 3) {
6212 case 0: /* mov to cr */
6213 switch (cr) {
6214 case 0:
6215 if (vmcs12->cr0_guest_host_mask &
6216 (val ^ vmcs12->cr0_read_shadow))
6217 return 1;
6218 break;
6219 case 3:
6220 if ((vmcs12->cr3_target_count >= 1 &&
6221 vmcs12->cr3_target_value0 == val) ||
6222 (vmcs12->cr3_target_count >= 2 &&
6223 vmcs12->cr3_target_value1 == val) ||
6224 (vmcs12->cr3_target_count >= 3 &&
6225 vmcs12->cr3_target_value2 == val) ||
6226 (vmcs12->cr3_target_count >= 4 &&
6227 vmcs12->cr3_target_value3 == val))
6228 return 0;
6229 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6230 return 1;
6231 break;
6232 case 4:
6233 if (vmcs12->cr4_guest_host_mask &
6234 (vmcs12->cr4_read_shadow ^ val))
6235 return 1;
6236 break;
6237 case 8:
6238 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6239 return 1;
6240 break;
6241 }
6242 break;
6243 case 2: /* clts */
6244 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6245 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6246 return 1;
6247 break;
6248 case 1: /* mov from cr */
6249 switch (cr) {
6250 case 3:
6251 if (vmcs12->cpu_based_vm_exec_control &
6252 CPU_BASED_CR3_STORE_EXITING)
6253 return 1;
6254 break;
6255 case 8:
6256 if (vmcs12->cpu_based_vm_exec_control &
6257 CPU_BASED_CR8_STORE_EXITING)
6258 return 1;
6259 break;
6260 }
6261 break;
6262 case 3: /* lmsw */
6263 /*
6264 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6265 * cr0. Other attempted changes are ignored, with no exit.
6266 */
6267 if (vmcs12->cr0_guest_host_mask & 0xe &
6268 (val ^ vmcs12->cr0_read_shadow))
6269 return 1;
6270 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6271 !(vmcs12->cr0_read_shadow & 0x1) &&
6272 (val & 0x1))
6273 return 1;
6274 break;
6275 }
6276 return 0;
6277}
6278
6279/*
6280 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6281 * should handle it ourselves in L0 (and then continue L2). Only call this
6282 * when in is_guest_mode (L2).
6283 */
6284static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6285{
644d711a
NHE		 6286 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6287 struct vcpu_vmx *vmx = to_vmx(vcpu);
6288 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6289 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6290
6291 if (vmx->nested.nested_run_pending)
6292 return 0;
6293
6294 if (unlikely(vmx->fail)) {
bd80158a
JK		 6295 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6296 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6297 return 1;
6298 }
6299
6300 switch (exit_reason) {
6301 case EXIT_REASON_EXCEPTION_NMI:
6302 if (!is_exception(intr_info))
6303 return 0;
6304 else if (is_page_fault(intr_info))
6305 return enable_ept;
6306 return vmcs12->exception_bitmap &
6307 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6308 case EXIT_REASON_EXTERNAL_INTERRUPT:
6309 return 0;
6310 case EXIT_REASON_TRIPLE_FAULT:
6311 return 1;
6312 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6313 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6314 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6315 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6316 case EXIT_REASON_TASK_SWITCH:
6317 return 1;
6318 case EXIT_REASON_CPUID:
6319 return 1;
6320 case EXIT_REASON_HLT:
6321 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6322 case EXIT_REASON_INVD:
6323 return 1;
6324 case EXIT_REASON_INVLPG:
6325 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6326 case EXIT_REASON_RDPMC:
6327 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6328 case EXIT_REASON_RDTSC:
6329 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6330 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6331 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6332 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6333 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6334 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6335 /*
6336 * VMX instructions trap unconditionally. This allows L1 to
6337 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6338 */
6339 return 1;
6340 case EXIT_REASON_CR_ACCESS:
6341 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6342 case EXIT_REASON_DR_ACCESS:
6343 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6344 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6345 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6346 case EXIT_REASON_MSR_READ:
6347 case EXIT_REASON_MSR_WRITE:
6348 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6349 case EXIT_REASON_INVALID_STATE:
6350 return 1;
6351 case EXIT_REASON_MWAIT_INSTRUCTION:
6352 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6353 case EXIT_REASON_MONITOR_INSTRUCTION:
6354 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6355 case EXIT_REASON_PAUSE_INSTRUCTION:
6356 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6357 nested_cpu_has2(vmcs12,
6358 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6359 case EXIT_REASON_MCE_DURING_VMENTRY:
6360 return 0;
6361 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6362 return 1;
6363 case EXIT_REASON_APIC_ACCESS:
6364 return nested_cpu_has2(vmcs12,
6365 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6366 case EXIT_REASON_EPT_VIOLATION:
6367 case EXIT_REASON_EPT_MISCONFIG:
6368 return 0;
0238ea91
JK		 6369 case EXIT_REASON_PREEMPTION_TIMER:
6370 return vmcs12->pin_based_vm_exec_control &
6371 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6372 case EXIT_REASON_WBINVD:
6373 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6374 case EXIT_REASON_XSETBV:
6375 return 1;
6376 default:
6377 return 1;
6378 }
6379}
6380
586f9607
AK		 6381static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6382{
6383 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6384 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6385}
6386
6aa8b732
AK		 6387/*
6388 * The guest has exited. See if we can fix it or if we need userspace
6389 * assistance.
6390 */
851ba692 6391static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6392{
29bd8a78 6393 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6394 u32 exit_reason = vmx->exit_reason;
1155f76a 6395 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6396
80ced186 6397 /* If guest state is invalid, start emulating */
14168786 6398 if (vmx->emulation_required)
80ced186 6399 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6400
b6f1250e
NHE		 6401 /*
6402 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6403 * we did not inject a still-pending event to L1 now because of
6404 * nested_run_pending, we need to re-enable this bit.
6405 */
6406 if (vmx->nested.nested_run_pending)
6407 kvm_make_request(KVM_REQ_EVENT, vcpu);
6408
509c75ea
NHE		 6409 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6410 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6411 vmx->nested.nested_run_pending = 1;
6412 else
6413 vmx->nested.nested_run_pending = 0;
6414
6415 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6416 nested_vmx_vmexit(vcpu);
6417 return 1;
6418 }
6419
5120702e
MG		 6420 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6421 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6422 vcpu->run->fail_entry.hardware_entry_failure_reason
6423 = exit_reason;
6424 return 0;
6425 }
6426
29bd8a78 6427 if (unlikely(vmx->fail)) {
851ba692
AK		 6428 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6429 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6430 = vmcs_read32(VM_INSTRUCTION_ERROR);
6431 return 0;
6432 }
6aa8b732 6433
b9bf6882
XG		 6434 /*
6435 * Note:
6436 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6437 * delivery event since it indicates guest is accessing MMIO.
6438 * The vm-exit can be triggered again after return to guest that
6439 * will cause infinite loop.
6440 */
d77c26fc 6441 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6442 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6443 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6444 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6445 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6446 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6447 vcpu->run->internal.ndata = 2;
6448 vcpu->run->internal.data[0] = vectoring_info;
6449 vcpu->run->internal.data[1] = exit_reason;
6450 return 0;
6451 }
3b86cd99 6452
644d711a
NHE		 6453 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6454 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6455 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6456 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6457 vmx->soft_vnmi_blocked = 0;
3b86cd99 6458 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6459 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6460 /*
6461 * This CPU don't support us in finding the end of an
6462 * NMI-blocked window if the guest runs with IRQs
6463 * disabled. So we pull the trigger after 1 s of
6464 * futile waiting, but inform the user about this.
6465 */
6466 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6467 "state on VCPU %d after 1 s timeout\n",
6468 __func__, vcpu->vcpu_id);
6469 vmx->soft_vnmi_blocked = 0;
3b86cd99 6470 }
3b86cd99
JK		 6471 }
6472
6aa8b732
AK		 6473 if (exit_reason < kvm_vmx_max_exit_handlers
6474 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6475 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6476 else {
851ba692
AK		 6477 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6478 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6479 }
6480 return 0;
6481}
6482
95ba8273 6483static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6484{
95ba8273 6485 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6486 vmcs_write32(TPR_THRESHOLD, 0);
6487 return;
6488 }
6489
95ba8273 6490 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6491}
6492
8d14695f
YZ		 6493static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6494{
6495 u32 sec_exec_control;
6496
6497 /*
6498 * There is not point to enable virtualize x2apic without enable
6499 * apicv
6500 */
c7c9c56c
YZ		 6501 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6502 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6503 return;
6504
6505 if (!vm_need_tpr_shadow(vcpu->kvm))
6506 return;
6507
6508 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6509
6510 if (set) {
6511 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6512 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6513 } else {
6514 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6515 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6516 }
6517 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6518
6519 vmx_set_msr_bitmap(vcpu);
6520}
6521
c7c9c56c
YZ		 6522static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6523{
6524 u16 status;
6525 u8 old;
6526
6527 if (!vmx_vm_has_apicv(kvm))
6528 return;
6529
6530 if (isr == -1)
6531 isr = 0;
6532
6533 status = vmcs_read16(GUEST_INTR_STATUS);
6534 old = status >> 8;
6535 if (isr != old) {
6536 status &= 0xff;
6537 status |= isr << 8;
6538 vmcs_write16(GUEST_INTR_STATUS, status);
6539 }
6540}
6541
6542static void vmx_set_rvi(int vector)
6543{
6544 u16 status;
6545 u8 old;
6546
6547 status = vmcs_read16(GUEST_INTR_STATUS);
6548 old = (u8)status & 0xff;
6549 if ((u8)vector != old) {
6550 status &= ~0xff;
6551 status |= (u8)vector;
6552 vmcs_write16(GUEST_INTR_STATUS, status);
6553 }
6554}
6555
6556static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6557{
6558 if (max_irr == -1)
6559 return;
6560
6561 vmx_set_rvi(max_irr);
6562}
6563
6564static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6565{
3d81bc7e
YZ		 6566 if (!vmx_vm_has_apicv(vcpu->kvm))
6567 return;
6568
c7c9c56c
YZ		 6569 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6570 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6571 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6572 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6573}
6574
51aa01d1 6575static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6576{
00eba012
AK		 6577 u32 exit_intr_info;
6578
6579 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6580 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6581 return;
6582
c5ca8e57 6583 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6584 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6585
6586 /* Handle machine checks before interrupts are enabled */
00eba012 6587 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6588 kvm_machine_check();
6589
20f65983 6590 /* We need to handle NMIs before interrupts are enabled */
00eba012 6591 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6592 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6593 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6594 asm("int $2");
ff9d07a0
ZY		 6595 kvm_after_handle_nmi(&vmx->vcpu);
6596 }
51aa01d1 6597}
20f65983 6598
a547c6db
YZ		 6599static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6600{
6601 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6602
6603 /*
6604 * If external interrupt exists, IF bit is set in rflags/eflags on the
6605 * interrupt stack frame, and interrupt will be enabled on a return
6606 * from interrupt handler.
6607 */
6608 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6609 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6610 unsigned int vector;
6611 unsigned long entry;
6612 gate_desc *desc;
6613 struct vcpu_vmx *vmx = to_vmx(vcpu);
6614#ifdef CONFIG_X86_64
6615 unsigned long tmp;
6616#endif
6617
6618 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6619 desc = (gate_desc *)vmx->host_idt_base + vector;
6620 entry = gate_offset(*desc);
6621 asm volatile(
6622#ifdef CONFIG_X86_64
6623 "mov %%" _ASM_SP ", %[sp]\n\t"
6624 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6625 "push $%c[ss]\n\t"
6626 "push %[sp]\n\t"
6627#endif
6628 "pushf\n\t"
6629 "orl $0x200, (%%" _ASM_SP ")\n\t"
6630 __ASM_SIZE(push) " $%c[cs]\n\t"
6631 "call *%[entry]\n\t"
6632 :
6633#ifdef CONFIG_X86_64
6634 [sp]"=&r"(tmp)
6635#endif
6636 :
6637 [entry]"r"(entry),
6638 [ss]"i"(__KERNEL_DS),
6639 [cs]"i"(__KERNEL_CS)
6640 );
6641 } else
6642 local_irq_enable();
6643}
6644
51aa01d1
AK		 6645static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6646{
c5ca8e57 6647 u32 exit_intr_info;
51aa01d1
AK		 6648 bool unblock_nmi;
6649 u8 vector;
6650 bool idtv_info_valid;
6651
6652 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6653
cf393f75 6654 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6655 if (vmx->nmi_known_unmasked)
6656 return;
c5ca8e57
AK		 6657 /*
6658 * Can't use vmx->exit_intr_info since we're not sure what
6659 * the exit reason is.
6660 */
6661 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6662 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6663 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6664 /*
7b4a25cb 6665 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6666 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6667 * a guest IRET fault.
7b4a25cb
GN		 6668 * SDM 3: 23.2.2 (September 2008)
6669 * Bit 12 is undefined in any of the following cases:
6670 * If the VM exit sets the valid bit in the IDT-vectoring
6671 * information field.
6672 * If the VM exit is due to a double fault.
cf393f75 6673 */
7b4a25cb
GN		 6674 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6675 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6677 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6678 else
6679 vmx->nmi_known_unmasked =
6680 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6681 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6682 } else if (unlikely(vmx->soft_vnmi_blocked))
6683 vmx->vnmi_blocked_time +=
6684 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6685}
6686
3ab66e8a 6687static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6688 u32 idt_vectoring_info,
6689 int instr_len_field,
6690 int error_code_field)
51aa01d1 6691{
51aa01d1
AK		 6692 u8 vector;
6693 int type;
6694 bool idtv_info_valid;
6695
6696 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6697
3ab66e8a
JK		 6698 vcpu->arch.nmi_injected = false;
6699 kvm_clear_exception_queue(vcpu);
6700 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6701
6702 if (!idtv_info_valid)
6703 return;
6704
3ab66e8a 6705 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6706
668f612f
AK		 6707 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6708 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6709
64a7ec06 6710 switch (type) {
37b96e98 6711 case INTR_TYPE_NMI_INTR:
3ab66e8a 6712 vcpu->arch.nmi_injected = true;
668f612f 6713 /*
7b4a25cb 6714 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6715 * Clear bit "block by NMI" before VM entry if a NMI
6716 * delivery faulted.
668f612f 6717 */
3ab66e8a 6718 vmx_set_nmi_mask(vcpu, false);
37b96e98 6719 break;
37b96e98 6720 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6721 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6722 /* fall through */
6723 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6724 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6725 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6726 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6727 } else
3ab66e8a 6728 kvm_queue_exception(vcpu, vector);
37b96e98 6729 break;
66fd3f7f 6730 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6731 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6732 /* fall through */
37b96e98 6733 case INTR_TYPE_EXT_INTR:
3ab66e8a 6734 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6735 break;
6736 default:
6737 break;
f7d9238f 6738 }
cf393f75
AK		 6739}
6740
83422e17
AK		 6741static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6742{
3ab66e8a 6743 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6744 VM_EXIT_INSTRUCTION_LEN,
6745 IDT_VECTORING_ERROR_CODE);
6746}
6747
b463a6f7
AK		 6748static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6749{
3ab66e8a 6750 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6751 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6752 VM_ENTRY_INSTRUCTION_LEN,
6753 VM_ENTRY_EXCEPTION_ERROR_CODE);
6754
6755 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6756}
6757
d7cd9796
GN		 6758static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6759{
6760 int i, nr_msrs;
6761 struct perf_guest_switch_msr *msrs;
6762
6763 msrs = perf_guest_get_msrs(&nr_msrs);
6764
6765 if (!msrs)
6766 return;
6767
6768 for (i = 0; i < nr_msrs; i++)
6769 if (msrs[i].host == msrs[i].guest)
6770 clear_atomic_switch_msr(vmx, msrs[i].msr);
6771 else
6772 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6773 msrs[i].host);
6774}
6775
a3b5ba49 6776static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6777{
a2fa3e9f 6778 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6779 unsigned long debugctlmsr;
104f226b
AK		 6780
6781 /* Record the guest's net vcpu time for enforced NMI injections. */
6782 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6783 vmx->entry_time = ktime_get();
6784
6785 /* Don't enter VMX if guest state is invalid, let the exit handler
6786 start emulation until we arrive back to a valid state */
14168786 6787 if (vmx->emulation_required)
104f226b
AK		 6788 return;
6789
6790 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6791 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6792 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6793 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6794
6795 /* When single-stepping over STI and MOV SS, we must clear the
6796 * corresponding interruptibility bits in the guest state. Otherwise
6797 * vmentry fails as it then expects bit 14 (BS) in pending debug
6798 * exceptions being set, but that's not correct for the guest debugging
6799 * case. */
6800 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6801 vmx_set_interrupt_shadow(vcpu, 0);
6802
d7cd9796 6803 atomic_switch_perf_msrs(vmx);
2a7921b7 6804 debugctlmsr = get_debugctlmsr();
d7cd9796 6805
d462b819 6806 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6807 asm(
6aa8b732 6808 /* Store host registers */
b188c81f
AK		 6809 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6810 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6811 "push %%" _ASM_CX " \n\t"
6812 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6813 "je 1f \n\t"
b188c81f 6814 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6815 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6816 "1: \n\t"
d3edefc0 6817 /* Reload cr2 if changed */
b188c81f
AK		 6818 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6819 "mov %%cr2, %%" _ASM_DX " \n\t"
6820 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6821 "je 2f \n\t"
b188c81f 6822 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6823 "2: \n\t"
6aa8b732 6824 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6825 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6826 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6827 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6828 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6829 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6830 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6831 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6832 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6833#ifdef CONFIG_X86_64
e08aa78a
AK		 6834 "mov %c[r8](%0), %%r8 \n\t"
6835 "mov %c[r9](%0), %%r9 \n\t"
6836 "mov %c[r10](%0), %%r10 \n\t"
6837 "mov %c[r11](%0), %%r11 \n\t"
6838 "mov %c[r12](%0), %%r12 \n\t"
6839 "mov %c[r13](%0), %%r13 \n\t"
6840 "mov %c[r14](%0), %%r14 \n\t"
6841 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6842#endif
b188c81f 6843 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6844
6aa8b732 6845 /* Enter guest mode */
83287ea4 6846 "jne 1f \n\t"
4ecac3fd 6847 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6848 "jmp 2f \n\t"
6849 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6850 "2: "
6aa8b732 6851 /* Save guest registers, load host registers, keep flags */
b188c81f 6852 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6853 "pop %0 \n\t"
b188c81f
AK		 6854 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6855 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6856 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6857 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6858 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6859 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6860 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6861#ifdef CONFIG_X86_64
e08aa78a
AK		 6862 "mov %%r8, %c[r8](%0) \n\t"
6863 "mov %%r9, %c[r9](%0) \n\t"
6864 "mov %%r10, %c[r10](%0) \n\t"
6865 "mov %%r11, %c[r11](%0) \n\t"
6866 "mov %%r12, %c[r12](%0) \n\t"
6867 "mov %%r13, %c[r13](%0) \n\t"
6868 "mov %%r14, %c[r14](%0) \n\t"
6869 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6870#endif
b188c81f
AK		 6871 "mov %%cr2, %%" _ASM_AX " \n\t"
6872 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6873
b188c81f 6874 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6875 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6876 ".pushsection .rodata \n\t"
6877 ".global vmx_return \n\t"
6878 "vmx_return: " _ASM_PTR " 2b \n\t"
6879 ".popsection"
e08aa78a 6880 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6881 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6882 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6883 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6884 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6885 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6886 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6887 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6888 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6889 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6890 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6891#ifdef CONFIG_X86_64
ad312c7c
ZX		 6892 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6893 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6894 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6895 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6896 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6897 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6898 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6899 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6900#endif
40712fae
AK		 6901 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6902 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6903 : "cc", "memory"
6904#ifdef CONFIG_X86_64
b188c81f 6905 , "rax", "rbx", "rdi", "rsi"
c2036300 6906 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6907#else
6908 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6909#endif
6910 );
6aa8b732 6911
2a7921b7
GN		 6912 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6913 if (debugctlmsr)
6914 update_debugctlmsr(debugctlmsr);
6915
aa67f609
AK		 6916#ifndef CONFIG_X86_64
6917 /*
6918 * The sysexit path does not restore ds/es, so we must set them to
6919 * a reasonable value ourselves.
6920 *
6921 * We can't defer this to vmx_load_host_state() since that function
6922 * may be executed in interrupt context, which saves and restore segments
6923 * around it, nullifying its effect.
6924 */
6925 loadsegment(ds, __USER_DS);
6926 loadsegment(es, __USER_DS);
6927#endif
6928
6de4f3ad 6929 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6930 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6931 | (1 << VCPU_EXREG_CPL)
aff48baa 6932 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6933 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6934 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6935 vcpu->arch.regs_dirty = 0;
6936
1155f76a
AK		 6937 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6938
d462b819 6939 vmx->loaded_vmcs->launched = 1;
1b6269db 6940
51aa01d1 6941 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6942 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6943
6944 vmx_complete_atomic_exit(vmx);
6945 vmx_recover_nmi_blocking(vmx);
cf393f75 6946 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6947}
6948
6aa8b732
AK		 6949static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6950{
fb3f0f51
RR		 6951 struct vcpu_vmx *vmx = to_vmx(vcpu);
6952
cdbecfc3 6953 free_vpid(vmx);
ec378aee 6954 free_nested(vmx);
d462b819 6955 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6956 kfree(vmx->guest_msrs);
6957 kvm_vcpu_uninit(vcpu);
a4770347 6958 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6959}
6960
fb3f0f51 6961static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6962{
fb3f0f51 6963 int err;
c16f862d 6964 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6965 int cpu;
6aa8b732 6966
a2fa3e9f 6967 if (!vmx)
fb3f0f51
RR		 6968 return ERR_PTR(-ENOMEM);
6969
2384d2b3
SY		 6970 allocate_vpid(vmx);
6971
fb3f0f51
RR		 6972 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6973 if (err)
6974 goto free_vcpu;
965b58a5 6975
a2fa3e9f 6976 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6977 err = -ENOMEM;
fb3f0f51 6978 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6979 goto uninit_vcpu;
6980 }
965b58a5 6981
d462b819
NHE		 6982 vmx->loaded_vmcs = &vmx->vmcs01;
6983 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6984 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6985 goto free_msrs;
d462b819
NHE		 6986 if (!vmm_exclusive)
6987 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6988 loaded_vmcs_init(vmx->loaded_vmcs);
6989 if (!vmm_exclusive)
6990 kvm_cpu_vmxoff();
a2fa3e9f 6991
15ad7146
AK		 6992 cpu = get_cpu();
6993 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6994 vmx->vcpu.cpu = cpu;
8b9cf98c 6995 err = vmx_vcpu_setup(vmx);
fb3f0f51 6996 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6997 put_cpu();
fb3f0f51
RR		 6998 if (err)
6999 goto free_vmcs;
a63cb560 7000 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7001 err = alloc_apic_access_page(kvm);
7002 if (err)
5e4a0b3c 7003 goto free_vmcs;
a63cb560 7004 }
fb3f0f51 7005
b927a3ce
SY		 7006 if (enable_ept) {
7007 if (!kvm->arch.ept_identity_map_addr)
7008 kvm->arch.ept_identity_map_addr =
7009 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7010 err = -ENOMEM;
b7ebfb05
SY		 7011 if (alloc_identity_pagetable(kvm) != 0)
7012 goto free_vmcs;
93ea5388
GN		 7013 if (!init_rmode_identity_map(kvm))
7014 goto free_vmcs;
b927a3ce 7015 }
b7ebfb05 7016
a9d30f33
NHE		 7017 vmx->nested.current_vmptr = -1ull;
7018 vmx->nested.current_vmcs12 = NULL;
7019
fb3f0f51
RR		 7020 return &vmx->vcpu;
7021
7022free_vmcs:
5f3fbc34 7023 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7024free_msrs:
fb3f0f51
RR		 7025 kfree(vmx->guest_msrs);
7026uninit_vcpu:
7027 kvm_vcpu_uninit(&vmx->vcpu);
7028free_vcpu:
cdbecfc3 7029 free_vpid(vmx);
a4770347 7030 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7031 return ERR_PTR(err);
6aa8b732
AK		 7032}
7033
002c7f7c
YS		 7034static void __init vmx_check_processor_compat(void *rtn)
7035{
7036 struct vmcs_config vmcs_conf;
7037
7038 *(int *)rtn = 0;
7039 if (setup_vmcs_config(&vmcs_conf) < 0)
7040 *(int *)rtn = -EIO;
7041 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7042 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7043 smp_processor_id());
7044 *(int *)rtn = -EIO;
7045 }
7046}
7047
67253af5
SY		 7048static int get_ept_level(void)
7049{
7050 return VMX_EPT_DEFAULT_GAW + 1;
7051}
7052
4b12f0de 7053static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7054{
4b12f0de
SY		 7055 u64 ret;
7056
522c68c4
SY		 7057 /* For VT-d and EPT combination
7058 * 1. MMIO: always map as UC
7059 * 2. EPT with VT-d:
7060 * a. VT-d without snooping control feature: can't guarantee the
7061 * result, try to trust guest.
7062 * b. VT-d with snooping control feature: snooping control feature of
7063 * VT-d engine can guarantee the cache correctness. Just set it
7064 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7065 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7066 * consistent with host MTRR
7067 */
4b12f0de
SY		 7068 if (is_mmio)
7069 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7070 else if (vcpu->kvm->arch.iommu_domain &&
7071 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7072 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7073 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7074 else
522c68c4 7075 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7076 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7077
7078 return ret;
64d4d521
SY		 7079}
7080
17cc3935 7081static int vmx_get_lpage_level(void)
344f414f 7082{
878403b7
SY		 7083 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7084 return PT_DIRECTORY_LEVEL;
7085 else
7086 /* For shadow and EPT supported 1GB page */
7087 return PT_PDPE_LEVEL;
344f414f
JR		 7088}
7089
0e851880
SY		 7090static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7091{
4e47c7a6
SY		 7092 struct kvm_cpuid_entry2 *best;
7093 struct vcpu_vmx *vmx = to_vmx(vcpu);
7094 u32 exec_control;
7095
7096 vmx->rdtscp_enabled = false;
7097 if (vmx_rdtscp_supported()) {
7098 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7099 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7100 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7101 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7102 vmx->rdtscp_enabled = true;
7103 else {
7104 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7105 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7106 exec_control);
7107 }
7108 }
7109 }
ad756a16 7110
ad756a16
MJ		 7111 /* Exposing INVPCID only when PCID is exposed */
7112 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7113 if (vmx_invpcid_supported() &&
4f977045 7114 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7115 guest_cpuid_has_pcid(vcpu)) {
29282fde 7116 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7117 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7118 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7119 exec_control);
7120 } else {
29282fde
TI		 7121 if (cpu_has_secondary_exec_ctrls()) {
7122 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7123 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7124 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7125 exec_control);
7126 }
ad756a16 7127 if (best)
4f977045 7128 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7129 }
0e851880
SY		 7130}
7131
d4330ef2
JR		 7132static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7133{
7b8050f5
NHE		 7134 if (func == 1 && nested)
7135 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7136}
7137
fe3ef05c
NHE		 7138/*
7139 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7140 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7141 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7142 * guest in a way that will both be appropriate to L1's requests, and our
7143 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7144 * function also has additional necessary side-effects, like setting various
7145 * vcpu->arch fields.
7146 */
7147static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7148{
7149 struct vcpu_vmx *vmx = to_vmx(vcpu);
7150 u32 exec_control;
7151
7152 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7153 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7154 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7155 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7156 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7157 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7158 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7159 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7160 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7161 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7162 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7163 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7164 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7165 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7166 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7167 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7168 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7169 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7170 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7171 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7172 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7173 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7174 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7175 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7176 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7177 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7178 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7179 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7180 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7181 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7182 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7183 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7184 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7185 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7186 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7187 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7188
7189 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7190 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7191 vmcs12->vm_entry_intr_info_field);
7192 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7193 vmcs12->vm_entry_exception_error_code);
7194 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7195 vmcs12->vm_entry_instruction_len);
7196 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7197 vmcs12->guest_interruptibility_info);
fe3ef05c 7198 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7199 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7200 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7201 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7202 vmcs12->guest_pending_dbg_exceptions);
7203 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7204 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7205
7206 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7207
7208 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7209 (vmcs_config.pin_based_exec_ctrl |
7210 vmcs12->pin_based_vm_exec_control));
7211
0238ea91
JK		 7212 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7213 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7214 vmcs12->vmx_preemption_timer_value);
7215
fe3ef05c
NHE		 7216 /*
7217 * Whether page-faults are trapped is determined by a combination of
7218 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7219 * If enable_ept, L0 doesn't care about page faults and we should
7220 * set all of these to L1's desires. However, if !enable_ept, L0 does
7221 * care about (at least some) page faults, and because it is not easy
7222 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7223 * to exit on each and every L2 page fault. This is done by setting
7224 * MASK=MATCH=0 and (see below) EB.PF=1.
7225 * Note that below we don't need special code to set EB.PF beyond the
7226 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7227 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7228 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7229 *
7230 * A problem with this approach (when !enable_ept) is that L1 may be
7231 * injected with more page faults than it asked for. This could have
7232 * caused problems, but in practice existing hypervisors don't care.
7233 * To fix this, we will need to emulate the PFEC checking (on the L1
7234 * page tables), using walk_addr(), when injecting PFs to L1.
7235 */
7236 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7237 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7238 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7239 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7240
7241 if (cpu_has_secondary_exec_ctrls()) {
7242 u32 exec_control = vmx_secondary_exec_control(vmx);
7243 if (!vmx->rdtscp_enabled)
7244 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7245 /* Take the following fields only from vmcs12 */
7246 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7247 if (nested_cpu_has(vmcs12,
7248 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7249 exec_control |= vmcs12->secondary_vm_exec_control;
7250
7251 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7252 /*
7253 * Translate L1 physical address to host physical
7254 * address for vmcs02. Keep the page pinned, so this
7255 * physical address remains valid. We keep a reference
7256 * to it so we can release it later.
7257 */
7258 if (vmx->nested.apic_access_page) /* shouldn't happen */
7259 nested_release_page(vmx->nested.apic_access_page);
7260 vmx->nested.apic_access_page =
7261 nested_get_page(vcpu, vmcs12->apic_access_addr);
7262 /*
7263 * If translation failed, no matter: This feature asks
7264 * to exit when accessing the given address, and if it
7265 * can never be accessed, this feature won't do
7266 * anything anyway.
7267 */
7268 if (!vmx->nested.apic_access_page)
7269 exec_control &=
7270 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7271 else
7272 vmcs_write64(APIC_ACCESS_ADDR,
7273 page_to_phys(vmx->nested.apic_access_page));
7274 }
7275
7276 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7277 }
7278
7279
7280 /*
7281 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7282 * Some constant fields are set here by vmx_set_constant_host_state().
7283 * Other fields are different per CPU, and will be set later when
7284 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7285 */
a547c6db 7286 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7287
7288 /*
7289 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7290 * entry, but only if the current (host) sp changed from the value
7291 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7292 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7293 * here we just force the write to happen on entry.
7294 */
7295 vmx->host_rsp = 0;
7296
7297 exec_control = vmx_exec_control(vmx); /* L0's desires */
7298 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7299 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7300 exec_control &= ~CPU_BASED_TPR_SHADOW;
7301 exec_control |= vmcs12->cpu_based_vm_exec_control;
7302 /*
7303 * Merging of IO and MSR bitmaps not currently supported.
7304 * Rather, exit every time.
7305 */
7306 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7307 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7308 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7309
7310 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7311
7312 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7313 * bitwise-or of what L1 wants to trap for L2, and what we want to
7314 * trap. Note that CR0.TS also needs updating - we do this later.
7315 */
7316 update_exception_bitmap(vcpu);
7317 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7318 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7319
7320 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7321 vmcs_write32(VM_EXIT_CONTROLS,
7322 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7323 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7324 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7325
7326 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7327 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7328 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7329 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7330
7331
7332 set_cr4_guest_host_mask(vmx);
7333
27fc51b2
NHE		 7334 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7335 vmcs_write64(TSC_OFFSET,
7336 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7337 else
7338 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7339
7340 if (enable_vpid) {
7341 /*
7342 * Trivially support vpid by letting L2s share their parent
7343 * L1's vpid. TODO: move to a more elaborate solution, giving
7344 * each L2 its own vpid and exposing the vpid feature to L1.
7345 */
7346 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7347 vmx_flush_tlb(vcpu);
7348 }
7349
7350 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7351 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7352 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7353 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7354 else
7355 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7356 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7357 vmx_set_efer(vcpu, vcpu->arch.efer);
7358
7359 /*
7360 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7361 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7362 * The CR0_READ_SHADOW is what L2 should have expected to read given
7363 * the specifications by L1; It's not enough to take
7364 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7365 * have more bits than L1 expected.
7366 */
7367 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7368 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7369
7370 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7371 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7372
7373 /* shadow page tables on either EPT or shadow page tables */
7374 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7375 kvm_mmu_reset_context(vcpu);
7376
7377 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7378 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7379}
7380
cd232ad0
NHE		 7381/*
7382 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7383 * for running an L2 nested guest.
7384 */
7385static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7386{
7387 struct vmcs12 *vmcs12;
7388 struct vcpu_vmx *vmx = to_vmx(vcpu);
7389 int cpu;
7390 struct loaded_vmcs *vmcs02;
7391
7392 if (!nested_vmx_check_permission(vcpu) ||
7393 !nested_vmx_check_vmcs12(vcpu))
7394 return 1;
7395
7396 skip_emulated_instruction(vcpu);
7397 vmcs12 = get_vmcs12(vcpu);
7398
7c177938
NHE		 7399 /*
7400 * The nested entry process starts with enforcing various prerequisites
7401 * on vmcs12 as required by the Intel SDM, and act appropriately when
7402 * they fail: As the SDM explains, some conditions should cause the
7403 * instruction to fail, while others will cause the instruction to seem
7404 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7405 * To speed up the normal (success) code path, we should avoid checking
7406 * for misconfigurations which will anyway be caught by the processor
7407 * when using the merged vmcs02.
7408 */
7409 if (vmcs12->launch_state == launch) {
7410 nested_vmx_failValid(vcpu,
7411 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7412 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7413 return 1;
7414 }
7415
26539bd0
PB		 7416 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7417 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7418 return 1;
7419 }
7420
7c177938
NHE		 7421 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7422 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7423 /*TODO: Also verify bits beyond physical address width are 0*/
7424 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7425 return 1;
7426 }
7427
7428 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7429 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7430 /*TODO: Also verify bits beyond physical address width are 0*/
7431 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7432 return 1;
7433 }
7434
7435 if (vmcs12->vm_entry_msr_load_count > 0 ||
7436 vmcs12->vm_exit_msr_load_count > 0 ||
7437 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7438 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7439 __func__);
7c177938
NHE		 7440 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7441 return 1;
7442 }
7443
7444 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7445 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7446 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7447 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7448 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7449 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7450 !vmx_control_verify(vmcs12->vm_exit_controls,
7451 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7452 !vmx_control_verify(vmcs12->vm_entry_controls,
7453 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7454 {
7455 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7456 return 1;
7457 }
7458
7459 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7460 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7461 nested_vmx_failValid(vcpu,
7462 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7463 return 1;
7464 }
7465
7466 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7467 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7468 nested_vmx_entry_failure(vcpu, vmcs12,
7469 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7470 return 1;
7471 }
7472 if (vmcs12->vmcs_link_pointer != -1ull) {
7473 nested_vmx_entry_failure(vcpu, vmcs12,
7474 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7475 return 1;
7476 }
7477
7478 /*
7479 * We're finally done with prerequisite checking, and can start with
7480 * the nested entry.
7481 */
7482
cd232ad0
NHE		 7483 vmcs02 = nested_get_current_vmcs02(vmx);
7484 if (!vmcs02)
7485 return -ENOMEM;
7486
7487 enter_guest_mode(vcpu);
7488
7489 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7490
7491 cpu = get_cpu();
7492 vmx->loaded_vmcs = vmcs02;
7493 vmx_vcpu_put(vcpu);
7494 vmx_vcpu_load(vcpu, cpu);
7495 vcpu->cpu = cpu;
7496 put_cpu();
7497
36c3cc42
JK		 7498 vmx_segment_cache_clear(vmx);
7499
cd232ad0
NHE		 7500 vmcs12->launch_state = 1;
7501
7502 prepare_vmcs02(vcpu, vmcs12);
7503
7504 /*
7505 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7506 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7507 * returned as far as L1 is concerned. It will only return (and set
7508 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7509 */
7510 return 1;
7511}
7512
4704d0be
NHE		 7513/*
7514 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7515 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7516 * This function returns the new value we should put in vmcs12.guest_cr0.
7517 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7518 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7519 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7520 * didn't trap the bit, because if L1 did, so would L0).
7521 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7522 * been modified by L2, and L1 knows it. So just leave the old value of
7523 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7524 * isn't relevant, because if L0 traps this bit it can set it to anything.
7525 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7526 * changed these bits, and therefore they need to be updated, but L0
7527 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7528 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7529 */
7530static inline unsigned long
7531vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7532{
7533 return
7534 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7535 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7536 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7537 vcpu->arch.cr0_guest_owned_bits));
7538}
7539
7540static inline unsigned long
7541vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7542{
7543 return
7544 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7545 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7546 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7547 vcpu->arch.cr4_guest_owned_bits));
7548}
7549
5f3d5799
JK		 7550static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7551 struct vmcs12 *vmcs12)
7552{
7553 u32 idt_vectoring;
7554 unsigned int nr;
7555
7556 if (vcpu->arch.exception.pending) {
7557 nr = vcpu->arch.exception.nr;
7558 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7559
7560 if (kvm_exception_is_soft(nr)) {
7561 vmcs12->vm_exit_instruction_len =
7562 vcpu->arch.event_exit_inst_len;
7563 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7564 } else
7565 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7566
7567 if (vcpu->arch.exception.has_error_code) {
7568 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7569 vmcs12->idt_vectoring_error_code =
7570 vcpu->arch.exception.error_code;
7571 }
7572
7573 vmcs12->idt_vectoring_info_field = idt_vectoring;
7574 } else if (vcpu->arch.nmi_pending) {
7575 vmcs12->idt_vectoring_info_field =
7576 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7577 } else if (vcpu->arch.interrupt.pending) {
7578 nr = vcpu->arch.interrupt.nr;
7579 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7580
7581 if (vcpu->arch.interrupt.soft) {
7582 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7583 vmcs12->vm_entry_instruction_len =
7584 vcpu->arch.event_exit_inst_len;
7585 } else
7586 idt_vectoring |= INTR_TYPE_EXT_INTR;
7587
7588 vmcs12->idt_vectoring_info_field = idt_vectoring;
7589 }
7590}
7591
4704d0be
NHE		 7592/*
7593 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7594 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7595 * and this function updates it to reflect the changes to the guest state while
7596 * L2 was running (and perhaps made some exits which were handled directly by L0
7597 * without going back to L1), and to reflect the exit reason.
7598 * Note that we do not have to copy here all VMCS fields, just those that
7599 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7600 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7601 * which already writes to vmcs12 directly.
7602 */
733568f9 7603static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7604{
7605 /* update guest state fields: */
7606 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7607 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7608
7609 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7610 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7611 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7612 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7613
7614 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7615 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7616 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7617 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7618 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7619 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7620 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7621 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7622 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7623 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7624 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7625 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7626 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7627 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7628 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7629 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7630 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7631 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7632 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7633 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7634 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7635 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7636 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7637 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7638 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7639 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7640 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7641 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7642 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7643 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7644 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7645 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7646 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7647 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7648 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7649 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7650
4704d0be
NHE		 7651 vmcs12->guest_interruptibility_info =
7652 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7653 vmcs12->guest_pending_dbg_exceptions =
7654 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7655
c18911a2
JK		 7656 vmcs12->vm_entry_controls =
7657 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7658 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7659
4704d0be
NHE		 7660 /* TODO: These cannot have changed unless we have MSR bitmaps and
7661 * the relevant bit asks not to trap the change */
7662 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7663 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7664 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7665 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7666 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7667 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7668
7669 /* update exit information fields: */
7670
957c897e 7671 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7672 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7673
7674 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7675 if ((vmcs12->vm_exit_intr_info &
7676 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7677 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7678 vmcs12->vm_exit_intr_error_code =
7679 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7680 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7681 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7682 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7683
5f3d5799
JK		 7684 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7685 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7686 * instead of reading the real value. */
4704d0be 7687 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7688
7689 /*
7690 * Transfer the event that L0 or L1 may wanted to inject into
7691 * L2 to IDT_VECTORING_INFO_FIELD.
7692 */
7693 vmcs12_save_pending_event(vcpu, vmcs12);
7694 }
7695
7696 /*
7697 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7698 * preserved above and would only end up incorrectly in L1.
7699 */
7700 vcpu->arch.nmi_injected = false;
7701 kvm_clear_exception_queue(vcpu);
7702 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7703}
7704
7705/*
7706 * A part of what we need to when the nested L2 guest exits and we want to
7707 * run its L1 parent, is to reset L1's guest state to the host state specified
7708 * in vmcs12.
7709 * This function is to be called not only on normal nested exit, but also on
7710 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7711 * Failures During or After Loading Guest State").
7712 * This function should be called when the active VMCS is L1's (vmcs01).
7713 */
733568f9
JK		 7714static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7715 struct vmcs12 *vmcs12)
4704d0be
NHE		 7716{
7717 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7718 vcpu->arch.efer = vmcs12->host_ia32_efer;
7719 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7720 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7721 else
7722 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7723 vmx_set_efer(vcpu, vcpu->arch.efer);
7724
7725 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7726 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7727 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7728 /*
7729 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7730 * actually changed, because it depends on the current state of
7731 * fpu_active (which may have changed).
7732 * Note that vmx_set_cr0 refers to efer set above.
7733 */
7734 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7735 /*
7736 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7737 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7738 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7739 */
7740 update_exception_bitmap(vcpu);
7741 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7742 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7743
7744 /*
7745 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7746 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7747 */
7748 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7749 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7750
7751 /* shadow page tables on either EPT or shadow page tables */
7752 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7753 kvm_mmu_reset_context(vcpu);
7754
7755 if (enable_vpid) {
7756 /*
7757 * Trivially support vpid by letting L2s share their parent
7758 * L1's vpid. TODO: move to a more elaborate solution, giving
7759 * each L2 its own vpid and exposing the vpid feature to L1.
7760 */
7761 vmx_flush_tlb(vcpu);
7762 }
7763
7764
7765 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7766 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7767 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7768 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7769 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7770 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7771 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7772 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7773 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7774 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7775 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7776 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7777 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7778 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7779 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7780
7781 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7782 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7783 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7784 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7785 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7786
7787 kvm_set_dr(vcpu, 7, 0x400);
7788 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7789}
7790
7791/*
7792 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7793 * and modify vmcs12 to make it see what it would expect to see there if
7794 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7795 */
7796static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7797{
7798 struct vcpu_vmx *vmx = to_vmx(vcpu);
7799 int cpu;
7800 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7801
5f3d5799
JK		 7802 /* trying to cancel vmlaunch/vmresume is a bug */
7803 WARN_ON_ONCE(vmx->nested.nested_run_pending);
7804
4704d0be
NHE		 7805 leave_guest_mode(vcpu);
7806 prepare_vmcs12(vcpu, vmcs12);
7807
7808 cpu = get_cpu();
7809 vmx->loaded_vmcs = &vmx->vmcs01;
7810 vmx_vcpu_put(vcpu);
7811 vmx_vcpu_load(vcpu, cpu);
7812 vcpu->cpu = cpu;
7813 put_cpu();
7814
36c3cc42
JK		 7815 vmx_segment_cache_clear(vmx);
7816
4704d0be
NHE		 7817 /* if no vmcs02 cache requested, remove the one we used */
7818 if (VMCS02_POOL_SIZE == 0)
7819 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7820
7821 load_vmcs12_host_state(vcpu, vmcs12);
7822
27fc51b2 7823 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7824 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7825
7826 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7827 vmx->host_rsp = 0;
7828
7829 /* Unpin physical memory we referred to in vmcs02 */
7830 if (vmx->nested.apic_access_page) {
7831 nested_release_page(vmx->nested.apic_access_page);
7832 vmx->nested.apic_access_page = 0;
7833 }
7834
7835 /*
7836 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7837 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7838 * success or failure flag accordingly.
7839 */
7840 if (unlikely(vmx->fail)) {
7841 vmx->fail = 0;
7842 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7843 } else
7844 nested_vmx_succeed(vcpu);
7845}
7846
7c177938
NHE		 7847/*
7848 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7849 * 23.7 "VM-entry failures during or after loading guest state" (this also
7850 * lists the acceptable exit-reason and exit-qualification parameters).
7851 * It should only be called before L2 actually succeeded to run, and when
7852 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7853 */
7854static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7855 struct vmcs12 *vmcs12,
7856 u32 reason, unsigned long qualification)
7857{
7858 load_vmcs12_host_state(vcpu, vmcs12);
7859 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7860 vmcs12->exit_qualification = qualification;
7861 nested_vmx_succeed(vcpu);
7862}
7863
8a76d7f2
JR		 7864static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7865 struct x86_instruction_info *info,
7866 enum x86_intercept_stage stage)
7867{
7868 return X86EMUL_CONTINUE;
7869}
7870
cbdd1bea 7871static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7872 .cpu_has_kvm_support = cpu_has_kvm_support,
7873 .disabled_by_bios = vmx_disabled_by_bios,
7874 .hardware_setup = hardware_setup,
7875 .hardware_unsetup = hardware_unsetup,
002c7f7c 7876 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7877 .hardware_enable = hardware_enable,
7878 .hardware_disable = hardware_disable,
04547156 7879 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7880
7881 .vcpu_create = vmx_create_vcpu,
7882 .vcpu_free = vmx_free_vcpu,
04d2cc77 7883 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7884
04d2cc77 7885 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7886 .vcpu_load = vmx_vcpu_load,
7887 .vcpu_put = vmx_vcpu_put,
7888
c8639010 7889 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7890 .get_msr = vmx_get_msr,
7891 .set_msr = vmx_set_msr,
7892 .get_segment_base = vmx_get_segment_base,
7893 .get_segment = vmx_get_segment,
7894 .set_segment = vmx_set_segment,
2e4d2653 7895 .get_cpl = vmx_get_cpl,
6aa8b732 7896 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7897 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7898 .decache_cr3 = vmx_decache_cr3,
25c4c276 7899 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7900 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7901 .set_cr3 = vmx_set_cr3,
7902 .set_cr4 = vmx_set_cr4,
6aa8b732 7903 .set_efer = vmx_set_efer,
6aa8b732
AK		 7904 .get_idt = vmx_get_idt,
7905 .set_idt = vmx_set_idt,
7906 .get_gdt = vmx_get_gdt,
7907 .set_gdt = vmx_set_gdt,
020df079 7908 .set_dr7 = vmx_set_dr7,
5fdbf976 7909 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7910 .get_rflags = vmx_get_rflags,
7911 .set_rflags = vmx_set_rflags,
ebcbab4c 7912 .fpu_activate = vmx_fpu_activate,
02daab21 7913 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7914
7915 .tlb_flush = vmx_flush_tlb,
6aa8b732 7916
6aa8b732 7917 .run = vmx_vcpu_run,
6062d012 7918 .handle_exit = vmx_handle_exit,
6aa8b732 7919 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7920 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7921 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7922 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7923 .set_irq = vmx_inject_irq,
95ba8273 7924 .set_nmi = vmx_inject_nmi,
298101da 7925 .queue_exception = vmx_queue_exception,
b463a6f7 7926 .cancel_injection = vmx_cancel_injection,
78646121 7927 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7928 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7929 .get_nmi_mask = vmx_get_nmi_mask,
7930 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7931 .enable_nmi_window = enable_nmi_window,
7932 .enable_irq_window = enable_irq_window,
7933 .update_cr8_intercept = update_cr8_intercept,
8d14695f 7934 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 7935 .vm_has_apicv = vmx_vm_has_apicv,
7936 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7937 .hwapic_irr_update = vmx_hwapic_irr_update,
7938 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 7939 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7940 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7941
cbc94022 7942 .set_tss_addr = vmx_set_tss_addr,
67253af5 7943 .get_tdp_level = get_ept_level,
4b12f0de 7944 .get_mt_mask = vmx_get_mt_mask,
229456fc 7945
586f9607 7946 .get_exit_info = vmx_get_exit_info,
586f9607 7947
17cc3935 7948 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7949
7950 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7951
7952 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7953 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7954
7955 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7956
7957 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7958
4051b188 7959 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7960 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7961 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7962 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7963 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7964 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7965
7966 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7967
7968 .check_intercept = vmx_check_intercept,
a547c6db 7969 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 7970};
7971
7972static int __init vmx_init(void)
7973{
8d14695f 7974 int r, i, msr;
26bb0981
AK		 7975
7976 rdmsrl_safe(MSR_EFER, &host_efer);
7977
7978 for (i = 0; i < NR_VMX_MSR; ++i)
7979 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7980
3e7c73e9 7981 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7982 if (!vmx_io_bitmap_a)
7983 return -ENOMEM;
7984
2106a548
GC		 7985 r = -ENOMEM;
7986
3e7c73e9 7987 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7988 if (!vmx_io_bitmap_b)
fdef3ad1 7989 goto out;
fdef3ad1 7990
5897297b 7991 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7992 if (!vmx_msr_bitmap_legacy)
25c5f225 7993 goto out1;
2106a548 7994
8d14695f
YZ		 7995 vmx_msr_bitmap_legacy_x2apic =
7996 (unsigned long *)__get_free_page(GFP_KERNEL);
7997 if (!vmx_msr_bitmap_legacy_x2apic)
7998 goto out2;
25c5f225 7999
5897297b 8000 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8001 if (!vmx_msr_bitmap_longmode)
8d14695f 8002 goto out3;
2106a548 8003
8d14695f
YZ		 8004 vmx_msr_bitmap_longmode_x2apic =
8005 (unsigned long *)__get_free_page(GFP_KERNEL);
8006 if (!vmx_msr_bitmap_longmode_x2apic)
8007 goto out4;
4607c2d7
AG		 8008 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8009 if (!vmx_vmread_bitmap)
8010 goto out5;
8011
8012 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8013 if (!vmx_vmwrite_bitmap)
8014 goto out6;
8015
8016 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8017 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8018 /* shadowed read/write fields */
8019 for (i = 0; i < max_shadow_read_write_fields; i++) {
8020 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8021 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8022 }
8023 /* shadowed read only fields */
8024 for (i = 0; i < max_shadow_read_only_fields; i++)
8025 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8026
fdef3ad1
HQ		 8027 /*
8028 * Allow direct access to the PC debug port (it is often used for I/O
8029 * delays, but the vmexits simply slow things down).
8030 */
3e7c73e9
AK		 8031 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8032 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8033
3e7c73e9 8034 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8035
5897297b
AK		 8036 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8037 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8038
2384d2b3
SY		 8039 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8040
0ee75bea
AK		 8041 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8042 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8043 if (r)
4607c2d7 8044 goto out7;
25c5f225 8045
8f536b76
ZY		 8046#ifdef CONFIG_KEXEC
8047 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8048 crash_vmclear_local_loaded_vmcss);
8049#endif
8050
5897297b
AK		 8051 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8052 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8053 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8054 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8055 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8056 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8057 memcpy(vmx_msr_bitmap_legacy_x2apic,
8058 vmx_msr_bitmap_legacy, PAGE_SIZE);
8059 memcpy(vmx_msr_bitmap_longmode_x2apic,
8060 vmx_msr_bitmap_longmode, PAGE_SIZE);
8061
01e439be 8062 if (enable_apicv) {
8d14695f
YZ		 8063 for (msr = 0x800; msr <= 0x8ff; msr++)
8064 vmx_disable_intercept_msr_read_x2apic(msr);
8065
8066 /* According SDM, in x2apic mode, the whole id reg is used.
8067 * But in KVM, it only use the highest eight bits. Need to
8068 * intercept it */
8069 vmx_enable_intercept_msr_read_x2apic(0x802);
8070 /* TMCCT */
8071 vmx_enable_intercept_msr_read_x2apic(0x839);
8072 /* TPR */
8073 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8074 /* EOI */
8075 vmx_disable_intercept_msr_write_x2apic(0x80b);
8076 /* SELF-IPI */
8077 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8078 }
fdef3ad1 8079
089d034e 8080 if (enable_ept) {
3f6d8c8a
XH		 8081 kvm_mmu_set_mask_ptes(0ull,
8082 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8083 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8084 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8085 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8086 kvm_enable_tdp();
8087 } else
8088 kvm_disable_tdp();
1439442c 8089
fdef3ad1
HQ		 8090 return 0;
8091
4607c2d7
AG		 8092out7:
8093 free_page((unsigned long)vmx_vmwrite_bitmap);
8094out6:
8095 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8096out5:
8097 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8098out4:
5897297b 8099 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8100out3:
8101 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8102out2:
5897297b 8103 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8104out1:
3e7c73e9 8105 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8106out:
3e7c73e9 8107 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8108 return r;
6aa8b732
AK		 8109}
8110
8111static void __exit vmx_exit(void)
8112{
8d14695f
YZ		 8113 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8114 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8115 free_page((unsigned long)vmx_msr_bitmap_legacy);
8116 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8117 free_page((unsigned long)vmx_io_bitmap_b);
8118 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8119 free_page((unsigned long)vmx_vmwrite_bitmap);
8120 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8121
8f536b76
ZY		 8122#ifdef CONFIG_KEXEC
8123 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8124 synchronize_rcu();
8125#endif
8126
cb498ea2 8127 kvm_exit();
6aa8b732
AK		 8128}
8129
8130module_init(vmx_init)
8131module_exit(vmx_exit)
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