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KVM: x86: Add code to track call origin for msr assignment
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
83287ea4
AK		 130extern const ulong vmx_return;
131
8bf00a52 132#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 133#define VMCS02_POOL_SIZE 1
61d2ef2c 134
a2fa3e9f
GH		 135struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139};
140
d462b819
NHE		 141/*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151};
152
26bb0981
AK		 153struct shared_msr_entry {
154 unsigned index;
155 u64 data;
d5696725 156 u64 mask;
26bb0981
AK		 157};
158
a9d30f33
NHE		 159/*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
22bd0358 172typedef u64 natural_width;
a9d30f33
NHE		 173struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
22bd0358 179
27d6c865
NHE		 180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
22bd0358
NHE		 183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a2fa3e9f 381#ifdef CONFIG_X86_64
44ea2b17
AK		 382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
a2fa3e9f 384#endif
d462b819
NHE		 385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
a2fa3e9f
GH		 398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 401#ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403#endif
152d3f2f
LV		 404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
d77c26fc 406 } host_state;
9c8cba37 407 struct {
7ffd92c5 408 int vm86_active;
78ac8b47 409 ulong save_rflags;
f5f7b2fe
AK		 410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
f5f7b2fe 419 } seg[8];
2fb92db1 420 } segment_cache;
2384d2b3 421 int vpid;
04fa4d32 422 bool emulation_required;
3b86cd99
JK		 423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
a0861c02 428 u32 exit_reason;
4e47c7a6
SY		 429
430 bool rdtscp_enabled;
ec378aee
NHE		 431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
a2fa3e9f
GH		 434};
435
2fb92db1
AK		 436enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443};
444
a2fa3e9f
GH		 445static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446{
fb3f0f51 447 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 448}
449
22bd0358
NHE		 450#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
772e0318 455static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583};
584static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586static inline short vmcs_field_to_offset(unsigned long field)
587{
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591}
592
a9d30f33
NHE		 593static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594{
595 return to_vmx(vcpu)->nested.current_vmcs12;
596}
597
598static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599{
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 601 if (is_error_page(page))
a9d30f33 602 return NULL;
32cad84f 603
a9d30f33
NHE		 604 return page;
605}
606
607static void nested_release_page(struct page *page)
608{
609 kvm_release_page_dirty(page);
610}
611
612static void nested_release_page_clean(struct page *page)
613{
614 kvm_release_page_clean(page);
615}
616
4e1096d2 617static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 618static void kvm_cpu_vmxon(u64 addr);
619static void kvm_cpu_vmxoff(void);
aff48baa 620static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 621static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 622static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
75880a01 626
6aa8b732
AK		 627static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 629/*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 634static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 635
3e7c73e9
AK		 636static unsigned long *vmx_io_bitmap_a;
637static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 638static unsigned long *vmx_msr_bitmap_legacy;
639static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 640
110312c8 641static bool cpu_has_load_ia32_efer;
8bf00a52 642static bool cpu_has_load_perf_global_ctrl;
110312c8 643
2384d2b3
SY		 644static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645static DEFINE_SPINLOCK(vmx_vpid_lock);
646
1c3d14fe 647static struct vmcs_config {
6aa8b732
AK		 648 int size;
649 int order;
650 u32 revision_id;
1c3d14fe
YS		 651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
f78e0e2e 653 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656} vmcs_config;
6aa8b732 657
efff9e53 658static struct vmx_capability {
d56f546d
SY		 659 u32 ept;
660 u32 vpid;
661} vmx_capability;
662
6aa8b732
AK		 663#define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
772e0318 671static const struct kvm_vmx_segment_field {
6aa8b732
AK		 672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676} kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685};
686
26bb0981
AK		 687static u64 host_efer;
688
6de4f3ad
AK		 689static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
4d56c8a7 691/*
8c06585d 692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 693 * away by decrementing the array size.
694 */
6aa8b732 695static const u32 vmx_msr_index[] = {
05b3e0c2 696#ifdef CONFIG_X86_64
44ea2b17 697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 698#endif
8c06585d 699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 700};
9d8f549d 701#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 702
31299944 703static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 708}
709
31299944 710static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 711{
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 715}
716
31299944 717static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 718{
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 722}
723
31299944 724static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 725{
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728}
729
31299944 730static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735}
736
31299944 737static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 738{
04547156 739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 740}
741
31299944 742static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 743{
04547156 744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 745}
746
31299944 747static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 748{
04547156 749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 750}
751
31299944 752static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 753{
04547156
SY		 754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 756}
757
774ead3a 758static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762}
763
764static inline bool cpu_has_vmx_flexpriority(void)
765{
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 768}
769
e799794e
MT		 770static inline bool cpu_has_vmx_ept_execute_only(void)
771{
31299944 772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 773}
774
775static inline bool cpu_has_vmx_eptp_uncacheable(void)
776{
31299944 777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 778}
779
780static inline bool cpu_has_vmx_eptp_writeback(void)
781{
31299944 782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 783}
784
785static inline bool cpu_has_vmx_ept_2m_page(void)
786{
31299944 787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 788}
789
878403b7
SY		 790static inline bool cpu_has_vmx_ept_1g_page(void)
791{
31299944 792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 793}
794
4bc9b982
SY		 795static inline bool cpu_has_vmx_ept_4levels(void)
796{
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798}
799
83c3a331
XH		 800static inline bool cpu_has_vmx_ept_ad_bits(void)
801{
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803}
804
31299944 805static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 806{
31299944 807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_invept_context(void)
d56f546d 811{
31299944 812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 813}
814
31299944 815static inline bool cpu_has_vmx_invept_global(void)
d56f546d 816{
31299944 817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 818}
819
518c8aee
GJ		 820static inline bool cpu_has_vmx_invvpid_single(void)
821{
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823}
824
b9d762fa
GJ		 825static inline bool cpu_has_vmx_invvpid_global(void)
826{
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828}
829
31299944 830static inline bool cpu_has_vmx_ept(void)
d56f546d 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840}
841
31299944 842static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 843{
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846}
847
31299944 848static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 849{
6d3e435e 850 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 851}
852
31299944 853static inline bool cpu_has_vmx_vpid(void)
2384d2b3 854{
04547156
SY		 855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 857}
858
31299944 859static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 860{
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863}
864
ad756a16
MJ		 865static inline bool cpu_has_vmx_invpcid(void)
866{
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869}
870
31299944 871static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 872{
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874}
875
f5f48ee1
SY		 876static inline bool cpu_has_vmx_wbinvd_exit(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880}
881
04547156
SY		 882static inline bool report_flexpriority(void)
883{
884 return flexpriority_enabled;
885}
886
fe3ef05c
NHE		 887static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888{
889 return vmcs12->cpu_based_vm_exec_control & bit;
890}
891
892static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893{
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897}
898
644d711a
NHE		 899static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901{
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903}
904
905static inline bool is_exception(u32 intr_info)
906{
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909}
910
911static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 912static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
8b9cf98c 916static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 917{
918 int i;
919
a2fa3e9f 920 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 922 return i;
923 return -1;
924}
925
2384d2b3
SY		 926static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927{
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
4ecac3fd 934 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938}
939
1439442c
SY		 940static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941{
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
4ecac3fd 946 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950}
951
26bb0981 952static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 953{
954 int i;
955
8b9cf98c 956 i = __find_msr_index(vmx, msr);
a75beee6 957 if (i >= 0)
a2fa3e9f 958 return &vmx->guest_msrs[i];
8b6d44c7 959 return NULL;
7725f0ba
AK		 960}
961
6aa8b732
AK		 962static void vmcs_clear(struct vmcs *vmcs)
963{
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
4ecac3fd 967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973}
974
d462b819
NHE		 975static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976{
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980}
981
7725b894
DX		 982static void vmcs_load(struct vmcs *vmcs)
983{
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 989 : "cc", "memory");
990 if (error)
2844d849 991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 992 vmcs, phys_addr);
993}
994
d462b819 995static void __loaded_vmcs_clear(void *arg)
6aa8b732 996{
d462b819 997 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 998 int cpu = raw_smp_processor_id();
6aa8b732 999
d462b819
NHE		 1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1003 per_cpu(current_vmcs, cpu) = NULL;
d462b819 1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1005
1006 /*
1007 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1008 * is before setting loaded_vmcs->vcpu to -1 which is done in
1009 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1010 * then adds the vmcs into percpu list before it is deleted.
1011 */
1012 smp_wmb();
1013
d462b819 1014 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1015}
1016
d462b819 1017static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1018{
e6c7d321
XG		 1019 int cpu = loaded_vmcs->cpu;
1020
1021 if (cpu != -1)
1022 smp_call_function_single(cpu,
1023 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1024}
1025
1760dd49 1026static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1027{
1028 if (vmx->vpid == 0)
1029 return;
1030
518c8aee
GJ		 1031 if (cpu_has_vmx_invvpid_single())
1032 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1033}
1034
b9d762fa
GJ		 1035static inline void vpid_sync_vcpu_global(void)
1036{
1037 if (cpu_has_vmx_invvpid_global())
1038 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1039}
1040
1041static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1042{
1043 if (cpu_has_vmx_invvpid_single())
1760dd49 1044 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1045 else
1046 vpid_sync_vcpu_global();
1047}
1048
1439442c
SY		 1049static inline void ept_sync_global(void)
1050{
1051 if (cpu_has_vmx_invept_global())
1052 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1053}
1054
1055static inline void ept_sync_context(u64 eptp)
1056{
089d034e 1057 if (enable_ept) {
1439442c
SY		 1058 if (cpu_has_vmx_invept_context())
1059 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1060 else
1061 ept_sync_global();
1062 }
1063}
1064
1065static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1066{
089d034e 1067 if (enable_ept) {
1439442c
SY		 1068 if (cpu_has_vmx_invept_individual_addr())
1069 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1070 eptp, gpa);
1071 else
1072 ept_sync_context(eptp);
1073 }
1074}
1075
96304217 1076static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1077{
5e520e62 1078 unsigned long value;
6aa8b732 1079
5e520e62
AK		 1080 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1081 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1082 return value;
1083}
1084
96304217 1085static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1086{
1087 return vmcs_readl(field);
1088}
1089
96304217 1090static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1091{
1092 return vmcs_readl(field);
1093}
1094
96304217 1095static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1096{
05b3e0c2 1097#ifdef CONFIG_X86_64
6aa8b732
AK		 1098 return vmcs_readl(field);
1099#else
1100 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1101#endif
1102}
1103
e52de1b8
AK		 1104static noinline void vmwrite_error(unsigned long field, unsigned long value)
1105{
1106 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1107 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1108 dump_stack();
1109}
1110
6aa8b732
AK		 1111static void vmcs_writel(unsigned long field, unsigned long value)
1112{
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1116 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1117 if (unlikely(error))
1118 vmwrite_error(field, value);
6aa8b732
AK		 1119}
1120
1121static void vmcs_write16(unsigned long field, u16 value)
1122{
1123 vmcs_writel(field, value);
1124}
1125
1126static void vmcs_write32(unsigned long field, u32 value)
1127{
1128 vmcs_writel(field, value);
1129}
1130
1131static void vmcs_write64(unsigned long field, u64 value)
1132{
6aa8b732 1133 vmcs_writel(field, value);
7682f2d0 1134#ifndef CONFIG_X86_64
6aa8b732
AK		 1135 asm volatile ("");
1136 vmcs_writel(field+1, value >> 32);
1137#endif
1138}
1139
2ab455cc
AL		 1140static void vmcs_clear_bits(unsigned long field, u32 mask)
1141{
1142 vmcs_writel(field, vmcs_readl(field) & ~mask);
1143}
1144
1145static void vmcs_set_bits(unsigned long field, u32 mask)
1146{
1147 vmcs_writel(field, vmcs_readl(field) | mask);
1148}
1149
2fb92db1
AK		 1150static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1151{
1152 vmx->segment_cache.bitmask = 0;
1153}
1154
1155static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1156 unsigned field)
1157{
1158 bool ret;
1159 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1160
1161 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1162 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1163 vmx->segment_cache.bitmask = 0;
1164 }
1165 ret = vmx->segment_cache.bitmask & mask;
1166 vmx->segment_cache.bitmask |= mask;
1167 return ret;
1168}
1169
1170static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1171{
1172 u16 *p = &vmx->segment_cache.seg[seg].selector;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1175 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1176 return *p;
1177}
1178
1179static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1180{
1181 ulong *p = &vmx->segment_cache.seg[seg].base;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1184 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1185 return *p;
1186}
1187
1188static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1189{
1190 u32 *p = &vmx->segment_cache.seg[seg].limit;
1191
1192 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1193 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1194 return *p;
1195}
1196
1197static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1198{
1199 u32 *p = &vmx->segment_cache.seg[seg].ar;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1202 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1203 return *p;
1204}
1205
abd3f2d6
AK		 1206static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1207{
1208 u32 eb;
1209
fd7373cc
JK		 1210 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1211 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1212 if ((vcpu->guest_debug &
1213 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1214 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1215 eb |= 1u << BP_VECTOR;
7ffd92c5 1216 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1217 eb = ~0;
089d034e 1218 if (enable_ept)
1439442c 1219 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1220 if (vcpu->fpu_active)
1221 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1222
1223 /* When we are running a nested L2 guest and L1 specified for it a
1224 * certain exception bitmap, we must trap the same exceptions and pass
1225 * them to L1. When running L2, we will only handle the exceptions
1226 * specified above if L1 did not want them.
1227 */
1228 if (is_guest_mode(vcpu))
1229 eb |= get_vmcs12(vcpu)->exception_bitmap;
1230
abd3f2d6
AK		 1231 vmcs_write32(EXCEPTION_BITMAP, eb);
1232}
1233
8bf00a52
GN		 1234static void clear_atomic_switch_msr_special(unsigned long entry,
1235 unsigned long exit)
1236{
1237 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1238 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1239}
1240
61d2ef2c
AK		 1241static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1242{
1243 unsigned i;
1244 struct msr_autoload *m = &vmx->msr_autoload;
1245
8bf00a52
GN		 1246 switch (msr) {
1247 case MSR_EFER:
1248 if (cpu_has_load_ia32_efer) {
1249 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1250 VM_EXIT_LOAD_IA32_EFER);
1251 return;
1252 }
1253 break;
1254 case MSR_CORE_PERF_GLOBAL_CTRL:
1255 if (cpu_has_load_perf_global_ctrl) {
1256 clear_atomic_switch_msr_special(
1257 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1258 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1259 return;
1260 }
1261 break;
110312c8
AK		 1262 }
1263
61d2ef2c
AK		 1264 for (i = 0; i < m->nr; ++i)
1265 if (m->guest[i].index == msr)
1266 break;
1267
1268 if (i == m->nr)
1269 return;
1270 --m->nr;
1271 m->guest[i] = m->guest[m->nr];
1272 m->host[i] = m->host[m->nr];
1273 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1274 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1275}
1276
8bf00a52
GN		 1277static void add_atomic_switch_msr_special(unsigned long entry,
1278 unsigned long exit, unsigned long guest_val_vmcs,
1279 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1280{
1281 vmcs_write64(guest_val_vmcs, guest_val);
1282 vmcs_write64(host_val_vmcs, host_val);
1283 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1284 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1285}
1286
61d2ef2c
AK		 1287static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1288 u64 guest_val, u64 host_val)
1289{
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
8bf00a52
GN		 1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER,
1298 GUEST_IA32_EFER,
1299 HOST_IA32_EFER,
1300 guest_val, host_val);
1301 return;
1302 }
1303 break;
1304 case MSR_CORE_PERF_GLOBAL_CTRL:
1305 if (cpu_has_load_perf_global_ctrl) {
1306 add_atomic_switch_msr_special(
1307 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1308 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1309 GUEST_IA32_PERF_GLOBAL_CTRL,
1310 HOST_IA32_PERF_GLOBAL_CTRL,
1311 guest_val, host_val);
1312 return;
1313 }
1314 break;
110312c8
AK		 1315 }
1316
61d2ef2c
AK		 1317 for (i = 0; i < m->nr; ++i)
1318 if (m->guest[i].index == msr)
1319 break;
1320
e7fc6f93
GN		 1321 if (i == NR_AUTOLOAD_MSRS) {
1322 printk_once(KERN_WARNING"Not enough mst switch entries. "
1323 "Can't add msr %x\n", msr);
1324 return;
1325 } else if (i == m->nr) {
61d2ef2c
AK		 1326 ++m->nr;
1327 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1328 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1329 }
1330
1331 m->guest[i].index = msr;
1332 m->guest[i].value = guest_val;
1333 m->host[i].index = msr;
1334 m->host[i].value = host_val;
1335}
1336
33ed6329
AK		 1337static void reload_tss(void)
1338{
33ed6329
AK		 1339 /*
1340 * VT restores TR but not its size. Useless.
1341 */
d359192f 1342 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1343 struct desc_struct *descs;
33ed6329 1344
d359192f 1345 descs = (void *)gdt->address;
33ed6329
AK		 1346 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1347 load_TR_desc();
33ed6329
AK		 1348}
1349
92c0d900 1350static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1351{
3a34a881 1352 u64 guest_efer;
51c6cf66
AK		 1353 u64 ignore_bits;
1354
f6801dff 1355 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1356
51c6cf66 1357 /*
0fa06071 1358 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1359 * outside long mode
1360 */
1361 ignore_bits = EFER_NX | EFER_SCE;
1362#ifdef CONFIG_X86_64
1363 ignore_bits |= EFER_LMA | EFER_LME;
1364 /* SCE is meaningful only in long mode on Intel */
1365 if (guest_efer & EFER_LMA)
1366 ignore_bits &= ~(u64)EFER_SCE;
1367#endif
51c6cf66
AK		 1368 guest_efer &= ~ignore_bits;
1369 guest_efer |= host_efer & ignore_bits;
26bb0981 1370 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1371 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1372
1373 clear_atomic_switch_msr(vmx, MSR_EFER);
1374 /* On ept, can't emulate nx, and must switch nx atomically */
1375 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1376 guest_efer = vmx->vcpu.arch.efer;
1377 if (!(guest_efer & EFER_LMA))
1378 guest_efer &= ~EFER_LME;
1379 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1380 return false;
1381 }
1382
26bb0981 1383 return true;
51c6cf66
AK		 1384}
1385
2d49ec72
GN		 1386static unsigned long segment_base(u16 selector)
1387{
d359192f 1388 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1389 struct desc_struct *d;
1390 unsigned long table_base;
1391 unsigned long v;
1392
1393 if (!(selector & ~3))
1394 return 0;
1395
d359192f 1396 table_base = gdt->address;
2d49ec72
GN		 1397
1398 if (selector & 4) { /* from ldt */
1399 u16 ldt_selector = kvm_read_ldt();
1400
1401 if (!(ldt_selector & ~3))
1402 return 0;
1403
1404 table_base = segment_base(ldt_selector);
1405 }
1406 d = (struct desc_struct *)(table_base + (selector & ~7));
1407 v = get_desc_base(d);
1408#ifdef CONFIG_X86_64
1409 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1410 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1411#endif
1412 return v;
1413}
1414
1415static inline unsigned long kvm_read_tr_base(void)
1416{
1417 u16 tr;
1418 asm("str %0" : "=g"(tr));
1419 return segment_base(tr);
1420}
1421
04d2cc77 1422static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1423{
04d2cc77 1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1425 int i;
04d2cc77 1426
a2fa3e9f 1427 if (vmx->host_state.loaded)
33ed6329
AK		 1428 return;
1429
a2fa3e9f 1430 vmx->host_state.loaded = 1;
33ed6329
AK		 1431 /*
1432 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1433 * allow segment selectors with cpl > 0 or ti == 1.
1434 */
d6e88aec 1435 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1436 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1437 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1438 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1439 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1440 vmx->host_state.fs_reload_needed = 0;
1441 } else {
33ed6329 1442 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1443 vmx->host_state.fs_reload_needed = 1;
33ed6329 1444 }
9581d442 1445 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1446 if (!(vmx->host_state.gs_sel & 7))
1447 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1448 else {
1449 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1450 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1451 }
1452
b2da15ac
AK		 1453#ifdef CONFIG_X86_64
1454 savesegment(ds, vmx->host_state.ds_sel);
1455 savesegment(es, vmx->host_state.es_sel);
1456#endif
1457
33ed6329
AK		 1458#ifdef CONFIG_X86_64
1459 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1460 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1461#else
a2fa3e9f
GH		 1462 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1463 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1464#endif
707c0874
AK		 1465
1466#ifdef CONFIG_X86_64
c8770e7b
AK		 1467 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1468 if (is_long_mode(&vmx->vcpu))
44ea2b17 1469 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1470#endif
26bb0981
AK		 1471 for (i = 0; i < vmx->save_nmsrs; ++i)
1472 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1473 vmx->guest_msrs[i].data,
1474 vmx->guest_msrs[i].mask);
33ed6329
AK		 1475}
1476
a9b21b62 1477static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1478{
a2fa3e9f 1479 if (!vmx->host_state.loaded)
33ed6329
AK		 1480 return;
1481
e1beb1d3 1482 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1483 vmx->host_state.loaded = 0;
c8770e7b
AK		 1484#ifdef CONFIG_X86_64
1485 if (is_long_mode(&vmx->vcpu))
1486 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1487#endif
152d3f2f 1488 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1489 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1490#ifdef CONFIG_X86_64
9581d442 1491 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1492#else
1493 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1494#endif
33ed6329 1495 }
0a77fe4c
AK		 1496 if (vmx->host_state.fs_reload_needed)
1497 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1498#ifdef CONFIG_X86_64
1499 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1500 loadsegment(ds, vmx->host_state.ds_sel);
1501 loadsegment(es, vmx->host_state.es_sel);
1502 }
b2da15ac 1503#endif
152d3f2f 1504 reload_tss();
44ea2b17 1505#ifdef CONFIG_X86_64
c8770e7b 1506 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1507#endif
b1a74bf8
SS		 1508 /*
1509 * If the FPU is not active (through the host task or
1510 * the guest vcpu), then restore the cr0.TS bit.
1511 */
1512 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1513 stts();
3444d7da 1514 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1515}
1516
a9b21b62
AK		 1517static void vmx_load_host_state(struct vcpu_vmx *vmx)
1518{
1519 preempt_disable();
1520 __vmx_load_host_state(vmx);
1521 preempt_enable();
1522}
1523
6aa8b732
AK		 1524/*
1525 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1526 * vcpu mutex is already taken.
1527 */
15ad7146 1528static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1529{
a2fa3e9f 1530 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1531 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1532
4610c9cc
DX		 1533 if (!vmm_exclusive)
1534 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1535 else if (vmx->loaded_vmcs->cpu != cpu)
1536 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1537
d462b819
NHE		 1538 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1539 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1540 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1541 }
1542
d462b819 1543 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1544 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1545 unsigned long sysenter_esp;
1546
a8eeb04a 1547 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1548 local_irq_disable();
5a560f8b
XG		 1549
1550 /*
1551 * Read loaded_vmcs->cpu should be before fetching
1552 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1553 * See the comments in __loaded_vmcs_clear().
1554 */
1555 smp_rmb();
1556
d462b819
NHE		 1557 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1558 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1559 local_irq_enable();
1560
6aa8b732
AK		 1561 /*
1562 * Linux uses per-cpu TSS and GDT, so set these when switching
1563 * processors.
1564 */
d6e88aec 1565 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1566 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1567
1568 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1569 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1570 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1571 }
6aa8b732
AK		 1572}
1573
1574static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1575{
a9b21b62 1576 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1577 if (!vmm_exclusive) {
d462b819
NHE		 1578 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1579 vcpu->cpu = -1;
4610c9cc
DX		 1580 kvm_cpu_vmxoff();
1581 }
6aa8b732
AK		 1582}
1583
5fd86fcf
AK		 1584static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1585{
81231c69
AK		 1586 ulong cr0;
1587
5fd86fcf
AK		 1588 if (vcpu->fpu_active)
1589 return;
1590 vcpu->fpu_active = 1;
81231c69
AK		 1591 cr0 = vmcs_readl(GUEST_CR0);
1592 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1593 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1594 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1595 update_exception_bitmap(vcpu);
edcafe3c 1596 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1597 if (is_guest_mode(vcpu))
1598 vcpu->arch.cr0_guest_owned_bits &=
1599 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1600 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1601}
1602
edcafe3c
AK		 1603static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1604
fe3ef05c
NHE		 1605/*
1606 * Return the cr0 value that a nested guest would read. This is a combination
1607 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1608 * its hypervisor (cr0_read_shadow).
1609 */
1610static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1611{
1612 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1613 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1614}
1615static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1616{
1617 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1618 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1619}
1620
5fd86fcf
AK		 1621static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1622{
36cf24e0
NHE		 1623 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1624 * set this *before* calling this function.
1625 */
edcafe3c 1626 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1627 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1628 update_exception_bitmap(vcpu);
edcafe3c
AK		 1629 vcpu->arch.cr0_guest_owned_bits = 0;
1630 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1631 if (is_guest_mode(vcpu)) {
1632 /*
1633 * L1's specified read shadow might not contain the TS bit,
1634 * so now that we turned on shadowing of this bit, we need to
1635 * set this bit of the shadow. Like in nested_vmx_run we need
1636 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1637 * up-to-date here because we just decached cr0.TS (and we'll
1638 * only update vmcs12->guest_cr0 on nested exit).
1639 */
1640 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1641 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1642 (vcpu->arch.cr0 & X86_CR0_TS);
1643 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1644 } else
1645 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1646}
1647
6aa8b732
AK		 1648static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1649{
78ac8b47 1650 unsigned long rflags, save_rflags;
345dcaa8 1651
6de12732
AK		 1652 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1653 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1654 rflags = vmcs_readl(GUEST_RFLAGS);
1655 if (to_vmx(vcpu)->rmode.vm86_active) {
1656 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1657 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1658 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1659 }
1660 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1661 }
6de12732 1662 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1663}
1664
1665static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1666{
6de12732 1667 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1668 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1669 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1670 if (to_vmx(vcpu)->rmode.vm86_active) {
1671 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1672 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1673 }
6aa8b732
AK		 1674 vmcs_writel(GUEST_RFLAGS, rflags);
1675}
1676
2809f5d2
GC		 1677static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1678{
1679 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1680 int ret = 0;
1681
1682 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1683 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1684 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1685 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1686
1687 return ret & mask;
1688}
1689
1690static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1691{
1692 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1693 u32 interruptibility = interruptibility_old;
1694
1695 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1696
48005f64 1697 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1698 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1699 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1700 interruptibility |= GUEST_INTR_STATE_STI;
1701
1702 if ((interruptibility != interruptibility_old))
1703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1704}
1705
6aa8b732
AK		 1706static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1707{
1708 unsigned long rip;
6aa8b732 1709
5fdbf976 1710 rip = kvm_rip_read(vcpu);
6aa8b732 1711 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1712 kvm_rip_write(vcpu, rip);
6aa8b732 1713
2809f5d2
GC		 1714 /* skipping an emulated instruction also counts */
1715 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1716}
1717
0b6ac343
NHE		 1718/*
1719 * KVM wants to inject page-faults which it got to the guest. This function
1720 * checks whether in a nested guest, we need to inject them to L1 or L2.
1721 * This function assumes it is called with the exit reason in vmcs02 being
1722 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1723 * is running).
1724 */
1725static int nested_pf_handled(struct kvm_vcpu *vcpu)
1726{
1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728
1729 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1730 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1731 return 0;
1732
1733 nested_vmx_vmexit(vcpu);
1734 return 1;
1735}
1736
298101da 1737static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1738 bool has_error_code, u32 error_code,
1739 bool reinject)
298101da 1740{
77ab6db0 1741 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1742 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1743
0b6ac343
NHE		 1744 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1745 nested_pf_handled(vcpu))
1746 return;
1747
8ab2d2e2 1748 if (has_error_code) {
77ab6db0 1749 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1750 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1751 }
77ab6db0 1752
7ffd92c5 1753 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1754 int inc_eip = 0;
1755 if (kvm_exception_is_soft(nr))
1756 inc_eip = vcpu->arch.event_exit_inst_len;
1757 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1758 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1759 return;
1760 }
1761
66fd3f7f
GN		 1762 if (kvm_exception_is_soft(nr)) {
1763 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1764 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1765 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1766 } else
1767 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1768
1769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1770}
1771
4e47c7a6
SY		 1772static bool vmx_rdtscp_supported(void)
1773{
1774 return cpu_has_vmx_rdtscp();
1775}
1776
ad756a16
MJ		 1777static bool vmx_invpcid_supported(void)
1778{
1779 return cpu_has_vmx_invpcid() && enable_ept;
1780}
1781
a75beee6
ED		 1782/*
1783 * Swap MSR entry in host/guest MSR entry array.
1784 */
8b9cf98c 1785static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1786{
26bb0981 1787 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1788
1789 tmp = vmx->guest_msrs[to];
1790 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1791 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1792}
1793
e38aea3e
AK		 1794/*
1795 * Set up the vmcs to automatically save and restore system
1796 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1797 * mode, as fiddling with msrs is very expensive.
1798 */
8b9cf98c 1799static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1800{
26bb0981 1801 int save_nmsrs, index;
5897297b 1802 unsigned long *msr_bitmap;
e38aea3e 1803
a75beee6
ED		 1804 save_nmsrs = 0;
1805#ifdef CONFIG_X86_64
8b9cf98c 1806 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1807 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1808 if (index >= 0)
8b9cf98c
RR		 1809 move_msr_up(vmx, index, save_nmsrs++);
1810 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1811 if (index >= 0)
8b9cf98c
RR		 1812 move_msr_up(vmx, index, save_nmsrs++);
1813 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1814 if (index >= 0)
8b9cf98c 1815 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1816 index = __find_msr_index(vmx, MSR_TSC_AUX);
1817 if (index >= 0 && vmx->rdtscp_enabled)
1818 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1819 /*
8c06585d 1820 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1821 * if efer.sce is enabled.
1822 */
8c06585d 1823 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1824 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1825 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1826 }
1827#endif
92c0d900
AK		 1828 index = __find_msr_index(vmx, MSR_EFER);
1829 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1830 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1831
26bb0981 1832 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1833
1834 if (cpu_has_vmx_msr_bitmap()) {
1835 if (is_long_mode(&vmx->vcpu))
1836 msr_bitmap = vmx_msr_bitmap_longmode;
1837 else
1838 msr_bitmap = vmx_msr_bitmap_legacy;
1839
1840 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1841 }
e38aea3e
AK		 1842}
1843
6aa8b732
AK		 1844/*
1845 * reads and returns guest's timestamp counter "register"
1846 * guest_tsc = host_tsc + tsc_offset -- 21.3
1847 */
1848static u64 guest_read_tsc(void)
1849{
1850 u64 host_tsc, tsc_offset;
1851
1852 rdtscll(host_tsc);
1853 tsc_offset = vmcs_read64(TSC_OFFSET);
1854 return host_tsc + tsc_offset;
1855}
1856
d5c1785d
NHE		 1857/*
1858 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1859 * counter, even if a nested guest (L2) is currently running.
1860 */
886b470c 1861u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1862{
886b470c 1863 u64 tsc_offset;
d5c1785d 1864
d5c1785d
NHE		 1865 tsc_offset = is_guest_mode(vcpu) ?
1866 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1867 vmcs_read64(TSC_OFFSET);
1868 return host_tsc + tsc_offset;
1869}
1870
4051b188 1871/*
cc578287
ZA		 1872 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1873 * software catchup for faster rates on slower CPUs.
4051b188 1874 */
cc578287 1875static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1876{
cc578287
ZA		 1877 if (!scale)
1878 return;
1879
1880 if (user_tsc_khz > tsc_khz) {
1881 vcpu->arch.tsc_catchup = 1;
1882 vcpu->arch.tsc_always_catchup = 1;
1883 } else
1884 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1885}
1886
6aa8b732 1887/*
99e3e30a 1888 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1889 */
99e3e30a 1890static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1891{
27fc51b2 1892 if (is_guest_mode(vcpu)) {
7991825b 1893 /*
27fc51b2
NHE		 1894 * We're here if L1 chose not to trap WRMSR to TSC. According
1895 * to the spec, this should set L1's TSC; The offset that L1
1896 * set for L2 remains unchanged, and still needs to be added
1897 * to the newly set TSC to get L2's TSC.
7991825b 1898 */
27fc51b2
NHE		 1899 struct vmcs12 *vmcs12;
1900 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1901 /* recalculate vmcs02.TSC_OFFSET: */
1902 vmcs12 = get_vmcs12(vcpu);
1903 vmcs_write64(TSC_OFFSET, offset +
1904 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1905 vmcs12->tsc_offset : 0));
1906 } else {
1907 vmcs_write64(TSC_OFFSET, offset);
1908 }
6aa8b732
AK		 1909}
1910
f1e2b260 1911static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1912{
1913 u64 offset = vmcs_read64(TSC_OFFSET);
1914 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1915 if (is_guest_mode(vcpu)) {
1916 /* Even when running L2, the adjustment needs to apply to L1 */
1917 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1918 }
e48672fa
ZA		 1919}
1920
857e4099
JR		 1921static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1922{
1923 return target_tsc - native_read_tsc();
1924}
1925
801d3424
NHE		 1926static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1927{
1928 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1929 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1930}
1931
1932/*
1933 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1934 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1935 * all guests if the "nested" module option is off, and can also be disabled
1936 * for a single guest by disabling its VMX cpuid bit.
1937 */
1938static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1939{
1940 return nested && guest_cpuid_has_vmx(vcpu);
1941}
1942
b87a51ae
NHE		 1943/*
1944 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1945 * returned for the various VMX controls MSRs when nested VMX is enabled.
1946 * The same values should also be used to verify that vmcs12 control fields are
1947 * valid during nested entry from L1 to L2.
1948 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1949 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1950 * bit in the high half is on if the corresponding bit in the control field
1951 * may be on. See also vmx_control_verify().
1952 * TODO: allow these variables to be modified (downgraded) by module options
1953 * or other means.
1954 */
1955static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1956static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1957static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1958static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1959static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1960static __init void nested_vmx_setup_ctls_msrs(void)
1961{
1962 /*
1963 * Note that as a general rule, the high half of the MSRs (bits in
1964 * the control fields which may be 1) should be initialized by the
1965 * intersection of the underlying hardware's MSR (i.e., features which
1966 * can be supported) and the list of features we want to expose -
1967 * because they are known to be properly supported in our code.
1968 * Also, usually, the low half of the MSRs (bits which must be 1) can
1969 * be set to 0, meaning that L1 may turn off any of these bits. The
1970 * reason is that if one of these bits is necessary, it will appear
1971 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1972 * fields of vmcs01 and vmcs02, will turn these bits off - and
1973 * nested_vmx_exit_handled() will not pass related exits to L1.
1974 * These rules have exceptions below.
1975 */
1976
1977 /* pin-based controls */
1978 /*
1979 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1980 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1981 */
1982 nested_vmx_pinbased_ctls_low = 0x16 ;
1983 nested_vmx_pinbased_ctls_high = 0x16 |
1984 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1985 PIN_BASED_VIRTUAL_NMIS;
1986
1987 /* exit controls */
1988 nested_vmx_exit_ctls_low = 0;
b6f1250e 1989 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1990#ifdef CONFIG_X86_64
1991 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1992#else
1993 nested_vmx_exit_ctls_high = 0;
1994#endif
1995
1996 /* entry controls */
1997 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1998 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1999 nested_vmx_entry_ctls_low = 0;
2000 nested_vmx_entry_ctls_high &=
2001 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2002
2003 /* cpu-based controls */
2004 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2005 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2006 nested_vmx_procbased_ctls_low = 0;
2007 nested_vmx_procbased_ctls_high &=
2008 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2009 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2010 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2011 CPU_BASED_CR3_STORE_EXITING |
2012#ifdef CONFIG_X86_64
2013 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2014#endif
2015 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2016 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2017 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
b87a51ae
NHE		 2018 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2019 /*
2020 * We can allow some features even when not supported by the
2021 * hardware. For example, L1 can specify an MSR bitmap - and we
2022 * can use it to avoid exits to L1 - even when L0 runs L2
2023 * without MSR bitmaps.
2024 */
2025 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2026
2027 /* secondary cpu-based controls */
2028 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2029 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2030 nested_vmx_secondary_ctls_low = 0;
2031 nested_vmx_secondary_ctls_high &=
2032 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2033}
2034
2035static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2036{
2037 /*
2038 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2039 */
2040 return ((control & high) | low) == control;
2041}
2042
2043static inline u64 vmx_control_msr(u32 low, u32 high)
2044{
2045 return low | ((u64)high << 32);
2046}
2047
2048/*
2049 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2050 * also let it use VMX-specific MSRs.
2051 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2052 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2053 * like all other MSRs).
2054 */
2055static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2056{
2057 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2058 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2059 /*
2060 * According to the spec, processors which do not support VMX
2061 * should throw a #GP(0) when VMX capability MSRs are read.
2062 */
2063 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2064 return 1;
2065 }
2066
2067 switch (msr_index) {
2068 case MSR_IA32_FEATURE_CONTROL:
2069 *pdata = 0;
2070 break;
2071 case MSR_IA32_VMX_BASIC:
2072 /*
2073 * This MSR reports some information about VMX support. We
2074 * should return information about the VMX we emulate for the
2075 * guest, and the VMCS structure we give it - not about the
2076 * VMX support of the underlying hardware.
2077 */
2078 *pdata = VMCS12_REVISION |
2079 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2080 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2081 break;
2082 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2083 case MSR_IA32_VMX_PINBASED_CTLS:
2084 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2085 nested_vmx_pinbased_ctls_high);
2086 break;
2087 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2088 case MSR_IA32_VMX_PROCBASED_CTLS:
2089 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2090 nested_vmx_procbased_ctls_high);
2091 break;
2092 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2093 case MSR_IA32_VMX_EXIT_CTLS:
2094 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2095 nested_vmx_exit_ctls_high);
2096 break;
2097 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2098 case MSR_IA32_VMX_ENTRY_CTLS:
2099 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2100 nested_vmx_entry_ctls_high);
2101 break;
2102 case MSR_IA32_VMX_MISC:
2103 *pdata = 0;
2104 break;
2105 /*
2106 * These MSRs specify bits which the guest must keep fixed (on or off)
2107 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2108 * We picked the standard core2 setting.
2109 */
2110#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2111#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2112 case MSR_IA32_VMX_CR0_FIXED0:
2113 *pdata = VMXON_CR0_ALWAYSON;
2114 break;
2115 case MSR_IA32_VMX_CR0_FIXED1:
2116 *pdata = -1ULL;
2117 break;
2118 case MSR_IA32_VMX_CR4_FIXED0:
2119 *pdata = VMXON_CR4_ALWAYSON;
2120 break;
2121 case MSR_IA32_VMX_CR4_FIXED1:
2122 *pdata = -1ULL;
2123 break;
2124 case MSR_IA32_VMX_VMCS_ENUM:
2125 *pdata = 0x1f;
2126 break;
2127 case MSR_IA32_VMX_PROCBASED_CTLS2:
2128 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2129 nested_vmx_secondary_ctls_high);
2130 break;
2131 case MSR_IA32_VMX_EPT_VPID_CAP:
2132 /* Currently, no nested ept or nested vpid */
2133 *pdata = 0;
2134 break;
2135 default:
2136 return 0;
2137 }
2138
2139 return 1;
2140}
2141
2142static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2143{
2144 if (!nested_vmx_allowed(vcpu))
2145 return 0;
2146
2147 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2148 /* TODO: the right thing. */
2149 return 1;
2150 /*
2151 * No need to treat VMX capability MSRs specially: If we don't handle
2152 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2153 */
2154 return 0;
2155}
2156
6aa8b732
AK		 2157/*
2158 * Reads an msr value (of 'msr_index') into 'pdata'.
2159 * Returns 0 on success, non-0 otherwise.
2160 * Assumes vcpu_load() was already called.
2161 */
2162static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2163{
2164 u64 data;
26bb0981 2165 struct shared_msr_entry *msr;
6aa8b732
AK		 2166
2167 if (!pdata) {
2168 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2169 return -EINVAL;
2170 }
2171
2172 switch (msr_index) {
05b3e0c2 2173#ifdef CONFIG_X86_64
6aa8b732
AK		 2174 case MSR_FS_BASE:
2175 data = vmcs_readl(GUEST_FS_BASE);
2176 break;
2177 case MSR_GS_BASE:
2178 data = vmcs_readl(GUEST_GS_BASE);
2179 break;
44ea2b17
AK		 2180 case MSR_KERNEL_GS_BASE:
2181 vmx_load_host_state(to_vmx(vcpu));
2182 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2183 break;
26bb0981 2184#endif
6aa8b732 2185 case MSR_EFER:
3bab1f5d 2186 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2187 case MSR_IA32_TSC:
6aa8b732
AK		 2188 data = guest_read_tsc();
2189 break;
2190 case MSR_IA32_SYSENTER_CS:
2191 data = vmcs_read32(GUEST_SYSENTER_CS);
2192 break;
2193 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2194 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2195 break;
2196 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2197 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2198 break;
4e47c7a6
SY		 2199 case MSR_TSC_AUX:
2200 if (!to_vmx(vcpu)->rdtscp_enabled)
2201 return 1;
2202 /* Otherwise falls through */
6aa8b732 2203 default:
b87a51ae
NHE		 2204 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2205 return 0;
8b9cf98c 2206 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2207 if (msr) {
2208 data = msr->data;
2209 break;
6aa8b732 2210 }
3bab1f5d 2211 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2212 }
2213
2214 *pdata = data;
2215 return 0;
2216}
2217
2218/*
2219 * Writes msr value into into the appropriate "register".
2220 * Returns 0 on success, non-0 otherwise.
2221 * Assumes vcpu_load() was already called.
2222 */
8fe8ab46 2223static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2224{
a2fa3e9f 2225 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2226 struct shared_msr_entry *msr;
2cc51560 2227 int ret = 0;
8fe8ab46
WA		 2228 u32 msr_index = msr_info->index;
2229 u64 data = msr_info->data;
2cc51560 2230
6aa8b732 2231 switch (msr_index) {
3bab1f5d 2232 case MSR_EFER:
8fe8ab46 2233 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2234 break;
16175a79 2235#ifdef CONFIG_X86_64
6aa8b732 2236 case MSR_FS_BASE:
2fb92db1 2237 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2238 vmcs_writel(GUEST_FS_BASE, data);
2239 break;
2240 case MSR_GS_BASE:
2fb92db1 2241 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2242 vmcs_writel(GUEST_GS_BASE, data);
2243 break;
44ea2b17
AK		 2244 case MSR_KERNEL_GS_BASE:
2245 vmx_load_host_state(vmx);
2246 vmx->msr_guest_kernel_gs_base = data;
2247 break;
6aa8b732
AK		 2248#endif
2249 case MSR_IA32_SYSENTER_CS:
2250 vmcs_write32(GUEST_SYSENTER_CS, data);
2251 break;
2252 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2253 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2254 break;
2255 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2256 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2257 break;
af24a4e4 2258 case MSR_IA32_TSC:
8fe8ab46 2259 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2260 break;
468d472f
SY		 2261 case MSR_IA32_CR_PAT:
2262 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2263 vmcs_write64(GUEST_IA32_PAT, data);
2264 vcpu->arch.pat = data;
2265 break;
2266 }
8fe8ab46 2267 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2268 break;
2269 case MSR_TSC_AUX:
2270 if (!vmx->rdtscp_enabled)
2271 return 1;
2272 /* Check reserved bit, higher 32 bits should be zero */
2273 if ((data >> 32) != 0)
2274 return 1;
2275 /* Otherwise falls through */
6aa8b732 2276 default:
b87a51ae
NHE		 2277 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2278 break;
8b9cf98c 2279 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2280 if (msr) {
2281 msr->data = data;
2225fd56
AK		 2282 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2283 preempt_disable();
9ee73970
AK		 2284 kvm_set_shared_msr(msr->index, msr->data,
2285 msr->mask);
2225fd56
AK		 2286 preempt_enable();
2287 }
3bab1f5d 2288 break;
6aa8b732 2289 }
8fe8ab46 2290 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2291 }
2292
2cc51560 2293 return ret;
6aa8b732
AK		 2294}
2295
5fdbf976 2296static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2297{
5fdbf976
MT		 2298 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2299 switch (reg) {
2300 case VCPU_REGS_RSP:
2301 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2302 break;
2303 case VCPU_REGS_RIP:
2304 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2305 break;
6de4f3ad
AK		 2306 case VCPU_EXREG_PDPTR:
2307 if (enable_ept)
2308 ept_save_pdptrs(vcpu);
2309 break;
5fdbf976
MT		 2310 default:
2311 break;
2312 }
6aa8b732
AK		 2313}
2314
6aa8b732
AK		 2315static __init int cpu_has_kvm_support(void)
2316{
6210e37b 2317 return cpu_has_vmx();
6aa8b732
AK		 2318}
2319
2320static __init int vmx_disabled_by_bios(void)
2321{
2322 u64 msr;
2323
2324 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2325 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2326 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2327 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2328 && tboot_enabled())
2329 return 1;
23f3e991 2330 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2331 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2332 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2333 && !tboot_enabled()) {
2334 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2335 "activate TXT before enabling KVM\n");
cafd6659 2336 return 1;
f9335afe 2337 }
23f3e991
JC		 2338 /* launched w/o TXT and VMX disabled */
2339 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2340 && !tboot_enabled())
2341 return 1;
cafd6659
SW		 2342 }
2343
2344 return 0;
6aa8b732
AK		 2345}
2346
7725b894
DX		 2347static void kvm_cpu_vmxon(u64 addr)
2348{
2349 asm volatile (ASM_VMX_VMXON_RAX
2350 : : "a"(&addr), "m"(addr)
2351 : "memory", "cc");
2352}
2353
10474ae8 2354static int hardware_enable(void *garbage)
6aa8b732
AK		 2355{
2356 int cpu = raw_smp_processor_id();
2357 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2358 u64 old, test_bits;
6aa8b732 2359
10474ae8
AG		 2360 if (read_cr4() & X86_CR4_VMXE)
2361 return -EBUSY;
2362
d462b819 2363 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2364 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2365
2366 test_bits = FEATURE_CONTROL_LOCKED;
2367 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2368 if (tboot_enabled())
2369 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2370
2371 if ((old & test_bits) != test_bits) {
6aa8b732 2372 /* enable and lock */
cafd6659
SW		 2373 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2374 }
66aee91a 2375 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2376
4610c9cc
DX		 2377 if (vmm_exclusive) {
2378 kvm_cpu_vmxon(phys_addr);
2379 ept_sync_global();
2380 }
10474ae8 2381
3444d7da
AK		 2382 store_gdt(&__get_cpu_var(host_gdt));
2383
10474ae8 2384 return 0;
6aa8b732
AK		 2385}
2386
d462b819 2387static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2388{
2389 int cpu = raw_smp_processor_id();
d462b819 2390 struct loaded_vmcs *v, *n;
543e4243 2391
d462b819
NHE		 2392 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2393 loaded_vmcss_on_cpu_link)
2394 __loaded_vmcs_clear(v);
543e4243
AK		 2395}
2396
710ff4a8
EH		 2397
2398/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2399 * tricks.
2400 */
2401static void kvm_cpu_vmxoff(void)
6aa8b732 2402{
4ecac3fd 2403 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2404}
2405
710ff4a8
EH		 2406static void hardware_disable(void *garbage)
2407{
4610c9cc 2408 if (vmm_exclusive) {
d462b819 2409 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2410 kvm_cpu_vmxoff();
2411 }
7725b894 2412 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2413}
2414
1c3d14fe 2415static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2416 u32 msr, u32 *result)
1c3d14fe
YS		 2417{
2418 u32 vmx_msr_low, vmx_msr_high;
2419 u32 ctl = ctl_min | ctl_opt;
2420
2421 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2422
2423 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2424 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2425
2426 /* Ensure minimum (required) set of control bits are supported. */
2427 if (ctl_min & ~ctl)
002c7f7c 2428 return -EIO;
1c3d14fe
YS		 2429
2430 *result = ctl;
2431 return 0;
2432}
2433
110312c8
AK		 2434static __init bool allow_1_setting(u32 msr, u32 ctl)
2435{
2436 u32 vmx_msr_low, vmx_msr_high;
2437
2438 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2439 return vmx_msr_high & ctl;
2440}
2441
002c7f7c 2442static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2443{
2444 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2445 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2446 u32 _pin_based_exec_control = 0;
2447 u32 _cpu_based_exec_control = 0;
f78e0e2e 2448 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2449 u32 _vmexit_control = 0;
2450 u32 _vmentry_control = 0;
2451
2452 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2453 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2454 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2455 &_pin_based_exec_control) < 0)
002c7f7c 2456 return -EIO;
1c3d14fe 2457
10166744 2458 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2459#ifdef CONFIG_X86_64
2460 CPU_BASED_CR8_LOAD_EXITING |
2461 CPU_BASED_CR8_STORE_EXITING |
2462#endif
d56f546d
SY		 2463 CPU_BASED_CR3_LOAD_EXITING |
2464 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2465 CPU_BASED_USE_IO_BITMAPS |
2466 CPU_BASED_MOV_DR_EXITING |
a7052897 2467 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2468 CPU_BASED_MWAIT_EXITING |
2469 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2470 CPU_BASED_INVLPG_EXITING |
2471 CPU_BASED_RDPMC_EXITING;
443381a8 2472
f78e0e2e 2473 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2474 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2475 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2476 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2477 &_cpu_based_exec_control) < 0)
002c7f7c 2478 return -EIO;
6e5d865c
YS		 2479#ifdef CONFIG_X86_64
2480 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2481 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2482 ~CPU_BASED_CR8_STORE_EXITING;
2483#endif
f78e0e2e 2484 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2485 min2 = 0;
2486 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2487 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2488 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2489 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2490 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2491 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2492 SECONDARY_EXEC_RDTSCP |
2493 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2494 if (adjust_vmx_controls(min2, opt2,
2495 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2496 &_cpu_based_2nd_exec_control) < 0)
2497 return -EIO;
2498 }
2499#ifndef CONFIG_X86_64
2500 if (!(_cpu_based_2nd_exec_control &
2501 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2502 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2503#endif
d56f546d 2504 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2505 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2506 enabled */
5fff7d27
GN		 2507 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2508 CPU_BASED_CR3_STORE_EXITING |
2509 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2510 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2511 vmx_capability.ept, vmx_capability.vpid);
2512 }
1c3d14fe
YS		 2513
2514 min = 0;
2515#ifdef CONFIG_X86_64
2516 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2517#endif
468d472f 2518 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2519 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2520 &_vmexit_control) < 0)
002c7f7c 2521 return -EIO;
1c3d14fe 2522
468d472f
SY		 2523 min = 0;
2524 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2525 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2526 &_vmentry_control) < 0)
002c7f7c 2527 return -EIO;
6aa8b732 2528
c68876fd 2529 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2530
2531 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2532 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2533 return -EIO;
1c3d14fe
YS		 2534
2535#ifdef CONFIG_X86_64
2536 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2537 if (vmx_msr_high & (1u<<16))
002c7f7c 2538 return -EIO;
1c3d14fe
YS		 2539#endif
2540
2541 /* Require Write-Back (WB) memory type for VMCS accesses. */
2542 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2543 return -EIO;
1c3d14fe 2544
002c7f7c
YS		 2545 vmcs_conf->size = vmx_msr_high & 0x1fff;
2546 vmcs_conf->order = get_order(vmcs_config.size);
2547 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2548
002c7f7c
YS		 2549 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2550 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2551 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2552 vmcs_conf->vmexit_ctrl = _vmexit_control;
2553 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2554
110312c8
AK		 2555 cpu_has_load_ia32_efer =
2556 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2557 VM_ENTRY_LOAD_IA32_EFER)
2558 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2559 VM_EXIT_LOAD_IA32_EFER);
2560
8bf00a52
GN		 2561 cpu_has_load_perf_global_ctrl =
2562 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2563 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2564 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2565 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2566
2567 /*
2568 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2569 * but due to arrata below it can't be used. Workaround is to use
2570 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2571 *
2572 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2573 *
2574 * AAK155 (model 26)
2575 * AAP115 (model 30)
2576 * AAT100 (model 37)
2577 * BC86,AAY89,BD102 (model 44)
2578 * BA97 (model 46)
2579 *
2580 */
2581 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2582 switch (boot_cpu_data.x86_model) {
2583 case 26:
2584 case 30:
2585 case 37:
2586 case 44:
2587 case 46:
2588 cpu_has_load_perf_global_ctrl = false;
2589 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2590 "does not work properly. Using workaround\n");
2591 break;
2592 default:
2593 break;
2594 }
2595 }
2596
1c3d14fe 2597 return 0;
c68876fd 2598}
6aa8b732
AK		 2599
2600static struct vmcs *alloc_vmcs_cpu(int cpu)
2601{
2602 int node = cpu_to_node(cpu);
2603 struct page *pages;
2604 struct vmcs *vmcs;
2605
6484eb3e 2606 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2607 if (!pages)
2608 return NULL;
2609 vmcs = page_address(pages);
1c3d14fe
YS		 2610 memset(vmcs, 0, vmcs_config.size);
2611 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2612 return vmcs;
2613}
2614
2615static struct vmcs *alloc_vmcs(void)
2616{
d3b2c338 2617 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2618}
2619
2620static void free_vmcs(struct vmcs *vmcs)
2621{
1c3d14fe 2622 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2623}
2624
d462b819
NHE		 2625/*
2626 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2627 */
2628static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2629{
2630 if (!loaded_vmcs->vmcs)
2631 return;
2632 loaded_vmcs_clear(loaded_vmcs);
2633 free_vmcs(loaded_vmcs->vmcs);
2634 loaded_vmcs->vmcs = NULL;
2635}
2636
39959588 2637static void free_kvm_area(void)
6aa8b732
AK		 2638{
2639 int cpu;
2640
3230bb47 2641 for_each_possible_cpu(cpu) {
6aa8b732 2642 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2643 per_cpu(vmxarea, cpu) = NULL;
2644 }
6aa8b732
AK		 2645}
2646
6aa8b732
AK		 2647static __init int alloc_kvm_area(void)
2648{
2649 int cpu;
2650
3230bb47 2651 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2652 struct vmcs *vmcs;
2653
2654 vmcs = alloc_vmcs_cpu(cpu);
2655 if (!vmcs) {
2656 free_kvm_area();
2657 return -ENOMEM;
2658 }
2659
2660 per_cpu(vmxarea, cpu) = vmcs;
2661 }
2662 return 0;
2663}
2664
2665static __init int hardware_setup(void)
2666{
002c7f7c
YS		 2667 if (setup_vmcs_config(&vmcs_config) < 0)
2668 return -EIO;
50a37eb4
JR		 2669
2670 if (boot_cpu_has(X86_FEATURE_NX))
2671 kvm_enable_efer_bits(EFER_NX);
2672
93ba03c2
SY		 2673 if (!cpu_has_vmx_vpid())
2674 enable_vpid = 0;
2675
4bc9b982
SY		 2676 if (!cpu_has_vmx_ept() ||
2677 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2678 enable_ept = 0;
3a624e29 2679 enable_unrestricted_guest = 0;
83c3a331 2680 enable_ept_ad_bits = 0;
3a624e29
NK		 2681 }
2682
83c3a331
XH		 2683 if (!cpu_has_vmx_ept_ad_bits())
2684 enable_ept_ad_bits = 0;
2685
3a624e29
NK		 2686 if (!cpu_has_vmx_unrestricted_guest())
2687 enable_unrestricted_guest = 0;
93ba03c2
SY		 2688
2689 if (!cpu_has_vmx_flexpriority())
2690 flexpriority_enabled = 0;
2691
95ba8273
GN		 2692 if (!cpu_has_vmx_tpr_shadow())
2693 kvm_x86_ops->update_cr8_intercept = NULL;
2694
54dee993
MT		 2695 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2696 kvm_disable_largepages();
2697
4b8d54f9
ZE		 2698 if (!cpu_has_vmx_ple())
2699 ple_gap = 0;
2700
b87a51ae
NHE		 2701 if (nested)
2702 nested_vmx_setup_ctls_msrs();
2703
6aa8b732
AK		 2704 return alloc_kvm_area();
2705}
2706
2707static __exit void hardware_unsetup(void)
2708{
2709 free_kvm_area();
2710}
2711
f5f7b2fe 2712static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
6aa8b732 2713{
772e0318 2714 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
c865c43d 2715 struct kvm_segment tmp = *save;
6aa8b732 2716
c865c43d
AK		 2717 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2718 tmp.base = vmcs_readl(sf->base);
2719 tmp.selector = vmcs_read16(sf->selector);
2720 tmp.s = 1;
6aa8b732 2721 }
c865c43d 2722 vmx_set_segment(vcpu, &tmp, seg);
6aa8b732
AK		 2723}
2724
2725static void enter_pmode(struct kvm_vcpu *vcpu)
2726{
2727 unsigned long flags;
a89a8fb9 2728 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2729
a89a8fb9 2730 vmx->emulation_required = 1;
7ffd92c5 2731 vmx->rmode.vm86_active = 0;
6aa8b732 2732
2fb92db1
AK		 2733 vmx_segment_cache_clear(vmx);
2734
f5f7b2fe 2735 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2736
2737 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2738 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2739 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2740 vmcs_writel(GUEST_RFLAGS, flags);
2741
66aee91a
RR		 2742 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2743 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2744
2745 update_exception_bitmap(vcpu);
2746
a89a8fb9
MG		 2747 if (emulate_invalid_guest_state)
2748 return;
2749
f5f7b2fe
AK		 2750 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2751 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2752 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2753 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732 2754
2fb92db1
AK		 2755 vmx_segment_cache_clear(vmx);
2756
6aa8b732
AK		 2757 vmcs_write16(GUEST_SS_SELECTOR, 0);
2758 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2759
2760 vmcs_write16(GUEST_CS_SELECTOR,
2761 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2762 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2763}
2764
d77c26fc 2765static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2766{
bfc6d222 2767 if (!kvm->arch.tss_addr) {
bc6678a3 2768 struct kvm_memslots *slots;
28a37544 2769 struct kvm_memory_slot *slot;
bc6678a3
MT		 2770 gfn_t base_gfn;
2771
90d83dc3 2772 slots = kvm_memslots(kvm);
28a37544
XG		 2773 slot = id_to_memslot(slots, 0);
2774 base_gfn = slot->base_gfn + slot->npages - 3;
2775
cbc94022
IE		 2776 return base_gfn << PAGE_SHIFT;
2777 }
bfc6d222 2778 return kvm->arch.tss_addr;
6aa8b732
AK		 2779}
2780
f5f7b2fe 2781static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2782{
772e0318 2783 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
6aa8b732 2784
15b00f32 2785 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2786 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2787 vmcs_write32(sf->limit, 0xffff);
2788 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2789 if (save->base & 0xf)
2790 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2791 " aligned when entering protected mode (seg=%d)",
2792 seg);
6aa8b732
AK		 2793}
2794
2795static void enter_rmode(struct kvm_vcpu *vcpu)
2796{
2797 unsigned long flags;
a89a8fb9 2798 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2799 struct kvm_segment var;
6aa8b732 2800
3a624e29
NK		 2801 if (enable_unrestricted_guest)
2802 return;
2803
f5f7b2fe
AK		 2804 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2805 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2806 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2807 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2808 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2809
a89a8fb9 2810 vmx->emulation_required = 1;
7ffd92c5 2811 vmx->rmode.vm86_active = 1;
6aa8b732 2812
baa7e81e 2813
776e58ea
GN		 2814 /*
2815 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2816 * vcpu. Call it here with phys address pointing 16M below 4G.
2817 */
2818 if (!vcpu->kvm->arch.tss_addr) {
2819 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2820 "called before entering vcpu\n");
2821 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2822 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2823 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2824 }
2825
2fb92db1
AK		 2826 vmx_segment_cache_clear(vmx);
2827
6aa8b732 2828 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
6aa8b732 2829 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2830 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2831
2832 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2833 vmx->rmode.save_rflags = flags;
6aa8b732 2834
053de044 2835 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2836
2837 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2838 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2839 update_exception_bitmap(vcpu);
2840
a89a8fb9
MG		 2841 if (emulate_invalid_guest_state)
2842 goto continue_rmode;
2843
b246dd5d
OW		 2844 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2845 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2846
2847 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2848 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2849
2850 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2851 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2852
2853 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2854 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2855
b246dd5d
OW		 2856 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2857 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2858
b246dd5d
OW		 2859 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2860 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2861
a89a8fb9 2862continue_rmode:
8668a3c4 2863 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2864}
2865
401d10de
AS		 2866static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2867{
2868 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2869 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2870
2871 if (!msr)
2872 return;
401d10de 2873
44ea2b17
AK		 2874 /*
2875 * Force kernel_gs_base reloading before EFER changes, as control
2876 * of this msr depends on is_long_mode().
2877 */
2878 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2879 vcpu->arch.efer = efer;
401d10de
AS		 2880 if (efer & EFER_LMA) {
2881 vmcs_write32(VM_ENTRY_CONTROLS,
2882 vmcs_read32(VM_ENTRY_CONTROLS) |
2883 VM_ENTRY_IA32E_MODE);
2884 msr->data = efer;
2885 } else {
2886 vmcs_write32(VM_ENTRY_CONTROLS,
2887 vmcs_read32(VM_ENTRY_CONTROLS) &
2888 ~VM_ENTRY_IA32E_MODE);
2889
2890 msr->data = efer & ~EFER_LME;
2891 }
2892 setup_msrs(vmx);
2893}
2894
05b3e0c2 2895#ifdef CONFIG_X86_64
6aa8b732
AK		 2896
2897static void enter_lmode(struct kvm_vcpu *vcpu)
2898{
2899 u32 guest_tr_ar;
2900
2fb92db1
AK		 2901 vmx_segment_cache_clear(to_vmx(vcpu));
2902
6aa8b732
AK		 2903 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2904 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2905 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2906 __func__);
6aa8b732
AK		 2907 vmcs_write32(GUEST_TR_AR_BYTES,
2908 (guest_tr_ar & ~AR_TYPE_MASK)
2909 | AR_TYPE_BUSY_64_TSS);
2910 }
da38f438 2911 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2912}
2913
2914static void exit_lmode(struct kvm_vcpu *vcpu)
2915{
6aa8b732
AK		 2916 vmcs_write32(VM_ENTRY_CONTROLS,
2917 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2918 & ~VM_ENTRY_IA32E_MODE);
da38f438 2919 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2920}
2921
2922#endif
2923
2384d2b3
SY		 2924static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2925{
b9d762fa 2926 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2927 if (enable_ept) {
2928 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2929 return;
4e1096d2 2930 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2931 }
2384d2b3
SY		 2932}
2933
e8467fda
AK		 2934static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2935{
2936 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2937
2938 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2939 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2940}
2941
aff48baa
AK		 2942static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2943{
2944 if (enable_ept && is_paging(vcpu))
2945 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2946 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2947}
2948
25c4c276 2949static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2950{
fc78f519
AK		 2951 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2952
2953 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2954 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2955}
2956
1439442c
SY		 2957static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2958{
6de4f3ad
AK		 2959 if (!test_bit(VCPU_EXREG_PDPTR,
2960 (unsigned long *)&vcpu->arch.regs_dirty))
2961 return;
2962
1439442c 2963 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2964 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2965 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2966 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2967 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2968 }
2969}
2970
8f5d549f
AK		 2971static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2972{
2973 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2974 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2975 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2976 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2977 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2978 }
6de4f3ad
AK		 2979
2980 __set_bit(VCPU_EXREG_PDPTR,
2981 (unsigned long *)&vcpu->arch.regs_avail);
2982 __set_bit(VCPU_EXREG_PDPTR,
2983 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2984}
2985
5e1746d6 2986static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2987
2988static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2989 unsigned long cr0,
2990 struct kvm_vcpu *vcpu)
2991{
5233dd51
MT		 2992 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2993 vmx_decache_cr3(vcpu);
1439442c
SY		 2994 if (!(cr0 & X86_CR0_PG)) {
2995 /* From paging/starting to nonpaging */
2996 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2997 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2998 (CPU_BASED_CR3_LOAD_EXITING |
2999 CPU_BASED_CR3_STORE_EXITING));
3000 vcpu->arch.cr0 = cr0;
fc78f519 3001 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3002 } else if (!is_paging(vcpu)) {
3003 /* From nonpaging to paging */
3004 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3005 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3006 ~(CPU_BASED_CR3_LOAD_EXITING |
3007 CPU_BASED_CR3_STORE_EXITING));
3008 vcpu->arch.cr0 = cr0;
fc78f519 3009 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3010 }
95eb84a7
SY		 3011
3012 if (!(cr0 & X86_CR0_WP))
3013 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3014}
3015
6aa8b732
AK		 3016static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3017{
7ffd92c5 3018 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3019 unsigned long hw_cr0;
3020
3021 if (enable_unrestricted_guest)
3022 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3023 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3024 else
3025 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3026
7ffd92c5 3027 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3028 enter_pmode(vcpu);
3029
7ffd92c5 3030 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3031 enter_rmode(vcpu);
3032
05b3e0c2 3033#ifdef CONFIG_X86_64
f6801dff 3034 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3035 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3036 enter_lmode(vcpu);
707d92fa 3037 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3038 exit_lmode(vcpu);
3039 }
3040#endif
3041
089d034e 3042 if (enable_ept)
1439442c
SY		 3043 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3044
02daab21 3045 if (!vcpu->fpu_active)
81231c69 3046 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3047
6aa8b732 3048 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3049 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3050 vcpu->arch.cr0 = cr0;
69c73028 3051 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3052}
3053
1439442c
SY		 3054static u64 construct_eptp(unsigned long root_hpa)
3055{
3056 u64 eptp;
3057
3058 /* TODO write the value reading from MSR */
3059 eptp = VMX_EPT_DEFAULT_MT |
3060 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3061 if (enable_ept_ad_bits)
3062 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3063 eptp |= (root_hpa & PAGE_MASK);
3064
3065 return eptp;
3066}
3067
6aa8b732
AK		 3068static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3069{
1439442c
SY		 3070 unsigned long guest_cr3;
3071 u64 eptp;
3072
3073 guest_cr3 = cr3;
089d034e 3074 if (enable_ept) {
1439442c
SY		 3075 eptp = construct_eptp(cr3);
3076 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3077 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3078 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3079 ept_load_pdptrs(vcpu);
1439442c
SY		 3080 }
3081
2384d2b3 3082 vmx_flush_tlb(vcpu);
1439442c 3083 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3084}
3085
5e1746d6 3086static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3087{
7ffd92c5 3088 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3089 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3090
5e1746d6
NHE		 3091 if (cr4 & X86_CR4_VMXE) {
3092 /*
3093 * To use VMXON (and later other VMX instructions), a guest
3094 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3095 * So basically the check on whether to allow nested VMX
3096 * is here.
3097 */
3098 if (!nested_vmx_allowed(vcpu))
3099 return 1;
3100 } else if (to_vmx(vcpu)->nested.vmxon)
3101 return 1;
3102
ad312c7c 3103 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3104 if (enable_ept) {
3105 if (!is_paging(vcpu)) {
3106 hw_cr4 &= ~X86_CR4_PAE;
3107 hw_cr4 |= X86_CR4_PSE;
3108 } else if (!(cr4 & X86_CR4_PAE)) {
3109 hw_cr4 &= ~X86_CR4_PAE;
3110 }
3111 }
1439442c
SY		 3112
3113 vmcs_writel(CR4_READ_SHADOW, cr4);
3114 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3115 return 0;
6aa8b732
AK		 3116}
3117
6aa8b732
AK		 3118static void vmx_get_segment(struct kvm_vcpu *vcpu,
3119 struct kvm_segment *var, int seg)
3120{
a9179499 3121 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3122 u32 ar;
3123
a9179499
AK		 3124 if (vmx->rmode.vm86_active
3125 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3126 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
72636420 3127 || seg == VCPU_SREG_GS)) {
f5f7b2fe 3128 *var = vmx->rmode.segs[seg];
a9179499 3129 if (seg == VCPU_SREG_TR
2fb92db1 3130 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3131 return;
1390a28b
AK		 3132 var->base = vmx_read_guest_seg_base(vmx, seg);
3133 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3134 return;
a9179499 3135 }
2fb92db1
AK		 3136 var->base = vmx_read_guest_seg_base(vmx, seg);
3137 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3138 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3139 ar = vmx_read_guest_seg_ar(vmx, seg);
9fd4a3b7 3140 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3141 ar = 0;
3142 var->type = ar & 15;
3143 var->s = (ar >> 4) & 1;
3144 var->dpl = (ar >> 5) & 3;
3145 var->present = (ar >> 7) & 1;
3146 var->avl = (ar >> 12) & 1;
3147 var->l = (ar >> 13) & 1;
3148 var->db = (ar >> 14) & 1;
3149 var->g = (ar >> 15) & 1;
3150 var->unusable = (ar >> 16) & 1;
3151}
3152
a9179499
AK		 3153static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3154{
a9179499
AK		 3155 struct kvm_segment s;
3156
3157 if (to_vmx(vcpu)->rmode.vm86_active) {
3158 vmx_get_segment(vcpu, &s, seg);
3159 return s.base;
3160 }
2fb92db1 3161 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3162}
3163
69c73028 3164static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3165{
3eeb3288 3166 if (!is_protmode(vcpu))
2e4d2653
IE		 3167 return 0;
3168
f4c63e5d
AK		 3169 if (!is_long_mode(vcpu)
3170 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3171 return 3;
3172
2fb92db1 3173 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3174}
3175
69c73028
AK		 3176static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3177{
d881e6f6
AK		 3178 struct vcpu_vmx *vmx = to_vmx(vcpu);
3179
3180 /*
3181 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182 * fail; use the cache instead.
3183 */
3184 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3185 return vmx->cpl;
3186 }
3187
69c73028
AK		 3188 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3189 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3190 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3191 }
d881e6f6
AK		 3192
3193 return vmx->cpl;
69c73028
AK		 3194}
3195
3196
653e3108 3197static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3198{
6aa8b732
AK		 3199 u32 ar;
3200
f0495f9b 3201 if (var->unusable || !var->present)
6aa8b732
AK		 3202 ar = 1 << 16;
3203 else {
3204 ar = var->type & 15;
3205 ar |= (var->s & 1) << 4;
3206 ar |= (var->dpl & 3) << 5;
3207 ar |= (var->present & 1) << 7;
3208 ar |= (var->avl & 1) << 12;
3209 ar |= (var->l & 1) << 13;
3210 ar |= (var->db & 1) << 14;
3211 ar |= (var->g & 1) << 15;
3212 }
653e3108
AK		 3213
3214 return ar;
3215}
3216
3217static void vmx_set_segment(struct kvm_vcpu *vcpu,
3218 struct kvm_segment *var, int seg)
3219{
7ffd92c5 3220 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3221 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108
AK		 3222 u32 ar;
3223
2fb92db1
AK		 3224 vmx_segment_cache_clear(vmx);
3225
7ffd92c5 3226 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3227 vmcs_write16(sf->selector, var->selector);
f5f7b2fe 3228 vmx->rmode.segs[VCPU_SREG_TR] = *var;
653e3108
AK		 3229 return;
3230 }
3231 vmcs_writel(sf->base, var->base);
3232 vmcs_write32(sf->limit, var->limit);
3233 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3234 if (vmx->rmode.vm86_active && var->s) {
ce566803 3235 vmx->rmode.segs[seg] = *var;
653e3108
AK		 3236 /*
3237 * Hack real-mode segments into vm86 compatibility.
3238 */
3239 if (var->base == 0xffff0000 && var->selector == 0xf000)
3240 vmcs_writel(sf->base, 0xf0000);
3241 ar = 0xf3;
3242 } else
3243 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3244
3245 /*
3246 * Fix the "Accessed" bit in AR field of segment registers for older
3247 * qemu binaries.
3248 * IA32 arch specifies that at the time of processor reset the
3249 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3250 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3251 * state vmexit when "unrestricted guest" mode is turned on.
3252 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3253 * tree. Newer qemu binaries with that qemu fix would not need this
3254 * kvm hack.
3255 */
3256 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3257 ar |= 0x1; /* Accessed */
3258
6aa8b732 3259 vmcs_write32(sf->ar_bytes, ar);
69c73028 3260 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3261
3262 /*
3263 * Fix segments for real mode guest in hosts that don't have
3264 * "unrestricted_mode" or it was disabled.
3265 * This is done to allow migration of the guests from hosts with
3266 * unrestricted guest like Westmere to older host that don't have
3267 * unrestricted guest like Nehelem.
3268 */
3269 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3270 switch (seg) {
3271 case VCPU_SREG_CS:
3272 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3273 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3274 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3275 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3276 vmcs_write16(GUEST_CS_SELECTOR,
3277 vmcs_readl(GUEST_CS_BASE) >> 4);
3278 break;
3279 case VCPU_SREG_ES:
b246dd5d 3280 case VCPU_SREG_DS:
b246dd5d 3281 case VCPU_SREG_GS:
b246dd5d 3282 case VCPU_SREG_FS:
f5f7b2fe 3283 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
b246dd5d
OW		 3284 break;
3285 case VCPU_SREG_SS:
3286 vmcs_write16(GUEST_SS_SELECTOR,
3287 vmcs_readl(GUEST_SS_BASE) >> 4);
3288 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3289 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3290 break;
3291 }
3292 }
6aa8b732
AK		 3293}
3294
6aa8b732
AK		 3295static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3296{
2fb92db1 3297 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3298
3299 *db = (ar >> 14) & 1;
3300 *l = (ar >> 13) & 1;
3301}
3302
89a27f4d 3303static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3304{
89a27f4d
GN		 3305 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3306 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3307}
3308
89a27f4d 3309static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3310{
89a27f4d
GN		 3311 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3312 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3313}
3314
89a27f4d 3315static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3316{
89a27f4d
GN		 3317 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3318 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3319}
3320
89a27f4d 3321static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3322{
89a27f4d
GN		 3323 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3324 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3325}
3326
648dfaa7
MG		 3327static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3328{
3329 struct kvm_segment var;
3330 u32 ar;
3331
3332 vmx_get_segment(vcpu, &var, seg);
3333 ar = vmx_segment_access_rights(&var);
3334
3335 if (var.base != (var.selector << 4))
3336 return false;
e2a610d7 3337 if (var.limit < 0xffff)
648dfaa7 3338 return false;
a81aba14 3339 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
648dfaa7
MG		 3340 return false;
3341
3342 return true;
3343}
3344
3345static bool code_segment_valid(struct kvm_vcpu *vcpu)
3346{
3347 struct kvm_segment cs;
3348 unsigned int cs_rpl;
3349
3350 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3351 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3352
1872a3f4
AK		 3353 if (cs.unusable)
3354 return false;
648dfaa7
MG		 3355 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3356 return false;
3357 if (!cs.s)
3358 return false;
1872a3f4 3359 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3360 if (cs.dpl > cs_rpl)
3361 return false;
1872a3f4 3362 } else {
648dfaa7
MG		 3363 if (cs.dpl != cs_rpl)
3364 return false;
3365 }
3366 if (!cs.present)
3367 return false;
3368
3369 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3370 return true;
3371}
3372
3373static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3374{
3375 struct kvm_segment ss;
3376 unsigned int ss_rpl;
3377
3378 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3379 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3380
1872a3f4
AK		 3381 if (ss.unusable)
3382 return true;
3383 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3384 return false;
3385 if (!ss.s)
3386 return false;
3387 if (ss.dpl != ss_rpl) /* DPL != RPL */
3388 return false;
3389 if (!ss.present)
3390 return false;
3391
3392 return true;
3393}
3394
3395static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3396{
3397 struct kvm_segment var;
3398 unsigned int rpl;
3399
3400 vmx_get_segment(vcpu, &var, seg);
3401 rpl = var.selector & SELECTOR_RPL_MASK;
3402
1872a3f4
AK		 3403 if (var.unusable)
3404 return true;
648dfaa7
MG		 3405 if (!var.s)
3406 return false;
3407 if (!var.present)
3408 return false;
3409 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3410 if (var.dpl < rpl) /* DPL < RPL */
3411 return false;
3412 }
3413
3414 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3415 * rights flags
3416 */
3417 return true;
3418}
3419
3420static bool tr_valid(struct kvm_vcpu *vcpu)
3421{
3422 struct kvm_segment tr;
3423
3424 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3425
1872a3f4
AK		 3426 if (tr.unusable)
3427 return false;
648dfaa7
MG		 3428 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3429 return false;
1872a3f4 3430 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3431 return false;
3432 if (!tr.present)
3433 return false;
3434
3435 return true;
3436}
3437
3438static bool ldtr_valid(struct kvm_vcpu *vcpu)
3439{
3440 struct kvm_segment ldtr;
3441
3442 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3443
1872a3f4
AK		 3444 if (ldtr.unusable)
3445 return true;
648dfaa7
MG		 3446 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3447 return false;
3448 if (ldtr.type != 2)
3449 return false;
3450 if (!ldtr.present)
3451 return false;
3452
3453 return true;
3454}
3455
3456static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3457{
3458 struct kvm_segment cs, ss;
3459
3460 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3461 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3462
3463 return ((cs.selector & SELECTOR_RPL_MASK) ==
3464 (ss.selector & SELECTOR_RPL_MASK));
3465}
3466
3467/*
3468 * Check if guest state is valid. Returns true if valid, false if
3469 * not.
3470 * We assume that registers are always usable
3471 */
3472static bool guest_state_valid(struct kvm_vcpu *vcpu)
3473{
3474 /* real mode guest state checks */
3eeb3288 3475 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3476 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3477 return false;
3478 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3479 return false;
3480 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3481 return false;
3482 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3483 return false;
3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3485 return false;
3486 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3487 return false;
3488 } else {
3489 /* protected mode guest state checks */
3490 if (!cs_ss_rpl_check(vcpu))
3491 return false;
3492 if (!code_segment_valid(vcpu))
3493 return false;
3494 if (!stack_segment_valid(vcpu))
3495 return false;
3496 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3497 return false;
3498 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3499 return false;
3500 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3501 return false;
3502 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3503 return false;
3504 if (!tr_valid(vcpu))
3505 return false;
3506 if (!ldtr_valid(vcpu))
3507 return false;
3508 }
3509 /* TODO:
3510 * - Add checks on RIP
3511 * - Add checks on RFLAGS
3512 */
3513
3514 return true;
3515}
3516
d77c26fc 3517static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3518{
40dcaa9f 3519 gfn_t fn;
195aefde 3520 u16 data = 0;
40dcaa9f 3521 int r, idx, ret = 0;
6aa8b732 3522
40dcaa9f
XG		 3523 idx = srcu_read_lock(&kvm->srcu);
3524 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3525 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3526 if (r < 0)
10589a46 3527 goto out;
195aefde 3528 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3529 r = kvm_write_guest_page(kvm, fn++, &data,
3530 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3531 if (r < 0)
10589a46 3532 goto out;
195aefde
IE		 3533 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3534 if (r < 0)
10589a46 3535 goto out;
195aefde
IE		 3536 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3537 if (r < 0)
10589a46 3538 goto out;
195aefde 3539 data = ~0;
10589a46
MT		 3540 r = kvm_write_guest_page(kvm, fn, &data,
3541 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3542 sizeof(u8));
195aefde 3543 if (r < 0)
10589a46
MT		 3544 goto out;
3545
3546 ret = 1;
3547out:
40dcaa9f 3548 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3549 return ret;
6aa8b732
AK		 3550}
3551
b7ebfb05
SY		 3552static int init_rmode_identity_map(struct kvm *kvm)
3553{
40dcaa9f 3554 int i, idx, r, ret;
b7ebfb05
SY		 3555 pfn_t identity_map_pfn;
3556 u32 tmp;
3557
089d034e 3558 if (!enable_ept)
b7ebfb05
SY		 3559 return 1;
3560 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3561 printk(KERN_ERR "EPT: identity-mapping pagetable "
3562 "haven't been allocated!\n");
3563 return 0;
3564 }
3565 if (likely(kvm->arch.ept_identity_pagetable_done))
3566 return 1;
3567 ret = 0;
b927a3ce 3568 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3569 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3570 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3571 if (r < 0)
3572 goto out;
3573 /* Set up identity-mapping pagetable for EPT in real mode */
3574 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3575 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3576 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3577 r = kvm_write_guest_page(kvm, identity_map_pfn,
3578 &tmp, i * sizeof(tmp), sizeof(tmp));
3579 if (r < 0)
3580 goto out;
3581 }
3582 kvm->arch.ept_identity_pagetable_done = true;
3583 ret = 1;
3584out:
40dcaa9f 3585 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3586 return ret;
3587}
3588
6aa8b732
AK		 3589static void seg_setup(int seg)
3590{
772e0318 3591 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3592 unsigned int ar;
6aa8b732
AK		 3593
3594 vmcs_write16(sf->selector, 0);
3595 vmcs_writel(sf->base, 0);
3596 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3597 if (enable_unrestricted_guest) {
3598 ar = 0x93;
3599 if (seg == VCPU_SREG_CS)
3600 ar |= 0x08; /* code segment */
3601 } else
3602 ar = 0xf3;
3603
3604 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3605}
3606
f78e0e2e
SY		 3607static int alloc_apic_access_page(struct kvm *kvm)
3608{
4484141a 3609 struct page *page;
f78e0e2e
SY		 3610 struct kvm_userspace_memory_region kvm_userspace_mem;
3611 int r = 0;
3612
79fac95e 3613 mutex_lock(&kvm->slots_lock);
bfc6d222 3614 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3615 goto out;
3616 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3617 kvm_userspace_mem.flags = 0;
3618 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3619 kvm_userspace_mem.memory_size = PAGE_SIZE;
3620 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3621 if (r)
3622 goto out;
72dc67a6 3623
4484141a
XG		 3624 page = gfn_to_page(kvm, 0xfee00);
3625 if (is_error_page(page)) {
3626 r = -EFAULT;
3627 goto out;
3628 }
3629
3630 kvm->arch.apic_access_page = page;
f78e0e2e 3631out:
79fac95e 3632 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3633 return r;
3634}
3635
b7ebfb05
SY		 3636static int alloc_identity_pagetable(struct kvm *kvm)
3637{
4484141a 3638 struct page *page;
b7ebfb05
SY		 3639 struct kvm_userspace_memory_region kvm_userspace_mem;
3640 int r = 0;
3641
79fac95e 3642 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3643 if (kvm->arch.ept_identity_pagetable)
3644 goto out;
3645 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3646 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3647 kvm_userspace_mem.guest_phys_addr =
3648 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3649 kvm_userspace_mem.memory_size = PAGE_SIZE;
3650 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3651 if (r)
3652 goto out;
3653
4484141a
XG		 3654 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3655 if (is_error_page(page)) {
3656 r = -EFAULT;
3657 goto out;
3658 }
3659
3660 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3661out:
79fac95e 3662 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3663 return r;
3664}
3665
2384d2b3
SY		 3666static void allocate_vpid(struct vcpu_vmx *vmx)
3667{
3668 int vpid;
3669
3670 vmx->vpid = 0;
919818ab 3671 if (!enable_vpid)
2384d2b3
SY		 3672 return;
3673 spin_lock(&vmx_vpid_lock);
3674 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3675 if (vpid < VMX_NR_VPIDS) {
3676 vmx->vpid = vpid;
3677 __set_bit(vpid, vmx_vpid_bitmap);
3678 }
3679 spin_unlock(&vmx_vpid_lock);
3680}
3681
cdbecfc3
LJ		 3682static void free_vpid(struct vcpu_vmx *vmx)
3683{
3684 if (!enable_vpid)
3685 return;
3686 spin_lock(&vmx_vpid_lock);
3687 if (vmx->vpid != 0)
3688 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3689 spin_unlock(&vmx_vpid_lock);
3690}
3691
5897297b 3692static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3693{
3e7c73e9 3694 int f = sizeof(unsigned long);
25c5f225
SY		 3695
3696 if (!cpu_has_vmx_msr_bitmap())
3697 return;
3698
3699 /*
3700 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3701 * have the write-low and read-high bitmap offsets the wrong way round.
3702 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3703 */
25c5f225 3704 if (msr <= 0x1fff) {
3e7c73e9
AK		 3705 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3706 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3707 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3708 msr &= 0x1fff;
3e7c73e9
AK		 3709 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3710 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3711 }
25c5f225
SY		 3712}
3713
5897297b
AK		 3714static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3715{
3716 if (!longmode_only)
3717 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3718 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3719}
3720
a3a8ff8e
NHE		 3721/*
3722 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3723 * will not change in the lifetime of the guest.
3724 * Note that host-state that does change is set elsewhere. E.g., host-state
3725 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3726 */
3727static void vmx_set_constant_host_state(void)
3728{
3729 u32 low32, high32;
3730 unsigned long tmpl;
3731 struct desc_ptr dt;
3732
b1a74bf8 3733 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3734 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3735 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3736
3737 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3738#ifdef CONFIG_X86_64
3739 /*
3740 * Load null selectors, so we can avoid reloading them in
3741 * __vmx_load_host_state(), in case userspace uses the null selectors
3742 * too (the expected case).
3743 */
3744 vmcs_write16(HOST_DS_SELECTOR, 0);
3745 vmcs_write16(HOST_ES_SELECTOR, 0);
3746#else
a3a8ff8e
NHE		 3747 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3748 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3749#endif
a3a8ff8e
NHE		 3750 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3751 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3752
3753 native_store_idt(&dt);
3754 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3755
83287ea4 3756 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3757
3758 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3759 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3760 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3761 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3762
3763 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3764 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3765 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3766 }
3767}
3768
bf8179a0
NHE		 3769static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3770{
3771 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3772 if (enable_ept)
3773 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3774 if (is_guest_mode(&vmx->vcpu))
3775 vmx->vcpu.arch.cr4_guest_owned_bits &=
3776 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3777 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3778}
3779
3780static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3781{
3782 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3783 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3784 exec_control &= ~CPU_BASED_TPR_SHADOW;
3785#ifdef CONFIG_X86_64
3786 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3787 CPU_BASED_CR8_LOAD_EXITING;
3788#endif
3789 }
3790 if (!enable_ept)
3791 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3792 CPU_BASED_CR3_LOAD_EXITING |
3793 CPU_BASED_INVLPG_EXITING;
3794 return exec_control;
3795}
3796
3797static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3798{
3799 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3800 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3801 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3802 if (vmx->vpid == 0)
3803 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3804 if (!enable_ept) {
3805 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3806 enable_unrestricted_guest = 0;
ad756a16
MJ		 3807 /* Enable INVPCID for non-ept guests may cause performance regression. */
3808 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3809 }
3810 if (!enable_unrestricted_guest)
3811 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3812 if (!ple_gap)
3813 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3814 return exec_control;
3815}
3816
ce88decf
XG		 3817static void ept_set_mmio_spte_mask(void)
3818{
3819 /*
3820 * EPT Misconfigurations can be generated if the value of bits 2:0
3821 * of an EPT paging-structure entry is 110b (write/execute).
3822 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3823 * spte.
3824 */
3825 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3826}
3827
6aa8b732
AK		 3828/*
3829 * Sets up the vmcs for emulated real mode.
3830 */
8b9cf98c 3831static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3832{
2e4ce7f5 3833#ifdef CONFIG_X86_64
6aa8b732 3834 unsigned long a;
2e4ce7f5 3835#endif
6aa8b732 3836 int i;
6aa8b732 3837
6aa8b732 3838 /* I/O */
3e7c73e9
AK		 3839 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3840 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3841
25c5f225 3842 if (cpu_has_vmx_msr_bitmap())
5897297b 3843 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3844
6aa8b732
AK		 3845 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3846
6aa8b732 3847 /* Control */
1c3d14fe
YS		 3848 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3849 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3850
bf8179a0 3851 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3852
83ff3b9d 3853 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3854 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3855 vmx_secondary_exec_control(vmx));
83ff3b9d 3856 }
f78e0e2e 3857
4b8d54f9
ZE		 3858 if (ple_gap) {
3859 vmcs_write32(PLE_GAP, ple_gap);
3860 vmcs_write32(PLE_WINDOW, ple_window);
3861 }
3862
c3707958
XG		 3863 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3864 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3865 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3866
9581d442
AK		 3867 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3868 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3869 vmx_set_constant_host_state();
05b3e0c2 3870#ifdef CONFIG_X86_64
6aa8b732
AK		 3871 rdmsrl(MSR_FS_BASE, a);
3872 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3873 rdmsrl(MSR_GS_BASE, a);
3874 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3875#else
3876 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3877 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3878#endif
3879
2cc51560
ED		 3880 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3881 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3882 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3883 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3884 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3885
468d472f 3886 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3887 u32 msr_low, msr_high;
3888 u64 host_pat;
468d472f
SY		 3889 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3890 host_pat = msr_low | ((u64) msr_high << 32);
3891 /* Write the default value follow host pat */
3892 vmcs_write64(GUEST_IA32_PAT, host_pat);
3893 /* Keep arch.pat sync with GUEST_IA32_PAT */
3894 vmx->vcpu.arch.pat = host_pat;
3895 }
3896
6aa8b732
AK		 3897 for (i = 0; i < NR_VMX_MSR; ++i) {
3898 u32 index = vmx_msr_index[i];
3899 u32 data_low, data_high;
a2fa3e9f 3900 int j = vmx->nmsrs;
6aa8b732
AK		 3901
3902 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3903 continue;
432bd6cb
AK		 3904 if (wrmsr_safe(index, data_low, data_high) < 0)
3905 continue;
26bb0981
AK		 3906 vmx->guest_msrs[j].index = i;
3907 vmx->guest_msrs[j].data = 0;
d5696725 3908 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3909 ++vmx->nmsrs;
6aa8b732 3910 }
6aa8b732 3911
1c3d14fe 3912 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3913
3914 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3915 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3916
e00c8cf2 3917 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3918 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 3919
3920 return 0;
3921}
3922
3923static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3924{
3925 struct vcpu_vmx *vmx = to_vmx(vcpu);
3926 u64 msr;
4b9d3a04 3927 int ret;
e00c8cf2 3928
5fdbf976 3929 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3930
7ffd92c5 3931 vmx->rmode.vm86_active = 0;
e00c8cf2 3932
3b86cd99
JK		 3933 vmx->soft_vnmi_blocked = 0;
3934
ad312c7c 3935 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3936 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3937 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3938 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3939 msr |= MSR_IA32_APICBASE_BSP;
3940 kvm_set_apic_base(&vmx->vcpu, msr);
3941
10ab25cd
JK		 3942 ret = fx_init(&vmx->vcpu);
3943 if (ret != 0)
3944 goto out;
e00c8cf2 3945
2fb92db1
AK		 3946 vmx_segment_cache_clear(vmx);
3947
5706be0d 3948 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3949 /*
3950 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3951 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3952 */
c5af89b6 3953 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3954 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3955 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3956 } else {
ad312c7c
ZX		 3957 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3958 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3959 }
e00c8cf2
AK		 3960
3961 seg_setup(VCPU_SREG_DS);
3962 seg_setup(VCPU_SREG_ES);
3963 seg_setup(VCPU_SREG_FS);
3964 seg_setup(VCPU_SREG_GS);
3965 seg_setup(VCPU_SREG_SS);
3966
3967 vmcs_write16(GUEST_TR_SELECTOR, 0);
3968 vmcs_writel(GUEST_TR_BASE, 0);
3969 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3970 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3971
3972 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3973 vmcs_writel(GUEST_LDTR_BASE, 0);
3974 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3975 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3976
3977 vmcs_write32(GUEST_SYSENTER_CS, 0);
3978 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3979 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3980
3981 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3982 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3983 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3984 else
5fdbf976
MT		 3985 kvm_rip_write(vcpu, 0);
3986 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3987
e00c8cf2
AK		 3988 vmcs_writel(GUEST_GDTR_BASE, 0);
3989 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3990
3991 vmcs_writel(GUEST_IDTR_BASE, 0);
3992 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3993
443381a8 3994 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3995 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3996 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3997
e00c8cf2
AK		 3998 /* Special registers */
3999 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4000
4001 setup_msrs(vmx);
4002
6aa8b732
AK		 4003 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4004
f78e0e2e
SY		 4005 if (cpu_has_vmx_tpr_shadow()) {
4006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4007 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4008 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4009 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4010 vmcs_write32(TPR_THRESHOLD, 0);
4011 }
4012
4013 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4014 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4015 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4016
2384d2b3
SY		 4017 if (vmx->vpid != 0)
4018 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4019
fa40052c 4020 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4021 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4022 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4023 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4024 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4025 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4026 vmx_fpu_activate(&vmx->vcpu);
4027 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4028
b9d762fa 4029 vpid_sync_context(vmx);
2384d2b3 4030
3200f405 4031 ret = 0;
6aa8b732 4032
a89a8fb9
MG		 4033 /* HACK: Don't enable emulation on guest boot/reset */
4034 vmx->emulation_required = 0;
4035
6aa8b732
AK		 4036out:
4037 return ret;
4038}
4039
b6f1250e
NHE		 4040/*
4041 * In nested virtualization, check if L1 asked to exit on external interrupts.
4042 * For most existing hypervisors, this will always return true.
4043 */
4044static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4045{
4046 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4047 PIN_BASED_EXT_INTR_MASK;
4048}
4049
3b86cd99
JK		 4050static void enable_irq_window(struct kvm_vcpu *vcpu)
4051{
4052 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4053 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4054 /*
4055 * We get here if vmx_interrupt_allowed() said we can't
4056 * inject to L1 now because L2 must run. Ask L2 to exit
4057 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4058 */
d6185f20 4059 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4060 return;
d6185f20 4061 }
3b86cd99
JK		 4062
4063 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4064 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4065 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4066}
4067
4068static void enable_nmi_window(struct kvm_vcpu *vcpu)
4069{
4070 u32 cpu_based_vm_exec_control;
4071
4072 if (!cpu_has_virtual_nmis()) {
4073 enable_irq_window(vcpu);
4074 return;
4075 }
4076
30bd0c4c
AK		 4077 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4078 enable_irq_window(vcpu);
4079 return;
4080 }
3b86cd99
JK		 4081 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4082 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4083 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4084}
4085
66fd3f7f 4086static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4087{
9c8cba37 4088 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4089 uint32_t intr;
4090 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4091
229456fc 4092 trace_kvm_inj_virq(irq);
2714d1d3 4093
fa89a817 4094 ++vcpu->stat.irq_injections;
7ffd92c5 4095 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4096 int inc_eip = 0;
4097 if (vcpu->arch.interrupt.soft)
4098 inc_eip = vcpu->arch.event_exit_inst_len;
4099 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4100 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4101 return;
4102 }
66fd3f7f
GN		 4103 intr = irq | INTR_INFO_VALID_MASK;
4104 if (vcpu->arch.interrupt.soft) {
4105 intr |= INTR_TYPE_SOFT_INTR;
4106 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4107 vmx->vcpu.arch.event_exit_inst_len);
4108 } else
4109 intr |= INTR_TYPE_EXT_INTR;
4110 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4111}
4112
f08864b4
SY		 4113static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4114{
66a5a347
JK		 4115 struct vcpu_vmx *vmx = to_vmx(vcpu);
4116
0b6ac343
NHE		 4117 if (is_guest_mode(vcpu))
4118 return;
4119
3b86cd99
JK		 4120 if (!cpu_has_virtual_nmis()) {
4121 /*
4122 * Tracking the NMI-blocked state in software is built upon
4123 * finding the next open IRQ window. This, in turn, depends on
4124 * well-behaving guests: They have to keep IRQs disabled at
4125 * least as long as the NMI handler runs. Otherwise we may
4126 * cause NMI nesting, maybe breaking the guest. But as this is
4127 * highly unlikely, we can live with the residual risk.
4128 */
4129 vmx->soft_vnmi_blocked = 1;
4130 vmx->vnmi_blocked_time = 0;
4131 }
4132
487b391d 4133 ++vcpu->stat.nmi_injections;
9d58b931 4134 vmx->nmi_known_unmasked = false;
7ffd92c5 4135 if (vmx->rmode.vm86_active) {
71f9833b 4136 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4137 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4138 return;
4139 }
f08864b4
SY		 4140 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4141 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4142}
4143
c4282df9 4144static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4145{
3b86cd99 4146 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4147 return 0;
33f089ca 4148
c4282df9 4149 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4150 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4151 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4152}
4153
3cfc3092
JK		 4154static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4155{
4156 if (!cpu_has_virtual_nmis())
4157 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4158 if (to_vmx(vcpu)->nmi_known_unmasked)
4159 return false;
c332c83a 4160 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4161}
4162
4163static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4164{
4165 struct vcpu_vmx *vmx = to_vmx(vcpu);
4166
4167 if (!cpu_has_virtual_nmis()) {
4168 if (vmx->soft_vnmi_blocked != masked) {
4169 vmx->soft_vnmi_blocked = masked;
4170 vmx->vnmi_blocked_time = 0;
4171 }
4172 } else {
9d58b931 4173 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4174 if (masked)
4175 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4176 GUEST_INTR_STATE_NMI);
4177 else
4178 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4179 GUEST_INTR_STATE_NMI);
4180 }
4181}
4182
78646121
GN		 4183static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4184{
b6f1250e 4185 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4186 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4187 if (to_vmx(vcpu)->nested.nested_run_pending ||
4188 (vmcs12->idt_vectoring_info_field &
4189 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4190 return 0;
4191 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4192 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4193 vmcs12->vm_exit_intr_info = 0;
4194 /* fall through to normal code, but now in L1, not L2 */
4195 }
4196
c4282df9
GN		 4197 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4198 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4199 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4200}
4201
cbc94022
IE		 4202static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4203{
4204 int ret;
4205 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4206 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4207 .guest_phys_addr = addr,
4208 .memory_size = PAGE_SIZE * 3,
4209 .flags = 0,
4210 };
4211
4212 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4213 if (ret)
4214 return ret;
bfc6d222 4215 kvm->arch.tss_addr = addr;
93ea5388
GN		 4216 if (!init_rmode_tss(kvm))
4217 return -ENOMEM;
4218
cbc94022
IE		 4219 return 0;
4220}
4221
6aa8b732
AK		 4222static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4223 int vec, u32 err_code)
4224{
b3f37707
NK		 4225 /*
4226 * Instruction with address size override prefix opcode 0x67
4227 * Cause the #SS fault with 0 error code in VM86 mode.
4228 */
4229 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4230 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4231 return 1;
77ab6db0
JK		 4232 /*
4233 * Forward all other exceptions that are valid in real mode.
4234 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4235 * the required debugging infrastructure rework.
4236 */
4237 switch (vec) {
77ab6db0 4238 case DB_VECTOR:
d0bfb940
JK		 4239 if (vcpu->guest_debug &
4240 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4241 return 0;
4242 kvm_queue_exception(vcpu, vec);
4243 return 1;
77ab6db0 4244 case BP_VECTOR:
c573cd22
JK		 4245 /*
4246 * Update instruction length as we may reinject the exception
4247 * from user space while in guest debugging mode.
4248 */
4249 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4250 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4251 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4252 return 0;
4253 /* fall through */
4254 case DE_VECTOR:
77ab6db0
JK		 4255 case OF_VECTOR:
4256 case BR_VECTOR:
4257 case UD_VECTOR:
4258 case DF_VECTOR:
4259 case SS_VECTOR:
4260 case GP_VECTOR:
4261 case MF_VECTOR:
4262 kvm_queue_exception(vcpu, vec);
4263 return 1;
4264 }
6aa8b732
AK		 4265 return 0;
4266}
4267
a0861c02
AK		 4268/*
4269 * Trigger machine check on the host. We assume all the MSRs are already set up
4270 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4271 * We pass a fake environment to the machine check handler because we want
4272 * the guest to be always treated like user space, no matter what context
4273 * it used internally.
4274 */
4275static void kvm_machine_check(void)
4276{
4277#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4278 struct pt_regs regs = {
4279 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4280 .flags = X86_EFLAGS_IF,
4281 };
4282
4283 do_machine_check(&regs, 0);
4284#endif
4285}
4286
851ba692 4287static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4288{
4289 /* already handled by vcpu_run */
4290 return 1;
4291}
4292
851ba692 4293static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4294{
1155f76a 4295 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4296 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4297 u32 intr_info, ex_no, error_code;
42dbaa5a 4298 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4299 u32 vect_info;
4300 enum emulation_result er;
4301
1155f76a 4302 vect_info = vmx->idt_vectoring_info;
88786475 4303 intr_info = vmx->exit_intr_info;
6aa8b732 4304
a0861c02 4305 if (is_machine_check(intr_info))
851ba692 4306 return handle_machine_check(vcpu);
a0861c02 4307
e4a41889 4308 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4309 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4310
4311 if (is_no_device(intr_info)) {
5fd86fcf 4312 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4313 return 1;
4314 }
4315
7aa81cc0 4316 if (is_invalid_opcode(intr_info)) {
51d8b661 4317 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4318 if (er != EMULATE_DONE)
7ee5d940 4319 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4320 return 1;
4321 }
4322
6aa8b732 4323 error_code = 0;
2e11384c 4324 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4325 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4326
4327 /*
4328 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4329 * MMIO, it is better to report an internal error.
4330 * See the comments in vmx_handle_exit.
4331 */
4332 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4333 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4334 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4335 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4336 vcpu->run->internal.ndata = 2;
4337 vcpu->run->internal.data[0] = vect_info;
4338 vcpu->run->internal.data[1] = intr_info;
4339 return 0;
4340 }
4341
6aa8b732 4342 if (is_page_fault(intr_info)) {
1439442c 4343 /* EPT won't cause page fault directly */
cf3ace79 4344 BUG_ON(enable_ept);
6aa8b732 4345 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4346 trace_kvm_page_fault(cr2, error_code);
4347
3298b75c 4348 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4349 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4350 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4351 }
4352
7ffd92c5 4353 if (vmx->rmode.vm86_active &&
6aa8b732 4354 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4355 error_code)) {
ad312c7c
ZX		 4356 if (vcpu->arch.halt_request) {
4357 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4358 return kvm_emulate_halt(vcpu);
4359 }
6aa8b732 4360 return 1;
72d6e5a0 4361 }
6aa8b732 4362
d0bfb940 4363 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4364 switch (ex_no) {
4365 case DB_VECTOR:
4366 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4367 if (!(vcpu->guest_debug &
4368 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4369 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4370 kvm_queue_exception(vcpu, DB_VECTOR);
4371 return 1;
4372 }
4373 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4374 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4375 /* fall through */
4376 case BP_VECTOR:
c573cd22
JK		 4377 /*
4378 * Update instruction length as we may reinject #BP from
4379 * user space while in guest debugging mode. Reading it for
4380 * #DB as well causes no harm, it is not used in that case.
4381 */
4382 vmx->vcpu.arch.event_exit_inst_len =
4383 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4384 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4385 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4386 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4387 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4388 break;
4389 default:
d0bfb940
JK		 4390 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4391 kvm_run->ex.exception = ex_no;
4392 kvm_run->ex.error_code = error_code;
42dbaa5a 4393 break;
6aa8b732 4394 }
6aa8b732
AK		 4395 return 0;
4396}
4397
851ba692 4398static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4399{
1165f5fe 4400 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4401 return 1;
4402}
4403
851ba692 4404static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4405{
851ba692 4406 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4407 return 0;
4408}
6aa8b732 4409
851ba692 4410static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4411{
bfdaab09 4412 unsigned long exit_qualification;
34c33d16 4413 int size, in, string;
039576c0 4414 unsigned port;
6aa8b732 4415
bfdaab09 4416 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4417 string = (exit_qualification & 16) != 0;
cf8f70bf 4418 in = (exit_qualification & 8) != 0;
e70669ab 4419
cf8f70bf 4420 ++vcpu->stat.io_exits;
e70669ab 4421
cf8f70bf 4422 if (string || in)
51d8b661 4423 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4424
cf8f70bf
GN		 4425 port = exit_qualification >> 16;
4426 size = (exit_qualification & 7) + 1;
e93f36bc 4427 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4428
4429 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4430}
4431
102d8325
IM		 4432static void
4433vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4434{
4435 /*
4436 * Patch in the VMCALL instruction:
4437 */
4438 hypercall[0] = 0x0f;
4439 hypercall[1] = 0x01;
4440 hypercall[2] = 0xc1;
102d8325
IM		 4441}
4442
0fa06071 4443/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4444static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4445{
4446 if (to_vmx(vcpu)->nested.vmxon &&
4447 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4448 return 1;
4449
4450 if (is_guest_mode(vcpu)) {
4451 /*
4452 * We get here when L2 changed cr0 in a way that did not change
4453 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4454 * but did change L0 shadowed bits. This can currently happen
4455 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4456 * loading) while pretending to allow the guest to change it.
4457 */
4458 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4459 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4460 return 1;
4461 vmcs_writel(CR0_READ_SHADOW, val);
4462 return 0;
4463 } else
4464 return kvm_set_cr0(vcpu, val);
4465}
4466
4467static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4468{
4469 if (is_guest_mode(vcpu)) {
4470 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4471 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4472 return 1;
4473 vmcs_writel(CR4_READ_SHADOW, val);
4474 return 0;
4475 } else
4476 return kvm_set_cr4(vcpu, val);
4477}
4478
4479/* called to set cr0 as approriate for clts instruction exit. */
4480static void handle_clts(struct kvm_vcpu *vcpu)
4481{
4482 if (is_guest_mode(vcpu)) {
4483 /*
4484 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4485 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4486 * just pretend it's off (also in arch.cr0 for fpu_activate).
4487 */
4488 vmcs_writel(CR0_READ_SHADOW,
4489 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4490 vcpu->arch.cr0 &= ~X86_CR0_TS;
4491 } else
4492 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4493}
4494
851ba692 4495static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4496{
229456fc 4497 unsigned long exit_qualification, val;
6aa8b732
AK		 4498 int cr;
4499 int reg;
49a9b07e 4500 int err;
6aa8b732 4501
bfdaab09 4502 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4503 cr = exit_qualification & 15;
4504 reg = (exit_qualification >> 8) & 15;
4505 switch ((exit_qualification >> 4) & 3) {
4506 case 0: /* mov to cr */
229456fc
MT		 4507 val = kvm_register_read(vcpu, reg);
4508 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4509 switch (cr) {
4510 case 0:
eeadf9e7 4511 err = handle_set_cr0(vcpu, val);
db8fcefa 4512 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4513 return 1;
4514 case 3:
2390218b 4515 err = kvm_set_cr3(vcpu, val);
db8fcefa 4516 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4517 return 1;
4518 case 4:
eeadf9e7 4519 err = handle_set_cr4(vcpu, val);
db8fcefa 4520 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4521 return 1;
0a5fff19
GN		 4522 case 8: {
4523 u8 cr8_prev = kvm_get_cr8(vcpu);
4524 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4525 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4526 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4527 if (irqchip_in_kernel(vcpu->kvm))
4528 return 1;
4529 if (cr8_prev <= cr8)
4530 return 1;
851ba692 4531 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4532 return 0;
4533 }
4b8073e4 4534 }
6aa8b732 4535 break;
25c4c276 4536 case 2: /* clts */
eeadf9e7 4537 handle_clts(vcpu);
4d4ec087 4538 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4539 skip_emulated_instruction(vcpu);
6b52d186 4540 vmx_fpu_activate(vcpu);
25c4c276 4541 return 1;
6aa8b732
AK		 4542 case 1: /*mov from cr*/
4543 switch (cr) {
4544 case 3:
9f8fe504
AK		 4545 val = kvm_read_cr3(vcpu);
4546 kvm_register_write(vcpu, reg, val);
4547 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4548 skip_emulated_instruction(vcpu);
4549 return 1;
4550 case 8:
229456fc
MT		 4551 val = kvm_get_cr8(vcpu);
4552 kvm_register_write(vcpu, reg, val);
4553 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4554 skip_emulated_instruction(vcpu);
4555 return 1;
4556 }
4557 break;
4558 case 3: /* lmsw */
a1f83a74 4559 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4560 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4561 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4562
4563 skip_emulated_instruction(vcpu);
4564 return 1;
4565 default:
4566 break;
4567 }
851ba692 4568 vcpu->run->exit_reason = 0;
a737f256 4569 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4570 (int)(exit_qualification >> 4) & 3, cr);
4571 return 0;
4572}
4573
851ba692 4574static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4575{
bfdaab09 4576 unsigned long exit_qualification;
6aa8b732
AK		 4577 int dr, reg;
4578
f2483415 4579 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4580 if (!kvm_require_cpl(vcpu, 0))
4581 return 1;
42dbaa5a
JK		 4582 dr = vmcs_readl(GUEST_DR7);
4583 if (dr & DR7_GD) {
4584 /*
4585 * As the vm-exit takes precedence over the debug trap, we
4586 * need to emulate the latter, either for the host or the
4587 * guest debugging itself.
4588 */
4589 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4590 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4591 vcpu->run->debug.arch.dr7 = dr;
4592 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4593 vmcs_readl(GUEST_CS_BASE) +
4594 vmcs_readl(GUEST_RIP);
851ba692
AK		 4595 vcpu->run->debug.arch.exception = DB_VECTOR;
4596 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4597 return 0;
4598 } else {
4599 vcpu->arch.dr7 &= ~DR7_GD;
4600 vcpu->arch.dr6 |= DR6_BD;
4601 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4602 kvm_queue_exception(vcpu, DB_VECTOR);
4603 return 1;
4604 }
4605 }
4606
bfdaab09 4607 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4608 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4609 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4610 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4611 unsigned long val;
4612 if (!kvm_get_dr(vcpu, dr, &val))
4613 kvm_register_write(vcpu, reg, val);
4614 } else
4615 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4616 skip_emulated_instruction(vcpu);
4617 return 1;
4618}
4619
020df079
GN		 4620static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4621{
4622 vmcs_writel(GUEST_DR7, val);
4623}
4624
851ba692 4625static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4626{
06465c5a
AK		 4627 kvm_emulate_cpuid(vcpu);
4628 return 1;
6aa8b732
AK		 4629}
4630
851ba692 4631static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4632{
ad312c7c 4633 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4634 u64 data;
4635
4636 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4637 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4638 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4639 return 1;
4640 }
4641
229456fc 4642 trace_kvm_msr_read(ecx, data);
2714d1d3 4643
6aa8b732 4644 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4645 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4646 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4647 skip_emulated_instruction(vcpu);
4648 return 1;
4649}
4650
851ba692 4651static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4652{
8fe8ab46 4653 struct msr_data msr;
ad312c7c
ZX		 4654 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4655 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4656 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4657
8fe8ab46
WA		 4658 msr.data = data;
4659 msr.index = ecx;
4660 msr.host_initiated = false;
4661 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4662 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4663 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4664 return 1;
4665 }
4666
59200273 4667 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4668 skip_emulated_instruction(vcpu);
4669 return 1;
4670}
4671
851ba692 4672static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4673{
3842d135 4674 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4675 return 1;
4676}
4677
851ba692 4678static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4679{
85f455f7
ED		 4680 u32 cpu_based_vm_exec_control;
4681
4682 /* clear pending irq */
4683 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4684 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4685 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4686
3842d135
AK		 4687 kvm_make_request(KVM_REQ_EVENT, vcpu);
4688
a26bf12a 4689 ++vcpu->stat.irq_window_exits;
2714d1d3 4690
c1150d8c
DL		 4691 /*
4692 * If the user space waits to inject interrupts, exit as soon as
4693 * possible
4694 */
8061823a 4695 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4696 vcpu->run->request_interrupt_window &&
8061823a 4697 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4698 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4699 return 0;
4700 }
6aa8b732
AK		 4701 return 1;
4702}
4703
851ba692 4704static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4705{
4706 skip_emulated_instruction(vcpu);
d3bef15f 4707 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4708}
4709
851ba692 4710static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4711{
510043da 4712 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4713 kvm_emulate_hypercall(vcpu);
4714 return 1;
c21415e8
IM		 4715}
4716
ec25d5e6
GN		 4717static int handle_invd(struct kvm_vcpu *vcpu)
4718{
51d8b661 4719 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4720}
4721
851ba692 4722static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4723{
f9c617f6 4724 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4725
4726 kvm_mmu_invlpg(vcpu, exit_qualification);
4727 skip_emulated_instruction(vcpu);
4728 return 1;
4729}
4730
fee84b07
AK		 4731static int handle_rdpmc(struct kvm_vcpu *vcpu)
4732{
4733 int err;
4734
4735 err = kvm_rdpmc(vcpu);
4736 kvm_complete_insn_gp(vcpu, err);
4737
4738 return 1;
4739}
4740
851ba692 4741static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4742{
4743 skip_emulated_instruction(vcpu);
f5f48ee1 4744 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4745 return 1;
4746}
4747
2acf923e
DC		 4748static int handle_xsetbv(struct kvm_vcpu *vcpu)
4749{
4750 u64 new_bv = kvm_read_edx_eax(vcpu);
4751 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4752
4753 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4754 skip_emulated_instruction(vcpu);
4755 return 1;
4756}
4757
851ba692 4758static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4759{
58fbbf26
KT		 4760 if (likely(fasteoi)) {
4761 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4762 int access_type, offset;
4763
4764 access_type = exit_qualification & APIC_ACCESS_TYPE;
4765 offset = exit_qualification & APIC_ACCESS_OFFSET;
4766 /*
4767 * Sane guest uses MOV to write EOI, with written value
4768 * not cared. So make a short-circuit here by avoiding
4769 * heavy instruction emulation.
4770 */
4771 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4772 (offset == APIC_EOI)) {
4773 kvm_lapic_set_eoi(vcpu);
4774 skip_emulated_instruction(vcpu);
4775 return 1;
4776 }
4777 }
51d8b661 4778 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4779}
4780
851ba692 4781static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4782{
60637aac 4783 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4784 unsigned long exit_qualification;
e269fb21
JK		 4785 bool has_error_code = false;
4786 u32 error_code = 0;
37817f29 4787 u16 tss_selector;
7f3d35fd 4788 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4789
4790 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4791 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4792 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4793
4794 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4795
4796 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4797 if (reason == TASK_SWITCH_GATE && idt_v) {
4798 switch (type) {
4799 case INTR_TYPE_NMI_INTR:
4800 vcpu->arch.nmi_injected = false;
654f06fc 4801 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4802 break;
4803 case INTR_TYPE_EXT_INTR:
66fd3f7f 4804 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4805 kvm_clear_interrupt_queue(vcpu);
4806 break;
4807 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4808 if (vmx->idt_vectoring_info &
4809 VECTORING_INFO_DELIVER_CODE_MASK) {
4810 has_error_code = true;
4811 error_code =
4812 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4813 }
4814 /* fall through */
64a7ec06
GN		 4815 case INTR_TYPE_SOFT_EXCEPTION:
4816 kvm_clear_exception_queue(vcpu);
4817 break;
4818 default:
4819 break;
4820 }
60637aac 4821 }
37817f29
IE		 4822 tss_selector = exit_qualification;
4823
64a7ec06
GN		 4824 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4825 type != INTR_TYPE_EXT_INTR &&
4826 type != INTR_TYPE_NMI_INTR))
4827 skip_emulated_instruction(vcpu);
4828
7f3d35fd
KW		 4829 if (kvm_task_switch(vcpu, tss_selector,
4830 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4831 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4832 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4833 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4834 vcpu->run->internal.ndata = 0;
42dbaa5a 4835 return 0;
acb54517 4836 }
42dbaa5a
JK		 4837
4838 /* clear all local breakpoint enable flags */
4839 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4840
4841 /*
4842 * TODO: What about debug traps on tss switch?
4843 * Are we supposed to inject them and update dr6?
4844 */
4845
4846 return 1;
37817f29
IE		 4847}
4848
851ba692 4849static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4850{
f9c617f6 4851 unsigned long exit_qualification;
1439442c 4852 gpa_t gpa;
4f5982a5 4853 u32 error_code;
1439442c 4854 int gla_validity;
1439442c 4855
f9c617f6 4856 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4857
4858 if (exit_qualification & (1 << 6)) {
4859 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4860 return -EINVAL;
1439442c
SY		 4861 }
4862
4863 gla_validity = (exit_qualification >> 7) & 0x3;
4864 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4865 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4866 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4867 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4868 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4869 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4870 (long unsigned int)exit_qualification);
851ba692
AK		 4871 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4872 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4873 return 0;
1439442c
SY		 4874 }
4875
4876 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4877 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4878
4879 /* It is a write fault? */
4880 error_code = exit_qualification & (1U << 1);
4881 /* ept page table is present? */
4882 error_code |= (exit_qualification >> 3) & 0x1;
4883
4884 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4885}
4886
68f89400
MT		 4887static u64 ept_rsvd_mask(u64 spte, int level)
4888{
4889 int i;
4890 u64 mask = 0;
4891
4892 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4893 mask |= (1ULL << i);
4894
4895 if (level > 2)
4896 /* bits 7:3 reserved */
4897 mask |= 0xf8;
4898 else if (level == 2) {
4899 if (spte & (1ULL << 7))
4900 /* 2MB ref, bits 20:12 reserved */
4901 mask |= 0x1ff000;
4902 else
4903 /* bits 6:3 reserved */
4904 mask |= 0x78;
4905 }
4906
4907 return mask;
4908}
4909
4910static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4911 int level)
4912{
4913 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4914
4915 /* 010b (write-only) */
4916 WARN_ON((spte & 0x7) == 0x2);
4917
4918 /* 110b (write/execute) */
4919 WARN_ON((spte & 0x7) == 0x6);
4920
4921 /* 100b (execute-only) and value not supported by logical processor */
4922 if (!cpu_has_vmx_ept_execute_only())
4923 WARN_ON((spte & 0x7) == 0x4);
4924
4925 /* not 000b */
4926 if ((spte & 0x7)) {
4927 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4928
4929 if (rsvd_bits != 0) {
4930 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4931 __func__, rsvd_bits);
4932 WARN_ON(1);
4933 }
4934
4935 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4936 u64 ept_mem_type = (spte & 0x38) >> 3;
4937
4938 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4939 ept_mem_type == 7) {
4940 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4941 __func__, ept_mem_type);
4942 WARN_ON(1);
4943 }
4944 }
4945 }
4946}
4947
851ba692 4948static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4949{
4950 u64 sptes[4];
ce88decf 4951 int nr_sptes, i, ret;
68f89400
MT		 4952 gpa_t gpa;
4953
4954 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4955
ce88decf
XG		 4956 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4957 if (likely(ret == 1))
4958 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4959 EMULATE_DONE;
4960 if (unlikely(!ret))
4961 return 1;
4962
4963 /* It is the real ept misconfig */
68f89400
MT		 4964 printk(KERN_ERR "EPT: Misconfiguration.\n");
4965 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4966
4967 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4968
4969 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4970 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4971
851ba692
AK		 4972 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4973 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4974
4975 return 0;
4976}
4977
851ba692 4978static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4979{
4980 u32 cpu_based_vm_exec_control;
4981
4982 /* clear pending NMI */
4983 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4984 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4986 ++vcpu->stat.nmi_window_exits;
3842d135 4987 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4988
4989 return 1;
4990}
4991
80ced186 4992static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4993{
8b3079a5
AK		 4994 struct vcpu_vmx *vmx = to_vmx(vcpu);
4995 enum emulation_result err = EMULATE_DONE;
80ced186 4996 int ret = 1;
49e9d557
AK		 4997 u32 cpu_exec_ctrl;
4998 bool intr_window_requested;
b8405c18 4999 unsigned count = 130;
49e9d557
AK		 5000
5001 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5002 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5003
b8405c18 5004 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5005 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5006 return handle_interrupt_window(&vmx->vcpu);
5007
de87dcdd
AK		 5008 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5009 return 1;
5010
51d8b661 5011 err = emulate_instruction(vcpu, 0);
ea953ef0 5012
80ced186
MG		 5013 if (err == EMULATE_DO_MMIO) {
5014 ret = 0;
5015 goto out;
5016 }
1d5a4d9b 5017
de5f70e0
AK		 5018 if (err != EMULATE_DONE) {
5019 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5020 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5021 vcpu->run->internal.ndata = 0;
6d77dbfc 5022 return 0;
de5f70e0 5023 }
ea953ef0
MG		 5024
5025 if (signal_pending(current))
80ced186 5026 goto out;
ea953ef0
MG		 5027 if (need_resched())
5028 schedule();
5029 }
5030
7c068e45 5031 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5032out:
5033 return ret;
ea953ef0
MG		 5034}
5035
4b8d54f9
ZE		 5036/*
5037 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5038 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5039 */
9fb41ba8 5040static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5041{
5042 skip_emulated_instruction(vcpu);
5043 kvm_vcpu_on_spin(vcpu);
5044
5045 return 1;
5046}
5047
59708670
SY		 5048static int handle_invalid_op(struct kvm_vcpu *vcpu)
5049{
5050 kvm_queue_exception(vcpu, UD_VECTOR);
5051 return 1;
5052}
5053
ff2f6fe9
NHE		 5054/*
5055 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5056 * We could reuse a single VMCS for all the L2 guests, but we also want the
5057 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5058 * allows keeping them loaded on the processor, and in the future will allow
5059 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5060 * every entry if they never change.
5061 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5062 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5063 *
5064 * The following functions allocate and free a vmcs02 in this pool.
5065 */
5066
5067/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5068static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5069{
5070 struct vmcs02_list *item;
5071 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5072 if (item->vmptr == vmx->nested.current_vmptr) {
5073 list_move(&item->list, &vmx->nested.vmcs02_pool);
5074 return &item->vmcs02;
5075 }
5076
5077 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5078 /* Recycle the least recently used VMCS. */
5079 item = list_entry(vmx->nested.vmcs02_pool.prev,
5080 struct vmcs02_list, list);
5081 item->vmptr = vmx->nested.current_vmptr;
5082 list_move(&item->list, &vmx->nested.vmcs02_pool);
5083 return &item->vmcs02;
5084 }
5085
5086 /* Create a new VMCS */
5087 item = (struct vmcs02_list *)
5088 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5089 if (!item)
5090 return NULL;
5091 item->vmcs02.vmcs = alloc_vmcs();
5092 if (!item->vmcs02.vmcs) {
5093 kfree(item);
5094 return NULL;
5095 }
5096 loaded_vmcs_init(&item->vmcs02);
5097 item->vmptr = vmx->nested.current_vmptr;
5098 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5099 vmx->nested.vmcs02_num++;
5100 return &item->vmcs02;
5101}
5102
5103/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5104static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5105{
5106 struct vmcs02_list *item;
5107 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5108 if (item->vmptr == vmptr) {
5109 free_loaded_vmcs(&item->vmcs02);
5110 list_del(&item->list);
5111 kfree(item);
5112 vmx->nested.vmcs02_num--;
5113 return;
5114 }
5115}
5116
5117/*
5118 * Free all VMCSs saved for this vcpu, except the one pointed by
5119 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5120 * currently used, if running L2), and vmcs01 when running L2.
5121 */
5122static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5123{
5124 struct vmcs02_list *item, *n;
5125 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5126 if (vmx->loaded_vmcs != &item->vmcs02)
5127 free_loaded_vmcs(&item->vmcs02);
5128 list_del(&item->list);
5129 kfree(item);
5130 }
5131 vmx->nested.vmcs02_num = 0;
5132
5133 if (vmx->loaded_vmcs != &vmx->vmcs01)
5134 free_loaded_vmcs(&vmx->vmcs01);
5135}
5136
ec378aee
NHE		 5137/*
5138 * Emulate the VMXON instruction.
5139 * Currently, we just remember that VMX is active, and do not save or even
5140 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5141 * do not currently need to store anything in that guest-allocated memory
5142 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5143 * argument is different from the VMXON pointer (which the spec says they do).
5144 */
5145static int handle_vmon(struct kvm_vcpu *vcpu)
5146{
5147 struct kvm_segment cs;
5148 struct vcpu_vmx *vmx = to_vmx(vcpu);
5149
5150 /* The Intel VMX Instruction Reference lists a bunch of bits that
5151 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5152 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5153 * Otherwise, we should fail with #UD. We test these now:
5154 */
5155 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5156 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5157 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5158 kvm_queue_exception(vcpu, UD_VECTOR);
5159 return 1;
5160 }
5161
5162 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5163 if (is_long_mode(vcpu) && !cs.l) {
5164 kvm_queue_exception(vcpu, UD_VECTOR);
5165 return 1;
5166 }
5167
5168 if (vmx_get_cpl(vcpu)) {
5169 kvm_inject_gp(vcpu, 0);
5170 return 1;
5171 }
5172
ff2f6fe9
NHE		 5173 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5174 vmx->nested.vmcs02_num = 0;
5175
ec378aee
NHE		 5176 vmx->nested.vmxon = true;
5177
5178 skip_emulated_instruction(vcpu);
5179 return 1;
5180}
5181
5182/*
5183 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5184 * for running VMX instructions (except VMXON, whose prerequisites are
5185 * slightly different). It also specifies what exception to inject otherwise.
5186 */
5187static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5188{
5189 struct kvm_segment cs;
5190 struct vcpu_vmx *vmx = to_vmx(vcpu);
5191
5192 if (!vmx->nested.vmxon) {
5193 kvm_queue_exception(vcpu, UD_VECTOR);
5194 return 0;
5195 }
5196
5197 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5198 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5199 (is_long_mode(vcpu) && !cs.l)) {
5200 kvm_queue_exception(vcpu, UD_VECTOR);
5201 return 0;
5202 }
5203
5204 if (vmx_get_cpl(vcpu)) {
5205 kvm_inject_gp(vcpu, 0);
5206 return 0;
5207 }
5208
5209 return 1;
5210}
5211
5212/*
5213 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5214 * just stops using VMX.
5215 */
5216static void free_nested(struct vcpu_vmx *vmx)
5217{
5218 if (!vmx->nested.vmxon)
5219 return;
5220 vmx->nested.vmxon = false;
a9d30f33
NHE		 5221 if (vmx->nested.current_vmptr != -1ull) {
5222 kunmap(vmx->nested.current_vmcs12_page);
5223 nested_release_page(vmx->nested.current_vmcs12_page);
5224 vmx->nested.current_vmptr = -1ull;
5225 vmx->nested.current_vmcs12 = NULL;
5226 }
fe3ef05c
NHE		 5227 /* Unpin physical memory we referred to in current vmcs02 */
5228 if (vmx->nested.apic_access_page) {
5229 nested_release_page(vmx->nested.apic_access_page);
5230 vmx->nested.apic_access_page = 0;
5231 }
ff2f6fe9
NHE		 5232
5233 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5234}
5235
5236/* Emulate the VMXOFF instruction */
5237static int handle_vmoff(struct kvm_vcpu *vcpu)
5238{
5239 if (!nested_vmx_check_permission(vcpu))
5240 return 1;
5241 free_nested(to_vmx(vcpu));
5242 skip_emulated_instruction(vcpu);
5243 return 1;
5244}
5245
064aea77
NHE		 5246/*
5247 * Decode the memory-address operand of a vmx instruction, as recorded on an
5248 * exit caused by such an instruction (run by a guest hypervisor).
5249 * On success, returns 0. When the operand is invalid, returns 1 and throws
5250 * #UD or #GP.
5251 */
5252static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5253 unsigned long exit_qualification,
5254 u32 vmx_instruction_info, gva_t *ret)
5255{
5256 /*
5257 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5258 * Execution", on an exit, vmx_instruction_info holds most of the
5259 * addressing components of the operand. Only the displacement part
5260 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5261 * For how an actual address is calculated from all these components,
5262 * refer to Vol. 1, "Operand Addressing".
5263 */
5264 int scaling = vmx_instruction_info & 3;
5265 int addr_size = (vmx_instruction_info >> 7) & 7;
5266 bool is_reg = vmx_instruction_info & (1u << 10);
5267 int seg_reg = (vmx_instruction_info >> 15) & 7;
5268 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5269 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5270 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5271 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5272
5273 if (is_reg) {
5274 kvm_queue_exception(vcpu, UD_VECTOR);
5275 return 1;
5276 }
5277
5278 /* Addr = segment_base + offset */
5279 /* offset = base + [index * scale] + displacement */
5280 *ret = vmx_get_segment_base(vcpu, seg_reg);
5281 if (base_is_valid)
5282 *ret += kvm_register_read(vcpu, base_reg);
5283 if (index_is_valid)
5284 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5285 *ret += exit_qualification; /* holds the displacement */
5286
5287 if (addr_size == 1) /* 32 bit */
5288 *ret &= 0xffffffff;
5289
5290 /*
5291 * TODO: throw #GP (and return 1) in various cases that the VM*
5292 * instructions require it - e.g., offset beyond segment limit,
5293 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5294 * address, and so on. Currently these are not checked.
5295 */
5296 return 0;
5297}
5298
0140caea
NHE		 5299/*
5300 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5301 * set the success or error code of an emulated VMX instruction, as specified
5302 * by Vol 2B, VMX Instruction Reference, "Conventions".
5303 */
5304static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5305{
5306 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5307 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5308 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5309}
5310
5311static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5312{
5313 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5314 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5315 X86_EFLAGS_SF | X86_EFLAGS_OF))
5316 | X86_EFLAGS_CF);
5317}
5318
5319static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5320 u32 vm_instruction_error)
5321{
5322 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5323 /*
5324 * failValid writes the error number to the current VMCS, which
5325 * can't be done there isn't a current VMCS.
5326 */
5327 nested_vmx_failInvalid(vcpu);
5328 return;
5329 }
5330 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5331 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5332 X86_EFLAGS_SF | X86_EFLAGS_OF))
5333 | X86_EFLAGS_ZF);
5334 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5335}
5336
27d6c865
NHE		 5337/* Emulate the VMCLEAR instruction */
5338static int handle_vmclear(struct kvm_vcpu *vcpu)
5339{
5340 struct vcpu_vmx *vmx = to_vmx(vcpu);
5341 gva_t gva;
5342 gpa_t vmptr;
5343 struct vmcs12 *vmcs12;
5344 struct page *page;
5345 struct x86_exception e;
5346
5347 if (!nested_vmx_check_permission(vcpu))
5348 return 1;
5349
5350 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5351 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5352 return 1;
5353
5354 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5355 sizeof(vmptr), &e)) {
5356 kvm_inject_page_fault(vcpu, &e);
5357 return 1;
5358 }
5359
5360 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5361 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5362 skip_emulated_instruction(vcpu);
5363 return 1;
5364 }
5365
5366 if (vmptr == vmx->nested.current_vmptr) {
5367 kunmap(vmx->nested.current_vmcs12_page);
5368 nested_release_page(vmx->nested.current_vmcs12_page);
5369 vmx->nested.current_vmptr = -1ull;
5370 vmx->nested.current_vmcs12 = NULL;
5371 }
5372
5373 page = nested_get_page(vcpu, vmptr);
5374 if (page == NULL) {
5375 /*
5376 * For accurate processor emulation, VMCLEAR beyond available
5377 * physical memory should do nothing at all. However, it is
5378 * possible that a nested vmx bug, not a guest hypervisor bug,
5379 * resulted in this case, so let's shut down before doing any
5380 * more damage:
5381 */
5382 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5383 return 1;
5384 }
5385 vmcs12 = kmap(page);
5386 vmcs12->launch_state = 0;
5387 kunmap(page);
5388 nested_release_page(page);
5389
5390 nested_free_vmcs02(vmx, vmptr);
5391
5392 skip_emulated_instruction(vcpu);
5393 nested_vmx_succeed(vcpu);
5394 return 1;
5395}
5396
cd232ad0
NHE		 5397static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5398
5399/* Emulate the VMLAUNCH instruction */
5400static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5401{
5402 return nested_vmx_run(vcpu, true);
5403}
5404
5405/* Emulate the VMRESUME instruction */
5406static int handle_vmresume(struct kvm_vcpu *vcpu)
5407{
5408
5409 return nested_vmx_run(vcpu, false);
5410}
5411
49f705c5
NHE		 5412enum vmcs_field_type {
5413 VMCS_FIELD_TYPE_U16 = 0,
5414 VMCS_FIELD_TYPE_U64 = 1,
5415 VMCS_FIELD_TYPE_U32 = 2,
5416 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5417};
5418
5419static inline int vmcs_field_type(unsigned long field)
5420{
5421 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5422 return VMCS_FIELD_TYPE_U32;
5423 return (field >> 13) & 0x3 ;
5424}
5425
5426static inline int vmcs_field_readonly(unsigned long field)
5427{
5428 return (((field >> 10) & 0x3) == 1);
5429}
5430
5431/*
5432 * Read a vmcs12 field. Since these can have varying lengths and we return
5433 * one type, we chose the biggest type (u64) and zero-extend the return value
5434 * to that size. Note that the caller, handle_vmread, might need to use only
5435 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5436 * 64-bit fields are to be returned).
5437 */
5438static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5439 unsigned long field, u64 *ret)
5440{
5441 short offset = vmcs_field_to_offset(field);
5442 char *p;
5443
5444 if (offset < 0)
5445 return 0;
5446
5447 p = ((char *)(get_vmcs12(vcpu))) + offset;
5448
5449 switch (vmcs_field_type(field)) {
5450 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5451 *ret = *((natural_width *)p);
5452 return 1;
5453 case VMCS_FIELD_TYPE_U16:
5454 *ret = *((u16 *)p);
5455 return 1;
5456 case VMCS_FIELD_TYPE_U32:
5457 *ret = *((u32 *)p);
5458 return 1;
5459 case VMCS_FIELD_TYPE_U64:
5460 *ret = *((u64 *)p);
5461 return 1;
5462 default:
5463 return 0; /* can never happen. */
5464 }
5465}
5466
5467/*
5468 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5469 * used before) all generate the same failure when it is missing.
5470 */
5471static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5472{
5473 struct vcpu_vmx *vmx = to_vmx(vcpu);
5474 if (vmx->nested.current_vmptr == -1ull) {
5475 nested_vmx_failInvalid(vcpu);
5476 skip_emulated_instruction(vcpu);
5477 return 0;
5478 }
5479 return 1;
5480}
5481
5482static int handle_vmread(struct kvm_vcpu *vcpu)
5483{
5484 unsigned long field;
5485 u64 field_value;
5486 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5487 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5488 gva_t gva = 0;
5489
5490 if (!nested_vmx_check_permission(vcpu) ||
5491 !nested_vmx_check_vmcs12(vcpu))
5492 return 1;
5493
5494 /* Decode instruction info and find the field to read */
5495 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5496 /* Read the field, zero-extended to a u64 field_value */
5497 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5498 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5499 skip_emulated_instruction(vcpu);
5500 return 1;
5501 }
5502 /*
5503 * Now copy part of this value to register or memory, as requested.
5504 * Note that the number of bits actually copied is 32 or 64 depending
5505 * on the guest's mode (32 or 64 bit), not on the given field's length.
5506 */
5507 if (vmx_instruction_info & (1u << 10)) {
5508 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5509 field_value);
5510 } else {
5511 if (get_vmx_mem_address(vcpu, exit_qualification,
5512 vmx_instruction_info, &gva))
5513 return 1;
5514 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5515 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5516 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5517 }
5518
5519 nested_vmx_succeed(vcpu);
5520 skip_emulated_instruction(vcpu);
5521 return 1;
5522}
5523
5524
5525static int handle_vmwrite(struct kvm_vcpu *vcpu)
5526{
5527 unsigned long field;
5528 gva_t gva;
5529 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5530 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5531 char *p;
5532 short offset;
5533 /* The value to write might be 32 or 64 bits, depending on L1's long
5534 * mode, and eventually we need to write that into a field of several
5535 * possible lengths. The code below first zero-extends the value to 64
5536 * bit (field_value), and then copies only the approriate number of
5537 * bits into the vmcs12 field.
5538 */
5539 u64 field_value = 0;
5540 struct x86_exception e;
5541
5542 if (!nested_vmx_check_permission(vcpu) ||
5543 !nested_vmx_check_vmcs12(vcpu))
5544 return 1;
5545
5546 if (vmx_instruction_info & (1u << 10))
5547 field_value = kvm_register_read(vcpu,
5548 (((vmx_instruction_info) >> 3) & 0xf));
5549 else {
5550 if (get_vmx_mem_address(vcpu, exit_qualification,
5551 vmx_instruction_info, &gva))
5552 return 1;
5553 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5554 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5555 kvm_inject_page_fault(vcpu, &e);
5556 return 1;
5557 }
5558 }
5559
5560
5561 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5562 if (vmcs_field_readonly(field)) {
5563 nested_vmx_failValid(vcpu,
5564 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5565 skip_emulated_instruction(vcpu);
5566 return 1;
5567 }
5568
5569 offset = vmcs_field_to_offset(field);
5570 if (offset < 0) {
5571 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5572 skip_emulated_instruction(vcpu);
5573 return 1;
5574 }
5575 p = ((char *) get_vmcs12(vcpu)) + offset;
5576
5577 switch (vmcs_field_type(field)) {
5578 case VMCS_FIELD_TYPE_U16:
5579 *(u16 *)p = field_value;
5580 break;
5581 case VMCS_FIELD_TYPE_U32:
5582 *(u32 *)p = field_value;
5583 break;
5584 case VMCS_FIELD_TYPE_U64:
5585 *(u64 *)p = field_value;
5586 break;
5587 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5588 *(natural_width *)p = field_value;
5589 break;
5590 default:
5591 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5592 skip_emulated_instruction(vcpu);
5593 return 1;
5594 }
5595
5596 nested_vmx_succeed(vcpu);
5597 skip_emulated_instruction(vcpu);
5598 return 1;
5599}
5600
63846663
NHE		 5601/* Emulate the VMPTRLD instruction */
5602static int handle_vmptrld(struct kvm_vcpu *vcpu)
5603{
5604 struct vcpu_vmx *vmx = to_vmx(vcpu);
5605 gva_t gva;
5606 gpa_t vmptr;
5607 struct x86_exception e;
5608
5609 if (!nested_vmx_check_permission(vcpu))
5610 return 1;
5611
5612 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5613 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5614 return 1;
5615
5616 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5617 sizeof(vmptr), &e)) {
5618 kvm_inject_page_fault(vcpu, &e);
5619 return 1;
5620 }
5621
5622 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5623 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5624 skip_emulated_instruction(vcpu);
5625 return 1;
5626 }
5627
5628 if (vmx->nested.current_vmptr != vmptr) {
5629 struct vmcs12 *new_vmcs12;
5630 struct page *page;
5631 page = nested_get_page(vcpu, vmptr);
5632 if (page == NULL) {
5633 nested_vmx_failInvalid(vcpu);
5634 skip_emulated_instruction(vcpu);
5635 return 1;
5636 }
5637 new_vmcs12 = kmap(page);
5638 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5639 kunmap(page);
5640 nested_release_page_clean(page);
5641 nested_vmx_failValid(vcpu,
5642 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5643 skip_emulated_instruction(vcpu);
5644 return 1;
5645 }
5646 if (vmx->nested.current_vmptr != -1ull) {
5647 kunmap(vmx->nested.current_vmcs12_page);
5648 nested_release_page(vmx->nested.current_vmcs12_page);
5649 }
5650
5651 vmx->nested.current_vmptr = vmptr;
5652 vmx->nested.current_vmcs12 = new_vmcs12;
5653 vmx->nested.current_vmcs12_page = page;
5654 }
5655
5656 nested_vmx_succeed(vcpu);
5657 skip_emulated_instruction(vcpu);
5658 return 1;
5659}
5660
6a4d7550
NHE		 5661/* Emulate the VMPTRST instruction */
5662static int handle_vmptrst(struct kvm_vcpu *vcpu)
5663{
5664 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5665 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5666 gva_t vmcs_gva;
5667 struct x86_exception e;
5668
5669 if (!nested_vmx_check_permission(vcpu))
5670 return 1;
5671
5672 if (get_vmx_mem_address(vcpu, exit_qualification,
5673 vmx_instruction_info, &vmcs_gva))
5674 return 1;
5675 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5676 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5677 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5678 sizeof(u64), &e)) {
5679 kvm_inject_page_fault(vcpu, &e);
5680 return 1;
5681 }
5682 nested_vmx_succeed(vcpu);
5683 skip_emulated_instruction(vcpu);
5684 return 1;
5685}
5686
6aa8b732
AK		 5687/*
5688 * The exit handlers return 1 if the exit was handled fully and guest execution
5689 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5690 * to be done to userspace and return 0.
5691 */
772e0318 5692static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5693 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5694 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5695 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5696 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5697 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5698 [EXIT_REASON_CR_ACCESS] = handle_cr,
5699 [EXIT_REASON_DR_ACCESS] = handle_dr,
5700 [EXIT_REASON_CPUID] = handle_cpuid,
5701 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5702 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5703 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5704 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5705 [EXIT_REASON_INVD] = handle_invd,
a7052897 5706 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5707 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5708 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5709 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5710 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5711 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5712 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5713 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5714 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5715 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5716 [EXIT_REASON_VMOFF] = handle_vmoff,
5717 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5718 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5719 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5720 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5721 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5722 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5723 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5724 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5725 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5726 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5727 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5728 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5729};
5730
5731static const int kvm_vmx_max_exit_handlers =
50a3485c 5732 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5733
644d711a
NHE		 5734/*
5735 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5736 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5737 * disinterest in the current event (read or write a specific MSR) by using an
5738 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5739 */
5740static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5741 struct vmcs12 *vmcs12, u32 exit_reason)
5742{
5743 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5744 gpa_t bitmap;
5745
5746 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5747 return 1;
5748
5749 /*
5750 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5751 * for the four combinations of read/write and low/high MSR numbers.
5752 * First we need to figure out which of the four to use:
5753 */
5754 bitmap = vmcs12->msr_bitmap;
5755 if (exit_reason == EXIT_REASON_MSR_WRITE)
5756 bitmap += 2048;
5757 if (msr_index >= 0xc0000000) {
5758 msr_index -= 0xc0000000;
5759 bitmap += 1024;
5760 }
5761
5762 /* Then read the msr_index'th bit from this bitmap: */
5763 if (msr_index < 1024*8) {
5764 unsigned char b;
5765 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5766 return 1 & (b >> (msr_index & 7));
5767 } else
5768 return 1; /* let L1 handle the wrong parameter */
5769}
5770
5771/*
5772 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5773 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5774 * intercept (via guest_host_mask etc.) the current event.
5775 */
5776static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5777 struct vmcs12 *vmcs12)
5778{
5779 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5780 int cr = exit_qualification & 15;
5781 int reg = (exit_qualification >> 8) & 15;
5782 unsigned long val = kvm_register_read(vcpu, reg);
5783
5784 switch ((exit_qualification >> 4) & 3) {
5785 case 0: /* mov to cr */
5786 switch (cr) {
5787 case 0:
5788 if (vmcs12->cr0_guest_host_mask &
5789 (val ^ vmcs12->cr0_read_shadow))
5790 return 1;
5791 break;
5792 case 3:
5793 if ((vmcs12->cr3_target_count >= 1 &&
5794 vmcs12->cr3_target_value0 == val) ||
5795 (vmcs12->cr3_target_count >= 2 &&
5796 vmcs12->cr3_target_value1 == val) ||
5797 (vmcs12->cr3_target_count >= 3 &&
5798 vmcs12->cr3_target_value2 == val) ||
5799 (vmcs12->cr3_target_count >= 4 &&
5800 vmcs12->cr3_target_value3 == val))
5801 return 0;
5802 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5803 return 1;
5804 break;
5805 case 4:
5806 if (vmcs12->cr4_guest_host_mask &
5807 (vmcs12->cr4_read_shadow ^ val))
5808 return 1;
5809 break;
5810 case 8:
5811 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5812 return 1;
5813 break;
5814 }
5815 break;
5816 case 2: /* clts */
5817 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5818 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5819 return 1;
5820 break;
5821 case 1: /* mov from cr */
5822 switch (cr) {
5823 case 3:
5824 if (vmcs12->cpu_based_vm_exec_control &
5825 CPU_BASED_CR3_STORE_EXITING)
5826 return 1;
5827 break;
5828 case 8:
5829 if (vmcs12->cpu_based_vm_exec_control &
5830 CPU_BASED_CR8_STORE_EXITING)
5831 return 1;
5832 break;
5833 }
5834 break;
5835 case 3: /* lmsw */
5836 /*
5837 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5838 * cr0. Other attempted changes are ignored, with no exit.
5839 */
5840 if (vmcs12->cr0_guest_host_mask & 0xe &
5841 (val ^ vmcs12->cr0_read_shadow))
5842 return 1;
5843 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5844 !(vmcs12->cr0_read_shadow & 0x1) &&
5845 (val & 0x1))
5846 return 1;
5847 break;
5848 }
5849 return 0;
5850}
5851
5852/*
5853 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5854 * should handle it ourselves in L0 (and then continue L2). Only call this
5855 * when in is_guest_mode (L2).
5856 */
5857static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5858{
5859 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5860 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5861 struct vcpu_vmx *vmx = to_vmx(vcpu);
5862 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5863
5864 if (vmx->nested.nested_run_pending)
5865 return 0;
5866
5867 if (unlikely(vmx->fail)) {
bd80158a
JK		 5868 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5869 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5870 return 1;
5871 }
5872
5873 switch (exit_reason) {
5874 case EXIT_REASON_EXCEPTION_NMI:
5875 if (!is_exception(intr_info))
5876 return 0;
5877 else if (is_page_fault(intr_info))
5878 return enable_ept;
5879 return vmcs12->exception_bitmap &
5880 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5881 case EXIT_REASON_EXTERNAL_INTERRUPT:
5882 return 0;
5883 case EXIT_REASON_TRIPLE_FAULT:
5884 return 1;
5885 case EXIT_REASON_PENDING_INTERRUPT:
5886 case EXIT_REASON_NMI_WINDOW:
5887 /*
5888 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5889 * (aka Interrupt Window Exiting) only when L1 turned it on,
5890 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5891 * Same for NMI Window Exiting.
5892 */
5893 return 1;
5894 case EXIT_REASON_TASK_SWITCH:
5895 return 1;
5896 case EXIT_REASON_CPUID:
5897 return 1;
5898 case EXIT_REASON_HLT:
5899 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5900 case EXIT_REASON_INVD:
5901 return 1;
5902 case EXIT_REASON_INVLPG:
5903 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5904 case EXIT_REASON_RDPMC:
5905 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5906 case EXIT_REASON_RDTSC:
5907 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5908 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5909 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5910 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5911 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5912 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5913 /*
5914 * VMX instructions trap unconditionally. This allows L1 to
5915 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5916 */
5917 return 1;
5918 case EXIT_REASON_CR_ACCESS:
5919 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5920 case EXIT_REASON_DR_ACCESS:
5921 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5922 case EXIT_REASON_IO_INSTRUCTION:
5923 /* TODO: support IO bitmaps */
5924 return 1;
5925 case EXIT_REASON_MSR_READ:
5926 case EXIT_REASON_MSR_WRITE:
5927 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5928 case EXIT_REASON_INVALID_STATE:
5929 return 1;
5930 case EXIT_REASON_MWAIT_INSTRUCTION:
5931 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5932 case EXIT_REASON_MONITOR_INSTRUCTION:
5933 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5934 case EXIT_REASON_PAUSE_INSTRUCTION:
5935 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5936 nested_cpu_has2(vmcs12,
5937 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5938 case EXIT_REASON_MCE_DURING_VMENTRY:
5939 return 0;
5940 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5941 return 1;
5942 case EXIT_REASON_APIC_ACCESS:
5943 return nested_cpu_has2(vmcs12,
5944 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5945 case EXIT_REASON_EPT_VIOLATION:
5946 case EXIT_REASON_EPT_MISCONFIG:
5947 return 0;
5948 case EXIT_REASON_WBINVD:
5949 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5950 case EXIT_REASON_XSETBV:
5951 return 1;
5952 default:
5953 return 1;
5954 }
5955}
5956
586f9607
AK		 5957static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5958{
5959 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5960 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5961}
5962
6aa8b732
AK		 5963/*
5964 * The guest has exited. See if we can fix it or if we need userspace
5965 * assistance.
5966 */
851ba692 5967static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5968{
29bd8a78 5969 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5970 u32 exit_reason = vmx->exit_reason;
1155f76a 5971 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5972
80ced186
MG		 5973 /* If guest state is invalid, start emulating */
5974 if (vmx->emulation_required && emulate_invalid_guest_state)
5975 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5976
b6f1250e
NHE		 5977 /*
5978 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5979 * we did not inject a still-pending event to L1 now because of
5980 * nested_run_pending, we need to re-enable this bit.
5981 */
5982 if (vmx->nested.nested_run_pending)
5983 kvm_make_request(KVM_REQ_EVENT, vcpu);
5984
509c75ea
NHE		 5985 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5986 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5987 vmx->nested.nested_run_pending = 1;
5988 else
5989 vmx->nested.nested_run_pending = 0;
5990
5991 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5992 nested_vmx_vmexit(vcpu);
5993 return 1;
5994 }
5995
5120702e
MG		 5996 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5997 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5998 vcpu->run->fail_entry.hardware_entry_failure_reason
5999 = exit_reason;
6000 return 0;
6001 }
6002
29bd8a78 6003 if (unlikely(vmx->fail)) {
851ba692
AK		 6004 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6005 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6006 = vmcs_read32(VM_INSTRUCTION_ERROR);
6007 return 0;
6008 }
6aa8b732 6009
b9bf6882
XG		 6010 /*
6011 * Note:
6012 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6013 * delivery event since it indicates guest is accessing MMIO.
6014 * The vm-exit can be triggered again after return to guest that
6015 * will cause infinite loop.
6016 */
d77c26fc 6017 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6018 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6019 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6020 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6021 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6022 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6023 vcpu->run->internal.ndata = 2;
6024 vcpu->run->internal.data[0] = vectoring_info;
6025 vcpu->run->internal.data[1] = exit_reason;
6026 return 0;
6027 }
3b86cd99 6028
644d711a
NHE		 6029 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6030 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6031 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6032 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6033 vmx->soft_vnmi_blocked = 0;
3b86cd99 6034 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6035 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6036 /*
6037 * This CPU don't support us in finding the end of an
6038 * NMI-blocked window if the guest runs with IRQs
6039 * disabled. So we pull the trigger after 1 s of
6040 * futile waiting, but inform the user about this.
6041 */
6042 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6043 "state on VCPU %d after 1 s timeout\n",
6044 __func__, vcpu->vcpu_id);
6045 vmx->soft_vnmi_blocked = 0;
3b86cd99 6046 }
3b86cd99
JK		 6047 }
6048
6aa8b732
AK		 6049 if (exit_reason < kvm_vmx_max_exit_handlers
6050 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6051 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6052 else {
851ba692
AK		 6053 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6054 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6055 }
6056 return 0;
6057}
6058
95ba8273 6059static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6060{
95ba8273 6061 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6062 vmcs_write32(TPR_THRESHOLD, 0);
6063 return;
6064 }
6065
95ba8273 6066 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6067}
6068
51aa01d1 6069static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6070{
00eba012
AK		 6071 u32 exit_intr_info;
6072
6073 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6074 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6075 return;
6076
c5ca8e57 6077 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6078 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6079
6080 /* Handle machine checks before interrupts are enabled */
00eba012 6081 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6082 kvm_machine_check();
6083
20f65983 6084 /* We need to handle NMIs before interrupts are enabled */
00eba012 6085 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6086 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6087 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6088 asm("int $2");
ff9d07a0
ZY		 6089 kvm_after_handle_nmi(&vmx->vcpu);
6090 }
51aa01d1 6091}
20f65983 6092
51aa01d1
AK		 6093static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6094{
c5ca8e57 6095 u32 exit_intr_info;
51aa01d1
AK		 6096 bool unblock_nmi;
6097 u8 vector;
6098 bool idtv_info_valid;
6099
6100 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6101
cf393f75 6102 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6103 if (vmx->nmi_known_unmasked)
6104 return;
c5ca8e57
AK		 6105 /*
6106 * Can't use vmx->exit_intr_info since we're not sure what
6107 * the exit reason is.
6108 */
6109 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6110 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6111 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6112 /*
7b4a25cb 6113 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6114 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6115 * a guest IRET fault.
7b4a25cb
GN		 6116 * SDM 3: 23.2.2 (September 2008)
6117 * Bit 12 is undefined in any of the following cases:
6118 * If the VM exit sets the valid bit in the IDT-vectoring
6119 * information field.
6120 * If the VM exit is due to a double fault.
cf393f75 6121 */
7b4a25cb
GN		 6122 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6123 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6124 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6125 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6126 else
6127 vmx->nmi_known_unmasked =
6128 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6129 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6130 } else if (unlikely(vmx->soft_vnmi_blocked))
6131 vmx->vnmi_blocked_time +=
6132 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6133}
6134
83422e17
AK		 6135static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6136 u32 idt_vectoring_info,
6137 int instr_len_field,
6138 int error_code_field)
51aa01d1 6139{
51aa01d1
AK		 6140 u8 vector;
6141 int type;
6142 bool idtv_info_valid;
6143
6144 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6145
37b96e98
GN		 6146 vmx->vcpu.arch.nmi_injected = false;
6147 kvm_clear_exception_queue(&vmx->vcpu);
6148 kvm_clear_interrupt_queue(&vmx->vcpu);
6149
6150 if (!idtv_info_valid)
6151 return;
6152
3842d135
AK		 6153 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6154
668f612f
AK		 6155 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6156 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6157
64a7ec06 6158 switch (type) {
37b96e98
GN		 6159 case INTR_TYPE_NMI_INTR:
6160 vmx->vcpu.arch.nmi_injected = true;
668f612f 6161 /*
7b4a25cb 6162 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6163 * Clear bit "block by NMI" before VM entry if a NMI
6164 * delivery faulted.
668f612f 6165 */
654f06fc 6166 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6167 break;
37b96e98 6168 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6169 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6170 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6171 /* fall through */
6172 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6173 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6174 u32 err = vmcs_read32(error_code_field);
37b96e98 6175 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6176 } else
6177 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6178 break;
66fd3f7f
GN		 6179 case INTR_TYPE_SOFT_INTR:
6180 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6181 vmcs_read32(instr_len_field);
66fd3f7f 6182 /* fall through */
37b96e98 6183 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6184 kvm_queue_interrupt(&vmx->vcpu, vector,
6185 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6186 break;
6187 default:
6188 break;
f7d9238f 6189 }
cf393f75
AK		 6190}
6191
83422e17
AK		 6192static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6193{
66c78ae4
NHE		 6194 if (is_guest_mode(&vmx->vcpu))
6195 return;
83422e17
AK		 6196 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6197 VM_EXIT_INSTRUCTION_LEN,
6198 IDT_VECTORING_ERROR_CODE);
6199}
6200
b463a6f7
AK		 6201static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6202{
66c78ae4
NHE		 6203 if (is_guest_mode(vcpu))
6204 return;
b463a6f7
AK		 6205 __vmx_complete_interrupts(to_vmx(vcpu),
6206 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6207 VM_ENTRY_INSTRUCTION_LEN,
6208 VM_ENTRY_EXCEPTION_ERROR_CODE);
6209
6210 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6211}
6212
d7cd9796
GN		 6213static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6214{
6215 int i, nr_msrs;
6216 struct perf_guest_switch_msr *msrs;
6217
6218 msrs = perf_guest_get_msrs(&nr_msrs);
6219
6220 if (!msrs)
6221 return;
6222
6223 for (i = 0; i < nr_msrs; i++)
6224 if (msrs[i].host == msrs[i].guest)
6225 clear_atomic_switch_msr(vmx, msrs[i].msr);
6226 else
6227 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6228 msrs[i].host);
6229}
6230
a3b5ba49 6231static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6232{
a2fa3e9f 6233 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6234 unsigned long debugctlmsr;
104f226b 6235
66c78ae4
NHE		 6236 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6237 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6238 if (vmcs12->idt_vectoring_info_field &
6239 VECTORING_INFO_VALID_MASK) {
6240 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6241 vmcs12->idt_vectoring_info_field);
6242 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6243 vmcs12->vm_exit_instruction_len);
6244 if (vmcs12->idt_vectoring_info_field &
6245 VECTORING_INFO_DELIVER_CODE_MASK)
6246 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6247 vmcs12->idt_vectoring_error_code);
6248 }
6249 }
6250
104f226b
AK		 6251 /* Record the guest's net vcpu time for enforced NMI injections. */
6252 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6253 vmx->entry_time = ktime_get();
6254
6255 /* Don't enter VMX if guest state is invalid, let the exit handler
6256 start emulation until we arrive back to a valid state */
6257 if (vmx->emulation_required && emulate_invalid_guest_state)
6258 return;
6259
6260 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6261 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6262 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6263 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6264
6265 /* When single-stepping over STI and MOV SS, we must clear the
6266 * corresponding interruptibility bits in the guest state. Otherwise
6267 * vmentry fails as it then expects bit 14 (BS) in pending debug
6268 * exceptions being set, but that's not correct for the guest debugging
6269 * case. */
6270 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6271 vmx_set_interrupt_shadow(vcpu, 0);
6272
d7cd9796 6273 atomic_switch_perf_msrs(vmx);
2a7921b7 6274 debugctlmsr = get_debugctlmsr();
d7cd9796 6275
d462b819 6276 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6277 asm(
6aa8b732 6278 /* Store host registers */
b188c81f
AK		 6279 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6280 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6281 "push %%" _ASM_CX " \n\t"
6282 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6283 "je 1f \n\t"
b188c81f 6284 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6285 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6286 "1: \n\t"
d3edefc0 6287 /* Reload cr2 if changed */
b188c81f
AK		 6288 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6289 "mov %%cr2, %%" _ASM_DX " \n\t"
6290 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6291 "je 2f \n\t"
b188c81f 6292 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6293 "2: \n\t"
6aa8b732 6294 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6295 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6296 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6297 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6298 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6299 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6300 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6301 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6302 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6303#ifdef CONFIG_X86_64
e08aa78a
AK		 6304 "mov %c[r8](%0), %%r8 \n\t"
6305 "mov %c[r9](%0), %%r9 \n\t"
6306 "mov %c[r10](%0), %%r10 \n\t"
6307 "mov %c[r11](%0), %%r11 \n\t"
6308 "mov %c[r12](%0), %%r12 \n\t"
6309 "mov %c[r13](%0), %%r13 \n\t"
6310 "mov %c[r14](%0), %%r14 \n\t"
6311 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6312#endif
b188c81f 6313 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6314
6aa8b732 6315 /* Enter guest mode */
83287ea4 6316 "jne 1f \n\t"
4ecac3fd 6317 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6318 "jmp 2f \n\t"
6319 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6320 "2: "
6aa8b732 6321 /* Save guest registers, load host registers, keep flags */
b188c81f 6322 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6323 "pop %0 \n\t"
b188c81f
AK		 6324 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6325 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6326 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6327 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6328 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6329 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6330 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6331#ifdef CONFIG_X86_64
e08aa78a
AK		 6332 "mov %%r8, %c[r8](%0) \n\t"
6333 "mov %%r9, %c[r9](%0) \n\t"
6334 "mov %%r10, %c[r10](%0) \n\t"
6335 "mov %%r11, %c[r11](%0) \n\t"
6336 "mov %%r12, %c[r12](%0) \n\t"
6337 "mov %%r13, %c[r13](%0) \n\t"
6338 "mov %%r14, %c[r14](%0) \n\t"
6339 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6340#endif
b188c81f
AK		 6341 "mov %%cr2, %%" _ASM_AX " \n\t"
6342 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6343
b188c81f 6344 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6345 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6346 ".pushsection .rodata \n\t"
6347 ".global vmx_return \n\t"
6348 "vmx_return: " _ASM_PTR " 2b \n\t"
6349 ".popsection"
e08aa78a 6350 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6351 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6352 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6353 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6354 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6355 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6356 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6357 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6358 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6359 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6360 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6361#ifdef CONFIG_X86_64
ad312c7c
ZX		 6362 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6363 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6364 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6365 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6366 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6367 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6368 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6369 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6370#endif
40712fae
AK		 6371 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6372 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6373 : "cc", "memory"
6374#ifdef CONFIG_X86_64
b188c81f 6375 , "rax", "rbx", "rdi", "rsi"
c2036300 6376 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6377#else
6378 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6379#endif
6380 );
6aa8b732 6381
2a7921b7
GN		 6382 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6383 if (debugctlmsr)
6384 update_debugctlmsr(debugctlmsr);
6385
aa67f609
AK		 6386#ifndef CONFIG_X86_64
6387 /*
6388 * The sysexit path does not restore ds/es, so we must set them to
6389 * a reasonable value ourselves.
6390 *
6391 * We can't defer this to vmx_load_host_state() since that function
6392 * may be executed in interrupt context, which saves and restore segments
6393 * around it, nullifying its effect.
6394 */
6395 loadsegment(ds, __USER_DS);
6396 loadsegment(es, __USER_DS);
6397#endif
6398
6de4f3ad 6399 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6400 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6401 | (1 << VCPU_EXREG_CPL)
aff48baa 6402 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6403 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6404 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6405 vcpu->arch.regs_dirty = 0;
6406
1155f76a
AK		 6407 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6408
66c78ae4
NHE		 6409 if (is_guest_mode(vcpu)) {
6410 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6411 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6412 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6413 vmcs12->idt_vectoring_error_code =
6414 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6415 vmcs12->vm_exit_instruction_len =
6416 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6417 }
6418 }
6419
d462b819 6420 vmx->loaded_vmcs->launched = 1;
1b6269db 6421
51aa01d1 6422 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6423 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6424
6425 vmx_complete_atomic_exit(vmx);
6426 vmx_recover_nmi_blocking(vmx);
cf393f75 6427 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6428}
6429
6aa8b732
AK		 6430static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6431{
fb3f0f51
RR		 6432 struct vcpu_vmx *vmx = to_vmx(vcpu);
6433
cdbecfc3 6434 free_vpid(vmx);
ec378aee 6435 free_nested(vmx);
d462b819 6436 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6437 kfree(vmx->guest_msrs);
6438 kvm_vcpu_uninit(vcpu);
a4770347 6439 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6440}
6441
fb3f0f51 6442static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6443{
fb3f0f51 6444 int err;
c16f862d 6445 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6446 int cpu;
6aa8b732 6447
a2fa3e9f 6448 if (!vmx)
fb3f0f51
RR		 6449 return ERR_PTR(-ENOMEM);
6450
2384d2b3
SY		 6451 allocate_vpid(vmx);
6452
fb3f0f51
RR		 6453 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6454 if (err)
6455 goto free_vcpu;
965b58a5 6456
a2fa3e9f 6457 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6458 err = -ENOMEM;
fb3f0f51 6459 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6460 goto uninit_vcpu;
6461 }
965b58a5 6462
d462b819
NHE		 6463 vmx->loaded_vmcs = &vmx->vmcs01;
6464 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6465 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6466 goto free_msrs;
d462b819
NHE		 6467 if (!vmm_exclusive)
6468 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6469 loaded_vmcs_init(vmx->loaded_vmcs);
6470 if (!vmm_exclusive)
6471 kvm_cpu_vmxoff();
a2fa3e9f 6472
15ad7146
AK		 6473 cpu = get_cpu();
6474 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6475 vmx->vcpu.cpu = cpu;
8b9cf98c 6476 err = vmx_vcpu_setup(vmx);
fb3f0f51 6477 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6478 put_cpu();
fb3f0f51
RR		 6479 if (err)
6480 goto free_vmcs;
5e4a0b3c 6481 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6482 err = alloc_apic_access_page(kvm);
6483 if (err)
5e4a0b3c 6484 goto free_vmcs;
fb3f0f51 6485
b927a3ce
SY		 6486 if (enable_ept) {
6487 if (!kvm->arch.ept_identity_map_addr)
6488 kvm->arch.ept_identity_map_addr =
6489 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6490 err = -ENOMEM;
b7ebfb05
SY		 6491 if (alloc_identity_pagetable(kvm) != 0)
6492 goto free_vmcs;
93ea5388
GN		 6493 if (!init_rmode_identity_map(kvm))
6494 goto free_vmcs;
b927a3ce 6495 }
b7ebfb05 6496
a9d30f33
NHE		 6497 vmx->nested.current_vmptr = -1ull;
6498 vmx->nested.current_vmcs12 = NULL;
6499
fb3f0f51
RR		 6500 return &vmx->vcpu;
6501
6502free_vmcs:
5f3fbc34 6503 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6504free_msrs:
fb3f0f51
RR		 6505 kfree(vmx->guest_msrs);
6506uninit_vcpu:
6507 kvm_vcpu_uninit(&vmx->vcpu);
6508free_vcpu:
cdbecfc3 6509 free_vpid(vmx);
a4770347 6510 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6511 return ERR_PTR(err);
6aa8b732
AK		 6512}
6513
002c7f7c
YS		 6514static void __init vmx_check_processor_compat(void *rtn)
6515{
6516 struct vmcs_config vmcs_conf;
6517
6518 *(int *)rtn = 0;
6519 if (setup_vmcs_config(&vmcs_conf) < 0)
6520 *(int *)rtn = -EIO;
6521 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6522 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6523 smp_processor_id());
6524 *(int *)rtn = -EIO;
6525 }
6526}
6527
67253af5
SY		 6528static int get_ept_level(void)
6529{
6530 return VMX_EPT_DEFAULT_GAW + 1;
6531}
6532
4b12f0de 6533static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6534{
4b12f0de
SY		 6535 u64 ret;
6536
522c68c4
SY		 6537 /* For VT-d and EPT combination
6538 * 1. MMIO: always map as UC
6539 * 2. EPT with VT-d:
6540 * a. VT-d without snooping control feature: can't guarantee the
6541 * result, try to trust guest.
6542 * b. VT-d with snooping control feature: snooping control feature of
6543 * VT-d engine can guarantee the cache correctness. Just set it
6544 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6545 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6546 * consistent with host MTRR
6547 */
4b12f0de
SY		 6548 if (is_mmio)
6549 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6550 else if (vcpu->kvm->arch.iommu_domain &&
6551 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6552 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6553 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6554 else
522c68c4 6555 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6556 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6557
6558 return ret;
64d4d521
SY		 6559}
6560
17cc3935 6561static int vmx_get_lpage_level(void)
344f414f 6562{
878403b7
SY		 6563 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6564 return PT_DIRECTORY_LEVEL;
6565 else
6566 /* For shadow and EPT supported 1GB page */
6567 return PT_PDPE_LEVEL;
344f414f
JR		 6568}
6569
0e851880
SY		 6570static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6571{
4e47c7a6
SY		 6572 struct kvm_cpuid_entry2 *best;
6573 struct vcpu_vmx *vmx = to_vmx(vcpu);
6574 u32 exec_control;
6575
6576 vmx->rdtscp_enabled = false;
6577 if (vmx_rdtscp_supported()) {
6578 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6579 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6580 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6581 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6582 vmx->rdtscp_enabled = true;
6583 else {
6584 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6585 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6586 exec_control);
6587 }
6588 }
6589 }
ad756a16
MJ		 6590
6591 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6592 /* Exposing INVPCID only when PCID is exposed */
6593 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6594 if (vmx_invpcid_supported() &&
4f977045 6595 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16
MJ		 6596 guest_cpuid_has_pcid(vcpu)) {
6597 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6598 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6599 exec_control);
6600 } else {
6601 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6602 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6603 exec_control);
6604 if (best)
4f977045 6605 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6606 }
0e851880
SY		 6607}
6608
d4330ef2
JR		 6609static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6610{
7b8050f5
NHE		 6611 if (func == 1 && nested)
6612 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6613}
6614
fe3ef05c
NHE		 6615/*
6616 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6617 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6618 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6619 * guest in a way that will both be appropriate to L1's requests, and our
6620 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6621 * function also has additional necessary side-effects, like setting various
6622 * vcpu->arch fields.
6623 */
6624static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6625{
6626 struct vcpu_vmx *vmx = to_vmx(vcpu);
6627 u32 exec_control;
6628
6629 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6630 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6631 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6632 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6633 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6634 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6635 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6636 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6637 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6638 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6639 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6640 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6641 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6642 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6643 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6644 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6645 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6646 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6647 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6648 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6649 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6650 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6651 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6652 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6653 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6654 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6655 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6656 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6657 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6658 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6659 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6660 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6661 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6662 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6663 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6664 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6665
6666 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6667 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6668 vmcs12->vm_entry_intr_info_field);
6669 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6670 vmcs12->vm_entry_exception_error_code);
6671 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6672 vmcs12->vm_entry_instruction_len);
6673 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6674 vmcs12->guest_interruptibility_info);
6675 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6676 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6677 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6678 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6679 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6680 vmcs12->guest_pending_dbg_exceptions);
6681 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6682 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6683
6684 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6685
6686 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6687 (vmcs_config.pin_based_exec_ctrl |
6688 vmcs12->pin_based_vm_exec_control));
6689
6690 /*
6691 * Whether page-faults are trapped is determined by a combination of
6692 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6693 * If enable_ept, L0 doesn't care about page faults and we should
6694 * set all of these to L1's desires. However, if !enable_ept, L0 does
6695 * care about (at least some) page faults, and because it is not easy
6696 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6697 * to exit on each and every L2 page fault. This is done by setting
6698 * MASK=MATCH=0 and (see below) EB.PF=1.
6699 * Note that below we don't need special code to set EB.PF beyond the
6700 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6701 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6702 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6703 *
6704 * A problem with this approach (when !enable_ept) is that L1 may be
6705 * injected with more page faults than it asked for. This could have
6706 * caused problems, but in practice existing hypervisors don't care.
6707 * To fix this, we will need to emulate the PFEC checking (on the L1
6708 * page tables), using walk_addr(), when injecting PFs to L1.
6709 */
6710 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6711 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6712 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6713 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6714
6715 if (cpu_has_secondary_exec_ctrls()) {
6716 u32 exec_control = vmx_secondary_exec_control(vmx);
6717 if (!vmx->rdtscp_enabled)
6718 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6719 /* Take the following fields only from vmcs12 */
6720 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6721 if (nested_cpu_has(vmcs12,
6722 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6723 exec_control |= vmcs12->secondary_vm_exec_control;
6724
6725 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6726 /*
6727 * Translate L1 physical address to host physical
6728 * address for vmcs02. Keep the page pinned, so this
6729 * physical address remains valid. We keep a reference
6730 * to it so we can release it later.
6731 */
6732 if (vmx->nested.apic_access_page) /* shouldn't happen */
6733 nested_release_page(vmx->nested.apic_access_page);
6734 vmx->nested.apic_access_page =
6735 nested_get_page(vcpu, vmcs12->apic_access_addr);
6736 /*
6737 * If translation failed, no matter: This feature asks
6738 * to exit when accessing the given address, and if it
6739 * can never be accessed, this feature won't do
6740 * anything anyway.
6741 */
6742 if (!vmx->nested.apic_access_page)
6743 exec_control &=
6744 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6745 else
6746 vmcs_write64(APIC_ACCESS_ADDR,
6747 page_to_phys(vmx->nested.apic_access_page));
6748 }
6749
6750 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6751 }
6752
6753
6754 /*
6755 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6756 * Some constant fields are set here by vmx_set_constant_host_state().
6757 * Other fields are different per CPU, and will be set later when
6758 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6759 */
6760 vmx_set_constant_host_state();
6761
6762 /*
6763 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6764 * entry, but only if the current (host) sp changed from the value
6765 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6766 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6767 * here we just force the write to happen on entry.
6768 */
6769 vmx->host_rsp = 0;
6770
6771 exec_control = vmx_exec_control(vmx); /* L0's desires */
6772 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6773 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6774 exec_control &= ~CPU_BASED_TPR_SHADOW;
6775 exec_control |= vmcs12->cpu_based_vm_exec_control;
6776 /*
6777 * Merging of IO and MSR bitmaps not currently supported.
6778 * Rather, exit every time.
6779 */
6780 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6781 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6782 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6783
6784 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6785
6786 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6787 * bitwise-or of what L1 wants to trap for L2, and what we want to
6788 * trap. Note that CR0.TS also needs updating - we do this later.
6789 */
6790 update_exception_bitmap(vcpu);
6791 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6792 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6793
6794 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6795 vmcs_write32(VM_EXIT_CONTROLS,
6796 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6797 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6798 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6799
6800 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6801 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6802 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6803 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6804
6805
6806 set_cr4_guest_host_mask(vmx);
6807
27fc51b2
NHE		 6808 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6809 vmcs_write64(TSC_OFFSET,
6810 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6811 else
6812 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6813
6814 if (enable_vpid) {
6815 /*
6816 * Trivially support vpid by letting L2s share their parent
6817 * L1's vpid. TODO: move to a more elaborate solution, giving
6818 * each L2 its own vpid and exposing the vpid feature to L1.
6819 */
6820 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6821 vmx_flush_tlb(vcpu);
6822 }
6823
6824 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6825 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6826 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6827 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6828 else
6829 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6830 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6831 vmx_set_efer(vcpu, vcpu->arch.efer);
6832
6833 /*
6834 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6835 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6836 * The CR0_READ_SHADOW is what L2 should have expected to read given
6837 * the specifications by L1; It's not enough to take
6838 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6839 * have more bits than L1 expected.
6840 */
6841 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6842 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6843
6844 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6845 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6846
6847 /* shadow page tables on either EPT or shadow page tables */
6848 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6849 kvm_mmu_reset_context(vcpu);
6850
6851 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6852 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6853}
6854
cd232ad0
NHE		 6855/*
6856 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6857 * for running an L2 nested guest.
6858 */
6859static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6860{
6861 struct vmcs12 *vmcs12;
6862 struct vcpu_vmx *vmx = to_vmx(vcpu);
6863 int cpu;
6864 struct loaded_vmcs *vmcs02;
6865
6866 if (!nested_vmx_check_permission(vcpu) ||
6867 !nested_vmx_check_vmcs12(vcpu))
6868 return 1;
6869
6870 skip_emulated_instruction(vcpu);
6871 vmcs12 = get_vmcs12(vcpu);
6872
7c177938
NHE		 6873 /*
6874 * The nested entry process starts with enforcing various prerequisites
6875 * on vmcs12 as required by the Intel SDM, and act appropriately when
6876 * they fail: As the SDM explains, some conditions should cause the
6877 * instruction to fail, while others will cause the instruction to seem
6878 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6879 * To speed up the normal (success) code path, we should avoid checking
6880 * for misconfigurations which will anyway be caught by the processor
6881 * when using the merged vmcs02.
6882 */
6883 if (vmcs12->launch_state == launch) {
6884 nested_vmx_failValid(vcpu,
6885 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6886 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6887 return 1;
6888 }
6889
6890 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6891 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6892 /*TODO: Also verify bits beyond physical address width are 0*/
6893 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6894 return 1;
6895 }
6896
6897 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6898 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6899 /*TODO: Also verify bits beyond physical address width are 0*/
6900 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6901 return 1;
6902 }
6903
6904 if (vmcs12->vm_entry_msr_load_count > 0 ||
6905 vmcs12->vm_exit_msr_load_count > 0 ||
6906 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6907 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6908 __func__);
7c177938
NHE		 6909 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6910 return 1;
6911 }
6912
6913 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6914 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6915 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6916 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6917 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6918 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6919 !vmx_control_verify(vmcs12->vm_exit_controls,
6920 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6921 !vmx_control_verify(vmcs12->vm_entry_controls,
6922 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6923 {
6924 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6925 return 1;
6926 }
6927
6928 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6929 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6930 nested_vmx_failValid(vcpu,
6931 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6932 return 1;
6933 }
6934
6935 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6936 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6937 nested_vmx_entry_failure(vcpu, vmcs12,
6938 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6939 return 1;
6940 }
6941 if (vmcs12->vmcs_link_pointer != -1ull) {
6942 nested_vmx_entry_failure(vcpu, vmcs12,
6943 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6944 return 1;
6945 }
6946
6947 /*
6948 * We're finally done with prerequisite checking, and can start with
6949 * the nested entry.
6950 */
6951
cd232ad0
NHE		 6952 vmcs02 = nested_get_current_vmcs02(vmx);
6953 if (!vmcs02)
6954 return -ENOMEM;
6955
6956 enter_guest_mode(vcpu);
6957
6958 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6959
6960 cpu = get_cpu();
6961 vmx->loaded_vmcs = vmcs02;
6962 vmx_vcpu_put(vcpu);
6963 vmx_vcpu_load(vcpu, cpu);
6964 vcpu->cpu = cpu;
6965 put_cpu();
6966
6967 vmcs12->launch_state = 1;
6968
6969 prepare_vmcs02(vcpu, vmcs12);
6970
6971 /*
6972 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6973 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6974 * returned as far as L1 is concerned. It will only return (and set
6975 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6976 */
6977 return 1;
6978}
6979
4704d0be
NHE		 6980/*
6981 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6982 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6983 * This function returns the new value we should put in vmcs12.guest_cr0.
6984 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6985 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6986 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6987 * didn't trap the bit, because if L1 did, so would L0).
6988 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6989 * been modified by L2, and L1 knows it. So just leave the old value of
6990 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6991 * isn't relevant, because if L0 traps this bit it can set it to anything.
6992 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6993 * changed these bits, and therefore they need to be updated, but L0
6994 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6995 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6996 */
6997static inline unsigned long
6998vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6999{
7000 return
7001 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7002 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7003 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7004 vcpu->arch.cr0_guest_owned_bits));
7005}
7006
7007static inline unsigned long
7008vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7009{
7010 return
7011 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7012 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7013 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7014 vcpu->arch.cr4_guest_owned_bits));
7015}
7016
7017/*
7018 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7019 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7020 * and this function updates it to reflect the changes to the guest state while
7021 * L2 was running (and perhaps made some exits which were handled directly by L0
7022 * without going back to L1), and to reflect the exit reason.
7023 * Note that we do not have to copy here all VMCS fields, just those that
7024 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7025 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7026 * which already writes to vmcs12 directly.
7027 */
7028void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7029{
7030 /* update guest state fields: */
7031 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7032 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7033
7034 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7035 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7036 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7037 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7038
7039 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7040 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7041 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7042 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7043 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7044 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7045 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7046 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7047 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7048 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7049 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7050 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7051 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7052 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7053 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7054 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7055 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7056 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7057 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7058 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7059 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7060 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7061 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7062 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7063 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7064 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7065 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7066 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7067 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7068 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7069 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7070 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7071 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7072 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7073 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7074 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7075
7076 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7077 vmcs12->guest_interruptibility_info =
7078 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7079 vmcs12->guest_pending_dbg_exceptions =
7080 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7081
7082 /* TODO: These cannot have changed unless we have MSR bitmaps and
7083 * the relevant bit asks not to trap the change */
7084 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7085 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7086 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7087 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7088 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7089 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7090
7091 /* update exit information fields: */
7092
7093 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7094 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7095
7096 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7097 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7098 vmcs12->idt_vectoring_info_field =
7099 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7100 vmcs12->idt_vectoring_error_code =
7101 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7102 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7103 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7104
7105 /* clear vm-entry fields which are to be cleared on exit */
7106 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7107 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7108}
7109
7110/*
7111 * A part of what we need to when the nested L2 guest exits and we want to
7112 * run its L1 parent, is to reset L1's guest state to the host state specified
7113 * in vmcs12.
7114 * This function is to be called not only on normal nested exit, but also on
7115 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7116 * Failures During or After Loading Guest State").
7117 * This function should be called when the active VMCS is L1's (vmcs01).
7118 */
7119void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7120{
7121 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7122 vcpu->arch.efer = vmcs12->host_ia32_efer;
7123 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7124 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7125 else
7126 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7127 vmx_set_efer(vcpu, vcpu->arch.efer);
7128
7129 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7130 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7131 /*
7132 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7133 * actually changed, because it depends on the current state of
7134 * fpu_active (which may have changed).
7135 * Note that vmx_set_cr0 refers to efer set above.
7136 */
7137 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7138 /*
7139 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7140 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7141 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7142 */
7143 update_exception_bitmap(vcpu);
7144 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7145 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7146
7147 /*
7148 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7149 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7150 */
7151 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7152 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7153
7154 /* shadow page tables on either EPT or shadow page tables */
7155 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7156 kvm_mmu_reset_context(vcpu);
7157
7158 if (enable_vpid) {
7159 /*
7160 * Trivially support vpid by letting L2s share their parent
7161 * L1's vpid. TODO: move to a more elaborate solution, giving
7162 * each L2 its own vpid and exposing the vpid feature to L1.
7163 */
7164 vmx_flush_tlb(vcpu);
7165 }
7166
7167
7168 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7169 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7170 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7171 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7172 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7173 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7174 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7175 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7176 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7177 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7178 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7179 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7180 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7181 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7182 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7183
7184 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7185 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7186 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7187 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7188 vmcs12->host_ia32_perf_global_ctrl);
7189}
7190
7191/*
7192 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7193 * and modify vmcs12 to make it see what it would expect to see there if
7194 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7195 */
7196static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7197{
7198 struct vcpu_vmx *vmx = to_vmx(vcpu);
7199 int cpu;
7200 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7201
7202 leave_guest_mode(vcpu);
7203 prepare_vmcs12(vcpu, vmcs12);
7204
7205 cpu = get_cpu();
7206 vmx->loaded_vmcs = &vmx->vmcs01;
7207 vmx_vcpu_put(vcpu);
7208 vmx_vcpu_load(vcpu, cpu);
7209 vcpu->cpu = cpu;
7210 put_cpu();
7211
7212 /* if no vmcs02 cache requested, remove the one we used */
7213 if (VMCS02_POOL_SIZE == 0)
7214 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7215
7216 load_vmcs12_host_state(vcpu, vmcs12);
7217
27fc51b2 7218 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7219 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7220
7221 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7222 vmx->host_rsp = 0;
7223
7224 /* Unpin physical memory we referred to in vmcs02 */
7225 if (vmx->nested.apic_access_page) {
7226 nested_release_page(vmx->nested.apic_access_page);
7227 vmx->nested.apic_access_page = 0;
7228 }
7229
7230 /*
7231 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7232 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7233 * success or failure flag accordingly.
7234 */
7235 if (unlikely(vmx->fail)) {
7236 vmx->fail = 0;
7237 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7238 } else
7239 nested_vmx_succeed(vcpu);
7240}
7241
7c177938
NHE		 7242/*
7243 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7244 * 23.7 "VM-entry failures during or after loading guest state" (this also
7245 * lists the acceptable exit-reason and exit-qualification parameters).
7246 * It should only be called before L2 actually succeeded to run, and when
7247 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7248 */
7249static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7250 struct vmcs12 *vmcs12,
7251 u32 reason, unsigned long qualification)
7252{
7253 load_vmcs12_host_state(vcpu, vmcs12);
7254 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7255 vmcs12->exit_qualification = qualification;
7256 nested_vmx_succeed(vcpu);
7257}
7258
8a76d7f2
JR		 7259static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7260 struct x86_instruction_info *info,
7261 enum x86_intercept_stage stage)
7262{
7263 return X86EMUL_CONTINUE;
7264}
7265
cbdd1bea 7266static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7267 .cpu_has_kvm_support = cpu_has_kvm_support,
7268 .disabled_by_bios = vmx_disabled_by_bios,
7269 .hardware_setup = hardware_setup,
7270 .hardware_unsetup = hardware_unsetup,
002c7f7c 7271 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7272 .hardware_enable = hardware_enable,
7273 .hardware_disable = hardware_disable,
04547156 7274 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7275
7276 .vcpu_create = vmx_create_vcpu,
7277 .vcpu_free = vmx_free_vcpu,
04d2cc77 7278 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7279
04d2cc77 7280 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7281 .vcpu_load = vmx_vcpu_load,
7282 .vcpu_put = vmx_vcpu_put,
7283
c8639010 7284 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7285 .get_msr = vmx_get_msr,
7286 .set_msr = vmx_set_msr,
7287 .get_segment_base = vmx_get_segment_base,
7288 .get_segment = vmx_get_segment,
7289 .set_segment = vmx_set_segment,
2e4d2653 7290 .get_cpl = vmx_get_cpl,
6aa8b732 7291 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7292 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7293 .decache_cr3 = vmx_decache_cr3,
25c4c276 7294 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7295 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7296 .set_cr3 = vmx_set_cr3,
7297 .set_cr4 = vmx_set_cr4,
6aa8b732 7298 .set_efer = vmx_set_efer,
6aa8b732
AK		 7299 .get_idt = vmx_get_idt,
7300 .set_idt = vmx_set_idt,
7301 .get_gdt = vmx_get_gdt,
7302 .set_gdt = vmx_set_gdt,
020df079 7303 .set_dr7 = vmx_set_dr7,
5fdbf976 7304 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7305 .get_rflags = vmx_get_rflags,
7306 .set_rflags = vmx_set_rflags,
ebcbab4c 7307 .fpu_activate = vmx_fpu_activate,
02daab21 7308 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7309
7310 .tlb_flush = vmx_flush_tlb,
6aa8b732 7311
6aa8b732 7312 .run = vmx_vcpu_run,
6062d012 7313 .handle_exit = vmx_handle_exit,
6aa8b732 7314 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7315 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7316 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7317 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7318 .set_irq = vmx_inject_irq,
95ba8273 7319 .set_nmi = vmx_inject_nmi,
298101da 7320 .queue_exception = vmx_queue_exception,
b463a6f7 7321 .cancel_injection = vmx_cancel_injection,
78646121 7322 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7323 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7324 .get_nmi_mask = vmx_get_nmi_mask,
7325 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7326 .enable_nmi_window = enable_nmi_window,
7327 .enable_irq_window = enable_irq_window,
7328 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7329
cbc94022 7330 .set_tss_addr = vmx_set_tss_addr,
67253af5 7331 .get_tdp_level = get_ept_level,
4b12f0de 7332 .get_mt_mask = vmx_get_mt_mask,
229456fc 7333
586f9607 7334 .get_exit_info = vmx_get_exit_info,
586f9607 7335
17cc3935 7336 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7337
7338 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7339
7340 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7341 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7342
7343 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7344
7345 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7346
4051b188 7347 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7348 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7349 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7350 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7351 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7352
7353 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7354
7355 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7356};
7357
7358static int __init vmx_init(void)
7359{
26bb0981
AK		 7360 int r, i;
7361
7362 rdmsrl_safe(MSR_EFER, &host_efer);
7363
7364 for (i = 0; i < NR_VMX_MSR; ++i)
7365 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7366
3e7c73e9 7367 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7368 if (!vmx_io_bitmap_a)
7369 return -ENOMEM;
7370
2106a548
GC		 7371 r = -ENOMEM;
7372
3e7c73e9 7373 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7374 if (!vmx_io_bitmap_b)
fdef3ad1 7375 goto out;
fdef3ad1 7376
5897297b 7377 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7378 if (!vmx_msr_bitmap_legacy)
25c5f225 7379 goto out1;
2106a548 7380
25c5f225 7381
5897297b 7382 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7383 if (!vmx_msr_bitmap_longmode)
5897297b 7384 goto out2;
2106a548 7385
5897297b 7386
fdef3ad1
HQ		 7387 /*
7388 * Allow direct access to the PC debug port (it is often used for I/O
7389 * delays, but the vmexits simply slow things down).
7390 */
3e7c73e9
AK		 7391 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7392 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7393
3e7c73e9 7394 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7395
5897297b
AK		 7396 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7397 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7398
2384d2b3
SY		 7399 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7400
0ee75bea
AK		 7401 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7402 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7403 if (r)
5897297b 7404 goto out3;
25c5f225 7405
5897297b
AK		 7406 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7407 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7408 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7409 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7410 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7411 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7412
089d034e 7413 if (enable_ept) {
3f6d8c8a
XH		 7414 kvm_mmu_set_mask_ptes(0ull,
7415 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7416 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7417 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7418 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7419 kvm_enable_tdp();
7420 } else
7421 kvm_disable_tdp();
1439442c 7422
fdef3ad1
HQ		 7423 return 0;
7424
5897297b
AK		 7425out3:
7426 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7427out2:
5897297b 7428 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7429out1:
3e7c73e9 7430 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7431out:
3e7c73e9 7432 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7433 return r;
6aa8b732
AK		 7434}
7435
7436static void __exit vmx_exit(void)
7437{
5897297b
AK		 7438 free_page((unsigned long)vmx_msr_bitmap_legacy);
7439 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7440 free_page((unsigned long)vmx_io_bitmap_b);
7441 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7442
cb498ea2 7443 kvm_exit();
6aa8b732
AK		 7444}
7445
7446module_init(vmx_init)
7447module_exit(vmx_exit)
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