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KVM: Add ppc hypercall documentation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
6aa8b732 45
229456fc
MT		 46#include "trace.h"
47
4ecac3fd 48#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 49#define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 51
6aa8b732
AK		 52MODULE_AUTHOR("Qumranet");
53MODULE_LICENSE("GPL");
54
e9bda3b3
JT		 55static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58};
59MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
476bc001 61static bool __read_mostly enable_vpid = 1;
736caefe 62module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 63
476bc001 64static bool __read_mostly flexpriority_enabled = 1;
736caefe 65module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 66
476bc001 67static bool __read_mostly enable_ept = 1;
736caefe 68module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 69
476bc001 70static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 71module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
83c3a331
XH		 74static bool __read_mostly enable_ept_ad_bits = 1;
75module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
a27685c3 77static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 78module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 79
476bc001 80static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 81module_param(vmm_exclusive, bool, S_IRUGO);
82
476bc001 83static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 84module_param(fasteoi, bool, S_IRUGO);
85
801d3424
NHE		 86/*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
476bc001 91static bool __read_mostly nested = 0;
801d3424
NHE		 92module_param(nested, bool, S_IRUGO);
93
cdc0e244
AK		 94#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96#define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 99 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 100#define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 102#define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
cdc0e244
AK		 106#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
78ac8b47
AK		 109#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
4b8d54f9
ZE		 111/*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 115 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
00c25bce 122#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 123#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125module_param(ple_gap, int, S_IRUGO);
126
127static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128module_param(ple_window, int, S_IRUGO);
129
8bf00a52 130#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 131#define VMCS02_POOL_SIZE 1
61d2ef2c 132
a2fa3e9f
GH		 133struct vmcs {
134 u32 revision_id;
135 u32 abort;
136 char data[0];
137};
138
d462b819
NHE		 139/*
140 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
141 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
142 * loaded on this CPU (so we can clear them if the CPU goes down).
143 */
144struct loaded_vmcs {
145 struct vmcs *vmcs;
146 int cpu;
147 int launched;
148 struct list_head loaded_vmcss_on_cpu_link;
149};
150
26bb0981
AK		 151struct shared_msr_entry {
152 unsigned index;
153 u64 data;
d5696725 154 u64 mask;
26bb0981
AK		 155};
156
a9d30f33
NHE		 157/*
158 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
159 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
160 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
161 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
162 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
163 * More than one of these structures may exist, if L1 runs multiple L2 guests.
164 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
165 * underlying hardware which will be used to run L2.
166 * This structure is packed to ensure that its layout is identical across
167 * machines (necessary for live migration).
168 * If there are changes in this struct, VMCS12_REVISION must be changed.
169 */
22bd0358 170typedef u64 natural_width;
a9d30f33
NHE		 171struct __packed vmcs12 {
172 /* According to the Intel spec, a VMCS region must start with the
173 * following two fields. Then follow implementation-specific data.
174 */
175 u32 revision_id;
176 u32 abort;
22bd0358 177
27d6c865
NHE		 178 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
179 u32 padding[7]; /* room for future expansion */
180
22bd0358
NHE		 181 u64 io_bitmap_a;
182 u64 io_bitmap_b;
183 u64 msr_bitmap;
184 u64 vm_exit_msr_store_addr;
185 u64 vm_exit_msr_load_addr;
186 u64 vm_entry_msr_load_addr;
187 u64 tsc_offset;
188 u64 virtual_apic_page_addr;
189 u64 apic_access_addr;
190 u64 ept_pointer;
191 u64 guest_physical_address;
192 u64 vmcs_link_pointer;
193 u64 guest_ia32_debugctl;
194 u64 guest_ia32_pat;
195 u64 guest_ia32_efer;
196 u64 guest_ia32_perf_global_ctrl;
197 u64 guest_pdptr0;
198 u64 guest_pdptr1;
199 u64 guest_pdptr2;
200 u64 guest_pdptr3;
201 u64 host_ia32_pat;
202 u64 host_ia32_efer;
203 u64 host_ia32_perf_global_ctrl;
204 u64 padding64[8]; /* room for future expansion */
205 /*
206 * To allow migration of L1 (complete with its L2 guests) between
207 * machines of different natural widths (32 or 64 bit), we cannot have
208 * unsigned long fields with no explict size. We use u64 (aliased
209 * natural_width) instead. Luckily, x86 is little-endian.
210 */
211 natural_width cr0_guest_host_mask;
212 natural_width cr4_guest_host_mask;
213 natural_width cr0_read_shadow;
214 natural_width cr4_read_shadow;
215 natural_width cr3_target_value0;
216 natural_width cr3_target_value1;
217 natural_width cr3_target_value2;
218 natural_width cr3_target_value3;
219 natural_width exit_qualification;
220 natural_width guest_linear_address;
221 natural_width guest_cr0;
222 natural_width guest_cr3;
223 natural_width guest_cr4;
224 natural_width guest_es_base;
225 natural_width guest_cs_base;
226 natural_width guest_ss_base;
227 natural_width guest_ds_base;
228 natural_width guest_fs_base;
229 natural_width guest_gs_base;
230 natural_width guest_ldtr_base;
231 natural_width guest_tr_base;
232 natural_width guest_gdtr_base;
233 natural_width guest_idtr_base;
234 natural_width guest_dr7;
235 natural_width guest_rsp;
236 natural_width guest_rip;
237 natural_width guest_rflags;
238 natural_width guest_pending_dbg_exceptions;
239 natural_width guest_sysenter_esp;
240 natural_width guest_sysenter_eip;
241 natural_width host_cr0;
242 natural_width host_cr3;
243 natural_width host_cr4;
244 natural_width host_fs_base;
245 natural_width host_gs_base;
246 natural_width host_tr_base;
247 natural_width host_gdtr_base;
248 natural_width host_idtr_base;
249 natural_width host_ia32_sysenter_esp;
250 natural_width host_ia32_sysenter_eip;
251 natural_width host_rsp;
252 natural_width host_rip;
253 natural_width paddingl[8]; /* room for future expansion */
254 u32 pin_based_vm_exec_control;
255 u32 cpu_based_vm_exec_control;
256 u32 exception_bitmap;
257 u32 page_fault_error_code_mask;
258 u32 page_fault_error_code_match;
259 u32 cr3_target_count;
260 u32 vm_exit_controls;
261 u32 vm_exit_msr_store_count;
262 u32 vm_exit_msr_load_count;
263 u32 vm_entry_controls;
264 u32 vm_entry_msr_load_count;
265 u32 vm_entry_intr_info_field;
266 u32 vm_entry_exception_error_code;
267 u32 vm_entry_instruction_len;
268 u32 tpr_threshold;
269 u32 secondary_vm_exec_control;
270 u32 vm_instruction_error;
271 u32 vm_exit_reason;
272 u32 vm_exit_intr_info;
273 u32 vm_exit_intr_error_code;
274 u32 idt_vectoring_info_field;
275 u32 idt_vectoring_error_code;
276 u32 vm_exit_instruction_len;
277 u32 vmx_instruction_info;
278 u32 guest_es_limit;
279 u32 guest_cs_limit;
280 u32 guest_ss_limit;
281 u32 guest_ds_limit;
282 u32 guest_fs_limit;
283 u32 guest_gs_limit;
284 u32 guest_ldtr_limit;
285 u32 guest_tr_limit;
286 u32 guest_gdtr_limit;
287 u32 guest_idtr_limit;
288 u32 guest_es_ar_bytes;
289 u32 guest_cs_ar_bytes;
290 u32 guest_ss_ar_bytes;
291 u32 guest_ds_ar_bytes;
292 u32 guest_fs_ar_bytes;
293 u32 guest_gs_ar_bytes;
294 u32 guest_ldtr_ar_bytes;
295 u32 guest_tr_ar_bytes;
296 u32 guest_interruptibility_info;
297 u32 guest_activity_state;
298 u32 guest_sysenter_cs;
299 u32 host_ia32_sysenter_cs;
300 u32 padding32[8]; /* room for future expansion */
301 u16 virtual_processor_id;
302 u16 guest_es_selector;
303 u16 guest_cs_selector;
304 u16 guest_ss_selector;
305 u16 guest_ds_selector;
306 u16 guest_fs_selector;
307 u16 guest_gs_selector;
308 u16 guest_ldtr_selector;
309 u16 guest_tr_selector;
310 u16 host_es_selector;
311 u16 host_cs_selector;
312 u16 host_ss_selector;
313 u16 host_ds_selector;
314 u16 host_fs_selector;
315 u16 host_gs_selector;
316 u16 host_tr_selector;
a9d30f33
NHE		 317};
318
319/*
320 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
321 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
322 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
323 */
324#define VMCS12_REVISION 0x11e57ed0
325
326/*
327 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
328 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
329 * current implementation, 4K are reserved to avoid future complications.
330 */
331#define VMCS12_SIZE 0x1000
332
ff2f6fe9
NHE		 333/* Used to remember the last vmcs02 used for some recently used vmcs12s */
334struct vmcs02_list {
335 struct list_head list;
336 gpa_t vmptr;
337 struct loaded_vmcs vmcs02;
338};
339
ec378aee
NHE		 340/*
341 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
342 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
343 */
344struct nested_vmx {
345 /* Has the level1 guest done vmxon? */
346 bool vmxon;
a9d30f33
NHE		 347
348 /* The guest-physical address of the current VMCS L1 keeps for L2 */
349 gpa_t current_vmptr;
350 /* The host-usable pointer to the above */
351 struct page *current_vmcs12_page;
352 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 353
354 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
355 struct list_head vmcs02_pool;
356 int vmcs02_num;
fe3ef05c 357 u64 vmcs01_tsc_offset;
644d711a
NHE		 358 /* L2 must run next, and mustn't decide to exit to L1. */
359 bool nested_run_pending;
fe3ef05c
NHE		 360 /*
361 * Guest pages referred to in vmcs02 with host-physical pointers, so
362 * we must keep them pinned while L2 runs.
363 */
364 struct page *apic_access_page;
ec378aee
NHE		 365};
366
a2fa3e9f 367struct vcpu_vmx {
fb3f0f51 368 struct kvm_vcpu vcpu;
313dbd49 369 unsigned long host_rsp;
29bd8a78 370 u8 fail;
69c73028 371 u8 cpl;
9d58b931 372 bool nmi_known_unmasked;
51aa01d1 373 u32 exit_intr_info;
1155f76a 374 u32 idt_vectoring_info;
6de12732 375 ulong rflags;
26bb0981 376 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 377 int nmsrs;
378 int save_nmsrs;
a2fa3e9f 379#ifdef CONFIG_X86_64
44ea2b17
AK		 380 u64 msr_host_kernel_gs_base;
381 u64 msr_guest_kernel_gs_base;
a2fa3e9f 382#endif
d462b819
NHE		 383 /*
384 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
385 * non-nested (L1) guest, it always points to vmcs01. For a nested
386 * guest (L2), it points to a different VMCS.
387 */
388 struct loaded_vmcs vmcs01;
389 struct loaded_vmcs *loaded_vmcs;
390 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 391 struct msr_autoload {
392 unsigned nr;
393 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
394 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
395 } msr_autoload;
a2fa3e9f
GH		 396 struct {
397 int loaded;
398 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 399#ifdef CONFIG_X86_64
400 u16 ds_sel, es_sel;
401#endif
152d3f2f
LV		 402 int gs_ldt_reload_needed;
403 int fs_reload_needed;
d77c26fc 404 } host_state;
9c8cba37 405 struct {
7ffd92c5 406 int vm86_active;
78ac8b47 407 ulong save_rflags;
7ffd92c5
AK		 408 struct kvm_save_segment {
409 u16 selector;
410 unsigned long base;
411 u32 limit;
412 u32 ar;
413 } tr, es, ds, fs, gs;
9c8cba37 414 } rmode;
2fb92db1
AK		 415 struct {
416 u32 bitmask; /* 4 bits per segment (1 bit per field) */
417 struct kvm_save_segment seg[8];
418 } segment_cache;
2384d2b3 419 int vpid;
04fa4d32 420 bool emulation_required;
3b86cd99
JK		 421
422 /* Support for vnmi-less CPUs */
423 int soft_vnmi_blocked;
424 ktime_t entry_time;
425 s64 vnmi_blocked_time;
a0861c02 426 u32 exit_reason;
4e47c7a6
SY		 427
428 bool rdtscp_enabled;
ec378aee
NHE		 429
430 /* Support for a guest hypervisor (nested VMX) */
431 struct nested_vmx nested;
a2fa3e9f
GH		 432};
433
2fb92db1
AK		 434enum segment_cache_field {
435 SEG_FIELD_SEL = 0,
436 SEG_FIELD_BASE = 1,
437 SEG_FIELD_LIMIT = 2,
438 SEG_FIELD_AR = 3,
439
440 SEG_FIELD_NR = 4
441};
442
a2fa3e9f
GH		 443static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
444{
fb3f0f51 445 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 446}
447
22bd0358
NHE		 448#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
449#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
450#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
451 [number##_HIGH] = VMCS12_OFFSET(name)+4
452
453static unsigned short vmcs_field_to_offset_table[] = {
454 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
455 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
456 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
457 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
458 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
459 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
460 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
461 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
462 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
463 FIELD(HOST_ES_SELECTOR, host_es_selector),
464 FIELD(HOST_CS_SELECTOR, host_cs_selector),
465 FIELD(HOST_SS_SELECTOR, host_ss_selector),
466 FIELD(HOST_DS_SELECTOR, host_ds_selector),
467 FIELD(HOST_FS_SELECTOR, host_fs_selector),
468 FIELD(HOST_GS_SELECTOR, host_gs_selector),
469 FIELD(HOST_TR_SELECTOR, host_tr_selector),
470 FIELD64(IO_BITMAP_A, io_bitmap_a),
471 FIELD64(IO_BITMAP_B, io_bitmap_b),
472 FIELD64(MSR_BITMAP, msr_bitmap),
473 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
474 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
475 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
476 FIELD64(TSC_OFFSET, tsc_offset),
477 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
478 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
479 FIELD64(EPT_POINTER, ept_pointer),
480 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
481 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
482 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
483 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
484 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
485 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
486 FIELD64(GUEST_PDPTR0, guest_pdptr0),
487 FIELD64(GUEST_PDPTR1, guest_pdptr1),
488 FIELD64(GUEST_PDPTR2, guest_pdptr2),
489 FIELD64(GUEST_PDPTR3, guest_pdptr3),
490 FIELD64(HOST_IA32_PAT, host_ia32_pat),
491 FIELD64(HOST_IA32_EFER, host_ia32_efer),
492 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
493 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
494 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
495 FIELD(EXCEPTION_BITMAP, exception_bitmap),
496 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
497 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
498 FIELD(CR3_TARGET_COUNT, cr3_target_count),
499 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
500 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
501 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
502 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
503 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
504 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
505 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
506 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
507 FIELD(TPR_THRESHOLD, tpr_threshold),
508 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
509 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
510 FIELD(VM_EXIT_REASON, vm_exit_reason),
511 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
512 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
513 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
514 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
515 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
516 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
517 FIELD(GUEST_ES_LIMIT, guest_es_limit),
518 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
519 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
520 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
521 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
522 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
523 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
524 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
525 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
526 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
527 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
528 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
529 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
530 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
531 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
532 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
533 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
534 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
535 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
536 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
537 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
538 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
539 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
540 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
541 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
542 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
543 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
544 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
545 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
546 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
547 FIELD(EXIT_QUALIFICATION, exit_qualification),
548 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
549 FIELD(GUEST_CR0, guest_cr0),
550 FIELD(GUEST_CR3, guest_cr3),
551 FIELD(GUEST_CR4, guest_cr4),
552 FIELD(GUEST_ES_BASE, guest_es_base),
553 FIELD(GUEST_CS_BASE, guest_cs_base),
554 FIELD(GUEST_SS_BASE, guest_ss_base),
555 FIELD(GUEST_DS_BASE, guest_ds_base),
556 FIELD(GUEST_FS_BASE, guest_fs_base),
557 FIELD(GUEST_GS_BASE, guest_gs_base),
558 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
559 FIELD(GUEST_TR_BASE, guest_tr_base),
560 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
561 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
562 FIELD(GUEST_DR7, guest_dr7),
563 FIELD(GUEST_RSP, guest_rsp),
564 FIELD(GUEST_RIP, guest_rip),
565 FIELD(GUEST_RFLAGS, guest_rflags),
566 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
567 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
568 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
569 FIELD(HOST_CR0, host_cr0),
570 FIELD(HOST_CR3, host_cr3),
571 FIELD(HOST_CR4, host_cr4),
572 FIELD(HOST_FS_BASE, host_fs_base),
573 FIELD(HOST_GS_BASE, host_gs_base),
574 FIELD(HOST_TR_BASE, host_tr_base),
575 FIELD(HOST_GDTR_BASE, host_gdtr_base),
576 FIELD(HOST_IDTR_BASE, host_idtr_base),
577 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
578 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
579 FIELD(HOST_RSP, host_rsp),
580 FIELD(HOST_RIP, host_rip),
581};
582static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
583
584static inline short vmcs_field_to_offset(unsigned long field)
585{
586 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
587 return -1;
588 return vmcs_field_to_offset_table[field];
589}
590
a9d30f33
NHE		 591static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
592{
593 return to_vmx(vcpu)->nested.current_vmcs12;
594}
595
596static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
597{
598 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 599 if (is_error_page(page))
a9d30f33 600 return NULL;
32cad84f 601
a9d30f33
NHE		 602 return page;
603}
604
605static void nested_release_page(struct page *page)
606{
607 kvm_release_page_dirty(page);
608}
609
610static void nested_release_page_clean(struct page *page)
611{
612 kvm_release_page_clean(page);
613}
614
4e1096d2 615static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 616static void kvm_cpu_vmxon(u64 addr);
617static void kvm_cpu_vmxoff(void);
aff48baa 618static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 619static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 620static void vmx_set_segment(struct kvm_vcpu *vcpu,
621 struct kvm_segment *var, int seg);
622static void vmx_get_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
75880a01 624
6aa8b732
AK		 625static DEFINE_PER_CPU(struct vmcs *, vmxarea);
626static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 627/*
628 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
629 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
630 */
631static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 632static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 633
3e7c73e9
AK		 634static unsigned long *vmx_io_bitmap_a;
635static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 636static unsigned long *vmx_msr_bitmap_legacy;
637static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 638
110312c8 639static bool cpu_has_load_ia32_efer;
8bf00a52 640static bool cpu_has_load_perf_global_ctrl;
110312c8 641
2384d2b3
SY		 642static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
643static DEFINE_SPINLOCK(vmx_vpid_lock);
644
1c3d14fe 645static struct vmcs_config {
6aa8b732
AK		 646 int size;
647 int order;
648 u32 revision_id;
1c3d14fe
YS		 649 u32 pin_based_exec_ctrl;
650 u32 cpu_based_exec_ctrl;
f78e0e2e 651 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 652 u32 vmexit_ctrl;
653 u32 vmentry_ctrl;
654} vmcs_config;
6aa8b732 655
efff9e53 656static struct vmx_capability {
d56f546d
SY		 657 u32 ept;
658 u32 vpid;
659} vmx_capability;
660
6aa8b732
AK		 661#define VMX_SEGMENT_FIELD(seg) \
662 [VCPU_SREG_##seg] = { \
663 .selector = GUEST_##seg##_SELECTOR, \
664 .base = GUEST_##seg##_BASE, \
665 .limit = GUEST_##seg##_LIMIT, \
666 .ar_bytes = GUEST_##seg##_AR_BYTES, \
667 }
668
669static struct kvm_vmx_segment_field {
670 unsigned selector;
671 unsigned base;
672 unsigned limit;
673 unsigned ar_bytes;
674} kvm_vmx_segment_fields[] = {
675 VMX_SEGMENT_FIELD(CS),
676 VMX_SEGMENT_FIELD(DS),
677 VMX_SEGMENT_FIELD(ES),
678 VMX_SEGMENT_FIELD(FS),
679 VMX_SEGMENT_FIELD(GS),
680 VMX_SEGMENT_FIELD(SS),
681 VMX_SEGMENT_FIELD(TR),
682 VMX_SEGMENT_FIELD(LDTR),
683};
684
26bb0981
AK		 685static u64 host_efer;
686
6de4f3ad
AK		 687static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
688
4d56c8a7 689/*
8c06585d 690 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 691 * away by decrementing the array size.
692 */
6aa8b732 693static const u32 vmx_msr_index[] = {
05b3e0c2 694#ifdef CONFIG_X86_64
44ea2b17 695 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 696#endif
8c06585d 697 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 698};
9d8f549d 699#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 700
31299944 701static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 702{
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 705 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 706}
707
31299944 708static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 709{
710 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
711 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 712 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 713}
714
31299944 715static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 716{
717 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
718 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 719 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 720}
721
31299944 722static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 723{
724 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
725 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
726}
727
31299944 728static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 729{
730 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
731 INTR_INFO_VALID_MASK)) ==
732 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
733}
734
31299944 735static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 736{
04547156 737 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 738}
739
31299944 740static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 741{
04547156 742 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 743}
744
31299944 745static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 746{
04547156 747 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 748}
749
31299944 750static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 751{
04547156
SY		 752 return vmcs_config.cpu_based_exec_ctrl &
753 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 754}
755
774ead3a 756static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 757{
04547156
SY		 758 return vmcs_config.cpu_based_2nd_exec_ctrl &
759 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
760}
761
762static inline bool cpu_has_vmx_flexpriority(void)
763{
764 return cpu_has_vmx_tpr_shadow() &&
765 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 766}
767
e799794e
MT		 768static inline bool cpu_has_vmx_ept_execute_only(void)
769{
31299944 770 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 771}
772
773static inline bool cpu_has_vmx_eptp_uncacheable(void)
774{
31299944 775 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 776}
777
778static inline bool cpu_has_vmx_eptp_writeback(void)
779{
31299944 780 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 781}
782
783static inline bool cpu_has_vmx_ept_2m_page(void)
784{
31299944 785 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 786}
787
878403b7
SY		 788static inline bool cpu_has_vmx_ept_1g_page(void)
789{
31299944 790 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 791}
792
4bc9b982
SY		 793static inline bool cpu_has_vmx_ept_4levels(void)
794{
795 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
796}
797
83c3a331
XH		 798static inline bool cpu_has_vmx_ept_ad_bits(void)
799{
800 return vmx_capability.ept & VMX_EPT_AD_BIT;
801}
802
31299944 803static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 804{
31299944 805 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 806}
807
31299944 808static inline bool cpu_has_vmx_invept_context(void)
d56f546d 809{
31299944 810 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_invept_global(void)
d56f546d 814{
31299944 815 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 816}
817
518c8aee
GJ		 818static inline bool cpu_has_vmx_invvpid_single(void)
819{
820 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
821}
822
b9d762fa
GJ		 823static inline bool cpu_has_vmx_invvpid_global(void)
824{
825 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
826}
827
31299944 828static inline bool cpu_has_vmx_ept(void)
d56f546d 829{
04547156
SY		 830 return vmcs_config.cpu_based_2nd_exec_ctrl &
831 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 832}
833
31299944 834static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 835{
836 return vmcs_config.cpu_based_2nd_exec_ctrl &
837 SECONDARY_EXEC_UNRESTRICTED_GUEST;
838}
839
31299944 840static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 841{
842 return vmcs_config.cpu_based_2nd_exec_ctrl &
843 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
844}
845
31299944 846static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 847{
6d3e435e 848 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_vpid(void)
2384d2b3 852{
04547156
SY		 853 return vmcs_config.cpu_based_2nd_exec_ctrl &
854 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 855}
856
31299944 857static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 858{
859 return vmcs_config.cpu_based_2nd_exec_ctrl &
860 SECONDARY_EXEC_RDTSCP;
861}
862
ad756a16
MJ		 863static inline bool cpu_has_vmx_invpcid(void)
864{
865 return vmcs_config.cpu_based_2nd_exec_ctrl &
866 SECONDARY_EXEC_ENABLE_INVPCID;
867}
868
31299944 869static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 870{
871 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
872}
873
f5f48ee1
SY		 874static inline bool cpu_has_vmx_wbinvd_exit(void)
875{
876 return vmcs_config.cpu_based_2nd_exec_ctrl &
877 SECONDARY_EXEC_WBINVD_EXITING;
878}
879
04547156
SY		 880static inline bool report_flexpriority(void)
881{
882 return flexpriority_enabled;
883}
884
fe3ef05c
NHE		 885static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
886{
887 return vmcs12->cpu_based_vm_exec_control & bit;
888}
889
890static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
891{
892 return (vmcs12->cpu_based_vm_exec_control &
893 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
894 (vmcs12->secondary_vm_exec_control & bit);
895}
896
644d711a
NHE		 897static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
898 struct kvm_vcpu *vcpu)
899{
900 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
901}
902
903static inline bool is_exception(u32 intr_info)
904{
905 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
906 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
907}
908
909static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 910static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
911 struct vmcs12 *vmcs12,
912 u32 reason, unsigned long qualification);
913
8b9cf98c 914static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 915{
916 int i;
917
a2fa3e9f 918 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 919 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 920 return i;
921 return -1;
922}
923
2384d2b3
SY		 924static inline void __invvpid(int ext, u16 vpid, gva_t gva)
925{
926 struct {
927 u64 vpid : 16;
928 u64 rsvd : 48;
929 u64 gva;
930 } operand = { vpid, 0, gva };
931
4ecac3fd 932 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 933 /* CF==1 or ZF==1 --> rc = -1 */
934 "; ja 1f ; ud2 ; 1:"
935 : : "a"(&operand), "c"(ext) : "cc", "memory");
936}
937
1439442c
SY		 938static inline void __invept(int ext, u64 eptp, gpa_t gpa)
939{
940 struct {
941 u64 eptp, gpa;
942 } operand = {eptp, gpa};
943
4ecac3fd 944 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 945 /* CF==1 or ZF==1 --> rc = -1 */
946 "; ja 1f ; ud2 ; 1:\n"
947 : : "a" (&operand), "c" (ext) : "cc", "memory");
948}
949
26bb0981 950static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 951{
952 int i;
953
8b9cf98c 954 i = __find_msr_index(vmx, msr);
a75beee6 955 if (i >= 0)
a2fa3e9f 956 return &vmx->guest_msrs[i];
8b6d44c7 957 return NULL;
7725f0ba
AK		 958}
959
6aa8b732
AK		 960static void vmcs_clear(struct vmcs *vmcs)
961{
962 u64 phys_addr = __pa(vmcs);
963 u8 error;
964
4ecac3fd 965 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 966 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 967 : "cc", "memory");
968 if (error)
969 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
970 vmcs, phys_addr);
971}
972
d462b819
NHE		 973static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
974{
975 vmcs_clear(loaded_vmcs->vmcs);
976 loaded_vmcs->cpu = -1;
977 loaded_vmcs->launched = 0;
978}
979
7725b894
DX		 980static void vmcs_load(struct vmcs *vmcs)
981{
982 u64 phys_addr = __pa(vmcs);
983 u8 error;
984
985 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 986 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 987 : "cc", "memory");
988 if (error)
2844d849 989 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 990 vmcs, phys_addr);
991}
992
d462b819 993static void __loaded_vmcs_clear(void *arg)
6aa8b732 994{
d462b819 995 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 996 int cpu = raw_smp_processor_id();
6aa8b732 997
d462b819
NHE		 998 if (loaded_vmcs->cpu != cpu)
999 return; /* vcpu migration can race with cpu offline */
1000 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1001 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 1002 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1003 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 1004}
1005
d462b819 1006static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1007{
d462b819
NHE		 1008 if (loaded_vmcs->cpu != -1)
1009 smp_call_function_single(
1010 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1011}
1012
1760dd49 1013static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1014{
1015 if (vmx->vpid == 0)
1016 return;
1017
518c8aee
GJ		 1018 if (cpu_has_vmx_invvpid_single())
1019 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1020}
1021
b9d762fa
GJ		 1022static inline void vpid_sync_vcpu_global(void)
1023{
1024 if (cpu_has_vmx_invvpid_global())
1025 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1026}
1027
1028static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1029{
1030 if (cpu_has_vmx_invvpid_single())
1760dd49 1031 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1032 else
1033 vpid_sync_vcpu_global();
1034}
1035
1439442c
SY		 1036static inline void ept_sync_global(void)
1037{
1038 if (cpu_has_vmx_invept_global())
1039 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1040}
1041
1042static inline void ept_sync_context(u64 eptp)
1043{
089d034e 1044 if (enable_ept) {
1439442c
SY		 1045 if (cpu_has_vmx_invept_context())
1046 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1047 else
1048 ept_sync_global();
1049 }
1050}
1051
1052static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1053{
089d034e 1054 if (enable_ept) {
1439442c
SY		 1055 if (cpu_has_vmx_invept_individual_addr())
1056 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1057 eptp, gpa);
1058 else
1059 ept_sync_context(eptp);
1060 }
1061}
1062
96304217 1063static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1064{
5e520e62 1065 unsigned long value;
6aa8b732 1066
5e520e62
AK		 1067 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1068 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1069 return value;
1070}
1071
96304217 1072static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1073{
1074 return vmcs_readl(field);
1075}
1076
96304217 1077static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1078{
1079 return vmcs_readl(field);
1080}
1081
96304217 1082static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1083{
05b3e0c2 1084#ifdef CONFIG_X86_64
6aa8b732
AK		 1085 return vmcs_readl(field);
1086#else
1087 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1088#endif
1089}
1090
e52de1b8
AK		 1091static noinline void vmwrite_error(unsigned long field, unsigned long value)
1092{
1093 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1094 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1095 dump_stack();
1096}
1097
6aa8b732
AK		 1098static void vmcs_writel(unsigned long field, unsigned long value)
1099{
1100 u8 error;
1101
4ecac3fd 1102 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1103 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1104 if (unlikely(error))
1105 vmwrite_error(field, value);
6aa8b732
AK		 1106}
1107
1108static void vmcs_write16(unsigned long field, u16 value)
1109{
1110 vmcs_writel(field, value);
1111}
1112
1113static void vmcs_write32(unsigned long field, u32 value)
1114{
1115 vmcs_writel(field, value);
1116}
1117
1118static void vmcs_write64(unsigned long field, u64 value)
1119{
6aa8b732 1120 vmcs_writel(field, value);
7682f2d0 1121#ifndef CONFIG_X86_64
6aa8b732
AK		 1122 asm volatile ("");
1123 vmcs_writel(field+1, value >> 32);
1124#endif
1125}
1126
2ab455cc
AL		 1127static void vmcs_clear_bits(unsigned long field, u32 mask)
1128{
1129 vmcs_writel(field, vmcs_readl(field) & ~mask);
1130}
1131
1132static void vmcs_set_bits(unsigned long field, u32 mask)
1133{
1134 vmcs_writel(field, vmcs_readl(field) | mask);
1135}
1136
2fb92db1
AK		 1137static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1138{
1139 vmx->segment_cache.bitmask = 0;
1140}
1141
1142static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1143 unsigned field)
1144{
1145 bool ret;
1146 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1147
1148 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1149 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1150 vmx->segment_cache.bitmask = 0;
1151 }
1152 ret = vmx->segment_cache.bitmask & mask;
1153 vmx->segment_cache.bitmask |= mask;
1154 return ret;
1155}
1156
1157static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 u16 *p = &vmx->segment_cache.seg[seg].selector;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1162 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1163 return *p;
1164}
1165
1166static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1167{
1168 ulong *p = &vmx->segment_cache.seg[seg].base;
1169
1170 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1171 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1172 return *p;
1173}
1174
1175static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1176{
1177 u32 *p = &vmx->segment_cache.seg[seg].limit;
1178
1179 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1180 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1181 return *p;
1182}
1183
1184static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1185{
1186 u32 *p = &vmx->segment_cache.seg[seg].ar;
1187
1188 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1189 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1190 return *p;
1191}
1192
abd3f2d6
AK		 1193static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1194{
1195 u32 eb;
1196
fd7373cc
JK		 1197 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1198 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1199 if ((vcpu->guest_debug &
1200 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1201 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1202 eb |= 1u << BP_VECTOR;
7ffd92c5 1203 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1204 eb = ~0;
089d034e 1205 if (enable_ept)
1439442c 1206 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1207 if (vcpu->fpu_active)
1208 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1209
1210 /* When we are running a nested L2 guest and L1 specified for it a
1211 * certain exception bitmap, we must trap the same exceptions and pass
1212 * them to L1. When running L2, we will only handle the exceptions
1213 * specified above if L1 did not want them.
1214 */
1215 if (is_guest_mode(vcpu))
1216 eb |= get_vmcs12(vcpu)->exception_bitmap;
1217
abd3f2d6
AK		 1218 vmcs_write32(EXCEPTION_BITMAP, eb);
1219}
1220
8bf00a52
GN		 1221static void clear_atomic_switch_msr_special(unsigned long entry,
1222 unsigned long exit)
1223{
1224 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1225 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1226}
1227
61d2ef2c
AK		 1228static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1229{
1230 unsigned i;
1231 struct msr_autoload *m = &vmx->msr_autoload;
1232
8bf00a52
GN		 1233 switch (msr) {
1234 case MSR_EFER:
1235 if (cpu_has_load_ia32_efer) {
1236 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1237 VM_EXIT_LOAD_IA32_EFER);
1238 return;
1239 }
1240 break;
1241 case MSR_CORE_PERF_GLOBAL_CTRL:
1242 if (cpu_has_load_perf_global_ctrl) {
1243 clear_atomic_switch_msr_special(
1244 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1245 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1246 return;
1247 }
1248 break;
110312c8
AK		 1249 }
1250
61d2ef2c
AK		 1251 for (i = 0; i < m->nr; ++i)
1252 if (m->guest[i].index == msr)
1253 break;
1254
1255 if (i == m->nr)
1256 return;
1257 --m->nr;
1258 m->guest[i] = m->guest[m->nr];
1259 m->host[i] = m->host[m->nr];
1260 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1261 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1262}
1263
8bf00a52
GN		 1264static void add_atomic_switch_msr_special(unsigned long entry,
1265 unsigned long exit, unsigned long guest_val_vmcs,
1266 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1267{
1268 vmcs_write64(guest_val_vmcs, guest_val);
1269 vmcs_write64(host_val_vmcs, host_val);
1270 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1271 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1272}
1273
61d2ef2c
AK		 1274static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1275 u64 guest_val, u64 host_val)
1276{
1277 unsigned i;
1278 struct msr_autoload *m = &vmx->msr_autoload;
1279
8bf00a52
GN		 1280 switch (msr) {
1281 case MSR_EFER:
1282 if (cpu_has_load_ia32_efer) {
1283 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1284 VM_EXIT_LOAD_IA32_EFER,
1285 GUEST_IA32_EFER,
1286 HOST_IA32_EFER,
1287 guest_val, host_val);
1288 return;
1289 }
1290 break;
1291 case MSR_CORE_PERF_GLOBAL_CTRL:
1292 if (cpu_has_load_perf_global_ctrl) {
1293 add_atomic_switch_msr_special(
1294 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1295 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1296 GUEST_IA32_PERF_GLOBAL_CTRL,
1297 HOST_IA32_PERF_GLOBAL_CTRL,
1298 guest_val, host_val);
1299 return;
1300 }
1301 break;
110312c8
AK		 1302 }
1303
61d2ef2c
AK		 1304 for (i = 0; i < m->nr; ++i)
1305 if (m->guest[i].index == msr)
1306 break;
1307
e7fc6f93
GN		 1308 if (i == NR_AUTOLOAD_MSRS) {
1309 printk_once(KERN_WARNING"Not enough mst switch entries. "
1310 "Can't add msr %x\n", msr);
1311 return;
1312 } else if (i == m->nr) {
61d2ef2c
AK		 1313 ++m->nr;
1314 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1315 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1316 }
1317
1318 m->guest[i].index = msr;
1319 m->guest[i].value = guest_val;
1320 m->host[i].index = msr;
1321 m->host[i].value = host_val;
1322}
1323
33ed6329
AK		 1324static void reload_tss(void)
1325{
33ed6329
AK		 1326 /*
1327 * VT restores TR but not its size. Useless.
1328 */
d359192f 1329 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1330 struct desc_struct *descs;
33ed6329 1331
d359192f 1332 descs = (void *)gdt->address;
33ed6329
AK		 1333 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1334 load_TR_desc();
33ed6329
AK		 1335}
1336
92c0d900 1337static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1338{
3a34a881 1339 u64 guest_efer;
51c6cf66
AK		 1340 u64 ignore_bits;
1341
f6801dff 1342 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1343
51c6cf66 1344 /*
0fa06071 1345 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1346 * outside long mode
1347 */
1348 ignore_bits = EFER_NX | EFER_SCE;
1349#ifdef CONFIG_X86_64
1350 ignore_bits |= EFER_LMA | EFER_LME;
1351 /* SCE is meaningful only in long mode on Intel */
1352 if (guest_efer & EFER_LMA)
1353 ignore_bits &= ~(u64)EFER_SCE;
1354#endif
51c6cf66
AK		 1355 guest_efer &= ~ignore_bits;
1356 guest_efer |= host_efer & ignore_bits;
26bb0981 1357 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1358 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1359
1360 clear_atomic_switch_msr(vmx, MSR_EFER);
1361 /* On ept, can't emulate nx, and must switch nx atomically */
1362 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1363 guest_efer = vmx->vcpu.arch.efer;
1364 if (!(guest_efer & EFER_LMA))
1365 guest_efer &= ~EFER_LME;
1366 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1367 return false;
1368 }
1369
26bb0981 1370 return true;
51c6cf66
AK		 1371}
1372
2d49ec72
GN		 1373static unsigned long segment_base(u16 selector)
1374{
d359192f 1375 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1376 struct desc_struct *d;
1377 unsigned long table_base;
1378 unsigned long v;
1379
1380 if (!(selector & ~3))
1381 return 0;
1382
d359192f 1383 table_base = gdt->address;
2d49ec72
GN		 1384
1385 if (selector & 4) { /* from ldt */
1386 u16 ldt_selector = kvm_read_ldt();
1387
1388 if (!(ldt_selector & ~3))
1389 return 0;
1390
1391 table_base = segment_base(ldt_selector);
1392 }
1393 d = (struct desc_struct *)(table_base + (selector & ~7));
1394 v = get_desc_base(d);
1395#ifdef CONFIG_X86_64
1396 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1397 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1398#endif
1399 return v;
1400}
1401
1402static inline unsigned long kvm_read_tr_base(void)
1403{
1404 u16 tr;
1405 asm("str %0" : "=g"(tr));
1406 return segment_base(tr);
1407}
1408
04d2cc77 1409static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1410{
04d2cc77 1411 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1412 int i;
04d2cc77 1413
a2fa3e9f 1414 if (vmx->host_state.loaded)
33ed6329
AK		 1415 return;
1416
a2fa3e9f 1417 vmx->host_state.loaded = 1;
33ed6329
AK		 1418 /*
1419 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1420 * allow segment selectors with cpl > 0 or ti == 1.
1421 */
d6e88aec 1422 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1423 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1424 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1425 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1426 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1427 vmx->host_state.fs_reload_needed = 0;
1428 } else {
33ed6329 1429 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1430 vmx->host_state.fs_reload_needed = 1;
33ed6329 1431 }
9581d442 1432 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1433 if (!(vmx->host_state.gs_sel & 7))
1434 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1435 else {
1436 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1437 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1438 }
1439
b2da15ac
AK		 1440#ifdef CONFIG_X86_64
1441 savesegment(ds, vmx->host_state.ds_sel);
1442 savesegment(es, vmx->host_state.es_sel);
1443#endif
1444
33ed6329
AK		 1445#ifdef CONFIG_X86_64
1446 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1447 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1448#else
a2fa3e9f
GH		 1449 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1450 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1451#endif
707c0874
AK		 1452
1453#ifdef CONFIG_X86_64
c8770e7b
AK		 1454 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1455 if (is_long_mode(&vmx->vcpu))
44ea2b17 1456 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1457#endif
26bb0981
AK		 1458 for (i = 0; i < vmx->save_nmsrs; ++i)
1459 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1460 vmx->guest_msrs[i].data,
1461 vmx->guest_msrs[i].mask);
33ed6329
AK		 1462}
1463
a9b21b62 1464static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1465{
a2fa3e9f 1466 if (!vmx->host_state.loaded)
33ed6329
AK		 1467 return;
1468
e1beb1d3 1469 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1470 vmx->host_state.loaded = 0;
c8770e7b
AK		 1471#ifdef CONFIG_X86_64
1472 if (is_long_mode(&vmx->vcpu))
1473 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1474#endif
152d3f2f 1475 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1476 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1477#ifdef CONFIG_X86_64
9581d442 1478 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1479#else
1480 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1481#endif
33ed6329 1482 }
0a77fe4c
AK		 1483 if (vmx->host_state.fs_reload_needed)
1484 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1485#ifdef CONFIG_X86_64
1486 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1487 loadsegment(ds, vmx->host_state.ds_sel);
1488 loadsegment(es, vmx->host_state.es_sel);
1489 }
b2da15ac 1490#endif
152d3f2f 1491 reload_tss();
44ea2b17 1492#ifdef CONFIG_X86_64
c8770e7b 1493 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1494#endif
1361b83a 1495 if (user_has_fpu())
1c11e713 1496 clts();
3444d7da 1497 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1498}
1499
a9b21b62
AK		 1500static void vmx_load_host_state(struct vcpu_vmx *vmx)
1501{
1502 preempt_disable();
1503 __vmx_load_host_state(vmx);
1504 preempt_enable();
1505}
1506
6aa8b732
AK		 1507/*
1508 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1509 * vcpu mutex is already taken.
1510 */
15ad7146 1511static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1512{
a2fa3e9f 1513 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1514 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1515
4610c9cc
DX		 1516 if (!vmm_exclusive)
1517 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1518 else if (vmx->loaded_vmcs->cpu != cpu)
1519 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1520
d462b819
NHE		 1521 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1522 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1523 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1524 }
1525
d462b819 1526 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1527 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1528 unsigned long sysenter_esp;
1529
a8eeb04a 1530 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1531 local_irq_disable();
d462b819
NHE		 1532 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1533 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1534 local_irq_enable();
1535
6aa8b732
AK		 1536 /*
1537 * Linux uses per-cpu TSS and GDT, so set these when switching
1538 * processors.
1539 */
d6e88aec 1540 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1541 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1542
1543 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1544 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1545 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1546 }
6aa8b732
AK		 1547}
1548
1549static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1550{
a9b21b62 1551 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1552 if (!vmm_exclusive) {
d462b819
NHE		 1553 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1554 vcpu->cpu = -1;
4610c9cc
DX		 1555 kvm_cpu_vmxoff();
1556 }
6aa8b732
AK		 1557}
1558
5fd86fcf
AK		 1559static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1560{
81231c69
AK		 1561 ulong cr0;
1562
5fd86fcf
AK		 1563 if (vcpu->fpu_active)
1564 return;
1565 vcpu->fpu_active = 1;
81231c69
AK		 1566 cr0 = vmcs_readl(GUEST_CR0);
1567 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1568 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1569 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1570 update_exception_bitmap(vcpu);
edcafe3c 1571 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1572 if (is_guest_mode(vcpu))
1573 vcpu->arch.cr0_guest_owned_bits &=
1574 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1575 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1576}
1577
edcafe3c
AK		 1578static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1579
fe3ef05c
NHE		 1580/*
1581 * Return the cr0 value that a nested guest would read. This is a combination
1582 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1583 * its hypervisor (cr0_read_shadow).
1584 */
1585static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1586{
1587 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1588 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1589}
1590static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1591{
1592 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1593 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1594}
1595
5fd86fcf
AK		 1596static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1597{
36cf24e0
NHE		 1598 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1599 * set this *before* calling this function.
1600 */
edcafe3c 1601 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1602 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1603 update_exception_bitmap(vcpu);
edcafe3c
AK		 1604 vcpu->arch.cr0_guest_owned_bits = 0;
1605 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1606 if (is_guest_mode(vcpu)) {
1607 /*
1608 * L1's specified read shadow might not contain the TS bit,
1609 * so now that we turned on shadowing of this bit, we need to
1610 * set this bit of the shadow. Like in nested_vmx_run we need
1611 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1612 * up-to-date here because we just decached cr0.TS (and we'll
1613 * only update vmcs12->guest_cr0 on nested exit).
1614 */
1615 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1616 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1617 (vcpu->arch.cr0 & X86_CR0_TS);
1618 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1619 } else
1620 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1621}
1622
6aa8b732
AK		 1623static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1624{
78ac8b47 1625 unsigned long rflags, save_rflags;
345dcaa8 1626
6de12732
AK		 1627 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1628 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1629 rflags = vmcs_readl(GUEST_RFLAGS);
1630 if (to_vmx(vcpu)->rmode.vm86_active) {
1631 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1632 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1633 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1634 }
1635 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1636 }
6de12732 1637 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1638}
1639
1640static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1641{
6de12732 1642 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1643 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1644 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1645 if (to_vmx(vcpu)->rmode.vm86_active) {
1646 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1647 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1648 }
6aa8b732
AK		 1649 vmcs_writel(GUEST_RFLAGS, rflags);
1650}
1651
2809f5d2
GC		 1652static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1653{
1654 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1655 int ret = 0;
1656
1657 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1658 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1659 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1660 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1661
1662 return ret & mask;
1663}
1664
1665static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1666{
1667 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1668 u32 interruptibility = interruptibility_old;
1669
1670 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1671
48005f64 1672 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1673 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1674 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1675 interruptibility |= GUEST_INTR_STATE_STI;
1676
1677 if ((interruptibility != interruptibility_old))
1678 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1679}
1680
6aa8b732
AK		 1681static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1682{
1683 unsigned long rip;
6aa8b732 1684
5fdbf976 1685 rip = kvm_rip_read(vcpu);
6aa8b732 1686 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1687 kvm_rip_write(vcpu, rip);
6aa8b732 1688
2809f5d2
GC		 1689 /* skipping an emulated instruction also counts */
1690 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1691}
1692
0b6ac343
NHE		 1693/*
1694 * KVM wants to inject page-faults which it got to the guest. This function
1695 * checks whether in a nested guest, we need to inject them to L1 or L2.
1696 * This function assumes it is called with the exit reason in vmcs02 being
1697 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1698 * is running).
1699 */
1700static int nested_pf_handled(struct kvm_vcpu *vcpu)
1701{
1702 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1703
1704 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1705 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1706 return 0;
1707
1708 nested_vmx_vmexit(vcpu);
1709 return 1;
1710}
1711
298101da 1712static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1713 bool has_error_code, u32 error_code,
1714 bool reinject)
298101da 1715{
77ab6db0 1716 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1717 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1718
0b6ac343
NHE		 1719 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1720 nested_pf_handled(vcpu))
1721 return;
1722
8ab2d2e2 1723 if (has_error_code) {
77ab6db0 1724 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1725 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1726 }
77ab6db0 1727
7ffd92c5 1728 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1729 int inc_eip = 0;
1730 if (kvm_exception_is_soft(nr))
1731 inc_eip = vcpu->arch.event_exit_inst_len;
1732 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1733 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1734 return;
1735 }
1736
66fd3f7f
GN		 1737 if (kvm_exception_is_soft(nr)) {
1738 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1739 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1740 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1741 } else
1742 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1743
1744 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1745}
1746
4e47c7a6
SY		 1747static bool vmx_rdtscp_supported(void)
1748{
1749 return cpu_has_vmx_rdtscp();
1750}
1751
ad756a16
MJ		 1752static bool vmx_invpcid_supported(void)
1753{
1754 return cpu_has_vmx_invpcid() && enable_ept;
1755}
1756
a75beee6
ED		 1757/*
1758 * Swap MSR entry in host/guest MSR entry array.
1759 */
8b9cf98c 1760static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1761{
26bb0981 1762 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1763
1764 tmp = vmx->guest_msrs[to];
1765 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1766 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1767}
1768
e38aea3e
AK		 1769/*
1770 * Set up the vmcs to automatically save and restore system
1771 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1772 * mode, as fiddling with msrs is very expensive.
1773 */
8b9cf98c 1774static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1775{
26bb0981 1776 int save_nmsrs, index;
5897297b 1777 unsigned long *msr_bitmap;
e38aea3e 1778
a75beee6
ED		 1779 save_nmsrs = 0;
1780#ifdef CONFIG_X86_64
8b9cf98c 1781 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1782 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1783 if (index >= 0)
8b9cf98c
RR		 1784 move_msr_up(vmx, index, save_nmsrs++);
1785 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1786 if (index >= 0)
8b9cf98c
RR		 1787 move_msr_up(vmx, index, save_nmsrs++);
1788 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1789 if (index >= 0)
8b9cf98c 1790 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1791 index = __find_msr_index(vmx, MSR_TSC_AUX);
1792 if (index >= 0 && vmx->rdtscp_enabled)
1793 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1794 /*
8c06585d 1795 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1796 * if efer.sce is enabled.
1797 */
8c06585d 1798 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1799 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1800 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1801 }
1802#endif
92c0d900
AK		 1803 index = __find_msr_index(vmx, MSR_EFER);
1804 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1805 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1806
26bb0981 1807 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1808
1809 if (cpu_has_vmx_msr_bitmap()) {
1810 if (is_long_mode(&vmx->vcpu))
1811 msr_bitmap = vmx_msr_bitmap_longmode;
1812 else
1813 msr_bitmap = vmx_msr_bitmap_legacy;
1814
1815 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1816 }
e38aea3e
AK		 1817}
1818
6aa8b732
AK		 1819/*
1820 * reads and returns guest's timestamp counter "register"
1821 * guest_tsc = host_tsc + tsc_offset -- 21.3
1822 */
1823static u64 guest_read_tsc(void)
1824{
1825 u64 host_tsc, tsc_offset;
1826
1827 rdtscll(host_tsc);
1828 tsc_offset = vmcs_read64(TSC_OFFSET);
1829 return host_tsc + tsc_offset;
1830}
1831
d5c1785d
NHE		 1832/*
1833 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1834 * counter, even if a nested guest (L2) is currently running.
1835 */
1836u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1837{
1838 u64 host_tsc, tsc_offset;
1839
1840 rdtscll(host_tsc);
1841 tsc_offset = is_guest_mode(vcpu) ?
1842 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1843 vmcs_read64(TSC_OFFSET);
1844 return host_tsc + tsc_offset;
1845}
1846
4051b188 1847/*
cc578287
ZA		 1848 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1849 * software catchup for faster rates on slower CPUs.
4051b188 1850 */
cc578287 1851static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1852{
cc578287
ZA		 1853 if (!scale)
1854 return;
1855
1856 if (user_tsc_khz > tsc_khz) {
1857 vcpu->arch.tsc_catchup = 1;
1858 vcpu->arch.tsc_always_catchup = 1;
1859 } else
1860 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1861}
1862
6aa8b732 1863/*
99e3e30a 1864 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1865 */
99e3e30a 1866static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1867{
27fc51b2 1868 if (is_guest_mode(vcpu)) {
7991825b 1869 /*
27fc51b2
NHE		 1870 * We're here if L1 chose not to trap WRMSR to TSC. According
1871 * to the spec, this should set L1's TSC; The offset that L1
1872 * set for L2 remains unchanged, and still needs to be added
1873 * to the newly set TSC to get L2's TSC.
7991825b 1874 */
27fc51b2
NHE		 1875 struct vmcs12 *vmcs12;
1876 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1877 /* recalculate vmcs02.TSC_OFFSET: */
1878 vmcs12 = get_vmcs12(vcpu);
1879 vmcs_write64(TSC_OFFSET, offset +
1880 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1881 vmcs12->tsc_offset : 0));
1882 } else {
1883 vmcs_write64(TSC_OFFSET, offset);
1884 }
6aa8b732
AK		 1885}
1886
f1e2b260 1887static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1888{
1889 u64 offset = vmcs_read64(TSC_OFFSET);
1890 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1891 if (is_guest_mode(vcpu)) {
1892 /* Even when running L2, the adjustment needs to apply to L1 */
1893 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1894 }
e48672fa
ZA		 1895}
1896
857e4099
JR		 1897static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1898{
1899 return target_tsc - native_read_tsc();
1900}
1901
801d3424
NHE		 1902static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1903{
1904 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1905 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1906}
1907
1908/*
1909 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1910 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1911 * all guests if the "nested" module option is off, and can also be disabled
1912 * for a single guest by disabling its VMX cpuid bit.
1913 */
1914static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1915{
1916 return nested && guest_cpuid_has_vmx(vcpu);
1917}
1918
b87a51ae
NHE		 1919/*
1920 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1921 * returned for the various VMX controls MSRs when nested VMX is enabled.
1922 * The same values should also be used to verify that vmcs12 control fields are
1923 * valid during nested entry from L1 to L2.
1924 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1925 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1926 * bit in the high half is on if the corresponding bit in the control field
1927 * may be on. See also vmx_control_verify().
1928 * TODO: allow these variables to be modified (downgraded) by module options
1929 * or other means.
1930 */
1931static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1932static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1933static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1934static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1935static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1936static __init void nested_vmx_setup_ctls_msrs(void)
1937{
1938 /*
1939 * Note that as a general rule, the high half of the MSRs (bits in
1940 * the control fields which may be 1) should be initialized by the
1941 * intersection of the underlying hardware's MSR (i.e., features which
1942 * can be supported) and the list of features we want to expose -
1943 * because they are known to be properly supported in our code.
1944 * Also, usually, the low half of the MSRs (bits which must be 1) can
1945 * be set to 0, meaning that L1 may turn off any of these bits. The
1946 * reason is that if one of these bits is necessary, it will appear
1947 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1948 * fields of vmcs01 and vmcs02, will turn these bits off - and
1949 * nested_vmx_exit_handled() will not pass related exits to L1.
1950 * These rules have exceptions below.
1951 */
1952
1953 /* pin-based controls */
1954 /*
1955 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1956 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1957 */
1958 nested_vmx_pinbased_ctls_low = 0x16 ;
1959 nested_vmx_pinbased_ctls_high = 0x16 |
1960 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1961 PIN_BASED_VIRTUAL_NMIS;
1962
1963 /* exit controls */
1964 nested_vmx_exit_ctls_low = 0;
b6f1250e 1965 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1966#ifdef CONFIG_X86_64
1967 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1968#else
1969 nested_vmx_exit_ctls_high = 0;
1970#endif
1971
1972 /* entry controls */
1973 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1974 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1975 nested_vmx_entry_ctls_low = 0;
1976 nested_vmx_entry_ctls_high &=
1977 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1978
1979 /* cpu-based controls */
1980 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1981 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1982 nested_vmx_procbased_ctls_low = 0;
1983 nested_vmx_procbased_ctls_high &=
1984 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1985 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1986 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1987 CPU_BASED_CR3_STORE_EXITING |
1988#ifdef CONFIG_X86_64
1989 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1990#endif
1991 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1992 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
fee84b07 1993 CPU_BASED_RDPMC_EXITING |
b87a51ae
NHE		 1994 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1995 /*
1996 * We can allow some features even when not supported by the
1997 * hardware. For example, L1 can specify an MSR bitmap - and we
1998 * can use it to avoid exits to L1 - even when L0 runs L2
1999 * without MSR bitmaps.
2000 */
2001 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2002
2003 /* secondary cpu-based controls */
2004 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2005 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2006 nested_vmx_secondary_ctls_low = 0;
2007 nested_vmx_secondary_ctls_high &=
2008 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2009}
2010
2011static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2012{
2013 /*
2014 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2015 */
2016 return ((control & high) | low) == control;
2017}
2018
2019static inline u64 vmx_control_msr(u32 low, u32 high)
2020{
2021 return low | ((u64)high << 32);
2022}
2023
2024/*
2025 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2026 * also let it use VMX-specific MSRs.
2027 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2028 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2029 * like all other MSRs).
2030 */
2031static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2032{
2033 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2034 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2035 /*
2036 * According to the spec, processors which do not support VMX
2037 * should throw a #GP(0) when VMX capability MSRs are read.
2038 */
2039 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2040 return 1;
2041 }
2042
2043 switch (msr_index) {
2044 case MSR_IA32_FEATURE_CONTROL:
2045 *pdata = 0;
2046 break;
2047 case MSR_IA32_VMX_BASIC:
2048 /*
2049 * This MSR reports some information about VMX support. We
2050 * should return information about the VMX we emulate for the
2051 * guest, and the VMCS structure we give it - not about the
2052 * VMX support of the underlying hardware.
2053 */
2054 *pdata = VMCS12_REVISION |
2055 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2056 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2057 break;
2058 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2059 case MSR_IA32_VMX_PINBASED_CTLS:
2060 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2061 nested_vmx_pinbased_ctls_high);
2062 break;
2063 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2064 case MSR_IA32_VMX_PROCBASED_CTLS:
2065 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2066 nested_vmx_procbased_ctls_high);
2067 break;
2068 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2069 case MSR_IA32_VMX_EXIT_CTLS:
2070 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2071 nested_vmx_exit_ctls_high);
2072 break;
2073 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2074 case MSR_IA32_VMX_ENTRY_CTLS:
2075 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2076 nested_vmx_entry_ctls_high);
2077 break;
2078 case MSR_IA32_VMX_MISC:
2079 *pdata = 0;
2080 break;
2081 /*
2082 * These MSRs specify bits which the guest must keep fixed (on or off)
2083 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2084 * We picked the standard core2 setting.
2085 */
2086#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2087#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2088 case MSR_IA32_VMX_CR0_FIXED0:
2089 *pdata = VMXON_CR0_ALWAYSON;
2090 break;
2091 case MSR_IA32_VMX_CR0_FIXED1:
2092 *pdata = -1ULL;
2093 break;
2094 case MSR_IA32_VMX_CR4_FIXED0:
2095 *pdata = VMXON_CR4_ALWAYSON;
2096 break;
2097 case MSR_IA32_VMX_CR4_FIXED1:
2098 *pdata = -1ULL;
2099 break;
2100 case MSR_IA32_VMX_VMCS_ENUM:
2101 *pdata = 0x1f;
2102 break;
2103 case MSR_IA32_VMX_PROCBASED_CTLS2:
2104 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2105 nested_vmx_secondary_ctls_high);
2106 break;
2107 case MSR_IA32_VMX_EPT_VPID_CAP:
2108 /* Currently, no nested ept or nested vpid */
2109 *pdata = 0;
2110 break;
2111 default:
2112 return 0;
2113 }
2114
2115 return 1;
2116}
2117
2118static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2119{
2120 if (!nested_vmx_allowed(vcpu))
2121 return 0;
2122
2123 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2124 /* TODO: the right thing. */
2125 return 1;
2126 /*
2127 * No need to treat VMX capability MSRs specially: If we don't handle
2128 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2129 */
2130 return 0;
2131}
2132
6aa8b732
AK		 2133/*
2134 * Reads an msr value (of 'msr_index') into 'pdata'.
2135 * Returns 0 on success, non-0 otherwise.
2136 * Assumes vcpu_load() was already called.
2137 */
2138static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2139{
2140 u64 data;
26bb0981 2141 struct shared_msr_entry *msr;
6aa8b732
AK		 2142
2143 if (!pdata) {
2144 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2145 return -EINVAL;
2146 }
2147
2148 switch (msr_index) {
05b3e0c2 2149#ifdef CONFIG_X86_64
6aa8b732
AK		 2150 case MSR_FS_BASE:
2151 data = vmcs_readl(GUEST_FS_BASE);
2152 break;
2153 case MSR_GS_BASE:
2154 data = vmcs_readl(GUEST_GS_BASE);
2155 break;
44ea2b17
AK		 2156 case MSR_KERNEL_GS_BASE:
2157 vmx_load_host_state(to_vmx(vcpu));
2158 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2159 break;
26bb0981 2160#endif
6aa8b732 2161 case MSR_EFER:
3bab1f5d 2162 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2163 case MSR_IA32_TSC:
6aa8b732
AK		 2164 data = guest_read_tsc();
2165 break;
2166 case MSR_IA32_SYSENTER_CS:
2167 data = vmcs_read32(GUEST_SYSENTER_CS);
2168 break;
2169 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2170 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2171 break;
2172 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2173 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2174 break;
4e47c7a6
SY		 2175 case MSR_TSC_AUX:
2176 if (!to_vmx(vcpu)->rdtscp_enabled)
2177 return 1;
2178 /* Otherwise falls through */
6aa8b732 2179 default:
b87a51ae
NHE		 2180 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2181 return 0;
8b9cf98c 2182 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2183 if (msr) {
2184 data = msr->data;
2185 break;
6aa8b732 2186 }
3bab1f5d 2187 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2188 }
2189
2190 *pdata = data;
2191 return 0;
2192}
2193
2194/*
2195 * Writes msr value into into the appropriate "register".
2196 * Returns 0 on success, non-0 otherwise.
2197 * Assumes vcpu_load() was already called.
2198 */
2199static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2200{
a2fa3e9f 2201 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2202 struct shared_msr_entry *msr;
2cc51560
ED		 2203 int ret = 0;
2204
6aa8b732 2205 switch (msr_index) {
3bab1f5d 2206 case MSR_EFER:
2cc51560 2207 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2208 break;
16175a79 2209#ifdef CONFIG_X86_64
6aa8b732 2210 case MSR_FS_BASE:
2fb92db1 2211 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2212 vmcs_writel(GUEST_FS_BASE, data);
2213 break;
2214 case MSR_GS_BASE:
2fb92db1 2215 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2216 vmcs_writel(GUEST_GS_BASE, data);
2217 break;
44ea2b17
AK		 2218 case MSR_KERNEL_GS_BASE:
2219 vmx_load_host_state(vmx);
2220 vmx->msr_guest_kernel_gs_base = data;
2221 break;
6aa8b732
AK		 2222#endif
2223 case MSR_IA32_SYSENTER_CS:
2224 vmcs_write32(GUEST_SYSENTER_CS, data);
2225 break;
2226 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2227 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2228 break;
2229 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2230 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2231 break;
af24a4e4 2232 case MSR_IA32_TSC:
99e3e30a 2233 kvm_write_tsc(vcpu, data);
6aa8b732 2234 break;
468d472f
SY		 2235 case MSR_IA32_CR_PAT:
2236 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2237 vmcs_write64(GUEST_IA32_PAT, data);
2238 vcpu->arch.pat = data;
2239 break;
2240 }
4e47c7a6
SY		 2241 ret = kvm_set_msr_common(vcpu, msr_index, data);
2242 break;
2243 case MSR_TSC_AUX:
2244 if (!vmx->rdtscp_enabled)
2245 return 1;
2246 /* Check reserved bit, higher 32 bits should be zero */
2247 if ((data >> 32) != 0)
2248 return 1;
2249 /* Otherwise falls through */
6aa8b732 2250 default:
b87a51ae
NHE		 2251 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2252 break;
8b9cf98c 2253 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2254 if (msr) {
2255 msr->data = data;
2225fd56
AK		 2256 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2257 preempt_disable();
9ee73970
AK		 2258 kvm_set_shared_msr(msr->index, msr->data,
2259 msr->mask);
2225fd56
AK		 2260 preempt_enable();
2261 }
3bab1f5d 2262 break;
6aa8b732 2263 }
2cc51560 2264 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2265 }
2266
2cc51560 2267 return ret;
6aa8b732
AK		 2268}
2269
5fdbf976 2270static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2271{
5fdbf976
MT		 2272 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2273 switch (reg) {
2274 case VCPU_REGS_RSP:
2275 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2276 break;
2277 case VCPU_REGS_RIP:
2278 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2279 break;
6de4f3ad
AK		 2280 case VCPU_EXREG_PDPTR:
2281 if (enable_ept)
2282 ept_save_pdptrs(vcpu);
2283 break;
5fdbf976
MT		 2284 default:
2285 break;
2286 }
6aa8b732
AK		 2287}
2288
355be0b9 2289static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2290{
ae675ef0
JK		 2291 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2292 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2293 else
2294 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2295
abd3f2d6 2296 update_exception_bitmap(vcpu);
6aa8b732
AK		 2297}
2298
2299static __init int cpu_has_kvm_support(void)
2300{
6210e37b 2301 return cpu_has_vmx();
6aa8b732
AK		 2302}
2303
2304static __init int vmx_disabled_by_bios(void)
2305{
2306 u64 msr;
2307
2308 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2309 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2310 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2311 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2312 && tboot_enabled())
2313 return 1;
23f3e991 2314 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2315 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2316 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2317 && !tboot_enabled()) {
2318 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2319 "activate TXT before enabling KVM\n");
cafd6659 2320 return 1;
f9335afe 2321 }
23f3e991
JC		 2322 /* launched w/o TXT and VMX disabled */
2323 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2324 && !tboot_enabled())
2325 return 1;
cafd6659
SW		 2326 }
2327
2328 return 0;
6aa8b732
AK		 2329}
2330
7725b894
DX		 2331static void kvm_cpu_vmxon(u64 addr)
2332{
2333 asm volatile (ASM_VMX_VMXON_RAX
2334 : : "a"(&addr), "m"(addr)
2335 : "memory", "cc");
2336}
2337
10474ae8 2338static int hardware_enable(void *garbage)
6aa8b732
AK		 2339{
2340 int cpu = raw_smp_processor_id();
2341 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2342 u64 old, test_bits;
6aa8b732 2343
10474ae8
AG		 2344 if (read_cr4() & X86_CR4_VMXE)
2345 return -EBUSY;
2346
d462b819 2347 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2348 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2349
2350 test_bits = FEATURE_CONTROL_LOCKED;
2351 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2352 if (tboot_enabled())
2353 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2354
2355 if ((old & test_bits) != test_bits) {
6aa8b732 2356 /* enable and lock */
cafd6659
SW		 2357 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2358 }
66aee91a 2359 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2360
4610c9cc
DX		 2361 if (vmm_exclusive) {
2362 kvm_cpu_vmxon(phys_addr);
2363 ept_sync_global();
2364 }
10474ae8 2365
3444d7da
AK		 2366 store_gdt(&__get_cpu_var(host_gdt));
2367
10474ae8 2368 return 0;
6aa8b732
AK		 2369}
2370
d462b819 2371static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2372{
2373 int cpu = raw_smp_processor_id();
d462b819 2374 struct loaded_vmcs *v, *n;
543e4243 2375
d462b819
NHE		 2376 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2377 loaded_vmcss_on_cpu_link)
2378 __loaded_vmcs_clear(v);
543e4243
AK		 2379}
2380
710ff4a8
EH		 2381
2382/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2383 * tricks.
2384 */
2385static void kvm_cpu_vmxoff(void)
6aa8b732 2386{
4ecac3fd 2387 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2388}
2389
710ff4a8
EH		 2390static void hardware_disable(void *garbage)
2391{
4610c9cc 2392 if (vmm_exclusive) {
d462b819 2393 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2394 kvm_cpu_vmxoff();
2395 }
7725b894 2396 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2397}
2398
1c3d14fe 2399static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2400 u32 msr, u32 *result)
1c3d14fe
YS		 2401{
2402 u32 vmx_msr_low, vmx_msr_high;
2403 u32 ctl = ctl_min | ctl_opt;
2404
2405 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2406
2407 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2408 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2409
2410 /* Ensure minimum (required) set of control bits are supported. */
2411 if (ctl_min & ~ctl)
002c7f7c 2412 return -EIO;
1c3d14fe
YS		 2413
2414 *result = ctl;
2415 return 0;
2416}
2417
110312c8
AK		 2418static __init bool allow_1_setting(u32 msr, u32 ctl)
2419{
2420 u32 vmx_msr_low, vmx_msr_high;
2421
2422 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2423 return vmx_msr_high & ctl;
2424}
2425
002c7f7c 2426static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2427{
2428 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2429 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2430 u32 _pin_based_exec_control = 0;
2431 u32 _cpu_based_exec_control = 0;
f78e0e2e 2432 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2433 u32 _vmexit_control = 0;
2434 u32 _vmentry_control = 0;
2435
2436 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2437 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2439 &_pin_based_exec_control) < 0)
002c7f7c 2440 return -EIO;
1c3d14fe 2441
10166744 2442 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2443#ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING |
2445 CPU_BASED_CR8_STORE_EXITING |
2446#endif
d56f546d
SY		 2447 CPU_BASED_CR3_LOAD_EXITING |
2448 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2449 CPU_BASED_USE_IO_BITMAPS |
2450 CPU_BASED_MOV_DR_EXITING |
a7052897 2451 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2452 CPU_BASED_MWAIT_EXITING |
2453 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2454 CPU_BASED_INVLPG_EXITING |
2455 CPU_BASED_RDPMC_EXITING;
443381a8 2456
f78e0e2e 2457 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2458 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2459 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2460 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2461 &_cpu_based_exec_control) < 0)
002c7f7c 2462 return -EIO;
6e5d865c
YS		 2463#ifdef CONFIG_X86_64
2464 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2465 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2466 ~CPU_BASED_CR8_STORE_EXITING;
2467#endif
f78e0e2e 2468 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2469 min2 = 0;
2470 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2471 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2472 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2473 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2474 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2475 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16
MJ		 2476 SECONDARY_EXEC_RDTSCP |
2477 SECONDARY_EXEC_ENABLE_INVPCID;
d56f546d
SY		 2478 if (adjust_vmx_controls(min2, opt2,
2479 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2480 &_cpu_based_2nd_exec_control) < 0)
2481 return -EIO;
2482 }
2483#ifndef CONFIG_X86_64
2484 if (!(_cpu_based_2nd_exec_control &
2485 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2486 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2487#endif
d56f546d 2488 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2489 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2490 enabled */
5fff7d27
GN		 2491 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2492 CPU_BASED_CR3_STORE_EXITING |
2493 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2494 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2495 vmx_capability.ept, vmx_capability.vpid);
2496 }
1c3d14fe
YS		 2497
2498 min = 0;
2499#ifdef CONFIG_X86_64
2500 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2501#endif
468d472f 2502 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2503 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2504 &_vmexit_control) < 0)
002c7f7c 2505 return -EIO;
1c3d14fe 2506
468d472f
SY		 2507 min = 0;
2508 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2509 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2510 &_vmentry_control) < 0)
002c7f7c 2511 return -EIO;
6aa8b732 2512
c68876fd 2513 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2514
2515 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2516 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2517 return -EIO;
1c3d14fe
YS		 2518
2519#ifdef CONFIG_X86_64
2520 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2521 if (vmx_msr_high & (1u<<16))
002c7f7c 2522 return -EIO;
1c3d14fe
YS		 2523#endif
2524
2525 /* Require Write-Back (WB) memory type for VMCS accesses. */
2526 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2527 return -EIO;
1c3d14fe 2528
002c7f7c
YS		 2529 vmcs_conf->size = vmx_msr_high & 0x1fff;
2530 vmcs_conf->order = get_order(vmcs_config.size);
2531 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2532
002c7f7c
YS		 2533 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2534 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2535 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2536 vmcs_conf->vmexit_ctrl = _vmexit_control;
2537 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2538
110312c8
AK		 2539 cpu_has_load_ia32_efer =
2540 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2541 VM_ENTRY_LOAD_IA32_EFER)
2542 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2543 VM_EXIT_LOAD_IA32_EFER);
2544
8bf00a52
GN		 2545 cpu_has_load_perf_global_ctrl =
2546 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2547 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2548 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2549 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2550
2551 /*
2552 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2553 * but due to arrata below it can't be used. Workaround is to use
2554 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2555 *
2556 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2557 *
2558 * AAK155 (model 26)
2559 * AAP115 (model 30)
2560 * AAT100 (model 37)
2561 * BC86,AAY89,BD102 (model 44)
2562 * BA97 (model 46)
2563 *
2564 */
2565 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2566 switch (boot_cpu_data.x86_model) {
2567 case 26:
2568 case 30:
2569 case 37:
2570 case 44:
2571 case 46:
2572 cpu_has_load_perf_global_ctrl = false;
2573 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2574 "does not work properly. Using workaround\n");
2575 break;
2576 default:
2577 break;
2578 }
2579 }
2580
1c3d14fe 2581 return 0;
c68876fd 2582}
6aa8b732
AK		 2583
2584static struct vmcs *alloc_vmcs_cpu(int cpu)
2585{
2586 int node = cpu_to_node(cpu);
2587 struct page *pages;
2588 struct vmcs *vmcs;
2589
6484eb3e 2590 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2591 if (!pages)
2592 return NULL;
2593 vmcs = page_address(pages);
1c3d14fe
YS		 2594 memset(vmcs, 0, vmcs_config.size);
2595 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2596 return vmcs;
2597}
2598
2599static struct vmcs *alloc_vmcs(void)
2600{
d3b2c338 2601 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2602}
2603
2604static void free_vmcs(struct vmcs *vmcs)
2605{
1c3d14fe 2606 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2607}
2608
d462b819
NHE		 2609/*
2610 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2611 */
2612static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2613{
2614 if (!loaded_vmcs->vmcs)
2615 return;
2616 loaded_vmcs_clear(loaded_vmcs);
2617 free_vmcs(loaded_vmcs->vmcs);
2618 loaded_vmcs->vmcs = NULL;
2619}
2620
39959588 2621static void free_kvm_area(void)
6aa8b732
AK		 2622{
2623 int cpu;
2624
3230bb47 2625 for_each_possible_cpu(cpu) {
6aa8b732 2626 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2627 per_cpu(vmxarea, cpu) = NULL;
2628 }
6aa8b732
AK		 2629}
2630
6aa8b732
AK		 2631static __init int alloc_kvm_area(void)
2632{
2633 int cpu;
2634
3230bb47 2635 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2636 struct vmcs *vmcs;
2637
2638 vmcs = alloc_vmcs_cpu(cpu);
2639 if (!vmcs) {
2640 free_kvm_area();
2641 return -ENOMEM;
2642 }
2643
2644 per_cpu(vmxarea, cpu) = vmcs;
2645 }
2646 return 0;
2647}
2648
2649static __init int hardware_setup(void)
2650{
002c7f7c
YS		 2651 if (setup_vmcs_config(&vmcs_config) < 0)
2652 return -EIO;
50a37eb4
JR		 2653
2654 if (boot_cpu_has(X86_FEATURE_NX))
2655 kvm_enable_efer_bits(EFER_NX);
2656
93ba03c2
SY		 2657 if (!cpu_has_vmx_vpid())
2658 enable_vpid = 0;
2659
4bc9b982
SY		 2660 if (!cpu_has_vmx_ept() ||
2661 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2662 enable_ept = 0;
3a624e29 2663 enable_unrestricted_guest = 0;
83c3a331 2664 enable_ept_ad_bits = 0;
3a624e29
NK		 2665 }
2666
83c3a331
XH		 2667 if (!cpu_has_vmx_ept_ad_bits())
2668 enable_ept_ad_bits = 0;
2669
3a624e29
NK		 2670 if (!cpu_has_vmx_unrestricted_guest())
2671 enable_unrestricted_guest = 0;
93ba03c2
SY		 2672
2673 if (!cpu_has_vmx_flexpriority())
2674 flexpriority_enabled = 0;
2675
95ba8273
GN		 2676 if (!cpu_has_vmx_tpr_shadow())
2677 kvm_x86_ops->update_cr8_intercept = NULL;
2678
54dee993
MT		 2679 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2680 kvm_disable_largepages();
2681
4b8d54f9
ZE		 2682 if (!cpu_has_vmx_ple())
2683 ple_gap = 0;
2684
b87a51ae
NHE		 2685 if (nested)
2686 nested_vmx_setup_ctls_msrs();
2687
6aa8b732
AK		 2688 return alloc_kvm_area();
2689}
2690
2691static __exit void hardware_unsetup(void)
2692{
2693 free_kvm_area();
2694}
2695
6aa8b732
AK		 2696static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2697{
2698 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2699
6af11b9e 2700 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2701 vmcs_write16(sf->selector, save->selector);
2702 vmcs_writel(sf->base, save->base);
2703 vmcs_write32(sf->limit, save->limit);
2704 vmcs_write32(sf->ar_bytes, save->ar);
2705 } else {
2706 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2707 << AR_DPL_SHIFT;
2708 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2709 }
2710}
2711
2712static void enter_pmode(struct kvm_vcpu *vcpu)
2713{
2714 unsigned long flags;
a89a8fb9 2715 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2716
a89a8fb9 2717 vmx->emulation_required = 1;
7ffd92c5 2718 vmx->rmode.vm86_active = 0;
6aa8b732 2719
2fb92db1
AK		 2720 vmx_segment_cache_clear(vmx);
2721
d0ba64f9 2722 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2723 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2724 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2725 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2726
2727 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2728 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2729 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2730 vmcs_writel(GUEST_RFLAGS, flags);
2731
66aee91a
RR		 2732 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2733 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2734
2735 update_exception_bitmap(vcpu);
2736
a89a8fb9
MG		 2737 if (emulate_invalid_guest_state)
2738 return;
2739
7ffd92c5
AK		 2740 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2741 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2742 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2743 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2744
2fb92db1
AK		 2745 vmx_segment_cache_clear(vmx);
2746
6aa8b732
AK		 2747 vmcs_write16(GUEST_SS_SELECTOR, 0);
2748 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2749
2750 vmcs_write16(GUEST_CS_SELECTOR,
2751 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2752 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2753}
2754
d77c26fc 2755static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2756{
bfc6d222 2757 if (!kvm->arch.tss_addr) {
bc6678a3 2758 struct kvm_memslots *slots;
28a37544 2759 struct kvm_memory_slot *slot;
bc6678a3
MT		 2760 gfn_t base_gfn;
2761
90d83dc3 2762 slots = kvm_memslots(kvm);
28a37544
XG		 2763 slot = id_to_memslot(slots, 0);
2764 base_gfn = slot->base_gfn + slot->npages - 3;
2765
cbc94022
IE		 2766 return base_gfn << PAGE_SHIFT;
2767 }
bfc6d222 2768 return kvm->arch.tss_addr;
6aa8b732
AK		 2769}
2770
2771static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2772{
2773 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2774
2775 save->selector = vmcs_read16(sf->selector);
2776 save->base = vmcs_readl(sf->base);
2777 save->limit = vmcs_read32(sf->limit);
2778 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2779 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2780 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2781 vmcs_write32(sf->limit, 0xffff);
2782 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2783 if (save->base & 0xf)
2784 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2785 " aligned when entering protected mode (seg=%d)",
2786 seg);
6aa8b732
AK		 2787}
2788
2789static void enter_rmode(struct kvm_vcpu *vcpu)
2790{
2791 unsigned long flags;
a89a8fb9 2792 struct vcpu_vmx *vmx = to_vmx(vcpu);
b246dd5d 2793 struct kvm_segment var;
6aa8b732 2794
3a624e29
NK		 2795 if (enable_unrestricted_guest)
2796 return;
2797
a89a8fb9 2798 vmx->emulation_required = 1;
7ffd92c5 2799 vmx->rmode.vm86_active = 1;
6aa8b732 2800
776e58ea
GN		 2801 /*
2802 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2803 * vcpu. Call it here with phys address pointing 16M below 4G.
2804 */
2805 if (!vcpu->kvm->arch.tss_addr) {
2806 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2807 "called before entering vcpu\n");
2808 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2809 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2810 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2811 }
2812
2fb92db1
AK		 2813 vmx_segment_cache_clear(vmx);
2814
d0ba64f9 2815 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2816 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2817 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2818
7ffd92c5 2819 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2820 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2821
7ffd92c5 2822 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2823 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2824
2825 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2826 vmx->rmode.save_rflags = flags;
6aa8b732 2827
053de044 2828 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2829
2830 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2831 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2832 update_exception_bitmap(vcpu);
2833
a89a8fb9
MG		 2834 if (emulate_invalid_guest_state)
2835 goto continue_rmode;
2836
b246dd5d
OW		 2837 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2838 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2839
2840 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2841 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2842
2843 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2844 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2845
2846 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2847 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
6aa8b732 2848
b246dd5d
OW		 2849 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2850 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
6aa8b732 2851
b246dd5d
OW		 2852 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2853 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
75880a01 2854
a89a8fb9 2855continue_rmode:
8668a3c4 2856 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2857}
2858
401d10de
AS		 2859static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2860{
2861 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2862 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2863
2864 if (!msr)
2865 return;
401d10de 2866
44ea2b17
AK		 2867 /*
2868 * Force kernel_gs_base reloading before EFER changes, as control
2869 * of this msr depends on is_long_mode().
2870 */
2871 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2872 vcpu->arch.efer = efer;
401d10de
AS		 2873 if (efer & EFER_LMA) {
2874 vmcs_write32(VM_ENTRY_CONTROLS,
2875 vmcs_read32(VM_ENTRY_CONTROLS) |
2876 VM_ENTRY_IA32E_MODE);
2877 msr->data = efer;
2878 } else {
2879 vmcs_write32(VM_ENTRY_CONTROLS,
2880 vmcs_read32(VM_ENTRY_CONTROLS) &
2881 ~VM_ENTRY_IA32E_MODE);
2882
2883 msr->data = efer & ~EFER_LME;
2884 }
2885 setup_msrs(vmx);
2886}
2887
05b3e0c2 2888#ifdef CONFIG_X86_64
6aa8b732
AK		 2889
2890static void enter_lmode(struct kvm_vcpu *vcpu)
2891{
2892 u32 guest_tr_ar;
2893
2fb92db1
AK		 2894 vmx_segment_cache_clear(to_vmx(vcpu));
2895
6aa8b732
AK		 2896 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2897 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2898 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2899 __func__);
6aa8b732
AK		 2900 vmcs_write32(GUEST_TR_AR_BYTES,
2901 (guest_tr_ar & ~AR_TYPE_MASK)
2902 | AR_TYPE_BUSY_64_TSS);
2903 }
da38f438 2904 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2905}
2906
2907static void exit_lmode(struct kvm_vcpu *vcpu)
2908{
6aa8b732
AK		 2909 vmcs_write32(VM_ENTRY_CONTROLS,
2910 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2911 & ~VM_ENTRY_IA32E_MODE);
da38f438 2912 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2913}
2914
2915#endif
2916
2384d2b3
SY		 2917static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2918{
b9d762fa 2919 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2920 if (enable_ept) {
2921 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2922 return;
4e1096d2 2923 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2924 }
2384d2b3
SY		 2925}
2926
e8467fda
AK		 2927static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2928{
2929 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2930
2931 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2932 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2933}
2934
aff48baa
AK		 2935static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2936{
2937 if (enable_ept && is_paging(vcpu))
2938 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2939 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2940}
2941
25c4c276 2942static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2943{
fc78f519
AK		 2944 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2945
2946 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2947 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2948}
2949
1439442c
SY		 2950static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2951{
6de4f3ad
AK		 2952 if (!test_bit(VCPU_EXREG_PDPTR,
2953 (unsigned long *)&vcpu->arch.regs_dirty))
2954 return;
2955
1439442c 2956 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2957 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2958 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2959 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2960 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2961 }
2962}
2963
8f5d549f
AK		 2964static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2965{
2966 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2967 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2968 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2969 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2970 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2971 }
6de4f3ad
AK		 2972
2973 __set_bit(VCPU_EXREG_PDPTR,
2974 (unsigned long *)&vcpu->arch.regs_avail);
2975 __set_bit(VCPU_EXREG_PDPTR,
2976 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2977}
2978
5e1746d6 2979static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2980
2981static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2982 unsigned long cr0,
2983 struct kvm_vcpu *vcpu)
2984{
5233dd51
MT		 2985 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2986 vmx_decache_cr3(vcpu);
1439442c
SY		 2987 if (!(cr0 & X86_CR0_PG)) {
2988 /* From paging/starting to nonpaging */
2989 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2990 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2991 (CPU_BASED_CR3_LOAD_EXITING |
2992 CPU_BASED_CR3_STORE_EXITING));
2993 vcpu->arch.cr0 = cr0;
fc78f519 2994 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2995 } else if (!is_paging(vcpu)) {
2996 /* From nonpaging to paging */
2997 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2998 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2999 ~(CPU_BASED_CR3_LOAD_EXITING |
3000 CPU_BASED_CR3_STORE_EXITING));
3001 vcpu->arch.cr0 = cr0;
fc78f519 3002 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3003 }
95eb84a7
SY		 3004
3005 if (!(cr0 & X86_CR0_WP))
3006 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3007}
3008
6aa8b732
AK		 3009static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3010{
7ffd92c5 3011 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3012 unsigned long hw_cr0;
3013
3014 if (enable_unrestricted_guest)
3015 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3016 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3017 else
3018 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 3019
7ffd92c5 3020 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 3021 enter_pmode(vcpu);
3022
7ffd92c5 3023 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 3024 enter_rmode(vcpu);
3025
05b3e0c2 3026#ifdef CONFIG_X86_64
f6801dff 3027 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3028 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3029 enter_lmode(vcpu);
707d92fa 3030 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3031 exit_lmode(vcpu);
3032 }
3033#endif
3034
089d034e 3035 if (enable_ept)
1439442c
SY		 3036 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3037
02daab21 3038 if (!vcpu->fpu_active)
81231c69 3039 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3040
6aa8b732 3041 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3042 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3043 vcpu->arch.cr0 = cr0;
69c73028 3044 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3045}
3046
1439442c
SY		 3047static u64 construct_eptp(unsigned long root_hpa)
3048{
3049 u64 eptp;
3050
3051 /* TODO write the value reading from MSR */
3052 eptp = VMX_EPT_DEFAULT_MT |
3053 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3054 if (enable_ept_ad_bits)
3055 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3056 eptp |= (root_hpa & PAGE_MASK);
3057
3058 return eptp;
3059}
3060
6aa8b732
AK		 3061static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3062{
1439442c
SY		 3063 unsigned long guest_cr3;
3064 u64 eptp;
3065
3066 guest_cr3 = cr3;
089d034e 3067 if (enable_ept) {
1439442c
SY		 3068 eptp = construct_eptp(cr3);
3069 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3070 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3071 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3072 ept_load_pdptrs(vcpu);
1439442c
SY		 3073 }
3074
2384d2b3 3075 vmx_flush_tlb(vcpu);
1439442c 3076 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3077}
3078
5e1746d6 3079static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3080{
7ffd92c5 3081 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3082 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3083
5e1746d6
NHE		 3084 if (cr4 & X86_CR4_VMXE) {
3085 /*
3086 * To use VMXON (and later other VMX instructions), a guest
3087 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3088 * So basically the check on whether to allow nested VMX
3089 * is here.
3090 */
3091 if (!nested_vmx_allowed(vcpu))
3092 return 1;
3093 } else if (to_vmx(vcpu)->nested.vmxon)
3094 return 1;
3095
ad312c7c 3096 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3097 if (enable_ept) {
3098 if (!is_paging(vcpu)) {
3099 hw_cr4 &= ~X86_CR4_PAE;
3100 hw_cr4 |= X86_CR4_PSE;
3101 } else if (!(cr4 & X86_CR4_PAE)) {
3102 hw_cr4 &= ~X86_CR4_PAE;
3103 }
3104 }
1439442c
SY		 3105
3106 vmcs_writel(CR4_READ_SHADOW, cr4);
3107 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3108 return 0;
6aa8b732
AK		 3109}
3110
6aa8b732
AK		 3111static void vmx_get_segment(struct kvm_vcpu *vcpu,
3112 struct kvm_segment *var, int seg)
3113{
a9179499 3114 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 3115 struct kvm_save_segment *save;
6aa8b732
AK		 3116 u32 ar;
3117
a9179499
AK		 3118 if (vmx->rmode.vm86_active
3119 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3120 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3121 || seg == VCPU_SREG_GS)
3122 && !emulate_invalid_guest_state) {
3123 switch (seg) {
3124 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3125 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3126 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3127 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3128 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3129 default: BUG();
3130 }
3131 var->selector = save->selector;
3132 var->base = save->base;
3133 var->limit = save->limit;
3134 ar = save->ar;
3135 if (seg == VCPU_SREG_TR
2fb92db1 3136 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 3137 goto use_saved_rmode_seg;
3138 }
2fb92db1
AK		 3139 var->base = vmx_read_guest_seg_base(vmx, seg);
3140 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3141 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3142 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 3143use_saved_rmode_seg:
9fd4a3b7 3144 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 3145 ar = 0;
3146 var->type = ar & 15;
3147 var->s = (ar >> 4) & 1;
3148 var->dpl = (ar >> 5) & 3;
3149 var->present = (ar >> 7) & 1;
3150 var->avl = (ar >> 12) & 1;
3151 var->l = (ar >> 13) & 1;
3152 var->db = (ar >> 14) & 1;
3153 var->g = (ar >> 15) & 1;
3154 var->unusable = (ar >> 16) & 1;
3155}
3156
a9179499
AK		 3157static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3158{
a9179499
AK		 3159 struct kvm_segment s;
3160
3161 if (to_vmx(vcpu)->rmode.vm86_active) {
3162 vmx_get_segment(vcpu, &s, seg);
3163 return s.base;
3164 }
2fb92db1 3165 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3166}
3167
69c73028 3168static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3169{
3eeb3288 3170 if (!is_protmode(vcpu))
2e4d2653
IE		 3171 return 0;
3172
f4c63e5d
AK		 3173 if (!is_long_mode(vcpu)
3174 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3175 return 3;
3176
2fb92db1 3177 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3178}
3179
69c73028
AK		 3180static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3181{
d881e6f6
AK		 3182 struct vcpu_vmx *vmx = to_vmx(vcpu);
3183
3184 /*
3185 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3186 * fail; use the cache instead.
3187 */
3188 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3189 return vmx->cpl;
3190 }
3191
69c73028
AK		 3192 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3193 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
d881e6f6 3194 vmx->cpl = __vmx_get_cpl(vcpu);
69c73028 3195 }
d881e6f6
AK		 3196
3197 return vmx->cpl;
69c73028
AK		 3198}
3199
3200
653e3108 3201static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3202{
6aa8b732
AK		 3203 u32 ar;
3204
f0495f9b 3205 if (var->unusable || !var->present)
6aa8b732
AK		 3206 ar = 1 << 16;
3207 else {
3208 ar = var->type & 15;
3209 ar |= (var->s & 1) << 4;
3210 ar |= (var->dpl & 3) << 5;
3211 ar |= (var->present & 1) << 7;
3212 ar |= (var->avl & 1) << 12;
3213 ar |= (var->l & 1) << 13;
3214 ar |= (var->db & 1) << 14;
3215 ar |= (var->g & 1) << 15;
3216 }
653e3108
AK		 3217
3218 return ar;
3219}
3220
3221static void vmx_set_segment(struct kvm_vcpu *vcpu,
3222 struct kvm_segment *var, int seg)
3223{
7ffd92c5 3224 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3225 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3226 u32 ar;
3227
2fb92db1
AK		 3228 vmx_segment_cache_clear(vmx);
3229
7ffd92c5 3230 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3231 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3232 vmx->rmode.tr.selector = var->selector;
3233 vmx->rmode.tr.base = var->base;
3234 vmx->rmode.tr.limit = var->limit;
3235 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3236 return;
3237 }
3238 vmcs_writel(sf->base, var->base);
3239 vmcs_write32(sf->limit, var->limit);
3240 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3241 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3242 /*
3243 * Hack real-mode segments into vm86 compatibility.
3244 */
3245 if (var->base == 0xffff0000 && var->selector == 0xf000)
3246 vmcs_writel(sf->base, 0xf0000);
3247 ar = 0xf3;
3248 } else
3249 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3250
3251 /*
3252 * Fix the "Accessed" bit in AR field of segment registers for older
3253 * qemu binaries.
3254 * IA32 arch specifies that at the time of processor reset the
3255 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3256 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3257 * state vmexit when "unrestricted guest" mode is turned on.
3258 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3259 * tree. Newer qemu binaries with that qemu fix would not need this
3260 * kvm hack.
3261 */
3262 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3263 ar |= 0x1; /* Accessed */
3264
6aa8b732 3265 vmcs_write32(sf->ar_bytes, ar);
69c73028 3266 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b246dd5d
OW		 3267
3268 /*
3269 * Fix segments for real mode guest in hosts that don't have
3270 * "unrestricted_mode" or it was disabled.
3271 * This is done to allow migration of the guests from hosts with
3272 * unrestricted guest like Westmere to older host that don't have
3273 * unrestricted guest like Nehelem.
3274 */
3275 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3276 switch (seg) {
3277 case VCPU_SREG_CS:
3278 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3279 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3280 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3281 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3282 vmcs_write16(GUEST_CS_SELECTOR,
3283 vmcs_readl(GUEST_CS_BASE) >> 4);
3284 break;
3285 case VCPU_SREG_ES:
3286 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
3287 break;
3288 case VCPU_SREG_DS:
3289 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
3290 break;
3291 case VCPU_SREG_GS:
3292 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
3293 break;
3294 case VCPU_SREG_FS:
3295 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
3296 break;
3297 case VCPU_SREG_SS:
3298 vmcs_write16(GUEST_SS_SELECTOR,
3299 vmcs_readl(GUEST_SS_BASE) >> 4);
3300 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3301 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3302 break;
3303 }
3304 }
6aa8b732
AK		 3305}
3306
6aa8b732
AK		 3307static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3308{
2fb92db1 3309 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3310
3311 *db = (ar >> 14) & 1;
3312 *l = (ar >> 13) & 1;
3313}
3314
89a27f4d 3315static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3316{
89a27f4d
GN		 3317 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3318 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3319}
3320
89a27f4d 3321static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3322{
89a27f4d
GN		 3323 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3324 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3325}
3326
89a27f4d 3327static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3328{
89a27f4d
GN		 3329 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3330 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3331}
3332
89a27f4d 3333static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3334{
89a27f4d
GN		 3335 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3336 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3337}
3338
648dfaa7
MG		 3339static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3340{
3341 struct kvm_segment var;
3342 u32 ar;
3343
3344 vmx_get_segment(vcpu, &var, seg);
3345 ar = vmx_segment_access_rights(&var);
3346
3347 if (var.base != (var.selector << 4))
3348 return false;
3349 if (var.limit != 0xffff)
3350 return false;
3351 if (ar != 0xf3)
3352 return false;
3353
3354 return true;
3355}
3356
3357static bool code_segment_valid(struct kvm_vcpu *vcpu)
3358{
3359 struct kvm_segment cs;
3360 unsigned int cs_rpl;
3361
3362 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3363 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3364
1872a3f4
AK		 3365 if (cs.unusable)
3366 return false;
648dfaa7
MG		 3367 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3368 return false;
3369 if (!cs.s)
3370 return false;
1872a3f4 3371 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3372 if (cs.dpl > cs_rpl)
3373 return false;
1872a3f4 3374 } else {
648dfaa7
MG		 3375 if (cs.dpl != cs_rpl)
3376 return false;
3377 }
3378 if (!cs.present)
3379 return false;
3380
3381 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3382 return true;
3383}
3384
3385static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3386{
3387 struct kvm_segment ss;
3388 unsigned int ss_rpl;
3389
3390 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3391 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3392
1872a3f4
AK		 3393 if (ss.unusable)
3394 return true;
3395 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3396 return false;
3397 if (!ss.s)
3398 return false;
3399 if (ss.dpl != ss_rpl) /* DPL != RPL */
3400 return false;
3401 if (!ss.present)
3402 return false;
3403
3404 return true;
3405}
3406
3407static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3408{
3409 struct kvm_segment var;
3410 unsigned int rpl;
3411
3412 vmx_get_segment(vcpu, &var, seg);
3413 rpl = var.selector & SELECTOR_RPL_MASK;
3414
1872a3f4
AK		 3415 if (var.unusable)
3416 return true;
648dfaa7
MG		 3417 if (!var.s)
3418 return false;
3419 if (!var.present)
3420 return false;
3421 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3422 if (var.dpl < rpl) /* DPL < RPL */
3423 return false;
3424 }
3425
3426 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3427 * rights flags
3428 */
3429 return true;
3430}
3431
3432static bool tr_valid(struct kvm_vcpu *vcpu)
3433{
3434 struct kvm_segment tr;
3435
3436 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3437
1872a3f4
AK		 3438 if (tr.unusable)
3439 return false;
648dfaa7
MG		 3440 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3441 return false;
1872a3f4 3442 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3443 return false;
3444 if (!tr.present)
3445 return false;
3446
3447 return true;
3448}
3449
3450static bool ldtr_valid(struct kvm_vcpu *vcpu)
3451{
3452 struct kvm_segment ldtr;
3453
3454 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3455
1872a3f4
AK		 3456 if (ldtr.unusable)
3457 return true;
648dfaa7
MG		 3458 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3459 return false;
3460 if (ldtr.type != 2)
3461 return false;
3462 if (!ldtr.present)
3463 return false;
3464
3465 return true;
3466}
3467
3468static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3469{
3470 struct kvm_segment cs, ss;
3471
3472 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3473 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3474
3475 return ((cs.selector & SELECTOR_RPL_MASK) ==
3476 (ss.selector & SELECTOR_RPL_MASK));
3477}
3478
3479/*
3480 * Check if guest state is valid. Returns true if valid, false if
3481 * not.
3482 * We assume that registers are always usable
3483 */
3484static bool guest_state_valid(struct kvm_vcpu *vcpu)
3485{
3486 /* real mode guest state checks */
3eeb3288 3487 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3489 return false;
3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3491 return false;
3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3493 return false;
3494 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3495 return false;
3496 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3497 return false;
3498 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3499 return false;
3500 } else {
3501 /* protected mode guest state checks */
3502 if (!cs_ss_rpl_check(vcpu))
3503 return false;
3504 if (!code_segment_valid(vcpu))
3505 return false;
3506 if (!stack_segment_valid(vcpu))
3507 return false;
3508 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3509 return false;
3510 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3511 return false;
3512 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3513 return false;
3514 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3515 return false;
3516 if (!tr_valid(vcpu))
3517 return false;
3518 if (!ldtr_valid(vcpu))
3519 return false;
3520 }
3521 /* TODO:
3522 * - Add checks on RIP
3523 * - Add checks on RFLAGS
3524 */
3525
3526 return true;
3527}
3528
d77c26fc 3529static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3530{
40dcaa9f 3531 gfn_t fn;
195aefde 3532 u16 data = 0;
40dcaa9f 3533 int r, idx, ret = 0;
6aa8b732 3534
40dcaa9f
XG		 3535 idx = srcu_read_lock(&kvm->srcu);
3536 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3537 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3538 if (r < 0)
10589a46 3539 goto out;
195aefde 3540 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3541 r = kvm_write_guest_page(kvm, fn++, &data,
3542 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3543 if (r < 0)
10589a46 3544 goto out;
195aefde
IE		 3545 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3546 if (r < 0)
10589a46 3547 goto out;
195aefde
IE		 3548 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3549 if (r < 0)
10589a46 3550 goto out;
195aefde 3551 data = ~0;
10589a46
MT		 3552 r = kvm_write_guest_page(kvm, fn, &data,
3553 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3554 sizeof(u8));
195aefde 3555 if (r < 0)
10589a46
MT		 3556 goto out;
3557
3558 ret = 1;
3559out:
40dcaa9f 3560 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3561 return ret;
6aa8b732
AK		 3562}
3563
b7ebfb05
SY		 3564static int init_rmode_identity_map(struct kvm *kvm)
3565{
40dcaa9f 3566 int i, idx, r, ret;
b7ebfb05
SY		 3567 pfn_t identity_map_pfn;
3568 u32 tmp;
3569
089d034e 3570 if (!enable_ept)
b7ebfb05
SY		 3571 return 1;
3572 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3573 printk(KERN_ERR "EPT: identity-mapping pagetable "
3574 "haven't been allocated!\n");
3575 return 0;
3576 }
3577 if (likely(kvm->arch.ept_identity_pagetable_done))
3578 return 1;
3579 ret = 0;
b927a3ce 3580 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3581 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3582 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3583 if (r < 0)
3584 goto out;
3585 /* Set up identity-mapping pagetable for EPT in real mode */
3586 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3587 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3588 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3589 r = kvm_write_guest_page(kvm, identity_map_pfn,
3590 &tmp, i * sizeof(tmp), sizeof(tmp));
3591 if (r < 0)
3592 goto out;
3593 }
3594 kvm->arch.ept_identity_pagetable_done = true;
3595 ret = 1;
3596out:
40dcaa9f 3597 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3598 return ret;
3599}
3600
6aa8b732
AK		 3601static void seg_setup(int seg)
3602{
3603 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3604 unsigned int ar;
6aa8b732
AK		 3605
3606 vmcs_write16(sf->selector, 0);
3607 vmcs_writel(sf->base, 0);
3608 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3609 if (enable_unrestricted_guest) {
3610 ar = 0x93;
3611 if (seg == VCPU_SREG_CS)
3612 ar |= 0x08; /* code segment */
3613 } else
3614 ar = 0xf3;
3615
3616 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3617}
3618
f78e0e2e
SY		 3619static int alloc_apic_access_page(struct kvm *kvm)
3620{
3621 struct kvm_userspace_memory_region kvm_userspace_mem;
3622 int r = 0;
3623
79fac95e 3624 mutex_lock(&kvm->slots_lock);
bfc6d222 3625 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3626 goto out;
3627 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3628 kvm_userspace_mem.flags = 0;
3629 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3630 kvm_userspace_mem.memory_size = PAGE_SIZE;
3631 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3632 if (r)
3633 goto out;
72dc67a6 3634
bfc6d222 3635 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3636out:
79fac95e 3637 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3638 return r;
3639}
3640
b7ebfb05
SY		 3641static int alloc_identity_pagetable(struct kvm *kvm)
3642{
3643 struct kvm_userspace_memory_region kvm_userspace_mem;
3644 int r = 0;
3645
79fac95e 3646 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3647 if (kvm->arch.ept_identity_pagetable)
3648 goto out;
3649 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3650 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3651 kvm_userspace_mem.guest_phys_addr =
3652 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3653 kvm_userspace_mem.memory_size = PAGE_SIZE;
3654 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3655 if (r)
3656 goto out;
3657
b7ebfb05 3658 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3659 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3660out:
79fac95e 3661 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3662 return r;
3663}
3664
2384d2b3
SY		 3665static void allocate_vpid(struct vcpu_vmx *vmx)
3666{
3667 int vpid;
3668
3669 vmx->vpid = 0;
919818ab 3670 if (!enable_vpid)
2384d2b3
SY		 3671 return;
3672 spin_lock(&vmx_vpid_lock);
3673 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3674 if (vpid < VMX_NR_VPIDS) {
3675 vmx->vpid = vpid;
3676 __set_bit(vpid, vmx_vpid_bitmap);
3677 }
3678 spin_unlock(&vmx_vpid_lock);
3679}
3680
cdbecfc3
LJ		 3681static void free_vpid(struct vcpu_vmx *vmx)
3682{
3683 if (!enable_vpid)
3684 return;
3685 spin_lock(&vmx_vpid_lock);
3686 if (vmx->vpid != 0)
3687 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3688 spin_unlock(&vmx_vpid_lock);
3689}
3690
5897297b 3691static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3692{
3e7c73e9 3693 int f = sizeof(unsigned long);
25c5f225
SY		 3694
3695 if (!cpu_has_vmx_msr_bitmap())
3696 return;
3697
3698 /*
3699 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3700 * have the write-low and read-high bitmap offsets the wrong way round.
3701 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3702 */
25c5f225 3703 if (msr <= 0x1fff) {
3e7c73e9
AK		 3704 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3705 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3706 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3707 msr &= 0x1fff;
3e7c73e9
AK		 3708 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3709 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3710 }
25c5f225
SY		 3711}
3712
5897297b
AK		 3713static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3714{
3715 if (!longmode_only)
3716 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3717 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3718}
3719
a3a8ff8e
NHE		 3720/*
3721 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3722 * will not change in the lifetime of the guest.
3723 * Note that host-state that does change is set elsewhere. E.g., host-state
3724 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3725 */
3726static void vmx_set_constant_host_state(void)
3727{
3728 u32 low32, high32;
3729 unsigned long tmpl;
3730 struct desc_ptr dt;
3731
3732 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3733 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3734 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3735
3736 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3737#ifdef CONFIG_X86_64
3738 /*
3739 * Load null selectors, so we can avoid reloading them in
3740 * __vmx_load_host_state(), in case userspace uses the null selectors
3741 * too (the expected case).
3742 */
3743 vmcs_write16(HOST_DS_SELECTOR, 0);
3744 vmcs_write16(HOST_ES_SELECTOR, 0);
3745#else
a3a8ff8e
NHE		 3746 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3747 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3748#endif
a3a8ff8e
NHE		 3749 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3750 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3751
3752 native_store_idt(&dt);
3753 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3754
3755 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3756 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3757
3758 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3759 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3760 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3761 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3762
3763 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3764 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3765 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3766 }
3767}
3768
bf8179a0
NHE		 3769static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3770{
3771 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3772 if (enable_ept)
3773 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3774 if (is_guest_mode(&vmx->vcpu))
3775 vmx->vcpu.arch.cr4_guest_owned_bits &=
3776 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3777 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3778}
3779
3780static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3781{
3782 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3783 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3784 exec_control &= ~CPU_BASED_TPR_SHADOW;
3785#ifdef CONFIG_X86_64
3786 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3787 CPU_BASED_CR8_LOAD_EXITING;
3788#endif
3789 }
3790 if (!enable_ept)
3791 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3792 CPU_BASED_CR3_LOAD_EXITING |
3793 CPU_BASED_INVLPG_EXITING;
3794 return exec_control;
3795}
3796
3797static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3798{
3799 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3800 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3801 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3802 if (vmx->vpid == 0)
3803 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3804 if (!enable_ept) {
3805 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3806 enable_unrestricted_guest = 0;
ad756a16
MJ		 3807 /* Enable INVPCID for non-ept guests may cause performance regression. */
3808 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3809 }
3810 if (!enable_unrestricted_guest)
3811 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3812 if (!ple_gap)
3813 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3814 return exec_control;
3815}
3816
ce88decf
XG		 3817static void ept_set_mmio_spte_mask(void)
3818{
3819 /*
3820 * EPT Misconfigurations can be generated if the value of bits 2:0
3821 * of an EPT paging-structure entry is 110b (write/execute).
3822 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3823 * spte.
3824 */
3825 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3826}
3827
6aa8b732
AK		 3828/*
3829 * Sets up the vmcs for emulated real mode.
3830 */
8b9cf98c 3831static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3832{
2e4ce7f5 3833#ifdef CONFIG_X86_64
6aa8b732 3834 unsigned long a;
2e4ce7f5 3835#endif
6aa8b732 3836 int i;
6aa8b732 3837
6aa8b732 3838 /* I/O */
3e7c73e9
AK		 3839 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3840 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3841
25c5f225 3842 if (cpu_has_vmx_msr_bitmap())
5897297b 3843 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3844
6aa8b732
AK		 3845 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3846
6aa8b732 3847 /* Control */
1c3d14fe
YS		 3848 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3849 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3850
bf8179a0 3851 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3852
83ff3b9d 3853 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3854 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3855 vmx_secondary_exec_control(vmx));
83ff3b9d 3856 }
f78e0e2e 3857
4b8d54f9
ZE		 3858 if (ple_gap) {
3859 vmcs_write32(PLE_GAP, ple_gap);
3860 vmcs_write32(PLE_WINDOW, ple_window);
3861 }
3862
c3707958
XG		 3863 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3864 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3865 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3866
9581d442
AK		 3867 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3868 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3869 vmx_set_constant_host_state();
05b3e0c2 3870#ifdef CONFIG_X86_64
6aa8b732
AK		 3871 rdmsrl(MSR_FS_BASE, a);
3872 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3873 rdmsrl(MSR_GS_BASE, a);
3874 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3875#else
3876 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3877 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3878#endif
3879
2cc51560
ED		 3880 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3881 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3882 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3883 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3884 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3885
468d472f 3886 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3887 u32 msr_low, msr_high;
3888 u64 host_pat;
468d472f
SY		 3889 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3890 host_pat = msr_low | ((u64) msr_high << 32);
3891 /* Write the default value follow host pat */
3892 vmcs_write64(GUEST_IA32_PAT, host_pat);
3893 /* Keep arch.pat sync with GUEST_IA32_PAT */
3894 vmx->vcpu.arch.pat = host_pat;
3895 }
3896
6aa8b732
AK		 3897 for (i = 0; i < NR_VMX_MSR; ++i) {
3898 u32 index = vmx_msr_index[i];
3899 u32 data_low, data_high;
a2fa3e9f 3900 int j = vmx->nmsrs;
6aa8b732
AK		 3901
3902 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3903 continue;
432bd6cb
AK		 3904 if (wrmsr_safe(index, data_low, data_high) < 0)
3905 continue;
26bb0981
AK		 3906 vmx->guest_msrs[j].index = i;
3907 vmx->guest_msrs[j].data = 0;
d5696725 3908 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3909 ++vmx->nmsrs;
6aa8b732 3910 }
6aa8b732 3911
1c3d14fe 3912 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3913
3914 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3915 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3916
e00c8cf2 3917 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3918 set_cr4_guest_host_mask(vmx);
e00c8cf2 3919
99e3e30a 3920 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3921
e00c8cf2
AK		 3922 return 0;
3923}
3924
3925static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3926{
3927 struct vcpu_vmx *vmx = to_vmx(vcpu);
3928 u64 msr;
4b9d3a04 3929 int ret;
e00c8cf2 3930
5fdbf976 3931 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3932
7ffd92c5 3933 vmx->rmode.vm86_active = 0;
e00c8cf2 3934
3b86cd99
JK		 3935 vmx->soft_vnmi_blocked = 0;
3936
ad312c7c 3937 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3938 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3939 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3940 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3941 msr |= MSR_IA32_APICBASE_BSP;
3942 kvm_set_apic_base(&vmx->vcpu, msr);
3943
10ab25cd
JK		 3944 ret = fx_init(&vmx->vcpu);
3945 if (ret != 0)
3946 goto out;
e00c8cf2 3947
2fb92db1
AK		 3948 vmx_segment_cache_clear(vmx);
3949
5706be0d 3950 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3951 /*
3952 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3953 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3954 */
c5af89b6 3955 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3956 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3957 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3958 } else {
ad312c7c
ZX		 3959 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3960 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3961 }
e00c8cf2
AK		 3962
3963 seg_setup(VCPU_SREG_DS);
3964 seg_setup(VCPU_SREG_ES);
3965 seg_setup(VCPU_SREG_FS);
3966 seg_setup(VCPU_SREG_GS);
3967 seg_setup(VCPU_SREG_SS);
3968
3969 vmcs_write16(GUEST_TR_SELECTOR, 0);
3970 vmcs_writel(GUEST_TR_BASE, 0);
3971 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3972 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3973
3974 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3975 vmcs_writel(GUEST_LDTR_BASE, 0);
3976 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3977 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3978
3979 vmcs_write32(GUEST_SYSENTER_CS, 0);
3980 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3981 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3982
3983 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3984 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3985 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3986 else
5fdbf976
MT		 3987 kvm_rip_write(vcpu, 0);
3988 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3989
e00c8cf2
AK		 3990 vmcs_writel(GUEST_DR7, 0x400);
3991
3992 vmcs_writel(GUEST_GDTR_BASE, 0);
3993 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3994
3995 vmcs_writel(GUEST_IDTR_BASE, 0);
3996 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3997
443381a8 3998 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3999 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4000 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4001
e00c8cf2
AK		 4002 /* Special registers */
4003 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4004
4005 setup_msrs(vmx);
4006
6aa8b732
AK		 4007 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4008
f78e0e2e
SY		 4009 if (cpu_has_vmx_tpr_shadow()) {
4010 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4011 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4012 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4013 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4014 vmcs_write32(TPR_THRESHOLD, 0);
4015 }
4016
4017 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4018 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4019 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4020
2384d2b3
SY		 4021 if (vmx->vpid != 0)
4022 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4023
fa40052c 4024 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
7a4f5ad0 4025 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4d4ec087 4026 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
7a4f5ad0 4027 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8b9cf98c 4028 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4029 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4030 vmx_fpu_activate(&vmx->vcpu);
4031 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4032
b9d762fa 4033 vpid_sync_context(vmx);
2384d2b3 4034
3200f405 4035 ret = 0;
6aa8b732 4036
a89a8fb9
MG		 4037 /* HACK: Don't enable emulation on guest boot/reset */
4038 vmx->emulation_required = 0;
4039
6aa8b732
AK		 4040out:
4041 return ret;
4042}
4043
b6f1250e
NHE		 4044/*
4045 * In nested virtualization, check if L1 asked to exit on external interrupts.
4046 * For most existing hypervisors, this will always return true.
4047 */
4048static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4049{
4050 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4051 PIN_BASED_EXT_INTR_MASK;
4052}
4053
3b86cd99
JK		 4054static void enable_irq_window(struct kvm_vcpu *vcpu)
4055{
4056 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4057 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4058 /*
4059 * We get here if vmx_interrupt_allowed() said we can't
4060 * inject to L1 now because L2 must run. Ask L2 to exit
4061 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4062 */
d6185f20 4063 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4064 return;
d6185f20 4065 }
3b86cd99
JK		 4066
4067 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4068 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4069 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4070}
4071
4072static void enable_nmi_window(struct kvm_vcpu *vcpu)
4073{
4074 u32 cpu_based_vm_exec_control;
4075
4076 if (!cpu_has_virtual_nmis()) {
4077 enable_irq_window(vcpu);
4078 return;
4079 }
4080
30bd0c4c
AK		 4081 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4082 enable_irq_window(vcpu);
4083 return;
4084 }
3b86cd99
JK		 4085 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4086 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4087 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4088}
4089
66fd3f7f 4090static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4091{
9c8cba37 4092 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4093 uint32_t intr;
4094 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4095
229456fc 4096 trace_kvm_inj_virq(irq);
2714d1d3 4097
fa89a817 4098 ++vcpu->stat.irq_injections;
7ffd92c5 4099 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4100 int inc_eip = 0;
4101 if (vcpu->arch.interrupt.soft)
4102 inc_eip = vcpu->arch.event_exit_inst_len;
4103 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4104 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4105 return;
4106 }
66fd3f7f
GN		 4107 intr = irq | INTR_INFO_VALID_MASK;
4108 if (vcpu->arch.interrupt.soft) {
4109 intr |= INTR_TYPE_SOFT_INTR;
4110 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4111 vmx->vcpu.arch.event_exit_inst_len);
4112 } else
4113 intr |= INTR_TYPE_EXT_INTR;
4114 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4115}
4116
f08864b4
SY		 4117static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4118{
66a5a347
JK		 4119 struct vcpu_vmx *vmx = to_vmx(vcpu);
4120
0b6ac343
NHE		 4121 if (is_guest_mode(vcpu))
4122 return;
4123
3b86cd99
JK		 4124 if (!cpu_has_virtual_nmis()) {
4125 /*
4126 * Tracking the NMI-blocked state in software is built upon
4127 * finding the next open IRQ window. This, in turn, depends on
4128 * well-behaving guests: They have to keep IRQs disabled at
4129 * least as long as the NMI handler runs. Otherwise we may
4130 * cause NMI nesting, maybe breaking the guest. But as this is
4131 * highly unlikely, we can live with the residual risk.
4132 */
4133 vmx->soft_vnmi_blocked = 1;
4134 vmx->vnmi_blocked_time = 0;
4135 }
4136
487b391d 4137 ++vcpu->stat.nmi_injections;
9d58b931 4138 vmx->nmi_known_unmasked = false;
7ffd92c5 4139 if (vmx->rmode.vm86_active) {
71f9833b 4140 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4141 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4142 return;
4143 }
f08864b4
SY		 4144 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4145 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4146}
4147
c4282df9 4148static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4149{
3b86cd99 4150 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4151 return 0;
33f089ca 4152
c4282df9 4153 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4154 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4155 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4156}
4157
3cfc3092
JK		 4158static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4159{
4160 if (!cpu_has_virtual_nmis())
4161 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4162 if (to_vmx(vcpu)->nmi_known_unmasked)
4163 return false;
c332c83a 4164 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4165}
4166
4167static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4168{
4169 struct vcpu_vmx *vmx = to_vmx(vcpu);
4170
4171 if (!cpu_has_virtual_nmis()) {
4172 if (vmx->soft_vnmi_blocked != masked) {
4173 vmx->soft_vnmi_blocked = masked;
4174 vmx->vnmi_blocked_time = 0;
4175 }
4176 } else {
9d58b931 4177 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4178 if (masked)
4179 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4180 GUEST_INTR_STATE_NMI);
4181 else
4182 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4183 GUEST_INTR_STATE_NMI);
4184 }
4185}
4186
78646121
GN		 4187static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4188{
b6f1250e 4189 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
51cfe38e
NHE		 4190 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4191 if (to_vmx(vcpu)->nested.nested_run_pending ||
4192 (vmcs12->idt_vectoring_info_field &
4193 VECTORING_INFO_VALID_MASK))
b6f1250e
NHE		 4194 return 0;
4195 nested_vmx_vmexit(vcpu);
b6f1250e
NHE		 4196 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4197 vmcs12->vm_exit_intr_info = 0;
4198 /* fall through to normal code, but now in L1, not L2 */
4199 }
4200
c4282df9
GN		 4201 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4202 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4203 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4204}
4205
cbc94022
IE		 4206static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4207{
4208 int ret;
4209 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4210 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4211 .guest_phys_addr = addr,
4212 .memory_size = PAGE_SIZE * 3,
4213 .flags = 0,
4214 };
4215
4216 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4217 if (ret)
4218 return ret;
bfc6d222 4219 kvm->arch.tss_addr = addr;
93ea5388
GN		 4220 if (!init_rmode_tss(kvm))
4221 return -ENOMEM;
4222
cbc94022
IE		 4223 return 0;
4224}
4225
6aa8b732
AK		 4226static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4227 int vec, u32 err_code)
4228{
b3f37707
NK		 4229 /*
4230 * Instruction with address size override prefix opcode 0x67
4231 * Cause the #SS fault with 0 error code in VM86 mode.
4232 */
4233 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4234 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4235 return 1;
77ab6db0
JK		 4236 /*
4237 * Forward all other exceptions that are valid in real mode.
4238 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4239 * the required debugging infrastructure rework.
4240 */
4241 switch (vec) {
77ab6db0 4242 case DB_VECTOR:
d0bfb940
JK		 4243 if (vcpu->guest_debug &
4244 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4245 return 0;
4246 kvm_queue_exception(vcpu, vec);
4247 return 1;
77ab6db0 4248 case BP_VECTOR:
c573cd22
JK		 4249 /*
4250 * Update instruction length as we may reinject the exception
4251 * from user space while in guest debugging mode.
4252 */
4253 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4254 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4255 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4256 return 0;
4257 /* fall through */
4258 case DE_VECTOR:
77ab6db0
JK		 4259 case OF_VECTOR:
4260 case BR_VECTOR:
4261 case UD_VECTOR:
4262 case DF_VECTOR:
4263 case SS_VECTOR:
4264 case GP_VECTOR:
4265 case MF_VECTOR:
4266 kvm_queue_exception(vcpu, vec);
4267 return 1;
4268 }
6aa8b732
AK		 4269 return 0;
4270}
4271
a0861c02
AK		 4272/*
4273 * Trigger machine check on the host. We assume all the MSRs are already set up
4274 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4275 * We pass a fake environment to the machine check handler because we want
4276 * the guest to be always treated like user space, no matter what context
4277 * it used internally.
4278 */
4279static void kvm_machine_check(void)
4280{
4281#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4282 struct pt_regs regs = {
4283 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4284 .flags = X86_EFLAGS_IF,
4285 };
4286
4287 do_machine_check(&regs, 0);
4288#endif
4289}
4290
851ba692 4291static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4292{
4293 /* already handled by vcpu_run */
4294 return 1;
4295}
4296
851ba692 4297static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4298{
1155f76a 4299 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4300 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4301 u32 intr_info, ex_no, error_code;
42dbaa5a 4302 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4303 u32 vect_info;
4304 enum emulation_result er;
4305
1155f76a 4306 vect_info = vmx->idt_vectoring_info;
88786475 4307 intr_info = vmx->exit_intr_info;
6aa8b732 4308
a0861c02 4309 if (is_machine_check(intr_info))
851ba692 4310 return handle_machine_check(vcpu);
a0861c02 4311
6aa8b732 4312 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4313 !is_page_fault(intr_info)) {
4314 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4315 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4316 vcpu->run->internal.ndata = 2;
4317 vcpu->run->internal.data[0] = vect_info;
4318 vcpu->run->internal.data[1] = intr_info;
4319 return 0;
4320 }
6aa8b732 4321
e4a41889 4322 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4323 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4324
4325 if (is_no_device(intr_info)) {
5fd86fcf 4326 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4327 return 1;
4328 }
4329
7aa81cc0 4330 if (is_invalid_opcode(intr_info)) {
51d8b661 4331 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4332 if (er != EMULATE_DONE)
7ee5d940 4333 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4334 return 1;
4335 }
4336
6aa8b732 4337 error_code = 0;
2e11384c 4338 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4339 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4340 if (is_page_fault(intr_info)) {
1439442c 4341 /* EPT won't cause page fault directly */
cf3ace79 4342 BUG_ON(enable_ept);
6aa8b732 4343 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4344 trace_kvm_page_fault(cr2, error_code);
4345
3298b75c 4346 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4347 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4348 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4349 }
4350
7ffd92c5 4351 if (vmx->rmode.vm86_active &&
6aa8b732 4352 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4353 error_code)) {
ad312c7c
ZX		 4354 if (vcpu->arch.halt_request) {
4355 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4356 return kvm_emulate_halt(vcpu);
4357 }
6aa8b732 4358 return 1;
72d6e5a0 4359 }
6aa8b732 4360
d0bfb940 4361 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4362 switch (ex_no) {
4363 case DB_VECTOR:
4364 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4365 if (!(vcpu->guest_debug &
4366 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4367 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4368 kvm_queue_exception(vcpu, DB_VECTOR);
4369 return 1;
4370 }
4371 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4372 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4373 /* fall through */
4374 case BP_VECTOR:
c573cd22
JK		 4375 /*
4376 * Update instruction length as we may reinject #BP from
4377 * user space while in guest debugging mode. Reading it for
4378 * #DB as well causes no harm, it is not used in that case.
4379 */
4380 vmx->vcpu.arch.event_exit_inst_len =
4381 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4382 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4383 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4384 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4385 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4386 break;
4387 default:
d0bfb940
JK		 4388 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4389 kvm_run->ex.exception = ex_no;
4390 kvm_run->ex.error_code = error_code;
42dbaa5a 4391 break;
6aa8b732 4392 }
6aa8b732
AK		 4393 return 0;
4394}
4395
851ba692 4396static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4397{
1165f5fe 4398 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4399 return 1;
4400}
4401
851ba692 4402static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4403{
851ba692 4404 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4405 return 0;
4406}
6aa8b732 4407
851ba692 4408static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4409{
bfdaab09 4410 unsigned long exit_qualification;
34c33d16 4411 int size, in, string;
039576c0 4412 unsigned port;
6aa8b732 4413
bfdaab09 4414 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4415 string = (exit_qualification & 16) != 0;
cf8f70bf 4416 in = (exit_qualification & 8) != 0;
e70669ab 4417
cf8f70bf 4418 ++vcpu->stat.io_exits;
e70669ab 4419
cf8f70bf 4420 if (string || in)
51d8b661 4421 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4422
cf8f70bf
GN		 4423 port = exit_qualification >> 16;
4424 size = (exit_qualification & 7) + 1;
e93f36bc 4425 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4426
4427 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4428}
4429
102d8325
IM		 4430static void
4431vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4432{
4433 /*
4434 * Patch in the VMCALL instruction:
4435 */
4436 hypercall[0] = 0x0f;
4437 hypercall[1] = 0x01;
4438 hypercall[2] = 0xc1;
102d8325
IM		 4439}
4440
0fa06071 4441/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4442static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4443{
4444 if (to_vmx(vcpu)->nested.vmxon &&
4445 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4446 return 1;
4447
4448 if (is_guest_mode(vcpu)) {
4449 /*
4450 * We get here when L2 changed cr0 in a way that did not change
4451 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4452 * but did change L0 shadowed bits. This can currently happen
4453 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4454 * loading) while pretending to allow the guest to change it.
4455 */
4456 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4457 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4458 return 1;
4459 vmcs_writel(CR0_READ_SHADOW, val);
4460 return 0;
4461 } else
4462 return kvm_set_cr0(vcpu, val);
4463}
4464
4465static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4466{
4467 if (is_guest_mode(vcpu)) {
4468 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4469 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4470 return 1;
4471 vmcs_writel(CR4_READ_SHADOW, val);
4472 return 0;
4473 } else
4474 return kvm_set_cr4(vcpu, val);
4475}
4476
4477/* called to set cr0 as approriate for clts instruction exit. */
4478static void handle_clts(struct kvm_vcpu *vcpu)
4479{
4480 if (is_guest_mode(vcpu)) {
4481 /*
4482 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4483 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4484 * just pretend it's off (also in arch.cr0 for fpu_activate).
4485 */
4486 vmcs_writel(CR0_READ_SHADOW,
4487 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4488 vcpu->arch.cr0 &= ~X86_CR0_TS;
4489 } else
4490 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4491}
4492
851ba692 4493static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4494{
229456fc 4495 unsigned long exit_qualification, val;
6aa8b732
AK		 4496 int cr;
4497 int reg;
49a9b07e 4498 int err;
6aa8b732 4499
bfdaab09 4500 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4501 cr = exit_qualification & 15;
4502 reg = (exit_qualification >> 8) & 15;
4503 switch ((exit_qualification >> 4) & 3) {
4504 case 0: /* mov to cr */
229456fc
MT		 4505 val = kvm_register_read(vcpu, reg);
4506 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4507 switch (cr) {
4508 case 0:
eeadf9e7 4509 err = handle_set_cr0(vcpu, val);
db8fcefa 4510 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4511 return 1;
4512 case 3:
2390218b 4513 err = kvm_set_cr3(vcpu, val);
db8fcefa 4514 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4515 return 1;
4516 case 4:
eeadf9e7 4517 err = handle_set_cr4(vcpu, val);
db8fcefa 4518 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4519 return 1;
0a5fff19
GN		 4520 case 8: {
4521 u8 cr8_prev = kvm_get_cr8(vcpu);
4522 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4523 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4524 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4525 if (irqchip_in_kernel(vcpu->kvm))
4526 return 1;
4527 if (cr8_prev <= cr8)
4528 return 1;
851ba692 4529 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4530 return 0;
4531 }
6aa8b732
AK		 4532 };
4533 break;
25c4c276 4534 case 2: /* clts */
eeadf9e7 4535 handle_clts(vcpu);
4d4ec087 4536 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4537 skip_emulated_instruction(vcpu);
6b52d186 4538 vmx_fpu_activate(vcpu);
25c4c276 4539 return 1;
6aa8b732
AK		 4540 case 1: /*mov from cr*/
4541 switch (cr) {
4542 case 3:
9f8fe504
AK		 4543 val = kvm_read_cr3(vcpu);
4544 kvm_register_write(vcpu, reg, val);
4545 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4546 skip_emulated_instruction(vcpu);
4547 return 1;
4548 case 8:
229456fc
MT		 4549 val = kvm_get_cr8(vcpu);
4550 kvm_register_write(vcpu, reg, val);
4551 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4552 skip_emulated_instruction(vcpu);
4553 return 1;
4554 }
4555 break;
4556 case 3: /* lmsw */
a1f83a74 4557 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4558 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4559 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4560
4561 skip_emulated_instruction(vcpu);
4562 return 1;
4563 default:
4564 break;
4565 }
851ba692 4566 vcpu->run->exit_reason = 0;
a737f256 4567 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4568 (int)(exit_qualification >> 4) & 3, cr);
4569 return 0;
4570}
4571
851ba692 4572static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4573{
bfdaab09 4574 unsigned long exit_qualification;
6aa8b732
AK		 4575 int dr, reg;
4576
f2483415 4577 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4578 if (!kvm_require_cpl(vcpu, 0))
4579 return 1;
42dbaa5a
JK		 4580 dr = vmcs_readl(GUEST_DR7);
4581 if (dr & DR7_GD) {
4582 /*
4583 * As the vm-exit takes precedence over the debug trap, we
4584 * need to emulate the latter, either for the host or the
4585 * guest debugging itself.
4586 */
4587 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4588 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4589 vcpu->run->debug.arch.dr7 = dr;
4590 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4591 vmcs_readl(GUEST_CS_BASE) +
4592 vmcs_readl(GUEST_RIP);
851ba692
AK		 4593 vcpu->run->debug.arch.exception = DB_VECTOR;
4594 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4595 return 0;
4596 } else {
4597 vcpu->arch.dr7 &= ~DR7_GD;
4598 vcpu->arch.dr6 |= DR6_BD;
4599 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4600 kvm_queue_exception(vcpu, DB_VECTOR);
4601 return 1;
4602 }
4603 }
4604
bfdaab09 4605 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4606 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4607 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4608 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4609 unsigned long val;
4610 if (!kvm_get_dr(vcpu, dr, &val))
4611 kvm_register_write(vcpu, reg, val);
4612 } else
4613 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4614 skip_emulated_instruction(vcpu);
4615 return 1;
4616}
4617
020df079
GN		 4618static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4619{
4620 vmcs_writel(GUEST_DR7, val);
4621}
4622
851ba692 4623static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4624{
06465c5a
AK		 4625 kvm_emulate_cpuid(vcpu);
4626 return 1;
6aa8b732
AK		 4627}
4628
851ba692 4629static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4630{
ad312c7c 4631 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4632 u64 data;
4633
4634 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4635 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4636 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4637 return 1;
4638 }
4639
229456fc 4640 trace_kvm_msr_read(ecx, data);
2714d1d3 4641
6aa8b732 4642 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4643 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4644 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4645 skip_emulated_instruction(vcpu);
4646 return 1;
4647}
4648
851ba692 4649static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4650{
ad312c7c
ZX		 4651 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4652 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4653 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4654
4655 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4656 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4657 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4658 return 1;
4659 }
4660
59200273 4661 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4662 skip_emulated_instruction(vcpu);
4663 return 1;
4664}
4665
851ba692 4666static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4667{
3842d135 4668 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4669 return 1;
4670}
4671
851ba692 4672static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4673{
85f455f7
ED		 4674 u32 cpu_based_vm_exec_control;
4675
4676 /* clear pending irq */
4677 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4678 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4679 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4680
3842d135
AK		 4681 kvm_make_request(KVM_REQ_EVENT, vcpu);
4682
a26bf12a 4683 ++vcpu->stat.irq_window_exits;
2714d1d3 4684
c1150d8c
DL		 4685 /*
4686 * If the user space waits to inject interrupts, exit as soon as
4687 * possible
4688 */
8061823a 4689 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4690 vcpu->run->request_interrupt_window &&
8061823a 4691 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4692 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4693 return 0;
4694 }
6aa8b732
AK		 4695 return 1;
4696}
4697
851ba692 4698static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4699{
4700 skip_emulated_instruction(vcpu);
d3bef15f 4701 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4702}
4703
851ba692 4704static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4705{
510043da 4706 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4707 kvm_emulate_hypercall(vcpu);
4708 return 1;
c21415e8
IM		 4709}
4710
ec25d5e6
GN		 4711static int handle_invd(struct kvm_vcpu *vcpu)
4712{
51d8b661 4713 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4714}
4715
851ba692 4716static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4717{
f9c617f6 4718 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4719
4720 kvm_mmu_invlpg(vcpu, exit_qualification);
4721 skip_emulated_instruction(vcpu);
4722 return 1;
4723}
4724
fee84b07
AK		 4725static int handle_rdpmc(struct kvm_vcpu *vcpu)
4726{
4727 int err;
4728
4729 err = kvm_rdpmc(vcpu);
4730 kvm_complete_insn_gp(vcpu, err);
4731
4732 return 1;
4733}
4734
851ba692 4735static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4736{
4737 skip_emulated_instruction(vcpu);
f5f48ee1 4738 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4739 return 1;
4740}
4741
2acf923e
DC		 4742static int handle_xsetbv(struct kvm_vcpu *vcpu)
4743{
4744 u64 new_bv = kvm_read_edx_eax(vcpu);
4745 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4746
4747 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4748 skip_emulated_instruction(vcpu);
4749 return 1;
4750}
4751
851ba692 4752static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4753{
58fbbf26
KT		 4754 if (likely(fasteoi)) {
4755 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4756 int access_type, offset;
4757
4758 access_type = exit_qualification & APIC_ACCESS_TYPE;
4759 offset = exit_qualification & APIC_ACCESS_OFFSET;
4760 /*
4761 * Sane guest uses MOV to write EOI, with written value
4762 * not cared. So make a short-circuit here by avoiding
4763 * heavy instruction emulation.
4764 */
4765 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4766 (offset == APIC_EOI)) {
4767 kvm_lapic_set_eoi(vcpu);
4768 skip_emulated_instruction(vcpu);
4769 return 1;
4770 }
4771 }
51d8b661 4772 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4773}
4774
851ba692 4775static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4776{
60637aac 4777 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4778 unsigned long exit_qualification;
e269fb21
JK		 4779 bool has_error_code = false;
4780 u32 error_code = 0;
37817f29 4781 u16 tss_selector;
7f3d35fd 4782 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4783
4784 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4785 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4786 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4787
4788 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4789
4790 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4791 if (reason == TASK_SWITCH_GATE && idt_v) {
4792 switch (type) {
4793 case INTR_TYPE_NMI_INTR:
4794 vcpu->arch.nmi_injected = false;
654f06fc 4795 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4796 break;
4797 case INTR_TYPE_EXT_INTR:
66fd3f7f 4798 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4799 kvm_clear_interrupt_queue(vcpu);
4800 break;
4801 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4802 if (vmx->idt_vectoring_info &
4803 VECTORING_INFO_DELIVER_CODE_MASK) {
4804 has_error_code = true;
4805 error_code =
4806 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4807 }
4808 /* fall through */
64a7ec06
GN		 4809 case INTR_TYPE_SOFT_EXCEPTION:
4810 kvm_clear_exception_queue(vcpu);
4811 break;
4812 default:
4813 break;
4814 }
60637aac 4815 }
37817f29
IE		 4816 tss_selector = exit_qualification;
4817
64a7ec06
GN		 4818 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4819 type != INTR_TYPE_EXT_INTR &&
4820 type != INTR_TYPE_NMI_INTR))
4821 skip_emulated_instruction(vcpu);
4822
7f3d35fd
KW		 4823 if (kvm_task_switch(vcpu, tss_selector,
4824 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4825 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4826 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4827 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4828 vcpu->run->internal.ndata = 0;
42dbaa5a 4829 return 0;
acb54517 4830 }
42dbaa5a
JK		 4831
4832 /* clear all local breakpoint enable flags */
4833 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4834
4835 /*
4836 * TODO: What about debug traps on tss switch?
4837 * Are we supposed to inject them and update dr6?
4838 */
4839
4840 return 1;
37817f29
IE		 4841}
4842
851ba692 4843static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4844{
f9c617f6 4845 unsigned long exit_qualification;
1439442c 4846 gpa_t gpa;
4f5982a5 4847 u32 error_code;
1439442c 4848 int gla_validity;
1439442c 4849
f9c617f6 4850 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4851
4852 if (exit_qualification & (1 << 6)) {
4853 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4854 return -EINVAL;
1439442c
SY		 4855 }
4856
4857 gla_validity = (exit_qualification >> 7) & 0x3;
4858 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4859 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4860 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4861 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4862 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4863 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4864 (long unsigned int)exit_qualification);
851ba692
AK		 4865 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4866 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4867 return 0;
1439442c
SY		 4868 }
4869
4870 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4871 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 4872
4873 /* It is a write fault? */
4874 error_code = exit_qualification & (1U << 1);
4875 /* ept page table is present? */
4876 error_code |= (exit_qualification >> 3) & 0x1;
4877
4878 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4879}
4880
68f89400
MT		 4881static u64 ept_rsvd_mask(u64 spte, int level)
4882{
4883 int i;
4884 u64 mask = 0;
4885
4886 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4887 mask |= (1ULL << i);
4888
4889 if (level > 2)
4890 /* bits 7:3 reserved */
4891 mask |= 0xf8;
4892 else if (level == 2) {
4893 if (spte & (1ULL << 7))
4894 /* 2MB ref, bits 20:12 reserved */
4895 mask |= 0x1ff000;
4896 else
4897 /* bits 6:3 reserved */
4898 mask |= 0x78;
4899 }
4900
4901 return mask;
4902}
4903
4904static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4905 int level)
4906{
4907 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4908
4909 /* 010b (write-only) */
4910 WARN_ON((spte & 0x7) == 0x2);
4911
4912 /* 110b (write/execute) */
4913 WARN_ON((spte & 0x7) == 0x6);
4914
4915 /* 100b (execute-only) and value not supported by logical processor */
4916 if (!cpu_has_vmx_ept_execute_only())
4917 WARN_ON((spte & 0x7) == 0x4);
4918
4919 /* not 000b */
4920 if ((spte & 0x7)) {
4921 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4922
4923 if (rsvd_bits != 0) {
4924 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4925 __func__, rsvd_bits);
4926 WARN_ON(1);
4927 }
4928
4929 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4930 u64 ept_mem_type = (spte & 0x38) >> 3;
4931
4932 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4933 ept_mem_type == 7) {
4934 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4935 __func__, ept_mem_type);
4936 WARN_ON(1);
4937 }
4938 }
4939 }
4940}
4941
851ba692 4942static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4943{
4944 u64 sptes[4];
ce88decf 4945 int nr_sptes, i, ret;
68f89400
MT		 4946 gpa_t gpa;
4947
4948 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4949
ce88decf
XG		 4950 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4951 if (likely(ret == 1))
4952 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4953 EMULATE_DONE;
4954 if (unlikely(!ret))
4955 return 1;
4956
4957 /* It is the real ept misconfig */
68f89400
MT		 4958 printk(KERN_ERR "EPT: Misconfiguration.\n");
4959 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4960
4961 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4962
4963 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4964 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4965
851ba692
AK		 4966 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4967 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4968
4969 return 0;
4970}
4971
851ba692 4972static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4973{
4974 u32 cpu_based_vm_exec_control;
4975
4976 /* clear pending NMI */
4977 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4978 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4979 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4980 ++vcpu->stat.nmi_window_exits;
3842d135 4981 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4982
4983 return 1;
4984}
4985
80ced186 4986static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4987{
8b3079a5
AK		 4988 struct vcpu_vmx *vmx = to_vmx(vcpu);
4989 enum emulation_result err = EMULATE_DONE;
80ced186 4990 int ret = 1;
49e9d557
AK		 4991 u32 cpu_exec_ctrl;
4992 bool intr_window_requested;
b8405c18 4993 unsigned count = 130;
49e9d557
AK		 4994
4995 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4996 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4997
b8405c18 4998 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 4999 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5000 return handle_interrupt_window(&vmx->vcpu);
5001
de87dcdd
AK		 5002 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5003 return 1;
5004
51d8b661 5005 err = emulate_instruction(vcpu, 0);
ea953ef0 5006
80ced186
MG		 5007 if (err == EMULATE_DO_MMIO) {
5008 ret = 0;
5009 goto out;
5010 }
1d5a4d9b 5011
de5f70e0
AK		 5012 if (err != EMULATE_DONE) {
5013 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5014 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5015 vcpu->run->internal.ndata = 0;
6d77dbfc 5016 return 0;
de5f70e0 5017 }
ea953ef0
MG		 5018
5019 if (signal_pending(current))
80ced186 5020 goto out;
ea953ef0
MG		 5021 if (need_resched())
5022 schedule();
5023 }
5024
7c068e45 5025 vmx->emulation_required = !guest_state_valid(vcpu);
80ced186
MG		 5026out:
5027 return ret;
ea953ef0
MG		 5028}
5029
4b8d54f9
ZE		 5030/*
5031 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5032 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5033 */
9fb41ba8 5034static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5035{
5036 skip_emulated_instruction(vcpu);
5037 kvm_vcpu_on_spin(vcpu);
5038
5039 return 1;
5040}
5041
59708670
SY		 5042static int handle_invalid_op(struct kvm_vcpu *vcpu)
5043{
5044 kvm_queue_exception(vcpu, UD_VECTOR);
5045 return 1;
5046}
5047
ff2f6fe9
NHE		 5048/*
5049 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5050 * We could reuse a single VMCS for all the L2 guests, but we also want the
5051 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5052 * allows keeping them loaded on the processor, and in the future will allow
5053 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5054 * every entry if they never change.
5055 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5056 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5057 *
5058 * The following functions allocate and free a vmcs02 in this pool.
5059 */
5060
5061/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5062static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5063{
5064 struct vmcs02_list *item;
5065 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5066 if (item->vmptr == vmx->nested.current_vmptr) {
5067 list_move(&item->list, &vmx->nested.vmcs02_pool);
5068 return &item->vmcs02;
5069 }
5070
5071 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5072 /* Recycle the least recently used VMCS. */
5073 item = list_entry(vmx->nested.vmcs02_pool.prev,
5074 struct vmcs02_list, list);
5075 item->vmptr = vmx->nested.current_vmptr;
5076 list_move(&item->list, &vmx->nested.vmcs02_pool);
5077 return &item->vmcs02;
5078 }
5079
5080 /* Create a new VMCS */
5081 item = (struct vmcs02_list *)
5082 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5083 if (!item)
5084 return NULL;
5085 item->vmcs02.vmcs = alloc_vmcs();
5086 if (!item->vmcs02.vmcs) {
5087 kfree(item);
5088 return NULL;
5089 }
5090 loaded_vmcs_init(&item->vmcs02);
5091 item->vmptr = vmx->nested.current_vmptr;
5092 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5093 vmx->nested.vmcs02_num++;
5094 return &item->vmcs02;
5095}
5096
5097/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5098static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5099{
5100 struct vmcs02_list *item;
5101 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5102 if (item->vmptr == vmptr) {
5103 free_loaded_vmcs(&item->vmcs02);
5104 list_del(&item->list);
5105 kfree(item);
5106 vmx->nested.vmcs02_num--;
5107 return;
5108 }
5109}
5110
5111/*
5112 * Free all VMCSs saved for this vcpu, except the one pointed by
5113 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5114 * currently used, if running L2), and vmcs01 when running L2.
5115 */
5116static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5117{
5118 struct vmcs02_list *item, *n;
5119 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5120 if (vmx->loaded_vmcs != &item->vmcs02)
5121 free_loaded_vmcs(&item->vmcs02);
5122 list_del(&item->list);
5123 kfree(item);
5124 }
5125 vmx->nested.vmcs02_num = 0;
5126
5127 if (vmx->loaded_vmcs != &vmx->vmcs01)
5128 free_loaded_vmcs(&vmx->vmcs01);
5129}
5130
ec378aee
NHE		 5131/*
5132 * Emulate the VMXON instruction.
5133 * Currently, we just remember that VMX is active, and do not save or even
5134 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5135 * do not currently need to store anything in that guest-allocated memory
5136 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5137 * argument is different from the VMXON pointer (which the spec says they do).
5138 */
5139static int handle_vmon(struct kvm_vcpu *vcpu)
5140{
5141 struct kvm_segment cs;
5142 struct vcpu_vmx *vmx = to_vmx(vcpu);
5143
5144 /* The Intel VMX Instruction Reference lists a bunch of bits that
5145 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5146 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5147 * Otherwise, we should fail with #UD. We test these now:
5148 */
5149 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5150 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5151 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5152 kvm_queue_exception(vcpu, UD_VECTOR);
5153 return 1;
5154 }
5155
5156 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5157 if (is_long_mode(vcpu) && !cs.l) {
5158 kvm_queue_exception(vcpu, UD_VECTOR);
5159 return 1;
5160 }
5161
5162 if (vmx_get_cpl(vcpu)) {
5163 kvm_inject_gp(vcpu, 0);
5164 return 1;
5165 }
5166
ff2f6fe9
NHE		 5167 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5168 vmx->nested.vmcs02_num = 0;
5169
ec378aee
NHE		 5170 vmx->nested.vmxon = true;
5171
5172 skip_emulated_instruction(vcpu);
5173 return 1;
5174}
5175
5176/*
5177 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5178 * for running VMX instructions (except VMXON, whose prerequisites are
5179 * slightly different). It also specifies what exception to inject otherwise.
5180 */
5181static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5182{
5183 struct kvm_segment cs;
5184 struct vcpu_vmx *vmx = to_vmx(vcpu);
5185
5186 if (!vmx->nested.vmxon) {
5187 kvm_queue_exception(vcpu, UD_VECTOR);
5188 return 0;
5189 }
5190
5191 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5192 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5193 (is_long_mode(vcpu) && !cs.l)) {
5194 kvm_queue_exception(vcpu, UD_VECTOR);
5195 return 0;
5196 }
5197
5198 if (vmx_get_cpl(vcpu)) {
5199 kvm_inject_gp(vcpu, 0);
5200 return 0;
5201 }
5202
5203 return 1;
5204}
5205
5206/*
5207 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5208 * just stops using VMX.
5209 */
5210static void free_nested(struct vcpu_vmx *vmx)
5211{
5212 if (!vmx->nested.vmxon)
5213 return;
5214 vmx->nested.vmxon = false;
a9d30f33
NHE		 5215 if (vmx->nested.current_vmptr != -1ull) {
5216 kunmap(vmx->nested.current_vmcs12_page);
5217 nested_release_page(vmx->nested.current_vmcs12_page);
5218 vmx->nested.current_vmptr = -1ull;
5219 vmx->nested.current_vmcs12 = NULL;
5220 }
fe3ef05c
NHE		 5221 /* Unpin physical memory we referred to in current vmcs02 */
5222 if (vmx->nested.apic_access_page) {
5223 nested_release_page(vmx->nested.apic_access_page);
5224 vmx->nested.apic_access_page = 0;
5225 }
ff2f6fe9
NHE		 5226
5227 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5228}
5229
5230/* Emulate the VMXOFF instruction */
5231static int handle_vmoff(struct kvm_vcpu *vcpu)
5232{
5233 if (!nested_vmx_check_permission(vcpu))
5234 return 1;
5235 free_nested(to_vmx(vcpu));
5236 skip_emulated_instruction(vcpu);
5237 return 1;
5238}
5239
064aea77
NHE		 5240/*
5241 * Decode the memory-address operand of a vmx instruction, as recorded on an
5242 * exit caused by such an instruction (run by a guest hypervisor).
5243 * On success, returns 0. When the operand is invalid, returns 1 and throws
5244 * #UD or #GP.
5245 */
5246static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5247 unsigned long exit_qualification,
5248 u32 vmx_instruction_info, gva_t *ret)
5249{
5250 /*
5251 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5252 * Execution", on an exit, vmx_instruction_info holds most of the
5253 * addressing components of the operand. Only the displacement part
5254 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5255 * For how an actual address is calculated from all these components,
5256 * refer to Vol. 1, "Operand Addressing".
5257 */
5258 int scaling = vmx_instruction_info & 3;
5259 int addr_size = (vmx_instruction_info >> 7) & 7;
5260 bool is_reg = vmx_instruction_info & (1u << 10);
5261 int seg_reg = (vmx_instruction_info >> 15) & 7;
5262 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5263 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5264 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5265 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5266
5267 if (is_reg) {
5268 kvm_queue_exception(vcpu, UD_VECTOR);
5269 return 1;
5270 }
5271
5272 /* Addr = segment_base + offset */
5273 /* offset = base + [index * scale] + displacement */
5274 *ret = vmx_get_segment_base(vcpu, seg_reg);
5275 if (base_is_valid)
5276 *ret += kvm_register_read(vcpu, base_reg);
5277 if (index_is_valid)
5278 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5279 *ret += exit_qualification; /* holds the displacement */
5280
5281 if (addr_size == 1) /* 32 bit */
5282 *ret &= 0xffffffff;
5283
5284 /*
5285 * TODO: throw #GP (and return 1) in various cases that the VM*
5286 * instructions require it - e.g., offset beyond segment limit,
5287 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5288 * address, and so on. Currently these are not checked.
5289 */
5290 return 0;
5291}
5292
0140caea
NHE		 5293/*
5294 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5295 * set the success or error code of an emulated VMX instruction, as specified
5296 * by Vol 2B, VMX Instruction Reference, "Conventions".
5297 */
5298static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5299{
5300 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5301 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5302 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5303}
5304
5305static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5306{
5307 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5308 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5309 X86_EFLAGS_SF | X86_EFLAGS_OF))
5310 | X86_EFLAGS_CF);
5311}
5312
5313static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5314 u32 vm_instruction_error)
5315{
5316 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5317 /*
5318 * failValid writes the error number to the current VMCS, which
5319 * can't be done there isn't a current VMCS.
5320 */
5321 nested_vmx_failInvalid(vcpu);
5322 return;
5323 }
5324 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5325 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5326 X86_EFLAGS_SF | X86_EFLAGS_OF))
5327 | X86_EFLAGS_ZF);
5328 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5329}
5330
27d6c865
NHE		 5331/* Emulate the VMCLEAR instruction */
5332static int handle_vmclear(struct kvm_vcpu *vcpu)
5333{
5334 struct vcpu_vmx *vmx = to_vmx(vcpu);
5335 gva_t gva;
5336 gpa_t vmptr;
5337 struct vmcs12 *vmcs12;
5338 struct page *page;
5339 struct x86_exception e;
5340
5341 if (!nested_vmx_check_permission(vcpu))
5342 return 1;
5343
5344 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5345 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5346 return 1;
5347
5348 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5349 sizeof(vmptr), &e)) {
5350 kvm_inject_page_fault(vcpu, &e);
5351 return 1;
5352 }
5353
5354 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5355 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5356 skip_emulated_instruction(vcpu);
5357 return 1;
5358 }
5359
5360 if (vmptr == vmx->nested.current_vmptr) {
5361 kunmap(vmx->nested.current_vmcs12_page);
5362 nested_release_page(vmx->nested.current_vmcs12_page);
5363 vmx->nested.current_vmptr = -1ull;
5364 vmx->nested.current_vmcs12 = NULL;
5365 }
5366
5367 page = nested_get_page(vcpu, vmptr);
5368 if (page == NULL) {
5369 /*
5370 * For accurate processor emulation, VMCLEAR beyond available
5371 * physical memory should do nothing at all. However, it is
5372 * possible that a nested vmx bug, not a guest hypervisor bug,
5373 * resulted in this case, so let's shut down before doing any
5374 * more damage:
5375 */
5376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5377 return 1;
5378 }
5379 vmcs12 = kmap(page);
5380 vmcs12->launch_state = 0;
5381 kunmap(page);
5382 nested_release_page(page);
5383
5384 nested_free_vmcs02(vmx, vmptr);
5385
5386 skip_emulated_instruction(vcpu);
5387 nested_vmx_succeed(vcpu);
5388 return 1;
5389}
5390
cd232ad0
NHE		 5391static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5392
5393/* Emulate the VMLAUNCH instruction */
5394static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5395{
5396 return nested_vmx_run(vcpu, true);
5397}
5398
5399/* Emulate the VMRESUME instruction */
5400static int handle_vmresume(struct kvm_vcpu *vcpu)
5401{
5402
5403 return nested_vmx_run(vcpu, false);
5404}
5405
49f705c5
NHE		 5406enum vmcs_field_type {
5407 VMCS_FIELD_TYPE_U16 = 0,
5408 VMCS_FIELD_TYPE_U64 = 1,
5409 VMCS_FIELD_TYPE_U32 = 2,
5410 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5411};
5412
5413static inline int vmcs_field_type(unsigned long field)
5414{
5415 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5416 return VMCS_FIELD_TYPE_U32;
5417 return (field >> 13) & 0x3 ;
5418}
5419
5420static inline int vmcs_field_readonly(unsigned long field)
5421{
5422 return (((field >> 10) & 0x3) == 1);
5423}
5424
5425/*
5426 * Read a vmcs12 field. Since these can have varying lengths and we return
5427 * one type, we chose the biggest type (u64) and zero-extend the return value
5428 * to that size. Note that the caller, handle_vmread, might need to use only
5429 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5430 * 64-bit fields are to be returned).
5431 */
5432static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5433 unsigned long field, u64 *ret)
5434{
5435 short offset = vmcs_field_to_offset(field);
5436 char *p;
5437
5438 if (offset < 0)
5439 return 0;
5440
5441 p = ((char *)(get_vmcs12(vcpu))) + offset;
5442
5443 switch (vmcs_field_type(field)) {
5444 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5445 *ret = *((natural_width *)p);
5446 return 1;
5447 case VMCS_FIELD_TYPE_U16:
5448 *ret = *((u16 *)p);
5449 return 1;
5450 case VMCS_FIELD_TYPE_U32:
5451 *ret = *((u32 *)p);
5452 return 1;
5453 case VMCS_FIELD_TYPE_U64:
5454 *ret = *((u64 *)p);
5455 return 1;
5456 default:
5457 return 0; /* can never happen. */
5458 }
5459}
5460
5461/*
5462 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5463 * used before) all generate the same failure when it is missing.
5464 */
5465static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5466{
5467 struct vcpu_vmx *vmx = to_vmx(vcpu);
5468 if (vmx->nested.current_vmptr == -1ull) {
5469 nested_vmx_failInvalid(vcpu);
5470 skip_emulated_instruction(vcpu);
5471 return 0;
5472 }
5473 return 1;
5474}
5475
5476static int handle_vmread(struct kvm_vcpu *vcpu)
5477{
5478 unsigned long field;
5479 u64 field_value;
5480 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5481 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5482 gva_t gva = 0;
5483
5484 if (!nested_vmx_check_permission(vcpu) ||
5485 !nested_vmx_check_vmcs12(vcpu))
5486 return 1;
5487
5488 /* Decode instruction info and find the field to read */
5489 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5490 /* Read the field, zero-extended to a u64 field_value */
5491 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5492 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5493 skip_emulated_instruction(vcpu);
5494 return 1;
5495 }
5496 /*
5497 * Now copy part of this value to register or memory, as requested.
5498 * Note that the number of bits actually copied is 32 or 64 depending
5499 * on the guest's mode (32 or 64 bit), not on the given field's length.
5500 */
5501 if (vmx_instruction_info & (1u << 10)) {
5502 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5503 field_value);
5504 } else {
5505 if (get_vmx_mem_address(vcpu, exit_qualification,
5506 vmx_instruction_info, &gva))
5507 return 1;
5508 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5509 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5510 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5511 }
5512
5513 nested_vmx_succeed(vcpu);
5514 skip_emulated_instruction(vcpu);
5515 return 1;
5516}
5517
5518
5519static int handle_vmwrite(struct kvm_vcpu *vcpu)
5520{
5521 unsigned long field;
5522 gva_t gva;
5523 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525 char *p;
5526 short offset;
5527 /* The value to write might be 32 or 64 bits, depending on L1's long
5528 * mode, and eventually we need to write that into a field of several
5529 * possible lengths. The code below first zero-extends the value to 64
5530 * bit (field_value), and then copies only the approriate number of
5531 * bits into the vmcs12 field.
5532 */
5533 u64 field_value = 0;
5534 struct x86_exception e;
5535
5536 if (!nested_vmx_check_permission(vcpu) ||
5537 !nested_vmx_check_vmcs12(vcpu))
5538 return 1;
5539
5540 if (vmx_instruction_info & (1u << 10))
5541 field_value = kvm_register_read(vcpu,
5542 (((vmx_instruction_info) >> 3) & 0xf));
5543 else {
5544 if (get_vmx_mem_address(vcpu, exit_qualification,
5545 vmx_instruction_info, &gva))
5546 return 1;
5547 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5548 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5549 kvm_inject_page_fault(vcpu, &e);
5550 return 1;
5551 }
5552 }
5553
5554
5555 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5556 if (vmcs_field_readonly(field)) {
5557 nested_vmx_failValid(vcpu,
5558 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5559 skip_emulated_instruction(vcpu);
5560 return 1;
5561 }
5562
5563 offset = vmcs_field_to_offset(field);
5564 if (offset < 0) {
5565 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5566 skip_emulated_instruction(vcpu);
5567 return 1;
5568 }
5569 p = ((char *) get_vmcs12(vcpu)) + offset;
5570
5571 switch (vmcs_field_type(field)) {
5572 case VMCS_FIELD_TYPE_U16:
5573 *(u16 *)p = field_value;
5574 break;
5575 case VMCS_FIELD_TYPE_U32:
5576 *(u32 *)p = field_value;
5577 break;
5578 case VMCS_FIELD_TYPE_U64:
5579 *(u64 *)p = field_value;
5580 break;
5581 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5582 *(natural_width *)p = field_value;
5583 break;
5584 default:
5585 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5586 skip_emulated_instruction(vcpu);
5587 return 1;
5588 }
5589
5590 nested_vmx_succeed(vcpu);
5591 skip_emulated_instruction(vcpu);
5592 return 1;
5593}
5594
63846663
NHE		 5595/* Emulate the VMPTRLD instruction */
5596static int handle_vmptrld(struct kvm_vcpu *vcpu)
5597{
5598 struct vcpu_vmx *vmx = to_vmx(vcpu);
5599 gva_t gva;
5600 gpa_t vmptr;
5601 struct x86_exception e;
5602
5603 if (!nested_vmx_check_permission(vcpu))
5604 return 1;
5605
5606 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5607 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5608 return 1;
5609
5610 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5611 sizeof(vmptr), &e)) {
5612 kvm_inject_page_fault(vcpu, &e);
5613 return 1;
5614 }
5615
5616 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5617 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5618 skip_emulated_instruction(vcpu);
5619 return 1;
5620 }
5621
5622 if (vmx->nested.current_vmptr != vmptr) {
5623 struct vmcs12 *new_vmcs12;
5624 struct page *page;
5625 page = nested_get_page(vcpu, vmptr);
5626 if (page == NULL) {
5627 nested_vmx_failInvalid(vcpu);
5628 skip_emulated_instruction(vcpu);
5629 return 1;
5630 }
5631 new_vmcs12 = kmap(page);
5632 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5633 kunmap(page);
5634 nested_release_page_clean(page);
5635 nested_vmx_failValid(vcpu,
5636 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639 }
5640 if (vmx->nested.current_vmptr != -1ull) {
5641 kunmap(vmx->nested.current_vmcs12_page);
5642 nested_release_page(vmx->nested.current_vmcs12_page);
5643 }
5644
5645 vmx->nested.current_vmptr = vmptr;
5646 vmx->nested.current_vmcs12 = new_vmcs12;
5647 vmx->nested.current_vmcs12_page = page;
5648 }
5649
5650 nested_vmx_succeed(vcpu);
5651 skip_emulated_instruction(vcpu);
5652 return 1;
5653}
5654
6a4d7550
NHE		 5655/* Emulate the VMPTRST instruction */
5656static int handle_vmptrst(struct kvm_vcpu *vcpu)
5657{
5658 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5659 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5660 gva_t vmcs_gva;
5661 struct x86_exception e;
5662
5663 if (!nested_vmx_check_permission(vcpu))
5664 return 1;
5665
5666 if (get_vmx_mem_address(vcpu, exit_qualification,
5667 vmx_instruction_info, &vmcs_gva))
5668 return 1;
5669 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5670 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5671 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5672 sizeof(u64), &e)) {
5673 kvm_inject_page_fault(vcpu, &e);
5674 return 1;
5675 }
5676 nested_vmx_succeed(vcpu);
5677 skip_emulated_instruction(vcpu);
5678 return 1;
5679}
5680
6aa8b732
AK		 5681/*
5682 * The exit handlers return 1 if the exit was handled fully and guest execution
5683 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5684 * to be done to userspace and return 0.
5685 */
851ba692 5686static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5687 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5688 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5689 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5690 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5691 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5692 [EXIT_REASON_CR_ACCESS] = handle_cr,
5693 [EXIT_REASON_DR_ACCESS] = handle_dr,
5694 [EXIT_REASON_CPUID] = handle_cpuid,
5695 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5696 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5697 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5698 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5699 [EXIT_REASON_INVD] = handle_invd,
a7052897 5700 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5701 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5702 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5703 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5704 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5705 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5706 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5707 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5708 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5709 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5710 [EXIT_REASON_VMOFF] = handle_vmoff,
5711 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5712 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5713 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5714 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5715 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5716 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5717 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5718 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5719 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5720 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5721 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5722 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5723};
5724
5725static const int kvm_vmx_max_exit_handlers =
50a3485c 5726 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5727
644d711a
NHE		 5728/*
5729 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5730 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5731 * disinterest in the current event (read or write a specific MSR) by using an
5732 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5733 */
5734static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5735 struct vmcs12 *vmcs12, u32 exit_reason)
5736{
5737 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5738 gpa_t bitmap;
5739
5740 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5741 return 1;
5742
5743 /*
5744 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5745 * for the four combinations of read/write and low/high MSR numbers.
5746 * First we need to figure out which of the four to use:
5747 */
5748 bitmap = vmcs12->msr_bitmap;
5749 if (exit_reason == EXIT_REASON_MSR_WRITE)
5750 bitmap += 2048;
5751 if (msr_index >= 0xc0000000) {
5752 msr_index -= 0xc0000000;
5753 bitmap += 1024;
5754 }
5755
5756 /* Then read the msr_index'th bit from this bitmap: */
5757 if (msr_index < 1024*8) {
5758 unsigned char b;
5759 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5760 return 1 & (b >> (msr_index & 7));
5761 } else
5762 return 1; /* let L1 handle the wrong parameter */
5763}
5764
5765/*
5766 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5767 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5768 * intercept (via guest_host_mask etc.) the current event.
5769 */
5770static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5771 struct vmcs12 *vmcs12)
5772{
5773 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774 int cr = exit_qualification & 15;
5775 int reg = (exit_qualification >> 8) & 15;
5776 unsigned long val = kvm_register_read(vcpu, reg);
5777
5778 switch ((exit_qualification >> 4) & 3) {
5779 case 0: /* mov to cr */
5780 switch (cr) {
5781 case 0:
5782 if (vmcs12->cr0_guest_host_mask &
5783 (val ^ vmcs12->cr0_read_shadow))
5784 return 1;
5785 break;
5786 case 3:
5787 if ((vmcs12->cr3_target_count >= 1 &&
5788 vmcs12->cr3_target_value0 == val) ||
5789 (vmcs12->cr3_target_count >= 2 &&
5790 vmcs12->cr3_target_value1 == val) ||
5791 (vmcs12->cr3_target_count >= 3 &&
5792 vmcs12->cr3_target_value2 == val) ||
5793 (vmcs12->cr3_target_count >= 4 &&
5794 vmcs12->cr3_target_value3 == val))
5795 return 0;
5796 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5797 return 1;
5798 break;
5799 case 4:
5800 if (vmcs12->cr4_guest_host_mask &
5801 (vmcs12->cr4_read_shadow ^ val))
5802 return 1;
5803 break;
5804 case 8:
5805 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5806 return 1;
5807 break;
5808 }
5809 break;
5810 case 2: /* clts */
5811 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5812 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5813 return 1;
5814 break;
5815 case 1: /* mov from cr */
5816 switch (cr) {
5817 case 3:
5818 if (vmcs12->cpu_based_vm_exec_control &
5819 CPU_BASED_CR3_STORE_EXITING)
5820 return 1;
5821 break;
5822 case 8:
5823 if (vmcs12->cpu_based_vm_exec_control &
5824 CPU_BASED_CR8_STORE_EXITING)
5825 return 1;
5826 break;
5827 }
5828 break;
5829 case 3: /* lmsw */
5830 /*
5831 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5832 * cr0. Other attempted changes are ignored, with no exit.
5833 */
5834 if (vmcs12->cr0_guest_host_mask & 0xe &
5835 (val ^ vmcs12->cr0_read_shadow))
5836 return 1;
5837 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5838 !(vmcs12->cr0_read_shadow & 0x1) &&
5839 (val & 0x1))
5840 return 1;
5841 break;
5842 }
5843 return 0;
5844}
5845
5846/*
5847 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5848 * should handle it ourselves in L0 (and then continue L2). Only call this
5849 * when in is_guest_mode (L2).
5850 */
5851static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5852{
5853 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5854 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5855 struct vcpu_vmx *vmx = to_vmx(vcpu);
5856 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5857
5858 if (vmx->nested.nested_run_pending)
5859 return 0;
5860
5861 if (unlikely(vmx->fail)) {
bd80158a
JK		 5862 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5863 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 5864 return 1;
5865 }
5866
5867 switch (exit_reason) {
5868 case EXIT_REASON_EXCEPTION_NMI:
5869 if (!is_exception(intr_info))
5870 return 0;
5871 else if (is_page_fault(intr_info))
5872 return enable_ept;
5873 return vmcs12->exception_bitmap &
5874 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5875 case EXIT_REASON_EXTERNAL_INTERRUPT:
5876 return 0;
5877 case EXIT_REASON_TRIPLE_FAULT:
5878 return 1;
5879 case EXIT_REASON_PENDING_INTERRUPT:
5880 case EXIT_REASON_NMI_WINDOW:
5881 /*
5882 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5883 * (aka Interrupt Window Exiting) only when L1 turned it on,
5884 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5885 * Same for NMI Window Exiting.
5886 */
5887 return 1;
5888 case EXIT_REASON_TASK_SWITCH:
5889 return 1;
5890 case EXIT_REASON_CPUID:
5891 return 1;
5892 case EXIT_REASON_HLT:
5893 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5894 case EXIT_REASON_INVD:
5895 return 1;
5896 case EXIT_REASON_INVLPG:
5897 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5898 case EXIT_REASON_RDPMC:
5899 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5900 case EXIT_REASON_RDTSC:
5901 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5902 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5903 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5904 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5905 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5906 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5907 /*
5908 * VMX instructions trap unconditionally. This allows L1 to
5909 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5910 */
5911 return 1;
5912 case EXIT_REASON_CR_ACCESS:
5913 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5914 case EXIT_REASON_DR_ACCESS:
5915 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5916 case EXIT_REASON_IO_INSTRUCTION:
5917 /* TODO: support IO bitmaps */
5918 return 1;
5919 case EXIT_REASON_MSR_READ:
5920 case EXIT_REASON_MSR_WRITE:
5921 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5922 case EXIT_REASON_INVALID_STATE:
5923 return 1;
5924 case EXIT_REASON_MWAIT_INSTRUCTION:
5925 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5926 case EXIT_REASON_MONITOR_INSTRUCTION:
5927 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5928 case EXIT_REASON_PAUSE_INSTRUCTION:
5929 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5930 nested_cpu_has2(vmcs12,
5931 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5932 case EXIT_REASON_MCE_DURING_VMENTRY:
5933 return 0;
5934 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5935 return 1;
5936 case EXIT_REASON_APIC_ACCESS:
5937 return nested_cpu_has2(vmcs12,
5938 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5939 case EXIT_REASON_EPT_VIOLATION:
5940 case EXIT_REASON_EPT_MISCONFIG:
5941 return 0;
5942 case EXIT_REASON_WBINVD:
5943 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5944 case EXIT_REASON_XSETBV:
5945 return 1;
5946 default:
5947 return 1;
5948 }
5949}
5950
586f9607
AK		 5951static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5952{
5953 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5954 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5955}
5956
6aa8b732
AK		 5957/*
5958 * The guest has exited. See if we can fix it or if we need userspace
5959 * assistance.
5960 */
851ba692 5961static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5962{
29bd8a78 5963 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5964 u32 exit_reason = vmx->exit_reason;
1155f76a 5965 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5966
80ced186
MG		 5967 /* If guest state is invalid, start emulating */
5968 if (vmx->emulation_required && emulate_invalid_guest_state)
5969 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5970
b6f1250e
NHE		 5971 /*
5972 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5973 * we did not inject a still-pending event to L1 now because of
5974 * nested_run_pending, we need to re-enable this bit.
5975 */
5976 if (vmx->nested.nested_run_pending)
5977 kvm_make_request(KVM_REQ_EVENT, vcpu);
5978
509c75ea
NHE		 5979 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5980 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5981 vmx->nested.nested_run_pending = 1;
5982 else
5983 vmx->nested.nested_run_pending = 0;
5984
5985 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5986 nested_vmx_vmexit(vcpu);
5987 return 1;
5988 }
5989
5120702e
MG		 5990 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5991 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5992 vcpu->run->fail_entry.hardware_entry_failure_reason
5993 = exit_reason;
5994 return 0;
5995 }
5996
29bd8a78 5997 if (unlikely(vmx->fail)) {
851ba692
AK		 5998 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5999 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6000 = vmcs_read32(VM_INSTRUCTION_ERROR);
6001 return 0;
6002 }
6aa8b732 6003
d77c26fc 6004 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6005 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 6006 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6007 exit_reason != EXIT_REASON_TASK_SWITCH))
6008 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
6009 "(0x%x) and exit reason is 0x%x\n",
6010 __func__, vectoring_info, exit_reason);
3b86cd99 6011
644d711a
NHE		 6012 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6013 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6014 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6015 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6016 vmx->soft_vnmi_blocked = 0;
3b86cd99 6017 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6018 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6019 /*
6020 * This CPU don't support us in finding the end of an
6021 * NMI-blocked window if the guest runs with IRQs
6022 * disabled. So we pull the trigger after 1 s of
6023 * futile waiting, but inform the user about this.
6024 */
6025 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6026 "state on VCPU %d after 1 s timeout\n",
6027 __func__, vcpu->vcpu_id);
6028 vmx->soft_vnmi_blocked = 0;
3b86cd99 6029 }
3b86cd99
JK		 6030 }
6031
6aa8b732
AK		 6032 if (exit_reason < kvm_vmx_max_exit_handlers
6033 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6034 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6035 else {
851ba692
AK		 6036 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6037 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6038 }
6039 return 0;
6040}
6041
95ba8273 6042static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6043{
95ba8273 6044 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6045 vmcs_write32(TPR_THRESHOLD, 0);
6046 return;
6047 }
6048
95ba8273 6049 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6050}
6051
51aa01d1 6052static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6053{
00eba012
AK		 6054 u32 exit_intr_info;
6055
6056 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6057 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6058 return;
6059
c5ca8e57 6060 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6061 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6062
6063 /* Handle machine checks before interrupts are enabled */
00eba012 6064 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6065 kvm_machine_check();
6066
20f65983 6067 /* We need to handle NMIs before interrupts are enabled */
00eba012 6068 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6069 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6070 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6071 asm("int $2");
ff9d07a0
ZY		 6072 kvm_after_handle_nmi(&vmx->vcpu);
6073 }
51aa01d1 6074}
20f65983 6075
51aa01d1
AK		 6076static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6077{
c5ca8e57 6078 u32 exit_intr_info;
51aa01d1
AK		 6079 bool unblock_nmi;
6080 u8 vector;
6081 bool idtv_info_valid;
6082
6083 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6084
cf393f75 6085 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6086 if (vmx->nmi_known_unmasked)
6087 return;
c5ca8e57
AK		 6088 /*
6089 * Can't use vmx->exit_intr_info since we're not sure what
6090 * the exit reason is.
6091 */
6092 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6093 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6094 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6095 /*
7b4a25cb 6096 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6097 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6098 * a guest IRET fault.
7b4a25cb
GN		 6099 * SDM 3: 23.2.2 (September 2008)
6100 * Bit 12 is undefined in any of the following cases:
6101 * If the VM exit sets the valid bit in the IDT-vectoring
6102 * information field.
6103 * If the VM exit is due to a double fault.
cf393f75 6104 */
7b4a25cb
GN		 6105 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6106 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6107 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6108 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6109 else
6110 vmx->nmi_known_unmasked =
6111 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6112 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6113 } else if (unlikely(vmx->soft_vnmi_blocked))
6114 vmx->vnmi_blocked_time +=
6115 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6116}
6117
83422e17
AK		 6118static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6119 u32 idt_vectoring_info,
6120 int instr_len_field,
6121 int error_code_field)
51aa01d1 6122{
51aa01d1
AK		 6123 u8 vector;
6124 int type;
6125 bool idtv_info_valid;
6126
6127 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6128
37b96e98
GN		 6129 vmx->vcpu.arch.nmi_injected = false;
6130 kvm_clear_exception_queue(&vmx->vcpu);
6131 kvm_clear_interrupt_queue(&vmx->vcpu);
6132
6133 if (!idtv_info_valid)
6134 return;
6135
3842d135
AK		 6136 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6137
668f612f
AK		 6138 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6139 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6140
64a7ec06 6141 switch (type) {
37b96e98
GN		 6142 case INTR_TYPE_NMI_INTR:
6143 vmx->vcpu.arch.nmi_injected = true;
668f612f 6144 /*
7b4a25cb 6145 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6146 * Clear bit "block by NMI" before VM entry if a NMI
6147 * delivery faulted.
668f612f 6148 */
654f06fc 6149 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 6150 break;
37b96e98 6151 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 6152 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6153 vmcs_read32(instr_len_field);
66fd3f7f
GN		 6154 /* fall through */
6155 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6156 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6157 u32 err = vmcs_read32(error_code_field);
37b96e98 6158 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 6159 } else
6160 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 6161 break;
66fd3f7f
GN		 6162 case INTR_TYPE_SOFT_INTR:
6163 vmx->vcpu.arch.event_exit_inst_len =
83422e17 6164 vmcs_read32(instr_len_field);
66fd3f7f 6165 /* fall through */
37b96e98 6166 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 6167 kvm_queue_interrupt(&vmx->vcpu, vector,
6168 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6169 break;
6170 default:
6171 break;
f7d9238f 6172 }
cf393f75
AK		 6173}
6174
83422e17
AK		 6175static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6176{
66c78ae4
NHE		 6177 if (is_guest_mode(&vmx->vcpu))
6178 return;
83422e17
AK		 6179 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6180 VM_EXIT_INSTRUCTION_LEN,
6181 IDT_VECTORING_ERROR_CODE);
6182}
6183
b463a6f7
AK		 6184static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6185{
66c78ae4
NHE		 6186 if (is_guest_mode(vcpu))
6187 return;
b463a6f7
AK		 6188 __vmx_complete_interrupts(to_vmx(vcpu),
6189 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6190 VM_ENTRY_INSTRUCTION_LEN,
6191 VM_ENTRY_EXCEPTION_ERROR_CODE);
6192
6193 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6194}
6195
d7cd9796
GN		 6196static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6197{
6198 int i, nr_msrs;
6199 struct perf_guest_switch_msr *msrs;
6200
6201 msrs = perf_guest_get_msrs(&nr_msrs);
6202
6203 if (!msrs)
6204 return;
6205
6206 for (i = 0; i < nr_msrs; i++)
6207 if (msrs[i].host == msrs[i].guest)
6208 clear_atomic_switch_msr(vmx, msrs[i].msr);
6209 else
6210 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6211 msrs[i].host);
6212}
6213
c801949d
AK		 6214#ifdef CONFIG_X86_64
6215#define R "r"
6216#define Q "q"
6217#else
6218#define R "e"
6219#define Q "l"
6220#endif
6221
a3b5ba49 6222static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6223{
a2fa3e9f 6224 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 6225
66c78ae4
NHE		 6226 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6227 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6228 if (vmcs12->idt_vectoring_info_field &
6229 VECTORING_INFO_VALID_MASK) {
6230 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6231 vmcs12->idt_vectoring_info_field);
6232 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6233 vmcs12->vm_exit_instruction_len);
6234 if (vmcs12->idt_vectoring_info_field &
6235 VECTORING_INFO_DELIVER_CODE_MASK)
6236 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6237 vmcs12->idt_vectoring_error_code);
6238 }
6239 }
6240
104f226b
AK		 6241 /* Record the guest's net vcpu time for enforced NMI injections. */
6242 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6243 vmx->entry_time = ktime_get();
6244
6245 /* Don't enter VMX if guest state is invalid, let the exit handler
6246 start emulation until we arrive back to a valid state */
6247 if (vmx->emulation_required && emulate_invalid_guest_state)
6248 return;
6249
6250 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6251 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6252 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6253 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6254
6255 /* When single-stepping over STI and MOV SS, we must clear the
6256 * corresponding interruptibility bits in the guest state. Otherwise
6257 * vmentry fails as it then expects bit 14 (BS) in pending debug
6258 * exceptions being set, but that's not correct for the guest debugging
6259 * case. */
6260 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6261 vmx_set_interrupt_shadow(vcpu, 0);
6262
d7cd9796
GN		 6263 atomic_switch_perf_msrs(vmx);
6264
d462b819 6265 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6266 asm(
6aa8b732 6267 /* Store host registers */
c801949d 6268 "push %%"R"dx; push %%"R"bp;"
40712fae 6269 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 6270 "push %%"R"cx \n\t"
313dbd49
AK		 6271 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6272 "je 1f \n\t"
6273 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 6274 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6275 "1: \n\t"
d3edefc0
AK		 6276 /* Reload cr2 if changed */
6277 "mov %c[cr2](%0), %%"R"ax \n\t"
6278 "mov %%cr2, %%"R"dx \n\t"
6279 "cmp %%"R"ax, %%"R"dx \n\t"
6280 "je 2f \n\t"
6281 "mov %%"R"ax, %%cr2 \n\t"
6282 "2: \n\t"
6aa8b732 6283 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6284 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6285 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 6286 "mov %c[rax](%0), %%"R"ax \n\t"
6287 "mov %c[rbx](%0), %%"R"bx \n\t"
6288 "mov %c[rdx](%0), %%"R"dx \n\t"
6289 "mov %c[rsi](%0), %%"R"si \n\t"
6290 "mov %c[rdi](%0), %%"R"di \n\t"
6291 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6292#ifdef CONFIG_X86_64
e08aa78a
AK		 6293 "mov %c[r8](%0), %%r8 \n\t"
6294 "mov %c[r9](%0), %%r9 \n\t"
6295 "mov %c[r10](%0), %%r10 \n\t"
6296 "mov %c[r11](%0), %%r11 \n\t"
6297 "mov %c[r12](%0), %%r12 \n\t"
6298 "mov %c[r13](%0), %%r13 \n\t"
6299 "mov %c[r14](%0), %%r14 \n\t"
6300 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6301#endif
c801949d
AK		 6302 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6303
6aa8b732 6304 /* Enter guest mode */
cd2276a7 6305 "jne .Llaunched \n\t"
4ecac3fd 6306 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6307 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6308 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6309 ".Lkvm_vmx_return: "
6aa8b732 6310 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6311 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6312 "pop %0 \n\t"
c801949d
AK		 6313 "mov %%"R"ax, %c[rax](%0) \n\t"
6314 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6315 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6316 "mov %%"R"dx, %c[rdx](%0) \n\t"
6317 "mov %%"R"si, %c[rsi](%0) \n\t"
6318 "mov %%"R"di, %c[rdi](%0) \n\t"
6319 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6320#ifdef CONFIG_X86_64
e08aa78a
AK		 6321 "mov %%r8, %c[r8](%0) \n\t"
6322 "mov %%r9, %c[r9](%0) \n\t"
6323 "mov %%r10, %c[r10](%0) \n\t"
6324 "mov %%r11, %c[r11](%0) \n\t"
6325 "mov %%r12, %c[r12](%0) \n\t"
6326 "mov %%r13, %c[r13](%0) \n\t"
6327 "mov %%r14, %c[r14](%0) \n\t"
6328 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6329#endif
c801949d
AK		 6330 "mov %%cr2, %%"R"ax \n\t"
6331 "mov %%"R"ax, %c[cr2](%0) \n\t"
6332
1c696d0e 6333 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6334 "setbe %c[fail](%0) \n\t"
6335 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6336 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6337 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6338 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6339 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6340 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6341 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6342 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6343 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6344 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6345 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6346#ifdef CONFIG_X86_64
ad312c7c
ZX		 6347 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6348 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6349 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6350 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6351 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6352 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6353 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6354 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6355#endif
40712fae
AK		 6356 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6357 [wordsize]"i"(sizeof(ulong))
c2036300 6358 : "cc", "memory"
07d6f555 6359 , R"ax", R"bx", R"di", R"si"
c2036300 6360#ifdef CONFIG_X86_64
c2036300
LV		 6361 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6362#endif
6363 );
6aa8b732 6364
aa67f609
AK		 6365#ifndef CONFIG_X86_64
6366 /*
6367 * The sysexit path does not restore ds/es, so we must set them to
6368 * a reasonable value ourselves.
6369 *
6370 * We can't defer this to vmx_load_host_state() since that function
6371 * may be executed in interrupt context, which saves and restore segments
6372 * around it, nullifying its effect.
6373 */
6374 loadsegment(ds, __USER_DS);
6375 loadsegment(es, __USER_DS);
6376#endif
6377
6de4f3ad 6378 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6379 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6380 | (1 << VCPU_EXREG_CPL)
aff48baa 6381 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6382 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6383 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6384 vcpu->arch.regs_dirty = 0;
6385
1155f76a
AK		 6386 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6387
66c78ae4
NHE		 6388 if (is_guest_mode(vcpu)) {
6389 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6390 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6391 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6392 vmcs12->idt_vectoring_error_code =
6393 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6394 vmcs12->vm_exit_instruction_len =
6395 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6396 }
6397 }
6398
d462b819 6399 vmx->loaded_vmcs->launched = 1;
1b6269db 6400
51aa01d1 6401 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6402 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6403
6404 vmx_complete_atomic_exit(vmx);
6405 vmx_recover_nmi_blocking(vmx);
cf393f75 6406 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6407}
6408
c801949d
AK		 6409#undef R
6410#undef Q
6411
6aa8b732
AK		 6412static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6413{
fb3f0f51
RR		 6414 struct vcpu_vmx *vmx = to_vmx(vcpu);
6415
cdbecfc3 6416 free_vpid(vmx);
ec378aee 6417 free_nested(vmx);
d462b819 6418 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6419 kfree(vmx->guest_msrs);
6420 kvm_vcpu_uninit(vcpu);
a4770347 6421 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6422}
6423
fb3f0f51 6424static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6425{
fb3f0f51 6426 int err;
c16f862d 6427 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6428 int cpu;
6aa8b732 6429
a2fa3e9f 6430 if (!vmx)
fb3f0f51
RR		 6431 return ERR_PTR(-ENOMEM);
6432
2384d2b3
SY		 6433 allocate_vpid(vmx);
6434
fb3f0f51
RR		 6435 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6436 if (err)
6437 goto free_vcpu;
965b58a5 6438
a2fa3e9f 6439 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6440 err = -ENOMEM;
fb3f0f51 6441 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6442 goto uninit_vcpu;
6443 }
965b58a5 6444
d462b819
NHE		 6445 vmx->loaded_vmcs = &vmx->vmcs01;
6446 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6447 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6448 goto free_msrs;
d462b819
NHE		 6449 if (!vmm_exclusive)
6450 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6451 loaded_vmcs_init(vmx->loaded_vmcs);
6452 if (!vmm_exclusive)
6453 kvm_cpu_vmxoff();
a2fa3e9f 6454
15ad7146
AK		 6455 cpu = get_cpu();
6456 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6457 vmx->vcpu.cpu = cpu;
8b9cf98c 6458 err = vmx_vcpu_setup(vmx);
fb3f0f51 6459 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6460 put_cpu();
fb3f0f51
RR		 6461 if (err)
6462 goto free_vmcs;
5e4a0b3c 6463 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6464 err = alloc_apic_access_page(kvm);
6465 if (err)
5e4a0b3c 6466 goto free_vmcs;
fb3f0f51 6467
b927a3ce
SY		 6468 if (enable_ept) {
6469 if (!kvm->arch.ept_identity_map_addr)
6470 kvm->arch.ept_identity_map_addr =
6471 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6472 err = -ENOMEM;
b7ebfb05
SY		 6473 if (alloc_identity_pagetable(kvm) != 0)
6474 goto free_vmcs;
93ea5388
GN		 6475 if (!init_rmode_identity_map(kvm))
6476 goto free_vmcs;
b927a3ce 6477 }
b7ebfb05 6478
a9d30f33
NHE		 6479 vmx->nested.current_vmptr = -1ull;
6480 vmx->nested.current_vmcs12 = NULL;
6481
fb3f0f51
RR		 6482 return &vmx->vcpu;
6483
6484free_vmcs:
5f3fbc34 6485 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6486free_msrs:
fb3f0f51
RR		 6487 kfree(vmx->guest_msrs);
6488uninit_vcpu:
6489 kvm_vcpu_uninit(&vmx->vcpu);
6490free_vcpu:
cdbecfc3 6491 free_vpid(vmx);
a4770347 6492 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6493 return ERR_PTR(err);
6aa8b732
AK		 6494}
6495
002c7f7c
YS		 6496static void __init vmx_check_processor_compat(void *rtn)
6497{
6498 struct vmcs_config vmcs_conf;
6499
6500 *(int *)rtn = 0;
6501 if (setup_vmcs_config(&vmcs_conf) < 0)
6502 *(int *)rtn = -EIO;
6503 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6504 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6505 smp_processor_id());
6506 *(int *)rtn = -EIO;
6507 }
6508}
6509
67253af5
SY		 6510static int get_ept_level(void)
6511{
6512 return VMX_EPT_DEFAULT_GAW + 1;
6513}
6514
4b12f0de 6515static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6516{
4b12f0de
SY		 6517 u64 ret;
6518
522c68c4
SY		 6519 /* For VT-d and EPT combination
6520 * 1. MMIO: always map as UC
6521 * 2. EPT with VT-d:
6522 * a. VT-d without snooping control feature: can't guarantee the
6523 * result, try to trust guest.
6524 * b. VT-d with snooping control feature: snooping control feature of
6525 * VT-d engine can guarantee the cache correctness. Just set it
6526 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6527 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6528 * consistent with host MTRR
6529 */
4b12f0de
SY		 6530 if (is_mmio)
6531 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6532 else if (vcpu->kvm->arch.iommu_domain &&
6533 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6534 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6535 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6536 else
522c68c4 6537 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6538 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6539
6540 return ret;
64d4d521
SY		 6541}
6542
17cc3935 6543static int vmx_get_lpage_level(void)
344f414f 6544{
878403b7
SY		 6545 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6546 return PT_DIRECTORY_LEVEL;
6547 else
6548 /* For shadow and EPT supported 1GB page */
6549 return PT_PDPE_LEVEL;
344f414f
JR		 6550}
6551
0e851880
SY		 6552static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6553{
4e47c7a6
SY		 6554 struct kvm_cpuid_entry2 *best;
6555 struct vcpu_vmx *vmx = to_vmx(vcpu);
6556 u32 exec_control;
6557
6558 vmx->rdtscp_enabled = false;
6559 if (vmx_rdtscp_supported()) {
6560 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6561 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6562 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6563 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6564 vmx->rdtscp_enabled = true;
6565 else {
6566 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6568 exec_control);
6569 }
6570 }
6571 }
ad756a16
MJ		 6572
6573 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6574 /* Exposing INVPCID only when PCID is exposed */
6575 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6576 if (vmx_invpcid_supported() &&
6577 best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
6578 guest_cpuid_has_pcid(vcpu)) {
6579 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6580 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6581 exec_control);
6582 } else {
6583 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6584 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6585 exec_control);
6586 if (best)
6587 best->ecx &= ~bit(X86_FEATURE_INVPCID);
6588 }
0e851880
SY		 6589}
6590
d4330ef2
JR		 6591static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6592{
7b8050f5
NHE		 6593 if (func == 1 && nested)
6594 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6595}
6596
fe3ef05c
NHE		 6597/*
6598 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6599 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6600 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6601 * guest in a way that will both be appropriate to L1's requests, and our
6602 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6603 * function also has additional necessary side-effects, like setting various
6604 * vcpu->arch fields.
6605 */
6606static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6607{
6608 struct vcpu_vmx *vmx = to_vmx(vcpu);
6609 u32 exec_control;
6610
6611 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6612 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6613 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6614 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6615 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6616 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6617 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6618 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6619 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6620 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6621 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6622 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6623 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6624 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6625 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6626 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6627 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6628 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6629 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6630 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6631 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6632 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6633 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6634 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6635 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6636 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6637 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6638 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6639 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6640 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6641 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6642 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6643 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6644 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6645 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6646 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6647
6648 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6649 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6650 vmcs12->vm_entry_intr_info_field);
6651 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6652 vmcs12->vm_entry_exception_error_code);
6653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6654 vmcs12->vm_entry_instruction_len);
6655 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6656 vmcs12->guest_interruptibility_info);
6657 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6658 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6659 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6660 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6661 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6662 vmcs12->guest_pending_dbg_exceptions);
6663 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6664 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6665
6666 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6667
6668 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6669 (vmcs_config.pin_based_exec_ctrl |
6670 vmcs12->pin_based_vm_exec_control));
6671
6672 /*
6673 * Whether page-faults are trapped is determined by a combination of
6674 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6675 * If enable_ept, L0 doesn't care about page faults and we should
6676 * set all of these to L1's desires. However, if !enable_ept, L0 does
6677 * care about (at least some) page faults, and because it is not easy
6678 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6679 * to exit on each and every L2 page fault. This is done by setting
6680 * MASK=MATCH=0 and (see below) EB.PF=1.
6681 * Note that below we don't need special code to set EB.PF beyond the
6682 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6683 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6684 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6685 *
6686 * A problem with this approach (when !enable_ept) is that L1 may be
6687 * injected with more page faults than it asked for. This could have
6688 * caused problems, but in practice existing hypervisors don't care.
6689 * To fix this, we will need to emulate the PFEC checking (on the L1
6690 * page tables), using walk_addr(), when injecting PFs to L1.
6691 */
6692 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6693 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6694 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6695 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6696
6697 if (cpu_has_secondary_exec_ctrls()) {
6698 u32 exec_control = vmx_secondary_exec_control(vmx);
6699 if (!vmx->rdtscp_enabled)
6700 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6701 /* Take the following fields only from vmcs12 */
6702 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6703 if (nested_cpu_has(vmcs12,
6704 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6705 exec_control |= vmcs12->secondary_vm_exec_control;
6706
6707 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6708 /*
6709 * Translate L1 physical address to host physical
6710 * address for vmcs02. Keep the page pinned, so this
6711 * physical address remains valid. We keep a reference
6712 * to it so we can release it later.
6713 */
6714 if (vmx->nested.apic_access_page) /* shouldn't happen */
6715 nested_release_page(vmx->nested.apic_access_page);
6716 vmx->nested.apic_access_page =
6717 nested_get_page(vcpu, vmcs12->apic_access_addr);
6718 /*
6719 * If translation failed, no matter: This feature asks
6720 * to exit when accessing the given address, and if it
6721 * can never be accessed, this feature won't do
6722 * anything anyway.
6723 */
6724 if (!vmx->nested.apic_access_page)
6725 exec_control &=
6726 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6727 else
6728 vmcs_write64(APIC_ACCESS_ADDR,
6729 page_to_phys(vmx->nested.apic_access_page));
6730 }
6731
6732 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6733 }
6734
6735
6736 /*
6737 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6738 * Some constant fields are set here by vmx_set_constant_host_state().
6739 * Other fields are different per CPU, and will be set later when
6740 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6741 */
6742 vmx_set_constant_host_state();
6743
6744 /*
6745 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6746 * entry, but only if the current (host) sp changed from the value
6747 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6748 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6749 * here we just force the write to happen on entry.
6750 */
6751 vmx->host_rsp = 0;
6752
6753 exec_control = vmx_exec_control(vmx); /* L0's desires */
6754 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6755 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6756 exec_control &= ~CPU_BASED_TPR_SHADOW;
6757 exec_control |= vmcs12->cpu_based_vm_exec_control;
6758 /*
6759 * Merging of IO and MSR bitmaps not currently supported.
6760 * Rather, exit every time.
6761 */
6762 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6763 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6764 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6765
6766 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6767
6768 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6769 * bitwise-or of what L1 wants to trap for L2, and what we want to
6770 * trap. Note that CR0.TS also needs updating - we do this later.
6771 */
6772 update_exception_bitmap(vcpu);
6773 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6774 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6775
6776 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6777 vmcs_write32(VM_EXIT_CONTROLS,
6778 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6779 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6780 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6781
6782 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6783 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6784 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6785 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6786
6787
6788 set_cr4_guest_host_mask(vmx);
6789
27fc51b2
NHE		 6790 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6791 vmcs_write64(TSC_OFFSET,
6792 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6793 else
6794 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 6795
6796 if (enable_vpid) {
6797 /*
6798 * Trivially support vpid by letting L2s share their parent
6799 * L1's vpid. TODO: move to a more elaborate solution, giving
6800 * each L2 its own vpid and exposing the vpid feature to L1.
6801 */
6802 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6803 vmx_flush_tlb(vcpu);
6804 }
6805
6806 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6807 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6808 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6809 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6810 else
6811 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6812 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6813 vmx_set_efer(vcpu, vcpu->arch.efer);
6814
6815 /*
6816 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6817 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6818 * The CR0_READ_SHADOW is what L2 should have expected to read given
6819 * the specifications by L1; It's not enough to take
6820 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6821 * have more bits than L1 expected.
6822 */
6823 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6825
6826 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6827 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6828
6829 /* shadow page tables on either EPT or shadow page tables */
6830 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6831 kvm_mmu_reset_context(vcpu);
6832
6833 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6834 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6835}
6836
cd232ad0
NHE		 6837/*
6838 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6839 * for running an L2 nested guest.
6840 */
6841static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6842{
6843 struct vmcs12 *vmcs12;
6844 struct vcpu_vmx *vmx = to_vmx(vcpu);
6845 int cpu;
6846 struct loaded_vmcs *vmcs02;
6847
6848 if (!nested_vmx_check_permission(vcpu) ||
6849 !nested_vmx_check_vmcs12(vcpu))
6850 return 1;
6851
6852 skip_emulated_instruction(vcpu);
6853 vmcs12 = get_vmcs12(vcpu);
6854
7c177938
NHE		 6855 /*
6856 * The nested entry process starts with enforcing various prerequisites
6857 * on vmcs12 as required by the Intel SDM, and act appropriately when
6858 * they fail: As the SDM explains, some conditions should cause the
6859 * instruction to fail, while others will cause the instruction to seem
6860 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6861 * To speed up the normal (success) code path, we should avoid checking
6862 * for misconfigurations which will anyway be caught by the processor
6863 * when using the merged vmcs02.
6864 */
6865 if (vmcs12->launch_state == launch) {
6866 nested_vmx_failValid(vcpu,
6867 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6868 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6869 return 1;
6870 }
6871
6872 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6873 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6874 /*TODO: Also verify bits beyond physical address width are 0*/
6875 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6876 return 1;
6877 }
6878
6879 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6880 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6881 /*TODO: Also verify bits beyond physical address width are 0*/
6882 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6883 return 1;
6884 }
6885
6886 if (vmcs12->vm_entry_msr_load_count > 0 ||
6887 vmcs12->vm_exit_msr_load_count > 0 ||
6888 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 6889 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6890 __func__);
7c177938
NHE		 6891 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6892 return 1;
6893 }
6894
6895 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6896 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6897 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6898 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6899 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6900 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6901 !vmx_control_verify(vmcs12->vm_exit_controls,
6902 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6903 !vmx_control_verify(vmcs12->vm_entry_controls,
6904 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6905 {
6906 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6907 return 1;
6908 }
6909
6910 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6911 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6912 nested_vmx_failValid(vcpu,
6913 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6914 return 1;
6915 }
6916
6917 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6918 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6919 nested_vmx_entry_failure(vcpu, vmcs12,
6920 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6921 return 1;
6922 }
6923 if (vmcs12->vmcs_link_pointer != -1ull) {
6924 nested_vmx_entry_failure(vcpu, vmcs12,
6925 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6926 return 1;
6927 }
6928
6929 /*
6930 * We're finally done with prerequisite checking, and can start with
6931 * the nested entry.
6932 */
6933
cd232ad0
NHE		 6934 vmcs02 = nested_get_current_vmcs02(vmx);
6935 if (!vmcs02)
6936 return -ENOMEM;
6937
6938 enter_guest_mode(vcpu);
6939
6940 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6941
6942 cpu = get_cpu();
6943 vmx->loaded_vmcs = vmcs02;
6944 vmx_vcpu_put(vcpu);
6945 vmx_vcpu_load(vcpu, cpu);
6946 vcpu->cpu = cpu;
6947 put_cpu();
6948
6949 vmcs12->launch_state = 1;
6950
6951 prepare_vmcs02(vcpu, vmcs12);
6952
6953 /*
6954 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6955 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6956 * returned as far as L1 is concerned. It will only return (and set
6957 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6958 */
6959 return 1;
6960}
6961
4704d0be
NHE		 6962/*
6963 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6964 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6965 * This function returns the new value we should put in vmcs12.guest_cr0.
6966 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6967 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6968 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6969 * didn't trap the bit, because if L1 did, so would L0).
6970 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6971 * been modified by L2, and L1 knows it. So just leave the old value of
6972 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6973 * isn't relevant, because if L0 traps this bit it can set it to anything.
6974 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6975 * changed these bits, and therefore they need to be updated, but L0
6976 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6977 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6978 */
6979static inline unsigned long
6980vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6981{
6982 return
6983 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6984 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6985 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6986 vcpu->arch.cr0_guest_owned_bits));
6987}
6988
6989static inline unsigned long
6990vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6991{
6992 return
6993 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6994 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6995 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6996 vcpu->arch.cr4_guest_owned_bits));
6997}
6998
6999/*
7000 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7001 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7002 * and this function updates it to reflect the changes to the guest state while
7003 * L2 was running (and perhaps made some exits which were handled directly by L0
7004 * without going back to L1), and to reflect the exit reason.
7005 * Note that we do not have to copy here all VMCS fields, just those that
7006 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7007 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7008 * which already writes to vmcs12 directly.
7009 */
7010void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7011{
7012 /* update guest state fields: */
7013 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7014 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7015
7016 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7017 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7018 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7019 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7020
7021 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7022 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7023 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7024 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7025 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7026 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7027 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7028 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7029 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7030 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7031 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7032 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7033 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7034 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7035 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7036 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7037 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7038 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7039 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7040 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7041 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7042 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7043 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7044 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7045 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7046 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7047 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7048 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7049 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7050 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7051 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7052 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7053 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7054 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7055 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7056 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7057
7058 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7059 vmcs12->guest_interruptibility_info =
7060 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7061 vmcs12->guest_pending_dbg_exceptions =
7062 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7063
7064 /* TODO: These cannot have changed unless we have MSR bitmaps and
7065 * the relevant bit asks not to trap the change */
7066 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7067 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7068 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7069 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7070 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7071 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7072
7073 /* update exit information fields: */
7074
7075 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7076 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7077
7078 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7079 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7080 vmcs12->idt_vectoring_info_field =
7081 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7082 vmcs12->idt_vectoring_error_code =
7083 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7084 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7085 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7086
7087 /* clear vm-entry fields which are to be cleared on exit */
7088 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7089 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7090}
7091
7092/*
7093 * A part of what we need to when the nested L2 guest exits and we want to
7094 * run its L1 parent, is to reset L1's guest state to the host state specified
7095 * in vmcs12.
7096 * This function is to be called not only on normal nested exit, but also on
7097 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7098 * Failures During or After Loading Guest State").
7099 * This function should be called when the active VMCS is L1's (vmcs01).
7100 */
7101void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7102{
7103 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7104 vcpu->arch.efer = vmcs12->host_ia32_efer;
7105 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7106 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7107 else
7108 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7109 vmx_set_efer(vcpu, vcpu->arch.efer);
7110
7111 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7112 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7113 /*
7114 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7115 * actually changed, because it depends on the current state of
7116 * fpu_active (which may have changed).
7117 * Note that vmx_set_cr0 refers to efer set above.
7118 */
7119 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7120 /*
7121 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7122 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7123 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7124 */
7125 update_exception_bitmap(vcpu);
7126 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7127 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7128
7129 /*
7130 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7131 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7132 */
7133 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7134 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7135
7136 /* shadow page tables on either EPT or shadow page tables */
7137 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7138 kvm_mmu_reset_context(vcpu);
7139
7140 if (enable_vpid) {
7141 /*
7142 * Trivially support vpid by letting L2s share their parent
7143 * L1's vpid. TODO: move to a more elaborate solution, giving
7144 * each L2 its own vpid and exposing the vpid feature to L1.
7145 */
7146 vmx_flush_tlb(vcpu);
7147 }
7148
7149
7150 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7151 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7152 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7153 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7154 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7155 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7156 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7157 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7158 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7159 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7160 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7161 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7162 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7163 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7164 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7165
7166 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7167 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7168 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7169 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7170 vmcs12->host_ia32_perf_global_ctrl);
7171}
7172
7173/*
7174 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7175 * and modify vmcs12 to make it see what it would expect to see there if
7176 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7177 */
7178static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7179{
7180 struct vcpu_vmx *vmx = to_vmx(vcpu);
7181 int cpu;
7182 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7183
7184 leave_guest_mode(vcpu);
7185 prepare_vmcs12(vcpu, vmcs12);
7186
7187 cpu = get_cpu();
7188 vmx->loaded_vmcs = &vmx->vmcs01;
7189 vmx_vcpu_put(vcpu);
7190 vmx_vcpu_load(vcpu, cpu);
7191 vcpu->cpu = cpu;
7192 put_cpu();
7193
7194 /* if no vmcs02 cache requested, remove the one we used */
7195 if (VMCS02_POOL_SIZE == 0)
7196 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7197
7198 load_vmcs12_host_state(vcpu, vmcs12);
7199
27fc51b2 7200 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7201 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7202
7203 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7204 vmx->host_rsp = 0;
7205
7206 /* Unpin physical memory we referred to in vmcs02 */
7207 if (vmx->nested.apic_access_page) {
7208 nested_release_page(vmx->nested.apic_access_page);
7209 vmx->nested.apic_access_page = 0;
7210 }
7211
7212 /*
7213 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7214 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7215 * success or failure flag accordingly.
7216 */
7217 if (unlikely(vmx->fail)) {
7218 vmx->fail = 0;
7219 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7220 } else
7221 nested_vmx_succeed(vcpu);
7222}
7223
7c177938
NHE		 7224/*
7225 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7226 * 23.7 "VM-entry failures during or after loading guest state" (this also
7227 * lists the acceptable exit-reason and exit-qualification parameters).
7228 * It should only be called before L2 actually succeeded to run, and when
7229 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7230 */
7231static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7232 struct vmcs12 *vmcs12,
7233 u32 reason, unsigned long qualification)
7234{
7235 load_vmcs12_host_state(vcpu, vmcs12);
7236 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7237 vmcs12->exit_qualification = qualification;
7238 nested_vmx_succeed(vcpu);
7239}
7240
8a76d7f2
JR		 7241static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7242 struct x86_instruction_info *info,
7243 enum x86_intercept_stage stage)
7244{
7245 return X86EMUL_CONTINUE;
7246}
7247
cbdd1bea 7248static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7249 .cpu_has_kvm_support = cpu_has_kvm_support,
7250 .disabled_by_bios = vmx_disabled_by_bios,
7251 .hardware_setup = hardware_setup,
7252 .hardware_unsetup = hardware_unsetup,
002c7f7c 7253 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7254 .hardware_enable = hardware_enable,
7255 .hardware_disable = hardware_disable,
04547156 7256 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7257
7258 .vcpu_create = vmx_create_vcpu,
7259 .vcpu_free = vmx_free_vcpu,
04d2cc77 7260 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7261
04d2cc77 7262 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7263 .vcpu_load = vmx_vcpu_load,
7264 .vcpu_put = vmx_vcpu_put,
7265
7266 .set_guest_debug = set_guest_debug,
7267 .get_msr = vmx_get_msr,
7268 .set_msr = vmx_set_msr,
7269 .get_segment_base = vmx_get_segment_base,
7270 .get_segment = vmx_get_segment,
7271 .set_segment = vmx_set_segment,
2e4d2653 7272 .get_cpl = vmx_get_cpl,
6aa8b732 7273 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7274 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7275 .decache_cr3 = vmx_decache_cr3,
25c4c276 7276 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7277 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7278 .set_cr3 = vmx_set_cr3,
7279 .set_cr4 = vmx_set_cr4,
6aa8b732 7280 .set_efer = vmx_set_efer,
6aa8b732
AK		 7281 .get_idt = vmx_get_idt,
7282 .set_idt = vmx_set_idt,
7283 .get_gdt = vmx_get_gdt,
7284 .set_gdt = vmx_set_gdt,
020df079 7285 .set_dr7 = vmx_set_dr7,
5fdbf976 7286 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7287 .get_rflags = vmx_get_rflags,
7288 .set_rflags = vmx_set_rflags,
ebcbab4c 7289 .fpu_activate = vmx_fpu_activate,
02daab21 7290 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7291
7292 .tlb_flush = vmx_flush_tlb,
6aa8b732 7293
6aa8b732 7294 .run = vmx_vcpu_run,
6062d012 7295 .handle_exit = vmx_handle_exit,
6aa8b732 7296 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7297 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7298 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7299 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7300 .set_irq = vmx_inject_irq,
95ba8273 7301 .set_nmi = vmx_inject_nmi,
298101da 7302 .queue_exception = vmx_queue_exception,
b463a6f7 7303 .cancel_injection = vmx_cancel_injection,
78646121 7304 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7305 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7306 .get_nmi_mask = vmx_get_nmi_mask,
7307 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7308 .enable_nmi_window = enable_nmi_window,
7309 .enable_irq_window = enable_irq_window,
7310 .update_cr8_intercept = update_cr8_intercept,
95ba8273 7311
cbc94022 7312 .set_tss_addr = vmx_set_tss_addr,
67253af5 7313 .get_tdp_level = get_ept_level,
4b12f0de 7314 .get_mt_mask = vmx_get_mt_mask,
229456fc 7315
586f9607 7316 .get_exit_info = vmx_get_exit_info,
586f9607 7317
17cc3935 7318 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7319
7320 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7321
7322 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7323 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7324
7325 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7326
7327 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7328
4051b188 7329 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7330 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7331 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7332 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7333 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7334
7335 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7336
7337 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7338};
7339
7340static int __init vmx_init(void)
7341{
26bb0981
AK		 7342 int r, i;
7343
7344 rdmsrl_safe(MSR_EFER, &host_efer);
7345
7346 for (i = 0; i < NR_VMX_MSR; ++i)
7347 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7348
3e7c73e9 7349 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7350 if (!vmx_io_bitmap_a)
7351 return -ENOMEM;
7352
2106a548
GC		 7353 r = -ENOMEM;
7354
3e7c73e9 7355 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7356 if (!vmx_io_bitmap_b)
fdef3ad1 7357 goto out;
fdef3ad1 7358
5897297b 7359 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7360 if (!vmx_msr_bitmap_legacy)
25c5f225 7361 goto out1;
2106a548 7362
25c5f225 7363
5897297b 7364 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7365 if (!vmx_msr_bitmap_longmode)
5897297b 7366 goto out2;
2106a548 7367
5897297b 7368
fdef3ad1
HQ		 7369 /*
7370 * Allow direct access to the PC debug port (it is often used for I/O
7371 * delays, but the vmexits simply slow things down).
7372 */
3e7c73e9
AK		 7373 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7374 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7375
3e7c73e9 7376 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7377
5897297b
AK		 7378 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7379 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7380
2384d2b3
SY		 7381 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7382
0ee75bea
AK		 7383 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7384 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7385 if (r)
5897297b 7386 goto out3;
25c5f225 7387
5897297b
AK		 7388 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7389 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7390 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7391 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7392 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7393 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7394
089d034e 7395 if (enable_ept) {
3f6d8c8a
XH		 7396 kvm_mmu_set_mask_ptes(0ull,
7397 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7398 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7399 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7400 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7401 kvm_enable_tdp();
7402 } else
7403 kvm_disable_tdp();
1439442c 7404
fdef3ad1
HQ		 7405 return 0;
7406
5897297b
AK		 7407out3:
7408 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7409out2:
5897297b 7410 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7411out1:
3e7c73e9 7412 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7413out:
3e7c73e9 7414 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7415 return r;
6aa8b732
AK		 7416}
7417
7418static void __exit vmx_exit(void)
7419{
5897297b
AK		 7420 free_page((unsigned long)vmx_msr_bitmap_legacy);
7421 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7422 free_page((unsigned long)vmx_io_bitmap_b);
7423 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7424
cb498ea2 7425 kvm_exit();
6aa8b732
AK		 7426}
7427
7428module_init(vmx_init)
7429module_exit(vmx_exit)
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