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nVMX: Fix pick-up of uninjected NMIs
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93
GN		 1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1901 */
e011c663 1902static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1903{
1904 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
e011c663 1906 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1907 return 0;
1908
1909 nested_vmx_vmexit(vcpu);
1910 return 1;
1911}
1912
298101da 1913static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1914 bool has_error_code, u32 error_code,
1915 bool reinject)
298101da 1916{
77ab6db0 1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1918 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1919
e011c663
GN		 1920 if (!reinject && is_guest_mode(vcpu) &&
1921 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1922 return;
1923
8ab2d2e2 1924 if (has_error_code) {
77ab6db0 1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1926 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927 }
77ab6db0 1928
7ffd92c5 1929 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1930 int inc_eip = 0;
1931 if (kvm_exception_is_soft(nr))
1932 inc_eip = vcpu->arch.event_exit_inst_len;
1933 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1935 return;
1936 }
1937
66fd3f7f
GN		 1938 if (kvm_exception_is_soft(nr)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1941 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942 } else
1943 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1946}
1947
4e47c7a6
SY		 1948static bool vmx_rdtscp_supported(void)
1949{
1950 return cpu_has_vmx_rdtscp();
1951}
1952
ad756a16
MJ		 1953static bool vmx_invpcid_supported(void)
1954{
1955 return cpu_has_vmx_invpcid() && enable_ept;
1956}
1957
a75beee6
ED		 1958/*
1959 * Swap MSR entry in host/guest MSR entry array.
1960 */
8b9cf98c 1961static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1962{
26bb0981 1963 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1964
1965 tmp = vmx->guest_msrs[to];
1966 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1968}
1969
8d14695f
YZ		 1970static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971{
1972 unsigned long *msr_bitmap;
1973
1974 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975 if (is_long_mode(vcpu))
1976 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977 else
1978 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979 } else {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy;
1984 }
1985
1986 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987}
1988
e38aea3e
AK		 1989/*
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1993 */
8b9cf98c 1994static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1995{
26bb0981 1996 int save_nmsrs, index;
e38aea3e 1997
a75beee6
ED		 1998 save_nmsrs = 0;
1999#ifdef CONFIG_X86_64
8b9cf98c 2000 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2001 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2002 if (index >= 0)
8b9cf98c
RR		 2003 move_msr_up(vmx, index, save_nmsrs++);
2004 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2005 if (index >= 0)
8b9cf98c
RR		 2006 move_msr_up(vmx, index, save_nmsrs++);
2007 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2008 if (index >= 0)
8b9cf98c 2009 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2010 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011 if (index >= 0 && vmx->rdtscp_enabled)
2012 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2013 /*
8c06585d 2014 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2015 * if efer.sce is enabled.
2016 */
8c06585d 2017 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2018 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2019 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2020 }
2021#endif
92c0d900
AK		 2022 index = __find_msr_index(vmx, MSR_EFER);
2023 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2024 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2025
26bb0981 2026 vmx->save_nmsrs = save_nmsrs;
5897297b 2027
8d14695f
YZ		 2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2030}
2031
6aa8b732
AK		 2032/*
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2035 */
2036static u64 guest_read_tsc(void)
2037{
2038 u64 host_tsc, tsc_offset;
2039
2040 rdtscll(host_tsc);
2041 tsc_offset = vmcs_read64(TSC_OFFSET);
2042 return host_tsc + tsc_offset;
2043}
2044
d5c1785d
NHE		 2045/*
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2048 */
886b470c 2049u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2050{
886b470c 2051 u64 tsc_offset;
d5c1785d 2052
d5c1785d
NHE		 2053 tsc_offset = is_guest_mode(vcpu) ?
2054 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055 vmcs_read64(TSC_OFFSET);
2056 return host_tsc + tsc_offset;
2057}
2058
4051b188 2059/*
cc578287
ZA		 2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
4051b188 2062 */
cc578287 2063static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2064{
cc578287
ZA		 2065 if (!scale)
2066 return;
2067
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 } else
2072 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2073}
2074
ba904635
WA		 2075static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076{
2077 return vmcs_read64(TSC_OFFSET);
2078}
2079
6aa8b732 2080/*
99e3e30a 2081 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2082 */
99e3e30a 2083static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2084{
27fc51b2 2085 if (is_guest_mode(vcpu)) {
7991825b 2086 /*
27fc51b2
NHE		 2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
7991825b 2091 */
27fc51b2
NHE		 2092 struct vmcs12 *vmcs12;
2093 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12 = get_vmcs12(vcpu);
2096 vmcs_write64(TSC_OFFSET, offset +
2097 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098 vmcs12->tsc_offset : 0));
2099 } else {
489223ed
YY		 2100 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2102 vmcs_write64(TSC_OFFSET, offset);
2103 }
6aa8b732
AK		 2104}
2105
f1e2b260 2106static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2107{
2108 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2109
e48672fa 2110 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2111 if (is_guest_mode(vcpu)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2114 } else
2115 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116 offset + adjustment);
e48672fa
ZA		 2117}
2118
857e4099
JR		 2119static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120{
2121 return target_tsc - native_read_tsc();
2122}
2123
801d3424
NHE		 2124static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125{
2126 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128}
2129
2130/*
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2135 */
2136static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137{
2138 return nested && guest_cpuid_has_vmx(vcpu);
2139}
2140
b87a51ae
NHE		 2141/*
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2151 * or other means.
2152 */
2153static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2158static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2159static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2160static __init void nested_vmx_setup_ctls_msrs(void)
2161{
2162 /*
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2175 */
2176
2177 /* pin-based controls */
eabeaacc
JK		 2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2180 /*
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183 */
eabeaacc
JK		 2184 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2186 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2188 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2189
33fb20c3
JK		 2190 /*
2191 * Exit controls
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193 * 17 must be 1.
2194 */
c0dfee58
ACL		 2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2197 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2199 nested_vmx_exit_ctls_high &=
b87a51ae 2200#ifdef CONFIG_X86_64
c0dfee58 2201 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2202#endif
7854cbca
ACL		 2203 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2204 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2205 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2206 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2207 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2208 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2209 }
8049d651 2210 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2211 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2212
2213 /* entry controls */
2214 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2215 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2216 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2218 nested_vmx_entry_ctls_high &=
57435349
JK		 2219#ifdef CONFIG_X86_64
2220 VM_ENTRY_IA32E_MODE |
2221#endif
2222 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2223 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2224 VM_ENTRY_LOAD_IA32_EFER);
57435349 2225
b87a51ae
NHE		 2226 /* cpu-based controls */
2227 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2228 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2229 nested_vmx_procbased_ctls_low = 0;
2230 nested_vmx_procbased_ctls_high &=
2231 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2232 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2233 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2234 CPU_BASED_CR3_STORE_EXITING |
2235#ifdef CONFIG_X86_64
2236 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2237#endif
2238 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2239 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2240 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2241 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2242 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2243 /*
2244 * We can allow some features even when not supported by the
2245 * hardware. For example, L1 can specify an MSR bitmap - and we
2246 * can use it to avoid exits to L1 - even when L0 runs L2
2247 * without MSR bitmaps.
2248 */
2249 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2250
2251 /* secondary cpu-based controls */
2252 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2253 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2254 nested_vmx_secondary_ctls_low = 0;
2255 nested_vmx_secondary_ctls_high &=
d6851fbe 2256 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2257 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2258 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2259
afa61f75
NHE		 2260 if (enable_ept) {
2261 /* nested EPT: emulate EPT also to L1 */
2262 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2263 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2264 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2265 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2266 nested_vmx_ept_caps &= vmx_capability.ept;
2267 /*
2268 * Since invept is completely emulated we support both global
2269 * and context invalidation independent of what host cpu
2270 * supports
2271 */
2272 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2273 VMX_EPT_EXTENT_CONTEXT_BIT;
2274 } else
2275 nested_vmx_ept_caps = 0;
2276
c18911a2
JK		 2277 /* miscellaneous data */
2278 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2279 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2280 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2281 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2282}
2283
2284static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2285{
2286 /*
2287 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2288 */
2289 return ((control & high) | low) == control;
2290}
2291
2292static inline u64 vmx_control_msr(u32 low, u32 high)
2293{
2294 return low | ((u64)high << 32);
2295}
2296
2297/*
2298 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2299 * also let it use VMX-specific MSRs.
2300 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2301 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2302 * like all other MSRs).
2303 */
2304static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2305{
2306 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2307 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2308 /*
2309 * According to the spec, processors which do not support VMX
2310 * should throw a #GP(0) when VMX capability MSRs are read.
2311 */
2312 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2313 return 1;
2314 }
2315
2316 switch (msr_index) {
2317 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2318 if (nested_vmx_allowed(vcpu)) {
2319 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2320 break;
2321 }
2322 return 0;
b87a51ae
NHE		 2323 case MSR_IA32_VMX_BASIC:
2324 /*
2325 * This MSR reports some information about VMX support. We
2326 * should return information about the VMX we emulate for the
2327 * guest, and the VMCS structure we give it - not about the
2328 * VMX support of the underlying hardware.
2329 */
2330 *pdata = VMCS12_REVISION |
2331 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2332 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2333 break;
2334 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2335 case MSR_IA32_VMX_PINBASED_CTLS:
2336 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2337 nested_vmx_pinbased_ctls_high);
2338 break;
2339 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2340 case MSR_IA32_VMX_PROCBASED_CTLS:
2341 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2342 nested_vmx_procbased_ctls_high);
2343 break;
2344 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2345 case MSR_IA32_VMX_EXIT_CTLS:
2346 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2347 nested_vmx_exit_ctls_high);
2348 break;
2349 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2350 case MSR_IA32_VMX_ENTRY_CTLS:
2351 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2352 nested_vmx_entry_ctls_high);
2353 break;
2354 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2355 *pdata = vmx_control_msr(nested_vmx_misc_low,
2356 nested_vmx_misc_high);
b87a51ae
NHE		 2357 break;
2358 /*
2359 * These MSRs specify bits which the guest must keep fixed (on or off)
2360 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2361 * We picked the standard core2 setting.
2362 */
2363#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2364#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2365 case MSR_IA32_VMX_CR0_FIXED0:
2366 *pdata = VMXON_CR0_ALWAYSON;
2367 break;
2368 case MSR_IA32_VMX_CR0_FIXED1:
2369 *pdata = -1ULL;
2370 break;
2371 case MSR_IA32_VMX_CR4_FIXED0:
2372 *pdata = VMXON_CR4_ALWAYSON;
2373 break;
2374 case MSR_IA32_VMX_CR4_FIXED1:
2375 *pdata = -1ULL;
2376 break;
2377 case MSR_IA32_VMX_VMCS_ENUM:
2378 *pdata = 0x1f;
2379 break;
2380 case MSR_IA32_VMX_PROCBASED_CTLS2:
2381 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2382 nested_vmx_secondary_ctls_high);
2383 break;
2384 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2385 /* Currently, no nested vpid support */
2386 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2387 break;
2388 default:
2389 return 0;
2390 }
2391
2392 return 1;
2393}
2394
b3897a49 2395static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2396{
b3897a49
NHE		 2397 u32 msr_index = msr_info->index;
2398 u64 data = msr_info->data;
2399 bool host_initialized = msr_info->host_initiated;
2400
b87a51ae
NHE		 2401 if (!nested_vmx_allowed(vcpu))
2402 return 0;
2403
b3897a49
NHE		 2404 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2405 if (!host_initialized &&
2406 to_vmx(vcpu)->nested.msr_ia32_feature_control
2407 & FEATURE_CONTROL_LOCKED)
2408 return 0;
2409 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2410 return 1;
b3897a49
NHE		 2411 }
2412
b87a51ae
NHE		 2413 /*
2414 * No need to treat VMX capability MSRs specially: If we don't handle
2415 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2416 */
2417 return 0;
2418}
2419
6aa8b732
AK		 2420/*
2421 * Reads an msr value (of 'msr_index') into 'pdata'.
2422 * Returns 0 on success, non-0 otherwise.
2423 * Assumes vcpu_load() was already called.
2424 */
2425static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2426{
2427 u64 data;
26bb0981 2428 struct shared_msr_entry *msr;
6aa8b732
AK		 2429
2430 if (!pdata) {
2431 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2432 return -EINVAL;
2433 }
2434
2435 switch (msr_index) {
05b3e0c2 2436#ifdef CONFIG_X86_64
6aa8b732
AK		 2437 case MSR_FS_BASE:
2438 data = vmcs_readl(GUEST_FS_BASE);
2439 break;
2440 case MSR_GS_BASE:
2441 data = vmcs_readl(GUEST_GS_BASE);
2442 break;
44ea2b17
AK		 2443 case MSR_KERNEL_GS_BASE:
2444 vmx_load_host_state(to_vmx(vcpu));
2445 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2446 break;
26bb0981 2447#endif
6aa8b732 2448 case MSR_EFER:
3bab1f5d 2449 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2450 case MSR_IA32_TSC:
6aa8b732
AK		 2451 data = guest_read_tsc();
2452 break;
2453 case MSR_IA32_SYSENTER_CS:
2454 data = vmcs_read32(GUEST_SYSENTER_CS);
2455 break;
2456 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2457 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2458 break;
2459 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2460 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2461 break;
4e47c7a6
SY		 2462 case MSR_TSC_AUX:
2463 if (!to_vmx(vcpu)->rdtscp_enabled)
2464 return 1;
2465 /* Otherwise falls through */
6aa8b732 2466 default:
b87a51ae
NHE		 2467 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2468 return 0;
8b9cf98c 2469 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2470 if (msr) {
2471 data = msr->data;
2472 break;
6aa8b732 2473 }
3bab1f5d 2474 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2475 }
2476
2477 *pdata = data;
2478 return 0;
2479}
2480
2481/*
2482 * Writes msr value into into the appropriate "register".
2483 * Returns 0 on success, non-0 otherwise.
2484 * Assumes vcpu_load() was already called.
2485 */
8fe8ab46 2486static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2487{
a2fa3e9f 2488 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2489 struct shared_msr_entry *msr;
2cc51560 2490 int ret = 0;
8fe8ab46
WA		 2491 u32 msr_index = msr_info->index;
2492 u64 data = msr_info->data;
2cc51560 2493
6aa8b732 2494 switch (msr_index) {
3bab1f5d 2495 case MSR_EFER:
8fe8ab46 2496 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2497 break;
16175a79 2498#ifdef CONFIG_X86_64
6aa8b732 2499 case MSR_FS_BASE:
2fb92db1 2500 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2501 vmcs_writel(GUEST_FS_BASE, data);
2502 break;
2503 case MSR_GS_BASE:
2fb92db1 2504 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2505 vmcs_writel(GUEST_GS_BASE, data);
2506 break;
44ea2b17
AK		 2507 case MSR_KERNEL_GS_BASE:
2508 vmx_load_host_state(vmx);
2509 vmx->msr_guest_kernel_gs_base = data;
2510 break;
6aa8b732
AK		 2511#endif
2512 case MSR_IA32_SYSENTER_CS:
2513 vmcs_write32(GUEST_SYSENTER_CS, data);
2514 break;
2515 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2516 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2517 break;
2518 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2519 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2520 break;
af24a4e4 2521 case MSR_IA32_TSC:
8fe8ab46 2522 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2523 break;
468d472f
SY		 2524 case MSR_IA32_CR_PAT:
2525 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2526 vmcs_write64(GUEST_IA32_PAT, data);
2527 vcpu->arch.pat = data;
2528 break;
2529 }
8fe8ab46 2530 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2531 break;
ba904635
WA		 2532 case MSR_IA32_TSC_ADJUST:
2533 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2534 break;
2535 case MSR_TSC_AUX:
2536 if (!vmx->rdtscp_enabled)
2537 return 1;
2538 /* Check reserved bit, higher 32 bits should be zero */
2539 if ((data >> 32) != 0)
2540 return 1;
2541 /* Otherwise falls through */
6aa8b732 2542 default:
b3897a49 2543 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2544 break;
8b9cf98c 2545 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2546 if (msr) {
2547 msr->data = data;
2225fd56
AK		 2548 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2549 preempt_disable();
9ee73970
AK		 2550 kvm_set_shared_msr(msr->index, msr->data,
2551 msr->mask);
2225fd56
AK		 2552 preempt_enable();
2553 }
3bab1f5d 2554 break;
6aa8b732 2555 }
8fe8ab46 2556 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2557 }
2558
2cc51560 2559 return ret;
6aa8b732
AK		 2560}
2561
5fdbf976 2562static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2563{
5fdbf976
MT		 2564 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2565 switch (reg) {
2566 case VCPU_REGS_RSP:
2567 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2568 break;
2569 case VCPU_REGS_RIP:
2570 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2571 break;
6de4f3ad
AK		 2572 case VCPU_EXREG_PDPTR:
2573 if (enable_ept)
2574 ept_save_pdptrs(vcpu);
2575 break;
5fdbf976
MT		 2576 default:
2577 break;
2578 }
6aa8b732
AK		 2579}
2580
6aa8b732
AK		 2581static __init int cpu_has_kvm_support(void)
2582{
6210e37b 2583 return cpu_has_vmx();
6aa8b732
AK		 2584}
2585
2586static __init int vmx_disabled_by_bios(void)
2587{
2588 u64 msr;
2589
2590 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2591 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2592 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2593 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2594 && tboot_enabled())
2595 return 1;
23f3e991 2596 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2597 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2598 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2599 && !tboot_enabled()) {
2600 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2601 "activate TXT before enabling KVM\n");
cafd6659 2602 return 1;
f9335afe 2603 }
23f3e991
JC		 2604 /* launched w/o TXT and VMX disabled */
2605 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2606 && !tboot_enabled())
2607 return 1;
cafd6659
SW		 2608 }
2609
2610 return 0;
6aa8b732
AK		 2611}
2612
7725b894
DX		 2613static void kvm_cpu_vmxon(u64 addr)
2614{
2615 asm volatile (ASM_VMX_VMXON_RAX
2616 : : "a"(&addr), "m"(addr)
2617 : "memory", "cc");
2618}
2619
10474ae8 2620static int hardware_enable(void *garbage)
6aa8b732
AK		 2621{
2622 int cpu = raw_smp_processor_id();
2623 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2624 u64 old, test_bits;
6aa8b732 2625
10474ae8
AG		 2626 if (read_cr4() & X86_CR4_VMXE)
2627 return -EBUSY;
2628
d462b819 2629 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2630
2631 /*
2632 * Now we can enable the vmclear operation in kdump
2633 * since the loaded_vmcss_on_cpu list on this cpu
2634 * has been initialized.
2635 *
2636 * Though the cpu is not in VMX operation now, there
2637 * is no problem to enable the vmclear operation
2638 * for the loaded_vmcss_on_cpu list is empty!
2639 */
2640 crash_enable_local_vmclear(cpu);
2641
6aa8b732 2642 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2643
2644 test_bits = FEATURE_CONTROL_LOCKED;
2645 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2646 if (tboot_enabled())
2647 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2648
2649 if ((old & test_bits) != test_bits) {
6aa8b732 2650 /* enable and lock */
cafd6659
SW		 2651 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2652 }
66aee91a 2653 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2654
4610c9cc
DX		 2655 if (vmm_exclusive) {
2656 kvm_cpu_vmxon(phys_addr);
2657 ept_sync_global();
2658 }
10474ae8 2659
357d1226 2660 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2661
10474ae8 2662 return 0;
6aa8b732
AK		 2663}
2664
d462b819 2665static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2666{
2667 int cpu = raw_smp_processor_id();
d462b819 2668 struct loaded_vmcs *v, *n;
543e4243 2669
d462b819
NHE		 2670 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2671 loaded_vmcss_on_cpu_link)
2672 __loaded_vmcs_clear(v);
543e4243
AK		 2673}
2674
710ff4a8
EH		 2675
2676/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2677 * tricks.
2678 */
2679static void kvm_cpu_vmxoff(void)
6aa8b732 2680{
4ecac3fd 2681 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2682}
2683
710ff4a8
EH		 2684static void hardware_disable(void *garbage)
2685{
4610c9cc 2686 if (vmm_exclusive) {
d462b819 2687 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2688 kvm_cpu_vmxoff();
2689 }
7725b894 2690 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2691}
2692
1c3d14fe 2693static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2694 u32 msr, u32 *result)
1c3d14fe
YS		 2695{
2696 u32 vmx_msr_low, vmx_msr_high;
2697 u32 ctl = ctl_min | ctl_opt;
2698
2699 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2700
2701 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2702 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2703
2704 /* Ensure minimum (required) set of control bits are supported. */
2705 if (ctl_min & ~ctl)
002c7f7c 2706 return -EIO;
1c3d14fe
YS		 2707
2708 *result = ctl;
2709 return 0;
2710}
2711
110312c8
AK		 2712static __init bool allow_1_setting(u32 msr, u32 ctl)
2713{
2714 u32 vmx_msr_low, vmx_msr_high;
2715
2716 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2717 return vmx_msr_high & ctl;
2718}
2719
002c7f7c 2720static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2721{
2722 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2723 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2724 u32 _pin_based_exec_control = 0;
2725 u32 _cpu_based_exec_control = 0;
f78e0e2e 2726 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2727 u32 _vmexit_control = 0;
2728 u32 _vmentry_control = 0;
2729
10166744 2730 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2731#ifdef CONFIG_X86_64
2732 CPU_BASED_CR8_LOAD_EXITING |
2733 CPU_BASED_CR8_STORE_EXITING |
2734#endif
d56f546d
SY		 2735 CPU_BASED_CR3_LOAD_EXITING |
2736 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2737 CPU_BASED_USE_IO_BITMAPS |
2738 CPU_BASED_MOV_DR_EXITING |
a7052897 2739 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2740 CPU_BASED_MWAIT_EXITING |
2741 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2742 CPU_BASED_INVLPG_EXITING |
2743 CPU_BASED_RDPMC_EXITING;
443381a8 2744
f78e0e2e 2745 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2746 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2747 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2748 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2749 &_cpu_based_exec_control) < 0)
002c7f7c 2750 return -EIO;
6e5d865c
YS		 2751#ifdef CONFIG_X86_64
2752 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2753 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2754 ~CPU_BASED_CR8_STORE_EXITING;
2755#endif
f78e0e2e 2756 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2757 min2 = 0;
2758 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2759 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2760 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2761 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2762 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2763 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2764 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2765 SECONDARY_EXEC_RDTSCP |
83d4c286 2766 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2767 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2768 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2769 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2770 if (adjust_vmx_controls(min2, opt2,
2771 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2772 &_cpu_based_2nd_exec_control) < 0)
2773 return -EIO;
2774 }
2775#ifndef CONFIG_X86_64
2776 if (!(_cpu_based_2nd_exec_control &
2777 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2778 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2779#endif
83d4c286
YZ		 2780
2781 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2782 _cpu_based_2nd_exec_control &= ~(
8d14695f 2783 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2784 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2785 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2786
d56f546d 2787 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2788 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2789 enabled */
5fff7d27
GN		 2790 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2791 CPU_BASED_CR3_STORE_EXITING |
2792 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2793 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2794 vmx_capability.ept, vmx_capability.vpid);
2795 }
1c3d14fe
YS		 2796
2797 min = 0;
2798#ifdef CONFIG_X86_64
2799 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2800#endif
a547c6db
YZ		 2801 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2802 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2803 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2804 &_vmexit_control) < 0)
002c7f7c 2805 return -EIO;
1c3d14fe 2806
01e439be
YZ		 2807 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2808 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2809 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2810 &_pin_based_exec_control) < 0)
2811 return -EIO;
2812
2813 if (!(_cpu_based_2nd_exec_control &
2814 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2815 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2816 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2817
468d472f
SY		 2818 min = 0;
2819 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2820 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2821 &_vmentry_control) < 0)
002c7f7c 2822 return -EIO;
6aa8b732 2823
c68876fd 2824 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2825
2826 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2827 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2828 return -EIO;
1c3d14fe
YS		 2829
2830#ifdef CONFIG_X86_64
2831 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2832 if (vmx_msr_high & (1u<<16))
002c7f7c 2833 return -EIO;
1c3d14fe
YS		 2834#endif
2835
2836 /* Require Write-Back (WB) memory type for VMCS accesses. */
2837 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2838 return -EIO;
1c3d14fe 2839
002c7f7c
YS		 2840 vmcs_conf->size = vmx_msr_high & 0x1fff;
2841 vmcs_conf->order = get_order(vmcs_config.size);
2842 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2843
002c7f7c
YS		 2844 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2845 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2846 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2847 vmcs_conf->vmexit_ctrl = _vmexit_control;
2848 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2849
110312c8
AK		 2850 cpu_has_load_ia32_efer =
2851 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2852 VM_ENTRY_LOAD_IA32_EFER)
2853 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2854 VM_EXIT_LOAD_IA32_EFER);
2855
8bf00a52
GN		 2856 cpu_has_load_perf_global_ctrl =
2857 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2858 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2859 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2860 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2861
2862 /*
2863 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2864 * but due to arrata below it can't be used. Workaround is to use
2865 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2866 *
2867 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2868 *
2869 * AAK155 (model 26)
2870 * AAP115 (model 30)
2871 * AAT100 (model 37)
2872 * BC86,AAY89,BD102 (model 44)
2873 * BA97 (model 46)
2874 *
2875 */
2876 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2877 switch (boot_cpu_data.x86_model) {
2878 case 26:
2879 case 30:
2880 case 37:
2881 case 44:
2882 case 46:
2883 cpu_has_load_perf_global_ctrl = false;
2884 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2885 "does not work properly. Using workaround\n");
2886 break;
2887 default:
2888 break;
2889 }
2890 }
2891
1c3d14fe 2892 return 0;
c68876fd 2893}
6aa8b732
AK		 2894
2895static struct vmcs *alloc_vmcs_cpu(int cpu)
2896{
2897 int node = cpu_to_node(cpu);
2898 struct page *pages;
2899 struct vmcs *vmcs;
2900
6484eb3e 2901 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2902 if (!pages)
2903 return NULL;
2904 vmcs = page_address(pages);
1c3d14fe
YS		 2905 memset(vmcs, 0, vmcs_config.size);
2906 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2907 return vmcs;
2908}
2909
2910static struct vmcs *alloc_vmcs(void)
2911{
d3b2c338 2912 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2913}
2914
2915static void free_vmcs(struct vmcs *vmcs)
2916{
1c3d14fe 2917 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2918}
2919
d462b819
NHE		 2920/*
2921 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2922 */
2923static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2924{
2925 if (!loaded_vmcs->vmcs)
2926 return;
2927 loaded_vmcs_clear(loaded_vmcs);
2928 free_vmcs(loaded_vmcs->vmcs);
2929 loaded_vmcs->vmcs = NULL;
2930}
2931
39959588 2932static void free_kvm_area(void)
6aa8b732
AK		 2933{
2934 int cpu;
2935
3230bb47 2936 for_each_possible_cpu(cpu) {
6aa8b732 2937 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2938 per_cpu(vmxarea, cpu) = NULL;
2939 }
6aa8b732
AK		 2940}
2941
6aa8b732
AK		 2942static __init int alloc_kvm_area(void)
2943{
2944 int cpu;
2945
3230bb47 2946 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2947 struct vmcs *vmcs;
2948
2949 vmcs = alloc_vmcs_cpu(cpu);
2950 if (!vmcs) {
2951 free_kvm_area();
2952 return -ENOMEM;
2953 }
2954
2955 per_cpu(vmxarea, cpu) = vmcs;
2956 }
2957 return 0;
2958}
2959
2960static __init int hardware_setup(void)
2961{
002c7f7c
YS		 2962 if (setup_vmcs_config(&vmcs_config) < 0)
2963 return -EIO;
50a37eb4
JR		 2964
2965 if (boot_cpu_has(X86_FEATURE_NX))
2966 kvm_enable_efer_bits(EFER_NX);
2967
93ba03c2
SY		 2968 if (!cpu_has_vmx_vpid())
2969 enable_vpid = 0;
abc4fc58
AG		 2970 if (!cpu_has_vmx_shadow_vmcs())
2971 enable_shadow_vmcs = 0;
93ba03c2 2972
4bc9b982
SY		 2973 if (!cpu_has_vmx_ept() ||
2974 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2975 enable_ept = 0;
3a624e29 2976 enable_unrestricted_guest = 0;
83c3a331 2977 enable_ept_ad_bits = 0;
3a624e29
NK		 2978 }
2979
83c3a331
XH		 2980 if (!cpu_has_vmx_ept_ad_bits())
2981 enable_ept_ad_bits = 0;
2982
3a624e29
NK		 2983 if (!cpu_has_vmx_unrestricted_guest())
2984 enable_unrestricted_guest = 0;
93ba03c2
SY		 2985
2986 if (!cpu_has_vmx_flexpriority())
2987 flexpriority_enabled = 0;
2988
95ba8273
GN		 2989 if (!cpu_has_vmx_tpr_shadow())
2990 kvm_x86_ops->update_cr8_intercept = NULL;
2991
54dee993
MT		 2992 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2993 kvm_disable_largepages();
2994
4b8d54f9
ZE		 2995 if (!cpu_has_vmx_ple())
2996 ple_gap = 0;
2997
01e439be
YZ		 2998 if (!cpu_has_vmx_apicv())
2999 enable_apicv = 0;
c7c9c56c 3000
01e439be 3001 if (enable_apicv)
c7c9c56c 3002 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3003 else {
c7c9c56c 3004 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3005 kvm_x86_ops->deliver_posted_interrupt = NULL;
3006 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3007 }
83d4c286 3008
b87a51ae
NHE		 3009 if (nested)
3010 nested_vmx_setup_ctls_msrs();
3011
6aa8b732
AK		 3012 return alloc_kvm_area();
3013}
3014
3015static __exit void hardware_unsetup(void)
3016{
3017 free_kvm_area();
3018}
3019
14168786
GN		 3020static bool emulation_required(struct kvm_vcpu *vcpu)
3021{
3022 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3023}
3024
91b0aa2c 3025static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3026 struct kvm_segment *save)
6aa8b732 3027{
d99e4152
GN		 3028 if (!emulate_invalid_guest_state) {
3029 /*
3030 * CS and SS RPL should be equal during guest entry according
3031 * to VMX spec, but in reality it is not always so. Since vcpu
3032 * is in the middle of the transition from real mode to
3033 * protected mode it is safe to assume that RPL 0 is a good
3034 * default value.
3035 */
3036 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3037 save->selector &= ~SELECTOR_RPL_MASK;
3038 save->dpl = save->selector & SELECTOR_RPL_MASK;
3039 save->s = 1;
6aa8b732 3040 }
d99e4152 3041 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3042}
3043
3044static void enter_pmode(struct kvm_vcpu *vcpu)
3045{
3046 unsigned long flags;
a89a8fb9 3047 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3048
d99e4152
GN		 3049 /*
3050 * Update real mode segment cache. It may be not up-to-date if sement
3051 * register was written while vcpu was in a guest mode.
3052 */
3053 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3054 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3055 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3056 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3057 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3058 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3059
7ffd92c5 3060 vmx->rmode.vm86_active = 0;
6aa8b732 3061
2fb92db1
AK		 3062 vmx_segment_cache_clear(vmx);
3063
f5f7b2fe 3064 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3065
3066 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3067 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3068 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3069 vmcs_writel(GUEST_RFLAGS, flags);
3070
66aee91a
RR		 3071 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3072 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3073
3074 update_exception_bitmap(vcpu);
3075
91b0aa2c
GN		 3076 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3077 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3078 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3079 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3080 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3081 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3082
3083 /* CPL is always 0 when CPU enters protected mode */
3084 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3085 vmx->cpl = 0;
6aa8b732
AK		 3086}
3087
f5f7b2fe 3088static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3089{
772e0318 3090 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3091 struct kvm_segment var = *save;
3092
3093 var.dpl = 0x3;
3094 if (seg == VCPU_SREG_CS)
3095 var.type = 0x3;
3096
3097 if (!emulate_invalid_guest_state) {
3098 var.selector = var.base >> 4;
3099 var.base = var.base & 0xffff0;
3100 var.limit = 0xffff;
3101 var.g = 0;
3102 var.db = 0;
3103 var.present = 1;
3104 var.s = 1;
3105 var.l = 0;
3106 var.unusable = 0;
3107 var.type = 0x3;
3108 var.avl = 0;
3109 if (save->base & 0xf)
3110 printk_once(KERN_WARNING "kvm: segment base is not "
3111 "paragraph aligned when entering "
3112 "protected mode (seg=%d)", seg);
3113 }
6aa8b732 3114
d99e4152
GN		 3115 vmcs_write16(sf->selector, var.selector);
3116 vmcs_write32(sf->base, var.base);
3117 vmcs_write32(sf->limit, var.limit);
3118 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3119}
3120
3121static void enter_rmode(struct kvm_vcpu *vcpu)
3122{
3123 unsigned long flags;
a89a8fb9 3124 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3125
f5f7b2fe
AK		 3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3129 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3130 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3131 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3132 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3133
7ffd92c5 3134 vmx->rmode.vm86_active = 1;
6aa8b732 3135
776e58ea
GN		 3136 /*
3137 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3138 * vcpu. Warn the user that an update is overdue.
776e58ea 3139 */
4918c6ca 3140 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3141 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3142 "called before entering vcpu\n");
776e58ea 3143
2fb92db1
AK		 3144 vmx_segment_cache_clear(vmx);
3145
4918c6ca 3146 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3147 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3148 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3149
3150 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3151 vmx->rmode.save_rflags = flags;
6aa8b732 3152
053de044 3153 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3154
3155 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3156 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3157 update_exception_bitmap(vcpu);
3158
d99e4152
GN		 3159 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3160 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3161 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3162 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3163 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3164 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3165
8668a3c4 3166 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3167}
3168
401d10de
AS		 3169static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3170{
3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3172 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3173
3174 if (!msr)
3175 return;
401d10de 3176
44ea2b17
AK		 3177 /*
3178 * Force kernel_gs_base reloading before EFER changes, as control
3179 * of this msr depends on is_long_mode().
3180 */
3181 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3182 vcpu->arch.efer = efer;
401d10de
AS		 3183 if (efer & EFER_LMA) {
3184 vmcs_write32(VM_ENTRY_CONTROLS,
3185 vmcs_read32(VM_ENTRY_CONTROLS) |
3186 VM_ENTRY_IA32E_MODE);
3187 msr->data = efer;
3188 } else {
3189 vmcs_write32(VM_ENTRY_CONTROLS,
3190 vmcs_read32(VM_ENTRY_CONTROLS) &
3191 ~VM_ENTRY_IA32E_MODE);
3192
3193 msr->data = efer & ~EFER_LME;
3194 }
3195 setup_msrs(vmx);
3196}
3197
05b3e0c2 3198#ifdef CONFIG_X86_64
6aa8b732
AK		 3199
3200static void enter_lmode(struct kvm_vcpu *vcpu)
3201{
3202 u32 guest_tr_ar;
3203
2fb92db1
AK		 3204 vmx_segment_cache_clear(to_vmx(vcpu));
3205
6aa8b732
AK		 3206 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3207 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3208 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3209 __func__);
6aa8b732
AK		 3210 vmcs_write32(GUEST_TR_AR_BYTES,
3211 (guest_tr_ar & ~AR_TYPE_MASK)
3212 | AR_TYPE_BUSY_64_TSS);
3213 }
da38f438 3214 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3215}
3216
3217static void exit_lmode(struct kvm_vcpu *vcpu)
3218{
6aa8b732
AK		 3219 vmcs_write32(VM_ENTRY_CONTROLS,
3220 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3221 & ~VM_ENTRY_IA32E_MODE);
da38f438 3222 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3223}
3224
3225#endif
3226
2384d2b3
SY		 3227static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3228{
b9d762fa 3229 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3230 if (enable_ept) {
3231 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3232 return;
4e1096d2 3233 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3234 }
2384d2b3
SY		 3235}
3236
e8467fda
AK		 3237static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3238{
3239 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3240
3241 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3242 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3243}
3244
aff48baa
AK		 3245static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3246{
3247 if (enable_ept && is_paging(vcpu))
3248 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3249 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3250}
3251
25c4c276 3252static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3253{
fc78f519
AK		 3254 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3255
3256 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3257 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3258}
3259
1439442c
SY		 3260static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3261{
d0d538b9
GN		 3262 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3263
6de4f3ad
AK		 3264 if (!test_bit(VCPU_EXREG_PDPTR,
3265 (unsigned long *)&vcpu->arch.regs_dirty))
3266 return;
3267
1439442c 3268 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3269 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3270 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3271 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3272 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3273 }
3274}
3275
8f5d549f
AK		 3276static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3277{
d0d538b9
GN		 3278 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3279
8f5d549f 3280 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3281 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3282 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3283 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3284 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3285 }
6de4f3ad
AK		 3286
3287 __set_bit(VCPU_EXREG_PDPTR,
3288 (unsigned long *)&vcpu->arch.regs_avail);
3289 __set_bit(VCPU_EXREG_PDPTR,
3290 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3291}
3292
5e1746d6 3293static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3294
3295static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3296 unsigned long cr0,
3297 struct kvm_vcpu *vcpu)
3298{
5233dd51
MT		 3299 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3300 vmx_decache_cr3(vcpu);
1439442c
SY		 3301 if (!(cr0 & X86_CR0_PG)) {
3302 /* From paging/starting to nonpaging */
3303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3304 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3305 (CPU_BASED_CR3_LOAD_EXITING |
3306 CPU_BASED_CR3_STORE_EXITING));
3307 vcpu->arch.cr0 = cr0;
fc78f519 3308 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3309 } else if (!is_paging(vcpu)) {
3310 /* From nonpaging to paging */
3311 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3312 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3313 ~(CPU_BASED_CR3_LOAD_EXITING |
3314 CPU_BASED_CR3_STORE_EXITING));
3315 vcpu->arch.cr0 = cr0;
fc78f519 3316 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3317 }
95eb84a7
SY		 3318
3319 if (!(cr0 & X86_CR0_WP))
3320 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3321}
3322
6aa8b732
AK		 3323static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3324{
7ffd92c5 3325 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3326 unsigned long hw_cr0;
3327
5037878e 3328 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3329 if (enable_unrestricted_guest)
5037878e 3330 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3331 else {
5037878e 3332 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3333
218e763f
GN		 3334 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3335 enter_pmode(vcpu);
6aa8b732 3336
218e763f
GN		 3337 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3338 enter_rmode(vcpu);
3339 }
6aa8b732 3340
05b3e0c2 3341#ifdef CONFIG_X86_64
f6801dff 3342 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3343 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3344 enter_lmode(vcpu);
707d92fa 3345 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3346 exit_lmode(vcpu);
3347 }
3348#endif
3349
089d034e 3350 if (enable_ept)
1439442c
SY		 3351 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3352
02daab21 3353 if (!vcpu->fpu_active)
81231c69 3354 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3355
6aa8b732 3356 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3357 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3358 vcpu->arch.cr0 = cr0;
14168786
GN		 3359
3360 /* depends on vcpu->arch.cr0 to be set to a new value */
3361 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3362}
3363
1439442c
SY		 3364static u64 construct_eptp(unsigned long root_hpa)
3365{
3366 u64 eptp;
3367
3368 /* TODO write the value reading from MSR */
3369 eptp = VMX_EPT_DEFAULT_MT |
3370 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3371 if (enable_ept_ad_bits)
3372 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3373 eptp |= (root_hpa & PAGE_MASK);
3374
3375 return eptp;
3376}
3377
6aa8b732
AK		 3378static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3379{
1439442c
SY		 3380 unsigned long guest_cr3;
3381 u64 eptp;
3382
3383 guest_cr3 = cr3;
089d034e 3384 if (enable_ept) {
1439442c
SY		 3385 eptp = construct_eptp(cr3);
3386 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3387 if (is_paging(vcpu) || is_guest_mode(vcpu))
3388 guest_cr3 = kvm_read_cr3(vcpu);
3389 else
3390 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3391 ept_load_pdptrs(vcpu);
1439442c
SY		 3392 }
3393
2384d2b3 3394 vmx_flush_tlb(vcpu);
1439442c 3395 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3396}
3397
5e1746d6 3398static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3399{
7ffd92c5 3400 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3401 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3402
5e1746d6
NHE		 3403 if (cr4 & X86_CR4_VMXE) {
3404 /*
3405 * To use VMXON (and later other VMX instructions), a guest
3406 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3407 * So basically the check on whether to allow nested VMX
3408 * is here.
3409 */
3410 if (!nested_vmx_allowed(vcpu))
3411 return 1;
1a0d74e6
JK		 3412 }
3413 if (to_vmx(vcpu)->nested.vmxon &&
3414 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3415 return 1;
3416
ad312c7c 3417 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3418 if (enable_ept) {
3419 if (!is_paging(vcpu)) {
3420 hw_cr4 &= ~X86_CR4_PAE;
3421 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3422 /*
3423 * SMEP is disabled if CPU is in non-paging mode in
3424 * hardware. However KVM always uses paging mode to
3425 * emulate guest non-paging mode with TDP.
3426 * To emulate this behavior, SMEP needs to be manually
3427 * disabled when guest switches to non-paging mode.
3428 */
3429 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3430 } else if (!(cr4 & X86_CR4_PAE)) {
3431 hw_cr4 &= ~X86_CR4_PAE;
3432 }
3433 }
1439442c
SY		 3434
3435 vmcs_writel(CR4_READ_SHADOW, cr4);
3436 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3437 return 0;
6aa8b732
AK		 3438}
3439
6aa8b732
AK		 3440static void vmx_get_segment(struct kvm_vcpu *vcpu,
3441 struct kvm_segment *var, int seg)
3442{
a9179499 3443 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3444 u32 ar;
3445
c6ad1153 3446 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3447 *var = vmx->rmode.segs[seg];
a9179499 3448 if (seg == VCPU_SREG_TR
2fb92db1 3449 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3450 return;
1390a28b
AK		 3451 var->base = vmx_read_guest_seg_base(vmx, seg);
3452 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3453 return;
a9179499 3454 }
2fb92db1
AK		 3455 var->base = vmx_read_guest_seg_base(vmx, seg);
3456 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3457 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3458 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3459 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3460 var->type = ar & 15;
3461 var->s = (ar >> 4) & 1;
3462 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3463 /*
3464 * Some userspaces do not preserve unusable property. Since usable
3465 * segment has to be present according to VMX spec we can use present
3466 * property to amend userspace bug by making unusable segment always
3467 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3468 * segment as unusable.
3469 */
3470 var->present = !var->unusable;
6aa8b732
AK		 3471 var->avl = (ar >> 12) & 1;
3472 var->l = (ar >> 13) & 1;
3473 var->db = (ar >> 14) & 1;
3474 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3475}
3476
a9179499
AK		 3477static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3478{
a9179499
AK		 3479 struct kvm_segment s;
3480
3481 if (to_vmx(vcpu)->rmode.vm86_active) {
3482 vmx_get_segment(vcpu, &s, seg);
3483 return s.base;
3484 }
2fb92db1 3485 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3486}
3487
b09408d0 3488static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3489{
b09408d0
MT		 3490 struct vcpu_vmx *vmx = to_vmx(vcpu);
3491
3eeb3288 3492 if (!is_protmode(vcpu))
2e4d2653
IE		 3493 return 0;
3494
f4c63e5d
AK		 3495 if (!is_long_mode(vcpu)
3496 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3497 return 3;
3498
69c73028
AK		 3499 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3500 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3501 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3502 }
d881e6f6
AK		 3503
3504 return vmx->cpl;
69c73028
AK		 3505}
3506
3507
653e3108 3508static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3509{
6aa8b732
AK		 3510 u32 ar;
3511
f0495f9b 3512 if (var->unusable || !var->present)
6aa8b732
AK		 3513 ar = 1 << 16;
3514 else {
3515 ar = var->type & 15;
3516 ar |= (var->s & 1) << 4;
3517 ar |= (var->dpl & 3) << 5;
3518 ar |= (var->present & 1) << 7;
3519 ar |= (var->avl & 1) << 12;
3520 ar |= (var->l & 1) << 13;
3521 ar |= (var->db & 1) << 14;
3522 ar |= (var->g & 1) << 15;
3523 }
653e3108
AK		 3524
3525 return ar;
3526}
3527
3528static void vmx_set_segment(struct kvm_vcpu *vcpu,
3529 struct kvm_segment *var, int seg)
3530{
7ffd92c5 3531 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3532 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3533
2fb92db1 3534 vmx_segment_cache_clear(vmx);
2f143240
GN		 3535 if (seg == VCPU_SREG_CS)
3536 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3537
1ecd50a9
GN		 3538 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3539 vmx->rmode.segs[seg] = *var;
3540 if (seg == VCPU_SREG_TR)
3541 vmcs_write16(sf->selector, var->selector);
3542 else if (var->s)
3543 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3544 goto out;
653e3108 3545 }
1ecd50a9 3546
653e3108
AK		 3547 vmcs_writel(sf->base, var->base);
3548 vmcs_write32(sf->limit, var->limit);
3549 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3550
3551 /*
3552 * Fix the "Accessed" bit in AR field of segment registers for older
3553 * qemu binaries.
3554 * IA32 arch specifies that at the time of processor reset the
3555 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3556 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3557 * state vmexit when "unrestricted guest" mode is turned on.
3558 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3559 * tree. Newer qemu binaries with that qemu fix would not need this
3560 * kvm hack.
3561 */
3562 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3563 var->type |= 0x1; /* Accessed */
3a624e29 3564
f924d66d 3565 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3566
3567out:
14168786 3568 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3569}
3570
6aa8b732
AK		 3571static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3572{
2fb92db1 3573 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3574
3575 *db = (ar >> 14) & 1;
3576 *l = (ar >> 13) & 1;
3577}
3578
89a27f4d 3579static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3580{
89a27f4d
GN		 3581 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3582 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3583}
3584
89a27f4d 3585static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3586{
89a27f4d
GN		 3587 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3588 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3589}
3590
89a27f4d 3591static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3592{
89a27f4d
GN		 3593 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3594 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3595}
3596
89a27f4d 3597static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3598{
89a27f4d
GN		 3599 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3600 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3601}
3602
648dfaa7
MG		 3603static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3604{
3605 struct kvm_segment var;
3606 u32 ar;
3607
3608 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3609 var.dpl = 0x3;
0647f4aa
GN		 3610 if (seg == VCPU_SREG_CS)
3611 var.type = 0x3;
648dfaa7
MG		 3612 ar = vmx_segment_access_rights(&var);
3613
3614 if (var.base != (var.selector << 4))
3615 return false;
89efbed0 3616 if (var.limit != 0xffff)
648dfaa7 3617 return false;
07f42f5f 3618 if (ar != 0xf3)
648dfaa7
MG		 3619 return false;
3620
3621 return true;
3622}
3623
3624static bool code_segment_valid(struct kvm_vcpu *vcpu)
3625{
3626 struct kvm_segment cs;
3627 unsigned int cs_rpl;
3628
3629 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3630 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3631
1872a3f4
AK		 3632 if (cs.unusable)
3633 return false;
648dfaa7
MG		 3634 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3635 return false;
3636 if (!cs.s)
3637 return false;
1872a3f4 3638 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3639 if (cs.dpl > cs_rpl)
3640 return false;
1872a3f4 3641 } else {
648dfaa7
MG		 3642 if (cs.dpl != cs_rpl)
3643 return false;
3644 }
3645 if (!cs.present)
3646 return false;
3647
3648 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3649 return true;
3650}
3651
3652static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3653{
3654 struct kvm_segment ss;
3655 unsigned int ss_rpl;
3656
3657 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3658 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3659
1872a3f4
AK		 3660 if (ss.unusable)
3661 return true;
3662 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3663 return false;
3664 if (!ss.s)
3665 return false;
3666 if (ss.dpl != ss_rpl) /* DPL != RPL */
3667 return false;
3668 if (!ss.present)
3669 return false;
3670
3671 return true;
3672}
3673
3674static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3675{
3676 struct kvm_segment var;
3677 unsigned int rpl;
3678
3679 vmx_get_segment(vcpu, &var, seg);
3680 rpl = var.selector & SELECTOR_RPL_MASK;
3681
1872a3f4
AK		 3682 if (var.unusable)
3683 return true;
648dfaa7
MG		 3684 if (!var.s)
3685 return false;
3686 if (!var.present)
3687 return false;
3688 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3689 if (var.dpl < rpl) /* DPL < RPL */
3690 return false;
3691 }
3692
3693 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3694 * rights flags
3695 */
3696 return true;
3697}
3698
3699static bool tr_valid(struct kvm_vcpu *vcpu)
3700{
3701 struct kvm_segment tr;
3702
3703 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3704
1872a3f4
AK		 3705 if (tr.unusable)
3706 return false;
648dfaa7
MG		 3707 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3708 return false;
1872a3f4 3709 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3710 return false;
3711 if (!tr.present)
3712 return false;
3713
3714 return true;
3715}
3716
3717static bool ldtr_valid(struct kvm_vcpu *vcpu)
3718{
3719 struct kvm_segment ldtr;
3720
3721 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3722
1872a3f4
AK		 3723 if (ldtr.unusable)
3724 return true;
648dfaa7
MG		 3725 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3726 return false;
3727 if (ldtr.type != 2)
3728 return false;
3729 if (!ldtr.present)
3730 return false;
3731
3732 return true;
3733}
3734
3735static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3736{
3737 struct kvm_segment cs, ss;
3738
3739 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3740 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3741
3742 return ((cs.selector & SELECTOR_RPL_MASK) ==
3743 (ss.selector & SELECTOR_RPL_MASK));
3744}
3745
3746/*
3747 * Check if guest state is valid. Returns true if valid, false if
3748 * not.
3749 * We assume that registers are always usable
3750 */
3751static bool guest_state_valid(struct kvm_vcpu *vcpu)
3752{
c5e97c80
GN		 3753 if (enable_unrestricted_guest)
3754 return true;
3755
648dfaa7 3756 /* real mode guest state checks */
f13882d8 3757 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3758 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3759 return false;
3760 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3761 return false;
3762 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3763 return false;
3764 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3765 return false;
3766 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3767 return false;
3768 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3769 return false;
3770 } else {
3771 /* protected mode guest state checks */
3772 if (!cs_ss_rpl_check(vcpu))
3773 return false;
3774 if (!code_segment_valid(vcpu))
3775 return false;
3776 if (!stack_segment_valid(vcpu))
3777 return false;
3778 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3779 return false;
3780 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3781 return false;
3782 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3783 return false;
3784 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3785 return false;
3786 if (!tr_valid(vcpu))
3787 return false;
3788 if (!ldtr_valid(vcpu))
3789 return false;
3790 }
3791 /* TODO:
3792 * - Add checks on RIP
3793 * - Add checks on RFLAGS
3794 */
3795
3796 return true;
3797}
3798
d77c26fc 3799static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3800{
40dcaa9f 3801 gfn_t fn;
195aefde 3802 u16 data = 0;
40dcaa9f 3803 int r, idx, ret = 0;
6aa8b732 3804
40dcaa9f 3805 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3806 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3807 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3808 if (r < 0)
10589a46 3809 goto out;
195aefde 3810 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3811 r = kvm_write_guest_page(kvm, fn++, &data,
3812 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3813 if (r < 0)
10589a46 3814 goto out;
195aefde
IE		 3815 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3816 if (r < 0)
10589a46 3817 goto out;
195aefde
IE		 3818 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3819 if (r < 0)
10589a46 3820 goto out;
195aefde 3821 data = ~0;
10589a46
MT		 3822 r = kvm_write_guest_page(kvm, fn, &data,
3823 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3824 sizeof(u8));
195aefde 3825 if (r < 0)
10589a46
MT		 3826 goto out;
3827
3828 ret = 1;
3829out:
40dcaa9f 3830 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3831 return ret;
6aa8b732
AK		 3832}
3833
b7ebfb05
SY		 3834static int init_rmode_identity_map(struct kvm *kvm)
3835{
40dcaa9f 3836 int i, idx, r, ret;
b7ebfb05
SY		 3837 pfn_t identity_map_pfn;
3838 u32 tmp;
3839
089d034e 3840 if (!enable_ept)
b7ebfb05
SY		 3841 return 1;
3842 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3843 printk(KERN_ERR "EPT: identity-mapping pagetable "
3844 "haven't been allocated!\n");
3845 return 0;
3846 }
3847 if (likely(kvm->arch.ept_identity_pagetable_done))
3848 return 1;
3849 ret = 0;
b927a3ce 3850 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3851 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3852 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3853 if (r < 0)
3854 goto out;
3855 /* Set up identity-mapping pagetable for EPT in real mode */
3856 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3857 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3858 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3859 r = kvm_write_guest_page(kvm, identity_map_pfn,
3860 &tmp, i * sizeof(tmp), sizeof(tmp));
3861 if (r < 0)
3862 goto out;
3863 }
3864 kvm->arch.ept_identity_pagetable_done = true;
3865 ret = 1;
3866out:
40dcaa9f 3867 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3868 return ret;
3869}
3870
6aa8b732
AK		 3871static void seg_setup(int seg)
3872{
772e0318 3873 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3874 unsigned int ar;
6aa8b732
AK		 3875
3876 vmcs_write16(sf->selector, 0);
3877 vmcs_writel(sf->base, 0);
3878 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3879 ar = 0x93;
3880 if (seg == VCPU_SREG_CS)
3881 ar |= 0x08; /* code segment */
3a624e29
NK		 3882
3883 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3884}
3885
f78e0e2e
SY		 3886static int alloc_apic_access_page(struct kvm *kvm)
3887{
4484141a 3888 struct page *page;
f78e0e2e
SY		 3889 struct kvm_userspace_memory_region kvm_userspace_mem;
3890 int r = 0;
3891
79fac95e 3892 mutex_lock(&kvm->slots_lock);
bfc6d222 3893 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3894 goto out;
3895 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3896 kvm_userspace_mem.flags = 0;
3897 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3898 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3899 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3900 if (r)
3901 goto out;
72dc67a6 3902
4484141a
XG		 3903 page = gfn_to_page(kvm, 0xfee00);
3904 if (is_error_page(page)) {
3905 r = -EFAULT;
3906 goto out;
3907 }
3908
3909 kvm->arch.apic_access_page = page;
f78e0e2e 3910out:
79fac95e 3911 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3912 return r;
3913}
3914
b7ebfb05
SY		 3915static int alloc_identity_pagetable(struct kvm *kvm)
3916{
4484141a 3917 struct page *page;
b7ebfb05
SY		 3918 struct kvm_userspace_memory_region kvm_userspace_mem;
3919 int r = 0;
3920
79fac95e 3921 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3922 if (kvm->arch.ept_identity_pagetable)
3923 goto out;
3924 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3925 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3926 kvm_userspace_mem.guest_phys_addr =
3927 kvm->arch.ept_identity_map_addr;
b7ebfb05 3928 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3929 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3930 if (r)
3931 goto out;
3932
4484141a
XG		 3933 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3934 if (is_error_page(page)) {
3935 r = -EFAULT;
3936 goto out;
3937 }
3938
3939 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3940out:
79fac95e 3941 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3942 return r;
3943}
3944
2384d2b3
SY		 3945static void allocate_vpid(struct vcpu_vmx *vmx)
3946{
3947 int vpid;
3948
3949 vmx->vpid = 0;
919818ab 3950 if (!enable_vpid)
2384d2b3
SY		 3951 return;
3952 spin_lock(&vmx_vpid_lock);
3953 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3954 if (vpid < VMX_NR_VPIDS) {
3955 vmx->vpid = vpid;
3956 __set_bit(vpid, vmx_vpid_bitmap);
3957 }
3958 spin_unlock(&vmx_vpid_lock);
3959}
3960
cdbecfc3
LJ		 3961static void free_vpid(struct vcpu_vmx *vmx)
3962{
3963 if (!enable_vpid)
3964 return;
3965 spin_lock(&vmx_vpid_lock);
3966 if (vmx->vpid != 0)
3967 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3968 spin_unlock(&vmx_vpid_lock);
3969}
3970
8d14695f
YZ		 3971#define MSR_TYPE_R 1
3972#define MSR_TYPE_W 2
3973static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3974 u32 msr, int type)
25c5f225 3975{
3e7c73e9 3976 int f = sizeof(unsigned long);
25c5f225
SY		 3977
3978 if (!cpu_has_vmx_msr_bitmap())
3979 return;
3980
3981 /*
3982 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3983 * have the write-low and read-high bitmap offsets the wrong way round.
3984 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3985 */
25c5f225 3986 if (msr <= 0x1fff) {
8d14695f
YZ		 3987 if (type & MSR_TYPE_R)
3988 /* read-low */
3989 __clear_bit(msr, msr_bitmap + 0x000 / f);
3990
3991 if (type & MSR_TYPE_W)
3992 /* write-low */
3993 __clear_bit(msr, msr_bitmap + 0x800 / f);
3994
25c5f225
SY		 3995 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3996 msr &= 0x1fff;
8d14695f
YZ		 3997 if (type & MSR_TYPE_R)
3998 /* read-high */
3999 __clear_bit(msr, msr_bitmap + 0x400 / f);
4000
4001 if (type & MSR_TYPE_W)
4002 /* write-high */
4003 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4004
4005 }
4006}
4007
4008static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4009 u32 msr, int type)
4010{
4011 int f = sizeof(unsigned long);
4012
4013 if (!cpu_has_vmx_msr_bitmap())
4014 return;
4015
4016 /*
4017 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4018 * have the write-low and read-high bitmap offsets the wrong way round.
4019 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4020 */
4021 if (msr <= 0x1fff) {
4022 if (type & MSR_TYPE_R)
4023 /* read-low */
4024 __set_bit(msr, msr_bitmap + 0x000 / f);
4025
4026 if (type & MSR_TYPE_W)
4027 /* write-low */
4028 __set_bit(msr, msr_bitmap + 0x800 / f);
4029
4030 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4031 msr &= 0x1fff;
4032 if (type & MSR_TYPE_R)
4033 /* read-high */
4034 __set_bit(msr, msr_bitmap + 0x400 / f);
4035
4036 if (type & MSR_TYPE_W)
4037 /* write-high */
4038 __set_bit(msr, msr_bitmap + 0xc00 / f);
4039
25c5f225 4040 }
25c5f225
SY		 4041}
4042
5897297b
AK		 4043static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4044{
4045 if (!longmode_only)
8d14695f
YZ		 4046 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4047 msr, MSR_TYPE_R | MSR_TYPE_W);
4048 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4049 msr, MSR_TYPE_R | MSR_TYPE_W);
4050}
4051
4052static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4053{
4054 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4055 msr, MSR_TYPE_R);
4056 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4057 msr, MSR_TYPE_R);
4058}
4059
4060static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4061{
4062 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4063 msr, MSR_TYPE_R);
4064 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4065 msr, MSR_TYPE_R);
4066}
4067
4068static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4069{
4070 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4071 msr, MSR_TYPE_W);
4072 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4073 msr, MSR_TYPE_W);
5897297b
AK		 4074}
4075
01e439be
YZ		 4076static int vmx_vm_has_apicv(struct kvm *kvm)
4077{
4078 return enable_apicv && irqchip_in_kernel(kvm);
4079}
4080
a20ed54d
YZ		 4081/*
4082 * Send interrupt to vcpu via posted interrupt way.
4083 * 1. If target vcpu is running(non-root mode), send posted interrupt
4084 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4085 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4086 * interrupt from PIR in next vmentry.
4087 */
4088static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4089{
4090 struct vcpu_vmx *vmx = to_vmx(vcpu);
4091 int r;
4092
4093 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4094 return;
4095
4096 r = pi_test_and_set_on(&vmx->pi_desc);
4097 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4098#ifdef CONFIG_SMP
a20ed54d
YZ		 4099 if (!r && (vcpu->mode == IN_GUEST_MODE))
4100 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4101 POSTED_INTR_VECTOR);
4102 else
6ffbbbba 4103#endif
a20ed54d
YZ		 4104 kvm_vcpu_kick(vcpu);
4105}
4106
4107static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4108{
4109 struct vcpu_vmx *vmx = to_vmx(vcpu);
4110
4111 if (!pi_test_and_clear_on(&vmx->pi_desc))
4112 return;
4113
4114 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4115}
4116
4117static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4118{
4119 return;
4120}
4121
a3a8ff8e
NHE		 4122/*
4123 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4124 * will not change in the lifetime of the guest.
4125 * Note that host-state that does change is set elsewhere. E.g., host-state
4126 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4127 */
a547c6db 4128static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4129{
4130 u32 low32, high32;
4131 unsigned long tmpl;
4132 struct desc_ptr dt;
4133
b1a74bf8 4134 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4135 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4136 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4137
4138 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4139#ifdef CONFIG_X86_64
4140 /*
4141 * Load null selectors, so we can avoid reloading them in
4142 * __vmx_load_host_state(), in case userspace uses the null selectors
4143 * too (the expected case).
4144 */
4145 vmcs_write16(HOST_DS_SELECTOR, 0);
4146 vmcs_write16(HOST_ES_SELECTOR, 0);
4147#else
a3a8ff8e
NHE		 4148 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4149 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4150#endif
a3a8ff8e
NHE		 4151 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4152 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4153
4154 native_store_idt(&dt);
4155 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4156 vmx->host_idt_base = dt.address;
a3a8ff8e 4157
83287ea4 4158 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4159
4160 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4161 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4162 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4163 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4164
4165 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4166 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4167 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4168 }
4169}
4170
bf8179a0
NHE		 4171static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4172{
4173 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4174 if (enable_ept)
4175 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4176 if (is_guest_mode(&vmx->vcpu))
4177 vmx->vcpu.arch.cr4_guest_owned_bits &=
4178 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4179 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4180}
4181
01e439be
YZ		 4182static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4183{
4184 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4185
4186 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4187 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4188 return pin_based_exec_ctrl;
4189}
4190
bf8179a0
NHE		 4191static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4192{
4193 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4194 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4195 exec_control &= ~CPU_BASED_TPR_SHADOW;
4196#ifdef CONFIG_X86_64
4197 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4198 CPU_BASED_CR8_LOAD_EXITING;
4199#endif
4200 }
4201 if (!enable_ept)
4202 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4203 CPU_BASED_CR3_LOAD_EXITING |
4204 CPU_BASED_INVLPG_EXITING;
4205 return exec_control;
4206}
4207
4208static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4209{
4210 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4211 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4212 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4213 if (vmx->vpid == 0)
4214 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4215 if (!enable_ept) {
4216 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4217 enable_unrestricted_guest = 0;
ad756a16
MJ		 4218 /* Enable INVPCID for non-ept guests may cause performance regression. */
4219 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4220 }
4221 if (!enable_unrestricted_guest)
4222 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4223 if (!ple_gap)
4224 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4225 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4226 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4227 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4228 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4229 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4230 (handle_vmptrld).
4231 We can NOT enable shadow_vmcs here because we don't have yet
4232 a current VMCS12
4233 */
4234 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4235 return exec_control;
4236}
4237
ce88decf
XG		 4238static void ept_set_mmio_spte_mask(void)
4239{
4240 /*
4241 * EPT Misconfigurations can be generated if the value of bits 2:0
4242 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4243 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4244 * spte.
4245 */
885032b9 4246 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4247}
4248
6aa8b732
AK		 4249/*
4250 * Sets up the vmcs for emulated real mode.
4251 */
8b9cf98c 4252static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4253{
2e4ce7f5 4254#ifdef CONFIG_X86_64
6aa8b732 4255 unsigned long a;
2e4ce7f5 4256#endif
6aa8b732 4257 int i;
6aa8b732 4258
6aa8b732 4259 /* I/O */
3e7c73e9
AK		 4260 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4261 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4262
4607c2d7
AG		 4263 if (enable_shadow_vmcs) {
4264 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4265 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4266 }
25c5f225 4267 if (cpu_has_vmx_msr_bitmap())
5897297b 4268 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4269
6aa8b732
AK		 4270 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4271
6aa8b732 4272 /* Control */
01e439be 4273 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4274
bf8179a0 4275 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4276
83ff3b9d 4277 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4278 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4279 vmx_secondary_exec_control(vmx));
83ff3b9d 4280 }
f78e0e2e 4281
01e439be 4282 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4283 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4284 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4285 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4286 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4287
4288 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4289
4290 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4291 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4292 }
4293
4b8d54f9
ZE		 4294 if (ple_gap) {
4295 vmcs_write32(PLE_GAP, ple_gap);
4296 vmcs_write32(PLE_WINDOW, ple_window);
4297 }
4298
c3707958
XG		 4299 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4300 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4301 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4302
9581d442
AK		 4303 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4304 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4305 vmx_set_constant_host_state(vmx);
05b3e0c2 4306#ifdef CONFIG_X86_64
6aa8b732
AK		 4307 rdmsrl(MSR_FS_BASE, a);
4308 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4309 rdmsrl(MSR_GS_BASE, a);
4310 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4311#else
4312 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4313 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4314#endif
4315
2cc51560
ED		 4316 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4317 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4318 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4319 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4320 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4321
468d472f 4322 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4323 u32 msr_low, msr_high;
4324 u64 host_pat;
468d472f
SY		 4325 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4326 host_pat = msr_low | ((u64) msr_high << 32);
4327 /* Write the default value follow host pat */
4328 vmcs_write64(GUEST_IA32_PAT, host_pat);
4329 /* Keep arch.pat sync with GUEST_IA32_PAT */
4330 vmx->vcpu.arch.pat = host_pat;
4331 }
4332
6aa8b732
AK		 4333 for (i = 0; i < NR_VMX_MSR; ++i) {
4334 u32 index = vmx_msr_index[i];
4335 u32 data_low, data_high;
a2fa3e9f 4336 int j = vmx->nmsrs;
6aa8b732
AK		 4337
4338 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4339 continue;
432bd6cb
AK		 4340 if (wrmsr_safe(index, data_low, data_high) < 0)
4341 continue;
26bb0981
AK		 4342 vmx->guest_msrs[j].index = i;
4343 vmx->guest_msrs[j].data = 0;
d5696725 4344 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4345 ++vmx->nmsrs;
6aa8b732 4346 }
6aa8b732 4347
1c3d14fe 4348 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4349
4350 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4351 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4352
e00c8cf2 4353 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4354 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4355
4356 return 0;
4357}
4358
57f252f2 4359static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4360{
4361 struct vcpu_vmx *vmx = to_vmx(vcpu);
4362 u64 msr;
e00c8cf2 4363
7ffd92c5 4364 vmx->rmode.vm86_active = 0;
e00c8cf2 4365
3b86cd99
JK		 4366 vmx->soft_vnmi_blocked = 0;
4367
ad312c7c 4368 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4369 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4370 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4371 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4372 msr |= MSR_IA32_APICBASE_BSP;
4373 kvm_set_apic_base(&vmx->vcpu, msr);
4374
2fb92db1
AK		 4375 vmx_segment_cache_clear(vmx);
4376
5706be0d 4377 seg_setup(VCPU_SREG_CS);
66450a21 4378 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4379 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4380
4381 seg_setup(VCPU_SREG_DS);
4382 seg_setup(VCPU_SREG_ES);
4383 seg_setup(VCPU_SREG_FS);
4384 seg_setup(VCPU_SREG_GS);
4385 seg_setup(VCPU_SREG_SS);
4386
4387 vmcs_write16(GUEST_TR_SELECTOR, 0);
4388 vmcs_writel(GUEST_TR_BASE, 0);
4389 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4390 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4391
4392 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4393 vmcs_writel(GUEST_LDTR_BASE, 0);
4394 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4395 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4396
4397 vmcs_write32(GUEST_SYSENTER_CS, 0);
4398 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4399 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4400
4401 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4402 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4403
e00c8cf2
AK		 4404 vmcs_writel(GUEST_GDTR_BASE, 0);
4405 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4406
4407 vmcs_writel(GUEST_IDTR_BASE, 0);
4408 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4409
443381a8 4410 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4411 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4412 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4413
e00c8cf2
AK		 4414 /* Special registers */
4415 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4416
4417 setup_msrs(vmx);
4418
6aa8b732
AK		 4419 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4420
f78e0e2e
SY		 4421 if (cpu_has_vmx_tpr_shadow()) {
4422 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4423 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4424 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4425 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4426 vmcs_write32(TPR_THRESHOLD, 0);
4427 }
4428
4429 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4430 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4431 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4432
01e439be
YZ		 4433 if (vmx_vm_has_apicv(vcpu->kvm))
4434 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4435
2384d2b3
SY		 4436 if (vmx->vpid != 0)
4437 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4438
fa40052c 4439 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4440 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4441 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4442 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4443 vmx_fpu_activate(&vmx->vcpu);
4444 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4445
b9d762fa 4446 vpid_sync_context(vmx);
6aa8b732
AK		 4447}
4448
b6f1250e
NHE		 4449/*
4450 * In nested virtualization, check if L1 asked to exit on external interrupts.
4451 * For most existing hypervisors, this will always return true.
4452 */
4453static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4454{
4455 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4456 PIN_BASED_EXT_INTR_MASK;
4457}
4458
ea8ceb83
JK		 4459static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4460{
4461 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4462 PIN_BASED_NMI_EXITING;
4463}
4464
730dca42 4465static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4466{
4467 u32 cpu_based_vm_exec_control;
730dca42
JK		 4468
4469 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4470 /*
4471 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4472 * inject to L1 now because L2 must run. The caller will have
4473 * to make L2 exit right after entry, so we can inject to L1
4474 * more promptly.
b6f1250e 4475 */
730dca42 4476 return -EBUSY;
3b86cd99
JK		 4477
4478 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4479 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4480 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4481 return 0;
3b86cd99
JK		 4482}
4483
03b28f81 4484static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4485{
4486 u32 cpu_based_vm_exec_control;
4487
03b28f81
JK		 4488 if (!cpu_has_virtual_nmis())
4489 return enable_irq_window(vcpu);
4490
4491 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4492 return enable_irq_window(vcpu);
3b86cd99
JK		 4493
4494 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4495 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4496 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4497 return 0;
3b86cd99
JK		 4498}
4499
66fd3f7f 4500static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4501{
9c8cba37 4502 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4503 uint32_t intr;
4504 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4505
229456fc 4506 trace_kvm_inj_virq(irq);
2714d1d3 4507
fa89a817 4508 ++vcpu->stat.irq_injections;
7ffd92c5 4509 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4510 int inc_eip = 0;
4511 if (vcpu->arch.interrupt.soft)
4512 inc_eip = vcpu->arch.event_exit_inst_len;
4513 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4514 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4515 return;
4516 }
66fd3f7f
GN		 4517 intr = irq | INTR_INFO_VALID_MASK;
4518 if (vcpu->arch.interrupt.soft) {
4519 intr |= INTR_TYPE_SOFT_INTR;
4520 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4521 vmx->vcpu.arch.event_exit_inst_len);
4522 } else
4523 intr |= INTR_TYPE_EXT_INTR;
4524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4525}
4526
f08864b4
SY		 4527static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4528{
66a5a347
JK		 4529 struct vcpu_vmx *vmx = to_vmx(vcpu);
4530
0b6ac343
NHE		 4531 if (is_guest_mode(vcpu))
4532 return;
4533
3b86cd99
JK		 4534 if (!cpu_has_virtual_nmis()) {
4535 /*
4536 * Tracking the NMI-blocked state in software is built upon
4537 * finding the next open IRQ window. This, in turn, depends on
4538 * well-behaving guests: They have to keep IRQs disabled at
4539 * least as long as the NMI handler runs. Otherwise we may
4540 * cause NMI nesting, maybe breaking the guest. But as this is
4541 * highly unlikely, we can live with the residual risk.
4542 */
4543 vmx->soft_vnmi_blocked = 1;
4544 vmx->vnmi_blocked_time = 0;
4545 }
4546
487b391d 4547 ++vcpu->stat.nmi_injections;
9d58b931 4548 vmx->nmi_known_unmasked = false;
7ffd92c5 4549 if (vmx->rmode.vm86_active) {
71f9833b 4550 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4551 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4552 return;
4553 }
f08864b4
SY		 4554 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4555 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4556}
4557
3cfc3092
JK		 4558static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4559{
4560 if (!cpu_has_virtual_nmis())
4561 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4562 if (to_vmx(vcpu)->nmi_known_unmasked)
4563 return false;
c332c83a 4564 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4565}
4566
4567static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4568{
4569 struct vcpu_vmx *vmx = to_vmx(vcpu);
4570
4571 if (!cpu_has_virtual_nmis()) {
4572 if (vmx->soft_vnmi_blocked != masked) {
4573 vmx->soft_vnmi_blocked = masked;
4574 vmx->vnmi_blocked_time = 0;
4575 }
4576 } else {
9d58b931 4577 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4578 if (masked)
4579 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4580 GUEST_INTR_STATE_NMI);
4581 else
4582 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4583 GUEST_INTR_STATE_NMI);
4584 }
4585}
4586
2505dc9f
JK		 4587static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4588{
ea8ceb83
JK		 4589 if (is_guest_mode(vcpu)) {
4590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4591
4592 if (to_vmx(vcpu)->nested.nested_run_pending)
4593 return 0;
4594 if (nested_exit_on_nmi(vcpu)) {
4595 nested_vmx_vmexit(vcpu);
4596 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4597 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4598 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4599 /*
4600 * The NMI-triggered VM exit counts as injection:
4601 * clear this one and block further NMIs.
4602 */
4603 vcpu->arch.nmi_pending = 0;
4604 vmx_set_nmi_mask(vcpu, true);
4605 return 0;
4606 }
4607 }
4608
2505dc9f
JK		 4609 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4610 return 0;
4611
4612 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4613 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4614 | GUEST_INTR_STATE_NMI));
4615}
4616
78646121
GN		 4617static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4618{
e8457c67 4619 if (is_guest_mode(vcpu)) {
51cfe38e 4620 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4621
4622 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4623 return 0;
e8457c67
JK		 4624 if (nested_exit_on_intr(vcpu)) {
4625 nested_vmx_vmexit(vcpu);
4626 vmcs12->vm_exit_reason =
4627 EXIT_REASON_EXTERNAL_INTERRUPT;
4628 vmcs12->vm_exit_intr_info = 0;
4629 /*
4630 * fall through to normal code, but now in L1, not L2
4631 */
4632 }
b6f1250e
NHE		 4633 }
4634
c4282df9
GN		 4635 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4636 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4637 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4638}
4639
cbc94022
IE		 4640static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4641{
4642 int ret;
4643 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4644 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4645 .guest_phys_addr = addr,
4646 .memory_size = PAGE_SIZE * 3,
4647 .flags = 0,
4648 };
4649
47ae31e2 4650 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4651 if (ret)
4652 return ret;
bfc6d222 4653 kvm->arch.tss_addr = addr;
93ea5388
GN		 4654 if (!init_rmode_tss(kvm))
4655 return -ENOMEM;
4656
cbc94022
IE		 4657 return 0;
4658}
4659
0ca1b4f4 4660static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4661{
77ab6db0 4662 switch (vec) {
77ab6db0 4663 case BP_VECTOR:
c573cd22
JK		 4664 /*
4665 * Update instruction length as we may reinject the exception
4666 * from user space while in guest debugging mode.
4667 */
4668 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4669 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4670 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4671 return false;
4672 /* fall through */
4673 case DB_VECTOR:
4674 if (vcpu->guest_debug &
4675 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4676 return false;
d0bfb940
JK		 4677 /* fall through */
4678 case DE_VECTOR:
77ab6db0
JK		 4679 case OF_VECTOR:
4680 case BR_VECTOR:
4681 case UD_VECTOR:
4682 case DF_VECTOR:
4683 case SS_VECTOR:
4684 case GP_VECTOR:
4685 case MF_VECTOR:
0ca1b4f4
GN		 4686 return true;
4687 break;
77ab6db0 4688 }
0ca1b4f4
GN		 4689 return false;
4690}
4691
4692static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4693 int vec, u32 err_code)
4694{
4695 /*
4696 * Instruction with address size override prefix opcode 0x67
4697 * Cause the #SS fault with 0 error code in VM86 mode.
4698 */
4699 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4700 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4701 if (vcpu->arch.halt_request) {
4702 vcpu->arch.halt_request = 0;
4703 return kvm_emulate_halt(vcpu);
4704 }
4705 return 1;
4706 }
4707 return 0;
4708 }
4709
4710 /*
4711 * Forward all other exceptions that are valid in real mode.
4712 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4713 * the required debugging infrastructure rework.
4714 */
4715 kvm_queue_exception(vcpu, vec);
4716 return 1;
6aa8b732
AK		 4717}
4718
a0861c02
AK		 4719/*
4720 * Trigger machine check on the host. We assume all the MSRs are already set up
4721 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4722 * We pass a fake environment to the machine check handler because we want
4723 * the guest to be always treated like user space, no matter what context
4724 * it used internally.
4725 */
4726static void kvm_machine_check(void)
4727{
4728#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4729 struct pt_regs regs = {
4730 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4731 .flags = X86_EFLAGS_IF,
4732 };
4733
4734 do_machine_check(&regs, 0);
4735#endif
4736}
4737
851ba692 4738static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4739{
4740 /* already handled by vcpu_run */
4741 return 1;
4742}
4743
851ba692 4744static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4745{
1155f76a 4746 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4747 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4748 u32 intr_info, ex_no, error_code;
42dbaa5a 4749 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4750 u32 vect_info;
4751 enum emulation_result er;
4752
1155f76a 4753 vect_info = vmx->idt_vectoring_info;
88786475 4754 intr_info = vmx->exit_intr_info;
6aa8b732 4755
a0861c02 4756 if (is_machine_check(intr_info))
851ba692 4757 return handle_machine_check(vcpu);
a0861c02 4758
e4a41889 4759 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4760 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4761
4762 if (is_no_device(intr_info)) {
5fd86fcf 4763 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4764 return 1;
4765 }
4766
7aa81cc0 4767 if (is_invalid_opcode(intr_info)) {
51d8b661 4768 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4769 if (er != EMULATE_DONE)
7ee5d940 4770 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4771 return 1;
4772 }
4773
6aa8b732 4774 error_code = 0;
2e11384c 4775 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4776 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4777
4778 /*
4779 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4780 * MMIO, it is better to report an internal error.
4781 * See the comments in vmx_handle_exit.
4782 */
4783 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4784 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4785 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4786 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4787 vcpu->run->internal.ndata = 2;
4788 vcpu->run->internal.data[0] = vect_info;
4789 vcpu->run->internal.data[1] = intr_info;
4790 return 0;
4791 }
4792
6aa8b732 4793 if (is_page_fault(intr_info)) {
1439442c 4794 /* EPT won't cause page fault directly */
cf3ace79 4795 BUG_ON(enable_ept);
6aa8b732 4796 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4797 trace_kvm_page_fault(cr2, error_code);
4798
3298b75c 4799 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4800 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4801 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4802 }
4803
d0bfb940 4804 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4805
4806 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4807 return handle_rmode_exception(vcpu, ex_no, error_code);
4808
42dbaa5a
JK		 4809 switch (ex_no) {
4810 case DB_VECTOR:
4811 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4812 if (!(vcpu->guest_debug &
4813 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4814 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4815 kvm_queue_exception(vcpu, DB_VECTOR);
4816 return 1;
4817 }
4818 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4819 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4820 /* fall through */
4821 case BP_VECTOR:
c573cd22
JK		 4822 /*
4823 * Update instruction length as we may reinject #BP from
4824 * user space while in guest debugging mode. Reading it for
4825 * #DB as well causes no harm, it is not used in that case.
4826 */
4827 vmx->vcpu.arch.event_exit_inst_len =
4828 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4829 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4830 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4831 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4832 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4833 break;
4834 default:
d0bfb940
JK		 4835 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4836 kvm_run->ex.exception = ex_no;
4837 kvm_run->ex.error_code = error_code;
42dbaa5a 4838 break;
6aa8b732 4839 }
6aa8b732
AK		 4840 return 0;
4841}
4842
851ba692 4843static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4844{
1165f5fe 4845 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4846 return 1;
4847}
4848
851ba692 4849static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4850{
851ba692 4851 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4852 return 0;
4853}
6aa8b732 4854
851ba692 4855static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4856{
bfdaab09 4857 unsigned long exit_qualification;
34c33d16 4858 int size, in, string;
039576c0 4859 unsigned port;
6aa8b732 4860
bfdaab09 4861 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4862 string = (exit_qualification & 16) != 0;
cf8f70bf 4863 in = (exit_qualification & 8) != 0;
e70669ab 4864
cf8f70bf 4865 ++vcpu->stat.io_exits;
e70669ab 4866
cf8f70bf 4867 if (string || in)
51d8b661 4868 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4869
cf8f70bf
GN		 4870 port = exit_qualification >> 16;
4871 size = (exit_qualification & 7) + 1;
e93f36bc 4872 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4873
4874 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4875}
4876
102d8325
IM		 4877static void
4878vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4879{
4880 /*
4881 * Patch in the VMCALL instruction:
4882 */
4883 hypercall[0] = 0x0f;
4884 hypercall[1] = 0x01;
4885 hypercall[2] = 0xc1;
102d8325
IM		 4886}
4887
92fbc7b1
JK		 4888static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4889{
4890 unsigned long always_on = VMXON_CR0_ALWAYSON;
4891
4892 if (nested_vmx_secondary_ctls_high &
4893 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4894 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4895 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4896 return (val & always_on) == always_on;
4897}
4898
0fa06071 4899/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4900static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4901{
eeadf9e7 4902 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4903 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4904 unsigned long orig_val = val;
4905
eeadf9e7
NHE		 4906 /*
4907 * We get here when L2 changed cr0 in a way that did not change
4908 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4909 * but did change L0 shadowed bits. So we first calculate the
4910 * effective cr0 value that L1 would like to write into the
4911 * hardware. It consists of the L2-owned bits from the new
4912 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4913 */
1a0d74e6
JK		 4914 val = (val & ~vmcs12->cr0_guest_host_mask) |
4915 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4916
92fbc7b1 4917 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4918 return 1;
1a0d74e6
JK		 4919
4920 if (kvm_set_cr0(vcpu, val))
4921 return 1;
4922 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4923 return 0;
1a0d74e6
JK		 4924 } else {
4925 if (to_vmx(vcpu)->nested.vmxon &&
4926 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4927 return 1;
eeadf9e7 4928 return kvm_set_cr0(vcpu, val);
1a0d74e6 4929 }
eeadf9e7
NHE		 4930}
4931
4932static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4933{
4934 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4935 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4936 unsigned long orig_val = val;
4937
4938 /* analogously to handle_set_cr0 */
4939 val = (val & ~vmcs12->cr4_guest_host_mask) |
4940 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4941 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4942 return 1;
1a0d74e6 4943 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4944 return 0;
4945 } else
4946 return kvm_set_cr4(vcpu, val);
4947}
4948
4949/* called to set cr0 as approriate for clts instruction exit. */
4950static void handle_clts(struct kvm_vcpu *vcpu)
4951{
4952 if (is_guest_mode(vcpu)) {
4953 /*
4954 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4955 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4956 * just pretend it's off (also in arch.cr0 for fpu_activate).
4957 */
4958 vmcs_writel(CR0_READ_SHADOW,
4959 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4960 vcpu->arch.cr0 &= ~X86_CR0_TS;
4961 } else
4962 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4963}
4964
851ba692 4965static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4966{
229456fc 4967 unsigned long exit_qualification, val;
6aa8b732
AK		 4968 int cr;
4969 int reg;
49a9b07e 4970 int err;
6aa8b732 4971
bfdaab09 4972 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4973 cr = exit_qualification & 15;
4974 reg = (exit_qualification >> 8) & 15;
4975 switch ((exit_qualification >> 4) & 3) {
4976 case 0: /* mov to cr */
229456fc
MT		 4977 val = kvm_register_read(vcpu, reg);
4978 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4979 switch (cr) {
4980 case 0:
eeadf9e7 4981 err = handle_set_cr0(vcpu, val);
db8fcefa 4982 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4983 return 1;
4984 case 3:
2390218b 4985 err = kvm_set_cr3(vcpu, val);
db8fcefa 4986 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4987 return 1;
4988 case 4:
eeadf9e7 4989 err = handle_set_cr4(vcpu, val);
db8fcefa 4990 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4991 return 1;
0a5fff19
GN		 4992 case 8: {
4993 u8 cr8_prev = kvm_get_cr8(vcpu);
4994 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4995 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4996 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4997 if (irqchip_in_kernel(vcpu->kvm))
4998 return 1;
4999 if (cr8_prev <= cr8)
5000 return 1;
851ba692 5001 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5002 return 0;
5003 }
4b8073e4 5004 }
6aa8b732 5005 break;
25c4c276 5006 case 2: /* clts */
eeadf9e7 5007 handle_clts(vcpu);
4d4ec087 5008 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5009 skip_emulated_instruction(vcpu);
6b52d186 5010 vmx_fpu_activate(vcpu);
25c4c276 5011 return 1;
6aa8b732
AK		 5012 case 1: /*mov from cr*/
5013 switch (cr) {
5014 case 3:
9f8fe504
AK		 5015 val = kvm_read_cr3(vcpu);
5016 kvm_register_write(vcpu, reg, val);
5017 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5018 skip_emulated_instruction(vcpu);
5019 return 1;
5020 case 8:
229456fc
MT		 5021 val = kvm_get_cr8(vcpu);
5022 kvm_register_write(vcpu, reg, val);
5023 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5024 skip_emulated_instruction(vcpu);
5025 return 1;
5026 }
5027 break;
5028 case 3: /* lmsw */
a1f83a74 5029 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5030 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5031 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5032
5033 skip_emulated_instruction(vcpu);
5034 return 1;
5035 default:
5036 break;
5037 }
851ba692 5038 vcpu->run->exit_reason = 0;
a737f256 5039 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5040 (int)(exit_qualification >> 4) & 3, cr);
5041 return 0;
5042}
5043
851ba692 5044static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5045{
bfdaab09 5046 unsigned long exit_qualification;
6aa8b732
AK		 5047 int dr, reg;
5048
f2483415 5049 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5050 if (!kvm_require_cpl(vcpu, 0))
5051 return 1;
42dbaa5a
JK		 5052 dr = vmcs_readl(GUEST_DR7);
5053 if (dr & DR7_GD) {
5054 /*
5055 * As the vm-exit takes precedence over the debug trap, we
5056 * need to emulate the latter, either for the host or the
5057 * guest debugging itself.
5058 */
5059 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5060 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5061 vcpu->run->debug.arch.dr7 = dr;
5062 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5063 vmcs_readl(GUEST_CS_BASE) +
5064 vmcs_readl(GUEST_RIP);
851ba692
AK		 5065 vcpu->run->debug.arch.exception = DB_VECTOR;
5066 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5067 return 0;
5068 } else {
5069 vcpu->arch.dr7 &= ~DR7_GD;
5070 vcpu->arch.dr6 |= DR6_BD;
5071 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5072 kvm_queue_exception(vcpu, DB_VECTOR);
5073 return 1;
5074 }
5075 }
5076
bfdaab09 5077 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5078 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5079 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5080 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5081 unsigned long val;
5082 if (!kvm_get_dr(vcpu, dr, &val))
5083 kvm_register_write(vcpu, reg, val);
5084 } else
5085 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5086 skip_emulated_instruction(vcpu);
5087 return 1;
5088}
5089
020df079
GN		 5090static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5091{
5092 vmcs_writel(GUEST_DR7, val);
5093}
5094
851ba692 5095static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5096{
06465c5a
AK		 5097 kvm_emulate_cpuid(vcpu);
5098 return 1;
6aa8b732
AK		 5099}
5100
851ba692 5101static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5102{
ad312c7c 5103 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5104 u64 data;
5105
5106 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5107 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5108 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5109 return 1;
5110 }
5111
229456fc 5112 trace_kvm_msr_read(ecx, data);
2714d1d3 5113
6aa8b732 5114 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5115 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5116 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5117 skip_emulated_instruction(vcpu);
5118 return 1;
5119}
5120
851ba692 5121static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5122{
8fe8ab46 5123 struct msr_data msr;
ad312c7c
ZX		 5124 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5125 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5126 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5127
8fe8ab46
WA		 5128 msr.data = data;
5129 msr.index = ecx;
5130 msr.host_initiated = false;
5131 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5132 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5133 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5134 return 1;
5135 }
5136
59200273 5137 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5138 skip_emulated_instruction(vcpu);
5139 return 1;
5140}
5141
851ba692 5142static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5143{
3842d135 5144 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5145 return 1;
5146}
5147
851ba692 5148static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5149{
85f455f7
ED		 5150 u32 cpu_based_vm_exec_control;
5151
5152 /* clear pending irq */
5153 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5154 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5155 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5156
3842d135
AK		 5157 kvm_make_request(KVM_REQ_EVENT, vcpu);
5158
a26bf12a 5159 ++vcpu->stat.irq_window_exits;
2714d1d3 5160
c1150d8c
DL		 5161 /*
5162 * If the user space waits to inject interrupts, exit as soon as
5163 * possible
5164 */
8061823a 5165 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5166 vcpu->run->request_interrupt_window &&
8061823a 5167 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5168 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5169 return 0;
5170 }
6aa8b732
AK		 5171 return 1;
5172}
5173
851ba692 5174static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5175{
5176 skip_emulated_instruction(vcpu);
d3bef15f 5177 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5178}
5179
851ba692 5180static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5181{
510043da 5182 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5183 kvm_emulate_hypercall(vcpu);
5184 return 1;
c21415e8
IM		 5185}
5186
ec25d5e6
GN		 5187static int handle_invd(struct kvm_vcpu *vcpu)
5188{
51d8b661 5189 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5190}
5191
851ba692 5192static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5193{
f9c617f6 5194 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5195
5196 kvm_mmu_invlpg(vcpu, exit_qualification);
5197 skip_emulated_instruction(vcpu);
5198 return 1;
5199}
5200
fee84b07
AK		 5201static int handle_rdpmc(struct kvm_vcpu *vcpu)
5202{
5203 int err;
5204
5205 err = kvm_rdpmc(vcpu);
5206 kvm_complete_insn_gp(vcpu, err);
5207
5208 return 1;
5209}
5210
851ba692 5211static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5212{
5213 skip_emulated_instruction(vcpu);
f5f48ee1 5214 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5215 return 1;
5216}
5217
2acf923e
DC		 5218static int handle_xsetbv(struct kvm_vcpu *vcpu)
5219{
5220 u64 new_bv = kvm_read_edx_eax(vcpu);
5221 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5222
5223 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5224 skip_emulated_instruction(vcpu);
5225 return 1;
5226}
5227
851ba692 5228static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5229{
58fbbf26
KT		 5230 if (likely(fasteoi)) {
5231 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5232 int access_type, offset;
5233
5234 access_type = exit_qualification & APIC_ACCESS_TYPE;
5235 offset = exit_qualification & APIC_ACCESS_OFFSET;
5236 /*
5237 * Sane guest uses MOV to write EOI, with written value
5238 * not cared. So make a short-circuit here by avoiding
5239 * heavy instruction emulation.
5240 */
5241 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5242 (offset == APIC_EOI)) {
5243 kvm_lapic_set_eoi(vcpu);
5244 skip_emulated_instruction(vcpu);
5245 return 1;
5246 }
5247 }
51d8b661 5248 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5249}
5250
c7c9c56c
YZ		 5251static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5252{
5253 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5254 int vector = exit_qualification & 0xff;
5255
5256 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5257 kvm_apic_set_eoi_accelerated(vcpu, vector);
5258 return 1;
5259}
5260
83d4c286
YZ		 5261static int handle_apic_write(struct kvm_vcpu *vcpu)
5262{
5263 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5264 u32 offset = exit_qualification & 0xfff;
5265
5266 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5267 kvm_apic_write_nodecode(vcpu, offset);
5268 return 1;
5269}
5270
851ba692 5271static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5272{
60637aac 5273 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5274 unsigned long exit_qualification;
e269fb21
JK		 5275 bool has_error_code = false;
5276 u32 error_code = 0;
37817f29 5277 u16 tss_selector;
7f3d35fd 5278 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5279
5280 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5281 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5282 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5283
5284 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5285
5286 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5287 if (reason == TASK_SWITCH_GATE && idt_v) {
5288 switch (type) {
5289 case INTR_TYPE_NMI_INTR:
5290 vcpu->arch.nmi_injected = false;
654f06fc 5291 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5292 break;
5293 case INTR_TYPE_EXT_INTR:
66fd3f7f 5294 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5295 kvm_clear_interrupt_queue(vcpu);
5296 break;
5297 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5298 if (vmx->idt_vectoring_info &
5299 VECTORING_INFO_DELIVER_CODE_MASK) {
5300 has_error_code = true;
5301 error_code =
5302 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5303 }
5304 /* fall through */
64a7ec06
GN		 5305 case INTR_TYPE_SOFT_EXCEPTION:
5306 kvm_clear_exception_queue(vcpu);
5307 break;
5308 default:
5309 break;
5310 }
60637aac 5311 }
37817f29
IE		 5312 tss_selector = exit_qualification;
5313
64a7ec06
GN		 5314 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5315 type != INTR_TYPE_EXT_INTR &&
5316 type != INTR_TYPE_NMI_INTR))
5317 skip_emulated_instruction(vcpu);
5318
7f3d35fd
KW		 5319 if (kvm_task_switch(vcpu, tss_selector,
5320 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5321 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5322 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5323 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5324 vcpu->run->internal.ndata = 0;
42dbaa5a 5325 return 0;
acb54517 5326 }
42dbaa5a
JK		 5327
5328 /* clear all local breakpoint enable flags */
5329 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5330
5331 /*
5332 * TODO: What about debug traps on tss switch?
5333 * Are we supposed to inject them and update dr6?
5334 */
5335
5336 return 1;
37817f29
IE		 5337}
5338
851ba692 5339static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5340{
f9c617f6 5341 unsigned long exit_qualification;
1439442c 5342 gpa_t gpa;
4f5982a5 5343 u32 error_code;
1439442c 5344 int gla_validity;
1439442c 5345
f9c617f6 5346 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5347
1439442c
SY		 5348 gla_validity = (exit_qualification >> 7) & 0x3;
5349 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5350 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5351 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5352 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5353 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5354 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5355 (long unsigned int)exit_qualification);
851ba692
AK		 5356 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5357 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5358 return 0;
1439442c
SY		 5359 }
5360
0be9c7a8
GN		 5361 /*
5362 * EPT violation happened while executing iret from NMI,
5363 * "blocked by NMI" bit has to be set before next VM entry.
5364 * There are errata that may cause this bit to not be set:
5365 * AAK134, BY25.
5366 */
bcd1c294
GN		 5367 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5368 cpu_has_virtual_nmis() &&
5369 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5370 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5371
1439442c 5372 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5373 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5374
5375 /* It is a write fault? */
5376 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5377 /* It is a fetch fault? */
5378 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5379 /* ept page table is present? */
5380 error_code |= (exit_qualification >> 3) & 0x1;
5381
25d92081
YZ		 5382 vcpu->arch.exit_qualification = exit_qualification;
5383
4f5982a5 5384 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5385}
5386
68f89400
MT		 5387static u64 ept_rsvd_mask(u64 spte, int level)
5388{
5389 int i;
5390 u64 mask = 0;
5391
5392 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5393 mask |= (1ULL << i);
5394
5395 if (level > 2)
5396 /* bits 7:3 reserved */
5397 mask |= 0xf8;
5398 else if (level == 2) {
5399 if (spte & (1ULL << 7))
5400 /* 2MB ref, bits 20:12 reserved */
5401 mask |= 0x1ff000;
5402 else
5403 /* bits 6:3 reserved */
5404 mask |= 0x78;
5405 }
5406
5407 return mask;
5408}
5409
5410static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5411 int level)
5412{
5413 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5414
5415 /* 010b (write-only) */
5416 WARN_ON((spte & 0x7) == 0x2);
5417
5418 /* 110b (write/execute) */
5419 WARN_ON((spte & 0x7) == 0x6);
5420
5421 /* 100b (execute-only) and value not supported by logical processor */
5422 if (!cpu_has_vmx_ept_execute_only())
5423 WARN_ON((spte & 0x7) == 0x4);
5424
5425 /* not 000b */
5426 if ((spte & 0x7)) {
5427 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5428
5429 if (rsvd_bits != 0) {
5430 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5431 __func__, rsvd_bits);
5432 WARN_ON(1);
5433 }
5434
5435 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5436 u64 ept_mem_type = (spte & 0x38) >> 3;
5437
5438 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5439 ept_mem_type == 7) {
5440 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5441 __func__, ept_mem_type);
5442 WARN_ON(1);
5443 }
5444 }
5445 }
5446}
5447
851ba692 5448static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5449{
5450 u64 sptes[4];
ce88decf 5451 int nr_sptes, i, ret;
68f89400
MT		 5452 gpa_t gpa;
5453
5454 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5455
ce88decf 5456 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5457 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5458 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5459 EMULATE_DONE;
f8f55942
XG		 5460
5461 if (unlikely(ret == RET_MMIO_PF_INVALID))
5462 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5463
b37fbea6 5464 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5465 return 1;
5466
5467 /* It is the real ept misconfig */
68f89400
MT		 5468 printk(KERN_ERR "EPT: Misconfiguration.\n");
5469 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5470
5471 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5472
5473 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5474 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5475
851ba692
AK		 5476 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5477 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5478
5479 return 0;
5480}
5481
851ba692 5482static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5483{
5484 u32 cpu_based_vm_exec_control;
5485
5486 /* clear pending NMI */
5487 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5488 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5489 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5490 ++vcpu->stat.nmi_window_exits;
3842d135 5491 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5492
5493 return 1;
5494}
5495
80ced186 5496static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5497{
8b3079a5
AK		 5498 struct vcpu_vmx *vmx = to_vmx(vcpu);
5499 enum emulation_result err = EMULATE_DONE;
80ced186 5500 int ret = 1;
49e9d557
AK		 5501 u32 cpu_exec_ctrl;
5502 bool intr_window_requested;
b8405c18 5503 unsigned count = 130;
49e9d557
AK		 5504
5505 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5506 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5507
b8405c18 5508 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5509 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5510 return handle_interrupt_window(&vmx->vcpu);
5511
de87dcdd
AK		 5512 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5513 return 1;
5514
991eebf9 5515 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5516
ac0a48c3 5517 if (err == EMULATE_USER_EXIT) {
94452b9e 5518 ++vcpu->stat.mmio_exits;
80ced186
MG		 5519 ret = 0;
5520 goto out;
5521 }
1d5a4d9b 5522
de5f70e0
AK		 5523 if (err != EMULATE_DONE) {
5524 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5525 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5526 vcpu->run->internal.ndata = 0;
6d77dbfc 5527 return 0;
de5f70e0 5528 }
ea953ef0 5529
8d76c49e
GN		 5530 if (vcpu->arch.halt_request) {
5531 vcpu->arch.halt_request = 0;
5532 ret = kvm_emulate_halt(vcpu);
5533 goto out;
5534 }
5535
ea953ef0 5536 if (signal_pending(current))
80ced186 5537 goto out;
ea953ef0
MG		 5538 if (need_resched())
5539 schedule();
5540 }
5541
14168786 5542 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5543out:
5544 return ret;
ea953ef0
MG		 5545}
5546
4b8d54f9
ZE		 5547/*
5548 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5549 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5550 */
9fb41ba8 5551static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5552{
5553 skip_emulated_instruction(vcpu);
5554 kvm_vcpu_on_spin(vcpu);
5555
5556 return 1;
5557}
5558
59708670
SY		 5559static int handle_invalid_op(struct kvm_vcpu *vcpu)
5560{
5561 kvm_queue_exception(vcpu, UD_VECTOR);
5562 return 1;
5563}
5564
ff2f6fe9
NHE		 5565/*
5566 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5567 * We could reuse a single VMCS for all the L2 guests, but we also want the
5568 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5569 * allows keeping them loaded on the processor, and in the future will allow
5570 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5571 * every entry if they never change.
5572 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5573 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5574 *
5575 * The following functions allocate and free a vmcs02 in this pool.
5576 */
5577
5578/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5579static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5580{
5581 struct vmcs02_list *item;
5582 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5583 if (item->vmptr == vmx->nested.current_vmptr) {
5584 list_move(&item->list, &vmx->nested.vmcs02_pool);
5585 return &item->vmcs02;
5586 }
5587
5588 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5589 /* Recycle the least recently used VMCS. */
5590 item = list_entry(vmx->nested.vmcs02_pool.prev,
5591 struct vmcs02_list, list);
5592 item->vmptr = vmx->nested.current_vmptr;
5593 list_move(&item->list, &vmx->nested.vmcs02_pool);
5594 return &item->vmcs02;
5595 }
5596
5597 /* Create a new VMCS */
0fa24ce3 5598 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5599 if (!item)
5600 return NULL;
5601 item->vmcs02.vmcs = alloc_vmcs();
5602 if (!item->vmcs02.vmcs) {
5603 kfree(item);
5604 return NULL;
5605 }
5606 loaded_vmcs_init(&item->vmcs02);
5607 item->vmptr = vmx->nested.current_vmptr;
5608 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5609 vmx->nested.vmcs02_num++;
5610 return &item->vmcs02;
5611}
5612
5613/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5614static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5615{
5616 struct vmcs02_list *item;
5617 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5618 if (item->vmptr == vmptr) {
5619 free_loaded_vmcs(&item->vmcs02);
5620 list_del(&item->list);
5621 kfree(item);
5622 vmx->nested.vmcs02_num--;
5623 return;
5624 }
5625}
5626
5627/*
5628 * Free all VMCSs saved for this vcpu, except the one pointed by
5629 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5630 * currently used, if running L2), and vmcs01 when running L2.
5631 */
5632static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5633{
5634 struct vmcs02_list *item, *n;
5635 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5636 if (vmx->loaded_vmcs != &item->vmcs02)
5637 free_loaded_vmcs(&item->vmcs02);
5638 list_del(&item->list);
5639 kfree(item);
5640 }
5641 vmx->nested.vmcs02_num = 0;
5642
5643 if (vmx->loaded_vmcs != &vmx->vmcs01)
5644 free_loaded_vmcs(&vmx->vmcs01);
5645}
5646
0658fbaa
ACL		 5647/*
5648 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5649 * set the success or error code of an emulated VMX instruction, as specified
5650 * by Vol 2B, VMX Instruction Reference, "Conventions".
5651 */
5652static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5653{
5654 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5655 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5656 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5657}
5658
5659static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5660{
5661 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5662 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5663 X86_EFLAGS_SF | X86_EFLAGS_OF))
5664 | X86_EFLAGS_CF);
5665}
5666
145c28dd 5667static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5668 u32 vm_instruction_error)
5669{
5670 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5671 /*
5672 * failValid writes the error number to the current VMCS, which
5673 * can't be done there isn't a current VMCS.
5674 */
5675 nested_vmx_failInvalid(vcpu);
5676 return;
5677 }
5678 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5679 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5680 X86_EFLAGS_SF | X86_EFLAGS_OF))
5681 | X86_EFLAGS_ZF);
5682 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5683 /*
5684 * We don't need to force a shadow sync because
5685 * VM_INSTRUCTION_ERROR is not shadowed
5686 */
5687}
145c28dd 5688
ec378aee
NHE		 5689/*
5690 * Emulate the VMXON instruction.
5691 * Currently, we just remember that VMX is active, and do not save or even
5692 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5693 * do not currently need to store anything in that guest-allocated memory
5694 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5695 * argument is different from the VMXON pointer (which the spec says they do).
5696 */
5697static int handle_vmon(struct kvm_vcpu *vcpu)
5698{
5699 struct kvm_segment cs;
5700 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5701 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5702 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5703 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5704
5705 /* The Intel VMX Instruction Reference lists a bunch of bits that
5706 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5707 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5708 * Otherwise, we should fail with #UD. We test these now:
5709 */
5710 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5711 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5712 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5713 kvm_queue_exception(vcpu, UD_VECTOR);
5714 return 1;
5715 }
5716
5717 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5718 if (is_long_mode(vcpu) && !cs.l) {
5719 kvm_queue_exception(vcpu, UD_VECTOR);
5720 return 1;
5721 }
5722
5723 if (vmx_get_cpl(vcpu)) {
5724 kvm_inject_gp(vcpu, 0);
5725 return 1;
5726 }
145c28dd
AG		 5727 if (vmx->nested.vmxon) {
5728 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5729 skip_emulated_instruction(vcpu);
5730 return 1;
5731 }
b3897a49
NHE		 5732
5733 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5734 != VMXON_NEEDED_FEATURES) {
5735 kvm_inject_gp(vcpu, 0);
5736 return 1;
5737 }
5738
8de48833
AG		 5739 if (enable_shadow_vmcs) {
5740 shadow_vmcs = alloc_vmcs();
5741 if (!shadow_vmcs)
5742 return -ENOMEM;
5743 /* mark vmcs as shadow */
5744 shadow_vmcs->revision_id |= (1u << 31);
5745 /* init shadow vmcs */
5746 vmcs_clear(shadow_vmcs);
5747 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5748 }
ec378aee 5749
ff2f6fe9
NHE		 5750 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5751 vmx->nested.vmcs02_num = 0;
5752
ec378aee
NHE		 5753 vmx->nested.vmxon = true;
5754
5755 skip_emulated_instruction(vcpu);
a25eb114 5756 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5757 return 1;
5758}
5759
5760/*
5761 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5762 * for running VMX instructions (except VMXON, whose prerequisites are
5763 * slightly different). It also specifies what exception to inject otherwise.
5764 */
5765static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5766{
5767 struct kvm_segment cs;
5768 struct vcpu_vmx *vmx = to_vmx(vcpu);
5769
5770 if (!vmx->nested.vmxon) {
5771 kvm_queue_exception(vcpu, UD_VECTOR);
5772 return 0;
5773 }
5774
5775 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5776 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5777 (is_long_mode(vcpu) && !cs.l)) {
5778 kvm_queue_exception(vcpu, UD_VECTOR);
5779 return 0;
5780 }
5781
5782 if (vmx_get_cpl(vcpu)) {
5783 kvm_inject_gp(vcpu, 0);
5784 return 0;
5785 }
5786
5787 return 1;
5788}
5789
e7953d7f
AG		 5790static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5791{
8a1b9dd0 5792 u32 exec_control;
012f83cb
AG		 5793 if (enable_shadow_vmcs) {
5794 if (vmx->nested.current_vmcs12 != NULL) {
5795 /* copy to memory all shadowed fields in case
5796 they were modified */
5797 copy_shadow_to_vmcs12(vmx);
5798 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5799 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5800 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5801 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5802 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5803 }
5804 }
e7953d7f
AG		 5805 kunmap(vmx->nested.current_vmcs12_page);
5806 nested_release_page(vmx->nested.current_vmcs12_page);
5807}
5808
ec378aee
NHE		 5809/*
5810 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5811 * just stops using VMX.
5812 */
5813static void free_nested(struct vcpu_vmx *vmx)
5814{
5815 if (!vmx->nested.vmxon)
5816 return;
5817 vmx->nested.vmxon = false;
a9d30f33 5818 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5819 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5820 vmx->nested.current_vmptr = -1ull;
5821 vmx->nested.current_vmcs12 = NULL;
5822 }
e7953d7f
AG		 5823 if (enable_shadow_vmcs)
5824 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5825 /* Unpin physical memory we referred to in current vmcs02 */
5826 if (vmx->nested.apic_access_page) {
5827 nested_release_page(vmx->nested.apic_access_page);
5828 vmx->nested.apic_access_page = 0;
5829 }
ff2f6fe9
NHE		 5830
5831 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5832}
5833
5834/* Emulate the VMXOFF instruction */
5835static int handle_vmoff(struct kvm_vcpu *vcpu)
5836{
5837 if (!nested_vmx_check_permission(vcpu))
5838 return 1;
5839 free_nested(to_vmx(vcpu));
5840 skip_emulated_instruction(vcpu);
a25eb114 5841 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5842 return 1;
5843}
5844
064aea77
NHE		 5845/*
5846 * Decode the memory-address operand of a vmx instruction, as recorded on an
5847 * exit caused by such an instruction (run by a guest hypervisor).
5848 * On success, returns 0. When the operand is invalid, returns 1 and throws
5849 * #UD or #GP.
5850 */
5851static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5852 unsigned long exit_qualification,
5853 u32 vmx_instruction_info, gva_t *ret)
5854{
5855 /*
5856 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5857 * Execution", on an exit, vmx_instruction_info holds most of the
5858 * addressing components of the operand. Only the displacement part
5859 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5860 * For how an actual address is calculated from all these components,
5861 * refer to Vol. 1, "Operand Addressing".
5862 */
5863 int scaling = vmx_instruction_info & 3;
5864 int addr_size = (vmx_instruction_info >> 7) & 7;
5865 bool is_reg = vmx_instruction_info & (1u << 10);
5866 int seg_reg = (vmx_instruction_info >> 15) & 7;
5867 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5868 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5869 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5870 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5871
5872 if (is_reg) {
5873 kvm_queue_exception(vcpu, UD_VECTOR);
5874 return 1;
5875 }
5876
5877 /* Addr = segment_base + offset */
5878 /* offset = base + [index * scale] + displacement */
5879 *ret = vmx_get_segment_base(vcpu, seg_reg);
5880 if (base_is_valid)
5881 *ret += kvm_register_read(vcpu, base_reg);
5882 if (index_is_valid)
5883 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5884 *ret += exit_qualification; /* holds the displacement */
5885
5886 if (addr_size == 1) /* 32 bit */
5887 *ret &= 0xffffffff;
5888
5889 /*
5890 * TODO: throw #GP (and return 1) in various cases that the VM*
5891 * instructions require it - e.g., offset beyond segment limit,
5892 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5893 * address, and so on. Currently these are not checked.
5894 */
5895 return 0;
5896}
5897
27d6c865
NHE		 5898/* Emulate the VMCLEAR instruction */
5899static int handle_vmclear(struct kvm_vcpu *vcpu)
5900{
5901 struct vcpu_vmx *vmx = to_vmx(vcpu);
5902 gva_t gva;
5903 gpa_t vmptr;
5904 struct vmcs12 *vmcs12;
5905 struct page *page;
5906 struct x86_exception e;
5907
5908 if (!nested_vmx_check_permission(vcpu))
5909 return 1;
5910
5911 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5912 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5913 return 1;
5914
5915 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5916 sizeof(vmptr), &e)) {
5917 kvm_inject_page_fault(vcpu, &e);
5918 return 1;
5919 }
5920
5921 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5922 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5923 skip_emulated_instruction(vcpu);
5924 return 1;
5925 }
5926
5927 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5928 nested_release_vmcs12(vmx);
27d6c865
NHE		 5929 vmx->nested.current_vmptr = -1ull;
5930 vmx->nested.current_vmcs12 = NULL;
5931 }
5932
5933 page = nested_get_page(vcpu, vmptr);
5934 if (page == NULL) {
5935 /*
5936 * For accurate processor emulation, VMCLEAR beyond available
5937 * physical memory should do nothing at all. However, it is
5938 * possible that a nested vmx bug, not a guest hypervisor bug,
5939 * resulted in this case, so let's shut down before doing any
5940 * more damage:
5941 */
5942 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5943 return 1;
5944 }
5945 vmcs12 = kmap(page);
5946 vmcs12->launch_state = 0;
5947 kunmap(page);
5948 nested_release_page(page);
5949
5950 nested_free_vmcs02(vmx, vmptr);
5951
5952 skip_emulated_instruction(vcpu);
5953 nested_vmx_succeed(vcpu);
5954 return 1;
5955}
5956
cd232ad0
NHE		 5957static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5958
5959/* Emulate the VMLAUNCH instruction */
5960static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5961{
5962 return nested_vmx_run(vcpu, true);
5963}
5964
5965/* Emulate the VMRESUME instruction */
5966static int handle_vmresume(struct kvm_vcpu *vcpu)
5967{
5968
5969 return nested_vmx_run(vcpu, false);
5970}
5971
49f705c5
NHE		 5972enum vmcs_field_type {
5973 VMCS_FIELD_TYPE_U16 = 0,
5974 VMCS_FIELD_TYPE_U64 = 1,
5975 VMCS_FIELD_TYPE_U32 = 2,
5976 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5977};
5978
5979static inline int vmcs_field_type(unsigned long field)
5980{
5981 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5982 return VMCS_FIELD_TYPE_U32;
5983 return (field >> 13) & 0x3 ;
5984}
5985
5986static inline int vmcs_field_readonly(unsigned long field)
5987{
5988 return (((field >> 10) & 0x3) == 1);
5989}
5990
5991/*
5992 * Read a vmcs12 field. Since these can have varying lengths and we return
5993 * one type, we chose the biggest type (u64) and zero-extend the return value
5994 * to that size. Note that the caller, handle_vmread, might need to use only
5995 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5996 * 64-bit fields are to be returned).
5997 */
5998static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5999 unsigned long field, u64 *ret)
6000{
6001 short offset = vmcs_field_to_offset(field);
6002 char *p;
6003
6004 if (offset < 0)
6005 return 0;
6006
6007 p = ((char *)(get_vmcs12(vcpu))) + offset;
6008
6009 switch (vmcs_field_type(field)) {
6010 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6011 *ret = *((natural_width *)p);
6012 return 1;
6013 case VMCS_FIELD_TYPE_U16:
6014 *ret = *((u16 *)p);
6015 return 1;
6016 case VMCS_FIELD_TYPE_U32:
6017 *ret = *((u32 *)p);
6018 return 1;
6019 case VMCS_FIELD_TYPE_U64:
6020 *ret = *((u64 *)p);
6021 return 1;
6022 default:
6023 return 0; /* can never happen. */
6024 }
6025}
6026
20b97fea
AG		 6027
6028static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6029 unsigned long field, u64 field_value){
6030 short offset = vmcs_field_to_offset(field);
6031 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6032 if (offset < 0)
6033 return false;
6034
6035 switch (vmcs_field_type(field)) {
6036 case VMCS_FIELD_TYPE_U16:
6037 *(u16 *)p = field_value;
6038 return true;
6039 case VMCS_FIELD_TYPE_U32:
6040 *(u32 *)p = field_value;
6041 return true;
6042 case VMCS_FIELD_TYPE_U64:
6043 *(u64 *)p = field_value;
6044 return true;
6045 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6046 *(natural_width *)p = field_value;
6047 return true;
6048 default:
6049 return false; /* can never happen. */
6050 }
6051
6052}
6053
16f5b903
AG		 6054static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6055{
6056 int i;
6057 unsigned long field;
6058 u64 field_value;
6059 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6060 const unsigned long *fields = shadow_read_write_fields;
6061 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6062
6063 vmcs_load(shadow_vmcs);
6064
6065 for (i = 0; i < num_fields; i++) {
6066 field = fields[i];
6067 switch (vmcs_field_type(field)) {
6068 case VMCS_FIELD_TYPE_U16:
6069 field_value = vmcs_read16(field);
6070 break;
6071 case VMCS_FIELD_TYPE_U32:
6072 field_value = vmcs_read32(field);
6073 break;
6074 case VMCS_FIELD_TYPE_U64:
6075 field_value = vmcs_read64(field);
6076 break;
6077 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6078 field_value = vmcs_readl(field);
6079 break;
6080 }
6081 vmcs12_write_any(&vmx->vcpu, field, field_value);
6082 }
6083
6084 vmcs_clear(shadow_vmcs);
6085 vmcs_load(vmx->loaded_vmcs->vmcs);
6086}
6087
c3114420
AG		 6088static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6089{
c2bae893
MK		 6090 const unsigned long *fields[] = {
6091 shadow_read_write_fields,
6092 shadow_read_only_fields
c3114420 6093 };
c2bae893 6094 const int max_fields[] = {
c3114420
AG		 6095 max_shadow_read_write_fields,
6096 max_shadow_read_only_fields
6097 };
6098 int i, q;
6099 unsigned long field;
6100 u64 field_value = 0;
6101 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6102
6103 vmcs_load(shadow_vmcs);
6104
c2bae893 6105 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6106 for (i = 0; i < max_fields[q]; i++) {
6107 field = fields[q][i];
6108 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6109
6110 switch (vmcs_field_type(field)) {
6111 case VMCS_FIELD_TYPE_U16:
6112 vmcs_write16(field, (u16)field_value);
6113 break;
6114 case VMCS_FIELD_TYPE_U32:
6115 vmcs_write32(field, (u32)field_value);
6116 break;
6117 case VMCS_FIELD_TYPE_U64:
6118 vmcs_write64(field, (u64)field_value);
6119 break;
6120 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6121 vmcs_writel(field, (long)field_value);
6122 break;
6123 }
6124 }
6125 }
6126
6127 vmcs_clear(shadow_vmcs);
6128 vmcs_load(vmx->loaded_vmcs->vmcs);
6129}
6130
49f705c5
NHE		 6131/*
6132 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6133 * used before) all generate the same failure when it is missing.
6134 */
6135static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6136{
6137 struct vcpu_vmx *vmx = to_vmx(vcpu);
6138 if (vmx->nested.current_vmptr == -1ull) {
6139 nested_vmx_failInvalid(vcpu);
6140 skip_emulated_instruction(vcpu);
6141 return 0;
6142 }
6143 return 1;
6144}
6145
6146static int handle_vmread(struct kvm_vcpu *vcpu)
6147{
6148 unsigned long field;
6149 u64 field_value;
6150 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6151 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6152 gva_t gva = 0;
6153
6154 if (!nested_vmx_check_permission(vcpu) ||
6155 !nested_vmx_check_vmcs12(vcpu))
6156 return 1;
6157
6158 /* Decode instruction info and find the field to read */
6159 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6160 /* Read the field, zero-extended to a u64 field_value */
6161 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6162 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6163 skip_emulated_instruction(vcpu);
6164 return 1;
6165 }
6166 /*
6167 * Now copy part of this value to register or memory, as requested.
6168 * Note that the number of bits actually copied is 32 or 64 depending
6169 * on the guest's mode (32 or 64 bit), not on the given field's length.
6170 */
6171 if (vmx_instruction_info & (1u << 10)) {
6172 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6173 field_value);
6174 } else {
6175 if (get_vmx_mem_address(vcpu, exit_qualification,
6176 vmx_instruction_info, &gva))
6177 return 1;
6178 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6179 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6180 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6181 }
6182
6183 nested_vmx_succeed(vcpu);
6184 skip_emulated_instruction(vcpu);
6185 return 1;
6186}
6187
6188
6189static int handle_vmwrite(struct kvm_vcpu *vcpu)
6190{
6191 unsigned long field;
6192 gva_t gva;
6193 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6194 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6195 /* The value to write might be 32 or 64 bits, depending on L1's long
6196 * mode, and eventually we need to write that into a field of several
6197 * possible lengths. The code below first zero-extends the value to 64
6198 * bit (field_value), and then copies only the approriate number of
6199 * bits into the vmcs12 field.
6200 */
6201 u64 field_value = 0;
6202 struct x86_exception e;
6203
6204 if (!nested_vmx_check_permission(vcpu) ||
6205 !nested_vmx_check_vmcs12(vcpu))
6206 return 1;
6207
6208 if (vmx_instruction_info & (1u << 10))
6209 field_value = kvm_register_read(vcpu,
6210 (((vmx_instruction_info) >> 3) & 0xf));
6211 else {
6212 if (get_vmx_mem_address(vcpu, exit_qualification,
6213 vmx_instruction_info, &gva))
6214 return 1;
6215 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6216 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6217 kvm_inject_page_fault(vcpu, &e);
6218 return 1;
6219 }
6220 }
6221
6222
6223 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6224 if (vmcs_field_readonly(field)) {
6225 nested_vmx_failValid(vcpu,
6226 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6227 skip_emulated_instruction(vcpu);
6228 return 1;
6229 }
6230
20b97fea 6231 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6232 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6233 skip_emulated_instruction(vcpu);
6234 return 1;
6235 }
6236
6237 nested_vmx_succeed(vcpu);
6238 skip_emulated_instruction(vcpu);
6239 return 1;
6240}
6241
63846663
NHE		 6242/* Emulate the VMPTRLD instruction */
6243static int handle_vmptrld(struct kvm_vcpu *vcpu)
6244{
6245 struct vcpu_vmx *vmx = to_vmx(vcpu);
6246 gva_t gva;
6247 gpa_t vmptr;
6248 struct x86_exception e;
8a1b9dd0 6249 u32 exec_control;
63846663
NHE		 6250
6251 if (!nested_vmx_check_permission(vcpu))
6252 return 1;
6253
6254 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6255 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6256 return 1;
6257
6258 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6259 sizeof(vmptr), &e)) {
6260 kvm_inject_page_fault(vcpu, &e);
6261 return 1;
6262 }
6263
6264 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6265 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6266 skip_emulated_instruction(vcpu);
6267 return 1;
6268 }
6269
6270 if (vmx->nested.current_vmptr != vmptr) {
6271 struct vmcs12 *new_vmcs12;
6272 struct page *page;
6273 page = nested_get_page(vcpu, vmptr);
6274 if (page == NULL) {
6275 nested_vmx_failInvalid(vcpu);
6276 skip_emulated_instruction(vcpu);
6277 return 1;
6278 }
6279 new_vmcs12 = kmap(page);
6280 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6281 kunmap(page);
6282 nested_release_page_clean(page);
6283 nested_vmx_failValid(vcpu,
6284 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6285 skip_emulated_instruction(vcpu);
6286 return 1;
6287 }
e7953d7f
AG		 6288 if (vmx->nested.current_vmptr != -1ull)
6289 nested_release_vmcs12(vmx);
63846663
NHE		 6290
6291 vmx->nested.current_vmptr = vmptr;
6292 vmx->nested.current_vmcs12 = new_vmcs12;
6293 vmx->nested.current_vmcs12_page = page;
012f83cb 6294 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6295 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6296 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6297 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6298 vmcs_write64(VMCS_LINK_POINTER,
6299 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6300 vmx->nested.sync_shadow_vmcs = true;
6301 }
63846663
NHE		 6302 }
6303
6304 nested_vmx_succeed(vcpu);
6305 skip_emulated_instruction(vcpu);
6306 return 1;
6307}
6308
6a4d7550
NHE		 6309/* Emulate the VMPTRST instruction */
6310static int handle_vmptrst(struct kvm_vcpu *vcpu)
6311{
6312 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6313 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6314 gva_t vmcs_gva;
6315 struct x86_exception e;
6316
6317 if (!nested_vmx_check_permission(vcpu))
6318 return 1;
6319
6320 if (get_vmx_mem_address(vcpu, exit_qualification,
6321 vmx_instruction_info, &vmcs_gva))
6322 return 1;
6323 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6324 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6325 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6326 sizeof(u64), &e)) {
6327 kvm_inject_page_fault(vcpu, &e);
6328 return 1;
6329 }
6330 nested_vmx_succeed(vcpu);
6331 skip_emulated_instruction(vcpu);
6332 return 1;
6333}
6334
bfd0a56b
NHE		 6335/* Emulate the INVEPT instruction */
6336static int handle_invept(struct kvm_vcpu *vcpu)
6337{
6338 u32 vmx_instruction_info, types;
6339 unsigned long type;
6340 gva_t gva;
6341 struct x86_exception e;
6342 struct {
6343 u64 eptp, gpa;
6344 } operand;
6345 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6346
6347 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6348 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6349 kvm_queue_exception(vcpu, UD_VECTOR);
6350 return 1;
6351 }
6352
6353 if (!nested_vmx_check_permission(vcpu))
6354 return 1;
6355
6356 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6357 kvm_queue_exception(vcpu, UD_VECTOR);
6358 return 1;
6359 }
6360
6361 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6362 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6363
6364 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6365
6366 if (!(types & (1UL << type))) {
6367 nested_vmx_failValid(vcpu,
6368 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6369 return 1;
6370 }
6371
6372 /* According to the Intel VMX instruction reference, the memory
6373 * operand is read even if it isn't needed (e.g., for type==global)
6374 */
6375 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6376 vmx_instruction_info, &gva))
6377 return 1;
6378 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6379 sizeof(operand), &e)) {
6380 kvm_inject_page_fault(vcpu, &e);
6381 return 1;
6382 }
6383
6384 switch (type) {
6385 case VMX_EPT_EXTENT_CONTEXT:
6386 if ((operand.eptp & eptp_mask) !=
6387 (nested_ept_get_cr3(vcpu) & eptp_mask))
6388 break;
6389 case VMX_EPT_EXTENT_GLOBAL:
6390 kvm_mmu_sync_roots(vcpu);
6391 kvm_mmu_flush_tlb(vcpu);
6392 nested_vmx_succeed(vcpu);
6393 break;
6394 default:
6395 BUG_ON(1);
6396 break;
6397 }
6398
6399 skip_emulated_instruction(vcpu);
6400 return 1;
6401}
6402
6aa8b732
AK		 6403/*
6404 * The exit handlers return 1 if the exit was handled fully and guest execution
6405 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6406 * to be done to userspace and return 0.
6407 */
772e0318 6408static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6409 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6410 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6411 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6412 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6413 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6414 [EXIT_REASON_CR_ACCESS] = handle_cr,
6415 [EXIT_REASON_DR_ACCESS] = handle_dr,
6416 [EXIT_REASON_CPUID] = handle_cpuid,
6417 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6418 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6419 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6420 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6421 [EXIT_REASON_INVD] = handle_invd,
a7052897 6422 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6423 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6424 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6425 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6426 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6427 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6428 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6429 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6430 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6431 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6432 [EXIT_REASON_VMOFF] = handle_vmoff,
6433 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6434 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6435 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6436 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6437 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6438 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6439 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6440 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6441 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6442 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6443 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6444 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6445 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6446 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6447 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6448};
6449
6450static const int kvm_vmx_max_exit_handlers =
50a3485c 6451 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6452
908a7bdd
JK		 6453static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6454 struct vmcs12 *vmcs12)
6455{
6456 unsigned long exit_qualification;
6457 gpa_t bitmap, last_bitmap;
6458 unsigned int port;
6459 int size;
6460 u8 b;
6461
6462 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6463 return 1;
6464
6465 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6466 return 0;
6467
6468 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6469
6470 port = exit_qualification >> 16;
6471 size = (exit_qualification & 7) + 1;
6472
6473 last_bitmap = (gpa_t)-1;
6474 b = -1;
6475
6476 while (size > 0) {
6477 if (port < 0x8000)
6478 bitmap = vmcs12->io_bitmap_a;
6479 else if (port < 0x10000)
6480 bitmap = vmcs12->io_bitmap_b;
6481 else
6482 return 1;
6483 bitmap += (port & 0x7fff) / 8;
6484
6485 if (last_bitmap != bitmap)
6486 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6487 return 1;
6488 if (b & (1 << (port & 7)))
6489 return 1;
6490
6491 port++;
6492 size--;
6493 last_bitmap = bitmap;
6494 }
6495
6496 return 0;
6497}
6498
644d711a
NHE		 6499/*
6500 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6501 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6502 * disinterest in the current event (read or write a specific MSR) by using an
6503 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6504 */
6505static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6506 struct vmcs12 *vmcs12, u32 exit_reason)
6507{
6508 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6509 gpa_t bitmap;
6510
cbd29cb6 6511 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6512 return 1;
6513
6514 /*
6515 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6516 * for the four combinations of read/write and low/high MSR numbers.
6517 * First we need to figure out which of the four to use:
6518 */
6519 bitmap = vmcs12->msr_bitmap;
6520 if (exit_reason == EXIT_REASON_MSR_WRITE)
6521 bitmap += 2048;
6522 if (msr_index >= 0xc0000000) {
6523 msr_index -= 0xc0000000;
6524 bitmap += 1024;
6525 }
6526
6527 /* Then read the msr_index'th bit from this bitmap: */
6528 if (msr_index < 1024*8) {
6529 unsigned char b;
bd31a7f5
JK		 6530 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6531 return 1;
644d711a
NHE		 6532 return 1 & (b >> (msr_index & 7));
6533 } else
6534 return 1; /* let L1 handle the wrong parameter */
6535}
6536
6537/*
6538 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6539 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6540 * intercept (via guest_host_mask etc.) the current event.
6541 */
6542static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6543 struct vmcs12 *vmcs12)
6544{
6545 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6546 int cr = exit_qualification & 15;
6547 int reg = (exit_qualification >> 8) & 15;
6548 unsigned long val = kvm_register_read(vcpu, reg);
6549
6550 switch ((exit_qualification >> 4) & 3) {
6551 case 0: /* mov to cr */
6552 switch (cr) {
6553 case 0:
6554 if (vmcs12->cr0_guest_host_mask &
6555 (val ^ vmcs12->cr0_read_shadow))
6556 return 1;
6557 break;
6558 case 3:
6559 if ((vmcs12->cr3_target_count >= 1 &&
6560 vmcs12->cr3_target_value0 == val) ||
6561 (vmcs12->cr3_target_count >= 2 &&
6562 vmcs12->cr3_target_value1 == val) ||
6563 (vmcs12->cr3_target_count >= 3 &&
6564 vmcs12->cr3_target_value2 == val) ||
6565 (vmcs12->cr3_target_count >= 4 &&
6566 vmcs12->cr3_target_value3 == val))
6567 return 0;
6568 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6569 return 1;
6570 break;
6571 case 4:
6572 if (vmcs12->cr4_guest_host_mask &
6573 (vmcs12->cr4_read_shadow ^ val))
6574 return 1;
6575 break;
6576 case 8:
6577 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6578 return 1;
6579 break;
6580 }
6581 break;
6582 case 2: /* clts */
6583 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6584 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6585 return 1;
6586 break;
6587 case 1: /* mov from cr */
6588 switch (cr) {
6589 case 3:
6590 if (vmcs12->cpu_based_vm_exec_control &
6591 CPU_BASED_CR3_STORE_EXITING)
6592 return 1;
6593 break;
6594 case 8:
6595 if (vmcs12->cpu_based_vm_exec_control &
6596 CPU_BASED_CR8_STORE_EXITING)
6597 return 1;
6598 break;
6599 }
6600 break;
6601 case 3: /* lmsw */
6602 /*
6603 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6604 * cr0. Other attempted changes are ignored, with no exit.
6605 */
6606 if (vmcs12->cr0_guest_host_mask & 0xe &
6607 (val ^ vmcs12->cr0_read_shadow))
6608 return 1;
6609 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6610 !(vmcs12->cr0_read_shadow & 0x1) &&
6611 (val & 0x1))
6612 return 1;
6613 break;
6614 }
6615 return 0;
6616}
6617
6618/*
6619 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6620 * should handle it ourselves in L0 (and then continue L2). Only call this
6621 * when in is_guest_mode (L2).
6622 */
6623static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6624{
644d711a
NHE		 6625 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6626 struct vcpu_vmx *vmx = to_vmx(vcpu);
6627 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6628 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6629
6630 if (vmx->nested.nested_run_pending)
6631 return 0;
6632
6633 if (unlikely(vmx->fail)) {
bd80158a
JK		 6634 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6635 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6636 return 1;
6637 }
6638
6639 switch (exit_reason) {
6640 case EXIT_REASON_EXCEPTION_NMI:
6641 if (!is_exception(intr_info))
6642 return 0;
6643 else if (is_page_fault(intr_info))
6644 return enable_ept;
6645 return vmcs12->exception_bitmap &
6646 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6647 case EXIT_REASON_EXTERNAL_INTERRUPT:
6648 return 0;
6649 case EXIT_REASON_TRIPLE_FAULT:
6650 return 1;
6651 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6652 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6653 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6654 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6655 case EXIT_REASON_TASK_SWITCH:
6656 return 1;
6657 case EXIT_REASON_CPUID:
6658 return 1;
6659 case EXIT_REASON_HLT:
6660 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6661 case EXIT_REASON_INVD:
6662 return 1;
6663 case EXIT_REASON_INVLPG:
6664 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6665 case EXIT_REASON_RDPMC:
6666 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6667 case EXIT_REASON_RDTSC:
6668 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6669 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6670 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6671 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6672 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6673 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6674 case EXIT_REASON_INVEPT:
644d711a
NHE		 6675 /*
6676 * VMX instructions trap unconditionally. This allows L1 to
6677 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6678 */
6679 return 1;
6680 case EXIT_REASON_CR_ACCESS:
6681 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6682 case EXIT_REASON_DR_ACCESS:
6683 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6684 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6685 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6686 case EXIT_REASON_MSR_READ:
6687 case EXIT_REASON_MSR_WRITE:
6688 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6689 case EXIT_REASON_INVALID_STATE:
6690 return 1;
6691 case EXIT_REASON_MWAIT_INSTRUCTION:
6692 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6693 case EXIT_REASON_MONITOR_INSTRUCTION:
6694 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6695 case EXIT_REASON_PAUSE_INSTRUCTION:
6696 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6697 nested_cpu_has2(vmcs12,
6698 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6699 case EXIT_REASON_MCE_DURING_VMENTRY:
6700 return 0;
6701 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6702 return 1;
6703 case EXIT_REASON_APIC_ACCESS:
6704 return nested_cpu_has2(vmcs12,
6705 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6706 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6707 /*
6708 * L0 always deals with the EPT violation. If nested EPT is
6709 * used, and the nested mmu code discovers that the address is
6710 * missing in the guest EPT table (EPT12), the EPT violation
6711 * will be injected with nested_ept_inject_page_fault()
6712 */
6713 return 0;
644d711a 6714 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6715 /*
6716 * L2 never uses directly L1's EPT, but rather L0's own EPT
6717 * table (shadow on EPT) or a merged EPT table that L0 built
6718 * (EPT on EPT). So any problems with the structure of the
6719 * table is L0's fault.
6720 */
644d711a 6721 return 0;
0238ea91
JK		 6722 case EXIT_REASON_PREEMPTION_TIMER:
6723 return vmcs12->pin_based_vm_exec_control &
6724 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6725 case EXIT_REASON_WBINVD:
6726 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6727 case EXIT_REASON_XSETBV:
6728 return 1;
6729 default:
6730 return 1;
6731 }
6732}
6733
586f9607
AK		 6734static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6735{
6736 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6737 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6738}
6739
7854cbca
ACL		 6740static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6741{
6742 u64 delta_tsc_l1;
6743 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6744
6745 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6746 PIN_BASED_VMX_PREEMPTION_TIMER))
6747 return;
6748 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6749 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6750 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6751 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6752 - vcpu->arch.last_guest_tsc;
6753 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6754 if (preempt_val_l2 <= preempt_val_l1)
6755 preempt_val_l2 = 0;
6756 else
6757 preempt_val_l2 -= preempt_val_l1;
6758 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6759}
6760
6aa8b732
AK		 6761/*
6762 * The guest has exited. See if we can fix it or if we need userspace
6763 * assistance.
6764 */
851ba692 6765static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6766{
29bd8a78 6767 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6768 u32 exit_reason = vmx->exit_reason;
1155f76a 6769 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6770
80ced186 6771 /* If guest state is invalid, start emulating */
14168786 6772 if (vmx->emulation_required)
80ced186 6773 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6774
644d711a
NHE		 6775 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6776 nested_vmx_vmexit(vcpu);
6777 return 1;
6778 }
6779
5120702e
MG		 6780 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6781 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6782 vcpu->run->fail_entry.hardware_entry_failure_reason
6783 = exit_reason;
6784 return 0;
6785 }
6786
29bd8a78 6787 if (unlikely(vmx->fail)) {
851ba692
AK		 6788 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6789 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6790 = vmcs_read32(VM_INSTRUCTION_ERROR);
6791 return 0;
6792 }
6aa8b732 6793
b9bf6882
XG		 6794 /*
6795 * Note:
6796 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6797 * delivery event since it indicates guest is accessing MMIO.
6798 * The vm-exit can be triggered again after return to guest that
6799 * will cause infinite loop.
6800 */
d77c26fc 6801 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6802 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6803 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6804 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6805 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6806 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6807 vcpu->run->internal.ndata = 2;
6808 vcpu->run->internal.data[0] = vectoring_info;
6809 vcpu->run->internal.data[1] = exit_reason;
6810 return 0;
6811 }
3b86cd99 6812
644d711a
NHE		 6813 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6814 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6815 get_vmcs12(vcpu))))) {
c4282df9 6816 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6817 vmx->soft_vnmi_blocked = 0;
3b86cd99 6818 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6819 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6820 /*
6821 * This CPU don't support us in finding the end of an
6822 * NMI-blocked window if the guest runs with IRQs
6823 * disabled. So we pull the trigger after 1 s of
6824 * futile waiting, but inform the user about this.
6825 */
6826 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6827 "state on VCPU %d after 1 s timeout\n",
6828 __func__, vcpu->vcpu_id);
6829 vmx->soft_vnmi_blocked = 0;
3b86cd99 6830 }
3b86cd99
JK		 6831 }
6832
6aa8b732
AK		 6833 if (exit_reason < kvm_vmx_max_exit_handlers
6834 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6835 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6836 else {
851ba692
AK		 6837 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6838 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6839 }
6840 return 0;
6841}
6842
95ba8273 6843static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6844{
95ba8273 6845 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6846 vmcs_write32(TPR_THRESHOLD, 0);
6847 return;
6848 }
6849
95ba8273 6850 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6851}
6852
8d14695f
YZ		 6853static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6854{
6855 u32 sec_exec_control;
6856
6857 /*
6858 * There is not point to enable virtualize x2apic without enable
6859 * apicv
6860 */
c7c9c56c
YZ		 6861 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6862 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6863 return;
6864
6865 if (!vm_need_tpr_shadow(vcpu->kvm))
6866 return;
6867
6868 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6869
6870 if (set) {
6871 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6872 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6873 } else {
6874 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6875 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6876 }
6877 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6878
6879 vmx_set_msr_bitmap(vcpu);
6880}
6881
c7c9c56c
YZ		 6882static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6883{
6884 u16 status;
6885 u8 old;
6886
6887 if (!vmx_vm_has_apicv(kvm))
6888 return;
6889
6890 if (isr == -1)
6891 isr = 0;
6892
6893 status = vmcs_read16(GUEST_INTR_STATUS);
6894 old = status >> 8;
6895 if (isr != old) {
6896 status &= 0xff;
6897 status |= isr << 8;
6898 vmcs_write16(GUEST_INTR_STATUS, status);
6899 }
6900}
6901
6902static void vmx_set_rvi(int vector)
6903{
6904 u16 status;
6905 u8 old;
6906
6907 status = vmcs_read16(GUEST_INTR_STATUS);
6908 old = (u8)status & 0xff;
6909 if ((u8)vector != old) {
6910 status &= ~0xff;
6911 status |= (u8)vector;
6912 vmcs_write16(GUEST_INTR_STATUS, status);
6913 }
6914}
6915
6916static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6917{
6918 if (max_irr == -1)
6919 return;
6920
6921 vmx_set_rvi(max_irr);
6922}
6923
6924static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6925{
3d81bc7e
YZ		 6926 if (!vmx_vm_has_apicv(vcpu->kvm))
6927 return;
6928
c7c9c56c
YZ		 6929 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6930 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6931 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6932 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6933}
6934
51aa01d1 6935static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6936{
00eba012
AK		 6937 u32 exit_intr_info;
6938
6939 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6940 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6941 return;
6942
c5ca8e57 6943 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6944 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6945
6946 /* Handle machine checks before interrupts are enabled */
00eba012 6947 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6948 kvm_machine_check();
6949
20f65983 6950 /* We need to handle NMIs before interrupts are enabled */
00eba012 6951 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6952 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6953 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6954 asm("int $2");
ff9d07a0
ZY		 6955 kvm_after_handle_nmi(&vmx->vcpu);
6956 }
51aa01d1 6957}
20f65983 6958
a547c6db
YZ		 6959static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6960{
6961 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6962
6963 /*
6964 * If external interrupt exists, IF bit is set in rflags/eflags on the
6965 * interrupt stack frame, and interrupt will be enabled on a return
6966 * from interrupt handler.
6967 */
6968 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6969 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6970 unsigned int vector;
6971 unsigned long entry;
6972 gate_desc *desc;
6973 struct vcpu_vmx *vmx = to_vmx(vcpu);
6974#ifdef CONFIG_X86_64
6975 unsigned long tmp;
6976#endif
6977
6978 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6979 desc = (gate_desc *)vmx->host_idt_base + vector;
6980 entry = gate_offset(*desc);
6981 asm volatile(
6982#ifdef CONFIG_X86_64
6983 "mov %%" _ASM_SP ", %[sp]\n\t"
6984 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6985 "push $%c[ss]\n\t"
6986 "push %[sp]\n\t"
6987#endif
6988 "pushf\n\t"
6989 "orl $0x200, (%%" _ASM_SP ")\n\t"
6990 __ASM_SIZE(push) " $%c[cs]\n\t"
6991 "call *%[entry]\n\t"
6992 :
6993#ifdef CONFIG_X86_64
6994 [sp]"=&r"(tmp)
6995#endif
6996 :
6997 [entry]"r"(entry),
6998 [ss]"i"(__KERNEL_DS),
6999 [cs]"i"(__KERNEL_CS)
7000 );
7001 } else
7002 local_irq_enable();
7003}
7004
51aa01d1
AK		 7005static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7006{
c5ca8e57 7007 u32 exit_intr_info;
51aa01d1
AK		 7008 bool unblock_nmi;
7009 u8 vector;
7010 bool idtv_info_valid;
7011
7012 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7013
cf393f75 7014 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7015 if (vmx->nmi_known_unmasked)
7016 return;
c5ca8e57
AK		 7017 /*
7018 * Can't use vmx->exit_intr_info since we're not sure what
7019 * the exit reason is.
7020 */
7021 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7022 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7023 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7024 /*
7b4a25cb 7025 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7026 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7027 * a guest IRET fault.
7b4a25cb
GN		 7028 * SDM 3: 23.2.2 (September 2008)
7029 * Bit 12 is undefined in any of the following cases:
7030 * If the VM exit sets the valid bit in the IDT-vectoring
7031 * information field.
7032 * If the VM exit is due to a double fault.
cf393f75 7033 */
7b4a25cb
GN		 7034 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7035 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7036 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7037 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7038 else
7039 vmx->nmi_known_unmasked =
7040 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7041 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7042 } else if (unlikely(vmx->soft_vnmi_blocked))
7043 vmx->vnmi_blocked_time +=
7044 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7045}
7046
3ab66e8a 7047static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7048 u32 idt_vectoring_info,
7049 int instr_len_field,
7050 int error_code_field)
51aa01d1 7051{
51aa01d1
AK		 7052 u8 vector;
7053 int type;
7054 bool idtv_info_valid;
7055
7056 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7057
3ab66e8a
JK		 7058 vcpu->arch.nmi_injected = false;
7059 kvm_clear_exception_queue(vcpu);
7060 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7061
7062 if (!idtv_info_valid)
7063 return;
7064
3ab66e8a 7065 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7066
668f612f
AK		 7067 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7068 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7069
64a7ec06 7070 switch (type) {
37b96e98 7071 case INTR_TYPE_NMI_INTR:
3ab66e8a 7072 vcpu->arch.nmi_injected = true;
668f612f 7073 /*
7b4a25cb 7074 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7075 * Clear bit "block by NMI" before VM entry if a NMI
7076 * delivery faulted.
668f612f 7077 */
3ab66e8a 7078 vmx_set_nmi_mask(vcpu, false);
37b96e98 7079 break;
37b96e98 7080 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7081 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7082 /* fall through */
7083 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7084 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7085 u32 err = vmcs_read32(error_code_field);
851eb667 7086 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7087 } else
851eb667 7088 kvm_requeue_exception(vcpu, vector);
37b96e98 7089 break;
66fd3f7f 7090 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7091 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7092 /* fall through */
37b96e98 7093 case INTR_TYPE_EXT_INTR:
3ab66e8a 7094 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7095 break;
7096 default:
7097 break;
f7d9238f 7098 }
cf393f75
AK		 7099}
7100
83422e17
AK		 7101static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7102{
3ab66e8a 7103 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7104 VM_EXIT_INSTRUCTION_LEN,
7105 IDT_VECTORING_ERROR_CODE);
7106}
7107
b463a6f7
AK		 7108static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7109{
3ab66e8a 7110 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7111 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7112 VM_ENTRY_INSTRUCTION_LEN,
7113 VM_ENTRY_EXCEPTION_ERROR_CODE);
7114
7115 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7116}
7117
d7cd9796
GN		 7118static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7119{
7120 int i, nr_msrs;
7121 struct perf_guest_switch_msr *msrs;
7122
7123 msrs = perf_guest_get_msrs(&nr_msrs);
7124
7125 if (!msrs)
7126 return;
7127
7128 for (i = 0; i < nr_msrs; i++)
7129 if (msrs[i].host == msrs[i].guest)
7130 clear_atomic_switch_msr(vmx, msrs[i].msr);
7131 else
7132 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7133 msrs[i].host);
7134}
7135
a3b5ba49 7136static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7137{
a2fa3e9f 7138 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7139 unsigned long debugctlmsr;
104f226b
AK		 7140
7141 /* Record the guest's net vcpu time for enforced NMI injections. */
7142 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7143 vmx->entry_time = ktime_get();
7144
7145 /* Don't enter VMX if guest state is invalid, let the exit handler
7146 start emulation until we arrive back to a valid state */
14168786 7147 if (vmx->emulation_required)
104f226b
AK		 7148 return;
7149
012f83cb
AG		 7150 if (vmx->nested.sync_shadow_vmcs) {
7151 copy_vmcs12_to_shadow(vmx);
7152 vmx->nested.sync_shadow_vmcs = false;
7153 }
7154
104f226b
AK		 7155 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7156 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7157 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7158 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7159
7160 /* When single-stepping over STI and MOV SS, we must clear the
7161 * corresponding interruptibility bits in the guest state. Otherwise
7162 * vmentry fails as it then expects bit 14 (BS) in pending debug
7163 * exceptions being set, but that's not correct for the guest debugging
7164 * case. */
7165 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7166 vmx_set_interrupt_shadow(vcpu, 0);
7167
d7cd9796 7168 atomic_switch_perf_msrs(vmx);
2a7921b7 7169 debugctlmsr = get_debugctlmsr();
d7cd9796 7170
7854cbca
ACL		 7171 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7172 nested_adjust_preemption_timer(vcpu);
d462b819 7173 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7174 asm(
6aa8b732 7175 /* Store host registers */
b188c81f
AK		 7176 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7177 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7178 "push %%" _ASM_CX " \n\t"
7179 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7180 "je 1f \n\t"
b188c81f 7181 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7182 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7183 "1: \n\t"
d3edefc0 7184 /* Reload cr2 if changed */
b188c81f
AK		 7185 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7186 "mov %%cr2, %%" _ASM_DX " \n\t"
7187 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7188 "je 2f \n\t"
b188c81f 7189 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7190 "2: \n\t"
6aa8b732 7191 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7192 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7193 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7194 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7195 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7196 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7197 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7198 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7199 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7200#ifdef CONFIG_X86_64
e08aa78a
AK		 7201 "mov %c[r8](%0), %%r8 \n\t"
7202 "mov %c[r9](%0), %%r9 \n\t"
7203 "mov %c[r10](%0), %%r10 \n\t"
7204 "mov %c[r11](%0), %%r11 \n\t"
7205 "mov %c[r12](%0), %%r12 \n\t"
7206 "mov %c[r13](%0), %%r13 \n\t"
7207 "mov %c[r14](%0), %%r14 \n\t"
7208 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7209#endif
b188c81f 7210 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7211
6aa8b732 7212 /* Enter guest mode */
83287ea4 7213 "jne 1f \n\t"
4ecac3fd 7214 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7215 "jmp 2f \n\t"
7216 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7217 "2: "
6aa8b732 7218 /* Save guest registers, load host registers, keep flags */
b188c81f 7219 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7220 "pop %0 \n\t"
b188c81f
AK		 7221 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7222 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7223 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7224 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7225 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7226 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7227 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7228#ifdef CONFIG_X86_64
e08aa78a
AK		 7229 "mov %%r8, %c[r8](%0) \n\t"
7230 "mov %%r9, %c[r9](%0) \n\t"
7231 "mov %%r10, %c[r10](%0) \n\t"
7232 "mov %%r11, %c[r11](%0) \n\t"
7233 "mov %%r12, %c[r12](%0) \n\t"
7234 "mov %%r13, %c[r13](%0) \n\t"
7235 "mov %%r14, %c[r14](%0) \n\t"
7236 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7237#endif
b188c81f
AK		 7238 "mov %%cr2, %%" _ASM_AX " \n\t"
7239 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7240
b188c81f 7241 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7242 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7243 ".pushsection .rodata \n\t"
7244 ".global vmx_return \n\t"
7245 "vmx_return: " _ASM_PTR " 2b \n\t"
7246 ".popsection"
e08aa78a 7247 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7248 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7249 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7250 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7251 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7252 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7253 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7254 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7255 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7256 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7257 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7258#ifdef CONFIG_X86_64
ad312c7c
ZX		 7259 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7260 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7261 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7262 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7263 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7264 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7265 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7266 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7267#endif
40712fae
AK		 7268 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7269 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7270 : "cc", "memory"
7271#ifdef CONFIG_X86_64
b188c81f 7272 , "rax", "rbx", "rdi", "rsi"
c2036300 7273 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7274#else
7275 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7276#endif
7277 );
6aa8b732 7278
2a7921b7
GN		 7279 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7280 if (debugctlmsr)
7281 update_debugctlmsr(debugctlmsr);
7282
aa67f609
AK		 7283#ifndef CONFIG_X86_64
7284 /*
7285 * The sysexit path does not restore ds/es, so we must set them to
7286 * a reasonable value ourselves.
7287 *
7288 * We can't defer this to vmx_load_host_state() since that function
7289 * may be executed in interrupt context, which saves and restore segments
7290 * around it, nullifying its effect.
7291 */
7292 loadsegment(ds, __USER_DS);
7293 loadsegment(es, __USER_DS);
7294#endif
7295
6de4f3ad 7296 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7297 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7298 | (1 << VCPU_EXREG_CPL)
aff48baa 7299 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7300 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7301 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7302 vcpu->arch.regs_dirty = 0;
7303
1155f76a
AK		 7304 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7305
d462b819 7306 vmx->loaded_vmcs->launched = 1;
1b6269db 7307
51aa01d1 7308 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7309 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7310
e0b890d3
GN		 7311 /*
7312 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7313 * we did not inject a still-pending event to L1 now because of
7314 * nested_run_pending, we need to re-enable this bit.
7315 */
7316 if (vmx->nested.nested_run_pending)
7317 kvm_make_request(KVM_REQ_EVENT, vcpu);
7318
7319 vmx->nested.nested_run_pending = 0;
7320
51aa01d1
AK		 7321 vmx_complete_atomic_exit(vmx);
7322 vmx_recover_nmi_blocking(vmx);
cf393f75 7323 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7324}
7325
6aa8b732
AK		 7326static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7327{
fb3f0f51
RR		 7328 struct vcpu_vmx *vmx = to_vmx(vcpu);
7329
cdbecfc3 7330 free_vpid(vmx);
ec378aee 7331 free_nested(vmx);
d462b819 7332 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7333 kfree(vmx->guest_msrs);
7334 kvm_vcpu_uninit(vcpu);
a4770347 7335 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7336}
7337
fb3f0f51 7338static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7339{
fb3f0f51 7340 int err;
c16f862d 7341 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7342 int cpu;
6aa8b732 7343
a2fa3e9f 7344 if (!vmx)
fb3f0f51
RR		 7345 return ERR_PTR(-ENOMEM);
7346
2384d2b3
SY		 7347 allocate_vpid(vmx);
7348
fb3f0f51
RR		 7349 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7350 if (err)
7351 goto free_vcpu;
965b58a5 7352
a2fa3e9f 7353 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7354 err = -ENOMEM;
fb3f0f51 7355 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7356 goto uninit_vcpu;
7357 }
965b58a5 7358
d462b819
NHE		 7359 vmx->loaded_vmcs = &vmx->vmcs01;
7360 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7361 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7362 goto free_msrs;
d462b819
NHE		 7363 if (!vmm_exclusive)
7364 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7365 loaded_vmcs_init(vmx->loaded_vmcs);
7366 if (!vmm_exclusive)
7367 kvm_cpu_vmxoff();
a2fa3e9f 7368
15ad7146
AK		 7369 cpu = get_cpu();
7370 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7371 vmx->vcpu.cpu = cpu;
8b9cf98c 7372 err = vmx_vcpu_setup(vmx);
fb3f0f51 7373 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7374 put_cpu();
fb3f0f51
RR		 7375 if (err)
7376 goto free_vmcs;
a63cb560 7377 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7378 err = alloc_apic_access_page(kvm);
7379 if (err)
5e4a0b3c 7380 goto free_vmcs;
a63cb560 7381 }
fb3f0f51 7382
b927a3ce
SY		 7383 if (enable_ept) {
7384 if (!kvm->arch.ept_identity_map_addr)
7385 kvm->arch.ept_identity_map_addr =
7386 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7387 err = -ENOMEM;
b7ebfb05
SY		 7388 if (alloc_identity_pagetable(kvm) != 0)
7389 goto free_vmcs;
93ea5388
GN		 7390 if (!init_rmode_identity_map(kvm))
7391 goto free_vmcs;
b927a3ce 7392 }
b7ebfb05 7393
a9d30f33
NHE		 7394 vmx->nested.current_vmptr = -1ull;
7395 vmx->nested.current_vmcs12 = NULL;
7396
fb3f0f51
RR		 7397 return &vmx->vcpu;
7398
7399free_vmcs:
5f3fbc34 7400 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7401free_msrs:
fb3f0f51
RR		 7402 kfree(vmx->guest_msrs);
7403uninit_vcpu:
7404 kvm_vcpu_uninit(&vmx->vcpu);
7405free_vcpu:
cdbecfc3 7406 free_vpid(vmx);
a4770347 7407 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7408 return ERR_PTR(err);
6aa8b732
AK		 7409}
7410
002c7f7c
YS		 7411static void __init vmx_check_processor_compat(void *rtn)
7412{
7413 struct vmcs_config vmcs_conf;
7414
7415 *(int *)rtn = 0;
7416 if (setup_vmcs_config(&vmcs_conf) < 0)
7417 *(int *)rtn = -EIO;
7418 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7419 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7420 smp_processor_id());
7421 *(int *)rtn = -EIO;
7422 }
7423}
7424
67253af5
SY		 7425static int get_ept_level(void)
7426{
7427 return VMX_EPT_DEFAULT_GAW + 1;
7428}
7429
4b12f0de 7430static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7431{
4b12f0de
SY		 7432 u64 ret;
7433
522c68c4
SY		 7434 /* For VT-d and EPT combination
7435 * 1. MMIO: always map as UC
7436 * 2. EPT with VT-d:
7437 * a. VT-d without snooping control feature: can't guarantee the
7438 * result, try to trust guest.
7439 * b. VT-d with snooping control feature: snooping control feature of
7440 * VT-d engine can guarantee the cache correctness. Just set it
7441 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7442 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7443 * consistent with host MTRR
7444 */
4b12f0de
SY		 7445 if (is_mmio)
7446 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7447 else if (vcpu->kvm->arch.iommu_domain &&
7448 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7449 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7450 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7451 else
522c68c4 7452 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7453 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7454
7455 return ret;
64d4d521
SY		 7456}
7457
17cc3935 7458static int vmx_get_lpage_level(void)
344f414f 7459{
878403b7
SY		 7460 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7461 return PT_DIRECTORY_LEVEL;
7462 else
7463 /* For shadow and EPT supported 1GB page */
7464 return PT_PDPE_LEVEL;
344f414f
JR		 7465}
7466
0e851880
SY		 7467static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7468{
4e47c7a6
SY		 7469 struct kvm_cpuid_entry2 *best;
7470 struct vcpu_vmx *vmx = to_vmx(vcpu);
7471 u32 exec_control;
7472
7473 vmx->rdtscp_enabled = false;
7474 if (vmx_rdtscp_supported()) {
7475 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7476 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7477 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7478 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7479 vmx->rdtscp_enabled = true;
7480 else {
7481 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7482 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7483 exec_control);
7484 }
7485 }
7486 }
ad756a16 7487
ad756a16
MJ		 7488 /* Exposing INVPCID only when PCID is exposed */
7489 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7490 if (vmx_invpcid_supported() &&
4f977045 7491 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7492 guest_cpuid_has_pcid(vcpu)) {
29282fde 7493 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7494 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7495 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7496 exec_control);
7497 } else {
29282fde
TI		 7498 if (cpu_has_secondary_exec_ctrls()) {
7499 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7500 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7501 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7502 exec_control);
7503 }
ad756a16 7504 if (best)
4f977045 7505 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7506 }
0e851880
SY		 7507}
7508
d4330ef2
JR		 7509static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7510{
7b8050f5
NHE		 7511 if (func == 1 && nested)
7512 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7513}
7514
25d92081
YZ		 7515static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7516 struct x86_exception *fault)
7517{
7518 struct vmcs12 *vmcs12;
7519 nested_vmx_vmexit(vcpu);
7520 vmcs12 = get_vmcs12(vcpu);
7521
7522 if (fault->error_code & PFERR_RSVD_MASK)
7523 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7524 else
7525 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7526 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7527 vmcs12->guest_physical_address = fault->address;
7528}
7529
155a97a3
NHE		 7530/* Callbacks for nested_ept_init_mmu_context: */
7531
7532static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7533{
7534 /* return the page table to be shadowed - in our case, EPT12 */
7535 return get_vmcs12(vcpu)->ept_pointer;
7536}
7537
8a3c1a33 7538static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7539{
8a3c1a33 7540 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7541 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7542
7543 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7544 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7545 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7546
7547 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7548}
7549
7550static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7551{
7552 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7553}
7554
feaf0c7d
GN		 7555static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7556 struct x86_exception *fault)
7557{
7558 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7559
7560 WARN_ON(!is_guest_mode(vcpu));
7561
7562 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7563 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7564 nested_vmx_vmexit(vcpu);
7565 else
7566 kvm_inject_page_fault(vcpu, fault);
7567}
7568
fe3ef05c
NHE		 7569/*
7570 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7571 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7572 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7573 * guest in a way that will both be appropriate to L1's requests, and our
7574 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7575 * function also has additional necessary side-effects, like setting various
7576 * vcpu->arch fields.
7577 */
7578static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7579{
7580 struct vcpu_vmx *vmx = to_vmx(vcpu);
7581 u32 exec_control;
7854cbca 7582 u32 exit_control;
fe3ef05c
NHE		 7583
7584 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7585 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7586 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7587 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7588 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7589 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7590 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7591 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7592 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7593 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7594 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7595 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7596 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7597 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7598 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7599 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7600 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7601 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7602 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7603 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7604 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7605 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7606 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7607 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7608 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7609 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7610 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7611 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7612 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7613 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7614 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7615 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7616 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7617 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7618 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7619 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7620
7621 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7622 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7623 vmcs12->vm_entry_intr_info_field);
7624 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7625 vmcs12->vm_entry_exception_error_code);
7626 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7627 vmcs12->vm_entry_instruction_len);
7628 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7629 vmcs12->guest_interruptibility_info);
fe3ef05c 7630 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7631 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7632 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7633 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7634 vmcs12->guest_pending_dbg_exceptions);
7635 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7636 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7637
7638 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7639
7640 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7641 (vmcs_config.pin_based_exec_ctrl |
7642 vmcs12->pin_based_vm_exec_control));
7643
0238ea91
JK		 7644 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7645 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7646 vmcs12->vmx_preemption_timer_value);
7647
fe3ef05c
NHE		 7648 /*
7649 * Whether page-faults are trapped is determined by a combination of
7650 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7651 * If enable_ept, L0 doesn't care about page faults and we should
7652 * set all of these to L1's desires. However, if !enable_ept, L0 does
7653 * care about (at least some) page faults, and because it is not easy
7654 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7655 * to exit on each and every L2 page fault. This is done by setting
7656 * MASK=MATCH=0 and (see below) EB.PF=1.
7657 * Note that below we don't need special code to set EB.PF beyond the
7658 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7659 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7660 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7661 *
7662 * A problem with this approach (when !enable_ept) is that L1 may be
7663 * injected with more page faults than it asked for. This could have
7664 * caused problems, but in practice existing hypervisors don't care.
7665 * To fix this, we will need to emulate the PFEC checking (on the L1
7666 * page tables), using walk_addr(), when injecting PFs to L1.
7667 */
7668 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7669 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7670 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7671 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7672
7673 if (cpu_has_secondary_exec_ctrls()) {
7674 u32 exec_control = vmx_secondary_exec_control(vmx);
7675 if (!vmx->rdtscp_enabled)
7676 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7677 /* Take the following fields only from vmcs12 */
7678 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7679 if (nested_cpu_has(vmcs12,
7680 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7681 exec_control |= vmcs12->secondary_vm_exec_control;
7682
7683 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7684 /*
7685 * Translate L1 physical address to host physical
7686 * address for vmcs02. Keep the page pinned, so this
7687 * physical address remains valid. We keep a reference
7688 * to it so we can release it later.
7689 */
7690 if (vmx->nested.apic_access_page) /* shouldn't happen */
7691 nested_release_page(vmx->nested.apic_access_page);
7692 vmx->nested.apic_access_page =
7693 nested_get_page(vcpu, vmcs12->apic_access_addr);
7694 /*
7695 * If translation failed, no matter: This feature asks
7696 * to exit when accessing the given address, and if it
7697 * can never be accessed, this feature won't do
7698 * anything anyway.
7699 */
7700 if (!vmx->nested.apic_access_page)
7701 exec_control &=
7702 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7703 else
7704 vmcs_write64(APIC_ACCESS_ADDR,
7705 page_to_phys(vmx->nested.apic_access_page));
7706 }
7707
7708 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7709 }
7710
7711
7712 /*
7713 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7714 * Some constant fields are set here by vmx_set_constant_host_state().
7715 * Other fields are different per CPU, and will be set later when
7716 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7717 */
a547c6db 7718 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7719
7720 /*
7721 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7722 * entry, but only if the current (host) sp changed from the value
7723 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7724 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7725 * here we just force the write to happen on entry.
7726 */
7727 vmx->host_rsp = 0;
7728
7729 exec_control = vmx_exec_control(vmx); /* L0's desires */
7730 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7731 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7732 exec_control &= ~CPU_BASED_TPR_SHADOW;
7733 exec_control |= vmcs12->cpu_based_vm_exec_control;
7734 /*
7735 * Merging of IO and MSR bitmaps not currently supported.
7736 * Rather, exit every time.
7737 */
7738 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7739 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7740 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7741
7742 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7743
7744 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7745 * bitwise-or of what L1 wants to trap for L2, and what we want to
7746 * trap. Note that CR0.TS also needs updating - we do this later.
7747 */
7748 update_exception_bitmap(vcpu);
7749 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7750 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7751
8049d651
NHE		 7752 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7753 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7754 * bits are further modified by vmx_set_efer() below.
7755 */
7854cbca
ACL		 7756 exit_control = vmcs_config.vmexit_ctrl;
7757 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7758 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7759 vmcs_write32(VM_EXIT_CONTROLS, exit_control);
8049d651
NHE		 7760
7761 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7762 * emulated by vmx_set_efer(), below.
7763 */
7764 vmcs_write32(VM_ENTRY_CONTROLS,
7765 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7766 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7767 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7768
44811c02 7769 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7770 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7771 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7772 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7773 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7774
7775
7776 set_cr4_guest_host_mask(vmx);
7777
27fc51b2
NHE		 7778 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7779 vmcs_write64(TSC_OFFSET,
7780 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7781 else
7782 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7783
7784 if (enable_vpid) {
7785 /*
7786 * Trivially support vpid by letting L2s share their parent
7787 * L1's vpid. TODO: move to a more elaborate solution, giving
7788 * each L2 its own vpid and exposing the vpid feature to L1.
7789 */
7790 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7791 vmx_flush_tlb(vcpu);
7792 }
7793
155a97a3
NHE		 7794 if (nested_cpu_has_ept(vmcs12)) {
7795 kvm_mmu_unload(vcpu);
7796 nested_ept_init_mmu_context(vcpu);
7797 }
7798
fe3ef05c
NHE		 7799 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7800 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7801 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7802 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7803 else
7804 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7805 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7806 vmx_set_efer(vcpu, vcpu->arch.efer);
7807
7808 /*
7809 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7810 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7811 * The CR0_READ_SHADOW is what L2 should have expected to read given
7812 * the specifications by L1; It's not enough to take
7813 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7814 * have more bits than L1 expected.
7815 */
7816 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7817 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7818
7819 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7820 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7821
7822 /* shadow page tables on either EPT or shadow page tables */
7823 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7824 kvm_mmu_reset_context(vcpu);
7825
feaf0c7d
GN		 7826 if (!enable_ept)
7827 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7828
3633cfc3
NHE		 7829 /*
7830 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7831 */
7832 if (enable_ept) {
7833 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7834 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7835 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7836 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7837 }
7838
fe3ef05c
NHE		 7839 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7840 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7841}
7842
cd232ad0
NHE		 7843/*
7844 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7845 * for running an L2 nested guest.
7846 */
7847static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7848{
7849 struct vmcs12 *vmcs12;
7850 struct vcpu_vmx *vmx = to_vmx(vcpu);
7851 int cpu;
7852 struct loaded_vmcs *vmcs02;
384bb783 7853 bool ia32e;
cd232ad0
NHE		 7854
7855 if (!nested_vmx_check_permission(vcpu) ||
7856 !nested_vmx_check_vmcs12(vcpu))
7857 return 1;
7858
7859 skip_emulated_instruction(vcpu);
7860 vmcs12 = get_vmcs12(vcpu);
7861
012f83cb
AG		 7862 if (enable_shadow_vmcs)
7863 copy_shadow_to_vmcs12(vmx);
7864
7c177938
NHE		 7865 /*
7866 * The nested entry process starts with enforcing various prerequisites
7867 * on vmcs12 as required by the Intel SDM, and act appropriately when
7868 * they fail: As the SDM explains, some conditions should cause the
7869 * instruction to fail, while others will cause the instruction to seem
7870 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7871 * To speed up the normal (success) code path, we should avoid checking
7872 * for misconfigurations which will anyway be caught by the processor
7873 * when using the merged vmcs02.
7874 */
7875 if (vmcs12->launch_state == launch) {
7876 nested_vmx_failValid(vcpu,
7877 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7878 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7879 return 1;
7880 }
7881
26539bd0
PB		 7882 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7883 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7884 return 1;
7885 }
7886
7c177938
NHE		 7887 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7888 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7889 /*TODO: Also verify bits beyond physical address width are 0*/
7890 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7891 return 1;
7892 }
7893
7894 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7895 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7896 /*TODO: Also verify bits beyond physical address width are 0*/
7897 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7898 return 1;
7899 }
7900
7901 if (vmcs12->vm_entry_msr_load_count > 0 ||
7902 vmcs12->vm_exit_msr_load_count > 0 ||
7903 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7904 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7905 __func__);
7c177938
NHE		 7906 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7907 return 1;
7908 }
7909
7910 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7911 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7912 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7913 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7914 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7915 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7916 !vmx_control_verify(vmcs12->vm_exit_controls,
7917 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7918 !vmx_control_verify(vmcs12->vm_entry_controls,
7919 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7920 {
7921 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7922 return 1;
7923 }
7924
7925 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7926 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7927 nested_vmx_failValid(vcpu,
7928 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7929 return 1;
7930 }
7931
92fbc7b1 7932 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7933 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7934 nested_vmx_entry_failure(vcpu, vmcs12,
7935 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7936 return 1;
7937 }
7938 if (vmcs12->vmcs_link_pointer != -1ull) {
7939 nested_vmx_entry_failure(vcpu, vmcs12,
7940 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7941 return 1;
7942 }
7943
384bb783 7944 /*
cb0c8cda 7945 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7946 * are performed on the field for the IA32_EFER MSR:
7947 * - Bits reserved in the IA32_EFER MSR must be 0.
7948 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7949 * the IA-32e mode guest VM-exit control. It must also be identical
7950 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7951 * CR0.PG) is 1.
7952 */
7953 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7954 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7955 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7956 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7957 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7958 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7959 nested_vmx_entry_failure(vcpu, vmcs12,
7960 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7961 return 1;
7962 }
7963 }
7964
7965 /*
7966 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7967 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7968 * the values of the LMA and LME bits in the field must each be that of
7969 * the host address-space size VM-exit control.
7970 */
7971 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7972 ia32e = (vmcs12->vm_exit_controls &
7973 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7974 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7975 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7976 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7977 nested_vmx_entry_failure(vcpu, vmcs12,
7978 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7979 return 1;
7980 }
7981 }
7982
7c177938
NHE		 7983 /*
7984 * We're finally done with prerequisite checking, and can start with
7985 * the nested entry.
7986 */
7987
cd232ad0
NHE		 7988 vmcs02 = nested_get_current_vmcs02(vmx);
7989 if (!vmcs02)
7990 return -ENOMEM;
7991
7992 enter_guest_mode(vcpu);
7993
e0b890d3
GN		 7994 vmx->nested.nested_run_pending = 1;
7995
cd232ad0
NHE		 7996 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7997
7998 cpu = get_cpu();
7999 vmx->loaded_vmcs = vmcs02;
8000 vmx_vcpu_put(vcpu);
8001 vmx_vcpu_load(vcpu, cpu);
8002 vcpu->cpu = cpu;
8003 put_cpu();
8004
36c3cc42
JK		 8005 vmx_segment_cache_clear(vmx);
8006
cd232ad0
NHE		 8007 vmcs12->launch_state = 1;
8008
8009 prepare_vmcs02(vcpu, vmcs12);
8010
8011 /*
8012 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8013 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8014 * returned as far as L1 is concerned. It will only return (and set
8015 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8016 */
8017 return 1;
8018}
8019
4704d0be
NHE		 8020/*
8021 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8022 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8023 * This function returns the new value we should put in vmcs12.guest_cr0.
8024 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8025 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8026 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8027 * didn't trap the bit, because if L1 did, so would L0).
8028 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8029 * been modified by L2, and L1 knows it. So just leave the old value of
8030 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8031 * isn't relevant, because if L0 traps this bit it can set it to anything.
8032 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8033 * changed these bits, and therefore they need to be updated, but L0
8034 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8035 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8036 */
8037static inline unsigned long
8038vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8039{
8040 return
8041 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8042 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8043 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8044 vcpu->arch.cr0_guest_owned_bits));
8045}
8046
8047static inline unsigned long
8048vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8049{
8050 return
8051 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8052 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8053 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8054 vcpu->arch.cr4_guest_owned_bits));
8055}
8056
5f3d5799
JK		 8057static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8058 struct vmcs12 *vmcs12)
8059{
8060 u32 idt_vectoring;
8061 unsigned int nr;
8062
851eb667 8063 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8064 nr = vcpu->arch.exception.nr;
8065 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8066
8067 if (kvm_exception_is_soft(nr)) {
8068 vmcs12->vm_exit_instruction_len =
8069 vcpu->arch.event_exit_inst_len;
8070 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8071 } else
8072 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8073
8074 if (vcpu->arch.exception.has_error_code) {
8075 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8076 vmcs12->idt_vectoring_error_code =
8077 vcpu->arch.exception.error_code;
8078 }
8079
8080 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8081 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8082 vmcs12->idt_vectoring_info_field =
8083 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8084 } else if (vcpu->arch.interrupt.pending) {
8085 nr = vcpu->arch.interrupt.nr;
8086 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8087
8088 if (vcpu->arch.interrupt.soft) {
8089 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8090 vmcs12->vm_entry_instruction_len =
8091 vcpu->arch.event_exit_inst_len;
8092 } else
8093 idt_vectoring |= INTR_TYPE_EXT_INTR;
8094
8095 vmcs12->idt_vectoring_info_field = idt_vectoring;
8096 }
8097}
8098
4704d0be
NHE		 8099/*
8100 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8101 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8102 * and this function updates it to reflect the changes to the guest state while
8103 * L2 was running (and perhaps made some exits which were handled directly by L0
8104 * without going back to L1), and to reflect the exit reason.
8105 * Note that we do not have to copy here all VMCS fields, just those that
8106 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8107 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8108 * which already writes to vmcs12 directly.
8109 */
733568f9 8110static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8111{
8112 /* update guest state fields: */
8113 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8114 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8115
8116 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8117 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8118 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8119 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8120
8121 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8122 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8123 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8124 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8125 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8126 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8127 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8128 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8129 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8130 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8131 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8132 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8133 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8134 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8135 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8136 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8137 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8138 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8139 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8140 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8141 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8142 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8143 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8144 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8145 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8146 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8147 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8148 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8149 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8150 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8151 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8152 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8153 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8154 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8155 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8156 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8157
4704d0be
NHE		 8158 vmcs12->guest_interruptibility_info =
8159 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8160 vmcs12->guest_pending_dbg_exceptions =
8161 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8162
7854cbca
ACL		 8163 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8164 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8165 vmcs12->vmx_preemption_timer_value =
8166 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8167
3633cfc3
NHE		 8168 /*
8169 * In some cases (usually, nested EPT), L2 is allowed to change its
8170 * own CR3 without exiting. If it has changed it, we must keep it.
8171 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8172 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8173 *
8174 * Additionally, restore L2's PDPTR to vmcs12.
8175 */
8176 if (enable_ept) {
8177 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8178 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8179 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8180 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8181 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8182 }
8183
c18911a2
JK		 8184 vmcs12->vm_entry_controls =
8185 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8186 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8187
4704d0be
NHE		 8188 /* TODO: These cannot have changed unless we have MSR bitmaps and
8189 * the relevant bit asks not to trap the change */
8190 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8191 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8192 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8193 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8194 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8195 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8196 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8197 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8198
8199 /* update exit information fields: */
8200
957c897e 8201 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8202 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8203
8204 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8205 if ((vmcs12->vm_exit_intr_info &
8206 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8207 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8208 vmcs12->vm_exit_intr_error_code =
8209 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8210 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8211 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8212 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8213
5f3d5799
JK		 8214 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8215 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8216 * instead of reading the real value. */
4704d0be 8217 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8218
8219 /*
8220 * Transfer the event that L0 or L1 may wanted to inject into
8221 * L2 to IDT_VECTORING_INFO_FIELD.
8222 */
8223 vmcs12_save_pending_event(vcpu, vmcs12);
8224 }
8225
8226 /*
8227 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8228 * preserved above and would only end up incorrectly in L1.
8229 */
8230 vcpu->arch.nmi_injected = false;
8231 kvm_clear_exception_queue(vcpu);
8232 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8233}
8234
8235/*
8236 * A part of what we need to when the nested L2 guest exits and we want to
8237 * run its L1 parent, is to reset L1's guest state to the host state specified
8238 * in vmcs12.
8239 * This function is to be called not only on normal nested exit, but also on
8240 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8241 * Failures During or After Loading Guest State").
8242 * This function should be called when the active VMCS is L1's (vmcs01).
8243 */
733568f9
JK		 8244static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8245 struct vmcs12 *vmcs12)
4704d0be 8246{
21feb4eb
ACL		 8247 struct kvm_segment seg;
8248
4704d0be
NHE		 8249 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8250 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8251 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8252 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8253 else
8254 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8255 vmx_set_efer(vcpu, vcpu->arch.efer);
8256
8257 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8258 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8259 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8260 /*
8261 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8262 * actually changed, because it depends on the current state of
8263 * fpu_active (which may have changed).
8264 * Note that vmx_set_cr0 refers to efer set above.
8265 */
9e3e4dbf 8266 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8267 /*
8268 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8269 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8270 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8271 */
8272 update_exception_bitmap(vcpu);
8273 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8274 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8275
8276 /*
8277 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8278 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8279 */
8280 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8281 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8282
155a97a3
NHE		 8283 if (nested_cpu_has_ept(vmcs12))
8284 nested_ept_uninit_mmu_context(vcpu);
8285
4704d0be
NHE		 8286 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8287 kvm_mmu_reset_context(vcpu);
8288
feaf0c7d
GN		 8289 if (!enable_ept)
8290 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8291
4704d0be
NHE		 8292 if (enable_vpid) {
8293 /*
8294 * Trivially support vpid by letting L2s share their parent
8295 * L1's vpid. TODO: move to a more elaborate solution, giving
8296 * each L2 its own vpid and exposing the vpid feature to L1.
8297 */
8298 vmx_flush_tlb(vcpu);
8299 }
8300
8301
8302 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8303 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8304 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8305 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8306 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8307
44811c02 8308 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8309 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8310 vcpu->arch.pat = vmcs12->host_ia32_pat;
8311 }
4704d0be
NHE		 8312 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8313 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8314 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8315
21feb4eb
ACL		 8316 /* Set L1 segment info according to Intel SDM
8317 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8318 seg = (struct kvm_segment) {
8319 .base = 0,
8320 .limit = 0xFFFFFFFF,
8321 .selector = vmcs12->host_cs_selector,
8322 .type = 11,
8323 .present = 1,
8324 .s = 1,
8325 .g = 1
8326 };
8327 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8328 seg.l = 1;
8329 else
8330 seg.db = 1;
8331 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8332 seg = (struct kvm_segment) {
8333 .base = 0,
8334 .limit = 0xFFFFFFFF,
8335 .type = 3,
8336 .present = 1,
8337 .s = 1,
8338 .db = 1,
8339 .g = 1
8340 };
8341 seg.selector = vmcs12->host_ds_selector;
8342 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8343 seg.selector = vmcs12->host_es_selector;
8344 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8345 seg.selector = vmcs12->host_ss_selector;
8346 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8347 seg.selector = vmcs12->host_fs_selector;
8348 seg.base = vmcs12->host_fs_base;
8349 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8350 seg.selector = vmcs12->host_gs_selector;
8351 seg.base = vmcs12->host_gs_base;
8352 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8353 seg = (struct kvm_segment) {
205befd9 8354 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8355 .limit = 0x67,
8356 .selector = vmcs12->host_tr_selector,
8357 .type = 11,
8358 .present = 1
8359 };
8360 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8361
503cd0c5
JK		 8362 kvm_set_dr(vcpu, 7, 0x400);
8363 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8364}
8365
8366/*
8367 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8368 * and modify vmcs12 to make it see what it would expect to see there if
8369 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8370 */
8371static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8372{
8373 struct vcpu_vmx *vmx = to_vmx(vcpu);
8374 int cpu;
8375 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8376
5f3d5799
JK		 8377 /* trying to cancel vmlaunch/vmresume is a bug */
8378 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8379
4704d0be
NHE		 8380 leave_guest_mode(vcpu);
8381 prepare_vmcs12(vcpu, vmcs12);
8382
8383 cpu = get_cpu();
8384 vmx->loaded_vmcs = &vmx->vmcs01;
8385 vmx_vcpu_put(vcpu);
8386 vmx_vcpu_load(vcpu, cpu);
8387 vcpu->cpu = cpu;
8388 put_cpu();
8389
36c3cc42
JK		 8390 vmx_segment_cache_clear(vmx);
8391
4704d0be
NHE		 8392 /* if no vmcs02 cache requested, remove the one we used */
8393 if (VMCS02_POOL_SIZE == 0)
8394 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8395
8396 load_vmcs12_host_state(vcpu, vmcs12);
8397
27fc51b2 8398 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8399 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8400
8401 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8402 vmx->host_rsp = 0;
8403
8404 /* Unpin physical memory we referred to in vmcs02 */
8405 if (vmx->nested.apic_access_page) {
8406 nested_release_page(vmx->nested.apic_access_page);
8407 vmx->nested.apic_access_page = 0;
8408 }
8409
8410 /*
8411 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8412 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8413 * success or failure flag accordingly.
8414 */
8415 if (unlikely(vmx->fail)) {
8416 vmx->fail = 0;
8417 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8418 } else
8419 nested_vmx_succeed(vcpu);
012f83cb
AG		 8420 if (enable_shadow_vmcs)
8421 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8422}
8423
7c177938
NHE		 8424/*
8425 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8426 * 23.7 "VM-entry failures during or after loading guest state" (this also
8427 * lists the acceptable exit-reason and exit-qualification parameters).
8428 * It should only be called before L2 actually succeeded to run, and when
8429 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8430 */
8431static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8432 struct vmcs12 *vmcs12,
8433 u32 reason, unsigned long qualification)
8434{
8435 load_vmcs12_host_state(vcpu, vmcs12);
8436 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8437 vmcs12->exit_qualification = qualification;
8438 nested_vmx_succeed(vcpu);
012f83cb
AG		 8439 if (enable_shadow_vmcs)
8440 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8441}
8442
8a76d7f2
JR		 8443static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8444 struct x86_instruction_info *info,
8445 enum x86_intercept_stage stage)
8446{
8447 return X86EMUL_CONTINUE;
8448}
8449
cbdd1bea 8450static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8451 .cpu_has_kvm_support = cpu_has_kvm_support,
8452 .disabled_by_bios = vmx_disabled_by_bios,
8453 .hardware_setup = hardware_setup,
8454 .hardware_unsetup = hardware_unsetup,
002c7f7c 8455 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8456 .hardware_enable = hardware_enable,
8457 .hardware_disable = hardware_disable,
04547156 8458 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8459
8460 .vcpu_create = vmx_create_vcpu,
8461 .vcpu_free = vmx_free_vcpu,
04d2cc77 8462 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8463
04d2cc77 8464 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8465 .vcpu_load = vmx_vcpu_load,
8466 .vcpu_put = vmx_vcpu_put,
8467
c8639010 8468 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8469 .get_msr = vmx_get_msr,
8470 .set_msr = vmx_set_msr,
8471 .get_segment_base = vmx_get_segment_base,
8472 .get_segment = vmx_get_segment,
8473 .set_segment = vmx_set_segment,
2e4d2653 8474 .get_cpl = vmx_get_cpl,
6aa8b732 8475 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8476 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8477 .decache_cr3 = vmx_decache_cr3,
25c4c276 8478 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8479 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8480 .set_cr3 = vmx_set_cr3,
8481 .set_cr4 = vmx_set_cr4,
6aa8b732 8482 .set_efer = vmx_set_efer,
6aa8b732
AK		 8483 .get_idt = vmx_get_idt,
8484 .set_idt = vmx_set_idt,
8485 .get_gdt = vmx_get_gdt,
8486 .set_gdt = vmx_set_gdt,
020df079 8487 .set_dr7 = vmx_set_dr7,
5fdbf976 8488 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8489 .get_rflags = vmx_get_rflags,
8490 .set_rflags = vmx_set_rflags,
ebcbab4c 8491 .fpu_activate = vmx_fpu_activate,
02daab21 8492 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8493
8494 .tlb_flush = vmx_flush_tlb,
6aa8b732 8495
6aa8b732 8496 .run = vmx_vcpu_run,
6062d012 8497 .handle_exit = vmx_handle_exit,
6aa8b732 8498 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8499 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8500 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8501 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8502 .set_irq = vmx_inject_irq,
95ba8273 8503 .set_nmi = vmx_inject_nmi,
298101da 8504 .queue_exception = vmx_queue_exception,
b463a6f7 8505 .cancel_injection = vmx_cancel_injection,
78646121 8506 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8507 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8508 .get_nmi_mask = vmx_get_nmi_mask,
8509 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8510 .enable_nmi_window = enable_nmi_window,
8511 .enable_irq_window = enable_irq_window,
8512 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8513 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8514 .vm_has_apicv = vmx_vm_has_apicv,
8515 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8516 .hwapic_irr_update = vmx_hwapic_irr_update,
8517 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8518 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8519 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8520
cbc94022 8521 .set_tss_addr = vmx_set_tss_addr,
67253af5 8522 .get_tdp_level = get_ept_level,
4b12f0de 8523 .get_mt_mask = vmx_get_mt_mask,
229456fc 8524
586f9607 8525 .get_exit_info = vmx_get_exit_info,
586f9607 8526
17cc3935 8527 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8528
8529 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8530
8531 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8532 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8533
8534 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8535
8536 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8537
4051b188 8538 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8539 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8540 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8541 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8542 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8543 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8544
8545 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8546
8547 .check_intercept = vmx_check_intercept,
a547c6db 8548 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8549};
8550
8551static int __init vmx_init(void)
8552{
8d14695f 8553 int r, i, msr;
26bb0981
AK		 8554
8555 rdmsrl_safe(MSR_EFER, &host_efer);
8556
8557 for (i = 0; i < NR_VMX_MSR; ++i)
8558 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8559
3e7c73e9 8560 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8561 if (!vmx_io_bitmap_a)
8562 return -ENOMEM;
8563
2106a548
GC		 8564 r = -ENOMEM;
8565
3e7c73e9 8566 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8567 if (!vmx_io_bitmap_b)
fdef3ad1 8568 goto out;
fdef3ad1 8569
5897297b 8570 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8571 if (!vmx_msr_bitmap_legacy)
25c5f225 8572 goto out1;
2106a548 8573
8d14695f
YZ		 8574 vmx_msr_bitmap_legacy_x2apic =
8575 (unsigned long *)__get_free_page(GFP_KERNEL);
8576 if (!vmx_msr_bitmap_legacy_x2apic)
8577 goto out2;
25c5f225 8578
5897297b 8579 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8580 if (!vmx_msr_bitmap_longmode)
8d14695f 8581 goto out3;
2106a548 8582
8d14695f
YZ		 8583 vmx_msr_bitmap_longmode_x2apic =
8584 (unsigned long *)__get_free_page(GFP_KERNEL);
8585 if (!vmx_msr_bitmap_longmode_x2apic)
8586 goto out4;
4607c2d7
AG		 8587 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8588 if (!vmx_vmread_bitmap)
8589 goto out5;
8590
8591 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8592 if (!vmx_vmwrite_bitmap)
8593 goto out6;
8594
8595 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8596 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8597 /* shadowed read/write fields */
8598 for (i = 0; i < max_shadow_read_write_fields; i++) {
8599 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8600 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8601 }
8602 /* shadowed read only fields */
8603 for (i = 0; i < max_shadow_read_only_fields; i++)
8604 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8605
fdef3ad1
HQ		 8606 /*
8607 * Allow direct access to the PC debug port (it is often used for I/O
8608 * delays, but the vmexits simply slow things down).
8609 */
3e7c73e9
AK		 8610 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8611 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8612
3e7c73e9 8613 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8614
5897297b
AK		 8615 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8616 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8617
2384d2b3
SY		 8618 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8619
0ee75bea
AK		 8620 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8621 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8622 if (r)
4607c2d7 8623 goto out7;
25c5f225 8624
8f536b76
ZY		 8625#ifdef CONFIG_KEXEC
8626 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8627 crash_vmclear_local_loaded_vmcss);
8628#endif
8629
5897297b
AK		 8630 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8631 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8632 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8633 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8634 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8635 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8636 memcpy(vmx_msr_bitmap_legacy_x2apic,
8637 vmx_msr_bitmap_legacy, PAGE_SIZE);
8638 memcpy(vmx_msr_bitmap_longmode_x2apic,
8639 vmx_msr_bitmap_longmode, PAGE_SIZE);
8640
01e439be 8641 if (enable_apicv) {
8d14695f
YZ		 8642 for (msr = 0x800; msr <= 0x8ff; msr++)
8643 vmx_disable_intercept_msr_read_x2apic(msr);
8644
8645 /* According SDM, in x2apic mode, the whole id reg is used.
8646 * But in KVM, it only use the highest eight bits. Need to
8647 * intercept it */
8648 vmx_enable_intercept_msr_read_x2apic(0x802);
8649 /* TMCCT */
8650 vmx_enable_intercept_msr_read_x2apic(0x839);
8651 /* TPR */
8652 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8653 /* EOI */
8654 vmx_disable_intercept_msr_write_x2apic(0x80b);
8655 /* SELF-IPI */
8656 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8657 }
fdef3ad1 8658
089d034e 8659 if (enable_ept) {
3f6d8c8a
XH		 8660 kvm_mmu_set_mask_ptes(0ull,
8661 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8662 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8663 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8664 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8665 kvm_enable_tdp();
8666 } else
8667 kvm_disable_tdp();
1439442c 8668
fdef3ad1
HQ		 8669 return 0;
8670
4607c2d7
AG		 8671out7:
8672 free_page((unsigned long)vmx_vmwrite_bitmap);
8673out6:
8674 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8675out5:
8676 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8677out4:
5897297b 8678 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8679out3:
8680 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8681out2:
5897297b 8682 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8683out1:
3e7c73e9 8684 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8685out:
3e7c73e9 8686 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8687 return r;
6aa8b732
AK		 8688}
8689
8690static void __exit vmx_exit(void)
8691{
8d14695f
YZ		 8692 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8693 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8694 free_page((unsigned long)vmx_msr_bitmap_legacy);
8695 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8696 free_page((unsigned long)vmx_io_bitmap_b);
8697 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8698 free_page((unsigned long)vmx_vmwrite_bitmap);
8699 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8700
8f536b76
ZY		 8701#ifdef CONFIG_KEXEC
8702 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8703 synchronize_rcu();
8704#endif
8705
cb498ea2 8706 kvm_exit();
6aa8b732
AK		 8707}
8708
8709module_init(vmx_init)
8710module_exit(vmx_exit)
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