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KVM: nVMX: Replace kvm_set_cr0 with vmx_set_cr0 in load_vmcs12_host_state
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93
GN		 1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1901 * This function assumes it is called with the exit reason in vmcs02 being
1902 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1903 * is running).
1904 */
1905static int nested_pf_handled(struct kvm_vcpu *vcpu)
1906{
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908
1909 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1910 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1911 return 0;
1912
1913 nested_vmx_vmexit(vcpu);
1914 return 1;
1915}
1916
298101da 1917static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1918 bool has_error_code, u32 error_code,
1919 bool reinject)
298101da 1920{
77ab6db0 1921 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1922 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1923
0b6ac343 1924 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1925 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1926 return;
1927
8ab2d2e2 1928 if (has_error_code) {
77ab6db0 1929 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1930 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1931 }
77ab6db0 1932
7ffd92c5 1933 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1934 int inc_eip = 0;
1935 if (kvm_exception_is_soft(nr))
1936 inc_eip = vcpu->arch.event_exit_inst_len;
1937 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1938 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1939 return;
1940 }
1941
66fd3f7f
GN		 1942 if (kvm_exception_is_soft(nr)) {
1943 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1945 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1946 } else
1947 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1948
1949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1950}
1951
4e47c7a6
SY		 1952static bool vmx_rdtscp_supported(void)
1953{
1954 return cpu_has_vmx_rdtscp();
1955}
1956
ad756a16
MJ		 1957static bool vmx_invpcid_supported(void)
1958{
1959 return cpu_has_vmx_invpcid() && enable_ept;
1960}
1961
a75beee6
ED		 1962/*
1963 * Swap MSR entry in host/guest MSR entry array.
1964 */
8b9cf98c 1965static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1966{
26bb0981 1967 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1968
1969 tmp = vmx->guest_msrs[to];
1970 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1972}
1973
8d14695f
YZ		 1974static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1975{
1976 unsigned long *msr_bitmap;
1977
1978 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1983 } else {
1984 if (is_long_mode(vcpu))
1985 msr_bitmap = vmx_msr_bitmap_longmode;
1986 else
1987 msr_bitmap = vmx_msr_bitmap_legacy;
1988 }
1989
1990 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1991}
1992
e38aea3e
AK		 1993/*
1994 * Set up the vmcs to automatically save and restore system
1995 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1996 * mode, as fiddling with msrs is very expensive.
1997 */
8b9cf98c 1998static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1999{
26bb0981 2000 int save_nmsrs, index;
e38aea3e 2001
a75beee6
ED		 2002 save_nmsrs = 0;
2003#ifdef CONFIG_X86_64
8b9cf98c 2004 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2005 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2006 if (index >= 0)
8b9cf98c
RR		 2007 move_msr_up(vmx, index, save_nmsrs++);
2008 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2009 if (index >= 0)
8b9cf98c
RR		 2010 move_msr_up(vmx, index, save_nmsrs++);
2011 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2012 if (index >= 0)
8b9cf98c 2013 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2014 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015 if (index >= 0 && vmx->rdtscp_enabled)
2016 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2017 /*
8c06585d 2018 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2019 * if efer.sce is enabled.
2020 */
8c06585d 2021 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2022 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2023 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2024 }
2025#endif
92c0d900
AK		 2026 index = __find_msr_index(vmx, MSR_EFER);
2027 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2028 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2029
26bb0981 2030 vmx->save_nmsrs = save_nmsrs;
5897297b 2031
8d14695f
YZ		 2032 if (cpu_has_vmx_msr_bitmap())
2033 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2034}
2035
6aa8b732
AK		 2036/*
2037 * reads and returns guest's timestamp counter "register"
2038 * guest_tsc = host_tsc + tsc_offset -- 21.3
2039 */
2040static u64 guest_read_tsc(void)
2041{
2042 u64 host_tsc, tsc_offset;
2043
2044 rdtscll(host_tsc);
2045 tsc_offset = vmcs_read64(TSC_OFFSET);
2046 return host_tsc + tsc_offset;
2047}
2048
d5c1785d
NHE		 2049/*
2050 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051 * counter, even if a nested guest (L2) is currently running.
2052 */
886b470c 2053u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2054{
886b470c 2055 u64 tsc_offset;
d5c1785d 2056
d5c1785d
NHE		 2057 tsc_offset = is_guest_mode(vcpu) ?
2058 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059 vmcs_read64(TSC_OFFSET);
2060 return host_tsc + tsc_offset;
2061}
2062
4051b188 2063/*
cc578287
ZA		 2064 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2065 * software catchup for faster rates on slower CPUs.
4051b188 2066 */
cc578287 2067static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2068{
cc578287
ZA		 2069 if (!scale)
2070 return;
2071
2072 if (user_tsc_khz > tsc_khz) {
2073 vcpu->arch.tsc_catchup = 1;
2074 vcpu->arch.tsc_always_catchup = 1;
2075 } else
2076 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2077}
2078
ba904635
WA		 2079static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2080{
2081 return vmcs_read64(TSC_OFFSET);
2082}
2083
6aa8b732 2084/*
99e3e30a 2085 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2086 */
99e3e30a 2087static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2088{
27fc51b2 2089 if (is_guest_mode(vcpu)) {
7991825b 2090 /*
27fc51b2
NHE		 2091 * We're here if L1 chose not to trap WRMSR to TSC. According
2092 * to the spec, this should set L1's TSC; The offset that L1
2093 * set for L2 remains unchanged, and still needs to be added
2094 * to the newly set TSC to get L2's TSC.
7991825b 2095 */
27fc51b2
NHE		 2096 struct vmcs12 *vmcs12;
2097 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098 /* recalculate vmcs02.TSC_OFFSET: */
2099 vmcs12 = get_vmcs12(vcpu);
2100 vmcs_write64(TSC_OFFSET, offset +
2101 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102 vmcs12->tsc_offset : 0));
2103 } else {
489223ed
YY		 2104 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2106 vmcs_write64(TSC_OFFSET, offset);
2107 }
6aa8b732
AK		 2108}
2109
f1e2b260 2110static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2111{
2112 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2113
e48672fa 2114 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2115 if (is_guest_mode(vcpu)) {
2116 /* Even when running L2, the adjustment needs to apply to L1 */
2117 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2118 } else
2119 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120 offset + adjustment);
e48672fa
ZA		 2121}
2122
857e4099
JR		 2123static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2124{
2125 return target_tsc - native_read_tsc();
2126}
2127
801d3424
NHE		 2128static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2129{
2130 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2132}
2133
2134/*
2135 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137 * all guests if the "nested" module option is off, and can also be disabled
2138 * for a single guest by disabling its VMX cpuid bit.
2139 */
2140static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2141{
2142 return nested && guest_cpuid_has_vmx(vcpu);
2143}
2144
b87a51ae
NHE		 2145/*
2146 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147 * returned for the various VMX controls MSRs when nested VMX is enabled.
2148 * The same values should also be used to verify that vmcs12 control fields are
2149 * valid during nested entry from L1 to L2.
2150 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152 * bit in the high half is on if the corresponding bit in the control field
2153 * may be on. See also vmx_control_verify().
2154 * TODO: allow these variables to be modified (downgraded) by module options
2155 * or other means.
2156 */
2157static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2162static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2163static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2164static __init void nested_vmx_setup_ctls_msrs(void)
2165{
2166 /*
2167 * Note that as a general rule, the high half of the MSRs (bits in
2168 * the control fields which may be 1) should be initialized by the
2169 * intersection of the underlying hardware's MSR (i.e., features which
2170 * can be supported) and the list of features we want to expose -
2171 * because they are known to be properly supported in our code.
2172 * Also, usually, the low half of the MSRs (bits which must be 1) can
2173 * be set to 0, meaning that L1 may turn off any of these bits. The
2174 * reason is that if one of these bits is necessary, it will appear
2175 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176 * fields of vmcs01 and vmcs02, will turn these bits off - and
2177 * nested_vmx_exit_handled() will not pass related exits to L1.
2178 * These rules have exceptions below.
2179 */
2180
2181 /* pin-based controls */
eabeaacc
JK		 2182 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2184 /*
2185 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187 */
eabeaacc
JK		 2188 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2190 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2192 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2193
33fb20c3
JK		 2194 /*
2195 * Exit controls
2196 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197 * 17 must be 1.
2198 */
c0dfee58
ACL		 2199 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2200 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2201 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2202 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2203 nested_vmx_exit_ctls_high &=
b87a51ae 2204#ifdef CONFIG_X86_64
c0dfee58 2205 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2206#endif
c0dfee58 2207 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
8049d651
NHE		 2208 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209 VM_EXIT_LOAD_IA32_EFER);
b87a51ae
NHE		 2210
2211 /* entry controls */
2212 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2214 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2216 nested_vmx_entry_ctls_high &=
57435349
JK		 2217#ifdef CONFIG_X86_64
2218 VM_ENTRY_IA32E_MODE |
2219#endif
2220 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2221 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2222 VM_ENTRY_LOAD_IA32_EFER);
57435349 2223
b87a51ae
NHE		 2224 /* cpu-based controls */
2225 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2226 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2227 nested_vmx_procbased_ctls_low = 0;
2228 nested_vmx_procbased_ctls_high &=
2229 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2230 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2231 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2232 CPU_BASED_CR3_STORE_EXITING |
2233#ifdef CONFIG_X86_64
2234 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2235#endif
2236 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2237 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2238 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2239 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2240 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2241 /*
2242 * We can allow some features even when not supported by the
2243 * hardware. For example, L1 can specify an MSR bitmap - and we
2244 * can use it to avoid exits to L1 - even when L0 runs L2
2245 * without MSR bitmaps.
2246 */
2247 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2248
2249 /* secondary cpu-based controls */
2250 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2251 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2252 nested_vmx_secondary_ctls_low = 0;
2253 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2255 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2256
afa61f75
NHE		 2257 if (enable_ept) {
2258 /* nested EPT: emulate EPT also to L1 */
2259 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970
JK		 2260 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2261 VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2262 nested_vmx_ept_caps &= vmx_capability.ept;
2263 /*
2264 * Since invept is completely emulated we support both global
2265 * and context invalidation independent of what host cpu
2266 * supports
2267 */
2268 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2269 VMX_EPT_EXTENT_CONTEXT_BIT;
2270 } else
2271 nested_vmx_ept_caps = 0;
2272
c18911a2
JK		 2273 /* miscellaneous data */
2274 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2275 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2276 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2277 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2278}
2279
2280static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2281{
2282 /*
2283 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2284 */
2285 return ((control & high) | low) == control;
2286}
2287
2288static inline u64 vmx_control_msr(u32 low, u32 high)
2289{
2290 return low | ((u64)high << 32);
2291}
2292
2293/*
2294 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2295 * also let it use VMX-specific MSRs.
2296 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2297 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2298 * like all other MSRs).
2299 */
2300static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2301{
2302 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2303 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2304 /*
2305 * According to the spec, processors which do not support VMX
2306 * should throw a #GP(0) when VMX capability MSRs are read.
2307 */
2308 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2309 return 1;
2310 }
2311
2312 switch (msr_index) {
2313 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2314 if (nested_vmx_allowed(vcpu)) {
2315 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2316 break;
2317 }
2318 return 0;
b87a51ae
NHE		 2319 case MSR_IA32_VMX_BASIC:
2320 /*
2321 * This MSR reports some information about VMX support. We
2322 * should return information about the VMX we emulate for the
2323 * guest, and the VMCS structure we give it - not about the
2324 * VMX support of the underlying hardware.
2325 */
2326 *pdata = VMCS12_REVISION |
2327 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2328 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2329 break;
2330 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2331 case MSR_IA32_VMX_PINBASED_CTLS:
2332 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2333 nested_vmx_pinbased_ctls_high);
2334 break;
2335 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2336 case MSR_IA32_VMX_PROCBASED_CTLS:
2337 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2338 nested_vmx_procbased_ctls_high);
2339 break;
2340 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2341 case MSR_IA32_VMX_EXIT_CTLS:
2342 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2343 nested_vmx_exit_ctls_high);
2344 break;
2345 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2346 case MSR_IA32_VMX_ENTRY_CTLS:
2347 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2348 nested_vmx_entry_ctls_high);
2349 break;
2350 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2351 *pdata = vmx_control_msr(nested_vmx_misc_low,
2352 nested_vmx_misc_high);
b87a51ae
NHE		 2353 break;
2354 /*
2355 * These MSRs specify bits which the guest must keep fixed (on or off)
2356 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2357 * We picked the standard core2 setting.
2358 */
2359#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2360#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2361 case MSR_IA32_VMX_CR0_FIXED0:
2362 *pdata = VMXON_CR0_ALWAYSON;
2363 break;
2364 case MSR_IA32_VMX_CR0_FIXED1:
2365 *pdata = -1ULL;
2366 break;
2367 case MSR_IA32_VMX_CR4_FIXED0:
2368 *pdata = VMXON_CR4_ALWAYSON;
2369 break;
2370 case MSR_IA32_VMX_CR4_FIXED1:
2371 *pdata = -1ULL;
2372 break;
2373 case MSR_IA32_VMX_VMCS_ENUM:
2374 *pdata = 0x1f;
2375 break;
2376 case MSR_IA32_VMX_PROCBASED_CTLS2:
2377 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2378 nested_vmx_secondary_ctls_high);
2379 break;
2380 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2381 /* Currently, no nested vpid support */
2382 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2383 break;
2384 default:
2385 return 0;
2386 }
2387
2388 return 1;
2389}
2390
b3897a49 2391static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2392{
b3897a49
NHE		 2393 u32 msr_index = msr_info->index;
2394 u64 data = msr_info->data;
2395 bool host_initialized = msr_info->host_initiated;
2396
b87a51ae
NHE		 2397 if (!nested_vmx_allowed(vcpu))
2398 return 0;
2399
b3897a49
NHE		 2400 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2401 if (!host_initialized &&
2402 to_vmx(vcpu)->nested.msr_ia32_feature_control
2403 & FEATURE_CONTROL_LOCKED)
2404 return 0;
2405 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2406 return 1;
b3897a49
NHE		 2407 }
2408
b87a51ae
NHE		 2409 /*
2410 * No need to treat VMX capability MSRs specially: If we don't handle
2411 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2412 */
2413 return 0;
2414}
2415
6aa8b732
AK		 2416/*
2417 * Reads an msr value (of 'msr_index') into 'pdata'.
2418 * Returns 0 on success, non-0 otherwise.
2419 * Assumes vcpu_load() was already called.
2420 */
2421static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2422{
2423 u64 data;
26bb0981 2424 struct shared_msr_entry *msr;
6aa8b732
AK		 2425
2426 if (!pdata) {
2427 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2428 return -EINVAL;
2429 }
2430
2431 switch (msr_index) {
05b3e0c2 2432#ifdef CONFIG_X86_64
6aa8b732
AK		 2433 case MSR_FS_BASE:
2434 data = vmcs_readl(GUEST_FS_BASE);
2435 break;
2436 case MSR_GS_BASE:
2437 data = vmcs_readl(GUEST_GS_BASE);
2438 break;
44ea2b17
AK		 2439 case MSR_KERNEL_GS_BASE:
2440 vmx_load_host_state(to_vmx(vcpu));
2441 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2442 break;
26bb0981 2443#endif
6aa8b732 2444 case MSR_EFER:
3bab1f5d 2445 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2446 case MSR_IA32_TSC:
6aa8b732
AK		 2447 data = guest_read_tsc();
2448 break;
2449 case MSR_IA32_SYSENTER_CS:
2450 data = vmcs_read32(GUEST_SYSENTER_CS);
2451 break;
2452 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2453 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2454 break;
2455 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2456 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2457 break;
4e47c7a6
SY		 2458 case MSR_TSC_AUX:
2459 if (!to_vmx(vcpu)->rdtscp_enabled)
2460 return 1;
2461 /* Otherwise falls through */
6aa8b732 2462 default:
b87a51ae
NHE		 2463 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2464 return 0;
8b9cf98c 2465 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2466 if (msr) {
2467 data = msr->data;
2468 break;
6aa8b732 2469 }
3bab1f5d 2470 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2471 }
2472
2473 *pdata = data;
2474 return 0;
2475}
2476
2477/*
2478 * Writes msr value into into the appropriate "register".
2479 * Returns 0 on success, non-0 otherwise.
2480 * Assumes vcpu_load() was already called.
2481 */
8fe8ab46 2482static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2483{
a2fa3e9f 2484 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2485 struct shared_msr_entry *msr;
2cc51560 2486 int ret = 0;
8fe8ab46
WA		 2487 u32 msr_index = msr_info->index;
2488 u64 data = msr_info->data;
2cc51560 2489
6aa8b732 2490 switch (msr_index) {
3bab1f5d 2491 case MSR_EFER:
8fe8ab46 2492 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2493 break;
16175a79 2494#ifdef CONFIG_X86_64
6aa8b732 2495 case MSR_FS_BASE:
2fb92db1 2496 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2497 vmcs_writel(GUEST_FS_BASE, data);
2498 break;
2499 case MSR_GS_BASE:
2fb92db1 2500 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2501 vmcs_writel(GUEST_GS_BASE, data);
2502 break;
44ea2b17
AK		 2503 case MSR_KERNEL_GS_BASE:
2504 vmx_load_host_state(vmx);
2505 vmx->msr_guest_kernel_gs_base = data;
2506 break;
6aa8b732
AK		 2507#endif
2508 case MSR_IA32_SYSENTER_CS:
2509 vmcs_write32(GUEST_SYSENTER_CS, data);
2510 break;
2511 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2512 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2513 break;
2514 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2515 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2516 break;
af24a4e4 2517 case MSR_IA32_TSC:
8fe8ab46 2518 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2519 break;
468d472f
SY		 2520 case MSR_IA32_CR_PAT:
2521 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2522 vmcs_write64(GUEST_IA32_PAT, data);
2523 vcpu->arch.pat = data;
2524 break;
2525 }
8fe8ab46 2526 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2527 break;
ba904635
WA		 2528 case MSR_IA32_TSC_ADJUST:
2529 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2530 break;
2531 case MSR_TSC_AUX:
2532 if (!vmx->rdtscp_enabled)
2533 return 1;
2534 /* Check reserved bit, higher 32 bits should be zero */
2535 if ((data >> 32) != 0)
2536 return 1;
2537 /* Otherwise falls through */
6aa8b732 2538 default:
b3897a49 2539 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2540 break;
8b9cf98c 2541 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2542 if (msr) {
2543 msr->data = data;
2225fd56
AK		 2544 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2545 preempt_disable();
9ee73970
AK		 2546 kvm_set_shared_msr(msr->index, msr->data,
2547 msr->mask);
2225fd56
AK		 2548 preempt_enable();
2549 }
3bab1f5d 2550 break;
6aa8b732 2551 }
8fe8ab46 2552 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2553 }
2554
2cc51560 2555 return ret;
6aa8b732
AK		 2556}
2557
5fdbf976 2558static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2559{
5fdbf976
MT		 2560 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2561 switch (reg) {
2562 case VCPU_REGS_RSP:
2563 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2564 break;
2565 case VCPU_REGS_RIP:
2566 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2567 break;
6de4f3ad
AK		 2568 case VCPU_EXREG_PDPTR:
2569 if (enable_ept)
2570 ept_save_pdptrs(vcpu);
2571 break;
5fdbf976
MT		 2572 default:
2573 break;
2574 }
6aa8b732
AK		 2575}
2576
6aa8b732
AK		 2577static __init int cpu_has_kvm_support(void)
2578{
6210e37b 2579 return cpu_has_vmx();
6aa8b732
AK		 2580}
2581
2582static __init int vmx_disabled_by_bios(void)
2583{
2584 u64 msr;
2585
2586 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2587 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2588 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2589 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2590 && tboot_enabled())
2591 return 1;
23f3e991 2592 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2593 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2594 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2595 && !tboot_enabled()) {
2596 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2597 "activate TXT before enabling KVM\n");
cafd6659 2598 return 1;
f9335afe 2599 }
23f3e991
JC		 2600 /* launched w/o TXT and VMX disabled */
2601 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2602 && !tboot_enabled())
2603 return 1;
cafd6659
SW		 2604 }
2605
2606 return 0;
6aa8b732
AK		 2607}
2608
7725b894
DX		 2609static void kvm_cpu_vmxon(u64 addr)
2610{
2611 asm volatile (ASM_VMX_VMXON_RAX
2612 : : "a"(&addr), "m"(addr)
2613 : "memory", "cc");
2614}
2615
10474ae8 2616static int hardware_enable(void *garbage)
6aa8b732
AK		 2617{
2618 int cpu = raw_smp_processor_id();
2619 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2620 u64 old, test_bits;
6aa8b732 2621
10474ae8
AG		 2622 if (read_cr4() & X86_CR4_VMXE)
2623 return -EBUSY;
2624
d462b819 2625 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2626
2627 /*
2628 * Now we can enable the vmclear operation in kdump
2629 * since the loaded_vmcss_on_cpu list on this cpu
2630 * has been initialized.
2631 *
2632 * Though the cpu is not in VMX operation now, there
2633 * is no problem to enable the vmclear operation
2634 * for the loaded_vmcss_on_cpu list is empty!
2635 */
2636 crash_enable_local_vmclear(cpu);
2637
6aa8b732 2638 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2639
2640 test_bits = FEATURE_CONTROL_LOCKED;
2641 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2642 if (tboot_enabled())
2643 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2644
2645 if ((old & test_bits) != test_bits) {
6aa8b732 2646 /* enable and lock */
cafd6659
SW		 2647 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2648 }
66aee91a 2649 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2650
4610c9cc
DX		 2651 if (vmm_exclusive) {
2652 kvm_cpu_vmxon(phys_addr);
2653 ept_sync_global();
2654 }
10474ae8 2655
357d1226 2656 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2657
10474ae8 2658 return 0;
6aa8b732
AK		 2659}
2660
d462b819 2661static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2662{
2663 int cpu = raw_smp_processor_id();
d462b819 2664 struct loaded_vmcs *v, *n;
543e4243 2665
d462b819
NHE		 2666 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2667 loaded_vmcss_on_cpu_link)
2668 __loaded_vmcs_clear(v);
543e4243
AK		 2669}
2670
710ff4a8
EH		 2671
2672/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2673 * tricks.
2674 */
2675static void kvm_cpu_vmxoff(void)
6aa8b732 2676{
4ecac3fd 2677 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2678}
2679
710ff4a8
EH		 2680static void hardware_disable(void *garbage)
2681{
4610c9cc 2682 if (vmm_exclusive) {
d462b819 2683 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2684 kvm_cpu_vmxoff();
2685 }
7725b894 2686 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2687}
2688
1c3d14fe 2689static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2690 u32 msr, u32 *result)
1c3d14fe
YS		 2691{
2692 u32 vmx_msr_low, vmx_msr_high;
2693 u32 ctl = ctl_min | ctl_opt;
2694
2695 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2696
2697 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2698 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2699
2700 /* Ensure minimum (required) set of control bits are supported. */
2701 if (ctl_min & ~ctl)
002c7f7c 2702 return -EIO;
1c3d14fe
YS		 2703
2704 *result = ctl;
2705 return 0;
2706}
2707
110312c8
AK		 2708static __init bool allow_1_setting(u32 msr, u32 ctl)
2709{
2710 u32 vmx_msr_low, vmx_msr_high;
2711
2712 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2713 return vmx_msr_high & ctl;
2714}
2715
002c7f7c 2716static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2717{
2718 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2719 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2720 u32 _pin_based_exec_control = 0;
2721 u32 _cpu_based_exec_control = 0;
f78e0e2e 2722 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2723 u32 _vmexit_control = 0;
2724 u32 _vmentry_control = 0;
2725
10166744 2726 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2727#ifdef CONFIG_X86_64
2728 CPU_BASED_CR8_LOAD_EXITING |
2729 CPU_BASED_CR8_STORE_EXITING |
2730#endif
d56f546d
SY		 2731 CPU_BASED_CR3_LOAD_EXITING |
2732 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2733 CPU_BASED_USE_IO_BITMAPS |
2734 CPU_BASED_MOV_DR_EXITING |
a7052897 2735 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2736 CPU_BASED_MWAIT_EXITING |
2737 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2738 CPU_BASED_INVLPG_EXITING |
2739 CPU_BASED_RDPMC_EXITING;
443381a8 2740
f78e0e2e 2741 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2742 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2743 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2744 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2745 &_cpu_based_exec_control) < 0)
002c7f7c 2746 return -EIO;
6e5d865c
YS		 2747#ifdef CONFIG_X86_64
2748 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2749 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2750 ~CPU_BASED_CR8_STORE_EXITING;
2751#endif
f78e0e2e 2752 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2753 min2 = 0;
2754 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2755 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2756 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2757 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2758 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2759 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2760 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2761 SECONDARY_EXEC_RDTSCP |
83d4c286 2762 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2763 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2764 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2765 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2766 if (adjust_vmx_controls(min2, opt2,
2767 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2768 &_cpu_based_2nd_exec_control) < 0)
2769 return -EIO;
2770 }
2771#ifndef CONFIG_X86_64
2772 if (!(_cpu_based_2nd_exec_control &
2773 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2774 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2775#endif
83d4c286
YZ		 2776
2777 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2778 _cpu_based_2nd_exec_control &= ~(
8d14695f 2779 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2780 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2781 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2782
d56f546d 2783 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2784 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2785 enabled */
5fff7d27
GN		 2786 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2787 CPU_BASED_CR3_STORE_EXITING |
2788 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2789 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2790 vmx_capability.ept, vmx_capability.vpid);
2791 }
1c3d14fe
YS		 2792
2793 min = 0;
2794#ifdef CONFIG_X86_64
2795 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2796#endif
a547c6db
YZ		 2797 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2798 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2799 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2800 &_vmexit_control) < 0)
002c7f7c 2801 return -EIO;
1c3d14fe 2802
01e439be
YZ		 2803 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2804 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2805 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2806 &_pin_based_exec_control) < 0)
2807 return -EIO;
2808
2809 if (!(_cpu_based_2nd_exec_control &
2810 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2811 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2812 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2813
468d472f
SY		 2814 min = 0;
2815 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2816 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2817 &_vmentry_control) < 0)
002c7f7c 2818 return -EIO;
6aa8b732 2819
c68876fd 2820 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2821
2822 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2823 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2824 return -EIO;
1c3d14fe
YS		 2825
2826#ifdef CONFIG_X86_64
2827 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2828 if (vmx_msr_high & (1u<<16))
002c7f7c 2829 return -EIO;
1c3d14fe
YS		 2830#endif
2831
2832 /* Require Write-Back (WB) memory type for VMCS accesses. */
2833 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2834 return -EIO;
1c3d14fe 2835
002c7f7c
YS		 2836 vmcs_conf->size = vmx_msr_high & 0x1fff;
2837 vmcs_conf->order = get_order(vmcs_config.size);
2838 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2839
002c7f7c
YS		 2840 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2841 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2842 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2843 vmcs_conf->vmexit_ctrl = _vmexit_control;
2844 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2845
110312c8
AK		 2846 cpu_has_load_ia32_efer =
2847 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2848 VM_ENTRY_LOAD_IA32_EFER)
2849 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2850 VM_EXIT_LOAD_IA32_EFER);
2851
8bf00a52
GN		 2852 cpu_has_load_perf_global_ctrl =
2853 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2854 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2855 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2856 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2857
2858 /*
2859 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2860 * but due to arrata below it can't be used. Workaround is to use
2861 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2862 *
2863 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2864 *
2865 * AAK155 (model 26)
2866 * AAP115 (model 30)
2867 * AAT100 (model 37)
2868 * BC86,AAY89,BD102 (model 44)
2869 * BA97 (model 46)
2870 *
2871 */
2872 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2873 switch (boot_cpu_data.x86_model) {
2874 case 26:
2875 case 30:
2876 case 37:
2877 case 44:
2878 case 46:
2879 cpu_has_load_perf_global_ctrl = false;
2880 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2881 "does not work properly. Using workaround\n");
2882 break;
2883 default:
2884 break;
2885 }
2886 }
2887
1c3d14fe 2888 return 0;
c68876fd 2889}
6aa8b732
AK		 2890
2891static struct vmcs *alloc_vmcs_cpu(int cpu)
2892{
2893 int node = cpu_to_node(cpu);
2894 struct page *pages;
2895 struct vmcs *vmcs;
2896
6484eb3e 2897 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2898 if (!pages)
2899 return NULL;
2900 vmcs = page_address(pages);
1c3d14fe
YS		 2901 memset(vmcs, 0, vmcs_config.size);
2902 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2903 return vmcs;
2904}
2905
2906static struct vmcs *alloc_vmcs(void)
2907{
d3b2c338 2908 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2909}
2910
2911static void free_vmcs(struct vmcs *vmcs)
2912{
1c3d14fe 2913 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2914}
2915
d462b819
NHE		 2916/*
2917 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2918 */
2919static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2920{
2921 if (!loaded_vmcs->vmcs)
2922 return;
2923 loaded_vmcs_clear(loaded_vmcs);
2924 free_vmcs(loaded_vmcs->vmcs);
2925 loaded_vmcs->vmcs = NULL;
2926}
2927
39959588 2928static void free_kvm_area(void)
6aa8b732
AK		 2929{
2930 int cpu;
2931
3230bb47 2932 for_each_possible_cpu(cpu) {
6aa8b732 2933 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2934 per_cpu(vmxarea, cpu) = NULL;
2935 }
6aa8b732
AK		 2936}
2937
6aa8b732
AK		 2938static __init int alloc_kvm_area(void)
2939{
2940 int cpu;
2941
3230bb47 2942 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2943 struct vmcs *vmcs;
2944
2945 vmcs = alloc_vmcs_cpu(cpu);
2946 if (!vmcs) {
2947 free_kvm_area();
2948 return -ENOMEM;
2949 }
2950
2951 per_cpu(vmxarea, cpu) = vmcs;
2952 }
2953 return 0;
2954}
2955
2956static __init int hardware_setup(void)
2957{
002c7f7c
YS		 2958 if (setup_vmcs_config(&vmcs_config) < 0)
2959 return -EIO;
50a37eb4
JR		 2960
2961 if (boot_cpu_has(X86_FEATURE_NX))
2962 kvm_enable_efer_bits(EFER_NX);
2963
93ba03c2
SY		 2964 if (!cpu_has_vmx_vpid())
2965 enable_vpid = 0;
abc4fc58
AG		 2966 if (!cpu_has_vmx_shadow_vmcs())
2967 enable_shadow_vmcs = 0;
93ba03c2 2968
4bc9b982
SY		 2969 if (!cpu_has_vmx_ept() ||
2970 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2971 enable_ept = 0;
3a624e29 2972 enable_unrestricted_guest = 0;
83c3a331 2973 enable_ept_ad_bits = 0;
3a624e29
NK		 2974 }
2975
83c3a331
XH		 2976 if (!cpu_has_vmx_ept_ad_bits())
2977 enable_ept_ad_bits = 0;
2978
3a624e29
NK		 2979 if (!cpu_has_vmx_unrestricted_guest())
2980 enable_unrestricted_guest = 0;
93ba03c2
SY		 2981
2982 if (!cpu_has_vmx_flexpriority())
2983 flexpriority_enabled = 0;
2984
95ba8273
GN		 2985 if (!cpu_has_vmx_tpr_shadow())
2986 kvm_x86_ops->update_cr8_intercept = NULL;
2987
54dee993
MT		 2988 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2989 kvm_disable_largepages();
2990
4b8d54f9
ZE		 2991 if (!cpu_has_vmx_ple())
2992 ple_gap = 0;
2993
01e439be
YZ		 2994 if (!cpu_has_vmx_apicv())
2995 enable_apicv = 0;
c7c9c56c 2996
01e439be 2997 if (enable_apicv)
c7c9c56c 2998 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2999 else {
c7c9c56c 3000 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3001 kvm_x86_ops->deliver_posted_interrupt = NULL;
3002 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3003 }
83d4c286 3004
b87a51ae
NHE		 3005 if (nested)
3006 nested_vmx_setup_ctls_msrs();
3007
6aa8b732
AK		 3008 return alloc_kvm_area();
3009}
3010
3011static __exit void hardware_unsetup(void)
3012{
3013 free_kvm_area();
3014}
3015
14168786
GN		 3016static bool emulation_required(struct kvm_vcpu *vcpu)
3017{
3018 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3019}
3020
91b0aa2c 3021static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3022 struct kvm_segment *save)
6aa8b732 3023{
d99e4152
GN		 3024 if (!emulate_invalid_guest_state) {
3025 /*
3026 * CS and SS RPL should be equal during guest entry according
3027 * to VMX spec, but in reality it is not always so. Since vcpu
3028 * is in the middle of the transition from real mode to
3029 * protected mode it is safe to assume that RPL 0 is a good
3030 * default value.
3031 */
3032 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3033 save->selector &= ~SELECTOR_RPL_MASK;
3034 save->dpl = save->selector & SELECTOR_RPL_MASK;
3035 save->s = 1;
6aa8b732 3036 }
d99e4152 3037 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3038}
3039
3040static void enter_pmode(struct kvm_vcpu *vcpu)
3041{
3042 unsigned long flags;
a89a8fb9 3043 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3044
d99e4152
GN		 3045 /*
3046 * Update real mode segment cache. It may be not up-to-date if sement
3047 * register was written while vcpu was in a guest mode.
3048 */
3049 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3050 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3051 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3052 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3053 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3054 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3055
7ffd92c5 3056 vmx->rmode.vm86_active = 0;
6aa8b732 3057
2fb92db1
AK		 3058 vmx_segment_cache_clear(vmx);
3059
f5f7b2fe 3060 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3061
3062 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3063 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3064 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3065 vmcs_writel(GUEST_RFLAGS, flags);
3066
66aee91a
RR		 3067 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3068 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3069
3070 update_exception_bitmap(vcpu);
3071
91b0aa2c
GN		 3072 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3073 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3074 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3075 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3076 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3077 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3078
3079 /* CPL is always 0 when CPU enters protected mode */
3080 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3081 vmx->cpl = 0;
6aa8b732
AK		 3082}
3083
f5f7b2fe 3084static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3085{
772e0318 3086 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3087 struct kvm_segment var = *save;
3088
3089 var.dpl = 0x3;
3090 if (seg == VCPU_SREG_CS)
3091 var.type = 0x3;
3092
3093 if (!emulate_invalid_guest_state) {
3094 var.selector = var.base >> 4;
3095 var.base = var.base & 0xffff0;
3096 var.limit = 0xffff;
3097 var.g = 0;
3098 var.db = 0;
3099 var.present = 1;
3100 var.s = 1;
3101 var.l = 0;
3102 var.unusable = 0;
3103 var.type = 0x3;
3104 var.avl = 0;
3105 if (save->base & 0xf)
3106 printk_once(KERN_WARNING "kvm: segment base is not "
3107 "paragraph aligned when entering "
3108 "protected mode (seg=%d)", seg);
3109 }
6aa8b732 3110
d99e4152
GN		 3111 vmcs_write16(sf->selector, var.selector);
3112 vmcs_write32(sf->base, var.base);
3113 vmcs_write32(sf->limit, var.limit);
3114 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3115}
3116
3117static void enter_rmode(struct kvm_vcpu *vcpu)
3118{
3119 unsigned long flags;
a89a8fb9 3120 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3121
f5f7b2fe
AK		 3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3125 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3126 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3129
7ffd92c5 3130 vmx->rmode.vm86_active = 1;
6aa8b732 3131
776e58ea
GN		 3132 /*
3133 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3134 * vcpu. Warn the user that an update is overdue.
776e58ea 3135 */
4918c6ca 3136 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3137 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3138 "called before entering vcpu\n");
776e58ea 3139
2fb92db1
AK		 3140 vmx_segment_cache_clear(vmx);
3141
4918c6ca 3142 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3143 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3144 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3145
3146 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3147 vmx->rmode.save_rflags = flags;
6aa8b732 3148
053de044 3149 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3150
3151 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3152 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3153 update_exception_bitmap(vcpu);
3154
d99e4152
GN		 3155 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3156 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3157 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3158 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3159 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3160 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3161
8668a3c4 3162 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3163}
3164
401d10de
AS		 3165static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3166{
3167 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3168 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3169
3170 if (!msr)
3171 return;
401d10de 3172
44ea2b17
AK		 3173 /*
3174 * Force kernel_gs_base reloading before EFER changes, as control
3175 * of this msr depends on is_long_mode().
3176 */
3177 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3178 vcpu->arch.efer = efer;
401d10de
AS		 3179 if (efer & EFER_LMA) {
3180 vmcs_write32(VM_ENTRY_CONTROLS,
3181 vmcs_read32(VM_ENTRY_CONTROLS) |
3182 VM_ENTRY_IA32E_MODE);
3183 msr->data = efer;
3184 } else {
3185 vmcs_write32(VM_ENTRY_CONTROLS,
3186 vmcs_read32(VM_ENTRY_CONTROLS) &
3187 ~VM_ENTRY_IA32E_MODE);
3188
3189 msr->data = efer & ~EFER_LME;
3190 }
3191 setup_msrs(vmx);
3192}
3193
05b3e0c2 3194#ifdef CONFIG_X86_64
6aa8b732
AK		 3195
3196static void enter_lmode(struct kvm_vcpu *vcpu)
3197{
3198 u32 guest_tr_ar;
3199
2fb92db1
AK		 3200 vmx_segment_cache_clear(to_vmx(vcpu));
3201
6aa8b732
AK		 3202 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3203 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3204 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3205 __func__);
6aa8b732
AK		 3206 vmcs_write32(GUEST_TR_AR_BYTES,
3207 (guest_tr_ar & ~AR_TYPE_MASK)
3208 | AR_TYPE_BUSY_64_TSS);
3209 }
da38f438 3210 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3211}
3212
3213static void exit_lmode(struct kvm_vcpu *vcpu)
3214{
6aa8b732
AK		 3215 vmcs_write32(VM_ENTRY_CONTROLS,
3216 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3217 & ~VM_ENTRY_IA32E_MODE);
da38f438 3218 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3219}
3220
3221#endif
3222
2384d2b3
SY		 3223static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3224{
b9d762fa 3225 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3226 if (enable_ept) {
3227 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3228 return;
4e1096d2 3229 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3230 }
2384d2b3
SY		 3231}
3232
e8467fda
AK		 3233static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3234{
3235 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3236
3237 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3238 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3239}
3240
aff48baa
AK		 3241static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3242{
3243 if (enable_ept && is_paging(vcpu))
3244 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3245 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3246}
3247
25c4c276 3248static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3249{
fc78f519
AK		 3250 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3251
3252 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3253 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3254}
3255
1439442c
SY		 3256static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3257{
6de4f3ad
AK		 3258 if (!test_bit(VCPU_EXREG_PDPTR,
3259 (unsigned long *)&vcpu->arch.regs_dirty))
3260 return;
3261
1439442c 3262 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3263 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3264 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3265 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3266 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3267 }
3268}
3269
8f5d549f
AK		 3270static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3271{
3272 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3273 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3274 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3275 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3276 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3277 }
6de4f3ad
AK		 3278
3279 __set_bit(VCPU_EXREG_PDPTR,
3280 (unsigned long *)&vcpu->arch.regs_avail);
3281 __set_bit(VCPU_EXREG_PDPTR,
3282 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3283}
3284
5e1746d6 3285static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3286
3287static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3288 unsigned long cr0,
3289 struct kvm_vcpu *vcpu)
3290{
5233dd51
MT		 3291 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3292 vmx_decache_cr3(vcpu);
1439442c
SY		 3293 if (!(cr0 & X86_CR0_PG)) {
3294 /* From paging/starting to nonpaging */
3295 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3296 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3297 (CPU_BASED_CR3_LOAD_EXITING |
3298 CPU_BASED_CR3_STORE_EXITING));
3299 vcpu->arch.cr0 = cr0;
fc78f519 3300 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3301 } else if (!is_paging(vcpu)) {
3302 /* From nonpaging to paging */
3303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3304 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3305 ~(CPU_BASED_CR3_LOAD_EXITING |
3306 CPU_BASED_CR3_STORE_EXITING));
3307 vcpu->arch.cr0 = cr0;
fc78f519 3308 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3309 }
95eb84a7
SY		 3310
3311 if (!(cr0 & X86_CR0_WP))
3312 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3313}
3314
6aa8b732
AK		 3315static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3316{
7ffd92c5 3317 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3318 unsigned long hw_cr0;
3319
5037878e 3320 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3321 if (enable_unrestricted_guest)
5037878e 3322 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3323 else {
5037878e 3324 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3325
218e763f
GN		 3326 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3327 enter_pmode(vcpu);
6aa8b732 3328
218e763f
GN		 3329 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3330 enter_rmode(vcpu);
3331 }
6aa8b732 3332
05b3e0c2 3333#ifdef CONFIG_X86_64
f6801dff 3334 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3335 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3336 enter_lmode(vcpu);
707d92fa 3337 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3338 exit_lmode(vcpu);
3339 }
3340#endif
3341
089d034e 3342 if (enable_ept)
1439442c
SY		 3343 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3344
02daab21 3345 if (!vcpu->fpu_active)
81231c69 3346 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3347
6aa8b732 3348 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3349 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3350 vcpu->arch.cr0 = cr0;
14168786
GN		 3351
3352 /* depends on vcpu->arch.cr0 to be set to a new value */
3353 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3354}
3355
1439442c
SY		 3356static u64 construct_eptp(unsigned long root_hpa)
3357{
3358 u64 eptp;
3359
3360 /* TODO write the value reading from MSR */
3361 eptp = VMX_EPT_DEFAULT_MT |
3362 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3363 if (enable_ept_ad_bits)
3364 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3365 eptp |= (root_hpa & PAGE_MASK);
3366
3367 return eptp;
3368}
3369
6aa8b732
AK		 3370static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3371{
1439442c
SY		 3372 unsigned long guest_cr3;
3373 u64 eptp;
3374
3375 guest_cr3 = cr3;
089d034e 3376 if (enable_ept) {
1439442c
SY		 3377 eptp = construct_eptp(cr3);
3378 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3379 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3380 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3381 ept_load_pdptrs(vcpu);
1439442c
SY		 3382 }
3383
2384d2b3 3384 vmx_flush_tlb(vcpu);
1439442c 3385 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3386}
3387
5e1746d6 3388static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3389{
7ffd92c5 3390 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3391 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3392
5e1746d6
NHE		 3393 if (cr4 & X86_CR4_VMXE) {
3394 /*
3395 * To use VMXON (and later other VMX instructions), a guest
3396 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3397 * So basically the check on whether to allow nested VMX
3398 * is here.
3399 */
3400 if (!nested_vmx_allowed(vcpu))
3401 return 1;
1a0d74e6
JK		 3402 }
3403 if (to_vmx(vcpu)->nested.vmxon &&
3404 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3405 return 1;
3406
ad312c7c 3407 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3408 if (enable_ept) {
3409 if (!is_paging(vcpu)) {
3410 hw_cr4 &= ~X86_CR4_PAE;
3411 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3412 /*
3413 * SMEP is disabled if CPU is in non-paging mode in
3414 * hardware. However KVM always uses paging mode to
3415 * emulate guest non-paging mode with TDP.
3416 * To emulate this behavior, SMEP needs to be manually
3417 * disabled when guest switches to non-paging mode.
3418 */
3419 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3420 } else if (!(cr4 & X86_CR4_PAE)) {
3421 hw_cr4 &= ~X86_CR4_PAE;
3422 }
3423 }
1439442c
SY		 3424
3425 vmcs_writel(CR4_READ_SHADOW, cr4);
3426 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3427 return 0;
6aa8b732
AK		 3428}
3429
6aa8b732
AK		 3430static void vmx_get_segment(struct kvm_vcpu *vcpu,
3431 struct kvm_segment *var, int seg)
3432{
a9179499 3433 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3434 u32 ar;
3435
c6ad1153 3436 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3437 *var = vmx->rmode.segs[seg];
a9179499 3438 if (seg == VCPU_SREG_TR
2fb92db1 3439 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3440 return;
1390a28b
AK		 3441 var->base = vmx_read_guest_seg_base(vmx, seg);
3442 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3443 return;
a9179499 3444 }
2fb92db1
AK		 3445 var->base = vmx_read_guest_seg_base(vmx, seg);
3446 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3447 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3448 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3449 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3450 var->type = ar & 15;
3451 var->s = (ar >> 4) & 1;
3452 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3453 /*
3454 * Some userspaces do not preserve unusable property. Since usable
3455 * segment has to be present according to VMX spec we can use present
3456 * property to amend userspace bug by making unusable segment always
3457 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3458 * segment as unusable.
3459 */
3460 var->present = !var->unusable;
6aa8b732
AK		 3461 var->avl = (ar >> 12) & 1;
3462 var->l = (ar >> 13) & 1;
3463 var->db = (ar >> 14) & 1;
3464 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3465}
3466
a9179499
AK		 3467static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3468{
a9179499
AK		 3469 struct kvm_segment s;
3470
3471 if (to_vmx(vcpu)->rmode.vm86_active) {
3472 vmx_get_segment(vcpu, &s, seg);
3473 return s.base;
3474 }
2fb92db1 3475 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3476}
3477
b09408d0 3478static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3479{
b09408d0
MT		 3480 struct vcpu_vmx *vmx = to_vmx(vcpu);
3481
3eeb3288 3482 if (!is_protmode(vcpu))
2e4d2653
IE		 3483 return 0;
3484
f4c63e5d
AK		 3485 if (!is_long_mode(vcpu)
3486 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3487 return 3;
3488
69c73028
AK		 3489 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3490 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3491 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3492 }
d881e6f6
AK		 3493
3494 return vmx->cpl;
69c73028
AK		 3495}
3496
3497
653e3108 3498static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3499{
6aa8b732
AK		 3500 u32 ar;
3501
f0495f9b 3502 if (var->unusable || !var->present)
6aa8b732
AK		 3503 ar = 1 << 16;
3504 else {
3505 ar = var->type & 15;
3506 ar |= (var->s & 1) << 4;
3507 ar |= (var->dpl & 3) << 5;
3508 ar |= (var->present & 1) << 7;
3509 ar |= (var->avl & 1) << 12;
3510 ar |= (var->l & 1) << 13;
3511 ar |= (var->db & 1) << 14;
3512 ar |= (var->g & 1) << 15;
3513 }
653e3108
AK		 3514
3515 return ar;
3516}
3517
3518static void vmx_set_segment(struct kvm_vcpu *vcpu,
3519 struct kvm_segment *var, int seg)
3520{
7ffd92c5 3521 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3522 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3523
2fb92db1 3524 vmx_segment_cache_clear(vmx);
2f143240
GN		 3525 if (seg == VCPU_SREG_CS)
3526 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3527
1ecd50a9
GN		 3528 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3529 vmx->rmode.segs[seg] = *var;
3530 if (seg == VCPU_SREG_TR)
3531 vmcs_write16(sf->selector, var->selector);
3532 else if (var->s)
3533 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3534 goto out;
653e3108 3535 }
1ecd50a9 3536
653e3108
AK		 3537 vmcs_writel(sf->base, var->base);
3538 vmcs_write32(sf->limit, var->limit);
3539 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3540
3541 /*
3542 * Fix the "Accessed" bit in AR field of segment registers for older
3543 * qemu binaries.
3544 * IA32 arch specifies that at the time of processor reset the
3545 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3546 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3547 * state vmexit when "unrestricted guest" mode is turned on.
3548 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3549 * tree. Newer qemu binaries with that qemu fix would not need this
3550 * kvm hack.
3551 */
3552 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3553 var->type |= 0x1; /* Accessed */
3a624e29 3554
f924d66d 3555 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3556
3557out:
14168786 3558 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3559}
3560
6aa8b732
AK		 3561static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3562{
2fb92db1 3563 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3564
3565 *db = (ar >> 14) & 1;
3566 *l = (ar >> 13) & 1;
3567}
3568
89a27f4d 3569static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3570{
89a27f4d
GN		 3571 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3572 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3573}
3574
89a27f4d 3575static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3576{
89a27f4d
GN		 3577 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3578 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3579}
3580
89a27f4d 3581static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3582{
89a27f4d
GN		 3583 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3584 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3585}
3586
89a27f4d 3587static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3588{
89a27f4d
GN		 3589 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3590 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3591}
3592
648dfaa7
MG		 3593static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3594{
3595 struct kvm_segment var;
3596 u32 ar;
3597
3598 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3599 var.dpl = 0x3;
0647f4aa
GN		 3600 if (seg == VCPU_SREG_CS)
3601 var.type = 0x3;
648dfaa7
MG		 3602 ar = vmx_segment_access_rights(&var);
3603
3604 if (var.base != (var.selector << 4))
3605 return false;
89efbed0 3606 if (var.limit != 0xffff)
648dfaa7 3607 return false;
07f42f5f 3608 if (ar != 0xf3)
648dfaa7
MG		 3609 return false;
3610
3611 return true;
3612}
3613
3614static bool code_segment_valid(struct kvm_vcpu *vcpu)
3615{
3616 struct kvm_segment cs;
3617 unsigned int cs_rpl;
3618
3619 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3620 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3621
1872a3f4
AK		 3622 if (cs.unusable)
3623 return false;
648dfaa7
MG		 3624 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3625 return false;
3626 if (!cs.s)
3627 return false;
1872a3f4 3628 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3629 if (cs.dpl > cs_rpl)
3630 return false;
1872a3f4 3631 } else {
648dfaa7
MG		 3632 if (cs.dpl != cs_rpl)
3633 return false;
3634 }
3635 if (!cs.present)
3636 return false;
3637
3638 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3639 return true;
3640}
3641
3642static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3643{
3644 struct kvm_segment ss;
3645 unsigned int ss_rpl;
3646
3647 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3648 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3649
1872a3f4
AK		 3650 if (ss.unusable)
3651 return true;
3652 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3653 return false;
3654 if (!ss.s)
3655 return false;
3656 if (ss.dpl != ss_rpl) /* DPL != RPL */
3657 return false;
3658 if (!ss.present)
3659 return false;
3660
3661 return true;
3662}
3663
3664static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3665{
3666 struct kvm_segment var;
3667 unsigned int rpl;
3668
3669 vmx_get_segment(vcpu, &var, seg);
3670 rpl = var.selector & SELECTOR_RPL_MASK;
3671
1872a3f4
AK		 3672 if (var.unusable)
3673 return true;
648dfaa7
MG		 3674 if (!var.s)
3675 return false;
3676 if (!var.present)
3677 return false;
3678 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3679 if (var.dpl < rpl) /* DPL < RPL */
3680 return false;
3681 }
3682
3683 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3684 * rights flags
3685 */
3686 return true;
3687}
3688
3689static bool tr_valid(struct kvm_vcpu *vcpu)
3690{
3691 struct kvm_segment tr;
3692
3693 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3694
1872a3f4
AK		 3695 if (tr.unusable)
3696 return false;
648dfaa7
MG		 3697 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3698 return false;
1872a3f4 3699 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3700 return false;
3701 if (!tr.present)
3702 return false;
3703
3704 return true;
3705}
3706
3707static bool ldtr_valid(struct kvm_vcpu *vcpu)
3708{
3709 struct kvm_segment ldtr;
3710
3711 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3712
1872a3f4
AK		 3713 if (ldtr.unusable)
3714 return true;
648dfaa7
MG		 3715 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3716 return false;
3717 if (ldtr.type != 2)
3718 return false;
3719 if (!ldtr.present)
3720 return false;
3721
3722 return true;
3723}
3724
3725static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3726{
3727 struct kvm_segment cs, ss;
3728
3729 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3730 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3731
3732 return ((cs.selector & SELECTOR_RPL_MASK) ==
3733 (ss.selector & SELECTOR_RPL_MASK));
3734}
3735
3736/*
3737 * Check if guest state is valid. Returns true if valid, false if
3738 * not.
3739 * We assume that registers are always usable
3740 */
3741static bool guest_state_valid(struct kvm_vcpu *vcpu)
3742{
c5e97c80
GN		 3743 if (enable_unrestricted_guest)
3744 return true;
3745
648dfaa7 3746 /* real mode guest state checks */
f13882d8 3747 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3748 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3749 return false;
3750 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3751 return false;
3752 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3753 return false;
3754 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3755 return false;
3756 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3757 return false;
3758 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3759 return false;
3760 } else {
3761 /* protected mode guest state checks */
3762 if (!cs_ss_rpl_check(vcpu))
3763 return false;
3764 if (!code_segment_valid(vcpu))
3765 return false;
3766 if (!stack_segment_valid(vcpu))
3767 return false;
3768 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3769 return false;
3770 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3771 return false;
3772 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3773 return false;
3774 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3775 return false;
3776 if (!tr_valid(vcpu))
3777 return false;
3778 if (!ldtr_valid(vcpu))
3779 return false;
3780 }
3781 /* TODO:
3782 * - Add checks on RIP
3783 * - Add checks on RFLAGS
3784 */
3785
3786 return true;
3787}
3788
d77c26fc 3789static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3790{
40dcaa9f 3791 gfn_t fn;
195aefde 3792 u16 data = 0;
40dcaa9f 3793 int r, idx, ret = 0;
6aa8b732 3794
40dcaa9f 3795 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3796 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3797 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3798 if (r < 0)
10589a46 3799 goto out;
195aefde 3800 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3801 r = kvm_write_guest_page(kvm, fn++, &data,
3802 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3803 if (r < 0)
10589a46 3804 goto out;
195aefde
IE		 3805 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3806 if (r < 0)
10589a46 3807 goto out;
195aefde
IE		 3808 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3809 if (r < 0)
10589a46 3810 goto out;
195aefde 3811 data = ~0;
10589a46
MT		 3812 r = kvm_write_guest_page(kvm, fn, &data,
3813 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3814 sizeof(u8));
195aefde 3815 if (r < 0)
10589a46
MT		 3816 goto out;
3817
3818 ret = 1;
3819out:
40dcaa9f 3820 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3821 return ret;
6aa8b732
AK		 3822}
3823
b7ebfb05
SY		 3824static int init_rmode_identity_map(struct kvm *kvm)
3825{
40dcaa9f 3826 int i, idx, r, ret;
b7ebfb05
SY		 3827 pfn_t identity_map_pfn;
3828 u32 tmp;
3829
089d034e 3830 if (!enable_ept)
b7ebfb05
SY		 3831 return 1;
3832 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3833 printk(KERN_ERR "EPT: identity-mapping pagetable "
3834 "haven't been allocated!\n");
3835 return 0;
3836 }
3837 if (likely(kvm->arch.ept_identity_pagetable_done))
3838 return 1;
3839 ret = 0;
b927a3ce 3840 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3841 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3842 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3843 if (r < 0)
3844 goto out;
3845 /* Set up identity-mapping pagetable for EPT in real mode */
3846 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3847 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3848 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3849 r = kvm_write_guest_page(kvm, identity_map_pfn,
3850 &tmp, i * sizeof(tmp), sizeof(tmp));
3851 if (r < 0)
3852 goto out;
3853 }
3854 kvm->arch.ept_identity_pagetable_done = true;
3855 ret = 1;
3856out:
40dcaa9f 3857 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3858 return ret;
3859}
3860
6aa8b732
AK		 3861static void seg_setup(int seg)
3862{
772e0318 3863 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3864 unsigned int ar;
6aa8b732
AK		 3865
3866 vmcs_write16(sf->selector, 0);
3867 vmcs_writel(sf->base, 0);
3868 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3869 ar = 0x93;
3870 if (seg == VCPU_SREG_CS)
3871 ar |= 0x08; /* code segment */
3a624e29
NK		 3872
3873 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3874}
3875
f78e0e2e
SY		 3876static int alloc_apic_access_page(struct kvm *kvm)
3877{
4484141a 3878 struct page *page;
f78e0e2e
SY		 3879 struct kvm_userspace_memory_region kvm_userspace_mem;
3880 int r = 0;
3881
79fac95e 3882 mutex_lock(&kvm->slots_lock);
bfc6d222 3883 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3884 goto out;
3885 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3886 kvm_userspace_mem.flags = 0;
3887 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3888 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3889 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3890 if (r)
3891 goto out;
72dc67a6 3892
4484141a
XG		 3893 page = gfn_to_page(kvm, 0xfee00);
3894 if (is_error_page(page)) {
3895 r = -EFAULT;
3896 goto out;
3897 }
3898
3899 kvm->arch.apic_access_page = page;
f78e0e2e 3900out:
79fac95e 3901 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3902 return r;
3903}
3904
b7ebfb05
SY		 3905static int alloc_identity_pagetable(struct kvm *kvm)
3906{
4484141a 3907 struct page *page;
b7ebfb05
SY		 3908 struct kvm_userspace_memory_region kvm_userspace_mem;
3909 int r = 0;
3910
79fac95e 3911 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3912 if (kvm->arch.ept_identity_pagetable)
3913 goto out;
3914 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3915 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3916 kvm_userspace_mem.guest_phys_addr =
3917 kvm->arch.ept_identity_map_addr;
b7ebfb05 3918 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3919 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3920 if (r)
3921 goto out;
3922
4484141a
XG		 3923 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3924 if (is_error_page(page)) {
3925 r = -EFAULT;
3926 goto out;
3927 }
3928
3929 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3930out:
79fac95e 3931 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3932 return r;
3933}
3934
2384d2b3
SY		 3935static void allocate_vpid(struct vcpu_vmx *vmx)
3936{
3937 int vpid;
3938
3939 vmx->vpid = 0;
919818ab 3940 if (!enable_vpid)
2384d2b3
SY		 3941 return;
3942 spin_lock(&vmx_vpid_lock);
3943 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3944 if (vpid < VMX_NR_VPIDS) {
3945 vmx->vpid = vpid;
3946 __set_bit(vpid, vmx_vpid_bitmap);
3947 }
3948 spin_unlock(&vmx_vpid_lock);
3949}
3950
cdbecfc3
LJ		 3951static void free_vpid(struct vcpu_vmx *vmx)
3952{
3953 if (!enable_vpid)
3954 return;
3955 spin_lock(&vmx_vpid_lock);
3956 if (vmx->vpid != 0)
3957 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3958 spin_unlock(&vmx_vpid_lock);
3959}
3960
8d14695f
YZ		 3961#define MSR_TYPE_R 1
3962#define MSR_TYPE_W 2
3963static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3964 u32 msr, int type)
25c5f225 3965{
3e7c73e9 3966 int f = sizeof(unsigned long);
25c5f225
SY		 3967
3968 if (!cpu_has_vmx_msr_bitmap())
3969 return;
3970
3971 /*
3972 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3973 * have the write-low and read-high bitmap offsets the wrong way round.
3974 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3975 */
25c5f225 3976 if (msr <= 0x1fff) {
8d14695f
YZ		 3977 if (type & MSR_TYPE_R)
3978 /* read-low */
3979 __clear_bit(msr, msr_bitmap + 0x000 / f);
3980
3981 if (type & MSR_TYPE_W)
3982 /* write-low */
3983 __clear_bit(msr, msr_bitmap + 0x800 / f);
3984
25c5f225
SY		 3985 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3986 msr &= 0x1fff;
8d14695f
YZ		 3987 if (type & MSR_TYPE_R)
3988 /* read-high */
3989 __clear_bit(msr, msr_bitmap + 0x400 / f);
3990
3991 if (type & MSR_TYPE_W)
3992 /* write-high */
3993 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3994
3995 }
3996}
3997
3998static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3999 u32 msr, int type)
4000{
4001 int f = sizeof(unsigned long);
4002
4003 if (!cpu_has_vmx_msr_bitmap())
4004 return;
4005
4006 /*
4007 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4008 * have the write-low and read-high bitmap offsets the wrong way round.
4009 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4010 */
4011 if (msr <= 0x1fff) {
4012 if (type & MSR_TYPE_R)
4013 /* read-low */
4014 __set_bit(msr, msr_bitmap + 0x000 / f);
4015
4016 if (type & MSR_TYPE_W)
4017 /* write-low */
4018 __set_bit(msr, msr_bitmap + 0x800 / f);
4019
4020 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4021 msr &= 0x1fff;
4022 if (type & MSR_TYPE_R)
4023 /* read-high */
4024 __set_bit(msr, msr_bitmap + 0x400 / f);
4025
4026 if (type & MSR_TYPE_W)
4027 /* write-high */
4028 __set_bit(msr, msr_bitmap + 0xc00 / f);
4029
25c5f225 4030 }
25c5f225
SY		 4031}
4032
5897297b
AK		 4033static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4034{
4035 if (!longmode_only)
8d14695f
YZ		 4036 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4037 msr, MSR_TYPE_R | MSR_TYPE_W);
4038 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4039 msr, MSR_TYPE_R | MSR_TYPE_W);
4040}
4041
4042static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4043{
4044 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4045 msr, MSR_TYPE_R);
4046 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4047 msr, MSR_TYPE_R);
4048}
4049
4050static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4051{
4052 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4053 msr, MSR_TYPE_R);
4054 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4055 msr, MSR_TYPE_R);
4056}
4057
4058static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4059{
4060 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4061 msr, MSR_TYPE_W);
4062 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4063 msr, MSR_TYPE_W);
5897297b
AK		 4064}
4065
01e439be
YZ		 4066static int vmx_vm_has_apicv(struct kvm *kvm)
4067{
4068 return enable_apicv && irqchip_in_kernel(kvm);
4069}
4070
a20ed54d
YZ		 4071/*
4072 * Send interrupt to vcpu via posted interrupt way.
4073 * 1. If target vcpu is running(non-root mode), send posted interrupt
4074 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4075 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4076 * interrupt from PIR in next vmentry.
4077 */
4078static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4079{
4080 struct vcpu_vmx *vmx = to_vmx(vcpu);
4081 int r;
4082
4083 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4084 return;
4085
4086 r = pi_test_and_set_on(&vmx->pi_desc);
4087 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4088#ifdef CONFIG_SMP
a20ed54d
YZ		 4089 if (!r && (vcpu->mode == IN_GUEST_MODE))
4090 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4091 POSTED_INTR_VECTOR);
4092 else
6ffbbbba 4093#endif
a20ed54d
YZ		 4094 kvm_vcpu_kick(vcpu);
4095}
4096
4097static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4098{
4099 struct vcpu_vmx *vmx = to_vmx(vcpu);
4100
4101 if (!pi_test_and_clear_on(&vmx->pi_desc))
4102 return;
4103
4104 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4105}
4106
4107static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4108{
4109 return;
4110}
4111
a3a8ff8e
NHE		 4112/*
4113 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4114 * will not change in the lifetime of the guest.
4115 * Note that host-state that does change is set elsewhere. E.g., host-state
4116 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4117 */
a547c6db 4118static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4119{
4120 u32 low32, high32;
4121 unsigned long tmpl;
4122 struct desc_ptr dt;
4123
b1a74bf8 4124 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4125 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4126 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4127
4128 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4129#ifdef CONFIG_X86_64
4130 /*
4131 * Load null selectors, so we can avoid reloading them in
4132 * __vmx_load_host_state(), in case userspace uses the null selectors
4133 * too (the expected case).
4134 */
4135 vmcs_write16(HOST_DS_SELECTOR, 0);
4136 vmcs_write16(HOST_ES_SELECTOR, 0);
4137#else
a3a8ff8e
NHE		 4138 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4139 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4140#endif
a3a8ff8e
NHE		 4141 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4142 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4143
4144 native_store_idt(&dt);
4145 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4146 vmx->host_idt_base = dt.address;
a3a8ff8e 4147
83287ea4 4148 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4149
4150 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4151 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4152 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4153 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4154
4155 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4156 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4157 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4158 }
4159}
4160
bf8179a0
NHE		 4161static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4162{
4163 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4164 if (enable_ept)
4165 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4166 if (is_guest_mode(&vmx->vcpu))
4167 vmx->vcpu.arch.cr4_guest_owned_bits &=
4168 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4169 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4170}
4171
01e439be
YZ		 4172static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4173{
4174 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4175
4176 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4177 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4178 return pin_based_exec_ctrl;
4179}
4180
bf8179a0
NHE		 4181static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4182{
4183 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4184 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4185 exec_control &= ~CPU_BASED_TPR_SHADOW;
4186#ifdef CONFIG_X86_64
4187 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4188 CPU_BASED_CR8_LOAD_EXITING;
4189#endif
4190 }
4191 if (!enable_ept)
4192 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4193 CPU_BASED_CR3_LOAD_EXITING |
4194 CPU_BASED_INVLPG_EXITING;
4195 return exec_control;
4196}
4197
4198static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4199{
4200 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4201 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4202 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4203 if (vmx->vpid == 0)
4204 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4205 if (!enable_ept) {
4206 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4207 enable_unrestricted_guest = 0;
ad756a16
MJ		 4208 /* Enable INVPCID for non-ept guests may cause performance regression. */
4209 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4210 }
4211 if (!enable_unrestricted_guest)
4212 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4213 if (!ple_gap)
4214 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4215 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4216 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4217 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4218 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4219 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4220 (handle_vmptrld).
4221 We can NOT enable shadow_vmcs here because we don't have yet
4222 a current VMCS12
4223 */
4224 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4225 return exec_control;
4226}
4227
ce88decf
XG		 4228static void ept_set_mmio_spte_mask(void)
4229{
4230 /*
4231 * EPT Misconfigurations can be generated if the value of bits 2:0
4232 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4233 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4234 * spte.
4235 */
885032b9 4236 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4237}
4238
6aa8b732
AK		 4239/*
4240 * Sets up the vmcs for emulated real mode.
4241 */
8b9cf98c 4242static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4243{
2e4ce7f5 4244#ifdef CONFIG_X86_64
6aa8b732 4245 unsigned long a;
2e4ce7f5 4246#endif
6aa8b732 4247 int i;
6aa8b732 4248
6aa8b732 4249 /* I/O */
3e7c73e9
AK		 4250 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4251 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4252
4607c2d7
AG		 4253 if (enable_shadow_vmcs) {
4254 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4255 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4256 }
25c5f225 4257 if (cpu_has_vmx_msr_bitmap())
5897297b 4258 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4259
6aa8b732
AK		 4260 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4261
6aa8b732 4262 /* Control */
01e439be 4263 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4264
bf8179a0 4265 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4266
83ff3b9d 4267 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4268 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4269 vmx_secondary_exec_control(vmx));
83ff3b9d 4270 }
f78e0e2e 4271
01e439be 4272 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4273 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4274 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4275 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4276 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4277
4278 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4279
4280 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4281 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4282 }
4283
4b8d54f9
ZE		 4284 if (ple_gap) {
4285 vmcs_write32(PLE_GAP, ple_gap);
4286 vmcs_write32(PLE_WINDOW, ple_window);
4287 }
4288
c3707958
XG		 4289 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4290 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4291 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4292
9581d442
AK		 4293 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4294 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4295 vmx_set_constant_host_state(vmx);
05b3e0c2 4296#ifdef CONFIG_X86_64
6aa8b732
AK		 4297 rdmsrl(MSR_FS_BASE, a);
4298 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4299 rdmsrl(MSR_GS_BASE, a);
4300 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4301#else
4302 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4303 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4304#endif
4305
2cc51560
ED		 4306 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4307 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4308 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4309 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4310 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4311
468d472f 4312 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4313 u32 msr_low, msr_high;
4314 u64 host_pat;
468d472f
SY		 4315 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4316 host_pat = msr_low | ((u64) msr_high << 32);
4317 /* Write the default value follow host pat */
4318 vmcs_write64(GUEST_IA32_PAT, host_pat);
4319 /* Keep arch.pat sync with GUEST_IA32_PAT */
4320 vmx->vcpu.arch.pat = host_pat;
4321 }
4322
6aa8b732
AK		 4323 for (i = 0; i < NR_VMX_MSR; ++i) {
4324 u32 index = vmx_msr_index[i];
4325 u32 data_low, data_high;
a2fa3e9f 4326 int j = vmx->nmsrs;
6aa8b732
AK		 4327
4328 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4329 continue;
432bd6cb
AK		 4330 if (wrmsr_safe(index, data_low, data_high) < 0)
4331 continue;
26bb0981
AK		 4332 vmx->guest_msrs[j].index = i;
4333 vmx->guest_msrs[j].data = 0;
d5696725 4334 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4335 ++vmx->nmsrs;
6aa8b732 4336 }
6aa8b732 4337
1c3d14fe 4338 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4339
4340 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4341 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4342
e00c8cf2 4343 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4344 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4345
4346 return 0;
4347}
4348
57f252f2 4349static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4350{
4351 struct vcpu_vmx *vmx = to_vmx(vcpu);
4352 u64 msr;
e00c8cf2 4353
7ffd92c5 4354 vmx->rmode.vm86_active = 0;
e00c8cf2 4355
3b86cd99
JK		 4356 vmx->soft_vnmi_blocked = 0;
4357
ad312c7c 4358 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4359 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4360 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4361 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4362 msr |= MSR_IA32_APICBASE_BSP;
4363 kvm_set_apic_base(&vmx->vcpu, msr);
4364
2fb92db1
AK		 4365 vmx_segment_cache_clear(vmx);
4366
5706be0d 4367 seg_setup(VCPU_SREG_CS);
66450a21 4368 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4369 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4370
4371 seg_setup(VCPU_SREG_DS);
4372 seg_setup(VCPU_SREG_ES);
4373 seg_setup(VCPU_SREG_FS);
4374 seg_setup(VCPU_SREG_GS);
4375 seg_setup(VCPU_SREG_SS);
4376
4377 vmcs_write16(GUEST_TR_SELECTOR, 0);
4378 vmcs_writel(GUEST_TR_BASE, 0);
4379 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4380 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4381
4382 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4383 vmcs_writel(GUEST_LDTR_BASE, 0);
4384 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4385 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4386
4387 vmcs_write32(GUEST_SYSENTER_CS, 0);
4388 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4389 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4390
4391 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4392 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4393
e00c8cf2
AK		 4394 vmcs_writel(GUEST_GDTR_BASE, 0);
4395 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4396
4397 vmcs_writel(GUEST_IDTR_BASE, 0);
4398 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4399
443381a8 4400 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4401 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4402 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4403
e00c8cf2
AK		 4404 /* Special registers */
4405 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4406
4407 setup_msrs(vmx);
4408
6aa8b732
AK		 4409 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4410
f78e0e2e
SY		 4411 if (cpu_has_vmx_tpr_shadow()) {
4412 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4413 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4414 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4415 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4416 vmcs_write32(TPR_THRESHOLD, 0);
4417 }
4418
4419 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4420 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4421 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4422
01e439be
YZ		 4423 if (vmx_vm_has_apicv(vcpu->kvm))
4424 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4425
2384d2b3
SY		 4426 if (vmx->vpid != 0)
4427 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4428
fa40052c 4429 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4430 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4431 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4432 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4433 vmx_fpu_activate(&vmx->vcpu);
4434 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4435
b9d762fa 4436 vpid_sync_context(vmx);
6aa8b732
AK		 4437}
4438
b6f1250e
NHE		 4439/*
4440 * In nested virtualization, check if L1 asked to exit on external interrupts.
4441 * For most existing hypervisors, this will always return true.
4442 */
4443static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4444{
4445 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4446 PIN_BASED_EXT_INTR_MASK;
4447}
4448
ea8ceb83
JK		 4449static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4450{
4451 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4452 PIN_BASED_NMI_EXITING;
4453}
4454
730dca42 4455static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4456{
4457 u32 cpu_based_vm_exec_control;
730dca42
JK		 4458
4459 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4460 /*
4461 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4462 * inject to L1 now because L2 must run. The caller will have
4463 * to make L2 exit right after entry, so we can inject to L1
4464 * more promptly.
b6f1250e 4465 */
730dca42 4466 return -EBUSY;
3b86cd99
JK		 4467
4468 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4469 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4470 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4471 return 0;
3b86cd99
JK		 4472}
4473
03b28f81 4474static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4475{
4476 u32 cpu_based_vm_exec_control;
4477
03b28f81
JK		 4478 if (!cpu_has_virtual_nmis())
4479 return enable_irq_window(vcpu);
4480
4481 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4482 return enable_irq_window(vcpu);
3b86cd99
JK		 4483
4484 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4485 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4486 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4487 return 0;
3b86cd99
JK		 4488}
4489
66fd3f7f 4490static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4491{
9c8cba37 4492 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4493 uint32_t intr;
4494 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4495
229456fc 4496 trace_kvm_inj_virq(irq);
2714d1d3 4497
fa89a817 4498 ++vcpu->stat.irq_injections;
7ffd92c5 4499 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4500 int inc_eip = 0;
4501 if (vcpu->arch.interrupt.soft)
4502 inc_eip = vcpu->arch.event_exit_inst_len;
4503 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4504 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4505 return;
4506 }
66fd3f7f
GN		 4507 intr = irq | INTR_INFO_VALID_MASK;
4508 if (vcpu->arch.interrupt.soft) {
4509 intr |= INTR_TYPE_SOFT_INTR;
4510 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4511 vmx->vcpu.arch.event_exit_inst_len);
4512 } else
4513 intr |= INTR_TYPE_EXT_INTR;
4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4515}
4516
f08864b4
SY		 4517static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4518{
66a5a347
JK		 4519 struct vcpu_vmx *vmx = to_vmx(vcpu);
4520
0b6ac343
NHE		 4521 if (is_guest_mode(vcpu))
4522 return;
4523
3b86cd99
JK		 4524 if (!cpu_has_virtual_nmis()) {
4525 /*
4526 * Tracking the NMI-blocked state in software is built upon
4527 * finding the next open IRQ window. This, in turn, depends on
4528 * well-behaving guests: They have to keep IRQs disabled at
4529 * least as long as the NMI handler runs. Otherwise we may
4530 * cause NMI nesting, maybe breaking the guest. But as this is
4531 * highly unlikely, we can live with the residual risk.
4532 */
4533 vmx->soft_vnmi_blocked = 1;
4534 vmx->vnmi_blocked_time = 0;
4535 }
4536
487b391d 4537 ++vcpu->stat.nmi_injections;
9d58b931 4538 vmx->nmi_known_unmasked = false;
7ffd92c5 4539 if (vmx->rmode.vm86_active) {
71f9833b 4540 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4541 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4542 return;
4543 }
f08864b4
SY		 4544 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4545 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4546}
4547
3cfc3092
JK		 4548static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4549{
4550 if (!cpu_has_virtual_nmis())
4551 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4552 if (to_vmx(vcpu)->nmi_known_unmasked)
4553 return false;
c332c83a 4554 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4555}
4556
4557static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4558{
4559 struct vcpu_vmx *vmx = to_vmx(vcpu);
4560
4561 if (!cpu_has_virtual_nmis()) {
4562 if (vmx->soft_vnmi_blocked != masked) {
4563 vmx->soft_vnmi_blocked = masked;
4564 vmx->vnmi_blocked_time = 0;
4565 }
4566 } else {
9d58b931 4567 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4568 if (masked)
4569 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4570 GUEST_INTR_STATE_NMI);
4571 else
4572 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4573 GUEST_INTR_STATE_NMI);
4574 }
4575}
4576
2505dc9f
JK		 4577static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4578{
ea8ceb83
JK		 4579 if (is_guest_mode(vcpu)) {
4580 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4581
4582 if (to_vmx(vcpu)->nested.nested_run_pending)
4583 return 0;
4584 if (nested_exit_on_nmi(vcpu)) {
4585 nested_vmx_vmexit(vcpu);
4586 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4587 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4588 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4589 /*
4590 * The NMI-triggered VM exit counts as injection:
4591 * clear this one and block further NMIs.
4592 */
4593 vcpu->arch.nmi_pending = 0;
4594 vmx_set_nmi_mask(vcpu, true);
4595 return 0;
4596 }
4597 }
4598
2505dc9f
JK		 4599 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4600 return 0;
4601
4602 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4603 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4604 | GUEST_INTR_STATE_NMI));
4605}
4606
78646121
GN		 4607static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4608{
e8457c67 4609 if (is_guest_mode(vcpu)) {
51cfe38e 4610 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4611
4612 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4613 return 0;
e8457c67
JK		 4614 if (nested_exit_on_intr(vcpu)) {
4615 nested_vmx_vmexit(vcpu);
4616 vmcs12->vm_exit_reason =
4617 EXIT_REASON_EXTERNAL_INTERRUPT;
4618 vmcs12->vm_exit_intr_info = 0;
4619 /*
4620 * fall through to normal code, but now in L1, not L2
4621 */
4622 }
b6f1250e
NHE		 4623 }
4624
c4282df9
GN		 4625 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4626 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4627 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4628}
4629
cbc94022
IE		 4630static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4631{
4632 int ret;
4633 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4634 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4635 .guest_phys_addr = addr,
4636 .memory_size = PAGE_SIZE * 3,
4637 .flags = 0,
4638 };
4639
47ae31e2 4640 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4641 if (ret)
4642 return ret;
bfc6d222 4643 kvm->arch.tss_addr = addr;
93ea5388
GN		 4644 if (!init_rmode_tss(kvm))
4645 return -ENOMEM;
4646
cbc94022
IE		 4647 return 0;
4648}
4649
0ca1b4f4 4650static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4651{
77ab6db0 4652 switch (vec) {
77ab6db0 4653 case BP_VECTOR:
c573cd22
JK		 4654 /*
4655 * Update instruction length as we may reinject the exception
4656 * from user space while in guest debugging mode.
4657 */
4658 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4659 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4660 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4661 return false;
4662 /* fall through */
4663 case DB_VECTOR:
4664 if (vcpu->guest_debug &
4665 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4666 return false;
d0bfb940
JK		 4667 /* fall through */
4668 case DE_VECTOR:
77ab6db0
JK		 4669 case OF_VECTOR:
4670 case BR_VECTOR:
4671 case UD_VECTOR:
4672 case DF_VECTOR:
4673 case SS_VECTOR:
4674 case GP_VECTOR:
4675 case MF_VECTOR:
0ca1b4f4
GN		 4676 return true;
4677 break;
77ab6db0 4678 }
0ca1b4f4
GN		 4679 return false;
4680}
4681
4682static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4683 int vec, u32 err_code)
4684{
4685 /*
4686 * Instruction with address size override prefix opcode 0x67
4687 * Cause the #SS fault with 0 error code in VM86 mode.
4688 */
4689 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4690 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4691 if (vcpu->arch.halt_request) {
4692 vcpu->arch.halt_request = 0;
4693 return kvm_emulate_halt(vcpu);
4694 }
4695 return 1;
4696 }
4697 return 0;
4698 }
4699
4700 /*
4701 * Forward all other exceptions that are valid in real mode.
4702 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4703 * the required debugging infrastructure rework.
4704 */
4705 kvm_queue_exception(vcpu, vec);
4706 return 1;
6aa8b732
AK		 4707}
4708
a0861c02
AK		 4709/*
4710 * Trigger machine check on the host. We assume all the MSRs are already set up
4711 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4712 * We pass a fake environment to the machine check handler because we want
4713 * the guest to be always treated like user space, no matter what context
4714 * it used internally.
4715 */
4716static void kvm_machine_check(void)
4717{
4718#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4719 struct pt_regs regs = {
4720 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4721 .flags = X86_EFLAGS_IF,
4722 };
4723
4724 do_machine_check(&regs, 0);
4725#endif
4726}
4727
851ba692 4728static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4729{
4730 /* already handled by vcpu_run */
4731 return 1;
4732}
4733
851ba692 4734static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4735{
1155f76a 4736 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4737 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4738 u32 intr_info, ex_no, error_code;
42dbaa5a 4739 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4740 u32 vect_info;
4741 enum emulation_result er;
4742
1155f76a 4743 vect_info = vmx->idt_vectoring_info;
88786475 4744 intr_info = vmx->exit_intr_info;
6aa8b732 4745
a0861c02 4746 if (is_machine_check(intr_info))
851ba692 4747 return handle_machine_check(vcpu);
a0861c02 4748
e4a41889 4749 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4750 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4751
4752 if (is_no_device(intr_info)) {
5fd86fcf 4753 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4754 return 1;
4755 }
4756
7aa81cc0 4757 if (is_invalid_opcode(intr_info)) {
51d8b661 4758 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4759 if (er != EMULATE_DONE)
7ee5d940 4760 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4761 return 1;
4762 }
4763
6aa8b732 4764 error_code = 0;
2e11384c 4765 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4766 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4767
4768 /*
4769 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4770 * MMIO, it is better to report an internal error.
4771 * See the comments in vmx_handle_exit.
4772 */
4773 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4774 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4775 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4776 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4777 vcpu->run->internal.ndata = 2;
4778 vcpu->run->internal.data[0] = vect_info;
4779 vcpu->run->internal.data[1] = intr_info;
4780 return 0;
4781 }
4782
6aa8b732 4783 if (is_page_fault(intr_info)) {
1439442c 4784 /* EPT won't cause page fault directly */
cf3ace79 4785 BUG_ON(enable_ept);
6aa8b732 4786 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4787 trace_kvm_page_fault(cr2, error_code);
4788
3298b75c 4789 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4790 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4791 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4792 }
4793
d0bfb940 4794 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4795
4796 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4797 return handle_rmode_exception(vcpu, ex_no, error_code);
4798
42dbaa5a
JK		 4799 switch (ex_no) {
4800 case DB_VECTOR:
4801 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4802 if (!(vcpu->guest_debug &
4803 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4804 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4805 kvm_queue_exception(vcpu, DB_VECTOR);
4806 return 1;
4807 }
4808 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4809 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4810 /* fall through */
4811 case BP_VECTOR:
c573cd22
JK		 4812 /*
4813 * Update instruction length as we may reinject #BP from
4814 * user space while in guest debugging mode. Reading it for
4815 * #DB as well causes no harm, it is not used in that case.
4816 */
4817 vmx->vcpu.arch.event_exit_inst_len =
4818 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4819 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4820 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4821 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4822 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4823 break;
4824 default:
d0bfb940
JK		 4825 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4826 kvm_run->ex.exception = ex_no;
4827 kvm_run->ex.error_code = error_code;
42dbaa5a 4828 break;
6aa8b732 4829 }
6aa8b732
AK		 4830 return 0;
4831}
4832
851ba692 4833static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4834{
1165f5fe 4835 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4836 return 1;
4837}
4838
851ba692 4839static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4840{
851ba692 4841 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4842 return 0;
4843}
6aa8b732 4844
851ba692 4845static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4846{
bfdaab09 4847 unsigned long exit_qualification;
34c33d16 4848 int size, in, string;
039576c0 4849 unsigned port;
6aa8b732 4850
bfdaab09 4851 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4852 string = (exit_qualification & 16) != 0;
cf8f70bf 4853 in = (exit_qualification & 8) != 0;
e70669ab 4854
cf8f70bf 4855 ++vcpu->stat.io_exits;
e70669ab 4856
cf8f70bf 4857 if (string || in)
51d8b661 4858 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4859
cf8f70bf
GN		 4860 port = exit_qualification >> 16;
4861 size = (exit_qualification & 7) + 1;
e93f36bc 4862 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4863
4864 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4865}
4866
102d8325
IM		 4867static void
4868vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4869{
4870 /*
4871 * Patch in the VMCALL instruction:
4872 */
4873 hypercall[0] = 0x0f;
4874 hypercall[1] = 0x01;
4875 hypercall[2] = 0xc1;
102d8325
IM		 4876}
4877
0fa06071 4878/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4879static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4880{
eeadf9e7 4881 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4883 unsigned long orig_val = val;
4884
eeadf9e7
NHE		 4885 /*
4886 * We get here when L2 changed cr0 in a way that did not change
4887 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4888 * but did change L0 shadowed bits. So we first calculate the
4889 * effective cr0 value that L1 would like to write into the
4890 * hardware. It consists of the L2-owned bits from the new
4891 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4892 */
1a0d74e6
JK		 4893 val = (val & ~vmcs12->cr0_guest_host_mask) |
4894 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4895
4896 /* TODO: will have to take unrestricted guest mode into
4897 * account */
4898 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4899 return 1;
1a0d74e6
JK		 4900
4901 if (kvm_set_cr0(vcpu, val))
4902 return 1;
4903 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4904 return 0;
1a0d74e6
JK		 4905 } else {
4906 if (to_vmx(vcpu)->nested.vmxon &&
4907 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4908 return 1;
eeadf9e7 4909 return kvm_set_cr0(vcpu, val);
1a0d74e6 4910 }
eeadf9e7
NHE		 4911}
4912
4913static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4914{
4915 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4916 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4917 unsigned long orig_val = val;
4918
4919 /* analogously to handle_set_cr0 */
4920 val = (val & ~vmcs12->cr4_guest_host_mask) |
4921 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4922 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4923 return 1;
1a0d74e6 4924 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4925 return 0;
4926 } else
4927 return kvm_set_cr4(vcpu, val);
4928}
4929
4930/* called to set cr0 as approriate for clts instruction exit. */
4931static void handle_clts(struct kvm_vcpu *vcpu)
4932{
4933 if (is_guest_mode(vcpu)) {
4934 /*
4935 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4936 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4937 * just pretend it's off (also in arch.cr0 for fpu_activate).
4938 */
4939 vmcs_writel(CR0_READ_SHADOW,
4940 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4941 vcpu->arch.cr0 &= ~X86_CR0_TS;
4942 } else
4943 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4944}
4945
851ba692 4946static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4947{
229456fc 4948 unsigned long exit_qualification, val;
6aa8b732
AK		 4949 int cr;
4950 int reg;
49a9b07e 4951 int err;
6aa8b732 4952
bfdaab09 4953 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4954 cr = exit_qualification & 15;
4955 reg = (exit_qualification >> 8) & 15;
4956 switch ((exit_qualification >> 4) & 3) {
4957 case 0: /* mov to cr */
229456fc
MT		 4958 val = kvm_register_read(vcpu, reg);
4959 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4960 switch (cr) {
4961 case 0:
eeadf9e7 4962 err = handle_set_cr0(vcpu, val);
db8fcefa 4963 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4964 return 1;
4965 case 3:
2390218b 4966 err = kvm_set_cr3(vcpu, val);
db8fcefa 4967 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4968 return 1;
4969 case 4:
eeadf9e7 4970 err = handle_set_cr4(vcpu, val);
db8fcefa 4971 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4972 return 1;
0a5fff19
GN		 4973 case 8: {
4974 u8 cr8_prev = kvm_get_cr8(vcpu);
4975 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4976 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4977 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4978 if (irqchip_in_kernel(vcpu->kvm))
4979 return 1;
4980 if (cr8_prev <= cr8)
4981 return 1;
851ba692 4982 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4983 return 0;
4984 }
4b8073e4 4985 }
6aa8b732 4986 break;
25c4c276 4987 case 2: /* clts */
eeadf9e7 4988 handle_clts(vcpu);
4d4ec087 4989 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4990 skip_emulated_instruction(vcpu);
6b52d186 4991 vmx_fpu_activate(vcpu);
25c4c276 4992 return 1;
6aa8b732
AK		 4993 case 1: /*mov from cr*/
4994 switch (cr) {
4995 case 3:
9f8fe504
AK		 4996 val = kvm_read_cr3(vcpu);
4997 kvm_register_write(vcpu, reg, val);
4998 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4999 skip_emulated_instruction(vcpu);
5000 return 1;
5001 case 8:
229456fc
MT		 5002 val = kvm_get_cr8(vcpu);
5003 kvm_register_write(vcpu, reg, val);
5004 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5005 skip_emulated_instruction(vcpu);
5006 return 1;
5007 }
5008 break;
5009 case 3: /* lmsw */
a1f83a74 5010 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5011 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5012 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5013
5014 skip_emulated_instruction(vcpu);
5015 return 1;
5016 default:
5017 break;
5018 }
851ba692 5019 vcpu->run->exit_reason = 0;
a737f256 5020 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5021 (int)(exit_qualification >> 4) & 3, cr);
5022 return 0;
5023}
5024
851ba692 5025static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5026{
bfdaab09 5027 unsigned long exit_qualification;
6aa8b732
AK		 5028 int dr, reg;
5029
f2483415 5030 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5031 if (!kvm_require_cpl(vcpu, 0))
5032 return 1;
42dbaa5a
JK		 5033 dr = vmcs_readl(GUEST_DR7);
5034 if (dr & DR7_GD) {
5035 /*
5036 * As the vm-exit takes precedence over the debug trap, we
5037 * need to emulate the latter, either for the host or the
5038 * guest debugging itself.
5039 */
5040 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5041 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5042 vcpu->run->debug.arch.dr7 = dr;
5043 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5044 vmcs_readl(GUEST_CS_BASE) +
5045 vmcs_readl(GUEST_RIP);
851ba692
AK		 5046 vcpu->run->debug.arch.exception = DB_VECTOR;
5047 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5048 return 0;
5049 } else {
5050 vcpu->arch.dr7 &= ~DR7_GD;
5051 vcpu->arch.dr6 |= DR6_BD;
5052 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5053 kvm_queue_exception(vcpu, DB_VECTOR);
5054 return 1;
5055 }
5056 }
5057
bfdaab09 5058 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5059 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5060 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5061 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5062 unsigned long val;
5063 if (!kvm_get_dr(vcpu, dr, &val))
5064 kvm_register_write(vcpu, reg, val);
5065 } else
5066 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5067 skip_emulated_instruction(vcpu);
5068 return 1;
5069}
5070
020df079
GN		 5071static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5072{
5073 vmcs_writel(GUEST_DR7, val);
5074}
5075
851ba692 5076static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5077{
06465c5a
AK		 5078 kvm_emulate_cpuid(vcpu);
5079 return 1;
6aa8b732
AK		 5080}
5081
851ba692 5082static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5083{
ad312c7c 5084 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5085 u64 data;
5086
5087 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5088 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5089 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5090 return 1;
5091 }
5092
229456fc 5093 trace_kvm_msr_read(ecx, data);
2714d1d3 5094
6aa8b732 5095 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5096 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5097 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5098 skip_emulated_instruction(vcpu);
5099 return 1;
5100}
5101
851ba692 5102static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5103{
8fe8ab46 5104 struct msr_data msr;
ad312c7c
ZX		 5105 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5106 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5107 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5108
8fe8ab46
WA		 5109 msr.data = data;
5110 msr.index = ecx;
5111 msr.host_initiated = false;
5112 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5113 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5114 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5115 return 1;
5116 }
5117
59200273 5118 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5119 skip_emulated_instruction(vcpu);
5120 return 1;
5121}
5122
851ba692 5123static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5124{
3842d135 5125 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5126 return 1;
5127}
5128
851ba692 5129static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5130{
85f455f7
ED		 5131 u32 cpu_based_vm_exec_control;
5132
5133 /* clear pending irq */
5134 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5135 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5136 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5137
3842d135
AK		 5138 kvm_make_request(KVM_REQ_EVENT, vcpu);
5139
a26bf12a 5140 ++vcpu->stat.irq_window_exits;
2714d1d3 5141
c1150d8c
DL		 5142 /*
5143 * If the user space waits to inject interrupts, exit as soon as
5144 * possible
5145 */
8061823a 5146 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5147 vcpu->run->request_interrupt_window &&
8061823a 5148 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5149 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5150 return 0;
5151 }
6aa8b732
AK		 5152 return 1;
5153}
5154
851ba692 5155static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5156{
5157 skip_emulated_instruction(vcpu);
d3bef15f 5158 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5159}
5160
851ba692 5161static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5162{
510043da 5163 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5164 kvm_emulate_hypercall(vcpu);
5165 return 1;
c21415e8
IM		 5166}
5167
ec25d5e6
GN		 5168static int handle_invd(struct kvm_vcpu *vcpu)
5169{
51d8b661 5170 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5171}
5172
851ba692 5173static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5174{
f9c617f6 5175 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5176
5177 kvm_mmu_invlpg(vcpu, exit_qualification);
5178 skip_emulated_instruction(vcpu);
5179 return 1;
5180}
5181
fee84b07
AK		 5182static int handle_rdpmc(struct kvm_vcpu *vcpu)
5183{
5184 int err;
5185
5186 err = kvm_rdpmc(vcpu);
5187 kvm_complete_insn_gp(vcpu, err);
5188
5189 return 1;
5190}
5191
851ba692 5192static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5193{
5194 skip_emulated_instruction(vcpu);
f5f48ee1 5195 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5196 return 1;
5197}
5198
2acf923e
DC		 5199static int handle_xsetbv(struct kvm_vcpu *vcpu)
5200{
5201 u64 new_bv = kvm_read_edx_eax(vcpu);
5202 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5203
5204 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5205 skip_emulated_instruction(vcpu);
5206 return 1;
5207}
5208
851ba692 5209static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5210{
58fbbf26
KT		 5211 if (likely(fasteoi)) {
5212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5213 int access_type, offset;
5214
5215 access_type = exit_qualification & APIC_ACCESS_TYPE;
5216 offset = exit_qualification & APIC_ACCESS_OFFSET;
5217 /*
5218 * Sane guest uses MOV to write EOI, with written value
5219 * not cared. So make a short-circuit here by avoiding
5220 * heavy instruction emulation.
5221 */
5222 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5223 (offset == APIC_EOI)) {
5224 kvm_lapic_set_eoi(vcpu);
5225 skip_emulated_instruction(vcpu);
5226 return 1;
5227 }
5228 }
51d8b661 5229 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5230}
5231
c7c9c56c
YZ		 5232static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5233{
5234 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5235 int vector = exit_qualification & 0xff;
5236
5237 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5238 kvm_apic_set_eoi_accelerated(vcpu, vector);
5239 return 1;
5240}
5241
83d4c286
YZ		 5242static int handle_apic_write(struct kvm_vcpu *vcpu)
5243{
5244 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5245 u32 offset = exit_qualification & 0xfff;
5246
5247 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5248 kvm_apic_write_nodecode(vcpu, offset);
5249 return 1;
5250}
5251
851ba692 5252static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5253{
60637aac 5254 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5255 unsigned long exit_qualification;
e269fb21
JK		 5256 bool has_error_code = false;
5257 u32 error_code = 0;
37817f29 5258 u16 tss_selector;
7f3d35fd 5259 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5260
5261 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5262 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5263 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5264
5265 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5266
5267 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5268 if (reason == TASK_SWITCH_GATE && idt_v) {
5269 switch (type) {
5270 case INTR_TYPE_NMI_INTR:
5271 vcpu->arch.nmi_injected = false;
654f06fc 5272 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5273 break;
5274 case INTR_TYPE_EXT_INTR:
66fd3f7f 5275 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5276 kvm_clear_interrupt_queue(vcpu);
5277 break;
5278 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5279 if (vmx->idt_vectoring_info &
5280 VECTORING_INFO_DELIVER_CODE_MASK) {
5281 has_error_code = true;
5282 error_code =
5283 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5284 }
5285 /* fall through */
64a7ec06
GN		 5286 case INTR_TYPE_SOFT_EXCEPTION:
5287 kvm_clear_exception_queue(vcpu);
5288 break;
5289 default:
5290 break;
5291 }
60637aac 5292 }
37817f29
IE		 5293 tss_selector = exit_qualification;
5294
64a7ec06
GN		 5295 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5296 type != INTR_TYPE_EXT_INTR &&
5297 type != INTR_TYPE_NMI_INTR))
5298 skip_emulated_instruction(vcpu);
5299
7f3d35fd
KW		 5300 if (kvm_task_switch(vcpu, tss_selector,
5301 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5302 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5303 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5304 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5305 vcpu->run->internal.ndata = 0;
42dbaa5a 5306 return 0;
acb54517 5307 }
42dbaa5a
JK		 5308
5309 /* clear all local breakpoint enable flags */
5310 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5311
5312 /*
5313 * TODO: What about debug traps on tss switch?
5314 * Are we supposed to inject them and update dr6?
5315 */
5316
5317 return 1;
37817f29
IE		 5318}
5319
851ba692 5320static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5321{
f9c617f6 5322 unsigned long exit_qualification;
1439442c 5323 gpa_t gpa;
4f5982a5 5324 u32 error_code;
1439442c 5325 int gla_validity;
1439442c 5326
f9c617f6 5327 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5328
1439442c
SY		 5329 gla_validity = (exit_qualification >> 7) & 0x3;
5330 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5331 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5332 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5333 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5334 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5335 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5336 (long unsigned int)exit_qualification);
851ba692
AK		 5337 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5338 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5339 return 0;
1439442c
SY		 5340 }
5341
0be9c7a8
GN		 5342 /*
5343 * EPT violation happened while executing iret from NMI,
5344 * "blocked by NMI" bit has to be set before next VM entry.
5345 * There are errata that may cause this bit to not be set:
5346 * AAK134, BY25.
5347 */
5348 if (exit_qualification & INTR_INFO_UNBLOCK_NMI)
5349 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5350
1439442c 5351 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5352 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5353
5354 /* It is a write fault? */
5355 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5356 /* It is a fetch fault? */
5357 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5358 /* ept page table is present? */
5359 error_code |= (exit_qualification >> 3) & 0x1;
5360
25d92081
YZ		 5361 vcpu->arch.exit_qualification = exit_qualification;
5362
4f5982a5 5363 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5364}
5365
68f89400
MT		 5366static u64 ept_rsvd_mask(u64 spte, int level)
5367{
5368 int i;
5369 u64 mask = 0;
5370
5371 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5372 mask |= (1ULL << i);
5373
5374 if (level > 2)
5375 /* bits 7:3 reserved */
5376 mask |= 0xf8;
5377 else if (level == 2) {
5378 if (spte & (1ULL << 7))
5379 /* 2MB ref, bits 20:12 reserved */
5380 mask |= 0x1ff000;
5381 else
5382 /* bits 6:3 reserved */
5383 mask |= 0x78;
5384 }
5385
5386 return mask;
5387}
5388
5389static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5390 int level)
5391{
5392 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5393
5394 /* 010b (write-only) */
5395 WARN_ON((spte & 0x7) == 0x2);
5396
5397 /* 110b (write/execute) */
5398 WARN_ON((spte & 0x7) == 0x6);
5399
5400 /* 100b (execute-only) and value not supported by logical processor */
5401 if (!cpu_has_vmx_ept_execute_only())
5402 WARN_ON((spte & 0x7) == 0x4);
5403
5404 /* not 000b */
5405 if ((spte & 0x7)) {
5406 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5407
5408 if (rsvd_bits != 0) {
5409 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5410 __func__, rsvd_bits);
5411 WARN_ON(1);
5412 }
5413
5414 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5415 u64 ept_mem_type = (spte & 0x38) >> 3;
5416
5417 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5418 ept_mem_type == 7) {
5419 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5420 __func__, ept_mem_type);
5421 WARN_ON(1);
5422 }
5423 }
5424 }
5425}
5426
851ba692 5427static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5428{
5429 u64 sptes[4];
ce88decf 5430 int nr_sptes, i, ret;
68f89400
MT		 5431 gpa_t gpa;
5432
5433 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5434
ce88decf 5435 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5436 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5437 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5438 EMULATE_DONE;
f8f55942
XG		 5439
5440 if (unlikely(ret == RET_MMIO_PF_INVALID))
5441 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5442
b37fbea6 5443 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5444 return 1;
5445
5446 /* It is the real ept misconfig */
68f89400
MT		 5447 printk(KERN_ERR "EPT: Misconfiguration.\n");
5448 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5449
5450 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5451
5452 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5453 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5454
851ba692
AK		 5455 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5456 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5457
5458 return 0;
5459}
5460
851ba692 5461static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5462{
5463 u32 cpu_based_vm_exec_control;
5464
5465 /* clear pending NMI */
5466 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5467 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5468 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5469 ++vcpu->stat.nmi_window_exits;
3842d135 5470 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5471
5472 return 1;
5473}
5474
80ced186 5475static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5476{
8b3079a5
AK		 5477 struct vcpu_vmx *vmx = to_vmx(vcpu);
5478 enum emulation_result err = EMULATE_DONE;
80ced186 5479 int ret = 1;
49e9d557
AK		 5480 u32 cpu_exec_ctrl;
5481 bool intr_window_requested;
b8405c18 5482 unsigned count = 130;
49e9d557
AK		 5483
5484 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5485 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5486
b8405c18 5487 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5488 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5489 return handle_interrupt_window(&vmx->vcpu);
5490
de87dcdd
AK		 5491 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5492 return 1;
5493
991eebf9 5494 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5495
ac0a48c3 5496 if (err == EMULATE_USER_EXIT) {
94452b9e 5497 ++vcpu->stat.mmio_exits;
80ced186
MG		 5498 ret = 0;
5499 goto out;
5500 }
1d5a4d9b 5501
de5f70e0
AK		 5502 if (err != EMULATE_DONE) {
5503 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5504 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5505 vcpu->run->internal.ndata = 0;
6d77dbfc 5506 return 0;
de5f70e0 5507 }
ea953ef0 5508
8d76c49e
GN		 5509 if (vcpu->arch.halt_request) {
5510 vcpu->arch.halt_request = 0;
5511 ret = kvm_emulate_halt(vcpu);
5512 goto out;
5513 }
5514
ea953ef0 5515 if (signal_pending(current))
80ced186 5516 goto out;
ea953ef0
MG		 5517 if (need_resched())
5518 schedule();
5519 }
5520
14168786 5521 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5522out:
5523 return ret;
ea953ef0
MG		 5524}
5525
4b8d54f9
ZE		 5526/*
5527 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5528 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5529 */
9fb41ba8 5530static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5531{
5532 skip_emulated_instruction(vcpu);
5533 kvm_vcpu_on_spin(vcpu);
5534
5535 return 1;
5536}
5537
59708670
SY		 5538static int handle_invalid_op(struct kvm_vcpu *vcpu)
5539{
5540 kvm_queue_exception(vcpu, UD_VECTOR);
5541 return 1;
5542}
5543
ff2f6fe9
NHE		 5544/*
5545 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5546 * We could reuse a single VMCS for all the L2 guests, but we also want the
5547 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5548 * allows keeping them loaded on the processor, and in the future will allow
5549 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5550 * every entry if they never change.
5551 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5552 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5553 *
5554 * The following functions allocate and free a vmcs02 in this pool.
5555 */
5556
5557/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5558static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5559{
5560 struct vmcs02_list *item;
5561 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5562 if (item->vmptr == vmx->nested.current_vmptr) {
5563 list_move(&item->list, &vmx->nested.vmcs02_pool);
5564 return &item->vmcs02;
5565 }
5566
5567 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5568 /* Recycle the least recently used VMCS. */
5569 item = list_entry(vmx->nested.vmcs02_pool.prev,
5570 struct vmcs02_list, list);
5571 item->vmptr = vmx->nested.current_vmptr;
5572 list_move(&item->list, &vmx->nested.vmcs02_pool);
5573 return &item->vmcs02;
5574 }
5575
5576 /* Create a new VMCS */
0fa24ce3 5577 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5578 if (!item)
5579 return NULL;
5580 item->vmcs02.vmcs = alloc_vmcs();
5581 if (!item->vmcs02.vmcs) {
5582 kfree(item);
5583 return NULL;
5584 }
5585 loaded_vmcs_init(&item->vmcs02);
5586 item->vmptr = vmx->nested.current_vmptr;
5587 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5588 vmx->nested.vmcs02_num++;
5589 return &item->vmcs02;
5590}
5591
5592/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5593static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5594{
5595 struct vmcs02_list *item;
5596 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5597 if (item->vmptr == vmptr) {
5598 free_loaded_vmcs(&item->vmcs02);
5599 list_del(&item->list);
5600 kfree(item);
5601 vmx->nested.vmcs02_num--;
5602 return;
5603 }
5604}
5605
5606/*
5607 * Free all VMCSs saved for this vcpu, except the one pointed by
5608 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5609 * currently used, if running L2), and vmcs01 when running L2.
5610 */
5611static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5612{
5613 struct vmcs02_list *item, *n;
5614 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5615 if (vmx->loaded_vmcs != &item->vmcs02)
5616 free_loaded_vmcs(&item->vmcs02);
5617 list_del(&item->list);
5618 kfree(item);
5619 }
5620 vmx->nested.vmcs02_num = 0;
5621
5622 if (vmx->loaded_vmcs != &vmx->vmcs01)
5623 free_loaded_vmcs(&vmx->vmcs01);
5624}
5625
0658fbaa
ACL		 5626/*
5627 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5628 * set the success or error code of an emulated VMX instruction, as specified
5629 * by Vol 2B, VMX Instruction Reference, "Conventions".
5630 */
5631static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5632{
5633 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5634 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5635 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5636}
5637
5638static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5639{
5640 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5641 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5642 X86_EFLAGS_SF | X86_EFLAGS_OF))
5643 | X86_EFLAGS_CF);
5644}
5645
145c28dd 5646static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5647 u32 vm_instruction_error)
5648{
5649 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5650 /*
5651 * failValid writes the error number to the current VMCS, which
5652 * can't be done there isn't a current VMCS.
5653 */
5654 nested_vmx_failInvalid(vcpu);
5655 return;
5656 }
5657 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5658 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5659 X86_EFLAGS_SF | X86_EFLAGS_OF))
5660 | X86_EFLAGS_ZF);
5661 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5662 /*
5663 * We don't need to force a shadow sync because
5664 * VM_INSTRUCTION_ERROR is not shadowed
5665 */
5666}
145c28dd 5667
ec378aee
NHE		 5668/*
5669 * Emulate the VMXON instruction.
5670 * Currently, we just remember that VMX is active, and do not save or even
5671 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5672 * do not currently need to store anything in that guest-allocated memory
5673 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5674 * argument is different from the VMXON pointer (which the spec says they do).
5675 */
5676static int handle_vmon(struct kvm_vcpu *vcpu)
5677{
5678 struct kvm_segment cs;
5679 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5680 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5681 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5682 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5683
5684 /* The Intel VMX Instruction Reference lists a bunch of bits that
5685 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5686 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5687 * Otherwise, we should fail with #UD. We test these now:
5688 */
5689 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5690 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5691 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5692 kvm_queue_exception(vcpu, UD_VECTOR);
5693 return 1;
5694 }
5695
5696 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5697 if (is_long_mode(vcpu) && !cs.l) {
5698 kvm_queue_exception(vcpu, UD_VECTOR);
5699 return 1;
5700 }
5701
5702 if (vmx_get_cpl(vcpu)) {
5703 kvm_inject_gp(vcpu, 0);
5704 return 1;
5705 }
145c28dd
AG		 5706 if (vmx->nested.vmxon) {
5707 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5708 skip_emulated_instruction(vcpu);
5709 return 1;
5710 }
b3897a49
NHE		 5711
5712 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5713 != VMXON_NEEDED_FEATURES) {
5714 kvm_inject_gp(vcpu, 0);
5715 return 1;
5716 }
5717
8de48833
AG		 5718 if (enable_shadow_vmcs) {
5719 shadow_vmcs = alloc_vmcs();
5720 if (!shadow_vmcs)
5721 return -ENOMEM;
5722 /* mark vmcs as shadow */
5723 shadow_vmcs->revision_id |= (1u << 31);
5724 /* init shadow vmcs */
5725 vmcs_clear(shadow_vmcs);
5726 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5727 }
ec378aee 5728
ff2f6fe9
NHE		 5729 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5730 vmx->nested.vmcs02_num = 0;
5731
ec378aee
NHE		 5732 vmx->nested.vmxon = true;
5733
5734 skip_emulated_instruction(vcpu);
a25eb114 5735 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5736 return 1;
5737}
5738
5739/*
5740 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5741 * for running VMX instructions (except VMXON, whose prerequisites are
5742 * slightly different). It also specifies what exception to inject otherwise.
5743 */
5744static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5745{
5746 struct kvm_segment cs;
5747 struct vcpu_vmx *vmx = to_vmx(vcpu);
5748
5749 if (!vmx->nested.vmxon) {
5750 kvm_queue_exception(vcpu, UD_VECTOR);
5751 return 0;
5752 }
5753
5754 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5755 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5756 (is_long_mode(vcpu) && !cs.l)) {
5757 kvm_queue_exception(vcpu, UD_VECTOR);
5758 return 0;
5759 }
5760
5761 if (vmx_get_cpl(vcpu)) {
5762 kvm_inject_gp(vcpu, 0);
5763 return 0;
5764 }
5765
5766 return 1;
5767}
5768
e7953d7f
AG		 5769static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5770{
8a1b9dd0 5771 u32 exec_control;
012f83cb
AG		 5772 if (enable_shadow_vmcs) {
5773 if (vmx->nested.current_vmcs12 != NULL) {
5774 /* copy to memory all shadowed fields in case
5775 they were modified */
5776 copy_shadow_to_vmcs12(vmx);
5777 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5778 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5779 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5780 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5781 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5782 }
5783 }
e7953d7f
AG		 5784 kunmap(vmx->nested.current_vmcs12_page);
5785 nested_release_page(vmx->nested.current_vmcs12_page);
5786}
5787
ec378aee
NHE		 5788/*
5789 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5790 * just stops using VMX.
5791 */
5792static void free_nested(struct vcpu_vmx *vmx)
5793{
5794 if (!vmx->nested.vmxon)
5795 return;
5796 vmx->nested.vmxon = false;
a9d30f33 5797 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5798 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5799 vmx->nested.current_vmptr = -1ull;
5800 vmx->nested.current_vmcs12 = NULL;
5801 }
e7953d7f
AG		 5802 if (enable_shadow_vmcs)
5803 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5804 /* Unpin physical memory we referred to in current vmcs02 */
5805 if (vmx->nested.apic_access_page) {
5806 nested_release_page(vmx->nested.apic_access_page);
5807 vmx->nested.apic_access_page = 0;
5808 }
ff2f6fe9
NHE		 5809
5810 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5811}
5812
5813/* Emulate the VMXOFF instruction */
5814static int handle_vmoff(struct kvm_vcpu *vcpu)
5815{
5816 if (!nested_vmx_check_permission(vcpu))
5817 return 1;
5818 free_nested(to_vmx(vcpu));
5819 skip_emulated_instruction(vcpu);
a25eb114 5820 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5821 return 1;
5822}
5823
064aea77
NHE		 5824/*
5825 * Decode the memory-address operand of a vmx instruction, as recorded on an
5826 * exit caused by such an instruction (run by a guest hypervisor).
5827 * On success, returns 0. When the operand is invalid, returns 1 and throws
5828 * #UD or #GP.
5829 */
5830static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5831 unsigned long exit_qualification,
5832 u32 vmx_instruction_info, gva_t *ret)
5833{
5834 /*
5835 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5836 * Execution", on an exit, vmx_instruction_info holds most of the
5837 * addressing components of the operand. Only the displacement part
5838 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5839 * For how an actual address is calculated from all these components,
5840 * refer to Vol. 1, "Operand Addressing".
5841 */
5842 int scaling = vmx_instruction_info & 3;
5843 int addr_size = (vmx_instruction_info >> 7) & 7;
5844 bool is_reg = vmx_instruction_info & (1u << 10);
5845 int seg_reg = (vmx_instruction_info >> 15) & 7;
5846 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5847 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5848 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5849 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5850
5851 if (is_reg) {
5852 kvm_queue_exception(vcpu, UD_VECTOR);
5853 return 1;
5854 }
5855
5856 /* Addr = segment_base + offset */
5857 /* offset = base + [index * scale] + displacement */
5858 *ret = vmx_get_segment_base(vcpu, seg_reg);
5859 if (base_is_valid)
5860 *ret += kvm_register_read(vcpu, base_reg);
5861 if (index_is_valid)
5862 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5863 *ret += exit_qualification; /* holds the displacement */
5864
5865 if (addr_size == 1) /* 32 bit */
5866 *ret &= 0xffffffff;
5867
5868 /*
5869 * TODO: throw #GP (and return 1) in various cases that the VM*
5870 * instructions require it - e.g., offset beyond segment limit,
5871 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5872 * address, and so on. Currently these are not checked.
5873 */
5874 return 0;
5875}
5876
27d6c865
NHE		 5877/* Emulate the VMCLEAR instruction */
5878static int handle_vmclear(struct kvm_vcpu *vcpu)
5879{
5880 struct vcpu_vmx *vmx = to_vmx(vcpu);
5881 gva_t gva;
5882 gpa_t vmptr;
5883 struct vmcs12 *vmcs12;
5884 struct page *page;
5885 struct x86_exception e;
5886
5887 if (!nested_vmx_check_permission(vcpu))
5888 return 1;
5889
5890 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5891 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5892 return 1;
5893
5894 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5895 sizeof(vmptr), &e)) {
5896 kvm_inject_page_fault(vcpu, &e);
5897 return 1;
5898 }
5899
5900 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5901 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5902 skip_emulated_instruction(vcpu);
5903 return 1;
5904 }
5905
5906 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5907 nested_release_vmcs12(vmx);
27d6c865
NHE		 5908 vmx->nested.current_vmptr = -1ull;
5909 vmx->nested.current_vmcs12 = NULL;
5910 }
5911
5912 page = nested_get_page(vcpu, vmptr);
5913 if (page == NULL) {
5914 /*
5915 * For accurate processor emulation, VMCLEAR beyond available
5916 * physical memory should do nothing at all. However, it is
5917 * possible that a nested vmx bug, not a guest hypervisor bug,
5918 * resulted in this case, so let's shut down before doing any
5919 * more damage:
5920 */
5921 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5922 return 1;
5923 }
5924 vmcs12 = kmap(page);
5925 vmcs12->launch_state = 0;
5926 kunmap(page);
5927 nested_release_page(page);
5928
5929 nested_free_vmcs02(vmx, vmptr);
5930
5931 skip_emulated_instruction(vcpu);
5932 nested_vmx_succeed(vcpu);
5933 return 1;
5934}
5935
cd232ad0
NHE		 5936static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5937
5938/* Emulate the VMLAUNCH instruction */
5939static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5940{
5941 return nested_vmx_run(vcpu, true);
5942}
5943
5944/* Emulate the VMRESUME instruction */
5945static int handle_vmresume(struct kvm_vcpu *vcpu)
5946{
5947
5948 return nested_vmx_run(vcpu, false);
5949}
5950
49f705c5
NHE		 5951enum vmcs_field_type {
5952 VMCS_FIELD_TYPE_U16 = 0,
5953 VMCS_FIELD_TYPE_U64 = 1,
5954 VMCS_FIELD_TYPE_U32 = 2,
5955 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5956};
5957
5958static inline int vmcs_field_type(unsigned long field)
5959{
5960 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5961 return VMCS_FIELD_TYPE_U32;
5962 return (field >> 13) & 0x3 ;
5963}
5964
5965static inline int vmcs_field_readonly(unsigned long field)
5966{
5967 return (((field >> 10) & 0x3) == 1);
5968}
5969
5970/*
5971 * Read a vmcs12 field. Since these can have varying lengths and we return
5972 * one type, we chose the biggest type (u64) and zero-extend the return value
5973 * to that size. Note that the caller, handle_vmread, might need to use only
5974 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5975 * 64-bit fields are to be returned).
5976 */
5977static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5978 unsigned long field, u64 *ret)
5979{
5980 short offset = vmcs_field_to_offset(field);
5981 char *p;
5982
5983 if (offset < 0)
5984 return 0;
5985
5986 p = ((char *)(get_vmcs12(vcpu))) + offset;
5987
5988 switch (vmcs_field_type(field)) {
5989 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5990 *ret = *((natural_width *)p);
5991 return 1;
5992 case VMCS_FIELD_TYPE_U16:
5993 *ret = *((u16 *)p);
5994 return 1;
5995 case VMCS_FIELD_TYPE_U32:
5996 *ret = *((u32 *)p);
5997 return 1;
5998 case VMCS_FIELD_TYPE_U64:
5999 *ret = *((u64 *)p);
6000 return 1;
6001 default:
6002 return 0; /* can never happen. */
6003 }
6004}
6005
20b97fea
AG		 6006
6007static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6008 unsigned long field, u64 field_value){
6009 short offset = vmcs_field_to_offset(field);
6010 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6011 if (offset < 0)
6012 return false;
6013
6014 switch (vmcs_field_type(field)) {
6015 case VMCS_FIELD_TYPE_U16:
6016 *(u16 *)p = field_value;
6017 return true;
6018 case VMCS_FIELD_TYPE_U32:
6019 *(u32 *)p = field_value;
6020 return true;
6021 case VMCS_FIELD_TYPE_U64:
6022 *(u64 *)p = field_value;
6023 return true;
6024 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6025 *(natural_width *)p = field_value;
6026 return true;
6027 default:
6028 return false; /* can never happen. */
6029 }
6030
6031}
6032
16f5b903
AG		 6033static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6034{
6035 int i;
6036 unsigned long field;
6037 u64 field_value;
6038 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6039 const unsigned long *fields = shadow_read_write_fields;
6040 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6041
6042 vmcs_load(shadow_vmcs);
6043
6044 for (i = 0; i < num_fields; i++) {
6045 field = fields[i];
6046 switch (vmcs_field_type(field)) {
6047 case VMCS_FIELD_TYPE_U16:
6048 field_value = vmcs_read16(field);
6049 break;
6050 case VMCS_FIELD_TYPE_U32:
6051 field_value = vmcs_read32(field);
6052 break;
6053 case VMCS_FIELD_TYPE_U64:
6054 field_value = vmcs_read64(field);
6055 break;
6056 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6057 field_value = vmcs_readl(field);
6058 break;
6059 }
6060 vmcs12_write_any(&vmx->vcpu, field, field_value);
6061 }
6062
6063 vmcs_clear(shadow_vmcs);
6064 vmcs_load(vmx->loaded_vmcs->vmcs);
6065}
6066
c3114420
AG		 6067static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6068{
c2bae893
MK		 6069 const unsigned long *fields[] = {
6070 shadow_read_write_fields,
6071 shadow_read_only_fields
c3114420 6072 };
c2bae893 6073 const int max_fields[] = {
c3114420
AG		 6074 max_shadow_read_write_fields,
6075 max_shadow_read_only_fields
6076 };
6077 int i, q;
6078 unsigned long field;
6079 u64 field_value = 0;
6080 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6081
6082 vmcs_load(shadow_vmcs);
6083
c2bae893 6084 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6085 for (i = 0; i < max_fields[q]; i++) {
6086 field = fields[q][i];
6087 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6088
6089 switch (vmcs_field_type(field)) {
6090 case VMCS_FIELD_TYPE_U16:
6091 vmcs_write16(field, (u16)field_value);
6092 break;
6093 case VMCS_FIELD_TYPE_U32:
6094 vmcs_write32(field, (u32)field_value);
6095 break;
6096 case VMCS_FIELD_TYPE_U64:
6097 vmcs_write64(field, (u64)field_value);
6098 break;
6099 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6100 vmcs_writel(field, (long)field_value);
6101 break;
6102 }
6103 }
6104 }
6105
6106 vmcs_clear(shadow_vmcs);
6107 vmcs_load(vmx->loaded_vmcs->vmcs);
6108}
6109
49f705c5
NHE		 6110/*
6111 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6112 * used before) all generate the same failure when it is missing.
6113 */
6114static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6115{
6116 struct vcpu_vmx *vmx = to_vmx(vcpu);
6117 if (vmx->nested.current_vmptr == -1ull) {
6118 nested_vmx_failInvalid(vcpu);
6119 skip_emulated_instruction(vcpu);
6120 return 0;
6121 }
6122 return 1;
6123}
6124
6125static int handle_vmread(struct kvm_vcpu *vcpu)
6126{
6127 unsigned long field;
6128 u64 field_value;
6129 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6130 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6131 gva_t gva = 0;
6132
6133 if (!nested_vmx_check_permission(vcpu) ||
6134 !nested_vmx_check_vmcs12(vcpu))
6135 return 1;
6136
6137 /* Decode instruction info and find the field to read */
6138 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6139 /* Read the field, zero-extended to a u64 field_value */
6140 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6141 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6142 skip_emulated_instruction(vcpu);
6143 return 1;
6144 }
6145 /*
6146 * Now copy part of this value to register or memory, as requested.
6147 * Note that the number of bits actually copied is 32 or 64 depending
6148 * on the guest's mode (32 or 64 bit), not on the given field's length.
6149 */
6150 if (vmx_instruction_info & (1u << 10)) {
6151 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6152 field_value);
6153 } else {
6154 if (get_vmx_mem_address(vcpu, exit_qualification,
6155 vmx_instruction_info, &gva))
6156 return 1;
6157 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6158 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6159 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6160 }
6161
6162 nested_vmx_succeed(vcpu);
6163 skip_emulated_instruction(vcpu);
6164 return 1;
6165}
6166
6167
6168static int handle_vmwrite(struct kvm_vcpu *vcpu)
6169{
6170 unsigned long field;
6171 gva_t gva;
6172 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6173 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6174 /* The value to write might be 32 or 64 bits, depending on L1's long
6175 * mode, and eventually we need to write that into a field of several
6176 * possible lengths. The code below first zero-extends the value to 64
6177 * bit (field_value), and then copies only the approriate number of
6178 * bits into the vmcs12 field.
6179 */
6180 u64 field_value = 0;
6181 struct x86_exception e;
6182
6183 if (!nested_vmx_check_permission(vcpu) ||
6184 !nested_vmx_check_vmcs12(vcpu))
6185 return 1;
6186
6187 if (vmx_instruction_info & (1u << 10))
6188 field_value = kvm_register_read(vcpu,
6189 (((vmx_instruction_info) >> 3) & 0xf));
6190 else {
6191 if (get_vmx_mem_address(vcpu, exit_qualification,
6192 vmx_instruction_info, &gva))
6193 return 1;
6194 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6195 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6196 kvm_inject_page_fault(vcpu, &e);
6197 return 1;
6198 }
6199 }
6200
6201
6202 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6203 if (vmcs_field_readonly(field)) {
6204 nested_vmx_failValid(vcpu,
6205 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6206 skip_emulated_instruction(vcpu);
6207 return 1;
6208 }
6209
20b97fea 6210 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6211 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6212 skip_emulated_instruction(vcpu);
6213 return 1;
6214 }
6215
6216 nested_vmx_succeed(vcpu);
6217 skip_emulated_instruction(vcpu);
6218 return 1;
6219}
6220
63846663
NHE		 6221/* Emulate the VMPTRLD instruction */
6222static int handle_vmptrld(struct kvm_vcpu *vcpu)
6223{
6224 struct vcpu_vmx *vmx = to_vmx(vcpu);
6225 gva_t gva;
6226 gpa_t vmptr;
6227 struct x86_exception e;
8a1b9dd0 6228 u32 exec_control;
63846663
NHE		 6229
6230 if (!nested_vmx_check_permission(vcpu))
6231 return 1;
6232
6233 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6234 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6235 return 1;
6236
6237 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6238 sizeof(vmptr), &e)) {
6239 kvm_inject_page_fault(vcpu, &e);
6240 return 1;
6241 }
6242
6243 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6244 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6245 skip_emulated_instruction(vcpu);
6246 return 1;
6247 }
6248
6249 if (vmx->nested.current_vmptr != vmptr) {
6250 struct vmcs12 *new_vmcs12;
6251 struct page *page;
6252 page = nested_get_page(vcpu, vmptr);
6253 if (page == NULL) {
6254 nested_vmx_failInvalid(vcpu);
6255 skip_emulated_instruction(vcpu);
6256 return 1;
6257 }
6258 new_vmcs12 = kmap(page);
6259 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6260 kunmap(page);
6261 nested_release_page_clean(page);
6262 nested_vmx_failValid(vcpu,
6263 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6264 skip_emulated_instruction(vcpu);
6265 return 1;
6266 }
e7953d7f
AG		 6267 if (vmx->nested.current_vmptr != -1ull)
6268 nested_release_vmcs12(vmx);
63846663
NHE		 6269
6270 vmx->nested.current_vmptr = vmptr;
6271 vmx->nested.current_vmcs12 = new_vmcs12;
6272 vmx->nested.current_vmcs12_page = page;
012f83cb 6273 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6274 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6275 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6276 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6277 vmcs_write64(VMCS_LINK_POINTER,
6278 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6279 vmx->nested.sync_shadow_vmcs = true;
6280 }
63846663
NHE		 6281 }
6282
6283 nested_vmx_succeed(vcpu);
6284 skip_emulated_instruction(vcpu);
6285 return 1;
6286}
6287
6a4d7550
NHE		 6288/* Emulate the VMPTRST instruction */
6289static int handle_vmptrst(struct kvm_vcpu *vcpu)
6290{
6291 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6292 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6293 gva_t vmcs_gva;
6294 struct x86_exception e;
6295
6296 if (!nested_vmx_check_permission(vcpu))
6297 return 1;
6298
6299 if (get_vmx_mem_address(vcpu, exit_qualification,
6300 vmx_instruction_info, &vmcs_gva))
6301 return 1;
6302 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6303 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6304 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6305 sizeof(u64), &e)) {
6306 kvm_inject_page_fault(vcpu, &e);
6307 return 1;
6308 }
6309 nested_vmx_succeed(vcpu);
6310 skip_emulated_instruction(vcpu);
6311 return 1;
6312}
6313
bfd0a56b
NHE		 6314/* Emulate the INVEPT instruction */
6315static int handle_invept(struct kvm_vcpu *vcpu)
6316{
6317 u32 vmx_instruction_info, types;
6318 unsigned long type;
6319 gva_t gva;
6320 struct x86_exception e;
6321 struct {
6322 u64 eptp, gpa;
6323 } operand;
6324 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6325
6326 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6327 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6328 kvm_queue_exception(vcpu, UD_VECTOR);
6329 return 1;
6330 }
6331
6332 if (!nested_vmx_check_permission(vcpu))
6333 return 1;
6334
6335 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6336 kvm_queue_exception(vcpu, UD_VECTOR);
6337 return 1;
6338 }
6339
6340 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6341 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6342
6343 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6344
6345 if (!(types & (1UL << type))) {
6346 nested_vmx_failValid(vcpu,
6347 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6348 return 1;
6349 }
6350
6351 /* According to the Intel VMX instruction reference, the memory
6352 * operand is read even if it isn't needed (e.g., for type==global)
6353 */
6354 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6355 vmx_instruction_info, &gva))
6356 return 1;
6357 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6358 sizeof(operand), &e)) {
6359 kvm_inject_page_fault(vcpu, &e);
6360 return 1;
6361 }
6362
6363 switch (type) {
6364 case VMX_EPT_EXTENT_CONTEXT:
6365 if ((operand.eptp & eptp_mask) !=
6366 (nested_ept_get_cr3(vcpu) & eptp_mask))
6367 break;
6368 case VMX_EPT_EXTENT_GLOBAL:
6369 kvm_mmu_sync_roots(vcpu);
6370 kvm_mmu_flush_tlb(vcpu);
6371 nested_vmx_succeed(vcpu);
6372 break;
6373 default:
6374 BUG_ON(1);
6375 break;
6376 }
6377
6378 skip_emulated_instruction(vcpu);
6379 return 1;
6380}
6381
6aa8b732
AK		 6382/*
6383 * The exit handlers return 1 if the exit was handled fully and guest execution
6384 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6385 * to be done to userspace and return 0.
6386 */
772e0318 6387static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6388 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6389 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6390 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6391 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6392 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6393 [EXIT_REASON_CR_ACCESS] = handle_cr,
6394 [EXIT_REASON_DR_ACCESS] = handle_dr,
6395 [EXIT_REASON_CPUID] = handle_cpuid,
6396 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6397 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6398 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6399 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6400 [EXIT_REASON_INVD] = handle_invd,
a7052897 6401 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6402 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6403 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6404 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6405 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6406 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6407 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6408 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6409 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6410 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6411 [EXIT_REASON_VMOFF] = handle_vmoff,
6412 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6413 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6414 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6415 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6416 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6417 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6418 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6419 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6420 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6421 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6422 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6423 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6424 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6425 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6426 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6427};
6428
6429static const int kvm_vmx_max_exit_handlers =
50a3485c 6430 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6431
908a7bdd
JK		 6432static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6433 struct vmcs12 *vmcs12)
6434{
6435 unsigned long exit_qualification;
6436 gpa_t bitmap, last_bitmap;
6437 unsigned int port;
6438 int size;
6439 u8 b;
6440
6441 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6442 return 1;
6443
6444 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6445 return 0;
6446
6447 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6448
6449 port = exit_qualification >> 16;
6450 size = (exit_qualification & 7) + 1;
6451
6452 last_bitmap = (gpa_t)-1;
6453 b = -1;
6454
6455 while (size > 0) {
6456 if (port < 0x8000)
6457 bitmap = vmcs12->io_bitmap_a;
6458 else if (port < 0x10000)
6459 bitmap = vmcs12->io_bitmap_b;
6460 else
6461 return 1;
6462 bitmap += (port & 0x7fff) / 8;
6463
6464 if (last_bitmap != bitmap)
6465 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6466 return 1;
6467 if (b & (1 << (port & 7)))
6468 return 1;
6469
6470 port++;
6471 size--;
6472 last_bitmap = bitmap;
6473 }
6474
6475 return 0;
6476}
6477
644d711a
NHE		 6478/*
6479 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6480 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6481 * disinterest in the current event (read or write a specific MSR) by using an
6482 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6483 */
6484static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6485 struct vmcs12 *vmcs12, u32 exit_reason)
6486{
6487 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6488 gpa_t bitmap;
6489
cbd29cb6 6490 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6491 return 1;
6492
6493 /*
6494 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6495 * for the four combinations of read/write and low/high MSR numbers.
6496 * First we need to figure out which of the four to use:
6497 */
6498 bitmap = vmcs12->msr_bitmap;
6499 if (exit_reason == EXIT_REASON_MSR_WRITE)
6500 bitmap += 2048;
6501 if (msr_index >= 0xc0000000) {
6502 msr_index -= 0xc0000000;
6503 bitmap += 1024;
6504 }
6505
6506 /* Then read the msr_index'th bit from this bitmap: */
6507 if (msr_index < 1024*8) {
6508 unsigned char b;
bd31a7f5
JK		 6509 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6510 return 1;
644d711a
NHE		 6511 return 1 & (b >> (msr_index & 7));
6512 } else
6513 return 1; /* let L1 handle the wrong parameter */
6514}
6515
6516/*
6517 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6518 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6519 * intercept (via guest_host_mask etc.) the current event.
6520 */
6521static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6522 struct vmcs12 *vmcs12)
6523{
6524 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6525 int cr = exit_qualification & 15;
6526 int reg = (exit_qualification >> 8) & 15;
6527 unsigned long val = kvm_register_read(vcpu, reg);
6528
6529 switch ((exit_qualification >> 4) & 3) {
6530 case 0: /* mov to cr */
6531 switch (cr) {
6532 case 0:
6533 if (vmcs12->cr0_guest_host_mask &
6534 (val ^ vmcs12->cr0_read_shadow))
6535 return 1;
6536 break;
6537 case 3:
6538 if ((vmcs12->cr3_target_count >= 1 &&
6539 vmcs12->cr3_target_value0 == val) ||
6540 (vmcs12->cr3_target_count >= 2 &&
6541 vmcs12->cr3_target_value1 == val) ||
6542 (vmcs12->cr3_target_count >= 3 &&
6543 vmcs12->cr3_target_value2 == val) ||
6544 (vmcs12->cr3_target_count >= 4 &&
6545 vmcs12->cr3_target_value3 == val))
6546 return 0;
6547 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6548 return 1;
6549 break;
6550 case 4:
6551 if (vmcs12->cr4_guest_host_mask &
6552 (vmcs12->cr4_read_shadow ^ val))
6553 return 1;
6554 break;
6555 case 8:
6556 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6557 return 1;
6558 break;
6559 }
6560 break;
6561 case 2: /* clts */
6562 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6563 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6564 return 1;
6565 break;
6566 case 1: /* mov from cr */
6567 switch (cr) {
6568 case 3:
6569 if (vmcs12->cpu_based_vm_exec_control &
6570 CPU_BASED_CR3_STORE_EXITING)
6571 return 1;
6572 break;
6573 case 8:
6574 if (vmcs12->cpu_based_vm_exec_control &
6575 CPU_BASED_CR8_STORE_EXITING)
6576 return 1;
6577 break;
6578 }
6579 break;
6580 case 3: /* lmsw */
6581 /*
6582 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6583 * cr0. Other attempted changes are ignored, with no exit.
6584 */
6585 if (vmcs12->cr0_guest_host_mask & 0xe &
6586 (val ^ vmcs12->cr0_read_shadow))
6587 return 1;
6588 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6589 !(vmcs12->cr0_read_shadow & 0x1) &&
6590 (val & 0x1))
6591 return 1;
6592 break;
6593 }
6594 return 0;
6595}
6596
6597/*
6598 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6599 * should handle it ourselves in L0 (and then continue L2). Only call this
6600 * when in is_guest_mode (L2).
6601 */
6602static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6603{
644d711a
NHE		 6604 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6605 struct vcpu_vmx *vmx = to_vmx(vcpu);
6606 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6607 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6608
6609 if (vmx->nested.nested_run_pending)
6610 return 0;
6611
6612 if (unlikely(vmx->fail)) {
bd80158a
JK		 6613 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6614 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6615 return 1;
6616 }
6617
6618 switch (exit_reason) {
6619 case EXIT_REASON_EXCEPTION_NMI:
6620 if (!is_exception(intr_info))
6621 return 0;
6622 else if (is_page_fault(intr_info))
6623 return enable_ept;
6624 return vmcs12->exception_bitmap &
6625 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6626 case EXIT_REASON_EXTERNAL_INTERRUPT:
6627 return 0;
6628 case EXIT_REASON_TRIPLE_FAULT:
6629 return 1;
6630 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6631 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6632 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6633 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6634 case EXIT_REASON_TASK_SWITCH:
6635 return 1;
6636 case EXIT_REASON_CPUID:
6637 return 1;
6638 case EXIT_REASON_HLT:
6639 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6640 case EXIT_REASON_INVD:
6641 return 1;
6642 case EXIT_REASON_INVLPG:
6643 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6644 case EXIT_REASON_RDPMC:
6645 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6646 case EXIT_REASON_RDTSC:
6647 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6648 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6649 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6650 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6651 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6652 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6653 case EXIT_REASON_INVEPT:
644d711a
NHE		 6654 /*
6655 * VMX instructions trap unconditionally. This allows L1 to
6656 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6657 */
6658 return 1;
6659 case EXIT_REASON_CR_ACCESS:
6660 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6661 case EXIT_REASON_DR_ACCESS:
6662 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6663 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6664 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6665 case EXIT_REASON_MSR_READ:
6666 case EXIT_REASON_MSR_WRITE:
6667 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6668 case EXIT_REASON_INVALID_STATE:
6669 return 1;
6670 case EXIT_REASON_MWAIT_INSTRUCTION:
6671 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6672 case EXIT_REASON_MONITOR_INSTRUCTION:
6673 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6674 case EXIT_REASON_PAUSE_INSTRUCTION:
6675 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6676 nested_cpu_has2(vmcs12,
6677 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6678 case EXIT_REASON_MCE_DURING_VMENTRY:
6679 return 0;
6680 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6681 return 1;
6682 case EXIT_REASON_APIC_ACCESS:
6683 return nested_cpu_has2(vmcs12,
6684 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6685 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6686 /*
6687 * L0 always deals with the EPT violation. If nested EPT is
6688 * used, and the nested mmu code discovers that the address is
6689 * missing in the guest EPT table (EPT12), the EPT violation
6690 * will be injected with nested_ept_inject_page_fault()
6691 */
6692 return 0;
644d711a 6693 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6694 /*
6695 * L2 never uses directly L1's EPT, but rather L0's own EPT
6696 * table (shadow on EPT) or a merged EPT table that L0 built
6697 * (EPT on EPT). So any problems with the structure of the
6698 * table is L0's fault.
6699 */
644d711a 6700 return 0;
0238ea91
JK		 6701 case EXIT_REASON_PREEMPTION_TIMER:
6702 return vmcs12->pin_based_vm_exec_control &
6703 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6704 case EXIT_REASON_WBINVD:
6705 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6706 case EXIT_REASON_XSETBV:
6707 return 1;
6708 default:
6709 return 1;
6710 }
6711}
6712
586f9607
AK		 6713static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6714{
6715 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6716 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6717}
6718
6aa8b732
AK		 6719/*
6720 * The guest has exited. See if we can fix it or if we need userspace
6721 * assistance.
6722 */
851ba692 6723static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6724{
29bd8a78 6725 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6726 u32 exit_reason = vmx->exit_reason;
1155f76a 6727 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6728
80ced186 6729 /* If guest state is invalid, start emulating */
14168786 6730 if (vmx->emulation_required)
80ced186 6731 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6732
b6f1250e
NHE		 6733 /*
6734 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6735 * we did not inject a still-pending event to L1 now because of
6736 * nested_run_pending, we need to re-enable this bit.
6737 */
6738 if (vmx->nested.nested_run_pending)
6739 kvm_make_request(KVM_REQ_EVENT, vcpu);
6740
509c75ea
NHE		 6741 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6742 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6743 vmx->nested.nested_run_pending = 1;
6744 else
6745 vmx->nested.nested_run_pending = 0;
6746
6747 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6748 nested_vmx_vmexit(vcpu);
6749 return 1;
6750 }
6751
5120702e
MG		 6752 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6753 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6754 vcpu->run->fail_entry.hardware_entry_failure_reason
6755 = exit_reason;
6756 return 0;
6757 }
6758
29bd8a78 6759 if (unlikely(vmx->fail)) {
851ba692
AK		 6760 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6761 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6762 = vmcs_read32(VM_INSTRUCTION_ERROR);
6763 return 0;
6764 }
6aa8b732 6765
b9bf6882
XG		 6766 /*
6767 * Note:
6768 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6769 * delivery event since it indicates guest is accessing MMIO.
6770 * The vm-exit can be triggered again after return to guest that
6771 * will cause infinite loop.
6772 */
d77c26fc 6773 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6774 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6775 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6776 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6777 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6778 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6779 vcpu->run->internal.ndata = 2;
6780 vcpu->run->internal.data[0] = vectoring_info;
6781 vcpu->run->internal.data[1] = exit_reason;
6782 return 0;
6783 }
3b86cd99 6784
644d711a
NHE		 6785 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6786 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6787 get_vmcs12(vcpu))))) {
c4282df9 6788 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6789 vmx->soft_vnmi_blocked = 0;
3b86cd99 6790 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6791 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6792 /*
6793 * This CPU don't support us in finding the end of an
6794 * NMI-blocked window if the guest runs with IRQs
6795 * disabled. So we pull the trigger after 1 s of
6796 * futile waiting, but inform the user about this.
6797 */
6798 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6799 "state on VCPU %d after 1 s timeout\n",
6800 __func__, vcpu->vcpu_id);
6801 vmx->soft_vnmi_blocked = 0;
3b86cd99 6802 }
3b86cd99
JK		 6803 }
6804
6aa8b732
AK		 6805 if (exit_reason < kvm_vmx_max_exit_handlers
6806 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6807 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6808 else {
851ba692
AK		 6809 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6810 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6811 }
6812 return 0;
6813}
6814
95ba8273 6815static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6816{
95ba8273 6817 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6818 vmcs_write32(TPR_THRESHOLD, 0);
6819 return;
6820 }
6821
95ba8273 6822 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6823}
6824
8d14695f
YZ		 6825static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6826{
6827 u32 sec_exec_control;
6828
6829 /*
6830 * There is not point to enable virtualize x2apic without enable
6831 * apicv
6832 */
c7c9c56c
YZ		 6833 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6834 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6835 return;
6836
6837 if (!vm_need_tpr_shadow(vcpu->kvm))
6838 return;
6839
6840 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6841
6842 if (set) {
6843 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6844 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6845 } else {
6846 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6847 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6848 }
6849 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6850
6851 vmx_set_msr_bitmap(vcpu);
6852}
6853
c7c9c56c
YZ		 6854static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6855{
6856 u16 status;
6857 u8 old;
6858
6859 if (!vmx_vm_has_apicv(kvm))
6860 return;
6861
6862 if (isr == -1)
6863 isr = 0;
6864
6865 status = vmcs_read16(GUEST_INTR_STATUS);
6866 old = status >> 8;
6867 if (isr != old) {
6868 status &= 0xff;
6869 status |= isr << 8;
6870 vmcs_write16(GUEST_INTR_STATUS, status);
6871 }
6872}
6873
6874static void vmx_set_rvi(int vector)
6875{
6876 u16 status;
6877 u8 old;
6878
6879 status = vmcs_read16(GUEST_INTR_STATUS);
6880 old = (u8)status & 0xff;
6881 if ((u8)vector != old) {
6882 status &= ~0xff;
6883 status |= (u8)vector;
6884 vmcs_write16(GUEST_INTR_STATUS, status);
6885 }
6886}
6887
6888static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6889{
6890 if (max_irr == -1)
6891 return;
6892
6893 vmx_set_rvi(max_irr);
6894}
6895
6896static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6897{
3d81bc7e
YZ		 6898 if (!vmx_vm_has_apicv(vcpu->kvm))
6899 return;
6900
c7c9c56c
YZ		 6901 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6902 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6903 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6904 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6905}
6906
51aa01d1 6907static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6908{
00eba012
AK		 6909 u32 exit_intr_info;
6910
6911 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6912 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6913 return;
6914
c5ca8e57 6915 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6916 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6917
6918 /* Handle machine checks before interrupts are enabled */
00eba012 6919 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6920 kvm_machine_check();
6921
20f65983 6922 /* We need to handle NMIs before interrupts are enabled */
00eba012 6923 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6924 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6925 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6926 asm("int $2");
ff9d07a0
ZY		 6927 kvm_after_handle_nmi(&vmx->vcpu);
6928 }
51aa01d1 6929}
20f65983 6930
a547c6db
YZ		 6931static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6932{
6933 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6934
6935 /*
6936 * If external interrupt exists, IF bit is set in rflags/eflags on the
6937 * interrupt stack frame, and interrupt will be enabled on a return
6938 * from interrupt handler.
6939 */
6940 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6941 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6942 unsigned int vector;
6943 unsigned long entry;
6944 gate_desc *desc;
6945 struct vcpu_vmx *vmx = to_vmx(vcpu);
6946#ifdef CONFIG_X86_64
6947 unsigned long tmp;
6948#endif
6949
6950 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6951 desc = (gate_desc *)vmx->host_idt_base + vector;
6952 entry = gate_offset(*desc);
6953 asm volatile(
6954#ifdef CONFIG_X86_64
6955 "mov %%" _ASM_SP ", %[sp]\n\t"
6956 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6957 "push $%c[ss]\n\t"
6958 "push %[sp]\n\t"
6959#endif
6960 "pushf\n\t"
6961 "orl $0x200, (%%" _ASM_SP ")\n\t"
6962 __ASM_SIZE(push) " $%c[cs]\n\t"
6963 "call *%[entry]\n\t"
6964 :
6965#ifdef CONFIG_X86_64
6966 [sp]"=&r"(tmp)
6967#endif
6968 :
6969 [entry]"r"(entry),
6970 [ss]"i"(__KERNEL_DS),
6971 [cs]"i"(__KERNEL_CS)
6972 );
6973 } else
6974 local_irq_enable();
6975}
6976
51aa01d1
AK		 6977static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6978{
c5ca8e57 6979 u32 exit_intr_info;
51aa01d1
AK		 6980 bool unblock_nmi;
6981 u8 vector;
6982 bool idtv_info_valid;
6983
6984 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6985
cf393f75 6986 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6987 if (vmx->nmi_known_unmasked)
6988 return;
c5ca8e57
AK		 6989 /*
6990 * Can't use vmx->exit_intr_info since we're not sure what
6991 * the exit reason is.
6992 */
6993 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6994 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6995 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6996 /*
7b4a25cb 6997 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6998 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6999 * a guest IRET fault.
7b4a25cb
GN		 7000 * SDM 3: 23.2.2 (September 2008)
7001 * Bit 12 is undefined in any of the following cases:
7002 * If the VM exit sets the valid bit in the IDT-vectoring
7003 * information field.
7004 * If the VM exit is due to a double fault.
cf393f75 7005 */
7b4a25cb
GN		 7006 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7007 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7008 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7009 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7010 else
7011 vmx->nmi_known_unmasked =
7012 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7013 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7014 } else if (unlikely(vmx->soft_vnmi_blocked))
7015 vmx->vnmi_blocked_time +=
7016 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7017}
7018
3ab66e8a 7019static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7020 u32 idt_vectoring_info,
7021 int instr_len_field,
7022 int error_code_field)
51aa01d1 7023{
51aa01d1
AK		 7024 u8 vector;
7025 int type;
7026 bool idtv_info_valid;
7027
7028 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7029
3ab66e8a
JK		 7030 vcpu->arch.nmi_injected = false;
7031 kvm_clear_exception_queue(vcpu);
7032 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7033
7034 if (!idtv_info_valid)
7035 return;
7036
3ab66e8a 7037 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7038
668f612f
AK		 7039 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7040 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7041
64a7ec06 7042 switch (type) {
37b96e98 7043 case INTR_TYPE_NMI_INTR:
3ab66e8a 7044 vcpu->arch.nmi_injected = true;
668f612f 7045 /*
7b4a25cb 7046 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7047 * Clear bit "block by NMI" before VM entry if a NMI
7048 * delivery faulted.
668f612f 7049 */
3ab66e8a 7050 vmx_set_nmi_mask(vcpu, false);
37b96e98 7051 break;
37b96e98 7052 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7053 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7054 /* fall through */
7055 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7056 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7057 u32 err = vmcs_read32(error_code_field);
3ab66e8a 7058 kvm_queue_exception_e(vcpu, vector, err);
35920a35 7059 } else
3ab66e8a 7060 kvm_queue_exception(vcpu, vector);
37b96e98 7061 break;
66fd3f7f 7062 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7063 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7064 /* fall through */
37b96e98 7065 case INTR_TYPE_EXT_INTR:
3ab66e8a 7066 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7067 break;
7068 default:
7069 break;
f7d9238f 7070 }
cf393f75
AK		 7071}
7072
83422e17
AK		 7073static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7074{
3ab66e8a 7075 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7076 VM_EXIT_INSTRUCTION_LEN,
7077 IDT_VECTORING_ERROR_CODE);
7078}
7079
b463a6f7
AK		 7080static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7081{
3ab66e8a 7082 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7083 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7084 VM_ENTRY_INSTRUCTION_LEN,
7085 VM_ENTRY_EXCEPTION_ERROR_CODE);
7086
7087 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7088}
7089
d7cd9796
GN		 7090static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7091{
7092 int i, nr_msrs;
7093 struct perf_guest_switch_msr *msrs;
7094
7095 msrs = perf_guest_get_msrs(&nr_msrs);
7096
7097 if (!msrs)
7098 return;
7099
7100 for (i = 0; i < nr_msrs; i++)
7101 if (msrs[i].host == msrs[i].guest)
7102 clear_atomic_switch_msr(vmx, msrs[i].msr);
7103 else
7104 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7105 msrs[i].host);
7106}
7107
a3b5ba49 7108static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7109{
a2fa3e9f 7110 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7111 unsigned long debugctlmsr;
104f226b
AK		 7112
7113 /* Record the guest's net vcpu time for enforced NMI injections. */
7114 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7115 vmx->entry_time = ktime_get();
7116
7117 /* Don't enter VMX if guest state is invalid, let the exit handler
7118 start emulation until we arrive back to a valid state */
14168786 7119 if (vmx->emulation_required)
104f226b
AK		 7120 return;
7121
012f83cb
AG		 7122 if (vmx->nested.sync_shadow_vmcs) {
7123 copy_vmcs12_to_shadow(vmx);
7124 vmx->nested.sync_shadow_vmcs = false;
7125 }
7126
104f226b
AK		 7127 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7128 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7129 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7130 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7131
7132 /* When single-stepping over STI and MOV SS, we must clear the
7133 * corresponding interruptibility bits in the guest state. Otherwise
7134 * vmentry fails as it then expects bit 14 (BS) in pending debug
7135 * exceptions being set, but that's not correct for the guest debugging
7136 * case. */
7137 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7138 vmx_set_interrupt_shadow(vcpu, 0);
7139
d7cd9796 7140 atomic_switch_perf_msrs(vmx);
2a7921b7 7141 debugctlmsr = get_debugctlmsr();
d7cd9796 7142
d462b819 7143 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7144 asm(
6aa8b732 7145 /* Store host registers */
b188c81f
AK		 7146 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7147 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7148 "push %%" _ASM_CX " \n\t"
7149 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7150 "je 1f \n\t"
b188c81f 7151 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7152 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7153 "1: \n\t"
d3edefc0 7154 /* Reload cr2 if changed */
b188c81f
AK		 7155 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7156 "mov %%cr2, %%" _ASM_DX " \n\t"
7157 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7158 "je 2f \n\t"
b188c81f 7159 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7160 "2: \n\t"
6aa8b732 7161 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7162 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7163 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7164 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7165 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7166 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7167 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7168 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7169 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7170#ifdef CONFIG_X86_64
e08aa78a
AK		 7171 "mov %c[r8](%0), %%r8 \n\t"
7172 "mov %c[r9](%0), %%r9 \n\t"
7173 "mov %c[r10](%0), %%r10 \n\t"
7174 "mov %c[r11](%0), %%r11 \n\t"
7175 "mov %c[r12](%0), %%r12 \n\t"
7176 "mov %c[r13](%0), %%r13 \n\t"
7177 "mov %c[r14](%0), %%r14 \n\t"
7178 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7179#endif
b188c81f 7180 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7181
6aa8b732 7182 /* Enter guest mode */
83287ea4 7183 "jne 1f \n\t"
4ecac3fd 7184 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7185 "jmp 2f \n\t"
7186 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7187 "2: "
6aa8b732 7188 /* Save guest registers, load host registers, keep flags */
b188c81f 7189 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7190 "pop %0 \n\t"
b188c81f
AK		 7191 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7192 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7193 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7194 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7195 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7196 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7197 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7198#ifdef CONFIG_X86_64
e08aa78a
AK		 7199 "mov %%r8, %c[r8](%0) \n\t"
7200 "mov %%r9, %c[r9](%0) \n\t"
7201 "mov %%r10, %c[r10](%0) \n\t"
7202 "mov %%r11, %c[r11](%0) \n\t"
7203 "mov %%r12, %c[r12](%0) \n\t"
7204 "mov %%r13, %c[r13](%0) \n\t"
7205 "mov %%r14, %c[r14](%0) \n\t"
7206 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7207#endif
b188c81f
AK		 7208 "mov %%cr2, %%" _ASM_AX " \n\t"
7209 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7210
b188c81f 7211 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7212 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7213 ".pushsection .rodata \n\t"
7214 ".global vmx_return \n\t"
7215 "vmx_return: " _ASM_PTR " 2b \n\t"
7216 ".popsection"
e08aa78a 7217 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7218 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7219 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7220 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7221 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7222 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7223 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7224 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7225 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7226 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7227 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7228#ifdef CONFIG_X86_64
ad312c7c
ZX		 7229 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7230 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7231 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7232 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7233 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7234 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7235 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7236 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7237#endif
40712fae
AK		 7238 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7239 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7240 : "cc", "memory"
7241#ifdef CONFIG_X86_64
b188c81f 7242 , "rax", "rbx", "rdi", "rsi"
c2036300 7243 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7244#else
7245 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7246#endif
7247 );
6aa8b732 7248
2a7921b7
GN		 7249 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7250 if (debugctlmsr)
7251 update_debugctlmsr(debugctlmsr);
7252
aa67f609
AK		 7253#ifndef CONFIG_X86_64
7254 /*
7255 * The sysexit path does not restore ds/es, so we must set them to
7256 * a reasonable value ourselves.
7257 *
7258 * We can't defer this to vmx_load_host_state() since that function
7259 * may be executed in interrupt context, which saves and restore segments
7260 * around it, nullifying its effect.
7261 */
7262 loadsegment(ds, __USER_DS);
7263 loadsegment(es, __USER_DS);
7264#endif
7265
6de4f3ad 7266 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7267 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7268 | (1 << VCPU_EXREG_CPL)
aff48baa 7269 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7270 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7271 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7272 vcpu->arch.regs_dirty = 0;
7273
1155f76a
AK		 7274 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7275
d462b819 7276 vmx->loaded_vmcs->launched = 1;
1b6269db 7277
51aa01d1 7278 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7279 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7280
7281 vmx_complete_atomic_exit(vmx);
7282 vmx_recover_nmi_blocking(vmx);
cf393f75 7283 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7284}
7285
6aa8b732
AK		 7286static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7287{
fb3f0f51
RR		 7288 struct vcpu_vmx *vmx = to_vmx(vcpu);
7289
cdbecfc3 7290 free_vpid(vmx);
ec378aee 7291 free_nested(vmx);
d462b819 7292 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7293 kfree(vmx->guest_msrs);
7294 kvm_vcpu_uninit(vcpu);
a4770347 7295 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7296}
7297
fb3f0f51 7298static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7299{
fb3f0f51 7300 int err;
c16f862d 7301 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7302 int cpu;
6aa8b732 7303
a2fa3e9f 7304 if (!vmx)
fb3f0f51
RR		 7305 return ERR_PTR(-ENOMEM);
7306
2384d2b3
SY		 7307 allocate_vpid(vmx);
7308
fb3f0f51
RR		 7309 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7310 if (err)
7311 goto free_vcpu;
965b58a5 7312
a2fa3e9f 7313 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7314 err = -ENOMEM;
fb3f0f51 7315 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7316 goto uninit_vcpu;
7317 }
965b58a5 7318
d462b819
NHE		 7319 vmx->loaded_vmcs = &vmx->vmcs01;
7320 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7321 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7322 goto free_msrs;
d462b819
NHE		 7323 if (!vmm_exclusive)
7324 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7325 loaded_vmcs_init(vmx->loaded_vmcs);
7326 if (!vmm_exclusive)
7327 kvm_cpu_vmxoff();
a2fa3e9f 7328
15ad7146
AK		 7329 cpu = get_cpu();
7330 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7331 vmx->vcpu.cpu = cpu;
8b9cf98c 7332 err = vmx_vcpu_setup(vmx);
fb3f0f51 7333 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7334 put_cpu();
fb3f0f51
RR		 7335 if (err)
7336 goto free_vmcs;
a63cb560 7337 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7338 err = alloc_apic_access_page(kvm);
7339 if (err)
5e4a0b3c 7340 goto free_vmcs;
a63cb560 7341 }
fb3f0f51 7342
b927a3ce
SY		 7343 if (enable_ept) {
7344 if (!kvm->arch.ept_identity_map_addr)
7345 kvm->arch.ept_identity_map_addr =
7346 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7347 err = -ENOMEM;
b7ebfb05
SY		 7348 if (alloc_identity_pagetable(kvm) != 0)
7349 goto free_vmcs;
93ea5388
GN		 7350 if (!init_rmode_identity_map(kvm))
7351 goto free_vmcs;
b927a3ce 7352 }
b7ebfb05 7353
a9d30f33
NHE		 7354 vmx->nested.current_vmptr = -1ull;
7355 vmx->nested.current_vmcs12 = NULL;
7356
fb3f0f51
RR		 7357 return &vmx->vcpu;
7358
7359free_vmcs:
5f3fbc34 7360 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7361free_msrs:
fb3f0f51
RR		 7362 kfree(vmx->guest_msrs);
7363uninit_vcpu:
7364 kvm_vcpu_uninit(&vmx->vcpu);
7365free_vcpu:
cdbecfc3 7366 free_vpid(vmx);
a4770347 7367 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7368 return ERR_PTR(err);
6aa8b732
AK		 7369}
7370
002c7f7c
YS		 7371static void __init vmx_check_processor_compat(void *rtn)
7372{
7373 struct vmcs_config vmcs_conf;
7374
7375 *(int *)rtn = 0;
7376 if (setup_vmcs_config(&vmcs_conf) < 0)
7377 *(int *)rtn = -EIO;
7378 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7379 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7380 smp_processor_id());
7381 *(int *)rtn = -EIO;
7382 }
7383}
7384
67253af5
SY		 7385static int get_ept_level(void)
7386{
7387 return VMX_EPT_DEFAULT_GAW + 1;
7388}
7389
4b12f0de 7390static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7391{
4b12f0de
SY		 7392 u64 ret;
7393
522c68c4
SY		 7394 /* For VT-d and EPT combination
7395 * 1. MMIO: always map as UC
7396 * 2. EPT with VT-d:
7397 * a. VT-d without snooping control feature: can't guarantee the
7398 * result, try to trust guest.
7399 * b. VT-d with snooping control feature: snooping control feature of
7400 * VT-d engine can guarantee the cache correctness. Just set it
7401 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7402 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7403 * consistent with host MTRR
7404 */
4b12f0de
SY		 7405 if (is_mmio)
7406 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7407 else if (vcpu->kvm->arch.iommu_domain &&
7408 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7409 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7410 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7411 else
522c68c4 7412 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7413 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7414
7415 return ret;
64d4d521
SY		 7416}
7417
17cc3935 7418static int vmx_get_lpage_level(void)
344f414f 7419{
878403b7
SY		 7420 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7421 return PT_DIRECTORY_LEVEL;
7422 else
7423 /* For shadow and EPT supported 1GB page */
7424 return PT_PDPE_LEVEL;
344f414f
JR		 7425}
7426
0e851880
SY		 7427static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7428{
4e47c7a6
SY		 7429 struct kvm_cpuid_entry2 *best;
7430 struct vcpu_vmx *vmx = to_vmx(vcpu);
7431 u32 exec_control;
7432
7433 vmx->rdtscp_enabled = false;
7434 if (vmx_rdtscp_supported()) {
7435 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7436 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7437 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7438 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7439 vmx->rdtscp_enabled = true;
7440 else {
7441 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7442 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7443 exec_control);
7444 }
7445 }
7446 }
ad756a16 7447
ad756a16
MJ		 7448 /* Exposing INVPCID only when PCID is exposed */
7449 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7450 if (vmx_invpcid_supported() &&
4f977045 7451 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7452 guest_cpuid_has_pcid(vcpu)) {
29282fde 7453 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7454 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7455 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7456 exec_control);
7457 } else {
29282fde
TI		 7458 if (cpu_has_secondary_exec_ctrls()) {
7459 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7460 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7461 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7462 exec_control);
7463 }
ad756a16 7464 if (best)
4f977045 7465 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7466 }
0e851880
SY		 7467}
7468
d4330ef2
JR		 7469static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7470{
7b8050f5
NHE		 7471 if (func == 1 && nested)
7472 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7473}
7474
25d92081
YZ		 7475static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7476 struct x86_exception *fault)
7477{
7478 struct vmcs12 *vmcs12;
7479 nested_vmx_vmexit(vcpu);
7480 vmcs12 = get_vmcs12(vcpu);
7481
7482 if (fault->error_code & PFERR_RSVD_MASK)
7483 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7484 else
7485 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7486 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7487 vmcs12->guest_physical_address = fault->address;
7488}
7489
155a97a3
NHE		 7490/* Callbacks for nested_ept_init_mmu_context: */
7491
7492static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7493{
7494 /* return the page table to be shadowed - in our case, EPT12 */
7495 return get_vmcs12(vcpu)->ept_pointer;
7496}
7497
7498static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7499{
7500 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7501 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7502
7503 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7504 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7505 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7506
7507 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7508
7509 return r;
7510}
7511
7512static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7513{
7514 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7515}
7516
fe3ef05c
NHE		 7517/*
7518 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7519 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7520 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7521 * guest in a way that will both be appropriate to L1's requests, and our
7522 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7523 * function also has additional necessary side-effects, like setting various
7524 * vcpu->arch fields.
7525 */
7526static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7527{
7528 struct vcpu_vmx *vmx = to_vmx(vcpu);
7529 u32 exec_control;
7530
7531 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7532 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7533 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7534 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7535 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7536 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7537 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7538 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7539 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7540 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7541 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7542 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7543 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7544 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7545 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7546 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7547 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7548 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7549 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7550 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7551 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7552 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7553 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7554 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7555 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7556 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7557 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7558 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7559 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7560 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7561 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7562 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7563 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7564 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7565 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7566 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7567
7568 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7570 vmcs12->vm_entry_intr_info_field);
7571 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7572 vmcs12->vm_entry_exception_error_code);
7573 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7574 vmcs12->vm_entry_instruction_len);
7575 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7576 vmcs12->guest_interruptibility_info);
fe3ef05c 7577 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7578 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7579 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7580 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7581 vmcs12->guest_pending_dbg_exceptions);
7582 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7583 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7584
7585 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7586
7587 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7588 (vmcs_config.pin_based_exec_ctrl |
7589 vmcs12->pin_based_vm_exec_control));
7590
0238ea91
JK		 7591 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7592 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7593 vmcs12->vmx_preemption_timer_value);
7594
fe3ef05c
NHE		 7595 /*
7596 * Whether page-faults are trapped is determined by a combination of
7597 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7598 * If enable_ept, L0 doesn't care about page faults and we should
7599 * set all of these to L1's desires. However, if !enable_ept, L0 does
7600 * care about (at least some) page faults, and because it is not easy
7601 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7602 * to exit on each and every L2 page fault. This is done by setting
7603 * MASK=MATCH=0 and (see below) EB.PF=1.
7604 * Note that below we don't need special code to set EB.PF beyond the
7605 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7606 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7607 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7608 *
7609 * A problem with this approach (when !enable_ept) is that L1 may be
7610 * injected with more page faults than it asked for. This could have
7611 * caused problems, but in practice existing hypervisors don't care.
7612 * To fix this, we will need to emulate the PFEC checking (on the L1
7613 * page tables), using walk_addr(), when injecting PFs to L1.
7614 */
7615 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7616 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7617 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7618 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7619
7620 if (cpu_has_secondary_exec_ctrls()) {
7621 u32 exec_control = vmx_secondary_exec_control(vmx);
7622 if (!vmx->rdtscp_enabled)
7623 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7624 /* Take the following fields only from vmcs12 */
7625 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7626 if (nested_cpu_has(vmcs12,
7627 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7628 exec_control |= vmcs12->secondary_vm_exec_control;
7629
7630 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7631 /*
7632 * Translate L1 physical address to host physical
7633 * address for vmcs02. Keep the page pinned, so this
7634 * physical address remains valid. We keep a reference
7635 * to it so we can release it later.
7636 */
7637 if (vmx->nested.apic_access_page) /* shouldn't happen */
7638 nested_release_page(vmx->nested.apic_access_page);
7639 vmx->nested.apic_access_page =
7640 nested_get_page(vcpu, vmcs12->apic_access_addr);
7641 /*
7642 * If translation failed, no matter: This feature asks
7643 * to exit when accessing the given address, and if it
7644 * can never be accessed, this feature won't do
7645 * anything anyway.
7646 */
7647 if (!vmx->nested.apic_access_page)
7648 exec_control &=
7649 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7650 else
7651 vmcs_write64(APIC_ACCESS_ADDR,
7652 page_to_phys(vmx->nested.apic_access_page));
7653 }
7654
7655 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7656 }
7657
7658
7659 /*
7660 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7661 * Some constant fields are set here by vmx_set_constant_host_state().
7662 * Other fields are different per CPU, and will be set later when
7663 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7664 */
a547c6db 7665 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7666
7667 /*
7668 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7669 * entry, but only if the current (host) sp changed from the value
7670 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7671 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7672 * here we just force the write to happen on entry.
7673 */
7674 vmx->host_rsp = 0;
7675
7676 exec_control = vmx_exec_control(vmx); /* L0's desires */
7677 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7678 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7679 exec_control &= ~CPU_BASED_TPR_SHADOW;
7680 exec_control |= vmcs12->cpu_based_vm_exec_control;
7681 /*
7682 * Merging of IO and MSR bitmaps not currently supported.
7683 * Rather, exit every time.
7684 */
7685 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7686 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7687 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7688
7689 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7690
7691 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7692 * bitwise-or of what L1 wants to trap for L2, and what we want to
7693 * trap. Note that CR0.TS also needs updating - we do this later.
7694 */
7695 update_exception_bitmap(vcpu);
7696 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7697 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7698
8049d651
NHE		 7699 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7700 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7701 * bits are further modified by vmx_set_efer() below.
7702 */
7703 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7704
7705 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7706 * emulated by vmx_set_efer(), below.
7707 */
7708 vmcs_write32(VM_ENTRY_CONTROLS,
7709 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7710 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7711 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7712
44811c02 7713 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7714 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7715 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7716 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7717 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7718
7719
7720 set_cr4_guest_host_mask(vmx);
7721
27fc51b2
NHE		 7722 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7723 vmcs_write64(TSC_OFFSET,
7724 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7725 else
7726 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7727
7728 if (enable_vpid) {
7729 /*
7730 * Trivially support vpid by letting L2s share their parent
7731 * L1's vpid. TODO: move to a more elaborate solution, giving
7732 * each L2 its own vpid and exposing the vpid feature to L1.
7733 */
7734 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7735 vmx_flush_tlb(vcpu);
7736 }
7737
155a97a3
NHE		 7738 if (nested_cpu_has_ept(vmcs12)) {
7739 kvm_mmu_unload(vcpu);
7740 nested_ept_init_mmu_context(vcpu);
7741 }
7742
fe3ef05c
NHE		 7743 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7744 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7745 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7746 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7747 else
7748 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7749 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7750 vmx_set_efer(vcpu, vcpu->arch.efer);
7751
7752 /*
7753 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7754 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7755 * The CR0_READ_SHADOW is what L2 should have expected to read given
7756 * the specifications by L1; It's not enough to take
7757 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7758 * have more bits than L1 expected.
7759 */
7760 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7761 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7762
7763 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7764 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7765
7766 /* shadow page tables on either EPT or shadow page tables */
7767 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7768 kvm_mmu_reset_context(vcpu);
7769
3633cfc3
NHE		 7770 /*
7771 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7772 */
7773 if (enable_ept) {
7774 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7775 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7776 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7777 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
72f85795
GN		 7778 __clear_bit(VCPU_EXREG_PDPTR,
7779 (unsigned long *)&vcpu->arch.regs_avail);
7780 __clear_bit(VCPU_EXREG_PDPTR,
7781 (unsigned long *)&vcpu->arch.regs_dirty);
3633cfc3
NHE		 7782 }
7783
fe3ef05c
NHE		 7784 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7785 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7786}
7787
cd232ad0
NHE		 7788/*
7789 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7790 * for running an L2 nested guest.
7791 */
7792static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7793{
7794 struct vmcs12 *vmcs12;
7795 struct vcpu_vmx *vmx = to_vmx(vcpu);
7796 int cpu;
7797 struct loaded_vmcs *vmcs02;
384bb783 7798 bool ia32e;
cd232ad0
NHE		 7799
7800 if (!nested_vmx_check_permission(vcpu) ||
7801 !nested_vmx_check_vmcs12(vcpu))
7802 return 1;
7803
7804 skip_emulated_instruction(vcpu);
7805 vmcs12 = get_vmcs12(vcpu);
7806
012f83cb
AG		 7807 if (enable_shadow_vmcs)
7808 copy_shadow_to_vmcs12(vmx);
7809
7c177938
NHE		 7810 /*
7811 * The nested entry process starts with enforcing various prerequisites
7812 * on vmcs12 as required by the Intel SDM, and act appropriately when
7813 * they fail: As the SDM explains, some conditions should cause the
7814 * instruction to fail, while others will cause the instruction to seem
7815 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7816 * To speed up the normal (success) code path, we should avoid checking
7817 * for misconfigurations which will anyway be caught by the processor
7818 * when using the merged vmcs02.
7819 */
7820 if (vmcs12->launch_state == launch) {
7821 nested_vmx_failValid(vcpu,
7822 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7823 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7824 return 1;
7825 }
7826
26539bd0
PB		 7827 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7828 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7829 return 1;
7830 }
7831
7c177938
NHE		 7832 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7833 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7834 /*TODO: Also verify bits beyond physical address width are 0*/
7835 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7836 return 1;
7837 }
7838
7839 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7840 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7841 /*TODO: Also verify bits beyond physical address width are 0*/
7842 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7843 return 1;
7844 }
7845
7846 if (vmcs12->vm_entry_msr_load_count > 0 ||
7847 vmcs12->vm_exit_msr_load_count > 0 ||
7848 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7849 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7850 __func__);
7c177938
NHE		 7851 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7852 return 1;
7853 }
7854
7855 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7856 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7857 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7858 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7859 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7860 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7861 !vmx_control_verify(vmcs12->vm_exit_controls,
7862 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7863 !vmx_control_verify(vmcs12->vm_entry_controls,
7864 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7865 {
7866 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7867 return 1;
7868 }
7869
7870 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7871 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7872 nested_vmx_failValid(vcpu,
7873 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7874 return 1;
7875 }
7876
7877 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7878 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7879 nested_vmx_entry_failure(vcpu, vmcs12,
7880 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7881 return 1;
7882 }
7883 if (vmcs12->vmcs_link_pointer != -1ull) {
7884 nested_vmx_entry_failure(vcpu, vmcs12,
7885 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7886 return 1;
7887 }
7888
384bb783 7889 /*
cb0c8cda 7890 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7891 * are performed on the field for the IA32_EFER MSR:
7892 * - Bits reserved in the IA32_EFER MSR must be 0.
7893 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7894 * the IA-32e mode guest VM-exit control. It must also be identical
7895 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7896 * CR0.PG) is 1.
7897 */
7898 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7899 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7900 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7901 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7902 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7903 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7904 nested_vmx_entry_failure(vcpu, vmcs12,
7905 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7906 return 1;
7907 }
7908 }
7909
7910 /*
7911 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7912 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7913 * the values of the LMA and LME bits in the field must each be that of
7914 * the host address-space size VM-exit control.
7915 */
7916 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7917 ia32e = (vmcs12->vm_exit_controls &
7918 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7919 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7920 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7921 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7922 nested_vmx_entry_failure(vcpu, vmcs12,
7923 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7924 return 1;
7925 }
7926 }
7927
7c177938
NHE		 7928 /*
7929 * We're finally done with prerequisite checking, and can start with
7930 * the nested entry.
7931 */
7932
cd232ad0
NHE		 7933 vmcs02 = nested_get_current_vmcs02(vmx);
7934 if (!vmcs02)
7935 return -ENOMEM;
7936
7937 enter_guest_mode(vcpu);
7938
7939 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7940
7941 cpu = get_cpu();
7942 vmx->loaded_vmcs = vmcs02;
7943 vmx_vcpu_put(vcpu);
7944 vmx_vcpu_load(vcpu, cpu);
7945 vcpu->cpu = cpu;
7946 put_cpu();
7947
36c3cc42
JK		 7948 vmx_segment_cache_clear(vmx);
7949
cd232ad0
NHE		 7950 vmcs12->launch_state = 1;
7951
7952 prepare_vmcs02(vcpu, vmcs12);
7953
7954 /*
7955 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7956 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7957 * returned as far as L1 is concerned. It will only return (and set
7958 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7959 */
7960 return 1;
7961}
7962
4704d0be
NHE		 7963/*
7964 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7965 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7966 * This function returns the new value we should put in vmcs12.guest_cr0.
7967 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7968 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7969 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7970 * didn't trap the bit, because if L1 did, so would L0).
7971 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7972 * been modified by L2, and L1 knows it. So just leave the old value of
7973 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7974 * isn't relevant, because if L0 traps this bit it can set it to anything.
7975 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7976 * changed these bits, and therefore they need to be updated, but L0
7977 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7978 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7979 */
7980static inline unsigned long
7981vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7982{
7983 return
7984 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7985 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7986 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7987 vcpu->arch.cr0_guest_owned_bits));
7988}
7989
7990static inline unsigned long
7991vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7992{
7993 return
7994 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7995 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7996 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7997 vcpu->arch.cr4_guest_owned_bits));
7998}
7999
5f3d5799
JK		 8000static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8001 struct vmcs12 *vmcs12)
8002{
8003 u32 idt_vectoring;
8004 unsigned int nr;
8005
8006 if (vcpu->arch.exception.pending) {
8007 nr = vcpu->arch.exception.nr;
8008 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8009
8010 if (kvm_exception_is_soft(nr)) {
8011 vmcs12->vm_exit_instruction_len =
8012 vcpu->arch.event_exit_inst_len;
8013 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8014 } else
8015 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8016
8017 if (vcpu->arch.exception.has_error_code) {
8018 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8019 vmcs12->idt_vectoring_error_code =
8020 vcpu->arch.exception.error_code;
8021 }
8022
8023 vmcs12->idt_vectoring_info_field = idt_vectoring;
8024 } else if (vcpu->arch.nmi_pending) {
8025 vmcs12->idt_vectoring_info_field =
8026 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8027 } else if (vcpu->arch.interrupt.pending) {
8028 nr = vcpu->arch.interrupt.nr;
8029 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8030
8031 if (vcpu->arch.interrupt.soft) {
8032 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8033 vmcs12->vm_entry_instruction_len =
8034 vcpu->arch.event_exit_inst_len;
8035 } else
8036 idt_vectoring |= INTR_TYPE_EXT_INTR;
8037
8038 vmcs12->idt_vectoring_info_field = idt_vectoring;
8039 }
8040}
8041
4704d0be
NHE		 8042/*
8043 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8044 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8045 * and this function updates it to reflect the changes to the guest state while
8046 * L2 was running (and perhaps made some exits which were handled directly by L0
8047 * without going back to L1), and to reflect the exit reason.
8048 * Note that we do not have to copy here all VMCS fields, just those that
8049 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8050 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8051 * which already writes to vmcs12 directly.
8052 */
733568f9 8053static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8054{
8055 /* update guest state fields: */
8056 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8057 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8058
8059 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8060 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8061 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8062 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8063
8064 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8065 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8066 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8067 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8068 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8069 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8070 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8071 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8072 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8073 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8074 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8075 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8076 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8077 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8078 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8079 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8080 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8081 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8082 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8083 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8084 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8085 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8086 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8087 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8088 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8089 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8090 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8091 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8092 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8093 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8094 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8095 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8096 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8097 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8098 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8099 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8100
4704d0be
NHE		 8101 vmcs12->guest_interruptibility_info =
8102 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8103 vmcs12->guest_pending_dbg_exceptions =
8104 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8105
3633cfc3
NHE		 8106 /*
8107 * In some cases (usually, nested EPT), L2 is allowed to change its
8108 * own CR3 without exiting. If it has changed it, we must keep it.
8109 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8110 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8111 *
8112 * Additionally, restore L2's PDPTR to vmcs12.
8113 */
8114 if (enable_ept) {
8115 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8116 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8117 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8118 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8119 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8120 }
8121
c18911a2
JK		 8122 vmcs12->vm_entry_controls =
8123 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8124 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8125
4704d0be
NHE		 8126 /* TODO: These cannot have changed unless we have MSR bitmaps and
8127 * the relevant bit asks not to trap the change */
8128 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8129 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 8130 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8131 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8132 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8133 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8134
8135 /* update exit information fields: */
8136
957c897e 8137 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8138 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8139
8140 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8141 if ((vmcs12->vm_exit_intr_info &
8142 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8143 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8144 vmcs12->vm_exit_intr_error_code =
8145 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8146 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8147 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8148 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8149
5f3d5799
JK		 8150 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8151 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8152 * instead of reading the real value. */
4704d0be 8153 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8154
8155 /*
8156 * Transfer the event that L0 or L1 may wanted to inject into
8157 * L2 to IDT_VECTORING_INFO_FIELD.
8158 */
8159 vmcs12_save_pending_event(vcpu, vmcs12);
8160 }
8161
8162 /*
8163 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8164 * preserved above and would only end up incorrectly in L1.
8165 */
8166 vcpu->arch.nmi_injected = false;
8167 kvm_clear_exception_queue(vcpu);
8168 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8169}
8170
8171/*
8172 * A part of what we need to when the nested L2 guest exits and we want to
8173 * run its L1 parent, is to reset L1's guest state to the host state specified
8174 * in vmcs12.
8175 * This function is to be called not only on normal nested exit, but also on
8176 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8177 * Failures During or After Loading Guest State").
8178 * This function should be called when the active VMCS is L1's (vmcs01).
8179 */
733568f9
JK		 8180static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8181 struct vmcs12 *vmcs12)
4704d0be 8182{
21feb4eb
ACL		 8183 struct kvm_segment seg;
8184
4704d0be
NHE		 8185 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8186 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8187 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8188 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8189 else
8190 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8191 vmx_set_efer(vcpu, vcpu->arch.efer);
8192
8193 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8194 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8195 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8196 /*
8197 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8198 * actually changed, because it depends on the current state of
8199 * fpu_active (which may have changed).
8200 * Note that vmx_set_cr0 refers to efer set above.
8201 */
9e3e4dbf 8202 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8203 /*
8204 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8205 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8206 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8207 */
8208 update_exception_bitmap(vcpu);
8209 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8210 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8211
8212 /*
8213 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8214 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8215 */
8216 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8217 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8218
155a97a3
NHE		 8219 if (nested_cpu_has_ept(vmcs12))
8220 nested_ept_uninit_mmu_context(vcpu);
8221
4704d0be
NHE		 8222 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8223 kvm_mmu_reset_context(vcpu);
8224
8225 if (enable_vpid) {
8226 /*
8227 * Trivially support vpid by letting L2s share their parent
8228 * L1's vpid. TODO: move to a more elaborate solution, giving
8229 * each L2 its own vpid and exposing the vpid feature to L1.
8230 */
8231 vmx_flush_tlb(vcpu);
8232 }
8233
8234
8235 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8236 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8237 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8238 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8239 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8240
44811c02 8241 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8242 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8243 vcpu->arch.pat = vmcs12->host_ia32_pat;
8244 }
4704d0be
NHE		 8245 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8246 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8247 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8248
21feb4eb
ACL		 8249 /* Set L1 segment info according to Intel SDM
8250 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8251 seg = (struct kvm_segment) {
8252 .base = 0,
8253 .limit = 0xFFFFFFFF,
8254 .selector = vmcs12->host_cs_selector,
8255 .type = 11,
8256 .present = 1,
8257 .s = 1,
8258 .g = 1
8259 };
8260 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8261 seg.l = 1;
8262 else
8263 seg.db = 1;
8264 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8265 seg = (struct kvm_segment) {
8266 .base = 0,
8267 .limit = 0xFFFFFFFF,
8268 .type = 3,
8269 .present = 1,
8270 .s = 1,
8271 .db = 1,
8272 .g = 1
8273 };
8274 seg.selector = vmcs12->host_ds_selector;
8275 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8276 seg.selector = vmcs12->host_es_selector;
8277 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8278 seg.selector = vmcs12->host_ss_selector;
8279 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8280 seg.selector = vmcs12->host_fs_selector;
8281 seg.base = vmcs12->host_fs_base;
8282 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8283 seg.selector = vmcs12->host_gs_selector;
8284 seg.base = vmcs12->host_gs_base;
8285 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8286 seg = (struct kvm_segment) {
205befd9 8287 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8288 .limit = 0x67,
8289 .selector = vmcs12->host_tr_selector,
8290 .type = 11,
8291 .present = 1
8292 };
8293 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8294
503cd0c5
JK		 8295 kvm_set_dr(vcpu, 7, 0x400);
8296 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8297}
8298
8299/*
8300 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8301 * and modify vmcs12 to make it see what it would expect to see there if
8302 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8303 */
8304static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8305{
8306 struct vcpu_vmx *vmx = to_vmx(vcpu);
8307 int cpu;
8308 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8309
5f3d5799
JK		 8310 /* trying to cancel vmlaunch/vmresume is a bug */
8311 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8312
4704d0be
NHE		 8313 leave_guest_mode(vcpu);
8314 prepare_vmcs12(vcpu, vmcs12);
8315
8316 cpu = get_cpu();
8317 vmx->loaded_vmcs = &vmx->vmcs01;
8318 vmx_vcpu_put(vcpu);
8319 vmx_vcpu_load(vcpu, cpu);
8320 vcpu->cpu = cpu;
8321 put_cpu();
8322
36c3cc42
JK		 8323 vmx_segment_cache_clear(vmx);
8324
4704d0be
NHE		 8325 /* if no vmcs02 cache requested, remove the one we used */
8326 if (VMCS02_POOL_SIZE == 0)
8327 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8328
8329 load_vmcs12_host_state(vcpu, vmcs12);
8330
27fc51b2 8331 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8332 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8333
8334 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8335 vmx->host_rsp = 0;
8336
8337 /* Unpin physical memory we referred to in vmcs02 */
8338 if (vmx->nested.apic_access_page) {
8339 nested_release_page(vmx->nested.apic_access_page);
8340 vmx->nested.apic_access_page = 0;
8341 }
8342
8343 /*
8344 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8345 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8346 * success or failure flag accordingly.
8347 */
8348 if (unlikely(vmx->fail)) {
8349 vmx->fail = 0;
8350 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8351 } else
8352 nested_vmx_succeed(vcpu);
012f83cb
AG		 8353 if (enable_shadow_vmcs)
8354 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8355}
8356
7c177938
NHE		 8357/*
8358 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8359 * 23.7 "VM-entry failures during or after loading guest state" (this also
8360 * lists the acceptable exit-reason and exit-qualification parameters).
8361 * It should only be called before L2 actually succeeded to run, and when
8362 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8363 */
8364static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8365 struct vmcs12 *vmcs12,
8366 u32 reason, unsigned long qualification)
8367{
8368 load_vmcs12_host_state(vcpu, vmcs12);
8369 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8370 vmcs12->exit_qualification = qualification;
8371 nested_vmx_succeed(vcpu);
012f83cb
AG		 8372 if (enable_shadow_vmcs)
8373 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8374}
8375
8a76d7f2
JR		 8376static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8377 struct x86_instruction_info *info,
8378 enum x86_intercept_stage stage)
8379{
8380 return X86EMUL_CONTINUE;
8381}
8382
cbdd1bea 8383static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8384 .cpu_has_kvm_support = cpu_has_kvm_support,
8385 .disabled_by_bios = vmx_disabled_by_bios,
8386 .hardware_setup = hardware_setup,
8387 .hardware_unsetup = hardware_unsetup,
002c7f7c 8388 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8389 .hardware_enable = hardware_enable,
8390 .hardware_disable = hardware_disable,
04547156 8391 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8392
8393 .vcpu_create = vmx_create_vcpu,
8394 .vcpu_free = vmx_free_vcpu,
04d2cc77 8395 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8396
04d2cc77 8397 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8398 .vcpu_load = vmx_vcpu_load,
8399 .vcpu_put = vmx_vcpu_put,
8400
c8639010 8401 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8402 .get_msr = vmx_get_msr,
8403 .set_msr = vmx_set_msr,
8404 .get_segment_base = vmx_get_segment_base,
8405 .get_segment = vmx_get_segment,
8406 .set_segment = vmx_set_segment,
2e4d2653 8407 .get_cpl = vmx_get_cpl,
6aa8b732 8408 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8409 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8410 .decache_cr3 = vmx_decache_cr3,
25c4c276 8411 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8412 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8413 .set_cr3 = vmx_set_cr3,
8414 .set_cr4 = vmx_set_cr4,
6aa8b732 8415 .set_efer = vmx_set_efer,
6aa8b732
AK		 8416 .get_idt = vmx_get_idt,
8417 .set_idt = vmx_set_idt,
8418 .get_gdt = vmx_get_gdt,
8419 .set_gdt = vmx_set_gdt,
020df079 8420 .set_dr7 = vmx_set_dr7,
5fdbf976 8421 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8422 .get_rflags = vmx_get_rflags,
8423 .set_rflags = vmx_set_rflags,
ebcbab4c 8424 .fpu_activate = vmx_fpu_activate,
02daab21 8425 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8426
8427 .tlb_flush = vmx_flush_tlb,
6aa8b732 8428
6aa8b732 8429 .run = vmx_vcpu_run,
6062d012 8430 .handle_exit = vmx_handle_exit,
6aa8b732 8431 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8432 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8433 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8434 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8435 .set_irq = vmx_inject_irq,
95ba8273 8436 .set_nmi = vmx_inject_nmi,
298101da 8437 .queue_exception = vmx_queue_exception,
b463a6f7 8438 .cancel_injection = vmx_cancel_injection,
78646121 8439 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8440 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8441 .get_nmi_mask = vmx_get_nmi_mask,
8442 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8443 .enable_nmi_window = enable_nmi_window,
8444 .enable_irq_window = enable_irq_window,
8445 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8446 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8447 .vm_has_apicv = vmx_vm_has_apicv,
8448 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8449 .hwapic_irr_update = vmx_hwapic_irr_update,
8450 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8451 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8452 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8453
cbc94022 8454 .set_tss_addr = vmx_set_tss_addr,
67253af5 8455 .get_tdp_level = get_ept_level,
4b12f0de 8456 .get_mt_mask = vmx_get_mt_mask,
229456fc 8457
586f9607 8458 .get_exit_info = vmx_get_exit_info,
586f9607 8459
17cc3935 8460 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8461
8462 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8463
8464 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8465 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8466
8467 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8468
8469 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8470
4051b188 8471 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8472 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8473 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8474 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8475 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8476 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8477
8478 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8479
8480 .check_intercept = vmx_check_intercept,
a547c6db 8481 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8482};
8483
8484static int __init vmx_init(void)
8485{
8d14695f 8486 int r, i, msr;
26bb0981
AK		 8487
8488 rdmsrl_safe(MSR_EFER, &host_efer);
8489
8490 for (i = 0; i < NR_VMX_MSR; ++i)
8491 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8492
3e7c73e9 8493 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8494 if (!vmx_io_bitmap_a)
8495 return -ENOMEM;
8496
2106a548
GC		 8497 r = -ENOMEM;
8498
3e7c73e9 8499 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8500 if (!vmx_io_bitmap_b)
fdef3ad1 8501 goto out;
fdef3ad1 8502
5897297b 8503 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8504 if (!vmx_msr_bitmap_legacy)
25c5f225 8505 goto out1;
2106a548 8506
8d14695f
YZ		 8507 vmx_msr_bitmap_legacy_x2apic =
8508 (unsigned long *)__get_free_page(GFP_KERNEL);
8509 if (!vmx_msr_bitmap_legacy_x2apic)
8510 goto out2;
25c5f225 8511
5897297b 8512 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8513 if (!vmx_msr_bitmap_longmode)
8d14695f 8514 goto out3;
2106a548 8515
8d14695f
YZ		 8516 vmx_msr_bitmap_longmode_x2apic =
8517 (unsigned long *)__get_free_page(GFP_KERNEL);
8518 if (!vmx_msr_bitmap_longmode_x2apic)
8519 goto out4;
4607c2d7
AG		 8520 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8521 if (!vmx_vmread_bitmap)
8522 goto out5;
8523
8524 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8525 if (!vmx_vmwrite_bitmap)
8526 goto out6;
8527
8528 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8529 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8530 /* shadowed read/write fields */
8531 for (i = 0; i < max_shadow_read_write_fields; i++) {
8532 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8533 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8534 }
8535 /* shadowed read only fields */
8536 for (i = 0; i < max_shadow_read_only_fields; i++)
8537 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8538
fdef3ad1
HQ		 8539 /*
8540 * Allow direct access to the PC debug port (it is often used for I/O
8541 * delays, but the vmexits simply slow things down).
8542 */
3e7c73e9
AK		 8543 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8544 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8545
3e7c73e9 8546 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8547
5897297b
AK		 8548 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8549 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8550
2384d2b3
SY		 8551 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8552
0ee75bea
AK		 8553 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8554 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8555 if (r)
4607c2d7 8556 goto out7;
25c5f225 8557
8f536b76
ZY		 8558#ifdef CONFIG_KEXEC
8559 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8560 crash_vmclear_local_loaded_vmcss);
8561#endif
8562
5897297b
AK		 8563 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8564 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8565 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8566 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8567 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8568 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8569 memcpy(vmx_msr_bitmap_legacy_x2apic,
8570 vmx_msr_bitmap_legacy, PAGE_SIZE);
8571 memcpy(vmx_msr_bitmap_longmode_x2apic,
8572 vmx_msr_bitmap_longmode, PAGE_SIZE);
8573
01e439be 8574 if (enable_apicv) {
8d14695f
YZ		 8575 for (msr = 0x800; msr <= 0x8ff; msr++)
8576 vmx_disable_intercept_msr_read_x2apic(msr);
8577
8578 /* According SDM, in x2apic mode, the whole id reg is used.
8579 * But in KVM, it only use the highest eight bits. Need to
8580 * intercept it */
8581 vmx_enable_intercept_msr_read_x2apic(0x802);
8582 /* TMCCT */
8583 vmx_enable_intercept_msr_read_x2apic(0x839);
8584 /* TPR */
8585 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8586 /* EOI */
8587 vmx_disable_intercept_msr_write_x2apic(0x80b);
8588 /* SELF-IPI */
8589 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8590 }
fdef3ad1 8591
089d034e 8592 if (enable_ept) {
3f6d8c8a
XH		 8593 kvm_mmu_set_mask_ptes(0ull,
8594 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8595 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8596 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8597 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8598 kvm_enable_tdp();
8599 } else
8600 kvm_disable_tdp();
1439442c 8601
fdef3ad1
HQ		 8602 return 0;
8603
4607c2d7
AG		 8604out7:
8605 free_page((unsigned long)vmx_vmwrite_bitmap);
8606out6:
8607 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8608out5:
8609 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8610out4:
5897297b 8611 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8612out3:
8613 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8614out2:
5897297b 8615 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8616out1:
3e7c73e9 8617 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8618out:
3e7c73e9 8619 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8620 return r;
6aa8b732
AK		 8621}
8622
8623static void __exit vmx_exit(void)
8624{
8d14695f
YZ		 8625 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8626 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8627 free_page((unsigned long)vmx_msr_bitmap_legacy);
8628 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8629 free_page((unsigned long)vmx_io_bitmap_b);
8630 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8631 free_page((unsigned long)vmx_vmwrite_bitmap);
8632 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8633
8f536b76
ZY		 8634#ifdef CONFIG_KEXEC
8635 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8636 synchronize_rcu();
8637#endif
8638
cb498ea2 8639 kvm_exit();
6aa8b732
AK		 8640}
8641
8642module_init(vmx_init)
8643module_exit(vmx_exit)
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