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KVM: nVMX: Set success rflags when emulate VMXON/VMXOFF in nested virt
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
ec378aee
NHE		 376};
377
01e439be
YZ		 378#define POSTED_INTR_ON 0
379/* Posted-Interrupt Descriptor */
380struct pi_desc {
381 u32 pir[8]; /* Posted interrupt requested */
382 u32 control; /* bit 0 of control is outstanding notification bit */
383 u32 rsvd[7];
384} __aligned(64);
385
a20ed54d
YZ		 386static bool pi_test_and_set_on(struct pi_desc *pi_desc)
387{
388 return test_and_set_bit(POSTED_INTR_ON,
389 (unsigned long *)&pi_desc->control);
390}
391
392static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
393{
394 return test_and_clear_bit(POSTED_INTR_ON,
395 (unsigned long *)&pi_desc->control);
396}
397
398static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
399{
400 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
401}
402
a2fa3e9f 403struct vcpu_vmx {
fb3f0f51 404 struct kvm_vcpu vcpu;
313dbd49 405 unsigned long host_rsp;
29bd8a78 406 u8 fail;
69c73028 407 u8 cpl;
9d58b931 408 bool nmi_known_unmasked;
51aa01d1 409 u32 exit_intr_info;
1155f76a 410 u32 idt_vectoring_info;
6de12732 411 ulong rflags;
26bb0981 412 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 413 int nmsrs;
414 int save_nmsrs;
a547c6db 415 unsigned long host_idt_base;
a2fa3e9f 416#ifdef CONFIG_X86_64
44ea2b17
AK		 417 u64 msr_host_kernel_gs_base;
418 u64 msr_guest_kernel_gs_base;
a2fa3e9f 419#endif
d462b819
NHE		 420 /*
421 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
422 * non-nested (L1) guest, it always points to vmcs01. For a nested
423 * guest (L2), it points to a different VMCS.
424 */
425 struct loaded_vmcs vmcs01;
426 struct loaded_vmcs *loaded_vmcs;
427 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 428 struct msr_autoload {
429 unsigned nr;
430 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
431 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
432 } msr_autoload;
a2fa3e9f
GH		 433 struct {
434 int loaded;
435 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 436#ifdef CONFIG_X86_64
437 u16 ds_sel, es_sel;
438#endif
152d3f2f
LV		 439 int gs_ldt_reload_needed;
440 int fs_reload_needed;
d77c26fc 441 } host_state;
9c8cba37 442 struct {
7ffd92c5 443 int vm86_active;
78ac8b47 444 ulong save_rflags;
f5f7b2fe
AK		 445 struct kvm_segment segs[8];
446 } rmode;
447 struct {
448 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 449 struct kvm_save_segment {
450 u16 selector;
451 unsigned long base;
452 u32 limit;
453 u32 ar;
f5f7b2fe 454 } seg[8];
2fb92db1 455 } segment_cache;
2384d2b3 456 int vpid;
04fa4d32 457 bool emulation_required;
3b86cd99
JK		 458
459 /* Support for vnmi-less CPUs */
460 int soft_vnmi_blocked;
461 ktime_t entry_time;
462 s64 vnmi_blocked_time;
a0861c02 463 u32 exit_reason;
4e47c7a6
SY		 464
465 bool rdtscp_enabled;
ec378aee 466
01e439be
YZ		 467 /* Posted interrupt descriptor */
468 struct pi_desc pi_desc;
469
ec378aee
NHE		 470 /* Support for a guest hypervisor (nested VMX) */
471 struct nested_vmx nested;
a2fa3e9f
GH		 472};
473
2fb92db1
AK		 474enum segment_cache_field {
475 SEG_FIELD_SEL = 0,
476 SEG_FIELD_BASE = 1,
477 SEG_FIELD_LIMIT = 2,
478 SEG_FIELD_AR = 3,
479
480 SEG_FIELD_NR = 4
481};
482
a2fa3e9f
GH		 483static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
484{
fb3f0f51 485 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 486}
487
22bd0358
NHE		 488#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
489#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
490#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
491 [number##_HIGH] = VMCS12_OFFSET(name)+4
492
4607c2d7
AG		 493
494static const unsigned long shadow_read_only_fields[] = {
495 /*
496 * We do NOT shadow fields that are modified when L0
497 * traps and emulates any vmx instruction (e.g. VMPTRLD,
498 * VMXON...) executed by L1.
499 * For example, VM_INSTRUCTION_ERROR is read
500 * by L1 if a vmx instruction fails (part of the error path).
501 * Note the code assumes this logic. If for some reason
502 * we start shadowing these fields then we need to
503 * force a shadow sync when L0 emulates vmx instructions
504 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
505 * by nested_vmx_failValid)
506 */
507 VM_EXIT_REASON,
508 VM_EXIT_INTR_INFO,
509 VM_EXIT_INSTRUCTION_LEN,
510 IDT_VECTORING_INFO_FIELD,
511 IDT_VECTORING_ERROR_CODE,
512 VM_EXIT_INTR_ERROR_CODE,
513 EXIT_QUALIFICATION,
514 GUEST_LINEAR_ADDRESS,
515 GUEST_PHYSICAL_ADDRESS
516};
517static const int max_shadow_read_only_fields =
518 ARRAY_SIZE(shadow_read_only_fields);
519
520static const unsigned long shadow_read_write_fields[] = {
521 GUEST_RIP,
522 GUEST_RSP,
523 GUEST_CR0,
524 GUEST_CR3,
525 GUEST_CR4,
526 GUEST_INTERRUPTIBILITY_INFO,
527 GUEST_RFLAGS,
528 GUEST_CS_SELECTOR,
529 GUEST_CS_AR_BYTES,
530 GUEST_CS_LIMIT,
531 GUEST_CS_BASE,
532 GUEST_ES_BASE,
533 CR0_GUEST_HOST_MASK,
534 CR0_READ_SHADOW,
535 CR4_READ_SHADOW,
536 TSC_OFFSET,
537 EXCEPTION_BITMAP,
538 CPU_BASED_VM_EXEC_CONTROL,
539 VM_ENTRY_EXCEPTION_ERROR_CODE,
540 VM_ENTRY_INTR_INFO_FIELD,
541 VM_ENTRY_INSTRUCTION_LEN,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 HOST_FS_BASE,
544 HOST_GS_BASE,
545 HOST_FS_SELECTOR,
546 HOST_GS_SELECTOR
547};
548static const int max_shadow_read_write_fields =
549 ARRAY_SIZE(shadow_read_write_fields);
550
772e0318 551static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 552 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
553 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
554 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
555 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
556 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
557 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
558 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
559 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
560 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
561 FIELD(HOST_ES_SELECTOR, host_es_selector),
562 FIELD(HOST_CS_SELECTOR, host_cs_selector),
563 FIELD(HOST_SS_SELECTOR, host_ss_selector),
564 FIELD(HOST_DS_SELECTOR, host_ds_selector),
565 FIELD(HOST_FS_SELECTOR, host_fs_selector),
566 FIELD(HOST_GS_SELECTOR, host_gs_selector),
567 FIELD(HOST_TR_SELECTOR, host_tr_selector),
568 FIELD64(IO_BITMAP_A, io_bitmap_a),
569 FIELD64(IO_BITMAP_B, io_bitmap_b),
570 FIELD64(MSR_BITMAP, msr_bitmap),
571 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
572 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
573 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
574 FIELD64(TSC_OFFSET, tsc_offset),
575 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
576 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
577 FIELD64(EPT_POINTER, ept_pointer),
578 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
579 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
580 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
581 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
582 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
583 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
584 FIELD64(GUEST_PDPTR0, guest_pdptr0),
585 FIELD64(GUEST_PDPTR1, guest_pdptr1),
586 FIELD64(GUEST_PDPTR2, guest_pdptr2),
587 FIELD64(GUEST_PDPTR3, guest_pdptr3),
588 FIELD64(HOST_IA32_PAT, host_ia32_pat),
589 FIELD64(HOST_IA32_EFER, host_ia32_efer),
590 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
591 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
592 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
593 FIELD(EXCEPTION_BITMAP, exception_bitmap),
594 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
595 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
596 FIELD(CR3_TARGET_COUNT, cr3_target_count),
597 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
598 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
599 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
600 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
601 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
602 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
603 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
604 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
605 FIELD(TPR_THRESHOLD, tpr_threshold),
606 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
607 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
608 FIELD(VM_EXIT_REASON, vm_exit_reason),
609 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
610 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
611 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
612 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
613 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
614 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
615 FIELD(GUEST_ES_LIMIT, guest_es_limit),
616 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
617 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
618 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
619 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
620 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
621 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
622 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
623 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
624 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
625 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
626 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
627 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
628 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
629 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
630 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
631 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
632 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
633 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
634 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
635 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
636 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 637 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 638 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
639 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
640 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
641 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
642 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
643 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
644 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
645 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
646 FIELD(EXIT_QUALIFICATION, exit_qualification),
647 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
648 FIELD(GUEST_CR0, guest_cr0),
649 FIELD(GUEST_CR3, guest_cr3),
650 FIELD(GUEST_CR4, guest_cr4),
651 FIELD(GUEST_ES_BASE, guest_es_base),
652 FIELD(GUEST_CS_BASE, guest_cs_base),
653 FIELD(GUEST_SS_BASE, guest_ss_base),
654 FIELD(GUEST_DS_BASE, guest_ds_base),
655 FIELD(GUEST_FS_BASE, guest_fs_base),
656 FIELD(GUEST_GS_BASE, guest_gs_base),
657 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
658 FIELD(GUEST_TR_BASE, guest_tr_base),
659 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
660 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
661 FIELD(GUEST_DR7, guest_dr7),
662 FIELD(GUEST_RSP, guest_rsp),
663 FIELD(GUEST_RIP, guest_rip),
664 FIELD(GUEST_RFLAGS, guest_rflags),
665 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
666 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
667 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
668 FIELD(HOST_CR0, host_cr0),
669 FIELD(HOST_CR3, host_cr3),
670 FIELD(HOST_CR4, host_cr4),
671 FIELD(HOST_FS_BASE, host_fs_base),
672 FIELD(HOST_GS_BASE, host_gs_base),
673 FIELD(HOST_TR_BASE, host_tr_base),
674 FIELD(HOST_GDTR_BASE, host_gdtr_base),
675 FIELD(HOST_IDTR_BASE, host_idtr_base),
676 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
677 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
678 FIELD(HOST_RSP, host_rsp),
679 FIELD(HOST_RIP, host_rip),
680};
681static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
682
683static inline short vmcs_field_to_offset(unsigned long field)
684{
685 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
686 return -1;
687 return vmcs_field_to_offset_table[field];
688}
689
a9d30f33
NHE		 690static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
691{
692 return to_vmx(vcpu)->nested.current_vmcs12;
693}
694
695static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
696{
697 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 698 if (is_error_page(page))
a9d30f33 699 return NULL;
32cad84f 700
a9d30f33
NHE		 701 return page;
702}
703
704static void nested_release_page(struct page *page)
705{
706 kvm_release_page_dirty(page);
707}
708
709static void nested_release_page_clean(struct page *page)
710{
711 kvm_release_page_clean(page);
712}
713
4e1096d2 714static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 715static void kvm_cpu_vmxon(u64 addr);
716static void kvm_cpu_vmxoff(void);
aff48baa 717static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 718static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 719static void vmx_set_segment(struct kvm_vcpu *vcpu,
720 struct kvm_segment *var, int seg);
721static void vmx_get_segment(struct kvm_vcpu *vcpu,
722 struct kvm_segment *var, int seg);
d99e4152
GN		 723static bool guest_state_valid(struct kvm_vcpu *vcpu);
724static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 725static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 726static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 727static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 728
6aa8b732
AK		 729static DEFINE_PER_CPU(struct vmcs *, vmxarea);
730static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 731/*
732 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
733 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
734 */
735static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 736static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 737
3e7c73e9
AK		 738static unsigned long *vmx_io_bitmap_a;
739static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 740static unsigned long *vmx_msr_bitmap_legacy;
741static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 742static unsigned long *vmx_msr_bitmap_legacy_x2apic;
743static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 744static unsigned long *vmx_vmread_bitmap;
745static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 746
110312c8 747static bool cpu_has_load_ia32_efer;
8bf00a52 748static bool cpu_has_load_perf_global_ctrl;
110312c8 749
2384d2b3
SY		 750static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
751static DEFINE_SPINLOCK(vmx_vpid_lock);
752
1c3d14fe 753static struct vmcs_config {
6aa8b732
AK		 754 int size;
755 int order;
756 u32 revision_id;
1c3d14fe
YS		 757 u32 pin_based_exec_ctrl;
758 u32 cpu_based_exec_ctrl;
f78e0e2e 759 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 760 u32 vmexit_ctrl;
761 u32 vmentry_ctrl;
762} vmcs_config;
6aa8b732 763
efff9e53 764static struct vmx_capability {
d56f546d
SY		 765 u32 ept;
766 u32 vpid;
767} vmx_capability;
768
6aa8b732
AK		 769#define VMX_SEGMENT_FIELD(seg) \
770 [VCPU_SREG_##seg] = { \
771 .selector = GUEST_##seg##_SELECTOR, \
772 .base = GUEST_##seg##_BASE, \
773 .limit = GUEST_##seg##_LIMIT, \
774 .ar_bytes = GUEST_##seg##_AR_BYTES, \
775 }
776
772e0318 777static const struct kvm_vmx_segment_field {
6aa8b732
AK		 778 unsigned selector;
779 unsigned base;
780 unsigned limit;
781 unsigned ar_bytes;
782} kvm_vmx_segment_fields[] = {
783 VMX_SEGMENT_FIELD(CS),
784 VMX_SEGMENT_FIELD(DS),
785 VMX_SEGMENT_FIELD(ES),
786 VMX_SEGMENT_FIELD(FS),
787 VMX_SEGMENT_FIELD(GS),
788 VMX_SEGMENT_FIELD(SS),
789 VMX_SEGMENT_FIELD(TR),
790 VMX_SEGMENT_FIELD(LDTR),
791};
792
26bb0981
AK		 793static u64 host_efer;
794
6de4f3ad
AK		 795static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
796
4d56c8a7 797/*
8c06585d 798 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 799 * away by decrementing the array size.
800 */
6aa8b732 801static const u32 vmx_msr_index[] = {
05b3e0c2 802#ifdef CONFIG_X86_64
44ea2b17 803 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 804#endif
8c06585d 805 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 806};
9d8f549d 807#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 808
31299944 809static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 810{
811 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
812 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 813 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 814}
815
31299944 816static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 817{
818 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
819 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 820 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 821}
822
31299944 823static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 824{
825 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
826 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 827 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 828}
829
31299944 830static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 831{
832 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
833 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
834}
835
31299944 836static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 837{
838 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
839 INTR_INFO_VALID_MASK)) ==
840 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
841}
842
31299944 843static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 844{
04547156 845 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 846}
847
31299944 848static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 849{
04547156 850 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 851}
852
31299944 853static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 854{
04547156 855 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 856}
857
31299944 858static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 859{
04547156
SY		 860 return vmcs_config.cpu_based_exec_ctrl &
861 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 862}
863
774ead3a 864static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 865{
04547156
SY		 866 return vmcs_config.cpu_based_2nd_exec_ctrl &
867 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
868}
869
8d14695f
YZ		 870static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
871{
872 return vmcs_config.cpu_based_2nd_exec_ctrl &
873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
874}
875
83d4c286
YZ		 876static inline bool cpu_has_vmx_apic_register_virt(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_APIC_REGISTER_VIRT;
880}
881
c7c9c56c
YZ		 882static inline bool cpu_has_vmx_virtual_intr_delivery(void)
883{
884 return vmcs_config.cpu_based_2nd_exec_ctrl &
885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
886}
887
01e439be
YZ		 888static inline bool cpu_has_vmx_posted_intr(void)
889{
890 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
891}
892
893static inline bool cpu_has_vmx_apicv(void)
894{
895 return cpu_has_vmx_apic_register_virt() &&
896 cpu_has_vmx_virtual_intr_delivery() &&
897 cpu_has_vmx_posted_intr();
898}
899
04547156
SY		 900static inline bool cpu_has_vmx_flexpriority(void)
901{
902 return cpu_has_vmx_tpr_shadow() &&
903 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 904}
905
e799794e
MT		 906static inline bool cpu_has_vmx_ept_execute_only(void)
907{
31299944 908 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 909}
910
911static inline bool cpu_has_vmx_eptp_uncacheable(void)
912{
31299944 913 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 914}
915
916static inline bool cpu_has_vmx_eptp_writeback(void)
917{
31299944 918 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 919}
920
921static inline bool cpu_has_vmx_ept_2m_page(void)
922{
31299944 923 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 924}
925
878403b7
SY		 926static inline bool cpu_has_vmx_ept_1g_page(void)
927{
31299944 928 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 929}
930
4bc9b982
SY		 931static inline bool cpu_has_vmx_ept_4levels(void)
932{
933 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
934}
935
83c3a331
XH		 936static inline bool cpu_has_vmx_ept_ad_bits(void)
937{
938 return vmx_capability.ept & VMX_EPT_AD_BIT;
939}
940
31299944 941static inline bool cpu_has_vmx_invept_context(void)
d56f546d 942{
31299944 943 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 944}
945
31299944 946static inline bool cpu_has_vmx_invept_global(void)
d56f546d 947{
31299944 948 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 949}
950
518c8aee
GJ		 951static inline bool cpu_has_vmx_invvpid_single(void)
952{
953 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
954}
955
b9d762fa
GJ		 956static inline bool cpu_has_vmx_invvpid_global(void)
957{
958 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
959}
960
31299944 961static inline bool cpu_has_vmx_ept(void)
d56f546d 962{
04547156
SY		 963 return vmcs_config.cpu_based_2nd_exec_ctrl &
964 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 965}
966
31299944 967static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 968{
969 return vmcs_config.cpu_based_2nd_exec_ctrl &
970 SECONDARY_EXEC_UNRESTRICTED_GUEST;
971}
972
31299944 973static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 974{
975 return vmcs_config.cpu_based_2nd_exec_ctrl &
976 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
977}
978
31299944 979static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 980{
6d3e435e 981 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 982}
983
31299944 984static inline bool cpu_has_vmx_vpid(void)
2384d2b3 985{
04547156
SY		 986 return vmcs_config.cpu_based_2nd_exec_ctrl &
987 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 988}
989
31299944 990static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 991{
992 return vmcs_config.cpu_based_2nd_exec_ctrl &
993 SECONDARY_EXEC_RDTSCP;
994}
995
ad756a16
MJ		 996static inline bool cpu_has_vmx_invpcid(void)
997{
998 return vmcs_config.cpu_based_2nd_exec_ctrl &
999 SECONDARY_EXEC_ENABLE_INVPCID;
1000}
1001
31299944 1002static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1003{
1004 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005}
1006
f5f48ee1
SY		 1007static inline bool cpu_has_vmx_wbinvd_exit(void)
1008{
1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_WBINVD_EXITING;
1011}
1012
abc4fc58
AG		 1013static inline bool cpu_has_vmx_shadow_vmcs(void)
1014{
1015 u64 vmx_msr;
1016 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017 /* check if the cpu supports writing r/o exit information fields */
1018 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019 return false;
1020
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_SHADOW_VMCS;
1023}
1024
04547156
SY		 1025static inline bool report_flexpriority(void)
1026{
1027 return flexpriority_enabled;
1028}
1029
fe3ef05c
NHE		 1030static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031{
1032 return vmcs12->cpu_based_vm_exec_control & bit;
1033}
1034
1035static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036{
1037 return (vmcs12->cpu_based_vm_exec_control &
1038 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039 (vmcs12->secondary_vm_exec_control & bit);
1040}
1041
644d711a
NHE		 1042static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043 struct kvm_vcpu *vcpu)
1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
1048static inline bool is_exception(u32 intr_info)
1049{
1050 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052}
1053
1054static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1055static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056 struct vmcs12 *vmcs12,
1057 u32 reason, unsigned long qualification);
1058
8b9cf98c 1059static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1060{
1061 int i;
1062
a2fa3e9f 1063 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1064 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1065 return i;
1066 return -1;
1067}
1068
2384d2b3
SY		 1069static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070{
1071 struct {
1072 u64 vpid : 16;
1073 u64 rsvd : 48;
1074 u64 gva;
1075 } operand = { vpid, 0, gva };
1076
4ecac3fd 1077 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1078 /* CF==1 or ZF==1 --> rc = -1 */
1079 "; ja 1f ; ud2 ; 1:"
1080 : : "a"(&operand), "c"(ext) : "cc", "memory");
1081}
1082
1439442c
SY		 1083static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084{
1085 struct {
1086 u64 eptp, gpa;
1087 } operand = {eptp, gpa};
1088
4ecac3fd 1089 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1090 /* CF==1 or ZF==1 --> rc = -1 */
1091 "; ja 1f ; ud2 ; 1:\n"
1092 : : "a" (&operand), "c" (ext) : "cc", "memory");
1093}
1094
26bb0981 1095static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1096{
1097 int i;
1098
8b9cf98c 1099 i = __find_msr_index(vmx, msr);
a75beee6 1100 if (i >= 0)
a2fa3e9f 1101 return &vmx->guest_msrs[i];
8b6d44c7 1102 return NULL;
7725f0ba
AK		 1103}
1104
6aa8b732
AK		 1105static void vmcs_clear(struct vmcs *vmcs)
1106{
1107 u64 phys_addr = __pa(vmcs);
1108 u8 error;
1109
4ecac3fd 1110 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1111 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1112 : "cc", "memory");
1113 if (error)
1114 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115 vmcs, phys_addr);
1116}
1117
d462b819
NHE		 1118static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119{
1120 vmcs_clear(loaded_vmcs->vmcs);
1121 loaded_vmcs->cpu = -1;
1122 loaded_vmcs->launched = 0;
1123}
1124
7725b894
DX		 1125static void vmcs_load(struct vmcs *vmcs)
1126{
1127 u64 phys_addr = __pa(vmcs);
1128 u8 error;
1129
1130 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1131 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1132 : "cc", "memory");
1133 if (error)
2844d849 1134 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1135 vmcs, phys_addr);
1136}
1137
8f536b76
ZY		 1138#ifdef CONFIG_KEXEC
1139/*
1140 * This bitmap is used to indicate whether the vmclear
1141 * operation is enabled on all cpus. All disabled by
1142 * default.
1143 */
1144static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146static inline void crash_enable_local_vmclear(int cpu)
1147{
1148 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149}
1150
1151static inline void crash_disable_local_vmclear(int cpu)
1152{
1153 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline int crash_local_vmclear_enabled(int cpu)
1157{
1158 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static void crash_vmclear_local_loaded_vmcss(void)
1162{
1163 int cpu = raw_smp_processor_id();
1164 struct loaded_vmcs *v;
1165
1166 if (!crash_local_vmclear_enabled(cpu))
1167 return;
1168
1169 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170 loaded_vmcss_on_cpu_link)
1171 vmcs_clear(v->vmcs);
1172}
1173#else
1174static inline void crash_enable_local_vmclear(int cpu) { }
1175static inline void crash_disable_local_vmclear(int cpu) { }
1176#endif /* CONFIG_KEXEC */
1177
d462b819 1178static void __loaded_vmcs_clear(void *arg)
6aa8b732 1179{
d462b819 1180 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1181 int cpu = raw_smp_processor_id();
6aa8b732 1182
d462b819
NHE		 1183 if (loaded_vmcs->cpu != cpu)
1184 return; /* vcpu migration can race with cpu offline */
1185 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1186 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1187 crash_disable_local_vmclear(cpu);
d462b819 1188 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1189
1190 /*
1191 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192 * is before setting loaded_vmcs->vcpu to -1 which is done in
1193 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194 * then adds the vmcs into percpu list before it is deleted.
1195 */
1196 smp_wmb();
1197
d462b819 1198 loaded_vmcs_init(loaded_vmcs);
8f536b76 1199 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1200}
1201
d462b819 1202static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1203{
e6c7d321
XG		 1204 int cpu = loaded_vmcs->cpu;
1205
1206 if (cpu != -1)
1207 smp_call_function_single(cpu,
1208 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1209}
1210
1760dd49 1211static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1212{
1213 if (vmx->vpid == 0)
1214 return;
1215
518c8aee
GJ		 1216 if (cpu_has_vmx_invvpid_single())
1217 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1218}
1219
b9d762fa
GJ		 1220static inline void vpid_sync_vcpu_global(void)
1221{
1222 if (cpu_has_vmx_invvpid_global())
1223 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224}
1225
1226static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227{
1228 if (cpu_has_vmx_invvpid_single())
1760dd49 1229 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1230 else
1231 vpid_sync_vcpu_global();
1232}
1233
1439442c
SY		 1234static inline void ept_sync_global(void)
1235{
1236 if (cpu_has_vmx_invept_global())
1237 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238}
1239
1240static inline void ept_sync_context(u64 eptp)
1241{
089d034e 1242 if (enable_ept) {
1439442c
SY		 1243 if (cpu_has_vmx_invept_context())
1244 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245 else
1246 ept_sync_global();
1247 }
1248}
1249
96304217 1250static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1251{
5e520e62 1252 unsigned long value;
6aa8b732 1253
5e520e62
AK		 1254 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1256 return value;
1257}
1258
96304217 1259static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1260{
1261 return vmcs_readl(field);
1262}
1263
96304217 1264static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1270{
05b3e0c2 1271#ifdef CONFIG_X86_64
6aa8b732
AK		 1272 return vmcs_readl(field);
1273#else
1274 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275#endif
1276}
1277
e52de1b8
AK		 1278static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279{
1280 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282 dump_stack();
1283}
1284
6aa8b732
AK		 1285static void vmcs_writel(unsigned long field, unsigned long value)
1286{
1287 u8 error;
1288
4ecac3fd 1289 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1290 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1291 if (unlikely(error))
1292 vmwrite_error(field, value);
6aa8b732
AK		 1293}
1294
1295static void vmcs_write16(unsigned long field, u16 value)
1296{
1297 vmcs_writel(field, value);
1298}
1299
1300static void vmcs_write32(unsigned long field, u32 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write64(unsigned long field, u64 value)
1306{
6aa8b732 1307 vmcs_writel(field, value);
7682f2d0 1308#ifndef CONFIG_X86_64
6aa8b732
AK		 1309 asm volatile ("");
1310 vmcs_writel(field+1, value >> 32);
1311#endif
1312}
1313
2ab455cc
AL		 1314static void vmcs_clear_bits(unsigned long field, u32 mask)
1315{
1316 vmcs_writel(field, vmcs_readl(field) & ~mask);
1317}
1318
1319static void vmcs_set_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) | mask);
1322}
1323
2fb92db1
AK		 1324static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325{
1326 vmx->segment_cache.bitmask = 0;
1327}
1328
1329static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330 unsigned field)
1331{
1332 bool ret;
1333 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337 vmx->segment_cache.bitmask = 0;
1338 }
1339 ret = vmx->segment_cache.bitmask & mask;
1340 vmx->segment_cache.bitmask |= mask;
1341 return ret;
1342}
1343
1344static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345{
1346 u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350 return *p;
1351}
1352
1353static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354{
1355 ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359 return *p;
1360}
1361
1362static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363{
1364 u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368 return *p;
1369}
1370
1371static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372{
1373 u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377 return *p;
1378}
1379
abd3f2d6
AK		 1380static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381{
1382 u32 eb;
1383
fd7373cc
JK		 1384 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386 if ((vcpu->guest_debug &
1387 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389 eb |= 1u << BP_VECTOR;
7ffd92c5 1390 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1391 eb = ~0;
089d034e 1392 if (enable_ept)
1439442c 1393 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1394 if (vcpu->fpu_active)
1395 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1396
1397 /* When we are running a nested L2 guest and L1 specified for it a
1398 * certain exception bitmap, we must trap the same exceptions and pass
1399 * them to L1. When running L2, we will only handle the exceptions
1400 * specified above if L1 did not want them.
1401 */
1402 if (is_guest_mode(vcpu))
1403 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
abd3f2d6
AK		 1405 vmcs_write32(EXCEPTION_BITMAP, eb);
1406}
1407
8bf00a52
GN		 1408static void clear_atomic_switch_msr_special(unsigned long entry,
1409 unsigned long exit)
1410{
1411 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413}
1414
61d2ef2c
AK		 1415static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416{
1417 unsigned i;
1418 struct msr_autoload *m = &vmx->msr_autoload;
1419
8bf00a52
GN		 1420 switch (msr) {
1421 case MSR_EFER:
1422 if (cpu_has_load_ia32_efer) {
1423 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424 VM_EXIT_LOAD_IA32_EFER);
1425 return;
1426 }
1427 break;
1428 case MSR_CORE_PERF_GLOBAL_CTRL:
1429 if (cpu_has_load_perf_global_ctrl) {
1430 clear_atomic_switch_msr_special(
1431 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433 return;
1434 }
1435 break;
110312c8
AK		 1436 }
1437
61d2ef2c
AK		 1438 for (i = 0; i < m->nr; ++i)
1439 if (m->guest[i].index == msr)
1440 break;
1441
1442 if (i == m->nr)
1443 return;
1444 --m->nr;
1445 m->guest[i] = m->guest[m->nr];
1446 m->host[i] = m->host[m->nr];
1447 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449}
1450
8bf00a52
GN		 1451static void add_atomic_switch_msr_special(unsigned long entry,
1452 unsigned long exit, unsigned long guest_val_vmcs,
1453 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454{
1455 vmcs_write64(guest_val_vmcs, guest_val);
1456 vmcs_write64(host_val_vmcs, host_val);
1457 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459}
1460
61d2ef2c
AK		 1461static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462 u64 guest_val, u64 host_val)
1463{
1464 unsigned i;
1465 struct msr_autoload *m = &vmx->msr_autoload;
1466
8bf00a52
GN		 1467 switch (msr) {
1468 case MSR_EFER:
1469 if (cpu_has_load_ia32_efer) {
1470 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471 VM_EXIT_LOAD_IA32_EFER,
1472 GUEST_IA32_EFER,
1473 HOST_IA32_EFER,
1474 guest_val, host_val);
1475 return;
1476 }
1477 break;
1478 case MSR_CORE_PERF_GLOBAL_CTRL:
1479 if (cpu_has_load_perf_global_ctrl) {
1480 add_atomic_switch_msr_special(
1481 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483 GUEST_IA32_PERF_GLOBAL_CTRL,
1484 HOST_IA32_PERF_GLOBAL_CTRL,
1485 guest_val, host_val);
1486 return;
1487 }
1488 break;
110312c8
AK		 1489 }
1490
61d2ef2c
AK		 1491 for (i = 0; i < m->nr; ++i)
1492 if (m->guest[i].index == msr)
1493 break;
1494
e7fc6f93
GN		 1495 if (i == NR_AUTOLOAD_MSRS) {
1496 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497 "Can't add msr %x\n", msr);
1498 return;
1499 } else if (i == m->nr) {
61d2ef2c
AK		 1500 ++m->nr;
1501 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503 }
1504
1505 m->guest[i].index = msr;
1506 m->guest[i].value = guest_val;
1507 m->host[i].index = msr;
1508 m->host[i].value = host_val;
1509}
1510
33ed6329
AK		 1511static void reload_tss(void)
1512{
33ed6329
AK		 1513 /*
1514 * VT restores TR but not its size. Useless.
1515 */
d359192f 1516 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1517 struct desc_struct *descs;
33ed6329 1518
d359192f 1519 descs = (void *)gdt->address;
33ed6329
AK		 1520 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521 load_TR_desc();
33ed6329
AK		 1522}
1523
92c0d900 1524static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1525{
3a34a881 1526 u64 guest_efer;
51c6cf66
AK		 1527 u64 ignore_bits;
1528
f6801dff 1529 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1530
51c6cf66 1531 /*
0fa06071 1532 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1533 * outside long mode
1534 */
1535 ignore_bits = EFER_NX | EFER_SCE;
1536#ifdef CONFIG_X86_64
1537 ignore_bits |= EFER_LMA | EFER_LME;
1538 /* SCE is meaningful only in long mode on Intel */
1539 if (guest_efer & EFER_LMA)
1540 ignore_bits &= ~(u64)EFER_SCE;
1541#endif
51c6cf66
AK		 1542 guest_efer &= ~ignore_bits;
1543 guest_efer |= host_efer & ignore_bits;
26bb0981 1544 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1545 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1546
1547 clear_atomic_switch_msr(vmx, MSR_EFER);
1548 /* On ept, can't emulate nx, and must switch nx atomically */
1549 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550 guest_efer = vmx->vcpu.arch.efer;
1551 if (!(guest_efer & EFER_LMA))
1552 guest_efer &= ~EFER_LME;
1553 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554 return false;
1555 }
1556
26bb0981 1557 return true;
51c6cf66
AK		 1558}
1559
2d49ec72
GN		 1560static unsigned long segment_base(u16 selector)
1561{
d359192f 1562 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1563 struct desc_struct *d;
1564 unsigned long table_base;
1565 unsigned long v;
1566
1567 if (!(selector & ~3))
1568 return 0;
1569
d359192f 1570 table_base = gdt->address;
2d49ec72
GN		 1571
1572 if (selector & 4) { /* from ldt */
1573 u16 ldt_selector = kvm_read_ldt();
1574
1575 if (!(ldt_selector & ~3))
1576 return 0;
1577
1578 table_base = segment_base(ldt_selector);
1579 }
1580 d = (struct desc_struct *)(table_base + (selector & ~7));
1581 v = get_desc_base(d);
1582#ifdef CONFIG_X86_64
1583 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585#endif
1586 return v;
1587}
1588
1589static inline unsigned long kvm_read_tr_base(void)
1590{
1591 u16 tr;
1592 asm("str %0" : "=g"(tr));
1593 return segment_base(tr);
1594}
1595
04d2cc77 1596static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1597{
04d2cc77 1598 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1599 int i;
04d2cc77 1600
a2fa3e9f 1601 if (vmx->host_state.loaded)
33ed6329
AK		 1602 return;
1603
a2fa3e9f 1604 vmx->host_state.loaded = 1;
33ed6329
AK		 1605 /*
1606 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1607 * allow segment selectors with cpl > 0 or ti == 1.
1608 */
d6e88aec 1609 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1610 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1611 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1612 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1613 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1614 vmx->host_state.fs_reload_needed = 0;
1615 } else {
33ed6329 1616 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1617 vmx->host_state.fs_reload_needed = 1;
33ed6329 1618 }
9581d442 1619 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1620 if (!(vmx->host_state.gs_sel & 7))
1621 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1622 else {
1623 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1624 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1625 }
1626
b2da15ac
AK		 1627#ifdef CONFIG_X86_64
1628 savesegment(ds, vmx->host_state.ds_sel);
1629 savesegment(es, vmx->host_state.es_sel);
1630#endif
1631
33ed6329
AK		 1632#ifdef CONFIG_X86_64
1633 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635#else
a2fa3e9f
GH		 1636 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1638#endif
707c0874
AK		 1639
1640#ifdef CONFIG_X86_64
c8770e7b
AK		 1641 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642 if (is_long_mode(&vmx->vcpu))
44ea2b17 1643 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1644#endif
26bb0981
AK		 1645 for (i = 0; i < vmx->save_nmsrs; ++i)
1646 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1647 vmx->guest_msrs[i].data,
1648 vmx->guest_msrs[i].mask);
33ed6329
AK		 1649}
1650
a9b21b62 1651static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1652{
a2fa3e9f 1653 if (!vmx->host_state.loaded)
33ed6329
AK		 1654 return;
1655
e1beb1d3 1656 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1657 vmx->host_state.loaded = 0;
c8770e7b
AK		 1658#ifdef CONFIG_X86_64
1659 if (is_long_mode(&vmx->vcpu))
1660 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661#endif
152d3f2f 1662 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1663 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1664#ifdef CONFIG_X86_64
9581d442 1665 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1666#else
1667 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1668#endif
33ed6329 1669 }
0a77fe4c
AK		 1670 if (vmx->host_state.fs_reload_needed)
1671 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1672#ifdef CONFIG_X86_64
1673 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674 loadsegment(ds, vmx->host_state.ds_sel);
1675 loadsegment(es, vmx->host_state.es_sel);
1676 }
b2da15ac 1677#endif
152d3f2f 1678 reload_tss();
44ea2b17 1679#ifdef CONFIG_X86_64
c8770e7b 1680 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1681#endif
b1a74bf8
SS		 1682 /*
1683 * If the FPU is not active (through the host task or
1684 * the guest vcpu), then restore the cr0.TS bit.
1685 */
1686 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687 stts();
3444d7da 1688 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1689}
1690
a9b21b62
AK		 1691static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692{
1693 preempt_disable();
1694 __vmx_load_host_state(vmx);
1695 preempt_enable();
1696}
1697
6aa8b732
AK		 1698/*
1699 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700 * vcpu mutex is already taken.
1701 */
15ad7146 1702static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1703{
a2fa3e9f 1704 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1705 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1706
4610c9cc
DX		 1707 if (!vmm_exclusive)
1708 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1709 else if (vmx->loaded_vmcs->cpu != cpu)
1710 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1711
d462b819
NHE		 1712 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1715 }
1716
d462b819 1717 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1718 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1719 unsigned long sysenter_esp;
1720
a8eeb04a 1721 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1722 local_irq_disable();
8f536b76 1723 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1724
1725 /*
1726 * Read loaded_vmcs->cpu should be before fetching
1727 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728 * See the comments in __loaded_vmcs_clear().
1729 */
1730 smp_rmb();
1731
d462b819
NHE		 1732 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1734 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1735 local_irq_enable();
1736
6aa8b732
AK		 1737 /*
1738 * Linux uses per-cpu TSS and GDT, so set these when switching
1739 * processors.
1740 */
d6e88aec 1741 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1742 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1743
1744 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1746 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1747 }
6aa8b732
AK		 1748}
1749
1750static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751{
a9b21b62 1752 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1753 if (!vmm_exclusive) {
d462b819
NHE		 1754 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755 vcpu->cpu = -1;
4610c9cc
DX		 1756 kvm_cpu_vmxoff();
1757 }
6aa8b732
AK		 1758}
1759
5fd86fcf
AK		 1760static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761{
81231c69
AK		 1762 ulong cr0;
1763
5fd86fcf
AK		 1764 if (vcpu->fpu_active)
1765 return;
1766 vcpu->fpu_active = 1;
81231c69
AK		 1767 cr0 = vmcs_readl(GUEST_CR0);
1768 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1771 update_exception_bitmap(vcpu);
edcafe3c 1772 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1773 if (is_guest_mode(vcpu))
1774 vcpu->arch.cr0_guest_owned_bits &=
1775 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1776 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1777}
1778
edcafe3c
AK		 1779static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
fe3ef05c
NHE		 1781/*
1782 * Return the cr0 value that a nested guest would read. This is a combination
1783 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784 * its hypervisor (cr0_read_shadow).
1785 */
1786static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787{
1788 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790}
1791static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795}
1796
5fd86fcf
AK		 1797static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798{
36cf24e0
NHE		 1799 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800 * set this *before* calling this function.
1801 */
edcafe3c 1802 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1803 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1804 update_exception_bitmap(vcpu);
edcafe3c
AK		 1805 vcpu->arch.cr0_guest_owned_bits = 0;
1806 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1807 if (is_guest_mode(vcpu)) {
1808 /*
1809 * L1's specified read shadow might not contain the TS bit,
1810 * so now that we turned on shadowing of this bit, we need to
1811 * set this bit of the shadow. Like in nested_vmx_run we need
1812 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813 * up-to-date here because we just decached cr0.TS (and we'll
1814 * only update vmcs12->guest_cr0 on nested exit).
1815 */
1816 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818 (vcpu->arch.cr0 & X86_CR0_TS);
1819 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820 } else
1821 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1822}
1823
6aa8b732
AK		 1824static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825{
78ac8b47 1826 unsigned long rflags, save_rflags;
345dcaa8 1827
6de12732
AK		 1828 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830 rflags = vmcs_readl(GUEST_RFLAGS);
1831 if (to_vmx(vcpu)->rmode.vm86_active) {
1832 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835 }
1836 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1837 }
6de12732 1838 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1839}
1840
1841static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842{
6de12732
AK		 1843 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1845 if (to_vmx(vcpu)->rmode.vm86_active) {
1846 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1847 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1848 }
6aa8b732
AK		 1849 vmcs_writel(GUEST_RFLAGS, rflags);
1850}
1851
2809f5d2
GC		 1852static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853{
1854 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855 int ret = 0;
1856
1857 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1858 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1859 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1860 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1861
1862 return ret & mask;
1863}
1864
1865static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866{
1867 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868 u32 interruptibility = interruptibility_old;
1869
1870 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
48005f64 1872 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1873 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1874 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1875 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877 if ((interruptibility != interruptibility_old))
1878 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879}
1880
6aa8b732
AK		 1881static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882{
1883 unsigned long rip;
6aa8b732 1884
5fdbf976 1885 rip = kvm_rip_read(vcpu);
6aa8b732 1886 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1887 kvm_rip_write(vcpu, rip);
6aa8b732 1888
2809f5d2
GC		 1889 /* skipping an emulated instruction also counts */
1890 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1891}
1892
0b6ac343
NHE		 1893/*
1894 * KVM wants to inject page-faults which it got to the guest. This function
1895 * checks whether in a nested guest, we need to inject them to L1 or L2.
1896 * This function assumes it is called with the exit reason in vmcs02 being
1897 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898 * is running).
1899 */
1900static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901{
1902 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1905 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1906 return 0;
1907
1908 nested_vmx_vmexit(vcpu);
1909 return 1;
1910}
1911
298101da 1912static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1913 bool has_error_code, u32 error_code,
1914 bool reinject)
298101da 1915{
77ab6db0 1916 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1917 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1918
0b6ac343 1919 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1920 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1921 return;
1922
8ab2d2e2 1923 if (has_error_code) {
77ab6db0 1924 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1925 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926 }
77ab6db0 1927
7ffd92c5 1928 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1929 int inc_eip = 0;
1930 if (kvm_exception_is_soft(nr))
1931 inc_eip = vcpu->arch.event_exit_inst_len;
1932 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1933 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1934 return;
1935 }
1936
66fd3f7f
GN		 1937 if (kvm_exception_is_soft(nr)) {
1938 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1940 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941 } else
1942 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1945}
1946
4e47c7a6
SY		 1947static bool vmx_rdtscp_supported(void)
1948{
1949 return cpu_has_vmx_rdtscp();
1950}
1951
ad756a16
MJ		 1952static bool vmx_invpcid_supported(void)
1953{
1954 return cpu_has_vmx_invpcid() && enable_ept;
1955}
1956
a75beee6
ED		 1957/*
1958 * Swap MSR entry in host/guest MSR entry array.
1959 */
8b9cf98c 1960static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1961{
26bb0981 1962 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1963
1964 tmp = vmx->guest_msrs[to];
1965 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1967}
1968
8d14695f
YZ		 1969static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970{
1971 unsigned long *msr_bitmap;
1972
1973 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974 if (is_long_mode(vcpu))
1975 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976 else
1977 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978 } else {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy;
1983 }
1984
1985 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986}
1987
e38aea3e
AK		 1988/*
1989 * Set up the vmcs to automatically save and restore system
1990 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1991 * mode, as fiddling with msrs is very expensive.
1992 */
8b9cf98c 1993static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1994{
26bb0981 1995 int save_nmsrs, index;
e38aea3e 1996
a75beee6
ED		 1997 save_nmsrs = 0;
1998#ifdef CONFIG_X86_64
8b9cf98c 1999 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2000 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2001 if (index >= 0)
8b9cf98c
RR		 2002 move_msr_up(vmx, index, save_nmsrs++);
2003 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2004 if (index >= 0)
8b9cf98c
RR		 2005 move_msr_up(vmx, index, save_nmsrs++);
2006 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2007 if (index >= 0)
8b9cf98c 2008 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2009 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010 if (index >= 0 && vmx->rdtscp_enabled)
2011 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2012 /*
8c06585d 2013 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2014 * if efer.sce is enabled.
2015 */
8c06585d 2016 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2017 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2018 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2019 }
2020#endif
92c0d900
AK		 2021 index = __find_msr_index(vmx, MSR_EFER);
2022 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2023 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2024
26bb0981 2025 vmx->save_nmsrs = save_nmsrs;
5897297b 2026
8d14695f
YZ		 2027 if (cpu_has_vmx_msr_bitmap())
2028 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2029}
2030
6aa8b732
AK		 2031/*
2032 * reads and returns guest's timestamp counter "register"
2033 * guest_tsc = host_tsc + tsc_offset -- 21.3
2034 */
2035static u64 guest_read_tsc(void)
2036{
2037 u64 host_tsc, tsc_offset;
2038
2039 rdtscll(host_tsc);
2040 tsc_offset = vmcs_read64(TSC_OFFSET);
2041 return host_tsc + tsc_offset;
2042}
2043
d5c1785d
NHE		 2044/*
2045 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046 * counter, even if a nested guest (L2) is currently running.
2047 */
886b470c 2048u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2049{
886b470c 2050 u64 tsc_offset;
d5c1785d 2051
d5c1785d
NHE		 2052 tsc_offset = is_guest_mode(vcpu) ?
2053 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054 vmcs_read64(TSC_OFFSET);
2055 return host_tsc + tsc_offset;
2056}
2057
4051b188 2058/*
cc578287
ZA		 2059 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2060 * software catchup for faster rates on slower CPUs.
4051b188 2061 */
cc578287 2062static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2063{
cc578287
ZA		 2064 if (!scale)
2065 return;
2066
2067 if (user_tsc_khz > tsc_khz) {
2068 vcpu->arch.tsc_catchup = 1;
2069 vcpu->arch.tsc_always_catchup = 1;
2070 } else
2071 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2072}
2073
ba904635
WA		 2074static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075{
2076 return vmcs_read64(TSC_OFFSET);
2077}
2078
6aa8b732 2079/*
99e3e30a 2080 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2081 */
99e3e30a 2082static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2083{
27fc51b2 2084 if (is_guest_mode(vcpu)) {
7991825b 2085 /*
27fc51b2
NHE		 2086 * We're here if L1 chose not to trap WRMSR to TSC. According
2087 * to the spec, this should set L1's TSC; The offset that L1
2088 * set for L2 remains unchanged, and still needs to be added
2089 * to the newly set TSC to get L2's TSC.
7991825b 2090 */
27fc51b2
NHE		 2091 struct vmcs12 *vmcs12;
2092 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093 /* recalculate vmcs02.TSC_OFFSET: */
2094 vmcs12 = get_vmcs12(vcpu);
2095 vmcs_write64(TSC_OFFSET, offset +
2096 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097 vmcs12->tsc_offset : 0));
2098 } else {
489223ed
YY		 2099 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2100 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2101 vmcs_write64(TSC_OFFSET, offset);
2102 }
6aa8b732
AK		 2103}
2104
f1e2b260 2105static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2106{
2107 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2108
e48672fa 2109 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2110 if (is_guest_mode(vcpu)) {
2111 /* Even when running L2, the adjustment needs to apply to L1 */
2112 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2113 } else
2114 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2115 offset + adjustment);
e48672fa
ZA		 2116}
2117
857e4099
JR		 2118static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2119{
2120 return target_tsc - native_read_tsc();
2121}
2122
801d3424
NHE		 2123static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2124{
2125 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2126 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2127}
2128
2129/*
2130 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2131 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2132 * all guests if the "nested" module option is off, and can also be disabled
2133 * for a single guest by disabling its VMX cpuid bit.
2134 */
2135static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2136{
2137 return nested && guest_cpuid_has_vmx(vcpu);
2138}
2139
b87a51ae
NHE		 2140/*
2141 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2142 * returned for the various VMX controls MSRs when nested VMX is enabled.
2143 * The same values should also be used to verify that vmcs12 control fields are
2144 * valid during nested entry from L1 to L2.
2145 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2146 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2147 * bit in the high half is on if the corresponding bit in the control field
2148 * may be on. See also vmx_control_verify().
2149 * TODO: allow these variables to be modified (downgraded) by module options
2150 * or other means.
2151 */
2152static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2153static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2154static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2155static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2156static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2157static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2158static __init void nested_vmx_setup_ctls_msrs(void)
2159{
2160 /*
2161 * Note that as a general rule, the high half of the MSRs (bits in
2162 * the control fields which may be 1) should be initialized by the
2163 * intersection of the underlying hardware's MSR (i.e., features which
2164 * can be supported) and the list of features we want to expose -
2165 * because they are known to be properly supported in our code.
2166 * Also, usually, the low half of the MSRs (bits which must be 1) can
2167 * be set to 0, meaning that L1 may turn off any of these bits. The
2168 * reason is that if one of these bits is necessary, it will appear
2169 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2170 * fields of vmcs01 and vmcs02, will turn these bits off - and
2171 * nested_vmx_exit_handled() will not pass related exits to L1.
2172 * These rules have exceptions below.
2173 */
2174
2175 /* pin-based controls */
eabeaacc
JK		 2176 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2177 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2178 /*
2179 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2180 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2181 */
eabeaacc
JK		 2182 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2183 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2184 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2185 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2186 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2187
33fb20c3
JK		 2188 /*
2189 * Exit controls
2190 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2191 * 17 must be 1.
2192 */
2193 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2194 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2195#ifdef CONFIG_X86_64
2196 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2197#else
2198 nested_vmx_exit_ctls_high = 0;
2199#endif
33fb20c3 2200 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2201
2202 /* entry controls */
2203 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2204 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2205 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2206 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2207 nested_vmx_entry_ctls_high &=
2208 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2209 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2210
2211 /* cpu-based controls */
2212 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2213 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2214 nested_vmx_procbased_ctls_low = 0;
2215 nested_vmx_procbased_ctls_high &=
2216 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2217 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2218 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2219 CPU_BASED_CR3_STORE_EXITING |
2220#ifdef CONFIG_X86_64
2221 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2222#endif
2223 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2224 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2225 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2226 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2227 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2228 /*
2229 * We can allow some features even when not supported by the
2230 * hardware. For example, L1 can specify an MSR bitmap - and we
2231 * can use it to avoid exits to L1 - even when L0 runs L2
2232 * without MSR bitmaps.
2233 */
2234 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2235
2236 /* secondary cpu-based controls */
2237 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2238 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2239 nested_vmx_secondary_ctls_low = 0;
2240 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2242 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2243
2244 /* miscellaneous data */
2245 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2246 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2247 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2248 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2249}
2250
2251static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2252{
2253 /*
2254 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2255 */
2256 return ((control & high) | low) == control;
2257}
2258
2259static inline u64 vmx_control_msr(u32 low, u32 high)
2260{
2261 return low | ((u64)high << 32);
2262}
2263
2264/*
2265 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2266 * also let it use VMX-specific MSRs.
2267 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2268 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2269 * like all other MSRs).
2270 */
2271static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2272{
2273 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2274 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2275 /*
2276 * According to the spec, processors which do not support VMX
2277 * should throw a #GP(0) when VMX capability MSRs are read.
2278 */
2279 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2280 return 1;
2281 }
2282
2283 switch (msr_index) {
2284 case MSR_IA32_FEATURE_CONTROL:
2285 *pdata = 0;
2286 break;
2287 case MSR_IA32_VMX_BASIC:
2288 /*
2289 * This MSR reports some information about VMX support. We
2290 * should return information about the VMX we emulate for the
2291 * guest, and the VMCS structure we give it - not about the
2292 * VMX support of the underlying hardware.
2293 */
2294 *pdata = VMCS12_REVISION |
2295 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2296 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2297 break;
2298 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2299 case MSR_IA32_VMX_PINBASED_CTLS:
2300 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2301 nested_vmx_pinbased_ctls_high);
2302 break;
2303 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2304 case MSR_IA32_VMX_PROCBASED_CTLS:
2305 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2306 nested_vmx_procbased_ctls_high);
2307 break;
2308 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2309 case MSR_IA32_VMX_EXIT_CTLS:
2310 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2311 nested_vmx_exit_ctls_high);
2312 break;
2313 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2314 case MSR_IA32_VMX_ENTRY_CTLS:
2315 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2316 nested_vmx_entry_ctls_high);
2317 break;
2318 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2319 *pdata = vmx_control_msr(nested_vmx_misc_low,
2320 nested_vmx_misc_high);
b87a51ae
NHE		 2321 break;
2322 /*
2323 * These MSRs specify bits which the guest must keep fixed (on or off)
2324 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2325 * We picked the standard core2 setting.
2326 */
2327#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2328#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2329 case MSR_IA32_VMX_CR0_FIXED0:
2330 *pdata = VMXON_CR0_ALWAYSON;
2331 break;
2332 case MSR_IA32_VMX_CR0_FIXED1:
2333 *pdata = -1ULL;
2334 break;
2335 case MSR_IA32_VMX_CR4_FIXED0:
2336 *pdata = VMXON_CR4_ALWAYSON;
2337 break;
2338 case MSR_IA32_VMX_CR4_FIXED1:
2339 *pdata = -1ULL;
2340 break;
2341 case MSR_IA32_VMX_VMCS_ENUM:
2342 *pdata = 0x1f;
2343 break;
2344 case MSR_IA32_VMX_PROCBASED_CTLS2:
2345 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2346 nested_vmx_secondary_ctls_high);
2347 break;
2348 case MSR_IA32_VMX_EPT_VPID_CAP:
2349 /* Currently, no nested ept or nested vpid */
2350 *pdata = 0;
2351 break;
2352 default:
2353 return 0;
2354 }
2355
2356 return 1;
2357}
2358
2359static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2360{
2361 if (!nested_vmx_allowed(vcpu))
2362 return 0;
2363
2364 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2365 /* TODO: the right thing. */
2366 return 1;
2367 /*
2368 * No need to treat VMX capability MSRs specially: If we don't handle
2369 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2370 */
2371 return 0;
2372}
2373
6aa8b732
AK		 2374/*
2375 * Reads an msr value (of 'msr_index') into 'pdata'.
2376 * Returns 0 on success, non-0 otherwise.
2377 * Assumes vcpu_load() was already called.
2378 */
2379static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2380{
2381 u64 data;
26bb0981 2382 struct shared_msr_entry *msr;
6aa8b732
AK		 2383
2384 if (!pdata) {
2385 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2386 return -EINVAL;
2387 }
2388
2389 switch (msr_index) {
05b3e0c2 2390#ifdef CONFIG_X86_64
6aa8b732
AK		 2391 case MSR_FS_BASE:
2392 data = vmcs_readl(GUEST_FS_BASE);
2393 break;
2394 case MSR_GS_BASE:
2395 data = vmcs_readl(GUEST_GS_BASE);
2396 break;
44ea2b17
AK		 2397 case MSR_KERNEL_GS_BASE:
2398 vmx_load_host_state(to_vmx(vcpu));
2399 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2400 break;
26bb0981 2401#endif
6aa8b732 2402 case MSR_EFER:
3bab1f5d 2403 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2404 case MSR_IA32_TSC:
6aa8b732
AK		 2405 data = guest_read_tsc();
2406 break;
2407 case MSR_IA32_SYSENTER_CS:
2408 data = vmcs_read32(GUEST_SYSENTER_CS);
2409 break;
2410 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2411 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2412 break;
2413 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2414 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2415 break;
4e47c7a6
SY		 2416 case MSR_TSC_AUX:
2417 if (!to_vmx(vcpu)->rdtscp_enabled)
2418 return 1;
2419 /* Otherwise falls through */
6aa8b732 2420 default:
b87a51ae
NHE		 2421 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2422 return 0;
8b9cf98c 2423 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2424 if (msr) {
2425 data = msr->data;
2426 break;
6aa8b732 2427 }
3bab1f5d 2428 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2429 }
2430
2431 *pdata = data;
2432 return 0;
2433}
2434
2435/*
2436 * Writes msr value into into the appropriate "register".
2437 * Returns 0 on success, non-0 otherwise.
2438 * Assumes vcpu_load() was already called.
2439 */
8fe8ab46 2440static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2441{
a2fa3e9f 2442 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2443 struct shared_msr_entry *msr;
2cc51560 2444 int ret = 0;
8fe8ab46
WA		 2445 u32 msr_index = msr_info->index;
2446 u64 data = msr_info->data;
2cc51560 2447
6aa8b732 2448 switch (msr_index) {
3bab1f5d 2449 case MSR_EFER:
8fe8ab46 2450 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2451 break;
16175a79 2452#ifdef CONFIG_X86_64
6aa8b732 2453 case MSR_FS_BASE:
2fb92db1 2454 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2455 vmcs_writel(GUEST_FS_BASE, data);
2456 break;
2457 case MSR_GS_BASE:
2fb92db1 2458 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2459 vmcs_writel(GUEST_GS_BASE, data);
2460 break;
44ea2b17
AK		 2461 case MSR_KERNEL_GS_BASE:
2462 vmx_load_host_state(vmx);
2463 vmx->msr_guest_kernel_gs_base = data;
2464 break;
6aa8b732
AK		 2465#endif
2466 case MSR_IA32_SYSENTER_CS:
2467 vmcs_write32(GUEST_SYSENTER_CS, data);
2468 break;
2469 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2470 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2471 break;
2472 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2473 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2474 break;
af24a4e4 2475 case MSR_IA32_TSC:
8fe8ab46 2476 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2477 break;
468d472f
SY		 2478 case MSR_IA32_CR_PAT:
2479 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2480 vmcs_write64(GUEST_IA32_PAT, data);
2481 vcpu->arch.pat = data;
2482 break;
2483 }
8fe8ab46 2484 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2485 break;
ba904635
WA		 2486 case MSR_IA32_TSC_ADJUST:
2487 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2488 break;
2489 case MSR_TSC_AUX:
2490 if (!vmx->rdtscp_enabled)
2491 return 1;
2492 /* Check reserved bit, higher 32 bits should be zero */
2493 if ((data >> 32) != 0)
2494 return 1;
2495 /* Otherwise falls through */
6aa8b732 2496 default:
b87a51ae
NHE		 2497 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2498 break;
8b9cf98c 2499 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2500 if (msr) {
2501 msr->data = data;
2225fd56
AK		 2502 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2503 preempt_disable();
9ee73970
AK		 2504 kvm_set_shared_msr(msr->index, msr->data,
2505 msr->mask);
2225fd56
AK		 2506 preempt_enable();
2507 }
3bab1f5d 2508 break;
6aa8b732 2509 }
8fe8ab46 2510 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2511 }
2512
2cc51560 2513 return ret;
6aa8b732
AK		 2514}
2515
5fdbf976 2516static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2517{
5fdbf976
MT		 2518 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2519 switch (reg) {
2520 case VCPU_REGS_RSP:
2521 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2522 break;
2523 case VCPU_REGS_RIP:
2524 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2525 break;
6de4f3ad
AK		 2526 case VCPU_EXREG_PDPTR:
2527 if (enable_ept)
2528 ept_save_pdptrs(vcpu);
2529 break;
5fdbf976
MT		 2530 default:
2531 break;
2532 }
6aa8b732
AK		 2533}
2534
6aa8b732
AK		 2535static __init int cpu_has_kvm_support(void)
2536{
6210e37b 2537 return cpu_has_vmx();
6aa8b732
AK		 2538}
2539
2540static __init int vmx_disabled_by_bios(void)
2541{
2542 u64 msr;
2543
2544 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2545 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2546 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2547 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2548 && tboot_enabled())
2549 return 1;
23f3e991 2550 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2551 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2552 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2553 && !tboot_enabled()) {
2554 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2555 "activate TXT before enabling KVM\n");
cafd6659 2556 return 1;
f9335afe 2557 }
23f3e991
JC		 2558 /* launched w/o TXT and VMX disabled */
2559 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2560 && !tboot_enabled())
2561 return 1;
cafd6659
SW		 2562 }
2563
2564 return 0;
6aa8b732
AK		 2565}
2566
7725b894
DX		 2567static void kvm_cpu_vmxon(u64 addr)
2568{
2569 asm volatile (ASM_VMX_VMXON_RAX
2570 : : "a"(&addr), "m"(addr)
2571 : "memory", "cc");
2572}
2573
10474ae8 2574static int hardware_enable(void *garbage)
6aa8b732
AK		 2575{
2576 int cpu = raw_smp_processor_id();
2577 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2578 u64 old, test_bits;
6aa8b732 2579
10474ae8
AG		 2580 if (read_cr4() & X86_CR4_VMXE)
2581 return -EBUSY;
2582
d462b819 2583 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2584
2585 /*
2586 * Now we can enable the vmclear operation in kdump
2587 * since the loaded_vmcss_on_cpu list on this cpu
2588 * has been initialized.
2589 *
2590 * Though the cpu is not in VMX operation now, there
2591 * is no problem to enable the vmclear operation
2592 * for the loaded_vmcss_on_cpu list is empty!
2593 */
2594 crash_enable_local_vmclear(cpu);
2595
6aa8b732 2596 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2597
2598 test_bits = FEATURE_CONTROL_LOCKED;
2599 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2600 if (tboot_enabled())
2601 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2602
2603 if ((old & test_bits) != test_bits) {
6aa8b732 2604 /* enable and lock */
cafd6659
SW		 2605 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2606 }
66aee91a 2607 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2608
4610c9cc
DX		 2609 if (vmm_exclusive) {
2610 kvm_cpu_vmxon(phys_addr);
2611 ept_sync_global();
2612 }
10474ae8 2613
357d1226 2614 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2615
10474ae8 2616 return 0;
6aa8b732
AK		 2617}
2618
d462b819 2619static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2620{
2621 int cpu = raw_smp_processor_id();
d462b819 2622 struct loaded_vmcs *v, *n;
543e4243 2623
d462b819
NHE		 2624 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2625 loaded_vmcss_on_cpu_link)
2626 __loaded_vmcs_clear(v);
543e4243
AK		 2627}
2628
710ff4a8
EH		 2629
2630/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2631 * tricks.
2632 */
2633static void kvm_cpu_vmxoff(void)
6aa8b732 2634{
4ecac3fd 2635 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2636}
2637
710ff4a8
EH		 2638static void hardware_disable(void *garbage)
2639{
4610c9cc 2640 if (vmm_exclusive) {
d462b819 2641 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2642 kvm_cpu_vmxoff();
2643 }
7725b894 2644 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2645}
2646
1c3d14fe 2647static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2648 u32 msr, u32 *result)
1c3d14fe
YS		 2649{
2650 u32 vmx_msr_low, vmx_msr_high;
2651 u32 ctl = ctl_min | ctl_opt;
2652
2653 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2654
2655 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2656 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2657
2658 /* Ensure minimum (required) set of control bits are supported. */
2659 if (ctl_min & ~ctl)
002c7f7c 2660 return -EIO;
1c3d14fe
YS		 2661
2662 *result = ctl;
2663 return 0;
2664}
2665
110312c8
AK		 2666static __init bool allow_1_setting(u32 msr, u32 ctl)
2667{
2668 u32 vmx_msr_low, vmx_msr_high;
2669
2670 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2671 return vmx_msr_high & ctl;
2672}
2673
002c7f7c 2674static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2675{
2676 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2677 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2678 u32 _pin_based_exec_control = 0;
2679 u32 _cpu_based_exec_control = 0;
f78e0e2e 2680 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2681 u32 _vmexit_control = 0;
2682 u32 _vmentry_control = 0;
2683
10166744 2684 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2685#ifdef CONFIG_X86_64
2686 CPU_BASED_CR8_LOAD_EXITING |
2687 CPU_BASED_CR8_STORE_EXITING |
2688#endif
d56f546d
SY		 2689 CPU_BASED_CR3_LOAD_EXITING |
2690 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2691 CPU_BASED_USE_IO_BITMAPS |
2692 CPU_BASED_MOV_DR_EXITING |
a7052897 2693 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2694 CPU_BASED_MWAIT_EXITING |
2695 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2696 CPU_BASED_INVLPG_EXITING |
2697 CPU_BASED_RDPMC_EXITING;
443381a8 2698
f78e0e2e 2699 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2700 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2701 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2702 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2703 &_cpu_based_exec_control) < 0)
002c7f7c 2704 return -EIO;
6e5d865c
YS		 2705#ifdef CONFIG_X86_64
2706 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2707 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2708 ~CPU_BASED_CR8_STORE_EXITING;
2709#endif
f78e0e2e 2710 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2711 min2 = 0;
2712 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2713 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2714 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2715 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2716 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2717 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2718 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2719 SECONDARY_EXEC_RDTSCP |
83d4c286 2720 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2721 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2722 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2723 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2724 if (adjust_vmx_controls(min2, opt2,
2725 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2726 &_cpu_based_2nd_exec_control) < 0)
2727 return -EIO;
2728 }
2729#ifndef CONFIG_X86_64
2730 if (!(_cpu_based_2nd_exec_control &
2731 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2732 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2733#endif
83d4c286
YZ		 2734
2735 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2736 _cpu_based_2nd_exec_control &= ~(
8d14695f 2737 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2738 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2739 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2740
d56f546d 2741 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2742 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2743 enabled */
5fff7d27
GN		 2744 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2745 CPU_BASED_CR3_STORE_EXITING |
2746 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2747 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2748 vmx_capability.ept, vmx_capability.vpid);
2749 }
1c3d14fe
YS		 2750
2751 min = 0;
2752#ifdef CONFIG_X86_64
2753 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2754#endif
a547c6db
YZ		 2755 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2756 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2757 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2758 &_vmexit_control) < 0)
002c7f7c 2759 return -EIO;
1c3d14fe 2760
01e439be
YZ		 2761 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2762 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2763 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2764 &_pin_based_exec_control) < 0)
2765 return -EIO;
2766
2767 if (!(_cpu_based_2nd_exec_control &
2768 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2769 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2770 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2771
468d472f
SY		 2772 min = 0;
2773 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2774 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2775 &_vmentry_control) < 0)
002c7f7c 2776 return -EIO;
6aa8b732 2777
c68876fd 2778 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2779
2780 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2781 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2782 return -EIO;
1c3d14fe
YS		 2783
2784#ifdef CONFIG_X86_64
2785 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2786 if (vmx_msr_high & (1u<<16))
002c7f7c 2787 return -EIO;
1c3d14fe
YS		 2788#endif
2789
2790 /* Require Write-Back (WB) memory type for VMCS accesses. */
2791 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2792 return -EIO;
1c3d14fe 2793
002c7f7c
YS		 2794 vmcs_conf->size = vmx_msr_high & 0x1fff;
2795 vmcs_conf->order = get_order(vmcs_config.size);
2796 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2797
002c7f7c
YS		 2798 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2799 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2800 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2801 vmcs_conf->vmexit_ctrl = _vmexit_control;
2802 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2803
110312c8
AK		 2804 cpu_has_load_ia32_efer =
2805 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2806 VM_ENTRY_LOAD_IA32_EFER)
2807 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2808 VM_EXIT_LOAD_IA32_EFER);
2809
8bf00a52
GN		 2810 cpu_has_load_perf_global_ctrl =
2811 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2812 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2813 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2814 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2815
2816 /*
2817 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2818 * but due to arrata below it can't be used. Workaround is to use
2819 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2820 *
2821 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2822 *
2823 * AAK155 (model 26)
2824 * AAP115 (model 30)
2825 * AAT100 (model 37)
2826 * BC86,AAY89,BD102 (model 44)
2827 * BA97 (model 46)
2828 *
2829 */
2830 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2831 switch (boot_cpu_data.x86_model) {
2832 case 26:
2833 case 30:
2834 case 37:
2835 case 44:
2836 case 46:
2837 cpu_has_load_perf_global_ctrl = false;
2838 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2839 "does not work properly. Using workaround\n");
2840 break;
2841 default:
2842 break;
2843 }
2844 }
2845
1c3d14fe 2846 return 0;
c68876fd 2847}
6aa8b732
AK		 2848
2849static struct vmcs *alloc_vmcs_cpu(int cpu)
2850{
2851 int node = cpu_to_node(cpu);
2852 struct page *pages;
2853 struct vmcs *vmcs;
2854
6484eb3e 2855 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2856 if (!pages)
2857 return NULL;
2858 vmcs = page_address(pages);
1c3d14fe
YS		 2859 memset(vmcs, 0, vmcs_config.size);
2860 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2861 return vmcs;
2862}
2863
2864static struct vmcs *alloc_vmcs(void)
2865{
d3b2c338 2866 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2867}
2868
2869static void free_vmcs(struct vmcs *vmcs)
2870{
1c3d14fe 2871 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2872}
2873
d462b819
NHE		 2874/*
2875 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2876 */
2877static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2878{
2879 if (!loaded_vmcs->vmcs)
2880 return;
2881 loaded_vmcs_clear(loaded_vmcs);
2882 free_vmcs(loaded_vmcs->vmcs);
2883 loaded_vmcs->vmcs = NULL;
2884}
2885
39959588 2886static void free_kvm_area(void)
6aa8b732
AK		 2887{
2888 int cpu;
2889
3230bb47 2890 for_each_possible_cpu(cpu) {
6aa8b732 2891 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2892 per_cpu(vmxarea, cpu) = NULL;
2893 }
6aa8b732
AK		 2894}
2895
6aa8b732
AK		 2896static __init int alloc_kvm_area(void)
2897{
2898 int cpu;
2899
3230bb47 2900 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2901 struct vmcs *vmcs;
2902
2903 vmcs = alloc_vmcs_cpu(cpu);
2904 if (!vmcs) {
2905 free_kvm_area();
2906 return -ENOMEM;
2907 }
2908
2909 per_cpu(vmxarea, cpu) = vmcs;
2910 }
2911 return 0;
2912}
2913
2914static __init int hardware_setup(void)
2915{
002c7f7c
YS		 2916 if (setup_vmcs_config(&vmcs_config) < 0)
2917 return -EIO;
50a37eb4
JR		 2918
2919 if (boot_cpu_has(X86_FEATURE_NX))
2920 kvm_enable_efer_bits(EFER_NX);
2921
93ba03c2
SY		 2922 if (!cpu_has_vmx_vpid())
2923 enable_vpid = 0;
abc4fc58
AG		 2924 if (!cpu_has_vmx_shadow_vmcs())
2925 enable_shadow_vmcs = 0;
93ba03c2 2926
4bc9b982
SY		 2927 if (!cpu_has_vmx_ept() ||
2928 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2929 enable_ept = 0;
3a624e29 2930 enable_unrestricted_guest = 0;
83c3a331 2931 enable_ept_ad_bits = 0;
3a624e29
NK		 2932 }
2933
83c3a331
XH		 2934 if (!cpu_has_vmx_ept_ad_bits())
2935 enable_ept_ad_bits = 0;
2936
3a624e29
NK		 2937 if (!cpu_has_vmx_unrestricted_guest())
2938 enable_unrestricted_guest = 0;
93ba03c2
SY		 2939
2940 if (!cpu_has_vmx_flexpriority())
2941 flexpriority_enabled = 0;
2942
95ba8273
GN		 2943 if (!cpu_has_vmx_tpr_shadow())
2944 kvm_x86_ops->update_cr8_intercept = NULL;
2945
54dee993
MT		 2946 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2947 kvm_disable_largepages();
2948
4b8d54f9
ZE		 2949 if (!cpu_has_vmx_ple())
2950 ple_gap = 0;
2951
01e439be
YZ		 2952 if (!cpu_has_vmx_apicv())
2953 enable_apicv = 0;
c7c9c56c 2954
01e439be 2955 if (enable_apicv)
c7c9c56c 2956 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2957 else {
c7c9c56c 2958 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2959 kvm_x86_ops->deliver_posted_interrupt = NULL;
2960 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2961 }
83d4c286 2962
b87a51ae
NHE		 2963 if (nested)
2964 nested_vmx_setup_ctls_msrs();
2965
6aa8b732
AK		 2966 return alloc_kvm_area();
2967}
2968
2969static __exit void hardware_unsetup(void)
2970{
2971 free_kvm_area();
2972}
2973
14168786
GN		 2974static bool emulation_required(struct kvm_vcpu *vcpu)
2975{
2976 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2977}
2978
91b0aa2c 2979static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2980 struct kvm_segment *save)
6aa8b732 2981{
d99e4152
GN		 2982 if (!emulate_invalid_guest_state) {
2983 /*
2984 * CS and SS RPL should be equal during guest entry according
2985 * to VMX spec, but in reality it is not always so. Since vcpu
2986 * is in the middle of the transition from real mode to
2987 * protected mode it is safe to assume that RPL 0 is a good
2988 * default value.
2989 */
2990 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2991 save->selector &= ~SELECTOR_RPL_MASK;
2992 save->dpl = save->selector & SELECTOR_RPL_MASK;
2993 save->s = 1;
6aa8b732 2994 }
d99e4152 2995 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2996}
2997
2998static void enter_pmode(struct kvm_vcpu *vcpu)
2999{
3000 unsigned long flags;
a89a8fb9 3001 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3002
d99e4152
GN		 3003 /*
3004 * Update real mode segment cache. It may be not up-to-date if sement
3005 * register was written while vcpu was in a guest mode.
3006 */
3007 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3008 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3009 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3010 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3011 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3012 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3013
7ffd92c5 3014 vmx->rmode.vm86_active = 0;
6aa8b732 3015
2fb92db1
AK		 3016 vmx_segment_cache_clear(vmx);
3017
f5f7b2fe 3018 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3019
3020 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3021 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3022 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3023 vmcs_writel(GUEST_RFLAGS, flags);
3024
66aee91a
RR		 3025 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3026 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3027
3028 update_exception_bitmap(vcpu);
3029
91b0aa2c
GN		 3030 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3031 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3032 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3033 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3034 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3035 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3036
3037 /* CPL is always 0 when CPU enters protected mode */
3038 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3039 vmx->cpl = 0;
6aa8b732
AK		 3040}
3041
f5f7b2fe 3042static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3043{
772e0318 3044 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3045 struct kvm_segment var = *save;
3046
3047 var.dpl = 0x3;
3048 if (seg == VCPU_SREG_CS)
3049 var.type = 0x3;
3050
3051 if (!emulate_invalid_guest_state) {
3052 var.selector = var.base >> 4;
3053 var.base = var.base & 0xffff0;
3054 var.limit = 0xffff;
3055 var.g = 0;
3056 var.db = 0;
3057 var.present = 1;
3058 var.s = 1;
3059 var.l = 0;
3060 var.unusable = 0;
3061 var.type = 0x3;
3062 var.avl = 0;
3063 if (save->base & 0xf)
3064 printk_once(KERN_WARNING "kvm: segment base is not "
3065 "paragraph aligned when entering "
3066 "protected mode (seg=%d)", seg);
3067 }
6aa8b732 3068
d99e4152
GN		 3069 vmcs_write16(sf->selector, var.selector);
3070 vmcs_write32(sf->base, var.base);
3071 vmcs_write32(sf->limit, var.limit);
3072 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3073}
3074
3075static void enter_rmode(struct kvm_vcpu *vcpu)
3076{
3077 unsigned long flags;
a89a8fb9 3078 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3079
f5f7b2fe
AK		 3080 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3081 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3082 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3083 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3084 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3085 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3086 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3087
7ffd92c5 3088 vmx->rmode.vm86_active = 1;
6aa8b732 3089
776e58ea
GN		 3090 /*
3091 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3092 * vcpu. Warn the user that an update is overdue.
776e58ea 3093 */
4918c6ca 3094 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3095 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3096 "called before entering vcpu\n");
776e58ea 3097
2fb92db1
AK		 3098 vmx_segment_cache_clear(vmx);
3099
4918c6ca 3100 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3101 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3102 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3103
3104 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3105 vmx->rmode.save_rflags = flags;
6aa8b732 3106
053de044 3107 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3108
3109 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3110 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3111 update_exception_bitmap(vcpu);
3112
d99e4152
GN		 3113 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3114 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3115 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3116 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3117 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3118 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3119
8668a3c4 3120 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3121}
3122
401d10de
AS		 3123static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3124{
3125 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3126 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3127
3128 if (!msr)
3129 return;
401d10de 3130
44ea2b17
AK		 3131 /*
3132 * Force kernel_gs_base reloading before EFER changes, as control
3133 * of this msr depends on is_long_mode().
3134 */
3135 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3136 vcpu->arch.efer = efer;
401d10de
AS		 3137 if (efer & EFER_LMA) {
3138 vmcs_write32(VM_ENTRY_CONTROLS,
3139 vmcs_read32(VM_ENTRY_CONTROLS) |
3140 VM_ENTRY_IA32E_MODE);
3141 msr->data = efer;
3142 } else {
3143 vmcs_write32(VM_ENTRY_CONTROLS,
3144 vmcs_read32(VM_ENTRY_CONTROLS) &
3145 ~VM_ENTRY_IA32E_MODE);
3146
3147 msr->data = efer & ~EFER_LME;
3148 }
3149 setup_msrs(vmx);
3150}
3151
05b3e0c2 3152#ifdef CONFIG_X86_64
6aa8b732
AK		 3153
3154static void enter_lmode(struct kvm_vcpu *vcpu)
3155{
3156 u32 guest_tr_ar;
3157
2fb92db1
AK		 3158 vmx_segment_cache_clear(to_vmx(vcpu));
3159
6aa8b732
AK		 3160 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3161 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3162 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3163 __func__);
6aa8b732
AK		 3164 vmcs_write32(GUEST_TR_AR_BYTES,
3165 (guest_tr_ar & ~AR_TYPE_MASK)
3166 | AR_TYPE_BUSY_64_TSS);
3167 }
da38f438 3168 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3169}
3170
3171static void exit_lmode(struct kvm_vcpu *vcpu)
3172{
6aa8b732
AK		 3173 vmcs_write32(VM_ENTRY_CONTROLS,
3174 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3175 & ~VM_ENTRY_IA32E_MODE);
da38f438 3176 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3177}
3178
3179#endif
3180
2384d2b3
SY		 3181static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3182{
b9d762fa 3183 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3184 if (enable_ept) {
3185 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3186 return;
4e1096d2 3187 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3188 }
2384d2b3
SY		 3189}
3190
e8467fda
AK		 3191static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3192{
3193 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3194
3195 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3196 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3197}
3198
aff48baa
AK		 3199static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3200{
3201 if (enable_ept && is_paging(vcpu))
3202 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3203 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3204}
3205
25c4c276 3206static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3207{
fc78f519
AK		 3208 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3209
3210 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3211 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3212}
3213
1439442c
SY		 3214static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3215{
6de4f3ad
AK		 3216 if (!test_bit(VCPU_EXREG_PDPTR,
3217 (unsigned long *)&vcpu->arch.regs_dirty))
3218 return;
3219
1439442c 3220 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3221 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3222 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3223 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3224 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3225 }
3226}
3227
8f5d549f
AK		 3228static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3229{
3230 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3231 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3232 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3233 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3234 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3235 }
6de4f3ad
AK		 3236
3237 __set_bit(VCPU_EXREG_PDPTR,
3238 (unsigned long *)&vcpu->arch.regs_avail);
3239 __set_bit(VCPU_EXREG_PDPTR,
3240 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3241}
3242
5e1746d6 3243static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3244
3245static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3246 unsigned long cr0,
3247 struct kvm_vcpu *vcpu)
3248{
5233dd51
MT		 3249 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3250 vmx_decache_cr3(vcpu);
1439442c
SY		 3251 if (!(cr0 & X86_CR0_PG)) {
3252 /* From paging/starting to nonpaging */
3253 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3254 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3255 (CPU_BASED_CR3_LOAD_EXITING |
3256 CPU_BASED_CR3_STORE_EXITING));
3257 vcpu->arch.cr0 = cr0;
fc78f519 3258 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3259 } else if (!is_paging(vcpu)) {
3260 /* From nonpaging to paging */
3261 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3262 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3263 ~(CPU_BASED_CR3_LOAD_EXITING |
3264 CPU_BASED_CR3_STORE_EXITING));
3265 vcpu->arch.cr0 = cr0;
fc78f519 3266 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3267 }
95eb84a7
SY		 3268
3269 if (!(cr0 & X86_CR0_WP))
3270 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3271}
3272
6aa8b732
AK		 3273static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3274{
7ffd92c5 3275 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3276 unsigned long hw_cr0;
3277
5037878e 3278 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3279 if (enable_unrestricted_guest)
5037878e 3280 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3281 else {
5037878e 3282 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3283
218e763f
GN		 3284 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3285 enter_pmode(vcpu);
6aa8b732 3286
218e763f
GN		 3287 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3288 enter_rmode(vcpu);
3289 }
6aa8b732 3290
05b3e0c2 3291#ifdef CONFIG_X86_64
f6801dff 3292 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3293 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3294 enter_lmode(vcpu);
707d92fa 3295 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3296 exit_lmode(vcpu);
3297 }
3298#endif
3299
089d034e 3300 if (enable_ept)
1439442c
SY		 3301 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3302
02daab21 3303 if (!vcpu->fpu_active)
81231c69 3304 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3305
6aa8b732 3306 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3307 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3308 vcpu->arch.cr0 = cr0;
14168786
GN		 3309
3310 /* depends on vcpu->arch.cr0 to be set to a new value */
3311 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3312}
3313
1439442c
SY		 3314static u64 construct_eptp(unsigned long root_hpa)
3315{
3316 u64 eptp;
3317
3318 /* TODO write the value reading from MSR */
3319 eptp = VMX_EPT_DEFAULT_MT |
3320 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3321 if (enable_ept_ad_bits)
3322 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3323 eptp |= (root_hpa & PAGE_MASK);
3324
3325 return eptp;
3326}
3327
6aa8b732
AK		 3328static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3329{
1439442c
SY		 3330 unsigned long guest_cr3;
3331 u64 eptp;
3332
3333 guest_cr3 = cr3;
089d034e 3334 if (enable_ept) {
1439442c
SY		 3335 eptp = construct_eptp(cr3);
3336 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3337 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3338 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3339 ept_load_pdptrs(vcpu);
1439442c
SY		 3340 }
3341
2384d2b3 3342 vmx_flush_tlb(vcpu);
1439442c 3343 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3344}
3345
5e1746d6 3346static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3347{
7ffd92c5 3348 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3349 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3350
5e1746d6
NHE		 3351 if (cr4 & X86_CR4_VMXE) {
3352 /*
3353 * To use VMXON (and later other VMX instructions), a guest
3354 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3355 * So basically the check on whether to allow nested VMX
3356 * is here.
3357 */
3358 if (!nested_vmx_allowed(vcpu))
3359 return 1;
1a0d74e6
JK		 3360 }
3361 if (to_vmx(vcpu)->nested.vmxon &&
3362 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3363 return 1;
3364
ad312c7c 3365 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3366 if (enable_ept) {
3367 if (!is_paging(vcpu)) {
3368 hw_cr4 &= ~X86_CR4_PAE;
3369 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3370 /*
3371 * SMEP is disabled if CPU is in non-paging mode in
3372 * hardware. However KVM always uses paging mode to
3373 * emulate guest non-paging mode with TDP.
3374 * To emulate this behavior, SMEP needs to be manually
3375 * disabled when guest switches to non-paging mode.
3376 */
3377 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3378 } else if (!(cr4 & X86_CR4_PAE)) {
3379 hw_cr4 &= ~X86_CR4_PAE;
3380 }
3381 }
1439442c
SY		 3382
3383 vmcs_writel(CR4_READ_SHADOW, cr4);
3384 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3385 return 0;
6aa8b732
AK		 3386}
3387
6aa8b732
AK		 3388static void vmx_get_segment(struct kvm_vcpu *vcpu,
3389 struct kvm_segment *var, int seg)
3390{
a9179499 3391 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3392 u32 ar;
3393
c6ad1153 3394 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3395 *var = vmx->rmode.segs[seg];
a9179499 3396 if (seg == VCPU_SREG_TR
2fb92db1 3397 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3398 return;
1390a28b
AK		 3399 var->base = vmx_read_guest_seg_base(vmx, seg);
3400 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401 return;
a9179499 3402 }
2fb92db1
AK		 3403 var->base = vmx_read_guest_seg_base(vmx, seg);
3404 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3405 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3406 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3407 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3408 var->type = ar & 15;
3409 var->s = (ar >> 4) & 1;
3410 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3411 /*
3412 * Some userspaces do not preserve unusable property. Since usable
3413 * segment has to be present according to VMX spec we can use present
3414 * property to amend userspace bug by making unusable segment always
3415 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3416 * segment as unusable.
3417 */
3418 var->present = !var->unusable;
6aa8b732
AK		 3419 var->avl = (ar >> 12) & 1;
3420 var->l = (ar >> 13) & 1;
3421 var->db = (ar >> 14) & 1;
3422 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3423}
3424
a9179499
AK		 3425static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3426{
a9179499
AK		 3427 struct kvm_segment s;
3428
3429 if (to_vmx(vcpu)->rmode.vm86_active) {
3430 vmx_get_segment(vcpu, &s, seg);
3431 return s.base;
3432 }
2fb92db1 3433 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3434}
3435
b09408d0 3436static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3437{
b09408d0
MT		 3438 struct vcpu_vmx *vmx = to_vmx(vcpu);
3439
3eeb3288 3440 if (!is_protmode(vcpu))
2e4d2653
IE		 3441 return 0;
3442
f4c63e5d
AK		 3443 if (!is_long_mode(vcpu)
3444 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3445 return 3;
3446
69c73028
AK		 3447 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3448 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3449 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3450 }
d881e6f6
AK		 3451
3452 return vmx->cpl;
69c73028
AK		 3453}
3454
3455
653e3108 3456static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3457{
6aa8b732
AK		 3458 u32 ar;
3459
f0495f9b 3460 if (var->unusable || !var->present)
6aa8b732
AK		 3461 ar = 1 << 16;
3462 else {
3463 ar = var->type & 15;
3464 ar |= (var->s & 1) << 4;
3465 ar |= (var->dpl & 3) << 5;
3466 ar |= (var->present & 1) << 7;
3467 ar |= (var->avl & 1) << 12;
3468 ar |= (var->l & 1) << 13;
3469 ar |= (var->db & 1) << 14;
3470 ar |= (var->g & 1) << 15;
3471 }
653e3108
AK		 3472
3473 return ar;
3474}
3475
3476static void vmx_set_segment(struct kvm_vcpu *vcpu,
3477 struct kvm_segment *var, int seg)
3478{
7ffd92c5 3479 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3480 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3481
2fb92db1 3482 vmx_segment_cache_clear(vmx);
2f143240
GN		 3483 if (seg == VCPU_SREG_CS)
3484 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3485
1ecd50a9
GN		 3486 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3487 vmx->rmode.segs[seg] = *var;
3488 if (seg == VCPU_SREG_TR)
3489 vmcs_write16(sf->selector, var->selector);
3490 else if (var->s)
3491 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3492 goto out;
653e3108 3493 }
1ecd50a9 3494
653e3108
AK		 3495 vmcs_writel(sf->base, var->base);
3496 vmcs_write32(sf->limit, var->limit);
3497 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3498
3499 /*
3500 * Fix the "Accessed" bit in AR field of segment registers for older
3501 * qemu binaries.
3502 * IA32 arch specifies that at the time of processor reset the
3503 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3504 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3505 * state vmexit when "unrestricted guest" mode is turned on.
3506 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3507 * tree. Newer qemu binaries with that qemu fix would not need this
3508 * kvm hack.
3509 */
3510 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3511 var->type |= 0x1; /* Accessed */
3a624e29 3512
f924d66d 3513 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3514
3515out:
14168786 3516 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3517}
3518
6aa8b732
AK		 3519static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3520{
2fb92db1 3521 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3522
3523 *db = (ar >> 14) & 1;
3524 *l = (ar >> 13) & 1;
3525}
3526
89a27f4d 3527static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3528{
89a27f4d
GN		 3529 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3530 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3531}
3532
89a27f4d 3533static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3534{
89a27f4d
GN		 3535 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3536 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3537}
3538
89a27f4d 3539static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3540{
89a27f4d
GN		 3541 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3542 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3543}
3544
89a27f4d 3545static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3546{
89a27f4d
GN		 3547 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3548 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3549}
3550
648dfaa7
MG		 3551static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3552{
3553 struct kvm_segment var;
3554 u32 ar;
3555
3556 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3557 var.dpl = 0x3;
0647f4aa
GN		 3558 if (seg == VCPU_SREG_CS)
3559 var.type = 0x3;
648dfaa7
MG		 3560 ar = vmx_segment_access_rights(&var);
3561
3562 if (var.base != (var.selector << 4))
3563 return false;
89efbed0 3564 if (var.limit != 0xffff)
648dfaa7 3565 return false;
07f42f5f 3566 if (ar != 0xf3)
648dfaa7
MG		 3567 return false;
3568
3569 return true;
3570}
3571
3572static bool code_segment_valid(struct kvm_vcpu *vcpu)
3573{
3574 struct kvm_segment cs;
3575 unsigned int cs_rpl;
3576
3577 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3578 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3579
1872a3f4
AK		 3580 if (cs.unusable)
3581 return false;
648dfaa7
MG		 3582 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3583 return false;
3584 if (!cs.s)
3585 return false;
1872a3f4 3586 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3587 if (cs.dpl > cs_rpl)
3588 return false;
1872a3f4 3589 } else {
648dfaa7
MG		 3590 if (cs.dpl != cs_rpl)
3591 return false;
3592 }
3593 if (!cs.present)
3594 return false;
3595
3596 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3597 return true;
3598}
3599
3600static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3601{
3602 struct kvm_segment ss;
3603 unsigned int ss_rpl;
3604
3605 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3606 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3607
1872a3f4
AK		 3608 if (ss.unusable)
3609 return true;
3610 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3611 return false;
3612 if (!ss.s)
3613 return false;
3614 if (ss.dpl != ss_rpl) /* DPL != RPL */
3615 return false;
3616 if (!ss.present)
3617 return false;
3618
3619 return true;
3620}
3621
3622static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3623{
3624 struct kvm_segment var;
3625 unsigned int rpl;
3626
3627 vmx_get_segment(vcpu, &var, seg);
3628 rpl = var.selector & SELECTOR_RPL_MASK;
3629
1872a3f4
AK		 3630 if (var.unusable)
3631 return true;
648dfaa7
MG		 3632 if (!var.s)
3633 return false;
3634 if (!var.present)
3635 return false;
3636 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3637 if (var.dpl < rpl) /* DPL < RPL */
3638 return false;
3639 }
3640
3641 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3642 * rights flags
3643 */
3644 return true;
3645}
3646
3647static bool tr_valid(struct kvm_vcpu *vcpu)
3648{
3649 struct kvm_segment tr;
3650
3651 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3652
1872a3f4
AK		 3653 if (tr.unusable)
3654 return false;
648dfaa7
MG		 3655 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3656 return false;
1872a3f4 3657 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3658 return false;
3659 if (!tr.present)
3660 return false;
3661
3662 return true;
3663}
3664
3665static bool ldtr_valid(struct kvm_vcpu *vcpu)
3666{
3667 struct kvm_segment ldtr;
3668
3669 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3670
1872a3f4
AK		 3671 if (ldtr.unusable)
3672 return true;
648dfaa7
MG		 3673 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3674 return false;
3675 if (ldtr.type != 2)
3676 return false;
3677 if (!ldtr.present)
3678 return false;
3679
3680 return true;
3681}
3682
3683static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3684{
3685 struct kvm_segment cs, ss;
3686
3687 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3688 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3689
3690 return ((cs.selector & SELECTOR_RPL_MASK) ==
3691 (ss.selector & SELECTOR_RPL_MASK));
3692}
3693
3694/*
3695 * Check if guest state is valid. Returns true if valid, false if
3696 * not.
3697 * We assume that registers are always usable
3698 */
3699static bool guest_state_valid(struct kvm_vcpu *vcpu)
3700{
c5e97c80
GN		 3701 if (enable_unrestricted_guest)
3702 return true;
3703
648dfaa7 3704 /* real mode guest state checks */
f13882d8 3705 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3706 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3707 return false;
3708 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3709 return false;
3710 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3711 return false;
3712 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3713 return false;
3714 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3715 return false;
3716 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3717 return false;
3718 } else {
3719 /* protected mode guest state checks */
3720 if (!cs_ss_rpl_check(vcpu))
3721 return false;
3722 if (!code_segment_valid(vcpu))
3723 return false;
3724 if (!stack_segment_valid(vcpu))
3725 return false;
3726 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3727 return false;
3728 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3729 return false;
3730 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3731 return false;
3732 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3733 return false;
3734 if (!tr_valid(vcpu))
3735 return false;
3736 if (!ldtr_valid(vcpu))
3737 return false;
3738 }
3739 /* TODO:
3740 * - Add checks on RIP
3741 * - Add checks on RFLAGS
3742 */
3743
3744 return true;
3745}
3746
d77c26fc 3747static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3748{
40dcaa9f 3749 gfn_t fn;
195aefde 3750 u16 data = 0;
40dcaa9f 3751 int r, idx, ret = 0;
6aa8b732 3752
40dcaa9f 3753 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3754 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3755 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3756 if (r < 0)
10589a46 3757 goto out;
195aefde 3758 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3759 r = kvm_write_guest_page(kvm, fn++, &data,
3760 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3761 if (r < 0)
10589a46 3762 goto out;
195aefde
IE		 3763 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3764 if (r < 0)
10589a46 3765 goto out;
195aefde
IE		 3766 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3767 if (r < 0)
10589a46 3768 goto out;
195aefde 3769 data = ~0;
10589a46
MT		 3770 r = kvm_write_guest_page(kvm, fn, &data,
3771 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3772 sizeof(u8));
195aefde 3773 if (r < 0)
10589a46
MT		 3774 goto out;
3775
3776 ret = 1;
3777out:
40dcaa9f 3778 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3779 return ret;
6aa8b732
AK		 3780}
3781
b7ebfb05
SY		 3782static int init_rmode_identity_map(struct kvm *kvm)
3783{
40dcaa9f 3784 int i, idx, r, ret;
b7ebfb05
SY		 3785 pfn_t identity_map_pfn;
3786 u32 tmp;
3787
089d034e 3788 if (!enable_ept)
b7ebfb05
SY		 3789 return 1;
3790 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3791 printk(KERN_ERR "EPT: identity-mapping pagetable "
3792 "haven't been allocated!\n");
3793 return 0;
3794 }
3795 if (likely(kvm->arch.ept_identity_pagetable_done))
3796 return 1;
3797 ret = 0;
b927a3ce 3798 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3799 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3800 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3801 if (r < 0)
3802 goto out;
3803 /* Set up identity-mapping pagetable for EPT in real mode */
3804 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3805 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3806 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3807 r = kvm_write_guest_page(kvm, identity_map_pfn,
3808 &tmp, i * sizeof(tmp), sizeof(tmp));
3809 if (r < 0)
3810 goto out;
3811 }
3812 kvm->arch.ept_identity_pagetable_done = true;
3813 ret = 1;
3814out:
40dcaa9f 3815 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3816 return ret;
3817}
3818
6aa8b732
AK		 3819static void seg_setup(int seg)
3820{
772e0318 3821 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3822 unsigned int ar;
6aa8b732
AK		 3823
3824 vmcs_write16(sf->selector, 0);
3825 vmcs_writel(sf->base, 0);
3826 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3827 ar = 0x93;
3828 if (seg == VCPU_SREG_CS)
3829 ar |= 0x08; /* code segment */
3a624e29
NK		 3830
3831 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3832}
3833
f78e0e2e
SY		 3834static int alloc_apic_access_page(struct kvm *kvm)
3835{
4484141a 3836 struct page *page;
f78e0e2e
SY		 3837 struct kvm_userspace_memory_region kvm_userspace_mem;
3838 int r = 0;
3839
79fac95e 3840 mutex_lock(&kvm->slots_lock);
bfc6d222 3841 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3842 goto out;
3843 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3844 kvm_userspace_mem.flags = 0;
3845 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3846 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3847 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3848 if (r)
3849 goto out;
72dc67a6 3850
4484141a
XG		 3851 page = gfn_to_page(kvm, 0xfee00);
3852 if (is_error_page(page)) {
3853 r = -EFAULT;
3854 goto out;
3855 }
3856
3857 kvm->arch.apic_access_page = page;
f78e0e2e 3858out:
79fac95e 3859 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3860 return r;
3861}
3862
b7ebfb05
SY		 3863static int alloc_identity_pagetable(struct kvm *kvm)
3864{
4484141a 3865 struct page *page;
b7ebfb05
SY		 3866 struct kvm_userspace_memory_region kvm_userspace_mem;
3867 int r = 0;
3868
79fac95e 3869 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3870 if (kvm->arch.ept_identity_pagetable)
3871 goto out;
3872 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3873 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3874 kvm_userspace_mem.guest_phys_addr =
3875 kvm->arch.ept_identity_map_addr;
b7ebfb05 3876 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3877 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3878 if (r)
3879 goto out;
3880
4484141a
XG		 3881 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3882 if (is_error_page(page)) {
3883 r = -EFAULT;
3884 goto out;
3885 }
3886
3887 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3888out:
79fac95e 3889 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3890 return r;
3891}
3892
2384d2b3
SY		 3893static void allocate_vpid(struct vcpu_vmx *vmx)
3894{
3895 int vpid;
3896
3897 vmx->vpid = 0;
919818ab 3898 if (!enable_vpid)
2384d2b3
SY		 3899 return;
3900 spin_lock(&vmx_vpid_lock);
3901 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3902 if (vpid < VMX_NR_VPIDS) {
3903 vmx->vpid = vpid;
3904 __set_bit(vpid, vmx_vpid_bitmap);
3905 }
3906 spin_unlock(&vmx_vpid_lock);
3907}
3908
cdbecfc3
LJ		 3909static void free_vpid(struct vcpu_vmx *vmx)
3910{
3911 if (!enable_vpid)
3912 return;
3913 spin_lock(&vmx_vpid_lock);
3914 if (vmx->vpid != 0)
3915 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3916 spin_unlock(&vmx_vpid_lock);
3917}
3918
8d14695f
YZ		 3919#define MSR_TYPE_R 1
3920#define MSR_TYPE_W 2
3921static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3922 u32 msr, int type)
25c5f225 3923{
3e7c73e9 3924 int f = sizeof(unsigned long);
25c5f225
SY		 3925
3926 if (!cpu_has_vmx_msr_bitmap())
3927 return;
3928
3929 /*
3930 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3931 * have the write-low and read-high bitmap offsets the wrong way round.
3932 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3933 */
25c5f225 3934 if (msr <= 0x1fff) {
8d14695f
YZ		 3935 if (type & MSR_TYPE_R)
3936 /* read-low */
3937 __clear_bit(msr, msr_bitmap + 0x000 / f);
3938
3939 if (type & MSR_TYPE_W)
3940 /* write-low */
3941 __clear_bit(msr, msr_bitmap + 0x800 / f);
3942
25c5f225
SY		 3943 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3944 msr &= 0x1fff;
8d14695f
YZ		 3945 if (type & MSR_TYPE_R)
3946 /* read-high */
3947 __clear_bit(msr, msr_bitmap + 0x400 / f);
3948
3949 if (type & MSR_TYPE_W)
3950 /* write-high */
3951 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3952
3953 }
3954}
3955
3956static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3957 u32 msr, int type)
3958{
3959 int f = sizeof(unsigned long);
3960
3961 if (!cpu_has_vmx_msr_bitmap())
3962 return;
3963
3964 /*
3965 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3966 * have the write-low and read-high bitmap offsets the wrong way round.
3967 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3968 */
3969 if (msr <= 0x1fff) {
3970 if (type & MSR_TYPE_R)
3971 /* read-low */
3972 __set_bit(msr, msr_bitmap + 0x000 / f);
3973
3974 if (type & MSR_TYPE_W)
3975 /* write-low */
3976 __set_bit(msr, msr_bitmap + 0x800 / f);
3977
3978 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3979 msr &= 0x1fff;
3980 if (type & MSR_TYPE_R)
3981 /* read-high */
3982 __set_bit(msr, msr_bitmap + 0x400 / f);
3983
3984 if (type & MSR_TYPE_W)
3985 /* write-high */
3986 __set_bit(msr, msr_bitmap + 0xc00 / f);
3987
25c5f225 3988 }
25c5f225
SY		 3989}
3990
5897297b
AK		 3991static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3992{
3993 if (!longmode_only)
8d14695f
YZ		 3994 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3995 msr, MSR_TYPE_R | MSR_TYPE_W);
3996 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3997 msr, MSR_TYPE_R | MSR_TYPE_W);
3998}
3999
4000static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4001{
4002 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4003 msr, MSR_TYPE_R);
4004 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4005 msr, MSR_TYPE_R);
4006}
4007
4008static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4009{
4010 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4011 msr, MSR_TYPE_R);
4012 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4013 msr, MSR_TYPE_R);
4014}
4015
4016static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4017{
4018 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4019 msr, MSR_TYPE_W);
4020 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4021 msr, MSR_TYPE_W);
5897297b
AK		 4022}
4023
01e439be
YZ		 4024static int vmx_vm_has_apicv(struct kvm *kvm)
4025{
4026 return enable_apicv && irqchip_in_kernel(kvm);
4027}
4028
a20ed54d
YZ		 4029/*
4030 * Send interrupt to vcpu via posted interrupt way.
4031 * 1. If target vcpu is running(non-root mode), send posted interrupt
4032 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4033 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4034 * interrupt from PIR in next vmentry.
4035 */
4036static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4037{
4038 struct vcpu_vmx *vmx = to_vmx(vcpu);
4039 int r;
4040
4041 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4042 return;
4043
4044 r = pi_test_and_set_on(&vmx->pi_desc);
4045 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4046#ifdef CONFIG_SMP
a20ed54d
YZ		 4047 if (!r && (vcpu->mode == IN_GUEST_MODE))
4048 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4049 POSTED_INTR_VECTOR);
4050 else
6ffbbbba 4051#endif
a20ed54d
YZ		 4052 kvm_vcpu_kick(vcpu);
4053}
4054
4055static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4056{
4057 struct vcpu_vmx *vmx = to_vmx(vcpu);
4058
4059 if (!pi_test_and_clear_on(&vmx->pi_desc))
4060 return;
4061
4062 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4063}
4064
4065static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4066{
4067 return;
4068}
4069
a3a8ff8e
NHE		 4070/*
4071 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4072 * will not change in the lifetime of the guest.
4073 * Note that host-state that does change is set elsewhere. E.g., host-state
4074 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4075 */
a547c6db 4076static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4077{
4078 u32 low32, high32;
4079 unsigned long tmpl;
4080 struct desc_ptr dt;
4081
b1a74bf8 4082 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4083 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4084 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4085
4086 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4087#ifdef CONFIG_X86_64
4088 /*
4089 * Load null selectors, so we can avoid reloading them in
4090 * __vmx_load_host_state(), in case userspace uses the null selectors
4091 * too (the expected case).
4092 */
4093 vmcs_write16(HOST_DS_SELECTOR, 0);
4094 vmcs_write16(HOST_ES_SELECTOR, 0);
4095#else
a3a8ff8e
NHE		 4096 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4097 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4098#endif
a3a8ff8e
NHE		 4099 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4100 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4101
4102 native_store_idt(&dt);
4103 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4104 vmx->host_idt_base = dt.address;
a3a8ff8e 4105
83287ea4 4106 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4107
4108 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4109 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4110 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4111 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4112
4113 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4114 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4115 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4116 }
4117}
4118
bf8179a0
NHE		 4119static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4120{
4121 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4122 if (enable_ept)
4123 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4124 if (is_guest_mode(&vmx->vcpu))
4125 vmx->vcpu.arch.cr4_guest_owned_bits &=
4126 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4127 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4128}
4129
01e439be
YZ		 4130static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4131{
4132 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4133
4134 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4135 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4136 return pin_based_exec_ctrl;
4137}
4138
bf8179a0
NHE		 4139static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4140{
4141 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4142 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4143 exec_control &= ~CPU_BASED_TPR_SHADOW;
4144#ifdef CONFIG_X86_64
4145 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4146 CPU_BASED_CR8_LOAD_EXITING;
4147#endif
4148 }
4149 if (!enable_ept)
4150 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4151 CPU_BASED_CR3_LOAD_EXITING |
4152 CPU_BASED_INVLPG_EXITING;
4153 return exec_control;
4154}
4155
4156static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4157{
4158 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4159 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4160 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4161 if (vmx->vpid == 0)
4162 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4163 if (!enable_ept) {
4164 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4165 enable_unrestricted_guest = 0;
ad756a16
MJ		 4166 /* Enable INVPCID for non-ept guests may cause performance regression. */
4167 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4168 }
4169 if (!enable_unrestricted_guest)
4170 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4171 if (!ple_gap)
4172 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4173 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4174 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4175 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4176 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4177 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4178 (handle_vmptrld).
4179 We can NOT enable shadow_vmcs here because we don't have yet
4180 a current VMCS12
4181 */
4182 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4183 return exec_control;
4184}
4185
ce88decf
XG		 4186static void ept_set_mmio_spte_mask(void)
4187{
4188 /*
4189 * EPT Misconfigurations can be generated if the value of bits 2:0
4190 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4191 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4192 * spte.
4193 */
885032b9 4194 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4195}
4196
6aa8b732
AK		 4197/*
4198 * Sets up the vmcs for emulated real mode.
4199 */
8b9cf98c 4200static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4201{
2e4ce7f5 4202#ifdef CONFIG_X86_64
6aa8b732 4203 unsigned long a;
2e4ce7f5 4204#endif
6aa8b732 4205 int i;
6aa8b732 4206
6aa8b732 4207 /* I/O */
3e7c73e9
AK		 4208 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4209 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4210
4607c2d7
AG		 4211 if (enable_shadow_vmcs) {
4212 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4213 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4214 }
25c5f225 4215 if (cpu_has_vmx_msr_bitmap())
5897297b 4216 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4217
6aa8b732
AK		 4218 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4219
6aa8b732 4220 /* Control */
01e439be 4221 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4222
bf8179a0 4223 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4224
83ff3b9d 4225 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4226 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4227 vmx_secondary_exec_control(vmx));
83ff3b9d 4228 }
f78e0e2e 4229
01e439be 4230 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4231 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4232 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4233 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4234 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4235
4236 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4237
4238 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4239 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4240 }
4241
4b8d54f9
ZE		 4242 if (ple_gap) {
4243 vmcs_write32(PLE_GAP, ple_gap);
4244 vmcs_write32(PLE_WINDOW, ple_window);
4245 }
4246
c3707958
XG		 4247 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4248 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4249 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4250
9581d442
AK		 4251 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4252 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4253 vmx_set_constant_host_state(vmx);
05b3e0c2 4254#ifdef CONFIG_X86_64
6aa8b732
AK		 4255 rdmsrl(MSR_FS_BASE, a);
4256 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4257 rdmsrl(MSR_GS_BASE, a);
4258 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4259#else
4260 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4261 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4262#endif
4263
2cc51560
ED		 4264 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4265 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4266 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4267 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4268 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4269
468d472f 4270 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4271 u32 msr_low, msr_high;
4272 u64 host_pat;
468d472f
SY		 4273 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4274 host_pat = msr_low | ((u64) msr_high << 32);
4275 /* Write the default value follow host pat */
4276 vmcs_write64(GUEST_IA32_PAT, host_pat);
4277 /* Keep arch.pat sync with GUEST_IA32_PAT */
4278 vmx->vcpu.arch.pat = host_pat;
4279 }
4280
6aa8b732
AK		 4281 for (i = 0; i < NR_VMX_MSR; ++i) {
4282 u32 index = vmx_msr_index[i];
4283 u32 data_low, data_high;
a2fa3e9f 4284 int j = vmx->nmsrs;
6aa8b732
AK		 4285
4286 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4287 continue;
432bd6cb
AK		 4288 if (wrmsr_safe(index, data_low, data_high) < 0)
4289 continue;
26bb0981
AK		 4290 vmx->guest_msrs[j].index = i;
4291 vmx->guest_msrs[j].data = 0;
d5696725 4292 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4293 ++vmx->nmsrs;
6aa8b732 4294 }
6aa8b732 4295
1c3d14fe 4296 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4297
4298 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4299 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4300
e00c8cf2 4301 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4302 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4303
4304 return 0;
4305}
4306
57f252f2 4307static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4308{
4309 struct vcpu_vmx *vmx = to_vmx(vcpu);
4310 u64 msr;
e00c8cf2 4311
7ffd92c5 4312 vmx->rmode.vm86_active = 0;
e00c8cf2 4313
3b86cd99
JK		 4314 vmx->soft_vnmi_blocked = 0;
4315
ad312c7c 4316 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4317 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4318 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4319 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4320 msr |= MSR_IA32_APICBASE_BSP;
4321 kvm_set_apic_base(&vmx->vcpu, msr);
4322
2fb92db1
AK		 4323 vmx_segment_cache_clear(vmx);
4324
5706be0d 4325 seg_setup(VCPU_SREG_CS);
66450a21 4326 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4327 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4328
4329 seg_setup(VCPU_SREG_DS);
4330 seg_setup(VCPU_SREG_ES);
4331 seg_setup(VCPU_SREG_FS);
4332 seg_setup(VCPU_SREG_GS);
4333 seg_setup(VCPU_SREG_SS);
4334
4335 vmcs_write16(GUEST_TR_SELECTOR, 0);
4336 vmcs_writel(GUEST_TR_BASE, 0);
4337 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4338 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4339
4340 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4341 vmcs_writel(GUEST_LDTR_BASE, 0);
4342 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4343 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4344
4345 vmcs_write32(GUEST_SYSENTER_CS, 0);
4346 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4347 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4348
4349 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4350 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4351
e00c8cf2
AK		 4352 vmcs_writel(GUEST_GDTR_BASE, 0);
4353 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4354
4355 vmcs_writel(GUEST_IDTR_BASE, 0);
4356 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4357
443381a8 4358 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4359 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4360 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4361
e00c8cf2
AK		 4362 /* Special registers */
4363 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4364
4365 setup_msrs(vmx);
4366
6aa8b732
AK		 4367 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4368
f78e0e2e
SY		 4369 if (cpu_has_vmx_tpr_shadow()) {
4370 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4371 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4372 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4373 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4374 vmcs_write32(TPR_THRESHOLD, 0);
4375 }
4376
4377 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4378 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4379 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4380
01e439be
YZ		 4381 if (vmx_vm_has_apicv(vcpu->kvm))
4382 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4383
2384d2b3
SY		 4384 if (vmx->vpid != 0)
4385 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4386
fa40052c 4387 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4388 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4389 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4390 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4391 vmx_fpu_activate(&vmx->vcpu);
4392 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4393
b9d762fa 4394 vpid_sync_context(vmx);
6aa8b732
AK		 4395}
4396
b6f1250e
NHE		 4397/*
4398 * In nested virtualization, check if L1 asked to exit on external interrupts.
4399 * For most existing hypervisors, this will always return true.
4400 */
4401static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4402{
4403 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4404 PIN_BASED_EXT_INTR_MASK;
4405}
4406
ea8ceb83
JK		 4407static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4408{
4409 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4410 PIN_BASED_NMI_EXITING;
4411}
4412
730dca42 4413static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4414{
4415 u32 cpu_based_vm_exec_control;
730dca42
JK		 4416
4417 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4418 /*
4419 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4420 * inject to L1 now because L2 must run. The caller will have
4421 * to make L2 exit right after entry, so we can inject to L1
4422 * more promptly.
b6f1250e 4423 */
730dca42 4424 return -EBUSY;
3b86cd99
JK		 4425
4426 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4427 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4428 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4429 return 0;
3b86cd99
JK		 4430}
4431
03b28f81 4432static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4433{
4434 u32 cpu_based_vm_exec_control;
4435
03b28f81
JK		 4436 if (!cpu_has_virtual_nmis())
4437 return enable_irq_window(vcpu);
4438
4439 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4440 return enable_irq_window(vcpu);
3b86cd99
JK		 4441
4442 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4443 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4444 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4445 return 0;
3b86cd99
JK		 4446}
4447
66fd3f7f 4448static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4449{
9c8cba37 4450 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4451 uint32_t intr;
4452 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4453
229456fc 4454 trace_kvm_inj_virq(irq);
2714d1d3 4455
fa89a817 4456 ++vcpu->stat.irq_injections;
7ffd92c5 4457 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4458 int inc_eip = 0;
4459 if (vcpu->arch.interrupt.soft)
4460 inc_eip = vcpu->arch.event_exit_inst_len;
4461 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4462 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4463 return;
4464 }
66fd3f7f
GN		 4465 intr = irq | INTR_INFO_VALID_MASK;
4466 if (vcpu->arch.interrupt.soft) {
4467 intr |= INTR_TYPE_SOFT_INTR;
4468 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4469 vmx->vcpu.arch.event_exit_inst_len);
4470 } else
4471 intr |= INTR_TYPE_EXT_INTR;
4472 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4473}
4474
f08864b4
SY		 4475static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4476{
66a5a347
JK		 4477 struct vcpu_vmx *vmx = to_vmx(vcpu);
4478
0b6ac343
NHE		 4479 if (is_guest_mode(vcpu))
4480 return;
4481
3b86cd99
JK		 4482 if (!cpu_has_virtual_nmis()) {
4483 /*
4484 * Tracking the NMI-blocked state in software is built upon
4485 * finding the next open IRQ window. This, in turn, depends on
4486 * well-behaving guests: They have to keep IRQs disabled at
4487 * least as long as the NMI handler runs. Otherwise we may
4488 * cause NMI nesting, maybe breaking the guest. But as this is
4489 * highly unlikely, we can live with the residual risk.
4490 */
4491 vmx->soft_vnmi_blocked = 1;
4492 vmx->vnmi_blocked_time = 0;
4493 }
4494
487b391d 4495 ++vcpu->stat.nmi_injections;
9d58b931 4496 vmx->nmi_known_unmasked = false;
7ffd92c5 4497 if (vmx->rmode.vm86_active) {
71f9833b 4498 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4499 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4500 return;
4501 }
f08864b4
SY		 4502 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4503 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4504}
4505
3cfc3092
JK		 4506static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4507{
4508 if (!cpu_has_virtual_nmis())
4509 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4510 if (to_vmx(vcpu)->nmi_known_unmasked)
4511 return false;
c332c83a 4512 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4513}
4514
4515static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4516{
4517 struct vcpu_vmx *vmx = to_vmx(vcpu);
4518
4519 if (!cpu_has_virtual_nmis()) {
4520 if (vmx->soft_vnmi_blocked != masked) {
4521 vmx->soft_vnmi_blocked = masked;
4522 vmx->vnmi_blocked_time = 0;
4523 }
4524 } else {
9d58b931 4525 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4526 if (masked)
4527 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4528 GUEST_INTR_STATE_NMI);
4529 else
4530 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4531 GUEST_INTR_STATE_NMI);
4532 }
4533}
4534
2505dc9f
JK		 4535static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4536{
ea8ceb83
JK		 4537 if (is_guest_mode(vcpu)) {
4538 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4539
4540 if (to_vmx(vcpu)->nested.nested_run_pending)
4541 return 0;
4542 if (nested_exit_on_nmi(vcpu)) {
4543 nested_vmx_vmexit(vcpu);
4544 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4545 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4546 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4547 /*
4548 * The NMI-triggered VM exit counts as injection:
4549 * clear this one and block further NMIs.
4550 */
4551 vcpu->arch.nmi_pending = 0;
4552 vmx_set_nmi_mask(vcpu, true);
4553 return 0;
4554 }
4555 }
4556
2505dc9f
JK		 4557 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4558 return 0;
4559
4560 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4561 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4562 | GUEST_INTR_STATE_NMI));
4563}
4564
78646121
GN		 4565static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4566{
e8457c67 4567 if (is_guest_mode(vcpu)) {
51cfe38e 4568 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4569
4570 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4571 return 0;
e8457c67
JK		 4572 if (nested_exit_on_intr(vcpu)) {
4573 nested_vmx_vmexit(vcpu);
4574 vmcs12->vm_exit_reason =
4575 EXIT_REASON_EXTERNAL_INTERRUPT;
4576 vmcs12->vm_exit_intr_info = 0;
4577 /*
4578 * fall through to normal code, but now in L1, not L2
4579 */
4580 }
b6f1250e
NHE		 4581 }
4582
c4282df9
GN		 4583 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4584 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4585 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4586}
4587
cbc94022
IE		 4588static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4589{
4590 int ret;
4591 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4592 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4593 .guest_phys_addr = addr,
4594 .memory_size = PAGE_SIZE * 3,
4595 .flags = 0,
4596 };
4597
47ae31e2 4598 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4599 if (ret)
4600 return ret;
bfc6d222 4601 kvm->arch.tss_addr = addr;
93ea5388
GN		 4602 if (!init_rmode_tss(kvm))
4603 return -ENOMEM;
4604
cbc94022
IE		 4605 return 0;
4606}
4607
0ca1b4f4 4608static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4609{
77ab6db0 4610 switch (vec) {
77ab6db0 4611 case BP_VECTOR:
c573cd22
JK		 4612 /*
4613 * Update instruction length as we may reinject the exception
4614 * from user space while in guest debugging mode.
4615 */
4616 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4617 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4618 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4619 return false;
4620 /* fall through */
4621 case DB_VECTOR:
4622 if (vcpu->guest_debug &
4623 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4624 return false;
d0bfb940
JK		 4625 /* fall through */
4626 case DE_VECTOR:
77ab6db0
JK		 4627 case OF_VECTOR:
4628 case BR_VECTOR:
4629 case UD_VECTOR:
4630 case DF_VECTOR:
4631 case SS_VECTOR:
4632 case GP_VECTOR:
4633 case MF_VECTOR:
0ca1b4f4
GN		 4634 return true;
4635 break;
77ab6db0 4636 }
0ca1b4f4
GN		 4637 return false;
4638}
4639
4640static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4641 int vec, u32 err_code)
4642{
4643 /*
4644 * Instruction with address size override prefix opcode 0x67
4645 * Cause the #SS fault with 0 error code in VM86 mode.
4646 */
4647 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4648 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4649 if (vcpu->arch.halt_request) {
4650 vcpu->arch.halt_request = 0;
4651 return kvm_emulate_halt(vcpu);
4652 }
4653 return 1;
4654 }
4655 return 0;
4656 }
4657
4658 /*
4659 * Forward all other exceptions that are valid in real mode.
4660 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4661 * the required debugging infrastructure rework.
4662 */
4663 kvm_queue_exception(vcpu, vec);
4664 return 1;
6aa8b732
AK		 4665}
4666
a0861c02
AK		 4667/*
4668 * Trigger machine check on the host. We assume all the MSRs are already set up
4669 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4670 * We pass a fake environment to the machine check handler because we want
4671 * the guest to be always treated like user space, no matter what context
4672 * it used internally.
4673 */
4674static void kvm_machine_check(void)
4675{
4676#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4677 struct pt_regs regs = {
4678 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4679 .flags = X86_EFLAGS_IF,
4680 };
4681
4682 do_machine_check(&regs, 0);
4683#endif
4684}
4685
851ba692 4686static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4687{
4688 /* already handled by vcpu_run */
4689 return 1;
4690}
4691
851ba692 4692static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4693{
1155f76a 4694 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4695 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4696 u32 intr_info, ex_no, error_code;
42dbaa5a 4697 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4698 u32 vect_info;
4699 enum emulation_result er;
4700
1155f76a 4701 vect_info = vmx->idt_vectoring_info;
88786475 4702 intr_info = vmx->exit_intr_info;
6aa8b732 4703
a0861c02 4704 if (is_machine_check(intr_info))
851ba692 4705 return handle_machine_check(vcpu);
a0861c02 4706
e4a41889 4707 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4708 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4709
4710 if (is_no_device(intr_info)) {
5fd86fcf 4711 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4712 return 1;
4713 }
4714
7aa81cc0 4715 if (is_invalid_opcode(intr_info)) {
51d8b661 4716 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4717 if (er != EMULATE_DONE)
7ee5d940 4718 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4719 return 1;
4720 }
4721
6aa8b732 4722 error_code = 0;
2e11384c 4723 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4724 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4725
4726 /*
4727 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4728 * MMIO, it is better to report an internal error.
4729 * See the comments in vmx_handle_exit.
4730 */
4731 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4732 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4733 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4734 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4735 vcpu->run->internal.ndata = 2;
4736 vcpu->run->internal.data[0] = vect_info;
4737 vcpu->run->internal.data[1] = intr_info;
4738 return 0;
4739 }
4740
6aa8b732 4741 if (is_page_fault(intr_info)) {
1439442c 4742 /* EPT won't cause page fault directly */
cf3ace79 4743 BUG_ON(enable_ept);
6aa8b732 4744 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4745 trace_kvm_page_fault(cr2, error_code);
4746
3298b75c 4747 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4748 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4749 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4750 }
4751
d0bfb940 4752 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4753
4754 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4755 return handle_rmode_exception(vcpu, ex_no, error_code);
4756
42dbaa5a
JK		 4757 switch (ex_no) {
4758 case DB_VECTOR:
4759 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4760 if (!(vcpu->guest_debug &
4761 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4762 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4763 kvm_queue_exception(vcpu, DB_VECTOR);
4764 return 1;
4765 }
4766 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4767 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4768 /* fall through */
4769 case BP_VECTOR:
c573cd22
JK		 4770 /*
4771 * Update instruction length as we may reinject #BP from
4772 * user space while in guest debugging mode. Reading it for
4773 * #DB as well causes no harm, it is not used in that case.
4774 */
4775 vmx->vcpu.arch.event_exit_inst_len =
4776 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4777 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4778 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4779 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4780 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4781 break;
4782 default:
d0bfb940
JK		 4783 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4784 kvm_run->ex.exception = ex_no;
4785 kvm_run->ex.error_code = error_code;
42dbaa5a 4786 break;
6aa8b732 4787 }
6aa8b732
AK		 4788 return 0;
4789}
4790
851ba692 4791static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4792{
1165f5fe 4793 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4794 return 1;
4795}
4796
851ba692 4797static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4798{
851ba692 4799 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4800 return 0;
4801}
6aa8b732 4802
851ba692 4803static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4804{
bfdaab09 4805 unsigned long exit_qualification;
34c33d16 4806 int size, in, string;
039576c0 4807 unsigned port;
6aa8b732 4808
bfdaab09 4809 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4810 string = (exit_qualification & 16) != 0;
cf8f70bf 4811 in = (exit_qualification & 8) != 0;
e70669ab 4812
cf8f70bf 4813 ++vcpu->stat.io_exits;
e70669ab 4814
cf8f70bf 4815 if (string || in)
51d8b661 4816 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4817
cf8f70bf
GN		 4818 port = exit_qualification >> 16;
4819 size = (exit_qualification & 7) + 1;
e93f36bc 4820 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4821
4822 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4823}
4824
102d8325
IM		 4825static void
4826vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4827{
4828 /*
4829 * Patch in the VMCALL instruction:
4830 */
4831 hypercall[0] = 0x0f;
4832 hypercall[1] = 0x01;
4833 hypercall[2] = 0xc1;
102d8325
IM		 4834}
4835
0fa06071 4836/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4837static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4838{
eeadf9e7 4839 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4840 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4841 unsigned long orig_val = val;
4842
eeadf9e7
NHE		 4843 /*
4844 * We get here when L2 changed cr0 in a way that did not change
4845 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4846 * but did change L0 shadowed bits. So we first calculate the
4847 * effective cr0 value that L1 would like to write into the
4848 * hardware. It consists of the L2-owned bits from the new
4849 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4850 */
1a0d74e6
JK		 4851 val = (val & ~vmcs12->cr0_guest_host_mask) |
4852 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4853
4854 /* TODO: will have to take unrestricted guest mode into
4855 * account */
4856 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4857 return 1;
1a0d74e6
JK		 4858
4859 if (kvm_set_cr0(vcpu, val))
4860 return 1;
4861 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4862 return 0;
1a0d74e6
JK		 4863 } else {
4864 if (to_vmx(vcpu)->nested.vmxon &&
4865 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4866 return 1;
eeadf9e7 4867 return kvm_set_cr0(vcpu, val);
1a0d74e6 4868 }
eeadf9e7
NHE		 4869}
4870
4871static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4872{
4873 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4874 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4875 unsigned long orig_val = val;
4876
4877 /* analogously to handle_set_cr0 */
4878 val = (val & ~vmcs12->cr4_guest_host_mask) |
4879 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4880 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4881 return 1;
1a0d74e6 4882 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4883 return 0;
4884 } else
4885 return kvm_set_cr4(vcpu, val);
4886}
4887
4888/* called to set cr0 as approriate for clts instruction exit. */
4889static void handle_clts(struct kvm_vcpu *vcpu)
4890{
4891 if (is_guest_mode(vcpu)) {
4892 /*
4893 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4894 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4895 * just pretend it's off (also in arch.cr0 for fpu_activate).
4896 */
4897 vmcs_writel(CR0_READ_SHADOW,
4898 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4899 vcpu->arch.cr0 &= ~X86_CR0_TS;
4900 } else
4901 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4902}
4903
851ba692 4904static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4905{
229456fc 4906 unsigned long exit_qualification, val;
6aa8b732
AK		 4907 int cr;
4908 int reg;
49a9b07e 4909 int err;
6aa8b732 4910
bfdaab09 4911 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4912 cr = exit_qualification & 15;
4913 reg = (exit_qualification >> 8) & 15;
4914 switch ((exit_qualification >> 4) & 3) {
4915 case 0: /* mov to cr */
229456fc
MT		 4916 val = kvm_register_read(vcpu, reg);
4917 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4918 switch (cr) {
4919 case 0:
eeadf9e7 4920 err = handle_set_cr0(vcpu, val);
db8fcefa 4921 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4922 return 1;
4923 case 3:
2390218b 4924 err = kvm_set_cr3(vcpu, val);
db8fcefa 4925 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4926 return 1;
4927 case 4:
eeadf9e7 4928 err = handle_set_cr4(vcpu, val);
db8fcefa 4929 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4930 return 1;
0a5fff19
GN		 4931 case 8: {
4932 u8 cr8_prev = kvm_get_cr8(vcpu);
4933 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4934 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4935 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4936 if (irqchip_in_kernel(vcpu->kvm))
4937 return 1;
4938 if (cr8_prev <= cr8)
4939 return 1;
851ba692 4940 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4941 return 0;
4942 }
4b8073e4 4943 }
6aa8b732 4944 break;
25c4c276 4945 case 2: /* clts */
eeadf9e7 4946 handle_clts(vcpu);
4d4ec087 4947 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4948 skip_emulated_instruction(vcpu);
6b52d186 4949 vmx_fpu_activate(vcpu);
25c4c276 4950 return 1;
6aa8b732
AK		 4951 case 1: /*mov from cr*/
4952 switch (cr) {
4953 case 3:
9f8fe504
AK		 4954 val = kvm_read_cr3(vcpu);
4955 kvm_register_write(vcpu, reg, val);
4956 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4957 skip_emulated_instruction(vcpu);
4958 return 1;
4959 case 8:
229456fc
MT		 4960 val = kvm_get_cr8(vcpu);
4961 kvm_register_write(vcpu, reg, val);
4962 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4963 skip_emulated_instruction(vcpu);
4964 return 1;
4965 }
4966 break;
4967 case 3: /* lmsw */
a1f83a74 4968 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4969 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4970 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4971
4972 skip_emulated_instruction(vcpu);
4973 return 1;
4974 default:
4975 break;
4976 }
851ba692 4977 vcpu->run->exit_reason = 0;
a737f256 4978 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4979 (int)(exit_qualification >> 4) & 3, cr);
4980 return 0;
4981}
4982
851ba692 4983static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4984{
bfdaab09 4985 unsigned long exit_qualification;
6aa8b732
AK		 4986 int dr, reg;
4987
f2483415 4988 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4989 if (!kvm_require_cpl(vcpu, 0))
4990 return 1;
42dbaa5a
JK		 4991 dr = vmcs_readl(GUEST_DR7);
4992 if (dr & DR7_GD) {
4993 /*
4994 * As the vm-exit takes precedence over the debug trap, we
4995 * need to emulate the latter, either for the host or the
4996 * guest debugging itself.
4997 */
4998 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4999 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5000 vcpu->run->debug.arch.dr7 = dr;
5001 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5002 vmcs_readl(GUEST_CS_BASE) +
5003 vmcs_readl(GUEST_RIP);
851ba692
AK		 5004 vcpu->run->debug.arch.exception = DB_VECTOR;
5005 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5006 return 0;
5007 } else {
5008 vcpu->arch.dr7 &= ~DR7_GD;
5009 vcpu->arch.dr6 |= DR6_BD;
5010 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5011 kvm_queue_exception(vcpu, DB_VECTOR);
5012 return 1;
5013 }
5014 }
5015
bfdaab09 5016 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5017 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5018 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5019 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5020 unsigned long val;
5021 if (!kvm_get_dr(vcpu, dr, &val))
5022 kvm_register_write(vcpu, reg, val);
5023 } else
5024 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5025 skip_emulated_instruction(vcpu);
5026 return 1;
5027}
5028
020df079
GN		 5029static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5030{
5031 vmcs_writel(GUEST_DR7, val);
5032}
5033
851ba692 5034static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5035{
06465c5a
AK		 5036 kvm_emulate_cpuid(vcpu);
5037 return 1;
6aa8b732
AK		 5038}
5039
851ba692 5040static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5041{
ad312c7c 5042 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5043 u64 data;
5044
5045 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5046 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5047 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5048 return 1;
5049 }
5050
229456fc 5051 trace_kvm_msr_read(ecx, data);
2714d1d3 5052
6aa8b732 5053 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5054 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5055 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5056 skip_emulated_instruction(vcpu);
5057 return 1;
5058}
5059
851ba692 5060static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5061{
8fe8ab46 5062 struct msr_data msr;
ad312c7c
ZX		 5063 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5064 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5065 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5066
8fe8ab46
WA		 5067 msr.data = data;
5068 msr.index = ecx;
5069 msr.host_initiated = false;
5070 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5071 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5072 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5073 return 1;
5074 }
5075
59200273 5076 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5077 skip_emulated_instruction(vcpu);
5078 return 1;
5079}
5080
851ba692 5081static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5082{
3842d135 5083 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5084 return 1;
5085}
5086
851ba692 5087static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5088{
85f455f7
ED		 5089 u32 cpu_based_vm_exec_control;
5090
5091 /* clear pending irq */
5092 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5093 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5094 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5095
3842d135
AK		 5096 kvm_make_request(KVM_REQ_EVENT, vcpu);
5097
a26bf12a 5098 ++vcpu->stat.irq_window_exits;
2714d1d3 5099
c1150d8c
DL		 5100 /*
5101 * If the user space waits to inject interrupts, exit as soon as
5102 * possible
5103 */
8061823a 5104 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5105 vcpu->run->request_interrupt_window &&
8061823a 5106 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5107 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5108 return 0;
5109 }
6aa8b732
AK		 5110 return 1;
5111}
5112
851ba692 5113static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5114{
5115 skip_emulated_instruction(vcpu);
d3bef15f 5116 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5117}
5118
851ba692 5119static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5120{
510043da 5121 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5122 kvm_emulate_hypercall(vcpu);
5123 return 1;
c21415e8
IM		 5124}
5125
ec25d5e6
GN		 5126static int handle_invd(struct kvm_vcpu *vcpu)
5127{
51d8b661 5128 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5129}
5130
851ba692 5131static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5132{
f9c617f6 5133 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5134
5135 kvm_mmu_invlpg(vcpu, exit_qualification);
5136 skip_emulated_instruction(vcpu);
5137 return 1;
5138}
5139
fee84b07
AK		 5140static int handle_rdpmc(struct kvm_vcpu *vcpu)
5141{
5142 int err;
5143
5144 err = kvm_rdpmc(vcpu);
5145 kvm_complete_insn_gp(vcpu, err);
5146
5147 return 1;
5148}
5149
851ba692 5150static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5151{
5152 skip_emulated_instruction(vcpu);
f5f48ee1 5153 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5154 return 1;
5155}
5156
2acf923e
DC		 5157static int handle_xsetbv(struct kvm_vcpu *vcpu)
5158{
5159 u64 new_bv = kvm_read_edx_eax(vcpu);
5160 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5161
5162 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5163 skip_emulated_instruction(vcpu);
5164 return 1;
5165}
5166
851ba692 5167static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5168{
58fbbf26
KT		 5169 if (likely(fasteoi)) {
5170 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5171 int access_type, offset;
5172
5173 access_type = exit_qualification & APIC_ACCESS_TYPE;
5174 offset = exit_qualification & APIC_ACCESS_OFFSET;
5175 /*
5176 * Sane guest uses MOV to write EOI, with written value
5177 * not cared. So make a short-circuit here by avoiding
5178 * heavy instruction emulation.
5179 */
5180 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5181 (offset == APIC_EOI)) {
5182 kvm_lapic_set_eoi(vcpu);
5183 skip_emulated_instruction(vcpu);
5184 return 1;
5185 }
5186 }
51d8b661 5187 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5188}
5189
c7c9c56c
YZ		 5190static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5191{
5192 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5193 int vector = exit_qualification & 0xff;
5194
5195 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5196 kvm_apic_set_eoi_accelerated(vcpu, vector);
5197 return 1;
5198}
5199
83d4c286
YZ		 5200static int handle_apic_write(struct kvm_vcpu *vcpu)
5201{
5202 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5203 u32 offset = exit_qualification & 0xfff;
5204
5205 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5206 kvm_apic_write_nodecode(vcpu, offset);
5207 return 1;
5208}
5209
851ba692 5210static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5211{
60637aac 5212 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5213 unsigned long exit_qualification;
e269fb21
JK		 5214 bool has_error_code = false;
5215 u32 error_code = 0;
37817f29 5216 u16 tss_selector;
7f3d35fd 5217 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5218
5219 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5220 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5221 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5222
5223 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5224
5225 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5226 if (reason == TASK_SWITCH_GATE && idt_v) {
5227 switch (type) {
5228 case INTR_TYPE_NMI_INTR:
5229 vcpu->arch.nmi_injected = false;
654f06fc 5230 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5231 break;
5232 case INTR_TYPE_EXT_INTR:
66fd3f7f 5233 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5234 kvm_clear_interrupt_queue(vcpu);
5235 break;
5236 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5237 if (vmx->idt_vectoring_info &
5238 VECTORING_INFO_DELIVER_CODE_MASK) {
5239 has_error_code = true;
5240 error_code =
5241 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5242 }
5243 /* fall through */
64a7ec06
GN		 5244 case INTR_TYPE_SOFT_EXCEPTION:
5245 kvm_clear_exception_queue(vcpu);
5246 break;
5247 default:
5248 break;
5249 }
60637aac 5250 }
37817f29
IE		 5251 tss_selector = exit_qualification;
5252
64a7ec06
GN		 5253 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5254 type != INTR_TYPE_EXT_INTR &&
5255 type != INTR_TYPE_NMI_INTR))
5256 skip_emulated_instruction(vcpu);
5257
7f3d35fd
KW		 5258 if (kvm_task_switch(vcpu, tss_selector,
5259 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5260 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5261 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5262 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5263 vcpu->run->internal.ndata = 0;
42dbaa5a 5264 return 0;
acb54517 5265 }
42dbaa5a
JK		 5266
5267 /* clear all local breakpoint enable flags */
5268 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5269
5270 /*
5271 * TODO: What about debug traps on tss switch?
5272 * Are we supposed to inject them and update dr6?
5273 */
5274
5275 return 1;
37817f29
IE		 5276}
5277
851ba692 5278static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5279{
f9c617f6 5280 unsigned long exit_qualification;
1439442c 5281 gpa_t gpa;
4f5982a5 5282 u32 error_code;
1439442c 5283 int gla_validity;
1439442c 5284
f9c617f6 5285 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5286
1439442c
SY		 5287 gla_validity = (exit_qualification >> 7) & 0x3;
5288 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5289 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5290 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5291 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5292 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5293 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5294 (long unsigned int)exit_qualification);
851ba692
AK		 5295 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5296 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5297 return 0;
1439442c
SY		 5298 }
5299
5300 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5301 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5302
5303 /* It is a write fault? */
5304 error_code = exit_qualification & (1U << 1);
5305 /* ept page table is present? */
5306 error_code |= (exit_qualification >> 3) & 0x1;
5307
5308 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5309}
5310
68f89400
MT		 5311static u64 ept_rsvd_mask(u64 spte, int level)
5312{
5313 int i;
5314 u64 mask = 0;
5315
5316 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5317 mask |= (1ULL << i);
5318
5319 if (level > 2)
5320 /* bits 7:3 reserved */
5321 mask |= 0xf8;
5322 else if (level == 2) {
5323 if (spte & (1ULL << 7))
5324 /* 2MB ref, bits 20:12 reserved */
5325 mask |= 0x1ff000;
5326 else
5327 /* bits 6:3 reserved */
5328 mask |= 0x78;
5329 }
5330
5331 return mask;
5332}
5333
5334static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5335 int level)
5336{
5337 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5338
5339 /* 010b (write-only) */
5340 WARN_ON((spte & 0x7) == 0x2);
5341
5342 /* 110b (write/execute) */
5343 WARN_ON((spte & 0x7) == 0x6);
5344
5345 /* 100b (execute-only) and value not supported by logical processor */
5346 if (!cpu_has_vmx_ept_execute_only())
5347 WARN_ON((spte & 0x7) == 0x4);
5348
5349 /* not 000b */
5350 if ((spte & 0x7)) {
5351 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5352
5353 if (rsvd_bits != 0) {
5354 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5355 __func__, rsvd_bits);
5356 WARN_ON(1);
5357 }
5358
5359 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5360 u64 ept_mem_type = (spte & 0x38) >> 3;
5361
5362 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5363 ept_mem_type == 7) {
5364 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5365 __func__, ept_mem_type);
5366 WARN_ON(1);
5367 }
5368 }
5369 }
5370}
5371
851ba692 5372static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5373{
5374 u64 sptes[4];
ce88decf 5375 int nr_sptes, i, ret;
68f89400
MT		 5376 gpa_t gpa;
5377
5378 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5379
ce88decf 5380 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5381 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5382 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5383 EMULATE_DONE;
f8f55942
XG		 5384
5385 if (unlikely(ret == RET_MMIO_PF_INVALID))
5386 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5387
b37fbea6 5388 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5389 return 1;
5390
5391 /* It is the real ept misconfig */
68f89400
MT		 5392 printk(KERN_ERR "EPT: Misconfiguration.\n");
5393 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5394
5395 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5396
5397 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5398 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5399
851ba692
AK		 5400 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5401 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5402
5403 return 0;
5404}
5405
851ba692 5406static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5407{
5408 u32 cpu_based_vm_exec_control;
5409
5410 /* clear pending NMI */
5411 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5412 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5413 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5414 ++vcpu->stat.nmi_window_exits;
3842d135 5415 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5416
5417 return 1;
5418}
5419
80ced186 5420static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5421{
8b3079a5
AK		 5422 struct vcpu_vmx *vmx = to_vmx(vcpu);
5423 enum emulation_result err = EMULATE_DONE;
80ced186 5424 int ret = 1;
49e9d557
AK		 5425 u32 cpu_exec_ctrl;
5426 bool intr_window_requested;
b8405c18 5427 unsigned count = 130;
49e9d557
AK		 5428
5429 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5430 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5431
b8405c18 5432 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5433 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5434 return handle_interrupt_window(&vmx->vcpu);
5435
de87dcdd
AK		 5436 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5437 return 1;
5438
991eebf9 5439 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5440
80ced186
MG		 5441 if (err == EMULATE_DO_MMIO) {
5442 ret = 0;
5443 goto out;
5444 }
1d5a4d9b 5445
de5f70e0
AK		 5446 if (err != EMULATE_DONE) {
5447 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5448 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5449 vcpu->run->internal.ndata = 0;
6d77dbfc 5450 return 0;
de5f70e0 5451 }
ea953ef0 5452
8d76c49e
GN		 5453 if (vcpu->arch.halt_request) {
5454 vcpu->arch.halt_request = 0;
5455 ret = kvm_emulate_halt(vcpu);
5456 goto out;
5457 }
5458
ea953ef0 5459 if (signal_pending(current))
80ced186 5460 goto out;
ea953ef0
MG		 5461 if (need_resched())
5462 schedule();
5463 }
5464
14168786 5465 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5466out:
5467 return ret;
ea953ef0
MG		 5468}
5469
4b8d54f9
ZE		 5470/*
5471 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5472 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5473 */
9fb41ba8 5474static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5475{
5476 skip_emulated_instruction(vcpu);
5477 kvm_vcpu_on_spin(vcpu);
5478
5479 return 1;
5480}
5481
59708670
SY		 5482static int handle_invalid_op(struct kvm_vcpu *vcpu)
5483{
5484 kvm_queue_exception(vcpu, UD_VECTOR);
5485 return 1;
5486}
5487
ff2f6fe9
NHE		 5488/*
5489 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5490 * We could reuse a single VMCS for all the L2 guests, but we also want the
5491 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5492 * allows keeping them loaded on the processor, and in the future will allow
5493 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5494 * every entry if they never change.
5495 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5496 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5497 *
5498 * The following functions allocate and free a vmcs02 in this pool.
5499 */
5500
5501/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5502static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5503{
5504 struct vmcs02_list *item;
5505 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5506 if (item->vmptr == vmx->nested.current_vmptr) {
5507 list_move(&item->list, &vmx->nested.vmcs02_pool);
5508 return &item->vmcs02;
5509 }
5510
5511 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5512 /* Recycle the least recently used VMCS. */
5513 item = list_entry(vmx->nested.vmcs02_pool.prev,
5514 struct vmcs02_list, list);
5515 item->vmptr = vmx->nested.current_vmptr;
5516 list_move(&item->list, &vmx->nested.vmcs02_pool);
5517 return &item->vmcs02;
5518 }
5519
5520 /* Create a new VMCS */
0fa24ce3 5521 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5522 if (!item)
5523 return NULL;
5524 item->vmcs02.vmcs = alloc_vmcs();
5525 if (!item->vmcs02.vmcs) {
5526 kfree(item);
5527 return NULL;
5528 }
5529 loaded_vmcs_init(&item->vmcs02);
5530 item->vmptr = vmx->nested.current_vmptr;
5531 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5532 vmx->nested.vmcs02_num++;
5533 return &item->vmcs02;
5534}
5535
5536/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5537static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5538{
5539 struct vmcs02_list *item;
5540 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5541 if (item->vmptr == vmptr) {
5542 free_loaded_vmcs(&item->vmcs02);
5543 list_del(&item->list);
5544 kfree(item);
5545 vmx->nested.vmcs02_num--;
5546 return;
5547 }
5548}
5549
5550/*
5551 * Free all VMCSs saved for this vcpu, except the one pointed by
5552 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5553 * currently used, if running L2), and vmcs01 when running L2.
5554 */
5555static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5556{
5557 struct vmcs02_list *item, *n;
5558 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5559 if (vmx->loaded_vmcs != &item->vmcs02)
5560 free_loaded_vmcs(&item->vmcs02);
5561 list_del(&item->list);
5562 kfree(item);
5563 }
5564 vmx->nested.vmcs02_num = 0;
5565
5566 if (vmx->loaded_vmcs != &vmx->vmcs01)
5567 free_loaded_vmcs(&vmx->vmcs01);
5568}
5569
0658fbaa
ACL		 5570/*
5571 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5572 * set the success or error code of an emulated VMX instruction, as specified
5573 * by Vol 2B, VMX Instruction Reference, "Conventions".
5574 */
5575static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5576{
5577 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5578 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5579 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5580}
5581
5582static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5583{
5584 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5585 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5586 X86_EFLAGS_SF | X86_EFLAGS_OF))
5587 | X86_EFLAGS_CF);
5588}
5589
145c28dd 5590static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5591 u32 vm_instruction_error)
5592{
5593 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5594 /*
5595 * failValid writes the error number to the current VMCS, which
5596 * can't be done there isn't a current VMCS.
5597 */
5598 nested_vmx_failInvalid(vcpu);
5599 return;
5600 }
5601 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5602 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5603 X86_EFLAGS_SF | X86_EFLAGS_OF))
5604 | X86_EFLAGS_ZF);
5605 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5606 /*
5607 * We don't need to force a shadow sync because
5608 * VM_INSTRUCTION_ERROR is not shadowed
5609 */
5610}
145c28dd 5611
ec378aee
NHE		 5612/*
5613 * Emulate the VMXON instruction.
5614 * Currently, we just remember that VMX is active, and do not save or even
5615 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5616 * do not currently need to store anything in that guest-allocated memory
5617 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5618 * argument is different from the VMXON pointer (which the spec says they do).
5619 */
5620static int handle_vmon(struct kvm_vcpu *vcpu)
5621{
5622 struct kvm_segment cs;
5623 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5624 struct vmcs *shadow_vmcs;
ec378aee
NHE		 5625
5626 /* The Intel VMX Instruction Reference lists a bunch of bits that
5627 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5628 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5629 * Otherwise, we should fail with #UD. We test these now:
5630 */
5631 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5632 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5633 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5634 kvm_queue_exception(vcpu, UD_VECTOR);
5635 return 1;
5636 }
5637
5638 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5639 if (is_long_mode(vcpu) && !cs.l) {
5640 kvm_queue_exception(vcpu, UD_VECTOR);
5641 return 1;
5642 }
5643
5644 if (vmx_get_cpl(vcpu)) {
5645 kvm_inject_gp(vcpu, 0);
5646 return 1;
5647 }
145c28dd
AG		 5648 if (vmx->nested.vmxon) {
5649 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5650 skip_emulated_instruction(vcpu);
5651 return 1;
5652 }
8de48833
AG		 5653 if (enable_shadow_vmcs) {
5654 shadow_vmcs = alloc_vmcs();
5655 if (!shadow_vmcs)
5656 return -ENOMEM;
5657 /* mark vmcs as shadow */
5658 shadow_vmcs->revision_id |= (1u << 31);
5659 /* init shadow vmcs */
5660 vmcs_clear(shadow_vmcs);
5661 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5662 }
ec378aee 5663
ff2f6fe9
NHE		 5664 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5665 vmx->nested.vmcs02_num = 0;
5666
ec378aee
NHE		 5667 vmx->nested.vmxon = true;
5668
5669 skip_emulated_instruction(vcpu);
a25eb114 5670 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5671 return 1;
5672}
5673
5674/*
5675 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5676 * for running VMX instructions (except VMXON, whose prerequisites are
5677 * slightly different). It also specifies what exception to inject otherwise.
5678 */
5679static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5680{
5681 struct kvm_segment cs;
5682 struct vcpu_vmx *vmx = to_vmx(vcpu);
5683
5684 if (!vmx->nested.vmxon) {
5685 kvm_queue_exception(vcpu, UD_VECTOR);
5686 return 0;
5687 }
5688
5689 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5690 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5691 (is_long_mode(vcpu) && !cs.l)) {
5692 kvm_queue_exception(vcpu, UD_VECTOR);
5693 return 0;
5694 }
5695
5696 if (vmx_get_cpl(vcpu)) {
5697 kvm_inject_gp(vcpu, 0);
5698 return 0;
5699 }
5700
5701 return 1;
5702}
5703
e7953d7f
AG		 5704static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5705{
8a1b9dd0 5706 u32 exec_control;
012f83cb
AG		 5707 if (enable_shadow_vmcs) {
5708 if (vmx->nested.current_vmcs12 != NULL) {
5709 /* copy to memory all shadowed fields in case
5710 they were modified */
5711 copy_shadow_to_vmcs12(vmx);
5712 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5713 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5714 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5715 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5716 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5717 }
5718 }
e7953d7f
AG		 5719 kunmap(vmx->nested.current_vmcs12_page);
5720 nested_release_page(vmx->nested.current_vmcs12_page);
5721}
5722
ec378aee
NHE		 5723/*
5724 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5725 * just stops using VMX.
5726 */
5727static void free_nested(struct vcpu_vmx *vmx)
5728{
5729 if (!vmx->nested.vmxon)
5730 return;
5731 vmx->nested.vmxon = false;
a9d30f33 5732 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5733 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5734 vmx->nested.current_vmptr = -1ull;
5735 vmx->nested.current_vmcs12 = NULL;
5736 }
e7953d7f
AG		 5737 if (enable_shadow_vmcs)
5738 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5739 /* Unpin physical memory we referred to in current vmcs02 */
5740 if (vmx->nested.apic_access_page) {
5741 nested_release_page(vmx->nested.apic_access_page);
5742 vmx->nested.apic_access_page = 0;
5743 }
ff2f6fe9
NHE		 5744
5745 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5746}
5747
5748/* Emulate the VMXOFF instruction */
5749static int handle_vmoff(struct kvm_vcpu *vcpu)
5750{
5751 if (!nested_vmx_check_permission(vcpu))
5752 return 1;
5753 free_nested(to_vmx(vcpu));
5754 skip_emulated_instruction(vcpu);
a25eb114 5755 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5756 return 1;
5757}
5758
064aea77
NHE		 5759/*
5760 * Decode the memory-address operand of a vmx instruction, as recorded on an
5761 * exit caused by such an instruction (run by a guest hypervisor).
5762 * On success, returns 0. When the operand is invalid, returns 1 and throws
5763 * #UD or #GP.
5764 */
5765static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5766 unsigned long exit_qualification,
5767 u32 vmx_instruction_info, gva_t *ret)
5768{
5769 /*
5770 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5771 * Execution", on an exit, vmx_instruction_info holds most of the
5772 * addressing components of the operand. Only the displacement part
5773 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5774 * For how an actual address is calculated from all these components,
5775 * refer to Vol. 1, "Operand Addressing".
5776 */
5777 int scaling = vmx_instruction_info & 3;
5778 int addr_size = (vmx_instruction_info >> 7) & 7;
5779 bool is_reg = vmx_instruction_info & (1u << 10);
5780 int seg_reg = (vmx_instruction_info >> 15) & 7;
5781 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5782 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5783 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5784 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5785
5786 if (is_reg) {
5787 kvm_queue_exception(vcpu, UD_VECTOR);
5788 return 1;
5789 }
5790
5791 /* Addr = segment_base + offset */
5792 /* offset = base + [index * scale] + displacement */
5793 *ret = vmx_get_segment_base(vcpu, seg_reg);
5794 if (base_is_valid)
5795 *ret += kvm_register_read(vcpu, base_reg);
5796 if (index_is_valid)
5797 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5798 *ret += exit_qualification; /* holds the displacement */
5799
5800 if (addr_size == 1) /* 32 bit */
5801 *ret &= 0xffffffff;
5802
5803 /*
5804 * TODO: throw #GP (and return 1) in various cases that the VM*
5805 * instructions require it - e.g., offset beyond segment limit,
5806 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5807 * address, and so on. Currently these are not checked.
5808 */
5809 return 0;
5810}
5811
27d6c865
NHE		 5812/* Emulate the VMCLEAR instruction */
5813static int handle_vmclear(struct kvm_vcpu *vcpu)
5814{
5815 struct vcpu_vmx *vmx = to_vmx(vcpu);
5816 gva_t gva;
5817 gpa_t vmptr;
5818 struct vmcs12 *vmcs12;
5819 struct page *page;
5820 struct x86_exception e;
5821
5822 if (!nested_vmx_check_permission(vcpu))
5823 return 1;
5824
5825 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5826 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5827 return 1;
5828
5829 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5830 sizeof(vmptr), &e)) {
5831 kvm_inject_page_fault(vcpu, &e);
5832 return 1;
5833 }
5834
5835 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5836 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5837 skip_emulated_instruction(vcpu);
5838 return 1;
5839 }
5840
5841 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5842 nested_release_vmcs12(vmx);
27d6c865
NHE		 5843 vmx->nested.current_vmptr = -1ull;
5844 vmx->nested.current_vmcs12 = NULL;
5845 }
5846
5847 page = nested_get_page(vcpu, vmptr);
5848 if (page == NULL) {
5849 /*
5850 * For accurate processor emulation, VMCLEAR beyond available
5851 * physical memory should do nothing at all. However, it is
5852 * possible that a nested vmx bug, not a guest hypervisor bug,
5853 * resulted in this case, so let's shut down before doing any
5854 * more damage:
5855 */
5856 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5857 return 1;
5858 }
5859 vmcs12 = kmap(page);
5860 vmcs12->launch_state = 0;
5861 kunmap(page);
5862 nested_release_page(page);
5863
5864 nested_free_vmcs02(vmx, vmptr);
5865
5866 skip_emulated_instruction(vcpu);
5867 nested_vmx_succeed(vcpu);
5868 return 1;
5869}
5870
cd232ad0
NHE		 5871static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5872
5873/* Emulate the VMLAUNCH instruction */
5874static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5875{
5876 return nested_vmx_run(vcpu, true);
5877}
5878
5879/* Emulate the VMRESUME instruction */
5880static int handle_vmresume(struct kvm_vcpu *vcpu)
5881{
5882
5883 return nested_vmx_run(vcpu, false);
5884}
5885
49f705c5
NHE		 5886enum vmcs_field_type {
5887 VMCS_FIELD_TYPE_U16 = 0,
5888 VMCS_FIELD_TYPE_U64 = 1,
5889 VMCS_FIELD_TYPE_U32 = 2,
5890 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5891};
5892
5893static inline int vmcs_field_type(unsigned long field)
5894{
5895 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5896 return VMCS_FIELD_TYPE_U32;
5897 return (field >> 13) & 0x3 ;
5898}
5899
5900static inline int vmcs_field_readonly(unsigned long field)
5901{
5902 return (((field >> 10) & 0x3) == 1);
5903}
5904
5905/*
5906 * Read a vmcs12 field. Since these can have varying lengths and we return
5907 * one type, we chose the biggest type (u64) and zero-extend the return value
5908 * to that size. Note that the caller, handle_vmread, might need to use only
5909 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5910 * 64-bit fields are to be returned).
5911 */
5912static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5913 unsigned long field, u64 *ret)
5914{
5915 short offset = vmcs_field_to_offset(field);
5916 char *p;
5917
5918 if (offset < 0)
5919 return 0;
5920
5921 p = ((char *)(get_vmcs12(vcpu))) + offset;
5922
5923 switch (vmcs_field_type(field)) {
5924 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5925 *ret = *((natural_width *)p);
5926 return 1;
5927 case VMCS_FIELD_TYPE_U16:
5928 *ret = *((u16 *)p);
5929 return 1;
5930 case VMCS_FIELD_TYPE_U32:
5931 *ret = *((u32 *)p);
5932 return 1;
5933 case VMCS_FIELD_TYPE_U64:
5934 *ret = *((u64 *)p);
5935 return 1;
5936 default:
5937 return 0; /* can never happen. */
5938 }
5939}
5940
20b97fea
AG		 5941
5942static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5943 unsigned long field, u64 field_value){
5944 short offset = vmcs_field_to_offset(field);
5945 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5946 if (offset < 0)
5947 return false;
5948
5949 switch (vmcs_field_type(field)) {
5950 case VMCS_FIELD_TYPE_U16:
5951 *(u16 *)p = field_value;
5952 return true;
5953 case VMCS_FIELD_TYPE_U32:
5954 *(u32 *)p = field_value;
5955 return true;
5956 case VMCS_FIELD_TYPE_U64:
5957 *(u64 *)p = field_value;
5958 return true;
5959 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5960 *(natural_width *)p = field_value;
5961 return true;
5962 default:
5963 return false; /* can never happen. */
5964 }
5965
5966}
5967
16f5b903
AG		 5968static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5969{
5970 int i;
5971 unsigned long field;
5972 u64 field_value;
5973 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5974 unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5975 int num_fields = max_shadow_read_write_fields;
5976
5977 vmcs_load(shadow_vmcs);
5978
5979 for (i = 0; i < num_fields; i++) {
5980 field = fields[i];
5981 switch (vmcs_field_type(field)) {
5982 case VMCS_FIELD_TYPE_U16:
5983 field_value = vmcs_read16(field);
5984 break;
5985 case VMCS_FIELD_TYPE_U32:
5986 field_value = vmcs_read32(field);
5987 break;
5988 case VMCS_FIELD_TYPE_U64:
5989 field_value = vmcs_read64(field);
5990 break;
5991 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5992 field_value = vmcs_readl(field);
5993 break;
5994 }
5995 vmcs12_write_any(&vmx->vcpu, field, field_value);
5996 }
5997
5998 vmcs_clear(shadow_vmcs);
5999 vmcs_load(vmx->loaded_vmcs->vmcs);
6000}
6001
c3114420
AG		 6002static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6003{
6004 unsigned long *fields[] = {
6005 (unsigned long *)shadow_read_write_fields,
6006 (unsigned long *)shadow_read_only_fields
6007 };
6008 int num_lists = ARRAY_SIZE(fields);
6009 int max_fields[] = {
6010 max_shadow_read_write_fields,
6011 max_shadow_read_only_fields
6012 };
6013 int i, q;
6014 unsigned long field;
6015 u64 field_value = 0;
6016 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6017
6018 vmcs_load(shadow_vmcs);
6019
6020 for (q = 0; q < num_lists; q++) {
6021 for (i = 0; i < max_fields[q]; i++) {
6022 field = fields[q][i];
6023 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6024
6025 switch (vmcs_field_type(field)) {
6026 case VMCS_FIELD_TYPE_U16:
6027 vmcs_write16(field, (u16)field_value);
6028 break;
6029 case VMCS_FIELD_TYPE_U32:
6030 vmcs_write32(field, (u32)field_value);
6031 break;
6032 case VMCS_FIELD_TYPE_U64:
6033 vmcs_write64(field, (u64)field_value);
6034 break;
6035 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6036 vmcs_writel(field, (long)field_value);
6037 break;
6038 }
6039 }
6040 }
6041
6042 vmcs_clear(shadow_vmcs);
6043 vmcs_load(vmx->loaded_vmcs->vmcs);
6044}
6045
49f705c5
NHE		 6046/*
6047 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6048 * used before) all generate the same failure when it is missing.
6049 */
6050static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6051{
6052 struct vcpu_vmx *vmx = to_vmx(vcpu);
6053 if (vmx->nested.current_vmptr == -1ull) {
6054 nested_vmx_failInvalid(vcpu);
6055 skip_emulated_instruction(vcpu);
6056 return 0;
6057 }
6058 return 1;
6059}
6060
6061static int handle_vmread(struct kvm_vcpu *vcpu)
6062{
6063 unsigned long field;
6064 u64 field_value;
6065 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6066 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6067 gva_t gva = 0;
6068
6069 if (!nested_vmx_check_permission(vcpu) ||
6070 !nested_vmx_check_vmcs12(vcpu))
6071 return 1;
6072
6073 /* Decode instruction info and find the field to read */
6074 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6075 /* Read the field, zero-extended to a u64 field_value */
6076 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6077 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6078 skip_emulated_instruction(vcpu);
6079 return 1;
6080 }
6081 /*
6082 * Now copy part of this value to register or memory, as requested.
6083 * Note that the number of bits actually copied is 32 or 64 depending
6084 * on the guest's mode (32 or 64 bit), not on the given field's length.
6085 */
6086 if (vmx_instruction_info & (1u << 10)) {
6087 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6088 field_value);
6089 } else {
6090 if (get_vmx_mem_address(vcpu, exit_qualification,
6091 vmx_instruction_info, &gva))
6092 return 1;
6093 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6094 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6095 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6096 }
6097
6098 nested_vmx_succeed(vcpu);
6099 skip_emulated_instruction(vcpu);
6100 return 1;
6101}
6102
6103
6104static int handle_vmwrite(struct kvm_vcpu *vcpu)
6105{
6106 unsigned long field;
6107 gva_t gva;
6108 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6109 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6110 /* The value to write might be 32 or 64 bits, depending on L1's long
6111 * mode, and eventually we need to write that into a field of several
6112 * possible lengths. The code below first zero-extends the value to 64
6113 * bit (field_value), and then copies only the approriate number of
6114 * bits into the vmcs12 field.
6115 */
6116 u64 field_value = 0;
6117 struct x86_exception e;
6118
6119 if (!nested_vmx_check_permission(vcpu) ||
6120 !nested_vmx_check_vmcs12(vcpu))
6121 return 1;
6122
6123 if (vmx_instruction_info & (1u << 10))
6124 field_value = kvm_register_read(vcpu,
6125 (((vmx_instruction_info) >> 3) & 0xf));
6126 else {
6127 if (get_vmx_mem_address(vcpu, exit_qualification,
6128 vmx_instruction_info, &gva))
6129 return 1;
6130 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6131 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6132 kvm_inject_page_fault(vcpu, &e);
6133 return 1;
6134 }
6135 }
6136
6137
6138 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6139 if (vmcs_field_readonly(field)) {
6140 nested_vmx_failValid(vcpu,
6141 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6142 skip_emulated_instruction(vcpu);
6143 return 1;
6144 }
6145
20b97fea 6146 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6147 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6148 skip_emulated_instruction(vcpu);
6149 return 1;
6150 }
6151
6152 nested_vmx_succeed(vcpu);
6153 skip_emulated_instruction(vcpu);
6154 return 1;
6155}
6156
63846663
NHE		 6157/* Emulate the VMPTRLD instruction */
6158static int handle_vmptrld(struct kvm_vcpu *vcpu)
6159{
6160 struct vcpu_vmx *vmx = to_vmx(vcpu);
6161 gva_t gva;
6162 gpa_t vmptr;
6163 struct x86_exception e;
8a1b9dd0 6164 u32 exec_control;
63846663
NHE		 6165
6166 if (!nested_vmx_check_permission(vcpu))
6167 return 1;
6168
6169 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6170 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6171 return 1;
6172
6173 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6174 sizeof(vmptr), &e)) {
6175 kvm_inject_page_fault(vcpu, &e);
6176 return 1;
6177 }
6178
6179 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6180 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6181 skip_emulated_instruction(vcpu);
6182 return 1;
6183 }
6184
6185 if (vmx->nested.current_vmptr != vmptr) {
6186 struct vmcs12 *new_vmcs12;
6187 struct page *page;
6188 page = nested_get_page(vcpu, vmptr);
6189 if (page == NULL) {
6190 nested_vmx_failInvalid(vcpu);
6191 skip_emulated_instruction(vcpu);
6192 return 1;
6193 }
6194 new_vmcs12 = kmap(page);
6195 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6196 kunmap(page);
6197 nested_release_page_clean(page);
6198 nested_vmx_failValid(vcpu,
6199 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6200 skip_emulated_instruction(vcpu);
6201 return 1;
6202 }
e7953d7f
AG		 6203 if (vmx->nested.current_vmptr != -1ull)
6204 nested_release_vmcs12(vmx);
63846663
NHE		 6205
6206 vmx->nested.current_vmptr = vmptr;
6207 vmx->nested.current_vmcs12 = new_vmcs12;
6208 vmx->nested.current_vmcs12_page = page;
012f83cb 6209 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6210 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6211 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6212 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6213 vmcs_write64(VMCS_LINK_POINTER,
6214 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6215 vmx->nested.sync_shadow_vmcs = true;
6216 }
63846663
NHE		 6217 }
6218
6219 nested_vmx_succeed(vcpu);
6220 skip_emulated_instruction(vcpu);
6221 return 1;
6222}
6223
6a4d7550
NHE		 6224/* Emulate the VMPTRST instruction */
6225static int handle_vmptrst(struct kvm_vcpu *vcpu)
6226{
6227 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6228 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6229 gva_t vmcs_gva;
6230 struct x86_exception e;
6231
6232 if (!nested_vmx_check_permission(vcpu))
6233 return 1;
6234
6235 if (get_vmx_mem_address(vcpu, exit_qualification,
6236 vmx_instruction_info, &vmcs_gva))
6237 return 1;
6238 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6239 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6240 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6241 sizeof(u64), &e)) {
6242 kvm_inject_page_fault(vcpu, &e);
6243 return 1;
6244 }
6245 nested_vmx_succeed(vcpu);
6246 skip_emulated_instruction(vcpu);
6247 return 1;
6248}
6249
6aa8b732
AK		 6250/*
6251 * The exit handlers return 1 if the exit was handled fully and guest execution
6252 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6253 * to be done to userspace and return 0.
6254 */
772e0318 6255static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6256 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6257 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6258 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6259 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6260 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6261 [EXIT_REASON_CR_ACCESS] = handle_cr,
6262 [EXIT_REASON_DR_ACCESS] = handle_dr,
6263 [EXIT_REASON_CPUID] = handle_cpuid,
6264 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6265 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6266 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6267 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6268 [EXIT_REASON_INVD] = handle_invd,
a7052897 6269 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6270 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6271 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6272 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6273 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6274 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6275 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6276 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6277 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6278 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6279 [EXIT_REASON_VMOFF] = handle_vmoff,
6280 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6281 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6282 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6283 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6284 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6285 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6286 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6287 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6288 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6289 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6290 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6291 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6292 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6293 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6294};
6295
6296static const int kvm_vmx_max_exit_handlers =
50a3485c 6297 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6298
908a7bdd
JK		 6299static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6300 struct vmcs12 *vmcs12)
6301{
6302 unsigned long exit_qualification;
6303 gpa_t bitmap, last_bitmap;
6304 unsigned int port;
6305 int size;
6306 u8 b;
6307
6308 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6309 return 1;
6310
6311 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6312 return 0;
6313
6314 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6315
6316 port = exit_qualification >> 16;
6317 size = (exit_qualification & 7) + 1;
6318
6319 last_bitmap = (gpa_t)-1;
6320 b = -1;
6321
6322 while (size > 0) {
6323 if (port < 0x8000)
6324 bitmap = vmcs12->io_bitmap_a;
6325 else if (port < 0x10000)
6326 bitmap = vmcs12->io_bitmap_b;
6327 else
6328 return 1;
6329 bitmap += (port & 0x7fff) / 8;
6330
6331 if (last_bitmap != bitmap)
6332 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6333 return 1;
6334 if (b & (1 << (port & 7)))
6335 return 1;
6336
6337 port++;
6338 size--;
6339 last_bitmap = bitmap;
6340 }
6341
6342 return 0;
6343}
6344
644d711a
NHE		 6345/*
6346 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6347 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6348 * disinterest in the current event (read or write a specific MSR) by using an
6349 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6350 */
6351static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6352 struct vmcs12 *vmcs12, u32 exit_reason)
6353{
6354 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6355 gpa_t bitmap;
6356
cbd29cb6 6357 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6358 return 1;
6359
6360 /*
6361 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6362 * for the four combinations of read/write and low/high MSR numbers.
6363 * First we need to figure out which of the four to use:
6364 */
6365 bitmap = vmcs12->msr_bitmap;
6366 if (exit_reason == EXIT_REASON_MSR_WRITE)
6367 bitmap += 2048;
6368 if (msr_index >= 0xc0000000) {
6369 msr_index -= 0xc0000000;
6370 bitmap += 1024;
6371 }
6372
6373 /* Then read the msr_index'th bit from this bitmap: */
6374 if (msr_index < 1024*8) {
6375 unsigned char b;
bd31a7f5
JK		 6376 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6377 return 1;
644d711a
NHE		 6378 return 1 & (b >> (msr_index & 7));
6379 } else
6380 return 1; /* let L1 handle the wrong parameter */
6381}
6382
6383/*
6384 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6385 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6386 * intercept (via guest_host_mask etc.) the current event.
6387 */
6388static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6389 struct vmcs12 *vmcs12)
6390{
6391 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6392 int cr = exit_qualification & 15;
6393 int reg = (exit_qualification >> 8) & 15;
6394 unsigned long val = kvm_register_read(vcpu, reg);
6395
6396 switch ((exit_qualification >> 4) & 3) {
6397 case 0: /* mov to cr */
6398 switch (cr) {
6399 case 0:
6400 if (vmcs12->cr0_guest_host_mask &
6401 (val ^ vmcs12->cr0_read_shadow))
6402 return 1;
6403 break;
6404 case 3:
6405 if ((vmcs12->cr3_target_count >= 1 &&
6406 vmcs12->cr3_target_value0 == val) ||
6407 (vmcs12->cr3_target_count >= 2 &&
6408 vmcs12->cr3_target_value1 == val) ||
6409 (vmcs12->cr3_target_count >= 3 &&
6410 vmcs12->cr3_target_value2 == val) ||
6411 (vmcs12->cr3_target_count >= 4 &&
6412 vmcs12->cr3_target_value3 == val))
6413 return 0;
6414 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6415 return 1;
6416 break;
6417 case 4:
6418 if (vmcs12->cr4_guest_host_mask &
6419 (vmcs12->cr4_read_shadow ^ val))
6420 return 1;
6421 break;
6422 case 8:
6423 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6424 return 1;
6425 break;
6426 }
6427 break;
6428 case 2: /* clts */
6429 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6430 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6431 return 1;
6432 break;
6433 case 1: /* mov from cr */
6434 switch (cr) {
6435 case 3:
6436 if (vmcs12->cpu_based_vm_exec_control &
6437 CPU_BASED_CR3_STORE_EXITING)
6438 return 1;
6439 break;
6440 case 8:
6441 if (vmcs12->cpu_based_vm_exec_control &
6442 CPU_BASED_CR8_STORE_EXITING)
6443 return 1;
6444 break;
6445 }
6446 break;
6447 case 3: /* lmsw */
6448 /*
6449 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6450 * cr0. Other attempted changes are ignored, with no exit.
6451 */
6452 if (vmcs12->cr0_guest_host_mask & 0xe &
6453 (val ^ vmcs12->cr0_read_shadow))
6454 return 1;
6455 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6456 !(vmcs12->cr0_read_shadow & 0x1) &&
6457 (val & 0x1))
6458 return 1;
6459 break;
6460 }
6461 return 0;
6462}
6463
6464/*
6465 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6466 * should handle it ourselves in L0 (and then continue L2). Only call this
6467 * when in is_guest_mode (L2).
6468 */
6469static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6470{
644d711a
NHE		 6471 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6472 struct vcpu_vmx *vmx = to_vmx(vcpu);
6473 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6474 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6475
6476 if (vmx->nested.nested_run_pending)
6477 return 0;
6478
6479 if (unlikely(vmx->fail)) {
bd80158a
JK		 6480 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6481 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6482 return 1;
6483 }
6484
6485 switch (exit_reason) {
6486 case EXIT_REASON_EXCEPTION_NMI:
6487 if (!is_exception(intr_info))
6488 return 0;
6489 else if (is_page_fault(intr_info))
6490 return enable_ept;
6491 return vmcs12->exception_bitmap &
6492 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6493 case EXIT_REASON_EXTERNAL_INTERRUPT:
6494 return 0;
6495 case EXIT_REASON_TRIPLE_FAULT:
6496 return 1;
6497 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6498 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6499 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6500 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6501 case EXIT_REASON_TASK_SWITCH:
6502 return 1;
6503 case EXIT_REASON_CPUID:
6504 return 1;
6505 case EXIT_REASON_HLT:
6506 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6507 case EXIT_REASON_INVD:
6508 return 1;
6509 case EXIT_REASON_INVLPG:
6510 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6511 case EXIT_REASON_RDPMC:
6512 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6513 case EXIT_REASON_RDTSC:
6514 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6515 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6516 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6517 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6518 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6519 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6520 /*
6521 * VMX instructions trap unconditionally. This allows L1 to
6522 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6523 */
6524 return 1;
6525 case EXIT_REASON_CR_ACCESS:
6526 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6527 case EXIT_REASON_DR_ACCESS:
6528 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6529 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6530 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6531 case EXIT_REASON_MSR_READ:
6532 case EXIT_REASON_MSR_WRITE:
6533 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6534 case EXIT_REASON_INVALID_STATE:
6535 return 1;
6536 case EXIT_REASON_MWAIT_INSTRUCTION:
6537 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6538 case EXIT_REASON_MONITOR_INSTRUCTION:
6539 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6540 case EXIT_REASON_PAUSE_INSTRUCTION:
6541 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6542 nested_cpu_has2(vmcs12,
6543 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6544 case EXIT_REASON_MCE_DURING_VMENTRY:
6545 return 0;
6546 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6547 return 1;
6548 case EXIT_REASON_APIC_ACCESS:
6549 return nested_cpu_has2(vmcs12,
6550 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6551 case EXIT_REASON_EPT_VIOLATION:
6552 case EXIT_REASON_EPT_MISCONFIG:
6553 return 0;
0238ea91
JK		 6554 case EXIT_REASON_PREEMPTION_TIMER:
6555 return vmcs12->pin_based_vm_exec_control &
6556 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6557 case EXIT_REASON_WBINVD:
6558 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6559 case EXIT_REASON_XSETBV:
6560 return 1;
6561 default:
6562 return 1;
6563 }
6564}
6565
586f9607
AK		 6566static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6567{
6568 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6569 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6570}
6571
6aa8b732
AK		 6572/*
6573 * The guest has exited. See if we can fix it or if we need userspace
6574 * assistance.
6575 */
851ba692 6576static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6577{
29bd8a78 6578 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6579 u32 exit_reason = vmx->exit_reason;
1155f76a 6580 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6581
80ced186 6582 /* If guest state is invalid, start emulating */
14168786 6583 if (vmx->emulation_required)
80ced186 6584 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6585
b6f1250e
NHE		 6586 /*
6587 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6588 * we did not inject a still-pending event to L1 now because of
6589 * nested_run_pending, we need to re-enable this bit.
6590 */
6591 if (vmx->nested.nested_run_pending)
6592 kvm_make_request(KVM_REQ_EVENT, vcpu);
6593
509c75ea
NHE		 6594 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6595 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6596 vmx->nested.nested_run_pending = 1;
6597 else
6598 vmx->nested.nested_run_pending = 0;
6599
6600 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6601 nested_vmx_vmexit(vcpu);
6602 return 1;
6603 }
6604
5120702e
MG		 6605 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6606 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6607 vcpu->run->fail_entry.hardware_entry_failure_reason
6608 = exit_reason;
6609 return 0;
6610 }
6611
29bd8a78 6612 if (unlikely(vmx->fail)) {
851ba692
AK		 6613 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6614 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6615 = vmcs_read32(VM_INSTRUCTION_ERROR);
6616 return 0;
6617 }
6aa8b732 6618
b9bf6882
XG		 6619 /*
6620 * Note:
6621 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6622 * delivery event since it indicates guest is accessing MMIO.
6623 * The vm-exit can be triggered again after return to guest that
6624 * will cause infinite loop.
6625 */
d77c26fc 6626 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6627 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6628 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6629 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6630 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6631 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6632 vcpu->run->internal.ndata = 2;
6633 vcpu->run->internal.data[0] = vectoring_info;
6634 vcpu->run->internal.data[1] = exit_reason;
6635 return 0;
6636 }
3b86cd99 6637
644d711a
NHE		 6638 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6639 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6640 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6641 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6642 vmx->soft_vnmi_blocked = 0;
3b86cd99 6643 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6644 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6645 /*
6646 * This CPU don't support us in finding the end of an
6647 * NMI-blocked window if the guest runs with IRQs
6648 * disabled. So we pull the trigger after 1 s of
6649 * futile waiting, but inform the user about this.
6650 */
6651 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6652 "state on VCPU %d after 1 s timeout\n",
6653 __func__, vcpu->vcpu_id);
6654 vmx->soft_vnmi_blocked = 0;
3b86cd99 6655 }
3b86cd99
JK		 6656 }
6657
6aa8b732
AK		 6658 if (exit_reason < kvm_vmx_max_exit_handlers
6659 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6660 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6661 else {
851ba692
AK		 6662 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6663 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6664 }
6665 return 0;
6666}
6667
95ba8273 6668static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6669{
95ba8273 6670 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6671 vmcs_write32(TPR_THRESHOLD, 0);
6672 return;
6673 }
6674
95ba8273 6675 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6676}
6677
8d14695f
YZ		 6678static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6679{
6680 u32 sec_exec_control;
6681
6682 /*
6683 * There is not point to enable virtualize x2apic without enable
6684 * apicv
6685 */
c7c9c56c
YZ		 6686 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6687 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6688 return;
6689
6690 if (!vm_need_tpr_shadow(vcpu->kvm))
6691 return;
6692
6693 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6694
6695 if (set) {
6696 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6697 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6698 } else {
6699 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6700 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6701 }
6702 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6703
6704 vmx_set_msr_bitmap(vcpu);
6705}
6706
c7c9c56c
YZ		 6707static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6708{
6709 u16 status;
6710 u8 old;
6711
6712 if (!vmx_vm_has_apicv(kvm))
6713 return;
6714
6715 if (isr == -1)
6716 isr = 0;
6717
6718 status = vmcs_read16(GUEST_INTR_STATUS);
6719 old = status >> 8;
6720 if (isr != old) {
6721 status &= 0xff;
6722 status |= isr << 8;
6723 vmcs_write16(GUEST_INTR_STATUS, status);
6724 }
6725}
6726
6727static void vmx_set_rvi(int vector)
6728{
6729 u16 status;
6730 u8 old;
6731
6732 status = vmcs_read16(GUEST_INTR_STATUS);
6733 old = (u8)status & 0xff;
6734 if ((u8)vector != old) {
6735 status &= ~0xff;
6736 status |= (u8)vector;
6737 vmcs_write16(GUEST_INTR_STATUS, status);
6738 }
6739}
6740
6741static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6742{
6743 if (max_irr == -1)
6744 return;
6745
6746 vmx_set_rvi(max_irr);
6747}
6748
6749static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6750{
3d81bc7e
YZ		 6751 if (!vmx_vm_has_apicv(vcpu->kvm))
6752 return;
6753
c7c9c56c
YZ		 6754 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6755 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6756 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6757 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6758}
6759
51aa01d1 6760static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6761{
00eba012
AK		 6762 u32 exit_intr_info;
6763
6764 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6765 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6766 return;
6767
c5ca8e57 6768 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6769 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6770
6771 /* Handle machine checks before interrupts are enabled */
00eba012 6772 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6773 kvm_machine_check();
6774
20f65983 6775 /* We need to handle NMIs before interrupts are enabled */
00eba012 6776 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6777 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6778 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6779 asm("int $2");
ff9d07a0
ZY		 6780 kvm_after_handle_nmi(&vmx->vcpu);
6781 }
51aa01d1 6782}
20f65983 6783
a547c6db
YZ		 6784static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6785{
6786 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6787
6788 /*
6789 * If external interrupt exists, IF bit is set in rflags/eflags on the
6790 * interrupt stack frame, and interrupt will be enabled on a return
6791 * from interrupt handler.
6792 */
6793 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6794 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6795 unsigned int vector;
6796 unsigned long entry;
6797 gate_desc *desc;
6798 struct vcpu_vmx *vmx = to_vmx(vcpu);
6799#ifdef CONFIG_X86_64
6800 unsigned long tmp;
6801#endif
6802
6803 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6804 desc = (gate_desc *)vmx->host_idt_base + vector;
6805 entry = gate_offset(*desc);
6806 asm volatile(
6807#ifdef CONFIG_X86_64
6808 "mov %%" _ASM_SP ", %[sp]\n\t"
6809 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6810 "push $%c[ss]\n\t"
6811 "push %[sp]\n\t"
6812#endif
6813 "pushf\n\t"
6814 "orl $0x200, (%%" _ASM_SP ")\n\t"
6815 __ASM_SIZE(push) " $%c[cs]\n\t"
6816 "call *%[entry]\n\t"
6817 :
6818#ifdef CONFIG_X86_64
6819 [sp]"=&r"(tmp)
6820#endif
6821 :
6822 [entry]"r"(entry),
6823 [ss]"i"(__KERNEL_DS),
6824 [cs]"i"(__KERNEL_CS)
6825 );
6826 } else
6827 local_irq_enable();
6828}
6829
51aa01d1
AK		 6830static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6831{
c5ca8e57 6832 u32 exit_intr_info;
51aa01d1
AK		 6833 bool unblock_nmi;
6834 u8 vector;
6835 bool idtv_info_valid;
6836
6837 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6838
cf393f75 6839 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6840 if (vmx->nmi_known_unmasked)
6841 return;
c5ca8e57
AK		 6842 /*
6843 * Can't use vmx->exit_intr_info since we're not sure what
6844 * the exit reason is.
6845 */
6846 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6847 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6848 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6849 /*
7b4a25cb 6850 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6851 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6852 * a guest IRET fault.
7b4a25cb
GN		 6853 * SDM 3: 23.2.2 (September 2008)
6854 * Bit 12 is undefined in any of the following cases:
6855 * If the VM exit sets the valid bit in the IDT-vectoring
6856 * information field.
6857 * If the VM exit is due to a double fault.
cf393f75 6858 */
7b4a25cb
GN		 6859 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6860 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6861 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6862 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6863 else
6864 vmx->nmi_known_unmasked =
6865 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6866 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6867 } else if (unlikely(vmx->soft_vnmi_blocked))
6868 vmx->vnmi_blocked_time +=
6869 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6870}
6871
3ab66e8a 6872static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6873 u32 idt_vectoring_info,
6874 int instr_len_field,
6875 int error_code_field)
51aa01d1 6876{
51aa01d1
AK		 6877 u8 vector;
6878 int type;
6879 bool idtv_info_valid;
6880
6881 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6882
3ab66e8a
JK		 6883 vcpu->arch.nmi_injected = false;
6884 kvm_clear_exception_queue(vcpu);
6885 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6886
6887 if (!idtv_info_valid)
6888 return;
6889
3ab66e8a 6890 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6891
668f612f
AK		 6892 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6893 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6894
64a7ec06 6895 switch (type) {
37b96e98 6896 case INTR_TYPE_NMI_INTR:
3ab66e8a 6897 vcpu->arch.nmi_injected = true;
668f612f 6898 /*
7b4a25cb 6899 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6900 * Clear bit "block by NMI" before VM entry if a NMI
6901 * delivery faulted.
668f612f 6902 */
3ab66e8a 6903 vmx_set_nmi_mask(vcpu, false);
37b96e98 6904 break;
37b96e98 6905 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6906 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6907 /* fall through */
6908 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6909 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6910 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6911 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6912 } else
3ab66e8a 6913 kvm_queue_exception(vcpu, vector);
37b96e98 6914 break;
66fd3f7f 6915 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6916 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6917 /* fall through */
37b96e98 6918 case INTR_TYPE_EXT_INTR:
3ab66e8a 6919 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6920 break;
6921 default:
6922 break;
f7d9238f 6923 }
cf393f75
AK		 6924}
6925
83422e17
AK		 6926static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6927{
3ab66e8a 6928 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6929 VM_EXIT_INSTRUCTION_LEN,
6930 IDT_VECTORING_ERROR_CODE);
6931}
6932
b463a6f7
AK		 6933static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6934{
3ab66e8a 6935 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6936 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6937 VM_ENTRY_INSTRUCTION_LEN,
6938 VM_ENTRY_EXCEPTION_ERROR_CODE);
6939
6940 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6941}
6942
d7cd9796
GN		 6943static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6944{
6945 int i, nr_msrs;
6946 struct perf_guest_switch_msr *msrs;
6947
6948 msrs = perf_guest_get_msrs(&nr_msrs);
6949
6950 if (!msrs)
6951 return;
6952
6953 for (i = 0; i < nr_msrs; i++)
6954 if (msrs[i].host == msrs[i].guest)
6955 clear_atomic_switch_msr(vmx, msrs[i].msr);
6956 else
6957 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6958 msrs[i].host);
6959}
6960
a3b5ba49 6961static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6962{
a2fa3e9f 6963 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6964 unsigned long debugctlmsr;
104f226b
AK		 6965
6966 /* Record the guest's net vcpu time for enforced NMI injections. */
6967 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6968 vmx->entry_time = ktime_get();
6969
6970 /* Don't enter VMX if guest state is invalid, let the exit handler
6971 start emulation until we arrive back to a valid state */
14168786 6972 if (vmx->emulation_required)
104f226b
AK		 6973 return;
6974
012f83cb
AG		 6975 if (vmx->nested.sync_shadow_vmcs) {
6976 copy_vmcs12_to_shadow(vmx);
6977 vmx->nested.sync_shadow_vmcs = false;
6978 }
6979
104f226b
AK		 6980 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6981 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6982 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6983 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6984
6985 /* When single-stepping over STI and MOV SS, we must clear the
6986 * corresponding interruptibility bits in the guest state. Otherwise
6987 * vmentry fails as it then expects bit 14 (BS) in pending debug
6988 * exceptions being set, but that's not correct for the guest debugging
6989 * case. */
6990 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6991 vmx_set_interrupt_shadow(vcpu, 0);
6992
d7cd9796 6993 atomic_switch_perf_msrs(vmx);
2a7921b7 6994 debugctlmsr = get_debugctlmsr();
d7cd9796 6995
d462b819 6996 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6997 asm(
6aa8b732 6998 /* Store host registers */
b188c81f
AK		 6999 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7000 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7001 "push %%" _ASM_CX " \n\t"
7002 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7003 "je 1f \n\t"
b188c81f 7004 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7005 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7006 "1: \n\t"
d3edefc0 7007 /* Reload cr2 if changed */
b188c81f
AK		 7008 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7009 "mov %%cr2, %%" _ASM_DX " \n\t"
7010 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7011 "je 2f \n\t"
b188c81f 7012 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7013 "2: \n\t"
6aa8b732 7014 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7015 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7016 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7017 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7018 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7019 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7020 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7021 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7022 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7023#ifdef CONFIG_X86_64
e08aa78a
AK		 7024 "mov %c[r8](%0), %%r8 \n\t"
7025 "mov %c[r9](%0), %%r9 \n\t"
7026 "mov %c[r10](%0), %%r10 \n\t"
7027 "mov %c[r11](%0), %%r11 \n\t"
7028 "mov %c[r12](%0), %%r12 \n\t"
7029 "mov %c[r13](%0), %%r13 \n\t"
7030 "mov %c[r14](%0), %%r14 \n\t"
7031 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7032#endif
b188c81f 7033 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7034
6aa8b732 7035 /* Enter guest mode */
83287ea4 7036 "jne 1f \n\t"
4ecac3fd 7037 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7038 "jmp 2f \n\t"
7039 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7040 "2: "
6aa8b732 7041 /* Save guest registers, load host registers, keep flags */
b188c81f 7042 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7043 "pop %0 \n\t"
b188c81f
AK		 7044 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7045 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7046 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7047 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7048 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7049 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7050 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7051#ifdef CONFIG_X86_64
e08aa78a
AK		 7052 "mov %%r8, %c[r8](%0) \n\t"
7053 "mov %%r9, %c[r9](%0) \n\t"
7054 "mov %%r10, %c[r10](%0) \n\t"
7055 "mov %%r11, %c[r11](%0) \n\t"
7056 "mov %%r12, %c[r12](%0) \n\t"
7057 "mov %%r13, %c[r13](%0) \n\t"
7058 "mov %%r14, %c[r14](%0) \n\t"
7059 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7060#endif
b188c81f
AK		 7061 "mov %%cr2, %%" _ASM_AX " \n\t"
7062 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7063
b188c81f 7064 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7065 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7066 ".pushsection .rodata \n\t"
7067 ".global vmx_return \n\t"
7068 "vmx_return: " _ASM_PTR " 2b \n\t"
7069 ".popsection"
e08aa78a 7070 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7071 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7072 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7073 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7074 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7075 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7076 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7077 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7078 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7079 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7080 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7081#ifdef CONFIG_X86_64
ad312c7c
ZX		 7082 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7083 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7084 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7085 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7086 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7087 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7088 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7089 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7090#endif
40712fae
AK		 7091 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7092 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7093 : "cc", "memory"
7094#ifdef CONFIG_X86_64
b188c81f 7095 , "rax", "rbx", "rdi", "rsi"
c2036300 7096 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7097#else
7098 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7099#endif
7100 );
6aa8b732 7101
2a7921b7
GN		 7102 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7103 if (debugctlmsr)
7104 update_debugctlmsr(debugctlmsr);
7105
aa67f609
AK		 7106#ifndef CONFIG_X86_64
7107 /*
7108 * The sysexit path does not restore ds/es, so we must set them to
7109 * a reasonable value ourselves.
7110 *
7111 * We can't defer this to vmx_load_host_state() since that function
7112 * may be executed in interrupt context, which saves and restore segments
7113 * around it, nullifying its effect.
7114 */
7115 loadsegment(ds, __USER_DS);
7116 loadsegment(es, __USER_DS);
7117#endif
7118
6de4f3ad 7119 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7120 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7121 | (1 << VCPU_EXREG_CPL)
aff48baa 7122 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7123 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7124 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7125 vcpu->arch.regs_dirty = 0;
7126
1155f76a
AK		 7127 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7128
d462b819 7129 vmx->loaded_vmcs->launched = 1;
1b6269db 7130
51aa01d1 7131 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7132 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7133
7134 vmx_complete_atomic_exit(vmx);
7135 vmx_recover_nmi_blocking(vmx);
cf393f75 7136 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7137}
7138
6aa8b732
AK		 7139static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7140{
fb3f0f51
RR		 7141 struct vcpu_vmx *vmx = to_vmx(vcpu);
7142
cdbecfc3 7143 free_vpid(vmx);
ec378aee 7144 free_nested(vmx);
d462b819 7145 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7146 kfree(vmx->guest_msrs);
7147 kvm_vcpu_uninit(vcpu);
a4770347 7148 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7149}
7150
fb3f0f51 7151static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7152{
fb3f0f51 7153 int err;
c16f862d 7154 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7155 int cpu;
6aa8b732 7156
a2fa3e9f 7157 if (!vmx)
fb3f0f51
RR		 7158 return ERR_PTR(-ENOMEM);
7159
2384d2b3
SY		 7160 allocate_vpid(vmx);
7161
fb3f0f51
RR		 7162 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7163 if (err)
7164 goto free_vcpu;
965b58a5 7165
a2fa3e9f 7166 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7167 err = -ENOMEM;
fb3f0f51 7168 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7169 goto uninit_vcpu;
7170 }
965b58a5 7171
d462b819
NHE		 7172 vmx->loaded_vmcs = &vmx->vmcs01;
7173 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7174 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7175 goto free_msrs;
d462b819
NHE		 7176 if (!vmm_exclusive)
7177 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7178 loaded_vmcs_init(vmx->loaded_vmcs);
7179 if (!vmm_exclusive)
7180 kvm_cpu_vmxoff();
a2fa3e9f 7181
15ad7146
AK		 7182 cpu = get_cpu();
7183 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7184 vmx->vcpu.cpu = cpu;
8b9cf98c 7185 err = vmx_vcpu_setup(vmx);
fb3f0f51 7186 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7187 put_cpu();
fb3f0f51
RR		 7188 if (err)
7189 goto free_vmcs;
a63cb560 7190 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7191 err = alloc_apic_access_page(kvm);
7192 if (err)
5e4a0b3c 7193 goto free_vmcs;
a63cb560 7194 }
fb3f0f51 7195
b927a3ce
SY		 7196 if (enable_ept) {
7197 if (!kvm->arch.ept_identity_map_addr)
7198 kvm->arch.ept_identity_map_addr =
7199 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7200 err = -ENOMEM;
b7ebfb05
SY		 7201 if (alloc_identity_pagetable(kvm) != 0)
7202 goto free_vmcs;
93ea5388
GN		 7203 if (!init_rmode_identity_map(kvm))
7204 goto free_vmcs;
b927a3ce 7205 }
b7ebfb05 7206
a9d30f33
NHE		 7207 vmx->nested.current_vmptr = -1ull;
7208 vmx->nested.current_vmcs12 = NULL;
7209
fb3f0f51
RR		 7210 return &vmx->vcpu;
7211
7212free_vmcs:
5f3fbc34 7213 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7214free_msrs:
fb3f0f51
RR		 7215 kfree(vmx->guest_msrs);
7216uninit_vcpu:
7217 kvm_vcpu_uninit(&vmx->vcpu);
7218free_vcpu:
cdbecfc3 7219 free_vpid(vmx);
a4770347 7220 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7221 return ERR_PTR(err);
6aa8b732
AK		 7222}
7223
002c7f7c
YS		 7224static void __init vmx_check_processor_compat(void *rtn)
7225{
7226 struct vmcs_config vmcs_conf;
7227
7228 *(int *)rtn = 0;
7229 if (setup_vmcs_config(&vmcs_conf) < 0)
7230 *(int *)rtn = -EIO;
7231 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7232 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7233 smp_processor_id());
7234 *(int *)rtn = -EIO;
7235 }
7236}
7237
67253af5
SY		 7238static int get_ept_level(void)
7239{
7240 return VMX_EPT_DEFAULT_GAW + 1;
7241}
7242
4b12f0de 7243static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7244{
4b12f0de
SY		 7245 u64 ret;
7246
522c68c4
SY		 7247 /* For VT-d and EPT combination
7248 * 1. MMIO: always map as UC
7249 * 2. EPT with VT-d:
7250 * a. VT-d without snooping control feature: can't guarantee the
7251 * result, try to trust guest.
7252 * b. VT-d with snooping control feature: snooping control feature of
7253 * VT-d engine can guarantee the cache correctness. Just set it
7254 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7255 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7256 * consistent with host MTRR
7257 */
4b12f0de
SY		 7258 if (is_mmio)
7259 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7260 else if (vcpu->kvm->arch.iommu_domain &&
7261 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7262 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7263 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7264 else
522c68c4 7265 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7266 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7267
7268 return ret;
64d4d521
SY		 7269}
7270
17cc3935 7271static int vmx_get_lpage_level(void)
344f414f 7272{
878403b7
SY		 7273 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7274 return PT_DIRECTORY_LEVEL;
7275 else
7276 /* For shadow and EPT supported 1GB page */
7277 return PT_PDPE_LEVEL;
344f414f
JR		 7278}
7279
0e851880
SY		 7280static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7281{
4e47c7a6
SY		 7282 struct kvm_cpuid_entry2 *best;
7283 struct vcpu_vmx *vmx = to_vmx(vcpu);
7284 u32 exec_control;
7285
7286 vmx->rdtscp_enabled = false;
7287 if (vmx_rdtscp_supported()) {
7288 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7289 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7290 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7291 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7292 vmx->rdtscp_enabled = true;
7293 else {
7294 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7295 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7296 exec_control);
7297 }
7298 }
7299 }
ad756a16 7300
ad756a16
MJ		 7301 /* Exposing INVPCID only when PCID is exposed */
7302 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7303 if (vmx_invpcid_supported() &&
4f977045 7304 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7305 guest_cpuid_has_pcid(vcpu)) {
29282fde 7306 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7307 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7308 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7309 exec_control);
7310 } else {
29282fde
TI		 7311 if (cpu_has_secondary_exec_ctrls()) {
7312 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7313 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7314 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7315 exec_control);
7316 }
ad756a16 7317 if (best)
4f977045 7318 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7319 }
0e851880
SY		 7320}
7321
d4330ef2
JR		 7322static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7323{
7b8050f5
NHE		 7324 if (func == 1 && nested)
7325 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7326}
7327
fe3ef05c
NHE		 7328/*
7329 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7330 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7331 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7332 * guest in a way that will both be appropriate to L1's requests, and our
7333 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7334 * function also has additional necessary side-effects, like setting various
7335 * vcpu->arch fields.
7336 */
7337static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7338{
7339 struct vcpu_vmx *vmx = to_vmx(vcpu);
7340 u32 exec_control;
7341
7342 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7343 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7344 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7345 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7346 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7347 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7348 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7349 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7350 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7351 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7352 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7353 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7354 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7355 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7356 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7357 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7358 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7359 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7360 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7361 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7362 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7363 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7364 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7365 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7366 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7367 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7368 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7369 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7370 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7371 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7372 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7373 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7374 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7375 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7376 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7377 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7378
7379 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7380 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7381 vmcs12->vm_entry_intr_info_field);
7382 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7383 vmcs12->vm_entry_exception_error_code);
7384 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7385 vmcs12->vm_entry_instruction_len);
7386 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7387 vmcs12->guest_interruptibility_info);
fe3ef05c 7388 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7389 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7390 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7391 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7392 vmcs12->guest_pending_dbg_exceptions);
7393 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7394 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7395
7396 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7397
7398 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7399 (vmcs_config.pin_based_exec_ctrl |
7400 vmcs12->pin_based_vm_exec_control));
7401
0238ea91
JK		 7402 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7403 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7404 vmcs12->vmx_preemption_timer_value);
7405
fe3ef05c
NHE		 7406 /*
7407 * Whether page-faults are trapped is determined by a combination of
7408 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7409 * If enable_ept, L0 doesn't care about page faults and we should
7410 * set all of these to L1's desires. However, if !enable_ept, L0 does
7411 * care about (at least some) page faults, and because it is not easy
7412 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7413 * to exit on each and every L2 page fault. This is done by setting
7414 * MASK=MATCH=0 and (see below) EB.PF=1.
7415 * Note that below we don't need special code to set EB.PF beyond the
7416 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7417 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7418 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7419 *
7420 * A problem with this approach (when !enable_ept) is that L1 may be
7421 * injected with more page faults than it asked for. This could have
7422 * caused problems, but in practice existing hypervisors don't care.
7423 * To fix this, we will need to emulate the PFEC checking (on the L1
7424 * page tables), using walk_addr(), when injecting PFs to L1.
7425 */
7426 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7427 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7428 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7429 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7430
7431 if (cpu_has_secondary_exec_ctrls()) {
7432 u32 exec_control = vmx_secondary_exec_control(vmx);
7433 if (!vmx->rdtscp_enabled)
7434 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7435 /* Take the following fields only from vmcs12 */
7436 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7437 if (nested_cpu_has(vmcs12,
7438 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7439 exec_control |= vmcs12->secondary_vm_exec_control;
7440
7441 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7442 /*
7443 * Translate L1 physical address to host physical
7444 * address for vmcs02. Keep the page pinned, so this
7445 * physical address remains valid. We keep a reference
7446 * to it so we can release it later.
7447 */
7448 if (vmx->nested.apic_access_page) /* shouldn't happen */
7449 nested_release_page(vmx->nested.apic_access_page);
7450 vmx->nested.apic_access_page =
7451 nested_get_page(vcpu, vmcs12->apic_access_addr);
7452 /*
7453 * If translation failed, no matter: This feature asks
7454 * to exit when accessing the given address, and if it
7455 * can never be accessed, this feature won't do
7456 * anything anyway.
7457 */
7458 if (!vmx->nested.apic_access_page)
7459 exec_control &=
7460 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7461 else
7462 vmcs_write64(APIC_ACCESS_ADDR,
7463 page_to_phys(vmx->nested.apic_access_page));
7464 }
7465
7466 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7467 }
7468
7469
7470 /*
7471 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7472 * Some constant fields are set here by vmx_set_constant_host_state().
7473 * Other fields are different per CPU, and will be set later when
7474 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7475 */
a547c6db 7476 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7477
7478 /*
7479 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7480 * entry, but only if the current (host) sp changed from the value
7481 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7482 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7483 * here we just force the write to happen on entry.
7484 */
7485 vmx->host_rsp = 0;
7486
7487 exec_control = vmx_exec_control(vmx); /* L0's desires */
7488 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7489 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7490 exec_control &= ~CPU_BASED_TPR_SHADOW;
7491 exec_control |= vmcs12->cpu_based_vm_exec_control;
7492 /*
7493 * Merging of IO and MSR bitmaps not currently supported.
7494 * Rather, exit every time.
7495 */
7496 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7497 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7498 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7499
7500 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7501
7502 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7503 * bitwise-or of what L1 wants to trap for L2, and what we want to
7504 * trap. Note that CR0.TS also needs updating - we do this later.
7505 */
7506 update_exception_bitmap(vcpu);
7507 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7508 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7509
7510 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7511 vmcs_write32(VM_EXIT_CONTROLS,
7512 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7513 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7514 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7515
7516 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7517 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7518 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7519 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7520
7521
7522 set_cr4_guest_host_mask(vmx);
7523
27fc51b2
NHE		 7524 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7525 vmcs_write64(TSC_OFFSET,
7526 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7527 else
7528 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7529
7530 if (enable_vpid) {
7531 /*
7532 * Trivially support vpid by letting L2s share their parent
7533 * L1's vpid. TODO: move to a more elaborate solution, giving
7534 * each L2 its own vpid and exposing the vpid feature to L1.
7535 */
7536 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7537 vmx_flush_tlb(vcpu);
7538 }
7539
7540 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7541 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7542 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7543 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7544 else
7545 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7546 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7547 vmx_set_efer(vcpu, vcpu->arch.efer);
7548
7549 /*
7550 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7551 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7552 * The CR0_READ_SHADOW is what L2 should have expected to read given
7553 * the specifications by L1; It's not enough to take
7554 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7555 * have more bits than L1 expected.
7556 */
7557 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7558 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7559
7560 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7561 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7562
7563 /* shadow page tables on either EPT or shadow page tables */
7564 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7565 kvm_mmu_reset_context(vcpu);
7566
7567 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7568 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7569}
7570
cd232ad0
NHE		 7571/*
7572 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7573 * for running an L2 nested guest.
7574 */
7575static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7576{
7577 struct vmcs12 *vmcs12;
7578 struct vcpu_vmx *vmx = to_vmx(vcpu);
7579 int cpu;
7580 struct loaded_vmcs *vmcs02;
384bb783 7581 bool ia32e;
cd232ad0
NHE		 7582
7583 if (!nested_vmx_check_permission(vcpu) ||
7584 !nested_vmx_check_vmcs12(vcpu))
7585 return 1;
7586
7587 skip_emulated_instruction(vcpu);
7588 vmcs12 = get_vmcs12(vcpu);
7589
012f83cb
AG		 7590 if (enable_shadow_vmcs)
7591 copy_shadow_to_vmcs12(vmx);
7592
7c177938
NHE		 7593 /*
7594 * The nested entry process starts with enforcing various prerequisites
7595 * on vmcs12 as required by the Intel SDM, and act appropriately when
7596 * they fail: As the SDM explains, some conditions should cause the
7597 * instruction to fail, while others will cause the instruction to seem
7598 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7599 * To speed up the normal (success) code path, we should avoid checking
7600 * for misconfigurations which will anyway be caught by the processor
7601 * when using the merged vmcs02.
7602 */
7603 if (vmcs12->launch_state == launch) {
7604 nested_vmx_failValid(vcpu,
7605 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7606 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7607 return 1;
7608 }
7609
26539bd0
PB		 7610 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7611 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7612 return 1;
7613 }
7614
7c177938
NHE		 7615 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7616 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7617 /*TODO: Also verify bits beyond physical address width are 0*/
7618 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7619 return 1;
7620 }
7621
7622 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7623 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7624 /*TODO: Also verify bits beyond physical address width are 0*/
7625 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7626 return 1;
7627 }
7628
7629 if (vmcs12->vm_entry_msr_load_count > 0 ||
7630 vmcs12->vm_exit_msr_load_count > 0 ||
7631 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7632 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7633 __func__);
7c177938
NHE		 7634 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7635 return 1;
7636 }
7637
7638 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7639 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7640 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7641 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7642 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7643 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7644 !vmx_control_verify(vmcs12->vm_exit_controls,
7645 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7646 !vmx_control_verify(vmcs12->vm_entry_controls,
7647 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7648 {
7649 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7650 return 1;
7651 }
7652
7653 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7654 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7655 nested_vmx_failValid(vcpu,
7656 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7657 return 1;
7658 }
7659
7660 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7661 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7662 nested_vmx_entry_failure(vcpu, vmcs12,
7663 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7664 return 1;
7665 }
7666 if (vmcs12->vmcs_link_pointer != -1ull) {
7667 nested_vmx_entry_failure(vcpu, vmcs12,
7668 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7669 return 1;
7670 }
7671
384bb783 7672 /*
cb0c8cda 7673 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7674 * are performed on the field for the IA32_EFER MSR:
7675 * - Bits reserved in the IA32_EFER MSR must be 0.
7676 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7677 * the IA-32e mode guest VM-exit control. It must also be identical
7678 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7679 * CR0.PG) is 1.
7680 */
7681 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7682 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7683 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7684 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7685 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7686 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7687 nested_vmx_entry_failure(vcpu, vmcs12,
7688 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7689 return 1;
7690 }
7691 }
7692
7693 /*
7694 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7695 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7696 * the values of the LMA and LME bits in the field must each be that of
7697 * the host address-space size VM-exit control.
7698 */
7699 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7700 ia32e = (vmcs12->vm_exit_controls &
7701 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7702 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7703 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7704 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7705 nested_vmx_entry_failure(vcpu, vmcs12,
7706 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7707 return 1;
7708 }
7709 }
7710
7c177938
NHE		 7711 /*
7712 * We're finally done with prerequisite checking, and can start with
7713 * the nested entry.
7714 */
7715
cd232ad0
NHE		 7716 vmcs02 = nested_get_current_vmcs02(vmx);
7717 if (!vmcs02)
7718 return -ENOMEM;
7719
7720 enter_guest_mode(vcpu);
7721
7722 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7723
7724 cpu = get_cpu();
7725 vmx->loaded_vmcs = vmcs02;
7726 vmx_vcpu_put(vcpu);
7727 vmx_vcpu_load(vcpu, cpu);
7728 vcpu->cpu = cpu;
7729 put_cpu();
7730
36c3cc42
JK		 7731 vmx_segment_cache_clear(vmx);
7732
cd232ad0
NHE		 7733 vmcs12->launch_state = 1;
7734
7735 prepare_vmcs02(vcpu, vmcs12);
7736
7737 /*
7738 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7739 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7740 * returned as far as L1 is concerned. It will only return (and set
7741 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7742 */
7743 return 1;
7744}
7745
4704d0be
NHE		 7746/*
7747 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7748 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7749 * This function returns the new value we should put in vmcs12.guest_cr0.
7750 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7751 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7752 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7753 * didn't trap the bit, because if L1 did, so would L0).
7754 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7755 * been modified by L2, and L1 knows it. So just leave the old value of
7756 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7757 * isn't relevant, because if L0 traps this bit it can set it to anything.
7758 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7759 * changed these bits, and therefore they need to be updated, but L0
7760 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7761 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7762 */
7763static inline unsigned long
7764vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7765{
7766 return
7767 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7768 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7769 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7770 vcpu->arch.cr0_guest_owned_bits));
7771}
7772
7773static inline unsigned long
7774vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7775{
7776 return
7777 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7778 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7779 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7780 vcpu->arch.cr4_guest_owned_bits));
7781}
7782
5f3d5799
JK		 7783static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7784 struct vmcs12 *vmcs12)
7785{
7786 u32 idt_vectoring;
7787 unsigned int nr;
7788
7789 if (vcpu->arch.exception.pending) {
7790 nr = vcpu->arch.exception.nr;
7791 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7792
7793 if (kvm_exception_is_soft(nr)) {
7794 vmcs12->vm_exit_instruction_len =
7795 vcpu->arch.event_exit_inst_len;
7796 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7797 } else
7798 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7799
7800 if (vcpu->arch.exception.has_error_code) {
7801 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7802 vmcs12->idt_vectoring_error_code =
7803 vcpu->arch.exception.error_code;
7804 }
7805
7806 vmcs12->idt_vectoring_info_field = idt_vectoring;
7807 } else if (vcpu->arch.nmi_pending) {
7808 vmcs12->idt_vectoring_info_field =
7809 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7810 } else if (vcpu->arch.interrupt.pending) {
7811 nr = vcpu->arch.interrupt.nr;
7812 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7813
7814 if (vcpu->arch.interrupt.soft) {
7815 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7816 vmcs12->vm_entry_instruction_len =
7817 vcpu->arch.event_exit_inst_len;
7818 } else
7819 idt_vectoring |= INTR_TYPE_EXT_INTR;
7820
7821 vmcs12->idt_vectoring_info_field = idt_vectoring;
7822 }
7823}
7824
4704d0be
NHE		 7825/*
7826 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7827 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7828 * and this function updates it to reflect the changes to the guest state while
7829 * L2 was running (and perhaps made some exits which were handled directly by L0
7830 * without going back to L1), and to reflect the exit reason.
7831 * Note that we do not have to copy here all VMCS fields, just those that
7832 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7833 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7834 * which already writes to vmcs12 directly.
7835 */
733568f9 7836static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7837{
7838 /* update guest state fields: */
7839 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7840 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7841
7842 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7843 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7844 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7845 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7846
7847 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7848 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7849 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7850 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7851 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7852 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7853 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7854 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7855 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7856 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7857 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7858 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7859 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7860 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7861 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7862 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7863 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7864 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7865 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7866 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7867 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7868 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7869 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7870 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7871 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7872 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7873 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7874 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7875 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7876 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7877 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7878 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7879 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7880 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7881 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7882 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7883
4704d0be
NHE		 7884 vmcs12->guest_interruptibility_info =
7885 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7886 vmcs12->guest_pending_dbg_exceptions =
7887 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7888
c18911a2
JK		 7889 vmcs12->vm_entry_controls =
7890 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7891 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7892
4704d0be
NHE		 7893 /* TODO: These cannot have changed unless we have MSR bitmaps and
7894 * the relevant bit asks not to trap the change */
7895 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7896 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7897 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7898 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7899 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7900 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7901
7902 /* update exit information fields: */
7903
957c897e 7904 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7905 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7906
7907 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7908 if ((vmcs12->vm_exit_intr_info &
7909 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7910 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7911 vmcs12->vm_exit_intr_error_code =
7912 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7913 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7914 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7915 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7916
5f3d5799
JK		 7917 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7918 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7919 * instead of reading the real value. */
4704d0be 7920 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7921
7922 /*
7923 * Transfer the event that L0 or L1 may wanted to inject into
7924 * L2 to IDT_VECTORING_INFO_FIELD.
7925 */
7926 vmcs12_save_pending_event(vcpu, vmcs12);
7927 }
7928
7929 /*
7930 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7931 * preserved above and would only end up incorrectly in L1.
7932 */
7933 vcpu->arch.nmi_injected = false;
7934 kvm_clear_exception_queue(vcpu);
7935 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7936}
7937
7938/*
7939 * A part of what we need to when the nested L2 guest exits and we want to
7940 * run its L1 parent, is to reset L1's guest state to the host state specified
7941 * in vmcs12.
7942 * This function is to be called not only on normal nested exit, but also on
7943 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7944 * Failures During or After Loading Guest State").
7945 * This function should be called when the active VMCS is L1's (vmcs01).
7946 */
733568f9
JK		 7947static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7948 struct vmcs12 *vmcs12)
4704d0be
NHE		 7949{
7950 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7951 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 7952 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 7953 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7954 else
7955 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7956 vmx_set_efer(vcpu, vcpu->arch.efer);
7957
7958 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7959 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 7960 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 7961 /*
7962 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7963 * actually changed, because it depends on the current state of
7964 * fpu_active (which may have changed).
7965 * Note that vmx_set_cr0 refers to efer set above.
7966 */
7967 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7968 /*
7969 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7970 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7971 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7972 */
7973 update_exception_bitmap(vcpu);
7974 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7975 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7976
7977 /*
7978 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7979 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7980 */
7981 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7982 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7983
7984 /* shadow page tables on either EPT or shadow page tables */
7985 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7986 kvm_mmu_reset_context(vcpu);
7987
7988 if (enable_vpid) {
7989 /*
7990 * Trivially support vpid by letting L2s share their parent
7991 * L1's vpid. TODO: move to a more elaborate solution, giving
7992 * each L2 its own vpid and exposing the vpid feature to L1.
7993 */
7994 vmx_flush_tlb(vcpu);
7995 }
7996
7997
7998 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7999 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8000 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8001 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8002 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
8003 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
8004 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
8005 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
8006 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
8007 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
8008 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
8009 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
8010 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
8011 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
8012 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
8013
8014 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8015 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8016 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8017 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8018 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 8019
8020 kvm_set_dr(vcpu, 7, 0x400);
8021 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8022}
8023
8024/*
8025 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8026 * and modify vmcs12 to make it see what it would expect to see there if
8027 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8028 */
8029static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8030{
8031 struct vcpu_vmx *vmx = to_vmx(vcpu);
8032 int cpu;
8033 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8034
5f3d5799
JK		 8035 /* trying to cancel vmlaunch/vmresume is a bug */
8036 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8037
4704d0be
NHE		 8038 leave_guest_mode(vcpu);
8039 prepare_vmcs12(vcpu, vmcs12);
8040
8041 cpu = get_cpu();
8042 vmx->loaded_vmcs = &vmx->vmcs01;
8043 vmx_vcpu_put(vcpu);
8044 vmx_vcpu_load(vcpu, cpu);
8045 vcpu->cpu = cpu;
8046 put_cpu();
8047
36c3cc42
JK		 8048 vmx_segment_cache_clear(vmx);
8049
4704d0be
NHE		 8050 /* if no vmcs02 cache requested, remove the one we used */
8051 if (VMCS02_POOL_SIZE == 0)
8052 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8053
8054 load_vmcs12_host_state(vcpu, vmcs12);
8055
27fc51b2 8056 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8057 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8058
8059 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8060 vmx->host_rsp = 0;
8061
8062 /* Unpin physical memory we referred to in vmcs02 */
8063 if (vmx->nested.apic_access_page) {
8064 nested_release_page(vmx->nested.apic_access_page);
8065 vmx->nested.apic_access_page = 0;
8066 }
8067
8068 /*
8069 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8070 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8071 * success or failure flag accordingly.
8072 */
8073 if (unlikely(vmx->fail)) {
8074 vmx->fail = 0;
8075 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8076 } else
8077 nested_vmx_succeed(vcpu);
012f83cb
AG		 8078 if (enable_shadow_vmcs)
8079 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8080}
8081
7c177938
NHE		 8082/*
8083 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8084 * 23.7 "VM-entry failures during or after loading guest state" (this also
8085 * lists the acceptable exit-reason and exit-qualification parameters).
8086 * It should only be called before L2 actually succeeded to run, and when
8087 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8088 */
8089static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8090 struct vmcs12 *vmcs12,
8091 u32 reason, unsigned long qualification)
8092{
8093 load_vmcs12_host_state(vcpu, vmcs12);
8094 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8095 vmcs12->exit_qualification = qualification;
8096 nested_vmx_succeed(vcpu);
012f83cb
AG		 8097 if (enable_shadow_vmcs)
8098 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8099}
8100
8a76d7f2
JR		 8101static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8102 struct x86_instruction_info *info,
8103 enum x86_intercept_stage stage)
8104{
8105 return X86EMUL_CONTINUE;
8106}
8107
cbdd1bea 8108static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8109 .cpu_has_kvm_support = cpu_has_kvm_support,
8110 .disabled_by_bios = vmx_disabled_by_bios,
8111 .hardware_setup = hardware_setup,
8112 .hardware_unsetup = hardware_unsetup,
002c7f7c 8113 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8114 .hardware_enable = hardware_enable,
8115 .hardware_disable = hardware_disable,
04547156 8116 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8117
8118 .vcpu_create = vmx_create_vcpu,
8119 .vcpu_free = vmx_free_vcpu,
04d2cc77 8120 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8121
04d2cc77 8122 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8123 .vcpu_load = vmx_vcpu_load,
8124 .vcpu_put = vmx_vcpu_put,
8125
c8639010 8126 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8127 .get_msr = vmx_get_msr,
8128 .set_msr = vmx_set_msr,
8129 .get_segment_base = vmx_get_segment_base,
8130 .get_segment = vmx_get_segment,
8131 .set_segment = vmx_set_segment,
2e4d2653 8132 .get_cpl = vmx_get_cpl,
6aa8b732 8133 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8134 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8135 .decache_cr3 = vmx_decache_cr3,
25c4c276 8136 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8137 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8138 .set_cr3 = vmx_set_cr3,
8139 .set_cr4 = vmx_set_cr4,
6aa8b732 8140 .set_efer = vmx_set_efer,
6aa8b732
AK		 8141 .get_idt = vmx_get_idt,
8142 .set_idt = vmx_set_idt,
8143 .get_gdt = vmx_get_gdt,
8144 .set_gdt = vmx_set_gdt,
020df079 8145 .set_dr7 = vmx_set_dr7,
5fdbf976 8146 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8147 .get_rflags = vmx_get_rflags,
8148 .set_rflags = vmx_set_rflags,
ebcbab4c 8149 .fpu_activate = vmx_fpu_activate,
02daab21 8150 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8151
8152 .tlb_flush = vmx_flush_tlb,
6aa8b732 8153
6aa8b732 8154 .run = vmx_vcpu_run,
6062d012 8155 .handle_exit = vmx_handle_exit,
6aa8b732 8156 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8157 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8158 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8159 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8160 .set_irq = vmx_inject_irq,
95ba8273 8161 .set_nmi = vmx_inject_nmi,
298101da 8162 .queue_exception = vmx_queue_exception,
b463a6f7 8163 .cancel_injection = vmx_cancel_injection,
78646121 8164 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8165 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8166 .get_nmi_mask = vmx_get_nmi_mask,
8167 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8168 .enable_nmi_window = enable_nmi_window,
8169 .enable_irq_window = enable_irq_window,
8170 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8171 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8172 .vm_has_apicv = vmx_vm_has_apicv,
8173 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8174 .hwapic_irr_update = vmx_hwapic_irr_update,
8175 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8176 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8177 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8178
cbc94022 8179 .set_tss_addr = vmx_set_tss_addr,
67253af5 8180 .get_tdp_level = get_ept_level,
4b12f0de 8181 .get_mt_mask = vmx_get_mt_mask,
229456fc 8182
586f9607 8183 .get_exit_info = vmx_get_exit_info,
586f9607 8184
17cc3935 8185 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8186
8187 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8188
8189 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8190 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8191
8192 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8193
8194 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8195
4051b188 8196 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8197 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8198 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8199 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8200 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8201 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8202
8203 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8204
8205 .check_intercept = vmx_check_intercept,
a547c6db 8206 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8207};
8208
8209static int __init vmx_init(void)
8210{
8d14695f 8211 int r, i, msr;
26bb0981
AK		 8212
8213 rdmsrl_safe(MSR_EFER, &host_efer);
8214
8215 for (i = 0; i < NR_VMX_MSR; ++i)
8216 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8217
3e7c73e9 8218 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8219 if (!vmx_io_bitmap_a)
8220 return -ENOMEM;
8221
2106a548
GC		 8222 r = -ENOMEM;
8223
3e7c73e9 8224 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8225 if (!vmx_io_bitmap_b)
fdef3ad1 8226 goto out;
fdef3ad1 8227
5897297b 8228 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8229 if (!vmx_msr_bitmap_legacy)
25c5f225 8230 goto out1;
2106a548 8231
8d14695f
YZ		 8232 vmx_msr_bitmap_legacy_x2apic =
8233 (unsigned long *)__get_free_page(GFP_KERNEL);
8234 if (!vmx_msr_bitmap_legacy_x2apic)
8235 goto out2;
25c5f225 8236
5897297b 8237 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8238 if (!vmx_msr_bitmap_longmode)
8d14695f 8239 goto out3;
2106a548 8240
8d14695f
YZ		 8241 vmx_msr_bitmap_longmode_x2apic =
8242 (unsigned long *)__get_free_page(GFP_KERNEL);
8243 if (!vmx_msr_bitmap_longmode_x2apic)
8244 goto out4;
4607c2d7
AG		 8245 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8246 if (!vmx_vmread_bitmap)
8247 goto out5;
8248
8249 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8250 if (!vmx_vmwrite_bitmap)
8251 goto out6;
8252
8253 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8254 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8255 /* shadowed read/write fields */
8256 for (i = 0; i < max_shadow_read_write_fields; i++) {
8257 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8258 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8259 }
8260 /* shadowed read only fields */
8261 for (i = 0; i < max_shadow_read_only_fields; i++)
8262 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8263
fdef3ad1
HQ		 8264 /*
8265 * Allow direct access to the PC debug port (it is often used for I/O
8266 * delays, but the vmexits simply slow things down).
8267 */
3e7c73e9
AK		 8268 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8269 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8270
3e7c73e9 8271 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8272
5897297b
AK		 8273 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8274 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8275
2384d2b3
SY		 8276 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8277
0ee75bea
AK		 8278 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8279 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8280 if (r)
4607c2d7 8281 goto out7;
25c5f225 8282
8f536b76
ZY		 8283#ifdef CONFIG_KEXEC
8284 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8285 crash_vmclear_local_loaded_vmcss);
8286#endif
8287
5897297b
AK		 8288 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8289 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8290 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8291 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8292 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8293 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8294 memcpy(vmx_msr_bitmap_legacy_x2apic,
8295 vmx_msr_bitmap_legacy, PAGE_SIZE);
8296 memcpy(vmx_msr_bitmap_longmode_x2apic,
8297 vmx_msr_bitmap_longmode, PAGE_SIZE);
8298
01e439be 8299 if (enable_apicv) {
8d14695f
YZ		 8300 for (msr = 0x800; msr <= 0x8ff; msr++)
8301 vmx_disable_intercept_msr_read_x2apic(msr);
8302
8303 /* According SDM, in x2apic mode, the whole id reg is used.
8304 * But in KVM, it only use the highest eight bits. Need to
8305 * intercept it */
8306 vmx_enable_intercept_msr_read_x2apic(0x802);
8307 /* TMCCT */
8308 vmx_enable_intercept_msr_read_x2apic(0x839);
8309 /* TPR */
8310 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8311 /* EOI */
8312 vmx_disable_intercept_msr_write_x2apic(0x80b);
8313 /* SELF-IPI */
8314 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8315 }
fdef3ad1 8316
089d034e 8317 if (enable_ept) {
3f6d8c8a
XH		 8318 kvm_mmu_set_mask_ptes(0ull,
8319 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8320 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8321 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8322 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8323 kvm_enable_tdp();
8324 } else
8325 kvm_disable_tdp();
1439442c 8326
fdef3ad1
HQ		 8327 return 0;
8328
4607c2d7
AG		 8329out7:
8330 free_page((unsigned long)vmx_vmwrite_bitmap);
8331out6:
8332 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8333out5:
8334 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8335out4:
5897297b 8336 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8337out3:
8338 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8339out2:
5897297b 8340 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8341out1:
3e7c73e9 8342 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8343out:
3e7c73e9 8344 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8345 return r;
6aa8b732
AK		 8346}
8347
8348static void __exit vmx_exit(void)
8349{
8d14695f
YZ		 8350 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8351 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8352 free_page((unsigned long)vmx_msr_bitmap_legacy);
8353 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8354 free_page((unsigned long)vmx_io_bitmap_b);
8355 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8356 free_page((unsigned long)vmx_vmwrite_bitmap);
8357 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8358
8f536b76
ZY		 8359#ifdef CONFIG_KEXEC
8360 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8361 synchronize_rcu();
8362#endif
8363
cb498ea2 8364 kvm_exit();
6aa8b732
AK		 8365}
8366
8367module_init(vmx_init)
8368module_exit(vmx_exit)
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