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Advertise the support of EPT to the L1 guest, through the appropriate MSR.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
aff48baa 719static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 720static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 721static void vmx_set_segment(struct kvm_vcpu *vcpu,
722 struct kvm_segment *var, int seg);
723static void vmx_get_segment(struct kvm_vcpu *vcpu,
724 struct kvm_segment *var, int seg);
d99e4152
GN		 725static bool guest_state_valid(struct kvm_vcpu *vcpu);
726static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 727static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 728static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 729static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 730
6aa8b732
AK		 731static DEFINE_PER_CPU(struct vmcs *, vmxarea);
732static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 733/*
734 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
735 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
736 */
737static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 738static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 739
3e7c73e9
AK		 740static unsigned long *vmx_io_bitmap_a;
741static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 742static unsigned long *vmx_msr_bitmap_legacy;
743static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 744static unsigned long *vmx_msr_bitmap_legacy_x2apic;
745static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 746static unsigned long *vmx_vmread_bitmap;
747static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 748
110312c8 749static bool cpu_has_load_ia32_efer;
8bf00a52 750static bool cpu_has_load_perf_global_ctrl;
110312c8 751
2384d2b3
SY		 752static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
753static DEFINE_SPINLOCK(vmx_vpid_lock);
754
1c3d14fe 755static struct vmcs_config {
6aa8b732
AK		 756 int size;
757 int order;
758 u32 revision_id;
1c3d14fe
YS		 759 u32 pin_based_exec_ctrl;
760 u32 cpu_based_exec_ctrl;
f78e0e2e 761 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 762 u32 vmexit_ctrl;
763 u32 vmentry_ctrl;
764} vmcs_config;
6aa8b732 765
efff9e53 766static struct vmx_capability {
d56f546d
SY		 767 u32 ept;
768 u32 vpid;
769} vmx_capability;
770
6aa8b732
AK		 771#define VMX_SEGMENT_FIELD(seg) \
772 [VCPU_SREG_##seg] = { \
773 .selector = GUEST_##seg##_SELECTOR, \
774 .base = GUEST_##seg##_BASE, \
775 .limit = GUEST_##seg##_LIMIT, \
776 .ar_bytes = GUEST_##seg##_AR_BYTES, \
777 }
778
772e0318 779static const struct kvm_vmx_segment_field {
6aa8b732
AK		 780 unsigned selector;
781 unsigned base;
782 unsigned limit;
783 unsigned ar_bytes;
784} kvm_vmx_segment_fields[] = {
785 VMX_SEGMENT_FIELD(CS),
786 VMX_SEGMENT_FIELD(DS),
787 VMX_SEGMENT_FIELD(ES),
788 VMX_SEGMENT_FIELD(FS),
789 VMX_SEGMENT_FIELD(GS),
790 VMX_SEGMENT_FIELD(SS),
791 VMX_SEGMENT_FIELD(TR),
792 VMX_SEGMENT_FIELD(LDTR),
793};
794
26bb0981
AK		 795static u64 host_efer;
796
6de4f3ad
AK		 797static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
798
4d56c8a7 799/*
8c06585d 800 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 801 * away by decrementing the array size.
802 */
6aa8b732 803static const u32 vmx_msr_index[] = {
05b3e0c2 804#ifdef CONFIG_X86_64
44ea2b17 805 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 806#endif
8c06585d 807 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 808};
9d8f549d 809#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 810
31299944 811static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 812{
813 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
814 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 815 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 816}
817
31299944 818static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 819{
820 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
821 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 822 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 823}
824
31299944 825static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 830}
831
31299944 832static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
835 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
836}
837
31299944 838static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 839{
840 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
841 INTR_INFO_VALID_MASK)) ==
842 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
843}
844
31299944 845static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 846{
04547156 847 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 848}
849
31299944 850static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 851{
04547156 852 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 853}
854
31299944 855static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 856{
04547156 857 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 858}
859
31299944 860static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 861{
04547156
SY		 862 return vmcs_config.cpu_based_exec_ctrl &
863 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 864}
865
774ead3a 866static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 867{
04547156
SY		 868 return vmcs_config.cpu_based_2nd_exec_ctrl &
869 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
870}
871
8d14695f
YZ		 872static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
873{
874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
876}
877
83d4c286
YZ		 878static inline bool cpu_has_vmx_apic_register_virt(void)
879{
880 return vmcs_config.cpu_based_2nd_exec_ctrl &
881 SECONDARY_EXEC_APIC_REGISTER_VIRT;
882}
883
c7c9c56c
YZ		 884static inline bool cpu_has_vmx_virtual_intr_delivery(void)
885{
886 return vmcs_config.cpu_based_2nd_exec_ctrl &
887 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
888}
889
01e439be
YZ		 890static inline bool cpu_has_vmx_posted_intr(void)
891{
892 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
893}
894
895static inline bool cpu_has_vmx_apicv(void)
896{
897 return cpu_has_vmx_apic_register_virt() &&
898 cpu_has_vmx_virtual_intr_delivery() &&
899 cpu_has_vmx_posted_intr();
900}
901
04547156
SY		 902static inline bool cpu_has_vmx_flexpriority(void)
903{
904 return cpu_has_vmx_tpr_shadow() &&
905 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 906}
907
e799794e
MT		 908static inline bool cpu_has_vmx_ept_execute_only(void)
909{
31299944 910 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 911}
912
913static inline bool cpu_has_vmx_eptp_uncacheable(void)
914{
31299944 915 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 916}
917
918static inline bool cpu_has_vmx_eptp_writeback(void)
919{
31299944 920 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 921}
922
923static inline bool cpu_has_vmx_ept_2m_page(void)
924{
31299944 925 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 926}
927
878403b7
SY		 928static inline bool cpu_has_vmx_ept_1g_page(void)
929{
31299944 930 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 931}
932
4bc9b982
SY		 933static inline bool cpu_has_vmx_ept_4levels(void)
934{
935 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
936}
937
83c3a331
XH		 938static inline bool cpu_has_vmx_ept_ad_bits(void)
939{
940 return vmx_capability.ept & VMX_EPT_AD_BIT;
941}
942
31299944 943static inline bool cpu_has_vmx_invept_context(void)
d56f546d 944{
31299944 945 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 946}
947
31299944 948static inline bool cpu_has_vmx_invept_global(void)
d56f546d 949{
31299944 950 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 951}
952
518c8aee
GJ		 953static inline bool cpu_has_vmx_invvpid_single(void)
954{
955 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
956}
957
b9d762fa
GJ		 958static inline bool cpu_has_vmx_invvpid_global(void)
959{
960 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
961}
962
31299944 963static inline bool cpu_has_vmx_ept(void)
d56f546d 964{
04547156
SY		 965 return vmcs_config.cpu_based_2nd_exec_ctrl &
966 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 967}
968
31299944 969static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 970{
971 return vmcs_config.cpu_based_2nd_exec_ctrl &
972 SECONDARY_EXEC_UNRESTRICTED_GUEST;
973}
974
31299944 975static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 976{
977 return vmcs_config.cpu_based_2nd_exec_ctrl &
978 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
979}
980
31299944 981static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 982{
6d3e435e 983 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 984}
985
31299944 986static inline bool cpu_has_vmx_vpid(void)
2384d2b3 987{
04547156
SY		 988 return vmcs_config.cpu_based_2nd_exec_ctrl &
989 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 990}
991
31299944 992static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 993{
994 return vmcs_config.cpu_based_2nd_exec_ctrl &
995 SECONDARY_EXEC_RDTSCP;
996}
997
ad756a16
MJ		 998static inline bool cpu_has_vmx_invpcid(void)
999{
1000 return vmcs_config.cpu_based_2nd_exec_ctrl &
1001 SECONDARY_EXEC_ENABLE_INVPCID;
1002}
1003
31299944 1004static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1005{
1006 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1007}
1008
f5f48ee1
SY		 1009static inline bool cpu_has_vmx_wbinvd_exit(void)
1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_WBINVD_EXITING;
1013}
1014
abc4fc58
AG		 1015static inline bool cpu_has_vmx_shadow_vmcs(void)
1016{
1017 u64 vmx_msr;
1018 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1019 /* check if the cpu supports writing r/o exit information fields */
1020 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1021 return false;
1022
1023 return vmcs_config.cpu_based_2nd_exec_ctrl &
1024 SECONDARY_EXEC_SHADOW_VMCS;
1025}
1026
04547156
SY		 1027static inline bool report_flexpriority(void)
1028{
1029 return flexpriority_enabled;
1030}
1031
fe3ef05c
NHE		 1032static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1033{
1034 return vmcs12->cpu_based_vm_exec_control & bit;
1035}
1036
1037static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1038{
1039 return (vmcs12->cpu_based_vm_exec_control &
1040 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1041 (vmcs12->secondary_vm_exec_control & bit);
1042}
1043
644d711a
NHE		 1044static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1045 struct kvm_vcpu *vcpu)
1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1062static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063 struct vmcs12 *vmcs12,
1064 u32 reason, unsigned long qualification);
1065
8b9cf98c 1066static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1067{
1068 int i;
1069
a2fa3e9f 1070 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1071 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1072 return i;
1073 return -1;
1074}
1075
2384d2b3
SY		 1076static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077{
1078 struct {
1079 u64 vpid : 16;
1080 u64 rsvd : 48;
1081 u64 gva;
1082 } operand = { vpid, 0, gva };
1083
4ecac3fd 1084 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:"
1087 : : "a"(&operand), "c"(ext) : "cc", "memory");
1088}
1089
1439442c
SY		 1090static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091{
1092 struct {
1093 u64 eptp, gpa;
1094 } operand = {eptp, gpa};
1095
4ecac3fd 1096 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1097 /* CF==1 or ZF==1 --> rc = -1 */
1098 "; ja 1f ; ud2 ; 1:\n"
1099 : : "a" (&operand), "c" (ext) : "cc", "memory");
1100}
1101
26bb0981 1102static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1103{
1104 int i;
1105
8b9cf98c 1106 i = __find_msr_index(vmx, msr);
a75beee6 1107 if (i >= 0)
a2fa3e9f 1108 return &vmx->guest_msrs[i];
8b6d44c7 1109 return NULL;
7725f0ba
AK		 1110}
1111
6aa8b732
AK		 1112static void vmcs_clear(struct vmcs *vmcs)
1113{
1114 u64 phys_addr = __pa(vmcs);
1115 u8 error;
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1118 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1119 : "cc", "memory");
1120 if (error)
1121 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122 vmcs, phys_addr);
1123}
1124
d462b819
NHE		 1125static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126{
1127 vmcs_clear(loaded_vmcs->vmcs);
1128 loaded_vmcs->cpu = -1;
1129 loaded_vmcs->launched = 0;
1130}
1131
7725b894
DX		 1132static void vmcs_load(struct vmcs *vmcs)
1133{
1134 u64 phys_addr = __pa(vmcs);
1135 u8 error;
1136
1137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1138 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1139 : "cc", "memory");
1140 if (error)
2844d849 1141 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1142 vmcs, phys_addr);
1143}
1144
8f536b76
ZY		 1145#ifdef CONFIG_KEXEC
1146/*
1147 * This bitmap is used to indicate whether the vmclear
1148 * operation is enabled on all cpus. All disabled by
1149 * default.
1150 */
1151static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153static inline void crash_enable_local_vmclear(int cpu)
1154{
1155 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156}
1157
1158static inline void crash_disable_local_vmclear(int cpu)
1159{
1160 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161}
1162
1163static inline int crash_local_vmclear_enabled(int cpu)
1164{
1165 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166}
1167
1168static void crash_vmclear_local_loaded_vmcss(void)
1169{
1170 int cpu = raw_smp_processor_id();
1171 struct loaded_vmcs *v;
1172
1173 if (!crash_local_vmclear_enabled(cpu))
1174 return;
1175
1176 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177 loaded_vmcss_on_cpu_link)
1178 vmcs_clear(v->vmcs);
1179}
1180#else
1181static inline void crash_enable_local_vmclear(int cpu) { }
1182static inline void crash_disable_local_vmclear(int cpu) { }
1183#endif /* CONFIG_KEXEC */
1184
d462b819 1185static void __loaded_vmcs_clear(void *arg)
6aa8b732 1186{
d462b819 1187 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1188 int cpu = raw_smp_processor_id();
6aa8b732 1189
d462b819
NHE		 1190 if (loaded_vmcs->cpu != cpu)
1191 return; /* vcpu migration can race with cpu offline */
1192 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1193 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1194 crash_disable_local_vmclear(cpu);
d462b819 1195 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1196
1197 /*
1198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199 * is before setting loaded_vmcs->vcpu to -1 which is done in
1200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201 * then adds the vmcs into percpu list before it is deleted.
1202 */
1203 smp_wmb();
1204
d462b819 1205 loaded_vmcs_init(loaded_vmcs);
8f536b76 1206 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1207}
1208
d462b819 1209static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1210{
e6c7d321
XG		 1211 int cpu = loaded_vmcs->cpu;
1212
1213 if (cpu != -1)
1214 smp_call_function_single(cpu,
1215 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1216}
1217
1760dd49 1218static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1219{
1220 if (vmx->vpid == 0)
1221 return;
1222
518c8aee
GJ		 1223 if (cpu_has_vmx_invvpid_single())
1224 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1225}
1226
b9d762fa
GJ		 1227static inline void vpid_sync_vcpu_global(void)
1228{
1229 if (cpu_has_vmx_invvpid_global())
1230 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231}
1232
1233static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234{
1235 if (cpu_has_vmx_invvpid_single())
1760dd49 1236 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1237 else
1238 vpid_sync_vcpu_global();
1239}
1240
1439442c
SY		 1241static inline void ept_sync_global(void)
1242{
1243 if (cpu_has_vmx_invept_global())
1244 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245}
1246
1247static inline void ept_sync_context(u64 eptp)
1248{
089d034e 1249 if (enable_ept) {
1439442c
SY		 1250 if (cpu_has_vmx_invept_context())
1251 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252 else
1253 ept_sync_global();
1254 }
1255}
1256
96304217 1257static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1258{
5e520e62 1259 unsigned long value;
6aa8b732 1260
5e520e62
AK		 1261 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1263 return value;
1264}
1265
96304217 1266static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1267{
1268 return vmcs_readl(field);
1269}
1270
96304217 1271static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1272{
1273 return vmcs_readl(field);
1274}
1275
96304217 1276static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1277{
05b3e0c2 1278#ifdef CONFIG_X86_64
6aa8b732
AK		 1279 return vmcs_readl(field);
1280#else
1281 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282#endif
1283}
1284
e52de1b8
AK		 1285static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286{
1287 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289 dump_stack();
1290}
1291
6aa8b732
AK		 1292static void vmcs_writel(unsigned long field, unsigned long value)
1293{
1294 u8 error;
1295
4ecac3fd 1296 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1297 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1298 if (unlikely(error))
1299 vmwrite_error(field, value);
6aa8b732
AK		 1300}
1301
1302static void vmcs_write16(unsigned long field, u16 value)
1303{
1304 vmcs_writel(field, value);
1305}
1306
1307static void vmcs_write32(unsigned long field, u32 value)
1308{
1309 vmcs_writel(field, value);
1310}
1311
1312static void vmcs_write64(unsigned long field, u64 value)
1313{
6aa8b732 1314 vmcs_writel(field, value);
7682f2d0 1315#ifndef CONFIG_X86_64
6aa8b732
AK		 1316 asm volatile ("");
1317 vmcs_writel(field+1, value >> 32);
1318#endif
1319}
1320
2ab455cc
AL		 1321static void vmcs_clear_bits(unsigned long field, u32 mask)
1322{
1323 vmcs_writel(field, vmcs_readl(field) & ~mask);
1324}
1325
1326static void vmcs_set_bits(unsigned long field, u32 mask)
1327{
1328 vmcs_writel(field, vmcs_readl(field) | mask);
1329}
1330
2fb92db1
AK		 1331static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1332{
1333 vmx->segment_cache.bitmask = 0;
1334}
1335
1336static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1337 unsigned field)
1338{
1339 bool ret;
1340 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1341
1342 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1343 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1344 vmx->segment_cache.bitmask = 0;
1345 }
1346 ret = vmx->segment_cache.bitmask & mask;
1347 vmx->segment_cache.bitmask |= mask;
1348 return ret;
1349}
1350
1351static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1352{
1353 u16 *p = &vmx->segment_cache.seg[seg].selector;
1354
1355 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1356 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1357 return *p;
1358}
1359
1360static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1361{
1362 ulong *p = &vmx->segment_cache.seg[seg].base;
1363
1364 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1365 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1366 return *p;
1367}
1368
1369static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1370{
1371 u32 *p = &vmx->segment_cache.seg[seg].limit;
1372
1373 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1374 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1375 return *p;
1376}
1377
1378static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1379{
1380 u32 *p = &vmx->segment_cache.seg[seg].ar;
1381
1382 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1383 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1384 return *p;
1385}
1386
abd3f2d6
AK		 1387static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1388{
1389 u32 eb;
1390
fd7373cc
JK		 1391 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1392 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1393 if ((vcpu->guest_debug &
1394 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1395 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1396 eb |= 1u << BP_VECTOR;
7ffd92c5 1397 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1398 eb = ~0;
089d034e 1399 if (enable_ept)
1439442c 1400 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1401 if (vcpu->fpu_active)
1402 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1403
1404 /* When we are running a nested L2 guest and L1 specified for it a
1405 * certain exception bitmap, we must trap the same exceptions and pass
1406 * them to L1. When running L2, we will only handle the exceptions
1407 * specified above if L1 did not want them.
1408 */
1409 if (is_guest_mode(vcpu))
1410 eb |= get_vmcs12(vcpu)->exception_bitmap;
1411
abd3f2d6
AK		 1412 vmcs_write32(EXCEPTION_BITMAP, eb);
1413}
1414
8bf00a52
GN		 1415static void clear_atomic_switch_msr_special(unsigned long entry,
1416 unsigned long exit)
1417{
1418 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1419 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1420}
1421
61d2ef2c
AK		 1422static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1423{
1424 unsigned i;
1425 struct msr_autoload *m = &vmx->msr_autoload;
1426
8bf00a52
GN		 1427 switch (msr) {
1428 case MSR_EFER:
1429 if (cpu_has_load_ia32_efer) {
1430 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1431 VM_EXIT_LOAD_IA32_EFER);
1432 return;
1433 }
1434 break;
1435 case MSR_CORE_PERF_GLOBAL_CTRL:
1436 if (cpu_has_load_perf_global_ctrl) {
1437 clear_atomic_switch_msr_special(
1438 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1439 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1440 return;
1441 }
1442 break;
110312c8
AK		 1443 }
1444
61d2ef2c
AK		 1445 for (i = 0; i < m->nr; ++i)
1446 if (m->guest[i].index == msr)
1447 break;
1448
1449 if (i == m->nr)
1450 return;
1451 --m->nr;
1452 m->guest[i] = m->guest[m->nr];
1453 m->host[i] = m->host[m->nr];
1454 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1455 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1456}
1457
8bf00a52
GN		 1458static void add_atomic_switch_msr_special(unsigned long entry,
1459 unsigned long exit, unsigned long guest_val_vmcs,
1460 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1461{
1462 vmcs_write64(guest_val_vmcs, guest_val);
1463 vmcs_write64(host_val_vmcs, host_val);
1464 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1465 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1466}
1467
61d2ef2c
AK		 1468static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1469 u64 guest_val, u64 host_val)
1470{
1471 unsigned i;
1472 struct msr_autoload *m = &vmx->msr_autoload;
1473
8bf00a52
GN		 1474 switch (msr) {
1475 case MSR_EFER:
1476 if (cpu_has_load_ia32_efer) {
1477 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1478 VM_EXIT_LOAD_IA32_EFER,
1479 GUEST_IA32_EFER,
1480 HOST_IA32_EFER,
1481 guest_val, host_val);
1482 return;
1483 }
1484 break;
1485 case MSR_CORE_PERF_GLOBAL_CTRL:
1486 if (cpu_has_load_perf_global_ctrl) {
1487 add_atomic_switch_msr_special(
1488 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1489 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1490 GUEST_IA32_PERF_GLOBAL_CTRL,
1491 HOST_IA32_PERF_GLOBAL_CTRL,
1492 guest_val, host_val);
1493 return;
1494 }
1495 break;
110312c8
AK		 1496 }
1497
61d2ef2c
AK		 1498 for (i = 0; i < m->nr; ++i)
1499 if (m->guest[i].index == msr)
1500 break;
1501
e7fc6f93
GN		 1502 if (i == NR_AUTOLOAD_MSRS) {
1503 printk_once(KERN_WARNING"Not enough mst switch entries. "
1504 "Can't add msr %x\n", msr);
1505 return;
1506 } else if (i == m->nr) {
61d2ef2c
AK		 1507 ++m->nr;
1508 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1509 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1510 }
1511
1512 m->guest[i].index = msr;
1513 m->guest[i].value = guest_val;
1514 m->host[i].index = msr;
1515 m->host[i].value = host_val;
1516}
1517
33ed6329
AK		 1518static void reload_tss(void)
1519{
33ed6329
AK		 1520 /*
1521 * VT restores TR but not its size. Useless.
1522 */
d359192f 1523 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1524 struct desc_struct *descs;
33ed6329 1525
d359192f 1526 descs = (void *)gdt->address;
33ed6329
AK		 1527 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1528 load_TR_desc();
33ed6329
AK		 1529}
1530
92c0d900 1531static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1532{
3a34a881 1533 u64 guest_efer;
51c6cf66
AK		 1534 u64 ignore_bits;
1535
f6801dff 1536 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1537
51c6cf66 1538 /*
0fa06071 1539 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1540 * outside long mode
1541 */
1542 ignore_bits = EFER_NX | EFER_SCE;
1543#ifdef CONFIG_X86_64
1544 ignore_bits |= EFER_LMA | EFER_LME;
1545 /* SCE is meaningful only in long mode on Intel */
1546 if (guest_efer & EFER_LMA)
1547 ignore_bits &= ~(u64)EFER_SCE;
1548#endif
51c6cf66
AK		 1549 guest_efer &= ~ignore_bits;
1550 guest_efer |= host_efer & ignore_bits;
26bb0981 1551 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1552 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1553
1554 clear_atomic_switch_msr(vmx, MSR_EFER);
1555 /* On ept, can't emulate nx, and must switch nx atomically */
1556 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1557 guest_efer = vmx->vcpu.arch.efer;
1558 if (!(guest_efer & EFER_LMA))
1559 guest_efer &= ~EFER_LME;
1560 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1561 return false;
1562 }
1563
26bb0981 1564 return true;
51c6cf66
AK		 1565}
1566
2d49ec72
GN		 1567static unsigned long segment_base(u16 selector)
1568{
d359192f 1569 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1570 struct desc_struct *d;
1571 unsigned long table_base;
1572 unsigned long v;
1573
1574 if (!(selector & ~3))
1575 return 0;
1576
d359192f 1577 table_base = gdt->address;
2d49ec72
GN		 1578
1579 if (selector & 4) { /* from ldt */
1580 u16 ldt_selector = kvm_read_ldt();
1581
1582 if (!(ldt_selector & ~3))
1583 return 0;
1584
1585 table_base = segment_base(ldt_selector);
1586 }
1587 d = (struct desc_struct *)(table_base + (selector & ~7));
1588 v = get_desc_base(d);
1589#ifdef CONFIG_X86_64
1590 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1591 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1592#endif
1593 return v;
1594}
1595
1596static inline unsigned long kvm_read_tr_base(void)
1597{
1598 u16 tr;
1599 asm("str %0" : "=g"(tr));
1600 return segment_base(tr);
1601}
1602
04d2cc77 1603static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1604{
04d2cc77 1605 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1606 int i;
04d2cc77 1607
a2fa3e9f 1608 if (vmx->host_state.loaded)
33ed6329
AK		 1609 return;
1610
a2fa3e9f 1611 vmx->host_state.loaded = 1;
33ed6329
AK		 1612 /*
1613 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1614 * allow segment selectors with cpl > 0 or ti == 1.
1615 */
d6e88aec 1616 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1617 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1618 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1619 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1620 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1621 vmx->host_state.fs_reload_needed = 0;
1622 } else {
33ed6329 1623 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1624 vmx->host_state.fs_reload_needed = 1;
33ed6329 1625 }
9581d442 1626 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1627 if (!(vmx->host_state.gs_sel & 7))
1628 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1629 else {
1630 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1631 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1632 }
1633
b2da15ac
AK		 1634#ifdef CONFIG_X86_64
1635 savesegment(ds, vmx->host_state.ds_sel);
1636 savesegment(es, vmx->host_state.es_sel);
1637#endif
1638
33ed6329
AK		 1639#ifdef CONFIG_X86_64
1640 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1641 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1642#else
a2fa3e9f
GH		 1643 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1644 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1645#endif
707c0874
AK		 1646
1647#ifdef CONFIG_X86_64
c8770e7b
AK		 1648 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1649 if (is_long_mode(&vmx->vcpu))
44ea2b17 1650 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1651#endif
26bb0981
AK		 1652 for (i = 0; i < vmx->save_nmsrs; ++i)
1653 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1654 vmx->guest_msrs[i].data,
1655 vmx->guest_msrs[i].mask);
33ed6329
AK		 1656}
1657
a9b21b62 1658static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1659{
a2fa3e9f 1660 if (!vmx->host_state.loaded)
33ed6329
AK		 1661 return;
1662
e1beb1d3 1663 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1664 vmx->host_state.loaded = 0;
c8770e7b
AK		 1665#ifdef CONFIG_X86_64
1666 if (is_long_mode(&vmx->vcpu))
1667 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1668#endif
152d3f2f 1669 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1670 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1671#ifdef CONFIG_X86_64
9581d442 1672 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1673#else
1674 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1675#endif
33ed6329 1676 }
0a77fe4c
AK		 1677 if (vmx->host_state.fs_reload_needed)
1678 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1679#ifdef CONFIG_X86_64
1680 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1681 loadsegment(ds, vmx->host_state.ds_sel);
1682 loadsegment(es, vmx->host_state.es_sel);
1683 }
b2da15ac 1684#endif
152d3f2f 1685 reload_tss();
44ea2b17 1686#ifdef CONFIG_X86_64
c8770e7b 1687 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1688#endif
b1a74bf8
SS		 1689 /*
1690 * If the FPU is not active (through the host task or
1691 * the guest vcpu), then restore the cr0.TS bit.
1692 */
1693 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1694 stts();
3444d7da 1695 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1696}
1697
a9b21b62
AK		 1698static void vmx_load_host_state(struct vcpu_vmx *vmx)
1699{
1700 preempt_disable();
1701 __vmx_load_host_state(vmx);
1702 preempt_enable();
1703}
1704
6aa8b732
AK		 1705/*
1706 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1707 * vcpu mutex is already taken.
1708 */
15ad7146 1709static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1710{
a2fa3e9f 1711 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1712 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1713
4610c9cc
DX		 1714 if (!vmm_exclusive)
1715 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1716 else if (vmx->loaded_vmcs->cpu != cpu)
1717 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1718
d462b819
NHE		 1719 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1720 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1721 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1722 }
1723
d462b819 1724 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1725 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1726 unsigned long sysenter_esp;
1727
a8eeb04a 1728 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1729 local_irq_disable();
8f536b76 1730 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1731
1732 /*
1733 * Read loaded_vmcs->cpu should be before fetching
1734 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1735 * See the comments in __loaded_vmcs_clear().
1736 */
1737 smp_rmb();
1738
d462b819
NHE		 1739 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1740 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1741 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1742 local_irq_enable();
1743
6aa8b732
AK		 1744 /*
1745 * Linux uses per-cpu TSS and GDT, so set these when switching
1746 * processors.
1747 */
d6e88aec 1748 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1749 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1750
1751 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1752 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1753 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1754 }
6aa8b732
AK		 1755}
1756
1757static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1758{
a9b21b62 1759 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1760 if (!vmm_exclusive) {
d462b819
NHE		 1761 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1762 vcpu->cpu = -1;
4610c9cc
DX		 1763 kvm_cpu_vmxoff();
1764 }
6aa8b732
AK		 1765}
1766
5fd86fcf
AK		 1767static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1768{
81231c69
AK		 1769 ulong cr0;
1770
5fd86fcf
AK		 1771 if (vcpu->fpu_active)
1772 return;
1773 vcpu->fpu_active = 1;
81231c69
AK		 1774 cr0 = vmcs_readl(GUEST_CR0);
1775 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1776 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1777 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1778 update_exception_bitmap(vcpu);
edcafe3c 1779 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1780 if (is_guest_mode(vcpu))
1781 vcpu->arch.cr0_guest_owned_bits &=
1782 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1783 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1784}
1785
edcafe3c
AK		 1786static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1787
fe3ef05c
NHE		 1788/*
1789 * Return the cr0 value that a nested guest would read. This is a combination
1790 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1791 * its hypervisor (cr0_read_shadow).
1792 */
1793static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1794{
1795 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1796 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1797}
1798static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1799{
1800 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1801 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1802}
1803
5fd86fcf
AK		 1804static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1805{
36cf24e0
NHE		 1806 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1807 * set this *before* calling this function.
1808 */
edcafe3c 1809 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1810 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1811 update_exception_bitmap(vcpu);
edcafe3c
AK		 1812 vcpu->arch.cr0_guest_owned_bits = 0;
1813 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1814 if (is_guest_mode(vcpu)) {
1815 /*
1816 * L1's specified read shadow might not contain the TS bit,
1817 * so now that we turned on shadowing of this bit, we need to
1818 * set this bit of the shadow. Like in nested_vmx_run we need
1819 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1820 * up-to-date here because we just decached cr0.TS (and we'll
1821 * only update vmcs12->guest_cr0 on nested exit).
1822 */
1823 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1824 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1825 (vcpu->arch.cr0 & X86_CR0_TS);
1826 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1827 } else
1828 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1829}
1830
6aa8b732
AK		 1831static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1832{
78ac8b47 1833 unsigned long rflags, save_rflags;
345dcaa8 1834
6de12732
AK		 1835 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1836 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1837 rflags = vmcs_readl(GUEST_RFLAGS);
1838 if (to_vmx(vcpu)->rmode.vm86_active) {
1839 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1841 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1842 }
1843 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1844 }
6de12732 1845 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1846}
1847
1848static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1849{
6de12732
AK		 1850 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1851 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1852 if (to_vmx(vcpu)->rmode.vm86_active) {
1853 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1854 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1855 }
6aa8b732
AK		 1856 vmcs_writel(GUEST_RFLAGS, rflags);
1857}
1858
2809f5d2
GC		 1859static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1860{
1861 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1862 int ret = 0;
1863
1864 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1866 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1867 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1868
1869 return ret & mask;
1870}
1871
1872static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1873{
1874 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1875 u32 interruptibility = interruptibility_old;
1876
1877 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1878
48005f64 1879 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1880 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1881 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1882 interruptibility |= GUEST_INTR_STATE_STI;
1883
1884 if ((interruptibility != interruptibility_old))
1885 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1886}
1887
6aa8b732
AK		 1888static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1889{
1890 unsigned long rip;
6aa8b732 1891
5fdbf976 1892 rip = kvm_rip_read(vcpu);
6aa8b732 1893 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1894 kvm_rip_write(vcpu, rip);
6aa8b732 1895
2809f5d2
GC		 1896 /* skipping an emulated instruction also counts */
1897 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1898}
1899
0b6ac343
NHE		 1900/*
1901 * KVM wants to inject page-faults which it got to the guest. This function
1902 * checks whether in a nested guest, we need to inject them to L1 or L2.
1903 * This function assumes it is called with the exit reason in vmcs02 being
1904 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1905 * is running).
1906 */
1907static int nested_pf_handled(struct kvm_vcpu *vcpu)
1908{
1909 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1910
1911 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1912 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1913 return 0;
1914
1915 nested_vmx_vmexit(vcpu);
1916 return 1;
1917}
1918
298101da 1919static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1920 bool has_error_code, u32 error_code,
1921 bool reinject)
298101da 1922{
77ab6db0 1923 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1924 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1925
0b6ac343 1926 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1927 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1928 return;
1929
8ab2d2e2 1930 if (has_error_code) {
77ab6db0 1931 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1932 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1933 }
77ab6db0 1934
7ffd92c5 1935 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1936 int inc_eip = 0;
1937 if (kvm_exception_is_soft(nr))
1938 inc_eip = vcpu->arch.event_exit_inst_len;
1939 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1940 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1941 return;
1942 }
1943
66fd3f7f
GN		 1944 if (kvm_exception_is_soft(nr)) {
1945 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1946 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1947 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1948 } else
1949 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1950
1951 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1952}
1953
4e47c7a6
SY		 1954static bool vmx_rdtscp_supported(void)
1955{
1956 return cpu_has_vmx_rdtscp();
1957}
1958
ad756a16
MJ		 1959static bool vmx_invpcid_supported(void)
1960{
1961 return cpu_has_vmx_invpcid() && enable_ept;
1962}
1963
a75beee6
ED		 1964/*
1965 * Swap MSR entry in host/guest MSR entry array.
1966 */
8b9cf98c 1967static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1968{
26bb0981 1969 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1970
1971 tmp = vmx->guest_msrs[to];
1972 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1973 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1974}
1975
8d14695f
YZ		 1976static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1977{
1978 unsigned long *msr_bitmap;
1979
1980 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1981 if (is_long_mode(vcpu))
1982 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1983 else
1984 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1985 } else {
1986 if (is_long_mode(vcpu))
1987 msr_bitmap = vmx_msr_bitmap_longmode;
1988 else
1989 msr_bitmap = vmx_msr_bitmap_legacy;
1990 }
1991
1992 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1993}
1994
e38aea3e
AK		 1995/*
1996 * Set up the vmcs to automatically save and restore system
1997 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1998 * mode, as fiddling with msrs is very expensive.
1999 */
8b9cf98c 2000static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2001{
26bb0981 2002 int save_nmsrs, index;
e38aea3e 2003
a75beee6
ED		 2004 save_nmsrs = 0;
2005#ifdef CONFIG_X86_64
8b9cf98c 2006 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2007 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2008 if (index >= 0)
8b9cf98c
RR		 2009 move_msr_up(vmx, index, save_nmsrs++);
2010 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2011 if (index >= 0)
8b9cf98c
RR		 2012 move_msr_up(vmx, index, save_nmsrs++);
2013 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2014 if (index >= 0)
8b9cf98c 2015 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2016 index = __find_msr_index(vmx, MSR_TSC_AUX);
2017 if (index >= 0 && vmx->rdtscp_enabled)
2018 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2019 /*
8c06585d 2020 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2021 * if efer.sce is enabled.
2022 */
8c06585d 2023 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2024 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2025 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2026 }
2027#endif
92c0d900
AK		 2028 index = __find_msr_index(vmx, MSR_EFER);
2029 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2030 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2031
26bb0981 2032 vmx->save_nmsrs = save_nmsrs;
5897297b 2033
8d14695f
YZ		 2034 if (cpu_has_vmx_msr_bitmap())
2035 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2036}
2037
6aa8b732
AK		 2038/*
2039 * reads and returns guest's timestamp counter "register"
2040 * guest_tsc = host_tsc + tsc_offset -- 21.3
2041 */
2042static u64 guest_read_tsc(void)
2043{
2044 u64 host_tsc, tsc_offset;
2045
2046 rdtscll(host_tsc);
2047 tsc_offset = vmcs_read64(TSC_OFFSET);
2048 return host_tsc + tsc_offset;
2049}
2050
d5c1785d
NHE		 2051/*
2052 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2053 * counter, even if a nested guest (L2) is currently running.
2054 */
886b470c 2055u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2056{
886b470c 2057 u64 tsc_offset;
d5c1785d 2058
d5c1785d
NHE		 2059 tsc_offset = is_guest_mode(vcpu) ?
2060 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2061 vmcs_read64(TSC_OFFSET);
2062 return host_tsc + tsc_offset;
2063}
2064
4051b188 2065/*
cc578287
ZA		 2066 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2067 * software catchup for faster rates on slower CPUs.
4051b188 2068 */
cc578287 2069static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2070{
cc578287
ZA		 2071 if (!scale)
2072 return;
2073
2074 if (user_tsc_khz > tsc_khz) {
2075 vcpu->arch.tsc_catchup = 1;
2076 vcpu->arch.tsc_always_catchup = 1;
2077 } else
2078 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2079}
2080
ba904635
WA		 2081static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2082{
2083 return vmcs_read64(TSC_OFFSET);
2084}
2085
6aa8b732 2086/*
99e3e30a 2087 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2088 */
99e3e30a 2089static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2090{
27fc51b2 2091 if (is_guest_mode(vcpu)) {
7991825b 2092 /*
27fc51b2
NHE		 2093 * We're here if L1 chose not to trap WRMSR to TSC. According
2094 * to the spec, this should set L1's TSC; The offset that L1
2095 * set for L2 remains unchanged, and still needs to be added
2096 * to the newly set TSC to get L2's TSC.
7991825b 2097 */
27fc51b2
NHE		 2098 struct vmcs12 *vmcs12;
2099 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2100 /* recalculate vmcs02.TSC_OFFSET: */
2101 vmcs12 = get_vmcs12(vcpu);
2102 vmcs_write64(TSC_OFFSET, offset +
2103 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2104 vmcs12->tsc_offset : 0));
2105 } else {
489223ed
YY		 2106 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2107 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2108 vmcs_write64(TSC_OFFSET, offset);
2109 }
6aa8b732
AK		 2110}
2111
f1e2b260 2112static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2113{
2114 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2115
e48672fa 2116 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2117 if (is_guest_mode(vcpu)) {
2118 /* Even when running L2, the adjustment needs to apply to L1 */
2119 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2120 } else
2121 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2122 offset + adjustment);
e48672fa
ZA		 2123}
2124
857e4099
JR		 2125static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2126{
2127 return target_tsc - native_read_tsc();
2128}
2129
801d3424
NHE		 2130static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2131{
2132 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2133 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2134}
2135
2136/*
2137 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2138 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2139 * all guests if the "nested" module option is off, and can also be disabled
2140 * for a single guest by disabling its VMX cpuid bit.
2141 */
2142static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2143{
2144 return nested && guest_cpuid_has_vmx(vcpu);
2145}
2146
b87a51ae
NHE		 2147/*
2148 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2149 * returned for the various VMX controls MSRs when nested VMX is enabled.
2150 * The same values should also be used to verify that vmcs12 control fields are
2151 * valid during nested entry from L1 to L2.
2152 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2153 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2154 * bit in the high half is on if the corresponding bit in the control field
2155 * may be on. See also vmx_control_verify().
2156 * TODO: allow these variables to be modified (downgraded) by module options
2157 * or other means.
2158 */
2159static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2160static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2161static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2162static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2163static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2164static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2165static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2166static __init void nested_vmx_setup_ctls_msrs(void)
2167{
2168 /*
2169 * Note that as a general rule, the high half of the MSRs (bits in
2170 * the control fields which may be 1) should be initialized by the
2171 * intersection of the underlying hardware's MSR (i.e., features which
2172 * can be supported) and the list of features we want to expose -
2173 * because they are known to be properly supported in our code.
2174 * Also, usually, the low half of the MSRs (bits which must be 1) can
2175 * be set to 0, meaning that L1 may turn off any of these bits. The
2176 * reason is that if one of these bits is necessary, it will appear
2177 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2178 * fields of vmcs01 and vmcs02, will turn these bits off - and
2179 * nested_vmx_exit_handled() will not pass related exits to L1.
2180 * These rules have exceptions below.
2181 */
2182
2183 /* pin-based controls */
eabeaacc
JK		 2184 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2185 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2186 /*
2187 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2188 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2189 */
eabeaacc
JK		 2190 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2191 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2192 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2193 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2194 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2195
33fb20c3
JK		 2196 /*
2197 * Exit controls
2198 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2199 * 17 must be 1.
2200 */
2201 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2202 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2203#ifdef CONFIG_X86_64
2204 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2205#else
2206 nested_vmx_exit_ctls_high = 0;
2207#endif
8049d651
NHE		 2208 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2209 VM_EXIT_LOAD_IA32_EFER);
b87a51ae
NHE		 2210
2211 /* entry controls */
2212 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2213 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2214 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2215 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2216 nested_vmx_entry_ctls_high &=
2217 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
8049d651
NHE		 2218 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2219 VM_ENTRY_LOAD_IA32_EFER);
b87a51ae
NHE		 2220 /* cpu-based controls */
2221 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2222 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2223 nested_vmx_procbased_ctls_low = 0;
2224 nested_vmx_procbased_ctls_high &=
2225 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2226 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2227 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2228 CPU_BASED_CR3_STORE_EXITING |
2229#ifdef CONFIG_X86_64
2230 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2231#endif
2232 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2233 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2234 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2235 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2236 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2237 /*
2238 * We can allow some features even when not supported by the
2239 * hardware. For example, L1 can specify an MSR bitmap - and we
2240 * can use it to avoid exits to L1 - even when L0 runs L2
2241 * without MSR bitmaps.
2242 */
2243 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2244
2245 /* secondary cpu-based controls */
2246 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2247 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2248 nested_vmx_secondary_ctls_low = 0;
2249 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2251 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2252
afa61f75
NHE		 2253 if (enable_ept) {
2254 /* nested EPT: emulate EPT also to L1 */
2255 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2256 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT;
2257 nested_vmx_ept_caps |= VMX_EPT_INVEPT_BIT;
2258 nested_vmx_ept_caps &= vmx_capability.ept;
2259 /*
2260 * Since invept is completely emulated we support both global
2261 * and context invalidation independent of what host cpu
2262 * supports
2263 */
2264 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2265 VMX_EPT_EXTENT_CONTEXT_BIT;
2266 } else
2267 nested_vmx_ept_caps = 0;
2268
c18911a2
JK		 2269 /* miscellaneous data */
2270 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2271 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2272 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2273 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2274}
2275
2276static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2277{
2278 /*
2279 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2280 */
2281 return ((control & high) | low) == control;
2282}
2283
2284static inline u64 vmx_control_msr(u32 low, u32 high)
2285{
2286 return low | ((u64)high << 32);
2287}
2288
2289/*
2290 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2291 * also let it use VMX-specific MSRs.
2292 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2293 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2294 * like all other MSRs).
2295 */
2296static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2297{
2298 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2299 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2300 /*
2301 * According to the spec, processors which do not support VMX
2302 * should throw a #GP(0) when VMX capability MSRs are read.
2303 */
2304 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2305 return 1;
2306 }
2307
2308 switch (msr_index) {
2309 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2310 if (nested_vmx_allowed(vcpu)) {
2311 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2312 break;
2313 }
2314 return 0;
b87a51ae
NHE		 2315 case MSR_IA32_VMX_BASIC:
2316 /*
2317 * This MSR reports some information about VMX support. We
2318 * should return information about the VMX we emulate for the
2319 * guest, and the VMCS structure we give it - not about the
2320 * VMX support of the underlying hardware.
2321 */
2322 *pdata = VMCS12_REVISION |
2323 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2324 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2325 break;
2326 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2327 case MSR_IA32_VMX_PINBASED_CTLS:
2328 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2329 nested_vmx_pinbased_ctls_high);
2330 break;
2331 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2332 case MSR_IA32_VMX_PROCBASED_CTLS:
2333 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2334 nested_vmx_procbased_ctls_high);
2335 break;
2336 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2337 case MSR_IA32_VMX_EXIT_CTLS:
2338 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2339 nested_vmx_exit_ctls_high);
2340 break;
2341 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2342 case MSR_IA32_VMX_ENTRY_CTLS:
2343 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2344 nested_vmx_entry_ctls_high);
2345 break;
2346 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2347 *pdata = vmx_control_msr(nested_vmx_misc_low,
2348 nested_vmx_misc_high);
b87a51ae
NHE		 2349 break;
2350 /*
2351 * These MSRs specify bits which the guest must keep fixed (on or off)
2352 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2353 * We picked the standard core2 setting.
2354 */
2355#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2356#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2357 case MSR_IA32_VMX_CR0_FIXED0:
2358 *pdata = VMXON_CR0_ALWAYSON;
2359 break;
2360 case MSR_IA32_VMX_CR0_FIXED1:
2361 *pdata = -1ULL;
2362 break;
2363 case MSR_IA32_VMX_CR4_FIXED0:
2364 *pdata = VMXON_CR4_ALWAYSON;
2365 break;
2366 case MSR_IA32_VMX_CR4_FIXED1:
2367 *pdata = -1ULL;
2368 break;
2369 case MSR_IA32_VMX_VMCS_ENUM:
2370 *pdata = 0x1f;
2371 break;
2372 case MSR_IA32_VMX_PROCBASED_CTLS2:
2373 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2374 nested_vmx_secondary_ctls_high);
2375 break;
2376 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2377 /* Currently, no nested vpid support */
2378 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2379 break;
2380 default:
2381 return 0;
2382 }
2383
2384 return 1;
2385}
2386
b3897a49 2387static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2388{
b3897a49
NHE		 2389 u32 msr_index = msr_info->index;
2390 u64 data = msr_info->data;
2391 bool host_initialized = msr_info->host_initiated;
2392
b87a51ae
NHE		 2393 if (!nested_vmx_allowed(vcpu))
2394 return 0;
2395
b3897a49
NHE		 2396 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2397 if (!host_initialized &&
2398 to_vmx(vcpu)->nested.msr_ia32_feature_control
2399 & FEATURE_CONTROL_LOCKED)
2400 return 0;
2401 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2402 return 1;
b3897a49
NHE		 2403 }
2404
b87a51ae
NHE		 2405 /*
2406 * No need to treat VMX capability MSRs specially: If we don't handle
2407 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2408 */
2409 return 0;
2410}
2411
6aa8b732
AK		 2412/*
2413 * Reads an msr value (of 'msr_index') into 'pdata'.
2414 * Returns 0 on success, non-0 otherwise.
2415 * Assumes vcpu_load() was already called.
2416 */
2417static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2418{
2419 u64 data;
26bb0981 2420 struct shared_msr_entry *msr;
6aa8b732
AK		 2421
2422 if (!pdata) {
2423 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2424 return -EINVAL;
2425 }
2426
2427 switch (msr_index) {
05b3e0c2 2428#ifdef CONFIG_X86_64
6aa8b732
AK		 2429 case MSR_FS_BASE:
2430 data = vmcs_readl(GUEST_FS_BASE);
2431 break;
2432 case MSR_GS_BASE:
2433 data = vmcs_readl(GUEST_GS_BASE);
2434 break;
44ea2b17
AK		 2435 case MSR_KERNEL_GS_BASE:
2436 vmx_load_host_state(to_vmx(vcpu));
2437 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2438 break;
26bb0981 2439#endif
6aa8b732 2440 case MSR_EFER:
3bab1f5d 2441 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2442 case MSR_IA32_TSC:
6aa8b732
AK		 2443 data = guest_read_tsc();
2444 break;
2445 case MSR_IA32_SYSENTER_CS:
2446 data = vmcs_read32(GUEST_SYSENTER_CS);
2447 break;
2448 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2449 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2450 break;
2451 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2452 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2453 break;
4e47c7a6
SY		 2454 case MSR_TSC_AUX:
2455 if (!to_vmx(vcpu)->rdtscp_enabled)
2456 return 1;
2457 /* Otherwise falls through */
6aa8b732 2458 default:
b87a51ae
NHE		 2459 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2460 return 0;
8b9cf98c 2461 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2462 if (msr) {
2463 data = msr->data;
2464 break;
6aa8b732 2465 }
3bab1f5d 2466 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2467 }
2468
2469 *pdata = data;
2470 return 0;
2471}
2472
2473/*
2474 * Writes msr value into into the appropriate "register".
2475 * Returns 0 on success, non-0 otherwise.
2476 * Assumes vcpu_load() was already called.
2477 */
8fe8ab46 2478static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2479{
a2fa3e9f 2480 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2481 struct shared_msr_entry *msr;
2cc51560 2482 int ret = 0;
8fe8ab46
WA		 2483 u32 msr_index = msr_info->index;
2484 u64 data = msr_info->data;
2cc51560 2485
6aa8b732 2486 switch (msr_index) {
3bab1f5d 2487 case MSR_EFER:
8fe8ab46 2488 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2489 break;
16175a79 2490#ifdef CONFIG_X86_64
6aa8b732 2491 case MSR_FS_BASE:
2fb92db1 2492 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2493 vmcs_writel(GUEST_FS_BASE, data);
2494 break;
2495 case MSR_GS_BASE:
2fb92db1 2496 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2497 vmcs_writel(GUEST_GS_BASE, data);
2498 break;
44ea2b17
AK		 2499 case MSR_KERNEL_GS_BASE:
2500 vmx_load_host_state(vmx);
2501 vmx->msr_guest_kernel_gs_base = data;
2502 break;
6aa8b732
AK		 2503#endif
2504 case MSR_IA32_SYSENTER_CS:
2505 vmcs_write32(GUEST_SYSENTER_CS, data);
2506 break;
2507 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2508 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2509 break;
2510 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2511 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2512 break;
af24a4e4 2513 case MSR_IA32_TSC:
8fe8ab46 2514 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2515 break;
468d472f
SY		 2516 case MSR_IA32_CR_PAT:
2517 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2518 vmcs_write64(GUEST_IA32_PAT, data);
2519 vcpu->arch.pat = data;
2520 break;
2521 }
8fe8ab46 2522 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2523 break;
ba904635
WA		 2524 case MSR_IA32_TSC_ADJUST:
2525 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2526 break;
2527 case MSR_TSC_AUX:
2528 if (!vmx->rdtscp_enabled)
2529 return 1;
2530 /* Check reserved bit, higher 32 bits should be zero */
2531 if ((data >> 32) != 0)
2532 return 1;
2533 /* Otherwise falls through */
6aa8b732 2534 default:
b3897a49 2535 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2536 break;
8b9cf98c 2537 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2538 if (msr) {
2539 msr->data = data;
2225fd56
AK		 2540 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2541 preempt_disable();
9ee73970
AK		 2542 kvm_set_shared_msr(msr->index, msr->data,
2543 msr->mask);
2225fd56
AK		 2544 preempt_enable();
2545 }
3bab1f5d 2546 break;
6aa8b732 2547 }
8fe8ab46 2548 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2549 }
2550
2cc51560 2551 return ret;
6aa8b732
AK		 2552}
2553
5fdbf976 2554static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2555{
5fdbf976
MT		 2556 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2557 switch (reg) {
2558 case VCPU_REGS_RSP:
2559 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2560 break;
2561 case VCPU_REGS_RIP:
2562 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2563 break;
6de4f3ad
AK		 2564 case VCPU_EXREG_PDPTR:
2565 if (enable_ept)
2566 ept_save_pdptrs(vcpu);
2567 break;
5fdbf976
MT		 2568 default:
2569 break;
2570 }
6aa8b732
AK		 2571}
2572
6aa8b732
AK		 2573static __init int cpu_has_kvm_support(void)
2574{
6210e37b 2575 return cpu_has_vmx();
6aa8b732
AK		 2576}
2577
2578static __init int vmx_disabled_by_bios(void)
2579{
2580 u64 msr;
2581
2582 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2583 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2584 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2585 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2586 && tboot_enabled())
2587 return 1;
23f3e991 2588 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2589 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2590 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2591 && !tboot_enabled()) {
2592 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2593 "activate TXT before enabling KVM\n");
cafd6659 2594 return 1;
f9335afe 2595 }
23f3e991
JC		 2596 /* launched w/o TXT and VMX disabled */
2597 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2598 && !tboot_enabled())
2599 return 1;
cafd6659
SW		 2600 }
2601
2602 return 0;
6aa8b732
AK		 2603}
2604
7725b894
DX		 2605static void kvm_cpu_vmxon(u64 addr)
2606{
2607 asm volatile (ASM_VMX_VMXON_RAX
2608 : : "a"(&addr), "m"(addr)
2609 : "memory", "cc");
2610}
2611
10474ae8 2612static int hardware_enable(void *garbage)
6aa8b732
AK		 2613{
2614 int cpu = raw_smp_processor_id();
2615 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2616 u64 old, test_bits;
6aa8b732 2617
10474ae8
AG		 2618 if (read_cr4() & X86_CR4_VMXE)
2619 return -EBUSY;
2620
d462b819 2621 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2622
2623 /*
2624 * Now we can enable the vmclear operation in kdump
2625 * since the loaded_vmcss_on_cpu list on this cpu
2626 * has been initialized.
2627 *
2628 * Though the cpu is not in VMX operation now, there
2629 * is no problem to enable the vmclear operation
2630 * for the loaded_vmcss_on_cpu list is empty!
2631 */
2632 crash_enable_local_vmclear(cpu);
2633
6aa8b732 2634 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2635
2636 test_bits = FEATURE_CONTROL_LOCKED;
2637 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2638 if (tboot_enabled())
2639 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2640
2641 if ((old & test_bits) != test_bits) {
6aa8b732 2642 /* enable and lock */
cafd6659
SW		 2643 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2644 }
66aee91a 2645 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2646
4610c9cc
DX		 2647 if (vmm_exclusive) {
2648 kvm_cpu_vmxon(phys_addr);
2649 ept_sync_global();
2650 }
10474ae8 2651
357d1226 2652 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2653
10474ae8 2654 return 0;
6aa8b732
AK		 2655}
2656
d462b819 2657static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2658{
2659 int cpu = raw_smp_processor_id();
d462b819 2660 struct loaded_vmcs *v, *n;
543e4243 2661
d462b819
NHE		 2662 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2663 loaded_vmcss_on_cpu_link)
2664 __loaded_vmcs_clear(v);
543e4243
AK		 2665}
2666
710ff4a8
EH		 2667
2668/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2669 * tricks.
2670 */
2671static void kvm_cpu_vmxoff(void)
6aa8b732 2672{
4ecac3fd 2673 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2674}
2675
710ff4a8
EH		 2676static void hardware_disable(void *garbage)
2677{
4610c9cc 2678 if (vmm_exclusive) {
d462b819 2679 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2680 kvm_cpu_vmxoff();
2681 }
7725b894 2682 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2683}
2684
1c3d14fe 2685static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2686 u32 msr, u32 *result)
1c3d14fe
YS		 2687{
2688 u32 vmx_msr_low, vmx_msr_high;
2689 u32 ctl = ctl_min | ctl_opt;
2690
2691 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2692
2693 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2694 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2695
2696 /* Ensure minimum (required) set of control bits are supported. */
2697 if (ctl_min & ~ctl)
002c7f7c 2698 return -EIO;
1c3d14fe
YS		 2699
2700 *result = ctl;
2701 return 0;
2702}
2703
110312c8
AK		 2704static __init bool allow_1_setting(u32 msr, u32 ctl)
2705{
2706 u32 vmx_msr_low, vmx_msr_high;
2707
2708 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2709 return vmx_msr_high & ctl;
2710}
2711
002c7f7c 2712static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2713{
2714 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2715 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2716 u32 _pin_based_exec_control = 0;
2717 u32 _cpu_based_exec_control = 0;
f78e0e2e 2718 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2719 u32 _vmexit_control = 0;
2720 u32 _vmentry_control = 0;
2721
10166744 2722 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2723#ifdef CONFIG_X86_64
2724 CPU_BASED_CR8_LOAD_EXITING |
2725 CPU_BASED_CR8_STORE_EXITING |
2726#endif
d56f546d
SY		 2727 CPU_BASED_CR3_LOAD_EXITING |
2728 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2729 CPU_BASED_USE_IO_BITMAPS |
2730 CPU_BASED_MOV_DR_EXITING |
a7052897 2731 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2732 CPU_BASED_MWAIT_EXITING |
2733 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2734 CPU_BASED_INVLPG_EXITING |
2735 CPU_BASED_RDPMC_EXITING;
443381a8 2736
f78e0e2e 2737 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2738 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2740 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2741 &_cpu_based_exec_control) < 0)
002c7f7c 2742 return -EIO;
6e5d865c
YS		 2743#ifdef CONFIG_X86_64
2744 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2745 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2746 ~CPU_BASED_CR8_STORE_EXITING;
2747#endif
f78e0e2e 2748 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2749 min2 = 0;
2750 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2751 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2752 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2753 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2754 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2755 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2756 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2757 SECONDARY_EXEC_RDTSCP |
83d4c286 2758 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2759 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2760 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2761 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2762 if (adjust_vmx_controls(min2, opt2,
2763 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2764 &_cpu_based_2nd_exec_control) < 0)
2765 return -EIO;
2766 }
2767#ifndef CONFIG_X86_64
2768 if (!(_cpu_based_2nd_exec_control &
2769 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2770 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2771#endif
83d4c286
YZ		 2772
2773 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2774 _cpu_based_2nd_exec_control &= ~(
8d14695f 2775 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2776 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2777 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2778
d56f546d 2779 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2780 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2781 enabled */
5fff7d27
GN		 2782 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2783 CPU_BASED_CR3_STORE_EXITING |
2784 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2785 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2786 vmx_capability.ept, vmx_capability.vpid);
2787 }
1c3d14fe
YS		 2788
2789 min = 0;
2790#ifdef CONFIG_X86_64
2791 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2792#endif
a547c6db
YZ		 2793 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2794 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2795 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2796 &_vmexit_control) < 0)
002c7f7c 2797 return -EIO;
1c3d14fe 2798
01e439be
YZ		 2799 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2800 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2801 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2802 &_pin_based_exec_control) < 0)
2803 return -EIO;
2804
2805 if (!(_cpu_based_2nd_exec_control &
2806 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2807 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2808 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2809
468d472f
SY		 2810 min = 0;
2811 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2812 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2813 &_vmentry_control) < 0)
002c7f7c 2814 return -EIO;
6aa8b732 2815
c68876fd 2816 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2817
2818 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2819 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2820 return -EIO;
1c3d14fe
YS		 2821
2822#ifdef CONFIG_X86_64
2823 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2824 if (vmx_msr_high & (1u<<16))
002c7f7c 2825 return -EIO;
1c3d14fe
YS		 2826#endif
2827
2828 /* Require Write-Back (WB) memory type for VMCS accesses. */
2829 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2830 return -EIO;
1c3d14fe 2831
002c7f7c
YS		 2832 vmcs_conf->size = vmx_msr_high & 0x1fff;
2833 vmcs_conf->order = get_order(vmcs_config.size);
2834 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2835
002c7f7c
YS		 2836 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2837 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2838 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2839 vmcs_conf->vmexit_ctrl = _vmexit_control;
2840 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2841
110312c8
AK		 2842 cpu_has_load_ia32_efer =
2843 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2844 VM_ENTRY_LOAD_IA32_EFER)
2845 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2846 VM_EXIT_LOAD_IA32_EFER);
2847
8bf00a52
GN		 2848 cpu_has_load_perf_global_ctrl =
2849 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2850 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2851 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2852 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2853
2854 /*
2855 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2856 * but due to arrata below it can't be used. Workaround is to use
2857 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2858 *
2859 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2860 *
2861 * AAK155 (model 26)
2862 * AAP115 (model 30)
2863 * AAT100 (model 37)
2864 * BC86,AAY89,BD102 (model 44)
2865 * BA97 (model 46)
2866 *
2867 */
2868 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2869 switch (boot_cpu_data.x86_model) {
2870 case 26:
2871 case 30:
2872 case 37:
2873 case 44:
2874 case 46:
2875 cpu_has_load_perf_global_ctrl = false;
2876 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2877 "does not work properly. Using workaround\n");
2878 break;
2879 default:
2880 break;
2881 }
2882 }
2883
1c3d14fe 2884 return 0;
c68876fd 2885}
6aa8b732
AK		 2886
2887static struct vmcs *alloc_vmcs_cpu(int cpu)
2888{
2889 int node = cpu_to_node(cpu);
2890 struct page *pages;
2891 struct vmcs *vmcs;
2892
6484eb3e 2893 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2894 if (!pages)
2895 return NULL;
2896 vmcs = page_address(pages);
1c3d14fe
YS		 2897 memset(vmcs, 0, vmcs_config.size);
2898 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2899 return vmcs;
2900}
2901
2902static struct vmcs *alloc_vmcs(void)
2903{
d3b2c338 2904 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2905}
2906
2907static void free_vmcs(struct vmcs *vmcs)
2908{
1c3d14fe 2909 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2910}
2911
d462b819
NHE		 2912/*
2913 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2914 */
2915static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2916{
2917 if (!loaded_vmcs->vmcs)
2918 return;
2919 loaded_vmcs_clear(loaded_vmcs);
2920 free_vmcs(loaded_vmcs->vmcs);
2921 loaded_vmcs->vmcs = NULL;
2922}
2923
39959588 2924static void free_kvm_area(void)
6aa8b732
AK		 2925{
2926 int cpu;
2927
3230bb47 2928 for_each_possible_cpu(cpu) {
6aa8b732 2929 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2930 per_cpu(vmxarea, cpu) = NULL;
2931 }
6aa8b732
AK		 2932}
2933
6aa8b732
AK		 2934static __init int alloc_kvm_area(void)
2935{
2936 int cpu;
2937
3230bb47 2938 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2939 struct vmcs *vmcs;
2940
2941 vmcs = alloc_vmcs_cpu(cpu);
2942 if (!vmcs) {
2943 free_kvm_area();
2944 return -ENOMEM;
2945 }
2946
2947 per_cpu(vmxarea, cpu) = vmcs;
2948 }
2949 return 0;
2950}
2951
2952static __init int hardware_setup(void)
2953{
002c7f7c
YS		 2954 if (setup_vmcs_config(&vmcs_config) < 0)
2955 return -EIO;
50a37eb4
JR		 2956
2957 if (boot_cpu_has(X86_FEATURE_NX))
2958 kvm_enable_efer_bits(EFER_NX);
2959
93ba03c2
SY		 2960 if (!cpu_has_vmx_vpid())
2961 enable_vpid = 0;
abc4fc58
AG		 2962 if (!cpu_has_vmx_shadow_vmcs())
2963 enable_shadow_vmcs = 0;
93ba03c2 2964
4bc9b982
SY		 2965 if (!cpu_has_vmx_ept() ||
2966 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2967 enable_ept = 0;
3a624e29 2968 enable_unrestricted_guest = 0;
83c3a331 2969 enable_ept_ad_bits = 0;
3a624e29
NK		 2970 }
2971
83c3a331
XH		 2972 if (!cpu_has_vmx_ept_ad_bits())
2973 enable_ept_ad_bits = 0;
2974
3a624e29
NK		 2975 if (!cpu_has_vmx_unrestricted_guest())
2976 enable_unrestricted_guest = 0;
93ba03c2
SY		 2977
2978 if (!cpu_has_vmx_flexpriority())
2979 flexpriority_enabled = 0;
2980
95ba8273
GN		 2981 if (!cpu_has_vmx_tpr_shadow())
2982 kvm_x86_ops->update_cr8_intercept = NULL;
2983
54dee993
MT		 2984 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2985 kvm_disable_largepages();
2986
4b8d54f9
ZE		 2987 if (!cpu_has_vmx_ple())
2988 ple_gap = 0;
2989
01e439be
YZ		 2990 if (!cpu_has_vmx_apicv())
2991 enable_apicv = 0;
c7c9c56c 2992
01e439be 2993 if (enable_apicv)
c7c9c56c 2994 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2995 else {
c7c9c56c 2996 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2997 kvm_x86_ops->deliver_posted_interrupt = NULL;
2998 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2999 }
83d4c286 3000
b87a51ae
NHE		 3001 if (nested)
3002 nested_vmx_setup_ctls_msrs();
3003
6aa8b732
AK		 3004 return alloc_kvm_area();
3005}
3006
3007static __exit void hardware_unsetup(void)
3008{
3009 free_kvm_area();
3010}
3011
14168786
GN		 3012static bool emulation_required(struct kvm_vcpu *vcpu)
3013{
3014 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3015}
3016
91b0aa2c 3017static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3018 struct kvm_segment *save)
6aa8b732 3019{
d99e4152
GN		 3020 if (!emulate_invalid_guest_state) {
3021 /*
3022 * CS and SS RPL should be equal during guest entry according
3023 * to VMX spec, but in reality it is not always so. Since vcpu
3024 * is in the middle of the transition from real mode to
3025 * protected mode it is safe to assume that RPL 0 is a good
3026 * default value.
3027 */
3028 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3029 save->selector &= ~SELECTOR_RPL_MASK;
3030 save->dpl = save->selector & SELECTOR_RPL_MASK;
3031 save->s = 1;
6aa8b732 3032 }
d99e4152 3033 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3034}
3035
3036static void enter_pmode(struct kvm_vcpu *vcpu)
3037{
3038 unsigned long flags;
a89a8fb9 3039 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3040
d99e4152
GN		 3041 /*
3042 * Update real mode segment cache. It may be not up-to-date if sement
3043 * register was written while vcpu was in a guest mode.
3044 */
3045 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3046 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3047 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3048 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3049 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3050 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3051
7ffd92c5 3052 vmx->rmode.vm86_active = 0;
6aa8b732 3053
2fb92db1
AK		 3054 vmx_segment_cache_clear(vmx);
3055
f5f7b2fe 3056 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3057
3058 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3059 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3060 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3061 vmcs_writel(GUEST_RFLAGS, flags);
3062
66aee91a
RR		 3063 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3064 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3065
3066 update_exception_bitmap(vcpu);
3067
91b0aa2c
GN		 3068 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3069 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3070 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3071 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3072 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3073 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3074
3075 /* CPL is always 0 when CPU enters protected mode */
3076 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3077 vmx->cpl = 0;
6aa8b732
AK		 3078}
3079
f5f7b2fe 3080static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3081{
772e0318 3082 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3083 struct kvm_segment var = *save;
3084
3085 var.dpl = 0x3;
3086 if (seg == VCPU_SREG_CS)
3087 var.type = 0x3;
3088
3089 if (!emulate_invalid_guest_state) {
3090 var.selector = var.base >> 4;
3091 var.base = var.base & 0xffff0;
3092 var.limit = 0xffff;
3093 var.g = 0;
3094 var.db = 0;
3095 var.present = 1;
3096 var.s = 1;
3097 var.l = 0;
3098 var.unusable = 0;
3099 var.type = 0x3;
3100 var.avl = 0;
3101 if (save->base & 0xf)
3102 printk_once(KERN_WARNING "kvm: segment base is not "
3103 "paragraph aligned when entering "
3104 "protected mode (seg=%d)", seg);
3105 }
6aa8b732 3106
d99e4152
GN		 3107 vmcs_write16(sf->selector, var.selector);
3108 vmcs_write32(sf->base, var.base);
3109 vmcs_write32(sf->limit, var.limit);
3110 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3111}
3112
3113static void enter_rmode(struct kvm_vcpu *vcpu)
3114{
3115 unsigned long flags;
a89a8fb9 3116 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3117
f5f7b2fe
AK		 3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3123 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3124 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3125
7ffd92c5 3126 vmx->rmode.vm86_active = 1;
6aa8b732 3127
776e58ea
GN		 3128 /*
3129 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3130 * vcpu. Warn the user that an update is overdue.
776e58ea 3131 */
4918c6ca 3132 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3133 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3134 "called before entering vcpu\n");
776e58ea 3135
2fb92db1
AK		 3136 vmx_segment_cache_clear(vmx);
3137
4918c6ca 3138 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3139 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3140 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3141
3142 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3143 vmx->rmode.save_rflags = flags;
6aa8b732 3144
053de044 3145 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3146
3147 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3148 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3149 update_exception_bitmap(vcpu);
3150
d99e4152
GN		 3151 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3152 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3153 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3154 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3155 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3156 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3157
8668a3c4 3158 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3159}
3160
401d10de
AS		 3161static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3162{
3163 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3164 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3165
3166 if (!msr)
3167 return;
401d10de 3168
44ea2b17
AK		 3169 /*
3170 * Force kernel_gs_base reloading before EFER changes, as control
3171 * of this msr depends on is_long_mode().
3172 */
3173 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3174 vcpu->arch.efer = efer;
401d10de
AS		 3175 if (efer & EFER_LMA) {
3176 vmcs_write32(VM_ENTRY_CONTROLS,
3177 vmcs_read32(VM_ENTRY_CONTROLS) |
3178 VM_ENTRY_IA32E_MODE);
3179 msr->data = efer;
3180 } else {
3181 vmcs_write32(VM_ENTRY_CONTROLS,
3182 vmcs_read32(VM_ENTRY_CONTROLS) &
3183 ~VM_ENTRY_IA32E_MODE);
3184
3185 msr->data = efer & ~EFER_LME;
3186 }
3187 setup_msrs(vmx);
3188}
3189
05b3e0c2 3190#ifdef CONFIG_X86_64
6aa8b732
AK		 3191
3192static void enter_lmode(struct kvm_vcpu *vcpu)
3193{
3194 u32 guest_tr_ar;
3195
2fb92db1
AK		 3196 vmx_segment_cache_clear(to_vmx(vcpu));
3197
6aa8b732
AK		 3198 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3199 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3200 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3201 __func__);
6aa8b732
AK		 3202 vmcs_write32(GUEST_TR_AR_BYTES,
3203 (guest_tr_ar & ~AR_TYPE_MASK)
3204 | AR_TYPE_BUSY_64_TSS);
3205 }
da38f438 3206 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3207}
3208
3209static void exit_lmode(struct kvm_vcpu *vcpu)
3210{
6aa8b732
AK		 3211 vmcs_write32(VM_ENTRY_CONTROLS,
3212 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3213 & ~VM_ENTRY_IA32E_MODE);
da38f438 3214 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3215}
3216
3217#endif
3218
2384d2b3
SY		 3219static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3220{
b9d762fa 3221 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3222 if (enable_ept) {
3223 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3224 return;
4e1096d2 3225 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3226 }
2384d2b3
SY		 3227}
3228
e8467fda
AK		 3229static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3230{
3231 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3232
3233 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3234 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3235}
3236
aff48baa
AK		 3237static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3238{
3239 if (enable_ept && is_paging(vcpu))
3240 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3241 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3242}
3243
25c4c276 3244static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3245{
fc78f519
AK		 3246 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3247
3248 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3249 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3250}
3251
1439442c
SY		 3252static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3253{
6de4f3ad
AK		 3254 if (!test_bit(VCPU_EXREG_PDPTR,
3255 (unsigned long *)&vcpu->arch.regs_dirty))
3256 return;
3257
1439442c 3258 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3259 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3260 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3261 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3262 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3263 }
3264}
3265
8f5d549f
AK		 3266static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3267{
3268 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3269 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3270 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3271 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3272 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3273 }
6de4f3ad
AK		 3274
3275 __set_bit(VCPU_EXREG_PDPTR,
3276 (unsigned long *)&vcpu->arch.regs_avail);
3277 __set_bit(VCPU_EXREG_PDPTR,
3278 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3279}
3280
5e1746d6 3281static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3282
3283static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3284 unsigned long cr0,
3285 struct kvm_vcpu *vcpu)
3286{
5233dd51
MT		 3287 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3288 vmx_decache_cr3(vcpu);
1439442c
SY		 3289 if (!(cr0 & X86_CR0_PG)) {
3290 /* From paging/starting to nonpaging */
3291 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3292 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3293 (CPU_BASED_CR3_LOAD_EXITING |
3294 CPU_BASED_CR3_STORE_EXITING));
3295 vcpu->arch.cr0 = cr0;
fc78f519 3296 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3297 } else if (!is_paging(vcpu)) {
3298 /* From nonpaging to paging */
3299 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3300 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3301 ~(CPU_BASED_CR3_LOAD_EXITING |
3302 CPU_BASED_CR3_STORE_EXITING));
3303 vcpu->arch.cr0 = cr0;
fc78f519 3304 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3305 }
95eb84a7
SY		 3306
3307 if (!(cr0 & X86_CR0_WP))
3308 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3309}
3310
6aa8b732
AK		 3311static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3312{
7ffd92c5 3313 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3314 unsigned long hw_cr0;
3315
5037878e 3316 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3317 if (enable_unrestricted_guest)
5037878e 3318 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3319 else {
5037878e 3320 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3321
218e763f
GN		 3322 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3323 enter_pmode(vcpu);
6aa8b732 3324
218e763f
GN		 3325 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3326 enter_rmode(vcpu);
3327 }
6aa8b732 3328
05b3e0c2 3329#ifdef CONFIG_X86_64
f6801dff 3330 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3331 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3332 enter_lmode(vcpu);
707d92fa 3333 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3334 exit_lmode(vcpu);
3335 }
3336#endif
3337
089d034e 3338 if (enable_ept)
1439442c
SY		 3339 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3340
02daab21 3341 if (!vcpu->fpu_active)
81231c69 3342 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3343
6aa8b732 3344 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3345 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3346 vcpu->arch.cr0 = cr0;
14168786
GN		 3347
3348 /* depends on vcpu->arch.cr0 to be set to a new value */
3349 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3350}
3351
1439442c
SY		 3352static u64 construct_eptp(unsigned long root_hpa)
3353{
3354 u64 eptp;
3355
3356 /* TODO write the value reading from MSR */
3357 eptp = VMX_EPT_DEFAULT_MT |
3358 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3359 if (enable_ept_ad_bits)
3360 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3361 eptp |= (root_hpa & PAGE_MASK);
3362
3363 return eptp;
3364}
3365
6aa8b732
AK		 3366static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3367{
1439442c
SY		 3368 unsigned long guest_cr3;
3369 u64 eptp;
3370
3371 guest_cr3 = cr3;
089d034e 3372 if (enable_ept) {
1439442c
SY		 3373 eptp = construct_eptp(cr3);
3374 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3375 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3376 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3377 ept_load_pdptrs(vcpu);
1439442c
SY		 3378 }
3379
2384d2b3 3380 vmx_flush_tlb(vcpu);
1439442c 3381 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3382}
3383
5e1746d6 3384static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3385{
7ffd92c5 3386 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3387 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3388
5e1746d6
NHE		 3389 if (cr4 & X86_CR4_VMXE) {
3390 /*
3391 * To use VMXON (and later other VMX instructions), a guest
3392 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3393 * So basically the check on whether to allow nested VMX
3394 * is here.
3395 */
3396 if (!nested_vmx_allowed(vcpu))
3397 return 1;
1a0d74e6
JK		 3398 }
3399 if (to_vmx(vcpu)->nested.vmxon &&
3400 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3401 return 1;
3402
ad312c7c 3403 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3404 if (enable_ept) {
3405 if (!is_paging(vcpu)) {
3406 hw_cr4 &= ~X86_CR4_PAE;
3407 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3408 /*
3409 * SMEP is disabled if CPU is in non-paging mode in
3410 * hardware. However KVM always uses paging mode to
3411 * emulate guest non-paging mode with TDP.
3412 * To emulate this behavior, SMEP needs to be manually
3413 * disabled when guest switches to non-paging mode.
3414 */
3415 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3416 } else if (!(cr4 & X86_CR4_PAE)) {
3417 hw_cr4 &= ~X86_CR4_PAE;
3418 }
3419 }
1439442c
SY		 3420
3421 vmcs_writel(CR4_READ_SHADOW, cr4);
3422 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3423 return 0;
6aa8b732
AK		 3424}
3425
6aa8b732
AK		 3426static void vmx_get_segment(struct kvm_vcpu *vcpu,
3427 struct kvm_segment *var, int seg)
3428{
a9179499 3429 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3430 u32 ar;
3431
c6ad1153 3432 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3433 *var = vmx->rmode.segs[seg];
a9179499 3434 if (seg == VCPU_SREG_TR
2fb92db1 3435 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3436 return;
1390a28b
AK		 3437 var->base = vmx_read_guest_seg_base(vmx, seg);
3438 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3439 return;
a9179499 3440 }
2fb92db1
AK		 3441 var->base = vmx_read_guest_seg_base(vmx, seg);
3442 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3443 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3444 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3445 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3446 var->type = ar & 15;
3447 var->s = (ar >> 4) & 1;
3448 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3449 /*
3450 * Some userspaces do not preserve unusable property. Since usable
3451 * segment has to be present according to VMX spec we can use present
3452 * property to amend userspace bug by making unusable segment always
3453 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3454 * segment as unusable.
3455 */
3456 var->present = !var->unusable;
6aa8b732
AK		 3457 var->avl = (ar >> 12) & 1;
3458 var->l = (ar >> 13) & 1;
3459 var->db = (ar >> 14) & 1;
3460 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3461}
3462
a9179499
AK		 3463static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3464{
a9179499
AK		 3465 struct kvm_segment s;
3466
3467 if (to_vmx(vcpu)->rmode.vm86_active) {
3468 vmx_get_segment(vcpu, &s, seg);
3469 return s.base;
3470 }
2fb92db1 3471 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3472}
3473
b09408d0 3474static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3475{
b09408d0
MT		 3476 struct vcpu_vmx *vmx = to_vmx(vcpu);
3477
3eeb3288 3478 if (!is_protmode(vcpu))
2e4d2653
IE		 3479 return 0;
3480
f4c63e5d
AK		 3481 if (!is_long_mode(vcpu)
3482 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3483 return 3;
3484
69c73028
AK		 3485 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3486 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3487 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3488 }
d881e6f6
AK		 3489
3490 return vmx->cpl;
69c73028
AK		 3491}
3492
3493
653e3108 3494static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3495{
6aa8b732
AK		 3496 u32 ar;
3497
f0495f9b 3498 if (var->unusable || !var->present)
6aa8b732
AK		 3499 ar = 1 << 16;
3500 else {
3501 ar = var->type & 15;
3502 ar |= (var->s & 1) << 4;
3503 ar |= (var->dpl & 3) << 5;
3504 ar |= (var->present & 1) << 7;
3505 ar |= (var->avl & 1) << 12;
3506 ar |= (var->l & 1) << 13;
3507 ar |= (var->db & 1) << 14;
3508 ar |= (var->g & 1) << 15;
3509 }
653e3108
AK		 3510
3511 return ar;
3512}
3513
3514static void vmx_set_segment(struct kvm_vcpu *vcpu,
3515 struct kvm_segment *var, int seg)
3516{
7ffd92c5 3517 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3518 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3519
2fb92db1 3520 vmx_segment_cache_clear(vmx);
2f143240
GN		 3521 if (seg == VCPU_SREG_CS)
3522 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3523
1ecd50a9
GN		 3524 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3525 vmx->rmode.segs[seg] = *var;
3526 if (seg == VCPU_SREG_TR)
3527 vmcs_write16(sf->selector, var->selector);
3528 else if (var->s)
3529 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3530 goto out;
653e3108 3531 }
1ecd50a9 3532
653e3108
AK		 3533 vmcs_writel(sf->base, var->base);
3534 vmcs_write32(sf->limit, var->limit);
3535 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3536
3537 /*
3538 * Fix the "Accessed" bit in AR field of segment registers for older
3539 * qemu binaries.
3540 * IA32 arch specifies that at the time of processor reset the
3541 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3542 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3543 * state vmexit when "unrestricted guest" mode is turned on.
3544 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3545 * tree. Newer qemu binaries with that qemu fix would not need this
3546 * kvm hack.
3547 */
3548 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3549 var->type |= 0x1; /* Accessed */
3a624e29 3550
f924d66d 3551 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3552
3553out:
14168786 3554 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3555}
3556
6aa8b732
AK		 3557static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3558{
2fb92db1 3559 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3560
3561 *db = (ar >> 14) & 1;
3562 *l = (ar >> 13) & 1;
3563}
3564
89a27f4d 3565static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3566{
89a27f4d
GN		 3567 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3568 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3569}
3570
89a27f4d 3571static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3572{
89a27f4d
GN		 3573 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3574 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3575}
3576
89a27f4d 3577static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3578{
89a27f4d
GN		 3579 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3580 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3581}
3582
89a27f4d 3583static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3584{
89a27f4d
GN		 3585 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3586 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3587}
3588
648dfaa7
MG		 3589static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3590{
3591 struct kvm_segment var;
3592 u32 ar;
3593
3594 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3595 var.dpl = 0x3;
0647f4aa
GN		 3596 if (seg == VCPU_SREG_CS)
3597 var.type = 0x3;
648dfaa7
MG		 3598 ar = vmx_segment_access_rights(&var);
3599
3600 if (var.base != (var.selector << 4))
3601 return false;
89efbed0 3602 if (var.limit != 0xffff)
648dfaa7 3603 return false;
07f42f5f 3604 if (ar != 0xf3)
648dfaa7
MG		 3605 return false;
3606
3607 return true;
3608}
3609
3610static bool code_segment_valid(struct kvm_vcpu *vcpu)
3611{
3612 struct kvm_segment cs;
3613 unsigned int cs_rpl;
3614
3615 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3616 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3617
1872a3f4
AK		 3618 if (cs.unusable)
3619 return false;
648dfaa7
MG		 3620 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3621 return false;
3622 if (!cs.s)
3623 return false;
1872a3f4 3624 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3625 if (cs.dpl > cs_rpl)
3626 return false;
1872a3f4 3627 } else {
648dfaa7
MG		 3628 if (cs.dpl != cs_rpl)
3629 return false;
3630 }
3631 if (!cs.present)
3632 return false;
3633
3634 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3635 return true;
3636}
3637
3638static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3639{
3640 struct kvm_segment ss;
3641 unsigned int ss_rpl;
3642
3643 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3644 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3645
1872a3f4
AK		 3646 if (ss.unusable)
3647 return true;
3648 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3649 return false;
3650 if (!ss.s)
3651 return false;
3652 if (ss.dpl != ss_rpl) /* DPL != RPL */
3653 return false;
3654 if (!ss.present)
3655 return false;
3656
3657 return true;
3658}
3659
3660static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3661{
3662 struct kvm_segment var;
3663 unsigned int rpl;
3664
3665 vmx_get_segment(vcpu, &var, seg);
3666 rpl = var.selector & SELECTOR_RPL_MASK;
3667
1872a3f4
AK		 3668 if (var.unusable)
3669 return true;
648dfaa7
MG		 3670 if (!var.s)
3671 return false;
3672 if (!var.present)
3673 return false;
3674 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3675 if (var.dpl < rpl) /* DPL < RPL */
3676 return false;
3677 }
3678
3679 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3680 * rights flags
3681 */
3682 return true;
3683}
3684
3685static bool tr_valid(struct kvm_vcpu *vcpu)
3686{
3687 struct kvm_segment tr;
3688
3689 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3690
1872a3f4
AK		 3691 if (tr.unusable)
3692 return false;
648dfaa7
MG		 3693 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3694 return false;
1872a3f4 3695 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3696 return false;
3697 if (!tr.present)
3698 return false;
3699
3700 return true;
3701}
3702
3703static bool ldtr_valid(struct kvm_vcpu *vcpu)
3704{
3705 struct kvm_segment ldtr;
3706
3707 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3708
1872a3f4
AK		 3709 if (ldtr.unusable)
3710 return true;
648dfaa7
MG		 3711 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3712 return false;
3713 if (ldtr.type != 2)
3714 return false;
3715 if (!ldtr.present)
3716 return false;
3717
3718 return true;
3719}
3720
3721static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3722{
3723 struct kvm_segment cs, ss;
3724
3725 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3726 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3727
3728 return ((cs.selector & SELECTOR_RPL_MASK) ==
3729 (ss.selector & SELECTOR_RPL_MASK));
3730}
3731
3732/*
3733 * Check if guest state is valid. Returns true if valid, false if
3734 * not.
3735 * We assume that registers are always usable
3736 */
3737static bool guest_state_valid(struct kvm_vcpu *vcpu)
3738{
c5e97c80
GN		 3739 if (enable_unrestricted_guest)
3740 return true;
3741
648dfaa7 3742 /* real mode guest state checks */
f13882d8 3743 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3744 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3745 return false;
3746 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3747 return false;
3748 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3749 return false;
3750 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3751 return false;
3752 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3753 return false;
3754 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3755 return false;
3756 } else {
3757 /* protected mode guest state checks */
3758 if (!cs_ss_rpl_check(vcpu))
3759 return false;
3760 if (!code_segment_valid(vcpu))
3761 return false;
3762 if (!stack_segment_valid(vcpu))
3763 return false;
3764 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3765 return false;
3766 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3767 return false;
3768 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3769 return false;
3770 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3771 return false;
3772 if (!tr_valid(vcpu))
3773 return false;
3774 if (!ldtr_valid(vcpu))
3775 return false;
3776 }
3777 /* TODO:
3778 * - Add checks on RIP
3779 * - Add checks on RFLAGS
3780 */
3781
3782 return true;
3783}
3784
d77c26fc 3785static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3786{
40dcaa9f 3787 gfn_t fn;
195aefde 3788 u16 data = 0;
40dcaa9f 3789 int r, idx, ret = 0;
6aa8b732 3790
40dcaa9f 3791 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3792 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3793 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3794 if (r < 0)
10589a46 3795 goto out;
195aefde 3796 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3797 r = kvm_write_guest_page(kvm, fn++, &data,
3798 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3799 if (r < 0)
10589a46 3800 goto out;
195aefde
IE		 3801 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3802 if (r < 0)
10589a46 3803 goto out;
195aefde
IE		 3804 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3805 if (r < 0)
10589a46 3806 goto out;
195aefde 3807 data = ~0;
10589a46
MT		 3808 r = kvm_write_guest_page(kvm, fn, &data,
3809 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3810 sizeof(u8));
195aefde 3811 if (r < 0)
10589a46
MT		 3812 goto out;
3813
3814 ret = 1;
3815out:
40dcaa9f 3816 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3817 return ret;
6aa8b732
AK		 3818}
3819
b7ebfb05
SY		 3820static int init_rmode_identity_map(struct kvm *kvm)
3821{
40dcaa9f 3822 int i, idx, r, ret;
b7ebfb05
SY		 3823 pfn_t identity_map_pfn;
3824 u32 tmp;
3825
089d034e 3826 if (!enable_ept)
b7ebfb05
SY		 3827 return 1;
3828 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3829 printk(KERN_ERR "EPT: identity-mapping pagetable "
3830 "haven't been allocated!\n");
3831 return 0;
3832 }
3833 if (likely(kvm->arch.ept_identity_pagetable_done))
3834 return 1;
3835 ret = 0;
b927a3ce 3836 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3837 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3838 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3839 if (r < 0)
3840 goto out;
3841 /* Set up identity-mapping pagetable for EPT in real mode */
3842 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3843 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3844 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3845 r = kvm_write_guest_page(kvm, identity_map_pfn,
3846 &tmp, i * sizeof(tmp), sizeof(tmp));
3847 if (r < 0)
3848 goto out;
3849 }
3850 kvm->arch.ept_identity_pagetable_done = true;
3851 ret = 1;
3852out:
40dcaa9f 3853 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3854 return ret;
3855}
3856
6aa8b732
AK		 3857static void seg_setup(int seg)
3858{
772e0318 3859 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3860 unsigned int ar;
6aa8b732
AK		 3861
3862 vmcs_write16(sf->selector, 0);
3863 vmcs_writel(sf->base, 0);
3864 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3865 ar = 0x93;
3866 if (seg == VCPU_SREG_CS)
3867 ar |= 0x08; /* code segment */
3a624e29
NK		 3868
3869 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3870}
3871
f78e0e2e
SY		 3872static int alloc_apic_access_page(struct kvm *kvm)
3873{
4484141a 3874 struct page *page;
f78e0e2e
SY		 3875 struct kvm_userspace_memory_region kvm_userspace_mem;
3876 int r = 0;
3877
79fac95e 3878 mutex_lock(&kvm->slots_lock);
bfc6d222 3879 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3880 goto out;
3881 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3882 kvm_userspace_mem.flags = 0;
3883 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3884 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3885 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3886 if (r)
3887 goto out;
72dc67a6 3888
4484141a
XG		 3889 page = gfn_to_page(kvm, 0xfee00);
3890 if (is_error_page(page)) {
3891 r = -EFAULT;
3892 goto out;
3893 }
3894
3895 kvm->arch.apic_access_page = page;
f78e0e2e 3896out:
79fac95e 3897 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3898 return r;
3899}
3900
b7ebfb05
SY		 3901static int alloc_identity_pagetable(struct kvm *kvm)
3902{
4484141a 3903 struct page *page;
b7ebfb05
SY		 3904 struct kvm_userspace_memory_region kvm_userspace_mem;
3905 int r = 0;
3906
79fac95e 3907 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3908 if (kvm->arch.ept_identity_pagetable)
3909 goto out;
3910 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3911 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3912 kvm_userspace_mem.guest_phys_addr =
3913 kvm->arch.ept_identity_map_addr;
b7ebfb05 3914 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3915 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3916 if (r)
3917 goto out;
3918
4484141a
XG		 3919 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3920 if (is_error_page(page)) {
3921 r = -EFAULT;
3922 goto out;
3923 }
3924
3925 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3926out:
79fac95e 3927 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3928 return r;
3929}
3930
2384d2b3
SY		 3931static void allocate_vpid(struct vcpu_vmx *vmx)
3932{
3933 int vpid;
3934
3935 vmx->vpid = 0;
919818ab 3936 if (!enable_vpid)
2384d2b3
SY		 3937 return;
3938 spin_lock(&vmx_vpid_lock);
3939 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3940 if (vpid < VMX_NR_VPIDS) {
3941 vmx->vpid = vpid;
3942 __set_bit(vpid, vmx_vpid_bitmap);
3943 }
3944 spin_unlock(&vmx_vpid_lock);
3945}
3946
cdbecfc3
LJ		 3947static void free_vpid(struct vcpu_vmx *vmx)
3948{
3949 if (!enable_vpid)
3950 return;
3951 spin_lock(&vmx_vpid_lock);
3952 if (vmx->vpid != 0)
3953 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3954 spin_unlock(&vmx_vpid_lock);
3955}
3956
8d14695f
YZ		 3957#define MSR_TYPE_R 1
3958#define MSR_TYPE_W 2
3959static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3960 u32 msr, int type)
25c5f225 3961{
3e7c73e9 3962 int f = sizeof(unsigned long);
25c5f225
SY		 3963
3964 if (!cpu_has_vmx_msr_bitmap())
3965 return;
3966
3967 /*
3968 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3969 * have the write-low and read-high bitmap offsets the wrong way round.
3970 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3971 */
25c5f225 3972 if (msr <= 0x1fff) {
8d14695f
YZ		 3973 if (type & MSR_TYPE_R)
3974 /* read-low */
3975 __clear_bit(msr, msr_bitmap + 0x000 / f);
3976
3977 if (type & MSR_TYPE_W)
3978 /* write-low */
3979 __clear_bit(msr, msr_bitmap + 0x800 / f);
3980
25c5f225
SY		 3981 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3982 msr &= 0x1fff;
8d14695f
YZ		 3983 if (type & MSR_TYPE_R)
3984 /* read-high */
3985 __clear_bit(msr, msr_bitmap + 0x400 / f);
3986
3987 if (type & MSR_TYPE_W)
3988 /* write-high */
3989 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3990
3991 }
3992}
3993
3994static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3995 u32 msr, int type)
3996{
3997 int f = sizeof(unsigned long);
3998
3999 if (!cpu_has_vmx_msr_bitmap())
4000 return;
4001
4002 /*
4003 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4004 * have the write-low and read-high bitmap offsets the wrong way round.
4005 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4006 */
4007 if (msr <= 0x1fff) {
4008 if (type & MSR_TYPE_R)
4009 /* read-low */
4010 __set_bit(msr, msr_bitmap + 0x000 / f);
4011
4012 if (type & MSR_TYPE_W)
4013 /* write-low */
4014 __set_bit(msr, msr_bitmap + 0x800 / f);
4015
4016 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4017 msr &= 0x1fff;
4018 if (type & MSR_TYPE_R)
4019 /* read-high */
4020 __set_bit(msr, msr_bitmap + 0x400 / f);
4021
4022 if (type & MSR_TYPE_W)
4023 /* write-high */
4024 __set_bit(msr, msr_bitmap + 0xc00 / f);
4025
25c5f225 4026 }
25c5f225
SY		 4027}
4028
5897297b
AK		 4029static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4030{
4031 if (!longmode_only)
8d14695f
YZ		 4032 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4033 msr, MSR_TYPE_R | MSR_TYPE_W);
4034 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4035 msr, MSR_TYPE_R | MSR_TYPE_W);
4036}
4037
4038static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4039{
4040 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4041 msr, MSR_TYPE_R);
4042 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4043 msr, MSR_TYPE_R);
4044}
4045
4046static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4047{
4048 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4049 msr, MSR_TYPE_R);
4050 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4051 msr, MSR_TYPE_R);
4052}
4053
4054static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4055{
4056 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4057 msr, MSR_TYPE_W);
4058 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4059 msr, MSR_TYPE_W);
5897297b
AK		 4060}
4061
01e439be
YZ		 4062static int vmx_vm_has_apicv(struct kvm *kvm)
4063{
4064 return enable_apicv && irqchip_in_kernel(kvm);
4065}
4066
a20ed54d
YZ		 4067/*
4068 * Send interrupt to vcpu via posted interrupt way.
4069 * 1. If target vcpu is running(non-root mode), send posted interrupt
4070 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4071 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4072 * interrupt from PIR in next vmentry.
4073 */
4074static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4075{
4076 struct vcpu_vmx *vmx = to_vmx(vcpu);
4077 int r;
4078
4079 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4080 return;
4081
4082 r = pi_test_and_set_on(&vmx->pi_desc);
4083 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4084#ifdef CONFIG_SMP
a20ed54d
YZ		 4085 if (!r && (vcpu->mode == IN_GUEST_MODE))
4086 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4087 POSTED_INTR_VECTOR);
4088 else
6ffbbbba 4089#endif
a20ed54d
YZ		 4090 kvm_vcpu_kick(vcpu);
4091}
4092
4093static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4094{
4095 struct vcpu_vmx *vmx = to_vmx(vcpu);
4096
4097 if (!pi_test_and_clear_on(&vmx->pi_desc))
4098 return;
4099
4100 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4101}
4102
4103static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4104{
4105 return;
4106}
4107
a3a8ff8e
NHE		 4108/*
4109 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4110 * will not change in the lifetime of the guest.
4111 * Note that host-state that does change is set elsewhere. E.g., host-state
4112 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4113 */
a547c6db 4114static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4115{
4116 u32 low32, high32;
4117 unsigned long tmpl;
4118 struct desc_ptr dt;
4119
b1a74bf8 4120 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4121 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4122 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4123
4124 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4125#ifdef CONFIG_X86_64
4126 /*
4127 * Load null selectors, so we can avoid reloading them in
4128 * __vmx_load_host_state(), in case userspace uses the null selectors
4129 * too (the expected case).
4130 */
4131 vmcs_write16(HOST_DS_SELECTOR, 0);
4132 vmcs_write16(HOST_ES_SELECTOR, 0);
4133#else
a3a8ff8e
NHE		 4134 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4135 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4136#endif
a3a8ff8e
NHE		 4137 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4138 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4139
4140 native_store_idt(&dt);
4141 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4142 vmx->host_idt_base = dt.address;
a3a8ff8e 4143
83287ea4 4144 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4145
4146 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4147 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4148 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4149 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4150
4151 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4152 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4153 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4154 }
4155}
4156
bf8179a0
NHE		 4157static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4158{
4159 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4160 if (enable_ept)
4161 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4162 if (is_guest_mode(&vmx->vcpu))
4163 vmx->vcpu.arch.cr4_guest_owned_bits &=
4164 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4165 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4166}
4167
01e439be
YZ		 4168static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4169{
4170 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4171
4172 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4173 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4174 return pin_based_exec_ctrl;
4175}
4176
bf8179a0
NHE		 4177static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4178{
4179 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4180 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4181 exec_control &= ~CPU_BASED_TPR_SHADOW;
4182#ifdef CONFIG_X86_64
4183 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4184 CPU_BASED_CR8_LOAD_EXITING;
4185#endif
4186 }
4187 if (!enable_ept)
4188 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4189 CPU_BASED_CR3_LOAD_EXITING |
4190 CPU_BASED_INVLPG_EXITING;
4191 return exec_control;
4192}
4193
4194static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4195{
4196 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4197 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4198 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4199 if (vmx->vpid == 0)
4200 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4201 if (!enable_ept) {
4202 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4203 enable_unrestricted_guest = 0;
ad756a16
MJ		 4204 /* Enable INVPCID for non-ept guests may cause performance regression. */
4205 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4206 }
4207 if (!enable_unrestricted_guest)
4208 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4209 if (!ple_gap)
4210 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4211 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4212 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4213 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4214 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4215 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4216 (handle_vmptrld).
4217 We can NOT enable shadow_vmcs here because we don't have yet
4218 a current VMCS12
4219 */
4220 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4221 return exec_control;
4222}
4223
ce88decf
XG		 4224static void ept_set_mmio_spte_mask(void)
4225{
4226 /*
4227 * EPT Misconfigurations can be generated if the value of bits 2:0
4228 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4229 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4230 * spte.
4231 */
885032b9 4232 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4233}
4234
6aa8b732
AK		 4235/*
4236 * Sets up the vmcs for emulated real mode.
4237 */
8b9cf98c 4238static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4239{
2e4ce7f5 4240#ifdef CONFIG_X86_64
6aa8b732 4241 unsigned long a;
2e4ce7f5 4242#endif
6aa8b732 4243 int i;
6aa8b732 4244
6aa8b732 4245 /* I/O */
3e7c73e9
AK		 4246 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4247 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4248
4607c2d7
AG		 4249 if (enable_shadow_vmcs) {
4250 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4251 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4252 }
25c5f225 4253 if (cpu_has_vmx_msr_bitmap())
5897297b 4254 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4255
6aa8b732
AK		 4256 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4257
6aa8b732 4258 /* Control */
01e439be 4259 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4260
bf8179a0 4261 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4262
83ff3b9d 4263 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4264 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4265 vmx_secondary_exec_control(vmx));
83ff3b9d 4266 }
f78e0e2e 4267
01e439be 4268 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4269 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4270 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4271 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4272 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4273
4274 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4275
4276 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4277 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4278 }
4279
4b8d54f9
ZE		 4280 if (ple_gap) {
4281 vmcs_write32(PLE_GAP, ple_gap);
4282 vmcs_write32(PLE_WINDOW, ple_window);
4283 }
4284
c3707958
XG		 4285 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4286 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4287 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4288
9581d442
AK		 4289 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4290 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4291 vmx_set_constant_host_state(vmx);
05b3e0c2 4292#ifdef CONFIG_X86_64
6aa8b732
AK		 4293 rdmsrl(MSR_FS_BASE, a);
4294 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4295 rdmsrl(MSR_GS_BASE, a);
4296 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4297#else
4298 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4299 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4300#endif
4301
2cc51560
ED		 4302 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4303 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4304 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4305 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4306 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4307
468d472f 4308 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4309 u32 msr_low, msr_high;
4310 u64 host_pat;
468d472f
SY		 4311 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4312 host_pat = msr_low | ((u64) msr_high << 32);
4313 /* Write the default value follow host pat */
4314 vmcs_write64(GUEST_IA32_PAT, host_pat);
4315 /* Keep arch.pat sync with GUEST_IA32_PAT */
4316 vmx->vcpu.arch.pat = host_pat;
4317 }
4318
6aa8b732
AK		 4319 for (i = 0; i < NR_VMX_MSR; ++i) {
4320 u32 index = vmx_msr_index[i];
4321 u32 data_low, data_high;
a2fa3e9f 4322 int j = vmx->nmsrs;
6aa8b732
AK		 4323
4324 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4325 continue;
432bd6cb
AK		 4326 if (wrmsr_safe(index, data_low, data_high) < 0)
4327 continue;
26bb0981
AK		 4328 vmx->guest_msrs[j].index = i;
4329 vmx->guest_msrs[j].data = 0;
d5696725 4330 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4331 ++vmx->nmsrs;
6aa8b732 4332 }
6aa8b732 4333
1c3d14fe 4334 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4335
4336 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4337 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4338
e00c8cf2 4339 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4340 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4341
4342 return 0;
4343}
4344
57f252f2 4345static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4346{
4347 struct vcpu_vmx *vmx = to_vmx(vcpu);
4348 u64 msr;
e00c8cf2 4349
7ffd92c5 4350 vmx->rmode.vm86_active = 0;
e00c8cf2 4351
3b86cd99
JK		 4352 vmx->soft_vnmi_blocked = 0;
4353
ad312c7c 4354 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4355 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4356 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4357 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4358 msr |= MSR_IA32_APICBASE_BSP;
4359 kvm_set_apic_base(&vmx->vcpu, msr);
4360
2fb92db1
AK		 4361 vmx_segment_cache_clear(vmx);
4362
5706be0d 4363 seg_setup(VCPU_SREG_CS);
66450a21 4364 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4365 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4366
4367 seg_setup(VCPU_SREG_DS);
4368 seg_setup(VCPU_SREG_ES);
4369 seg_setup(VCPU_SREG_FS);
4370 seg_setup(VCPU_SREG_GS);
4371 seg_setup(VCPU_SREG_SS);
4372
4373 vmcs_write16(GUEST_TR_SELECTOR, 0);
4374 vmcs_writel(GUEST_TR_BASE, 0);
4375 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4376 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4377
4378 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4379 vmcs_writel(GUEST_LDTR_BASE, 0);
4380 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4381 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4382
4383 vmcs_write32(GUEST_SYSENTER_CS, 0);
4384 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4385 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4386
4387 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4388 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4389
e00c8cf2
AK		 4390 vmcs_writel(GUEST_GDTR_BASE, 0);
4391 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4392
4393 vmcs_writel(GUEST_IDTR_BASE, 0);
4394 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4395
443381a8 4396 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4397 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4398 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4399
e00c8cf2
AK		 4400 /* Special registers */
4401 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4402
4403 setup_msrs(vmx);
4404
6aa8b732
AK		 4405 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4406
f78e0e2e
SY		 4407 if (cpu_has_vmx_tpr_shadow()) {
4408 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4409 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4410 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4411 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4412 vmcs_write32(TPR_THRESHOLD, 0);
4413 }
4414
4415 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4416 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4417 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4418
01e439be
YZ		 4419 if (vmx_vm_has_apicv(vcpu->kvm))
4420 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4421
2384d2b3
SY		 4422 if (vmx->vpid != 0)
4423 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4424
fa40052c 4425 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4426 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4427 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4428 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4429 vmx_fpu_activate(&vmx->vcpu);
4430 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4431
b9d762fa 4432 vpid_sync_context(vmx);
6aa8b732
AK		 4433}
4434
b6f1250e
NHE		 4435/*
4436 * In nested virtualization, check if L1 asked to exit on external interrupts.
4437 * For most existing hypervisors, this will always return true.
4438 */
4439static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4440{
4441 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4442 PIN_BASED_EXT_INTR_MASK;
4443}
4444
ea8ceb83
JK		 4445static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4446{
4447 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4448 PIN_BASED_NMI_EXITING;
4449}
4450
730dca42 4451static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4452{
4453 u32 cpu_based_vm_exec_control;
730dca42
JK		 4454
4455 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4456 /*
4457 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4458 * inject to L1 now because L2 must run. The caller will have
4459 * to make L2 exit right after entry, so we can inject to L1
4460 * more promptly.
b6f1250e 4461 */
730dca42 4462 return -EBUSY;
3b86cd99
JK		 4463
4464 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4465 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4466 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4467 return 0;
3b86cd99
JK		 4468}
4469
03b28f81 4470static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4471{
4472 u32 cpu_based_vm_exec_control;
4473
03b28f81
JK		 4474 if (!cpu_has_virtual_nmis())
4475 return enable_irq_window(vcpu);
4476
4477 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4478 return enable_irq_window(vcpu);
3b86cd99
JK		 4479
4480 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4481 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4482 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4483 return 0;
3b86cd99
JK		 4484}
4485
66fd3f7f 4486static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4487{
9c8cba37 4488 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4489 uint32_t intr;
4490 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4491
229456fc 4492 trace_kvm_inj_virq(irq);
2714d1d3 4493
fa89a817 4494 ++vcpu->stat.irq_injections;
7ffd92c5 4495 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4496 int inc_eip = 0;
4497 if (vcpu->arch.interrupt.soft)
4498 inc_eip = vcpu->arch.event_exit_inst_len;
4499 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4500 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4501 return;
4502 }
66fd3f7f
GN		 4503 intr = irq | INTR_INFO_VALID_MASK;
4504 if (vcpu->arch.interrupt.soft) {
4505 intr |= INTR_TYPE_SOFT_INTR;
4506 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4507 vmx->vcpu.arch.event_exit_inst_len);
4508 } else
4509 intr |= INTR_TYPE_EXT_INTR;
4510 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4511}
4512
f08864b4
SY		 4513static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4514{
66a5a347
JK		 4515 struct vcpu_vmx *vmx = to_vmx(vcpu);
4516
0b6ac343
NHE		 4517 if (is_guest_mode(vcpu))
4518 return;
4519
3b86cd99
JK		 4520 if (!cpu_has_virtual_nmis()) {
4521 /*
4522 * Tracking the NMI-blocked state in software is built upon
4523 * finding the next open IRQ window. This, in turn, depends on
4524 * well-behaving guests: They have to keep IRQs disabled at
4525 * least as long as the NMI handler runs. Otherwise we may
4526 * cause NMI nesting, maybe breaking the guest. But as this is
4527 * highly unlikely, we can live with the residual risk.
4528 */
4529 vmx->soft_vnmi_blocked = 1;
4530 vmx->vnmi_blocked_time = 0;
4531 }
4532
487b391d 4533 ++vcpu->stat.nmi_injections;
9d58b931 4534 vmx->nmi_known_unmasked = false;
7ffd92c5 4535 if (vmx->rmode.vm86_active) {
71f9833b 4536 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4537 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4538 return;
4539 }
f08864b4
SY		 4540 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4541 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4542}
4543
3cfc3092
JK		 4544static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4545{
4546 if (!cpu_has_virtual_nmis())
4547 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4548 if (to_vmx(vcpu)->nmi_known_unmasked)
4549 return false;
c332c83a 4550 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4551}
4552
4553static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4554{
4555 struct vcpu_vmx *vmx = to_vmx(vcpu);
4556
4557 if (!cpu_has_virtual_nmis()) {
4558 if (vmx->soft_vnmi_blocked != masked) {
4559 vmx->soft_vnmi_blocked = masked;
4560 vmx->vnmi_blocked_time = 0;
4561 }
4562 } else {
9d58b931 4563 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4564 if (masked)
4565 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4566 GUEST_INTR_STATE_NMI);
4567 else
4568 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4569 GUEST_INTR_STATE_NMI);
4570 }
4571}
4572
2505dc9f
JK		 4573static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4574{
ea8ceb83
JK		 4575 if (is_guest_mode(vcpu)) {
4576 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4577
4578 if (to_vmx(vcpu)->nested.nested_run_pending)
4579 return 0;
4580 if (nested_exit_on_nmi(vcpu)) {
4581 nested_vmx_vmexit(vcpu);
4582 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4583 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4584 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4585 /*
4586 * The NMI-triggered VM exit counts as injection:
4587 * clear this one and block further NMIs.
4588 */
4589 vcpu->arch.nmi_pending = 0;
4590 vmx_set_nmi_mask(vcpu, true);
4591 return 0;
4592 }
4593 }
4594
2505dc9f
JK		 4595 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4596 return 0;
4597
4598 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4599 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4600 | GUEST_INTR_STATE_NMI));
4601}
4602
78646121
GN		 4603static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4604{
e8457c67 4605 if (is_guest_mode(vcpu)) {
51cfe38e 4606 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4607
4608 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4609 return 0;
e8457c67
JK		 4610 if (nested_exit_on_intr(vcpu)) {
4611 nested_vmx_vmexit(vcpu);
4612 vmcs12->vm_exit_reason =
4613 EXIT_REASON_EXTERNAL_INTERRUPT;
4614 vmcs12->vm_exit_intr_info = 0;
4615 /*
4616 * fall through to normal code, but now in L1, not L2
4617 */
4618 }
b6f1250e
NHE		 4619 }
4620
c4282df9
GN		 4621 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4622 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4623 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4624}
4625
cbc94022
IE		 4626static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4627{
4628 int ret;
4629 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4630 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4631 .guest_phys_addr = addr,
4632 .memory_size = PAGE_SIZE * 3,
4633 .flags = 0,
4634 };
4635
47ae31e2 4636 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4637 if (ret)
4638 return ret;
bfc6d222 4639 kvm->arch.tss_addr = addr;
93ea5388
GN		 4640 if (!init_rmode_tss(kvm))
4641 return -ENOMEM;
4642
cbc94022
IE		 4643 return 0;
4644}
4645
0ca1b4f4 4646static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4647{
77ab6db0 4648 switch (vec) {
77ab6db0 4649 case BP_VECTOR:
c573cd22
JK		 4650 /*
4651 * Update instruction length as we may reinject the exception
4652 * from user space while in guest debugging mode.
4653 */
4654 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4655 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4656 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4657 return false;
4658 /* fall through */
4659 case DB_VECTOR:
4660 if (vcpu->guest_debug &
4661 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4662 return false;
d0bfb940
JK		 4663 /* fall through */
4664 case DE_VECTOR:
77ab6db0
JK		 4665 case OF_VECTOR:
4666 case BR_VECTOR:
4667 case UD_VECTOR:
4668 case DF_VECTOR:
4669 case SS_VECTOR:
4670 case GP_VECTOR:
4671 case MF_VECTOR:
0ca1b4f4
GN		 4672 return true;
4673 break;
77ab6db0 4674 }
0ca1b4f4
GN		 4675 return false;
4676}
4677
4678static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4679 int vec, u32 err_code)
4680{
4681 /*
4682 * Instruction with address size override prefix opcode 0x67
4683 * Cause the #SS fault with 0 error code in VM86 mode.
4684 */
4685 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4686 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4687 if (vcpu->arch.halt_request) {
4688 vcpu->arch.halt_request = 0;
4689 return kvm_emulate_halt(vcpu);
4690 }
4691 return 1;
4692 }
4693 return 0;
4694 }
4695
4696 /*
4697 * Forward all other exceptions that are valid in real mode.
4698 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4699 * the required debugging infrastructure rework.
4700 */
4701 kvm_queue_exception(vcpu, vec);
4702 return 1;
6aa8b732
AK		 4703}
4704
a0861c02
AK		 4705/*
4706 * Trigger machine check on the host. We assume all the MSRs are already set up
4707 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4708 * We pass a fake environment to the machine check handler because we want
4709 * the guest to be always treated like user space, no matter what context
4710 * it used internally.
4711 */
4712static void kvm_machine_check(void)
4713{
4714#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4715 struct pt_regs regs = {
4716 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4717 .flags = X86_EFLAGS_IF,
4718 };
4719
4720 do_machine_check(&regs, 0);
4721#endif
4722}
4723
851ba692 4724static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4725{
4726 /* already handled by vcpu_run */
4727 return 1;
4728}
4729
851ba692 4730static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4731{
1155f76a 4732 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4733 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4734 u32 intr_info, ex_no, error_code;
42dbaa5a 4735 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4736 u32 vect_info;
4737 enum emulation_result er;
4738
1155f76a 4739 vect_info = vmx->idt_vectoring_info;
88786475 4740 intr_info = vmx->exit_intr_info;
6aa8b732 4741
a0861c02 4742 if (is_machine_check(intr_info))
851ba692 4743 return handle_machine_check(vcpu);
a0861c02 4744
e4a41889 4745 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4746 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4747
4748 if (is_no_device(intr_info)) {
5fd86fcf 4749 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4750 return 1;
4751 }
4752
7aa81cc0 4753 if (is_invalid_opcode(intr_info)) {
51d8b661 4754 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4755 if (er != EMULATE_DONE)
7ee5d940 4756 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4757 return 1;
4758 }
4759
6aa8b732 4760 error_code = 0;
2e11384c 4761 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4762 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4763
4764 /*
4765 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4766 * MMIO, it is better to report an internal error.
4767 * See the comments in vmx_handle_exit.
4768 */
4769 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4770 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4771 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4772 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4773 vcpu->run->internal.ndata = 2;
4774 vcpu->run->internal.data[0] = vect_info;
4775 vcpu->run->internal.data[1] = intr_info;
4776 return 0;
4777 }
4778
6aa8b732 4779 if (is_page_fault(intr_info)) {
1439442c 4780 /* EPT won't cause page fault directly */
cf3ace79 4781 BUG_ON(enable_ept);
6aa8b732 4782 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4783 trace_kvm_page_fault(cr2, error_code);
4784
3298b75c 4785 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4786 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4787 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4788 }
4789
d0bfb940 4790 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4791
4792 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4793 return handle_rmode_exception(vcpu, ex_no, error_code);
4794
42dbaa5a
JK		 4795 switch (ex_no) {
4796 case DB_VECTOR:
4797 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4798 if (!(vcpu->guest_debug &
4799 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4800 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4801 kvm_queue_exception(vcpu, DB_VECTOR);
4802 return 1;
4803 }
4804 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4805 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4806 /* fall through */
4807 case BP_VECTOR:
c573cd22
JK		 4808 /*
4809 * Update instruction length as we may reinject #BP from
4810 * user space while in guest debugging mode. Reading it for
4811 * #DB as well causes no harm, it is not used in that case.
4812 */
4813 vmx->vcpu.arch.event_exit_inst_len =
4814 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4815 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4816 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4817 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4818 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4819 break;
4820 default:
d0bfb940
JK		 4821 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4822 kvm_run->ex.exception = ex_no;
4823 kvm_run->ex.error_code = error_code;
42dbaa5a 4824 break;
6aa8b732 4825 }
6aa8b732
AK		 4826 return 0;
4827}
4828
851ba692 4829static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4830{
1165f5fe 4831 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4832 return 1;
4833}
4834
851ba692 4835static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4836{
851ba692 4837 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4838 return 0;
4839}
6aa8b732 4840
851ba692 4841static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4842{
bfdaab09 4843 unsigned long exit_qualification;
34c33d16 4844 int size, in, string;
039576c0 4845 unsigned port;
6aa8b732 4846
bfdaab09 4847 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4848 string = (exit_qualification & 16) != 0;
cf8f70bf 4849 in = (exit_qualification & 8) != 0;
e70669ab 4850
cf8f70bf 4851 ++vcpu->stat.io_exits;
e70669ab 4852
cf8f70bf 4853 if (string || in)
51d8b661 4854 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4855
cf8f70bf
GN		 4856 port = exit_qualification >> 16;
4857 size = (exit_qualification & 7) + 1;
e93f36bc 4858 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4859
4860 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4861}
4862
102d8325
IM		 4863static void
4864vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4865{
4866 /*
4867 * Patch in the VMCALL instruction:
4868 */
4869 hypercall[0] = 0x0f;
4870 hypercall[1] = 0x01;
4871 hypercall[2] = 0xc1;
102d8325
IM		 4872}
4873
0fa06071 4874/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4875static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4876{
eeadf9e7 4877 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4878 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4879 unsigned long orig_val = val;
4880
eeadf9e7
NHE		 4881 /*
4882 * We get here when L2 changed cr0 in a way that did not change
4883 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4884 * but did change L0 shadowed bits. So we first calculate the
4885 * effective cr0 value that L1 would like to write into the
4886 * hardware. It consists of the L2-owned bits from the new
4887 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4888 */
1a0d74e6
JK		 4889 val = (val & ~vmcs12->cr0_guest_host_mask) |
4890 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4891
4892 /* TODO: will have to take unrestricted guest mode into
4893 * account */
4894 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4895 return 1;
1a0d74e6
JK		 4896
4897 if (kvm_set_cr0(vcpu, val))
4898 return 1;
4899 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4900 return 0;
1a0d74e6
JK		 4901 } else {
4902 if (to_vmx(vcpu)->nested.vmxon &&
4903 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4904 return 1;
eeadf9e7 4905 return kvm_set_cr0(vcpu, val);
1a0d74e6 4906 }
eeadf9e7
NHE		 4907}
4908
4909static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4910{
4911 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4912 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4913 unsigned long orig_val = val;
4914
4915 /* analogously to handle_set_cr0 */
4916 val = (val & ~vmcs12->cr4_guest_host_mask) |
4917 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4918 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4919 return 1;
1a0d74e6 4920 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4921 return 0;
4922 } else
4923 return kvm_set_cr4(vcpu, val);
4924}
4925
4926/* called to set cr0 as approriate for clts instruction exit. */
4927static void handle_clts(struct kvm_vcpu *vcpu)
4928{
4929 if (is_guest_mode(vcpu)) {
4930 /*
4931 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4932 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4933 * just pretend it's off (also in arch.cr0 for fpu_activate).
4934 */
4935 vmcs_writel(CR0_READ_SHADOW,
4936 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4937 vcpu->arch.cr0 &= ~X86_CR0_TS;
4938 } else
4939 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4940}
4941
851ba692 4942static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4943{
229456fc 4944 unsigned long exit_qualification, val;
6aa8b732
AK		 4945 int cr;
4946 int reg;
49a9b07e 4947 int err;
6aa8b732 4948
bfdaab09 4949 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4950 cr = exit_qualification & 15;
4951 reg = (exit_qualification >> 8) & 15;
4952 switch ((exit_qualification >> 4) & 3) {
4953 case 0: /* mov to cr */
229456fc
MT		 4954 val = kvm_register_read(vcpu, reg);
4955 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4956 switch (cr) {
4957 case 0:
eeadf9e7 4958 err = handle_set_cr0(vcpu, val);
db8fcefa 4959 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4960 return 1;
4961 case 3:
2390218b 4962 err = kvm_set_cr3(vcpu, val);
db8fcefa 4963 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4964 return 1;
4965 case 4:
eeadf9e7 4966 err = handle_set_cr4(vcpu, val);
db8fcefa 4967 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4968 return 1;
0a5fff19
GN		 4969 case 8: {
4970 u8 cr8_prev = kvm_get_cr8(vcpu);
4971 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4972 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4973 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4974 if (irqchip_in_kernel(vcpu->kvm))
4975 return 1;
4976 if (cr8_prev <= cr8)
4977 return 1;
851ba692 4978 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4979 return 0;
4980 }
4b8073e4 4981 }
6aa8b732 4982 break;
25c4c276 4983 case 2: /* clts */
eeadf9e7 4984 handle_clts(vcpu);
4d4ec087 4985 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4986 skip_emulated_instruction(vcpu);
6b52d186 4987 vmx_fpu_activate(vcpu);
25c4c276 4988 return 1;
6aa8b732
AK		 4989 case 1: /*mov from cr*/
4990 switch (cr) {
4991 case 3:
9f8fe504
AK		 4992 val = kvm_read_cr3(vcpu);
4993 kvm_register_write(vcpu, reg, val);
4994 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4995 skip_emulated_instruction(vcpu);
4996 return 1;
4997 case 8:
229456fc
MT		 4998 val = kvm_get_cr8(vcpu);
4999 kvm_register_write(vcpu, reg, val);
5000 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5001 skip_emulated_instruction(vcpu);
5002 return 1;
5003 }
5004 break;
5005 case 3: /* lmsw */
a1f83a74 5006 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5007 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5008 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5009
5010 skip_emulated_instruction(vcpu);
5011 return 1;
5012 default:
5013 break;
5014 }
851ba692 5015 vcpu->run->exit_reason = 0;
a737f256 5016 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5017 (int)(exit_qualification >> 4) & 3, cr);
5018 return 0;
5019}
5020
851ba692 5021static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5022{
bfdaab09 5023 unsigned long exit_qualification;
6aa8b732
AK		 5024 int dr, reg;
5025
f2483415 5026 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5027 if (!kvm_require_cpl(vcpu, 0))
5028 return 1;
42dbaa5a
JK		 5029 dr = vmcs_readl(GUEST_DR7);
5030 if (dr & DR7_GD) {
5031 /*
5032 * As the vm-exit takes precedence over the debug trap, we
5033 * need to emulate the latter, either for the host or the
5034 * guest debugging itself.
5035 */
5036 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5037 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5038 vcpu->run->debug.arch.dr7 = dr;
5039 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5040 vmcs_readl(GUEST_CS_BASE) +
5041 vmcs_readl(GUEST_RIP);
851ba692
AK		 5042 vcpu->run->debug.arch.exception = DB_VECTOR;
5043 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5044 return 0;
5045 } else {
5046 vcpu->arch.dr7 &= ~DR7_GD;
5047 vcpu->arch.dr6 |= DR6_BD;
5048 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5049 kvm_queue_exception(vcpu, DB_VECTOR);
5050 return 1;
5051 }
5052 }
5053
bfdaab09 5054 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5055 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5056 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5057 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5058 unsigned long val;
5059 if (!kvm_get_dr(vcpu, dr, &val))
5060 kvm_register_write(vcpu, reg, val);
5061 } else
5062 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5063 skip_emulated_instruction(vcpu);
5064 return 1;
5065}
5066
020df079
GN		 5067static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5068{
5069 vmcs_writel(GUEST_DR7, val);
5070}
5071
851ba692 5072static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5073{
06465c5a
AK		 5074 kvm_emulate_cpuid(vcpu);
5075 return 1;
6aa8b732
AK		 5076}
5077
851ba692 5078static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5079{
ad312c7c 5080 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5081 u64 data;
5082
5083 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5084 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5085 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5086 return 1;
5087 }
5088
229456fc 5089 trace_kvm_msr_read(ecx, data);
2714d1d3 5090
6aa8b732 5091 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5092 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5093 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5094 skip_emulated_instruction(vcpu);
5095 return 1;
5096}
5097
851ba692 5098static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5099{
8fe8ab46 5100 struct msr_data msr;
ad312c7c
ZX		 5101 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5102 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5103 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5104
8fe8ab46
WA		 5105 msr.data = data;
5106 msr.index = ecx;
5107 msr.host_initiated = false;
5108 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5109 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5110 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5111 return 1;
5112 }
5113
59200273 5114 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5115 skip_emulated_instruction(vcpu);
5116 return 1;
5117}
5118
851ba692 5119static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5120{
3842d135 5121 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5122 return 1;
5123}
5124
851ba692 5125static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5126{
85f455f7
ED		 5127 u32 cpu_based_vm_exec_control;
5128
5129 /* clear pending irq */
5130 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5131 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5132 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5133
3842d135
AK		 5134 kvm_make_request(KVM_REQ_EVENT, vcpu);
5135
a26bf12a 5136 ++vcpu->stat.irq_window_exits;
2714d1d3 5137
c1150d8c
DL		 5138 /*
5139 * If the user space waits to inject interrupts, exit as soon as
5140 * possible
5141 */
8061823a 5142 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5143 vcpu->run->request_interrupt_window &&
8061823a 5144 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5145 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5146 return 0;
5147 }
6aa8b732
AK		 5148 return 1;
5149}
5150
851ba692 5151static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5152{
5153 skip_emulated_instruction(vcpu);
d3bef15f 5154 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5155}
5156
851ba692 5157static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5158{
510043da 5159 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5160 kvm_emulate_hypercall(vcpu);
5161 return 1;
c21415e8
IM		 5162}
5163
ec25d5e6
GN		 5164static int handle_invd(struct kvm_vcpu *vcpu)
5165{
51d8b661 5166 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5167}
5168
851ba692 5169static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5170{
f9c617f6 5171 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5172
5173 kvm_mmu_invlpg(vcpu, exit_qualification);
5174 skip_emulated_instruction(vcpu);
5175 return 1;
5176}
5177
fee84b07
AK		 5178static int handle_rdpmc(struct kvm_vcpu *vcpu)
5179{
5180 int err;
5181
5182 err = kvm_rdpmc(vcpu);
5183 kvm_complete_insn_gp(vcpu, err);
5184
5185 return 1;
5186}
5187
851ba692 5188static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5189{
5190 skip_emulated_instruction(vcpu);
f5f48ee1 5191 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5192 return 1;
5193}
5194
2acf923e
DC		 5195static int handle_xsetbv(struct kvm_vcpu *vcpu)
5196{
5197 u64 new_bv = kvm_read_edx_eax(vcpu);
5198 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5199
5200 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5201 skip_emulated_instruction(vcpu);
5202 return 1;
5203}
5204
851ba692 5205static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5206{
58fbbf26
KT		 5207 if (likely(fasteoi)) {
5208 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5209 int access_type, offset;
5210
5211 access_type = exit_qualification & APIC_ACCESS_TYPE;
5212 offset = exit_qualification & APIC_ACCESS_OFFSET;
5213 /*
5214 * Sane guest uses MOV to write EOI, with written value
5215 * not cared. So make a short-circuit here by avoiding
5216 * heavy instruction emulation.
5217 */
5218 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5219 (offset == APIC_EOI)) {
5220 kvm_lapic_set_eoi(vcpu);
5221 skip_emulated_instruction(vcpu);
5222 return 1;
5223 }
5224 }
51d8b661 5225 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5226}
5227
c7c9c56c
YZ		 5228static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5229{
5230 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5231 int vector = exit_qualification & 0xff;
5232
5233 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5234 kvm_apic_set_eoi_accelerated(vcpu, vector);
5235 return 1;
5236}
5237
83d4c286
YZ		 5238static int handle_apic_write(struct kvm_vcpu *vcpu)
5239{
5240 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5241 u32 offset = exit_qualification & 0xfff;
5242
5243 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5244 kvm_apic_write_nodecode(vcpu, offset);
5245 return 1;
5246}
5247
851ba692 5248static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5249{
60637aac 5250 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5251 unsigned long exit_qualification;
e269fb21
JK		 5252 bool has_error_code = false;
5253 u32 error_code = 0;
37817f29 5254 u16 tss_selector;
7f3d35fd 5255 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5256
5257 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5258 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5259 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5260
5261 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5262
5263 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5264 if (reason == TASK_SWITCH_GATE && idt_v) {
5265 switch (type) {
5266 case INTR_TYPE_NMI_INTR:
5267 vcpu->arch.nmi_injected = false;
654f06fc 5268 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5269 break;
5270 case INTR_TYPE_EXT_INTR:
66fd3f7f 5271 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5272 kvm_clear_interrupt_queue(vcpu);
5273 break;
5274 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5275 if (vmx->idt_vectoring_info &
5276 VECTORING_INFO_DELIVER_CODE_MASK) {
5277 has_error_code = true;
5278 error_code =
5279 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5280 }
5281 /* fall through */
64a7ec06
GN		 5282 case INTR_TYPE_SOFT_EXCEPTION:
5283 kvm_clear_exception_queue(vcpu);
5284 break;
5285 default:
5286 break;
5287 }
60637aac 5288 }
37817f29
IE		 5289 tss_selector = exit_qualification;
5290
64a7ec06
GN		 5291 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5292 type != INTR_TYPE_EXT_INTR &&
5293 type != INTR_TYPE_NMI_INTR))
5294 skip_emulated_instruction(vcpu);
5295
7f3d35fd
KW		 5296 if (kvm_task_switch(vcpu, tss_selector,
5297 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5298 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5299 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5300 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5301 vcpu->run->internal.ndata = 0;
42dbaa5a 5302 return 0;
acb54517 5303 }
42dbaa5a
JK		 5304
5305 /* clear all local breakpoint enable flags */
5306 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5307
5308 /*
5309 * TODO: What about debug traps on tss switch?
5310 * Are we supposed to inject them and update dr6?
5311 */
5312
5313 return 1;
37817f29
IE		 5314}
5315
851ba692 5316static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5317{
f9c617f6 5318 unsigned long exit_qualification;
1439442c 5319 gpa_t gpa;
4f5982a5 5320 u32 error_code;
1439442c 5321 int gla_validity;
1439442c 5322
f9c617f6 5323 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5324
1439442c
SY		 5325 gla_validity = (exit_qualification >> 7) & 0x3;
5326 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5327 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5328 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5329 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5330 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5331 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5332 (long unsigned int)exit_qualification);
851ba692
AK		 5333 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5334 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5335 return 0;
1439442c
SY		 5336 }
5337
5338 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5339 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5340
5341 /* It is a write fault? */
5342 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5343 /* It is a fetch fault? */
5344 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5345 /* ept page table is present? */
5346 error_code |= (exit_qualification >> 3) & 0x1;
5347
25d92081
YZ		 5348 vcpu->arch.exit_qualification = exit_qualification;
5349
4f5982a5 5350 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5351}
5352
68f89400
MT		 5353static u64 ept_rsvd_mask(u64 spte, int level)
5354{
5355 int i;
5356 u64 mask = 0;
5357
5358 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5359 mask |= (1ULL << i);
5360
5361 if (level > 2)
5362 /* bits 7:3 reserved */
5363 mask |= 0xf8;
5364 else if (level == 2) {
5365 if (spte & (1ULL << 7))
5366 /* 2MB ref, bits 20:12 reserved */
5367 mask |= 0x1ff000;
5368 else
5369 /* bits 6:3 reserved */
5370 mask |= 0x78;
5371 }
5372
5373 return mask;
5374}
5375
5376static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5377 int level)
5378{
5379 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5380
5381 /* 010b (write-only) */
5382 WARN_ON((spte & 0x7) == 0x2);
5383
5384 /* 110b (write/execute) */
5385 WARN_ON((spte & 0x7) == 0x6);
5386
5387 /* 100b (execute-only) and value not supported by logical processor */
5388 if (!cpu_has_vmx_ept_execute_only())
5389 WARN_ON((spte & 0x7) == 0x4);
5390
5391 /* not 000b */
5392 if ((spte & 0x7)) {
5393 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5394
5395 if (rsvd_bits != 0) {
5396 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5397 __func__, rsvd_bits);
5398 WARN_ON(1);
5399 }
5400
5401 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5402 u64 ept_mem_type = (spte & 0x38) >> 3;
5403
5404 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5405 ept_mem_type == 7) {
5406 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5407 __func__, ept_mem_type);
5408 WARN_ON(1);
5409 }
5410 }
5411 }
5412}
5413
851ba692 5414static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5415{
5416 u64 sptes[4];
ce88decf 5417 int nr_sptes, i, ret;
68f89400
MT		 5418 gpa_t gpa;
5419
5420 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5421
ce88decf 5422 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5423 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5424 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5425 EMULATE_DONE;
f8f55942
XG		 5426
5427 if (unlikely(ret == RET_MMIO_PF_INVALID))
5428 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5429
b37fbea6 5430 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5431 return 1;
5432
5433 /* It is the real ept misconfig */
68f89400
MT		 5434 printk(KERN_ERR "EPT: Misconfiguration.\n");
5435 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5436
5437 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5438
5439 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5440 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5441
851ba692
AK		 5442 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5443 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5444
5445 return 0;
5446}
5447
851ba692 5448static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5449{
5450 u32 cpu_based_vm_exec_control;
5451
5452 /* clear pending NMI */
5453 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5454 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5455 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5456 ++vcpu->stat.nmi_window_exits;
3842d135 5457 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5458
5459 return 1;
5460}
5461
80ced186 5462static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5463{
8b3079a5
AK		 5464 struct vcpu_vmx *vmx = to_vmx(vcpu);
5465 enum emulation_result err = EMULATE_DONE;
80ced186 5466 int ret = 1;
49e9d557
AK		 5467 u32 cpu_exec_ctrl;
5468 bool intr_window_requested;
b8405c18 5469 unsigned count = 130;
49e9d557
AK		 5470
5471 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5472 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5473
b8405c18 5474 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5475 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5476 return handle_interrupt_window(&vmx->vcpu);
5477
de87dcdd
AK		 5478 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5479 return 1;
5480
991eebf9 5481 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5482
ac0a48c3 5483 if (err == EMULATE_USER_EXIT) {
80ced186
MG		 5484 ret = 0;
5485 goto out;
5486 }
1d5a4d9b 5487
de5f70e0
AK		 5488 if (err != EMULATE_DONE) {
5489 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5490 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5491 vcpu->run->internal.ndata = 0;
6d77dbfc 5492 return 0;
de5f70e0 5493 }
ea953ef0 5494
8d76c49e
GN		 5495 if (vcpu->arch.halt_request) {
5496 vcpu->arch.halt_request = 0;
5497 ret = kvm_emulate_halt(vcpu);
5498 goto out;
5499 }
5500
ea953ef0 5501 if (signal_pending(current))
80ced186 5502 goto out;
ea953ef0
MG		 5503 if (need_resched())
5504 schedule();
5505 }
5506
14168786 5507 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5508out:
5509 return ret;
ea953ef0
MG		 5510}
5511
4b8d54f9
ZE		 5512/*
5513 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5514 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5515 */
9fb41ba8 5516static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5517{
5518 skip_emulated_instruction(vcpu);
5519 kvm_vcpu_on_spin(vcpu);
5520
5521 return 1;
5522}
5523
59708670
SY		 5524static int handle_invalid_op(struct kvm_vcpu *vcpu)
5525{
5526 kvm_queue_exception(vcpu, UD_VECTOR);
5527 return 1;
5528}
5529
ff2f6fe9
NHE		 5530/*
5531 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5532 * We could reuse a single VMCS for all the L2 guests, but we also want the
5533 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5534 * allows keeping them loaded on the processor, and in the future will allow
5535 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5536 * every entry if they never change.
5537 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5538 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5539 *
5540 * The following functions allocate and free a vmcs02 in this pool.
5541 */
5542
5543/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5544static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5545{
5546 struct vmcs02_list *item;
5547 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5548 if (item->vmptr == vmx->nested.current_vmptr) {
5549 list_move(&item->list, &vmx->nested.vmcs02_pool);
5550 return &item->vmcs02;
5551 }
5552
5553 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5554 /* Recycle the least recently used VMCS. */
5555 item = list_entry(vmx->nested.vmcs02_pool.prev,
5556 struct vmcs02_list, list);
5557 item->vmptr = vmx->nested.current_vmptr;
5558 list_move(&item->list, &vmx->nested.vmcs02_pool);
5559 return &item->vmcs02;
5560 }
5561
5562 /* Create a new VMCS */
0fa24ce3 5563 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5564 if (!item)
5565 return NULL;
5566 item->vmcs02.vmcs = alloc_vmcs();
5567 if (!item->vmcs02.vmcs) {
5568 kfree(item);
5569 return NULL;
5570 }
5571 loaded_vmcs_init(&item->vmcs02);
5572 item->vmptr = vmx->nested.current_vmptr;
5573 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5574 vmx->nested.vmcs02_num++;
5575 return &item->vmcs02;
5576}
5577
5578/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5579static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5580{
5581 struct vmcs02_list *item;
5582 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5583 if (item->vmptr == vmptr) {
5584 free_loaded_vmcs(&item->vmcs02);
5585 list_del(&item->list);
5586 kfree(item);
5587 vmx->nested.vmcs02_num--;
5588 return;
5589 }
5590}
5591
5592/*
5593 * Free all VMCSs saved for this vcpu, except the one pointed by
5594 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5595 * currently used, if running L2), and vmcs01 when running L2.
5596 */
5597static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5598{
5599 struct vmcs02_list *item, *n;
5600 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5601 if (vmx->loaded_vmcs != &item->vmcs02)
5602 free_loaded_vmcs(&item->vmcs02);
5603 list_del(&item->list);
5604 kfree(item);
5605 }
5606 vmx->nested.vmcs02_num = 0;
5607
5608 if (vmx->loaded_vmcs != &vmx->vmcs01)
5609 free_loaded_vmcs(&vmx->vmcs01);
5610}
5611
0658fbaa
ACL		 5612/*
5613 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5614 * set the success or error code of an emulated VMX instruction, as specified
5615 * by Vol 2B, VMX Instruction Reference, "Conventions".
5616 */
5617static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5618{
5619 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5620 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5621 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5622}
5623
5624static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5625{
5626 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5627 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5628 X86_EFLAGS_SF | X86_EFLAGS_OF))
5629 | X86_EFLAGS_CF);
5630}
5631
145c28dd 5632static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5633 u32 vm_instruction_error)
5634{
5635 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5636 /*
5637 * failValid writes the error number to the current VMCS, which
5638 * can't be done there isn't a current VMCS.
5639 */
5640 nested_vmx_failInvalid(vcpu);
5641 return;
5642 }
5643 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5644 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5645 X86_EFLAGS_SF | X86_EFLAGS_OF))
5646 | X86_EFLAGS_ZF);
5647 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5648 /*
5649 * We don't need to force a shadow sync because
5650 * VM_INSTRUCTION_ERROR is not shadowed
5651 */
5652}
145c28dd 5653
ec378aee
NHE		 5654/*
5655 * Emulate the VMXON instruction.
5656 * Currently, we just remember that VMX is active, and do not save or even
5657 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5658 * do not currently need to store anything in that guest-allocated memory
5659 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5660 * argument is different from the VMXON pointer (which the spec says they do).
5661 */
5662static int handle_vmon(struct kvm_vcpu *vcpu)
5663{
5664 struct kvm_segment cs;
5665 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5666 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5667 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5668 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5669
5670 /* The Intel VMX Instruction Reference lists a bunch of bits that
5671 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5672 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5673 * Otherwise, we should fail with #UD. We test these now:
5674 */
5675 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5676 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5677 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5678 kvm_queue_exception(vcpu, UD_VECTOR);
5679 return 1;
5680 }
5681
5682 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5683 if (is_long_mode(vcpu) && !cs.l) {
5684 kvm_queue_exception(vcpu, UD_VECTOR);
5685 return 1;
5686 }
5687
5688 if (vmx_get_cpl(vcpu)) {
5689 kvm_inject_gp(vcpu, 0);
5690 return 1;
5691 }
145c28dd
AG		 5692 if (vmx->nested.vmxon) {
5693 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5694 skip_emulated_instruction(vcpu);
5695 return 1;
5696 }
b3897a49
NHE		 5697
5698 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5699 != VMXON_NEEDED_FEATURES) {
5700 kvm_inject_gp(vcpu, 0);
5701 return 1;
5702 }
5703
8de48833
AG		 5704 if (enable_shadow_vmcs) {
5705 shadow_vmcs = alloc_vmcs();
5706 if (!shadow_vmcs)
5707 return -ENOMEM;
5708 /* mark vmcs as shadow */
5709 shadow_vmcs->revision_id |= (1u << 31);
5710 /* init shadow vmcs */
5711 vmcs_clear(shadow_vmcs);
5712 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5713 }
ec378aee 5714
ff2f6fe9
NHE		 5715 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5716 vmx->nested.vmcs02_num = 0;
5717
ec378aee
NHE		 5718 vmx->nested.vmxon = true;
5719
5720 skip_emulated_instruction(vcpu);
a25eb114 5721 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5722 return 1;
5723}
5724
5725/*
5726 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5727 * for running VMX instructions (except VMXON, whose prerequisites are
5728 * slightly different). It also specifies what exception to inject otherwise.
5729 */
5730static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5731{
5732 struct kvm_segment cs;
5733 struct vcpu_vmx *vmx = to_vmx(vcpu);
5734
5735 if (!vmx->nested.vmxon) {
5736 kvm_queue_exception(vcpu, UD_VECTOR);
5737 return 0;
5738 }
5739
5740 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5741 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5742 (is_long_mode(vcpu) && !cs.l)) {
5743 kvm_queue_exception(vcpu, UD_VECTOR);
5744 return 0;
5745 }
5746
5747 if (vmx_get_cpl(vcpu)) {
5748 kvm_inject_gp(vcpu, 0);
5749 return 0;
5750 }
5751
5752 return 1;
5753}
5754
e7953d7f
AG		 5755static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5756{
8a1b9dd0 5757 u32 exec_control;
012f83cb
AG		 5758 if (enable_shadow_vmcs) {
5759 if (vmx->nested.current_vmcs12 != NULL) {
5760 /* copy to memory all shadowed fields in case
5761 they were modified */
5762 copy_shadow_to_vmcs12(vmx);
5763 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5764 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5765 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5766 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5767 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5768 }
5769 }
e7953d7f
AG		 5770 kunmap(vmx->nested.current_vmcs12_page);
5771 nested_release_page(vmx->nested.current_vmcs12_page);
5772}
5773
ec378aee
NHE		 5774/*
5775 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5776 * just stops using VMX.
5777 */
5778static void free_nested(struct vcpu_vmx *vmx)
5779{
5780 if (!vmx->nested.vmxon)
5781 return;
5782 vmx->nested.vmxon = false;
a9d30f33 5783 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5784 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5785 vmx->nested.current_vmptr = -1ull;
5786 vmx->nested.current_vmcs12 = NULL;
5787 }
e7953d7f
AG		 5788 if (enable_shadow_vmcs)
5789 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5790 /* Unpin physical memory we referred to in current vmcs02 */
5791 if (vmx->nested.apic_access_page) {
5792 nested_release_page(vmx->nested.apic_access_page);
5793 vmx->nested.apic_access_page = 0;
5794 }
ff2f6fe9
NHE		 5795
5796 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5797}
5798
5799/* Emulate the VMXOFF instruction */
5800static int handle_vmoff(struct kvm_vcpu *vcpu)
5801{
5802 if (!nested_vmx_check_permission(vcpu))
5803 return 1;
5804 free_nested(to_vmx(vcpu));
5805 skip_emulated_instruction(vcpu);
a25eb114 5806 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5807 return 1;
5808}
5809
064aea77
NHE		 5810/*
5811 * Decode the memory-address operand of a vmx instruction, as recorded on an
5812 * exit caused by such an instruction (run by a guest hypervisor).
5813 * On success, returns 0. When the operand is invalid, returns 1 and throws
5814 * #UD or #GP.
5815 */
5816static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5817 unsigned long exit_qualification,
5818 u32 vmx_instruction_info, gva_t *ret)
5819{
5820 /*
5821 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5822 * Execution", on an exit, vmx_instruction_info holds most of the
5823 * addressing components of the operand. Only the displacement part
5824 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5825 * For how an actual address is calculated from all these components,
5826 * refer to Vol. 1, "Operand Addressing".
5827 */
5828 int scaling = vmx_instruction_info & 3;
5829 int addr_size = (vmx_instruction_info >> 7) & 7;
5830 bool is_reg = vmx_instruction_info & (1u << 10);
5831 int seg_reg = (vmx_instruction_info >> 15) & 7;
5832 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5833 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5834 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5835 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5836
5837 if (is_reg) {
5838 kvm_queue_exception(vcpu, UD_VECTOR);
5839 return 1;
5840 }
5841
5842 /* Addr = segment_base + offset */
5843 /* offset = base + [index * scale] + displacement */
5844 *ret = vmx_get_segment_base(vcpu, seg_reg);
5845 if (base_is_valid)
5846 *ret += kvm_register_read(vcpu, base_reg);
5847 if (index_is_valid)
5848 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5849 *ret += exit_qualification; /* holds the displacement */
5850
5851 if (addr_size == 1) /* 32 bit */
5852 *ret &= 0xffffffff;
5853
5854 /*
5855 * TODO: throw #GP (and return 1) in various cases that the VM*
5856 * instructions require it - e.g., offset beyond segment limit,
5857 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5858 * address, and so on. Currently these are not checked.
5859 */
5860 return 0;
5861}
5862
27d6c865
NHE		 5863/* Emulate the VMCLEAR instruction */
5864static int handle_vmclear(struct kvm_vcpu *vcpu)
5865{
5866 struct vcpu_vmx *vmx = to_vmx(vcpu);
5867 gva_t gva;
5868 gpa_t vmptr;
5869 struct vmcs12 *vmcs12;
5870 struct page *page;
5871 struct x86_exception e;
5872
5873 if (!nested_vmx_check_permission(vcpu))
5874 return 1;
5875
5876 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5877 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5878 return 1;
5879
5880 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5881 sizeof(vmptr), &e)) {
5882 kvm_inject_page_fault(vcpu, &e);
5883 return 1;
5884 }
5885
5886 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5887 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5888 skip_emulated_instruction(vcpu);
5889 return 1;
5890 }
5891
5892 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5893 nested_release_vmcs12(vmx);
27d6c865
NHE		 5894 vmx->nested.current_vmptr = -1ull;
5895 vmx->nested.current_vmcs12 = NULL;
5896 }
5897
5898 page = nested_get_page(vcpu, vmptr);
5899 if (page == NULL) {
5900 /*
5901 * For accurate processor emulation, VMCLEAR beyond available
5902 * physical memory should do nothing at all. However, it is
5903 * possible that a nested vmx bug, not a guest hypervisor bug,
5904 * resulted in this case, so let's shut down before doing any
5905 * more damage:
5906 */
5907 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5908 return 1;
5909 }
5910 vmcs12 = kmap(page);
5911 vmcs12->launch_state = 0;
5912 kunmap(page);
5913 nested_release_page(page);
5914
5915 nested_free_vmcs02(vmx, vmptr);
5916
5917 skip_emulated_instruction(vcpu);
5918 nested_vmx_succeed(vcpu);
5919 return 1;
5920}
5921
cd232ad0
NHE		 5922static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5923
5924/* Emulate the VMLAUNCH instruction */
5925static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5926{
5927 return nested_vmx_run(vcpu, true);
5928}
5929
5930/* Emulate the VMRESUME instruction */
5931static int handle_vmresume(struct kvm_vcpu *vcpu)
5932{
5933
5934 return nested_vmx_run(vcpu, false);
5935}
5936
49f705c5
NHE		 5937enum vmcs_field_type {
5938 VMCS_FIELD_TYPE_U16 = 0,
5939 VMCS_FIELD_TYPE_U64 = 1,
5940 VMCS_FIELD_TYPE_U32 = 2,
5941 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5942};
5943
5944static inline int vmcs_field_type(unsigned long field)
5945{
5946 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5947 return VMCS_FIELD_TYPE_U32;
5948 return (field >> 13) & 0x3 ;
5949}
5950
5951static inline int vmcs_field_readonly(unsigned long field)
5952{
5953 return (((field >> 10) & 0x3) == 1);
5954}
5955
5956/*
5957 * Read a vmcs12 field. Since these can have varying lengths and we return
5958 * one type, we chose the biggest type (u64) and zero-extend the return value
5959 * to that size. Note that the caller, handle_vmread, might need to use only
5960 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5961 * 64-bit fields are to be returned).
5962 */
5963static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5964 unsigned long field, u64 *ret)
5965{
5966 short offset = vmcs_field_to_offset(field);
5967 char *p;
5968
5969 if (offset < 0)
5970 return 0;
5971
5972 p = ((char *)(get_vmcs12(vcpu))) + offset;
5973
5974 switch (vmcs_field_type(field)) {
5975 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5976 *ret = *((natural_width *)p);
5977 return 1;
5978 case VMCS_FIELD_TYPE_U16:
5979 *ret = *((u16 *)p);
5980 return 1;
5981 case VMCS_FIELD_TYPE_U32:
5982 *ret = *((u32 *)p);
5983 return 1;
5984 case VMCS_FIELD_TYPE_U64:
5985 *ret = *((u64 *)p);
5986 return 1;
5987 default:
5988 return 0; /* can never happen. */
5989 }
5990}
5991
20b97fea
AG		 5992
5993static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5994 unsigned long field, u64 field_value){
5995 short offset = vmcs_field_to_offset(field);
5996 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5997 if (offset < 0)
5998 return false;
5999
6000 switch (vmcs_field_type(field)) {
6001 case VMCS_FIELD_TYPE_U16:
6002 *(u16 *)p = field_value;
6003 return true;
6004 case VMCS_FIELD_TYPE_U32:
6005 *(u32 *)p = field_value;
6006 return true;
6007 case VMCS_FIELD_TYPE_U64:
6008 *(u64 *)p = field_value;
6009 return true;
6010 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6011 *(natural_width *)p = field_value;
6012 return true;
6013 default:
6014 return false; /* can never happen. */
6015 }
6016
6017}
6018
16f5b903
AG		 6019static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6020{
6021 int i;
6022 unsigned long field;
6023 u64 field_value;
6024 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6025 const unsigned long *fields = shadow_read_write_fields;
6026 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6027
6028 vmcs_load(shadow_vmcs);
6029
6030 for (i = 0; i < num_fields; i++) {
6031 field = fields[i];
6032 switch (vmcs_field_type(field)) {
6033 case VMCS_FIELD_TYPE_U16:
6034 field_value = vmcs_read16(field);
6035 break;
6036 case VMCS_FIELD_TYPE_U32:
6037 field_value = vmcs_read32(field);
6038 break;
6039 case VMCS_FIELD_TYPE_U64:
6040 field_value = vmcs_read64(field);
6041 break;
6042 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6043 field_value = vmcs_readl(field);
6044 break;
6045 }
6046 vmcs12_write_any(&vmx->vcpu, field, field_value);
6047 }
6048
6049 vmcs_clear(shadow_vmcs);
6050 vmcs_load(vmx->loaded_vmcs->vmcs);
6051}
6052
c3114420
AG		 6053static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6054{
c2bae893
MK		 6055 const unsigned long *fields[] = {
6056 shadow_read_write_fields,
6057 shadow_read_only_fields
c3114420 6058 };
c2bae893 6059 const int max_fields[] = {
c3114420
AG		 6060 max_shadow_read_write_fields,
6061 max_shadow_read_only_fields
6062 };
6063 int i, q;
6064 unsigned long field;
6065 u64 field_value = 0;
6066 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6067
6068 vmcs_load(shadow_vmcs);
6069
c2bae893 6070 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6071 for (i = 0; i < max_fields[q]; i++) {
6072 field = fields[q][i];
6073 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6074
6075 switch (vmcs_field_type(field)) {
6076 case VMCS_FIELD_TYPE_U16:
6077 vmcs_write16(field, (u16)field_value);
6078 break;
6079 case VMCS_FIELD_TYPE_U32:
6080 vmcs_write32(field, (u32)field_value);
6081 break;
6082 case VMCS_FIELD_TYPE_U64:
6083 vmcs_write64(field, (u64)field_value);
6084 break;
6085 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6086 vmcs_writel(field, (long)field_value);
6087 break;
6088 }
6089 }
6090 }
6091
6092 vmcs_clear(shadow_vmcs);
6093 vmcs_load(vmx->loaded_vmcs->vmcs);
6094}
6095
49f705c5
NHE		 6096/*
6097 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6098 * used before) all generate the same failure when it is missing.
6099 */
6100static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6101{
6102 struct vcpu_vmx *vmx = to_vmx(vcpu);
6103 if (vmx->nested.current_vmptr == -1ull) {
6104 nested_vmx_failInvalid(vcpu);
6105 skip_emulated_instruction(vcpu);
6106 return 0;
6107 }
6108 return 1;
6109}
6110
6111static int handle_vmread(struct kvm_vcpu *vcpu)
6112{
6113 unsigned long field;
6114 u64 field_value;
6115 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6116 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6117 gva_t gva = 0;
6118
6119 if (!nested_vmx_check_permission(vcpu) ||
6120 !nested_vmx_check_vmcs12(vcpu))
6121 return 1;
6122
6123 /* Decode instruction info and find the field to read */
6124 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6125 /* Read the field, zero-extended to a u64 field_value */
6126 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6127 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6128 skip_emulated_instruction(vcpu);
6129 return 1;
6130 }
6131 /*
6132 * Now copy part of this value to register or memory, as requested.
6133 * Note that the number of bits actually copied is 32 or 64 depending
6134 * on the guest's mode (32 or 64 bit), not on the given field's length.
6135 */
6136 if (vmx_instruction_info & (1u << 10)) {
6137 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6138 field_value);
6139 } else {
6140 if (get_vmx_mem_address(vcpu, exit_qualification,
6141 vmx_instruction_info, &gva))
6142 return 1;
6143 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6144 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6145 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6146 }
6147
6148 nested_vmx_succeed(vcpu);
6149 skip_emulated_instruction(vcpu);
6150 return 1;
6151}
6152
6153
6154static int handle_vmwrite(struct kvm_vcpu *vcpu)
6155{
6156 unsigned long field;
6157 gva_t gva;
6158 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6159 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6160 /* The value to write might be 32 or 64 bits, depending on L1's long
6161 * mode, and eventually we need to write that into a field of several
6162 * possible lengths. The code below first zero-extends the value to 64
6163 * bit (field_value), and then copies only the approriate number of
6164 * bits into the vmcs12 field.
6165 */
6166 u64 field_value = 0;
6167 struct x86_exception e;
6168
6169 if (!nested_vmx_check_permission(vcpu) ||
6170 !nested_vmx_check_vmcs12(vcpu))
6171 return 1;
6172
6173 if (vmx_instruction_info & (1u << 10))
6174 field_value = kvm_register_read(vcpu,
6175 (((vmx_instruction_info) >> 3) & 0xf));
6176 else {
6177 if (get_vmx_mem_address(vcpu, exit_qualification,
6178 vmx_instruction_info, &gva))
6179 return 1;
6180 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6181 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6182 kvm_inject_page_fault(vcpu, &e);
6183 return 1;
6184 }
6185 }
6186
6187
6188 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6189 if (vmcs_field_readonly(field)) {
6190 nested_vmx_failValid(vcpu,
6191 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6192 skip_emulated_instruction(vcpu);
6193 return 1;
6194 }
6195
20b97fea 6196 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6197 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6198 skip_emulated_instruction(vcpu);
6199 return 1;
6200 }
6201
6202 nested_vmx_succeed(vcpu);
6203 skip_emulated_instruction(vcpu);
6204 return 1;
6205}
6206
63846663
NHE		 6207/* Emulate the VMPTRLD instruction */
6208static int handle_vmptrld(struct kvm_vcpu *vcpu)
6209{
6210 struct vcpu_vmx *vmx = to_vmx(vcpu);
6211 gva_t gva;
6212 gpa_t vmptr;
6213 struct x86_exception e;
8a1b9dd0 6214 u32 exec_control;
63846663
NHE		 6215
6216 if (!nested_vmx_check_permission(vcpu))
6217 return 1;
6218
6219 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6220 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6221 return 1;
6222
6223 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6224 sizeof(vmptr), &e)) {
6225 kvm_inject_page_fault(vcpu, &e);
6226 return 1;
6227 }
6228
6229 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6230 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6231 skip_emulated_instruction(vcpu);
6232 return 1;
6233 }
6234
6235 if (vmx->nested.current_vmptr != vmptr) {
6236 struct vmcs12 *new_vmcs12;
6237 struct page *page;
6238 page = nested_get_page(vcpu, vmptr);
6239 if (page == NULL) {
6240 nested_vmx_failInvalid(vcpu);
6241 skip_emulated_instruction(vcpu);
6242 return 1;
6243 }
6244 new_vmcs12 = kmap(page);
6245 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6246 kunmap(page);
6247 nested_release_page_clean(page);
6248 nested_vmx_failValid(vcpu,
6249 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6250 skip_emulated_instruction(vcpu);
6251 return 1;
6252 }
e7953d7f
AG		 6253 if (vmx->nested.current_vmptr != -1ull)
6254 nested_release_vmcs12(vmx);
63846663
NHE		 6255
6256 vmx->nested.current_vmptr = vmptr;
6257 vmx->nested.current_vmcs12 = new_vmcs12;
6258 vmx->nested.current_vmcs12_page = page;
012f83cb 6259 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6260 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6261 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6262 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6263 vmcs_write64(VMCS_LINK_POINTER,
6264 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6265 vmx->nested.sync_shadow_vmcs = true;
6266 }
63846663
NHE		 6267 }
6268
6269 nested_vmx_succeed(vcpu);
6270 skip_emulated_instruction(vcpu);
6271 return 1;
6272}
6273
6a4d7550
NHE		 6274/* Emulate the VMPTRST instruction */
6275static int handle_vmptrst(struct kvm_vcpu *vcpu)
6276{
6277 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6278 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6279 gva_t vmcs_gva;
6280 struct x86_exception e;
6281
6282 if (!nested_vmx_check_permission(vcpu))
6283 return 1;
6284
6285 if (get_vmx_mem_address(vcpu, exit_qualification,
6286 vmx_instruction_info, &vmcs_gva))
6287 return 1;
6288 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6289 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6290 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6291 sizeof(u64), &e)) {
6292 kvm_inject_page_fault(vcpu, &e);
6293 return 1;
6294 }
6295 nested_vmx_succeed(vcpu);
6296 skip_emulated_instruction(vcpu);
6297 return 1;
6298}
6299
bfd0a56b
NHE		 6300/* Emulate the INVEPT instruction */
6301static int handle_invept(struct kvm_vcpu *vcpu)
6302{
6303 u32 vmx_instruction_info, types;
6304 unsigned long type;
6305 gva_t gva;
6306 struct x86_exception e;
6307 struct {
6308 u64 eptp, gpa;
6309 } operand;
6310 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6311
6312 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6313 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6314 kvm_queue_exception(vcpu, UD_VECTOR);
6315 return 1;
6316 }
6317
6318 if (!nested_vmx_check_permission(vcpu))
6319 return 1;
6320
6321 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6322 kvm_queue_exception(vcpu, UD_VECTOR);
6323 return 1;
6324 }
6325
6326 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6327 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6328
6329 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6330
6331 if (!(types & (1UL << type))) {
6332 nested_vmx_failValid(vcpu,
6333 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6334 return 1;
6335 }
6336
6337 /* According to the Intel VMX instruction reference, the memory
6338 * operand is read even if it isn't needed (e.g., for type==global)
6339 */
6340 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6341 vmx_instruction_info, &gva))
6342 return 1;
6343 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6344 sizeof(operand), &e)) {
6345 kvm_inject_page_fault(vcpu, &e);
6346 return 1;
6347 }
6348
6349 switch (type) {
6350 case VMX_EPT_EXTENT_CONTEXT:
6351 if ((operand.eptp & eptp_mask) !=
6352 (nested_ept_get_cr3(vcpu) & eptp_mask))
6353 break;
6354 case VMX_EPT_EXTENT_GLOBAL:
6355 kvm_mmu_sync_roots(vcpu);
6356 kvm_mmu_flush_tlb(vcpu);
6357 nested_vmx_succeed(vcpu);
6358 break;
6359 default:
6360 BUG_ON(1);
6361 break;
6362 }
6363
6364 skip_emulated_instruction(vcpu);
6365 return 1;
6366}
6367
6aa8b732
AK		 6368/*
6369 * The exit handlers return 1 if the exit was handled fully and guest execution
6370 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6371 * to be done to userspace and return 0.
6372 */
772e0318 6373static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6374 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6375 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6376 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6377 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6378 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6379 [EXIT_REASON_CR_ACCESS] = handle_cr,
6380 [EXIT_REASON_DR_ACCESS] = handle_dr,
6381 [EXIT_REASON_CPUID] = handle_cpuid,
6382 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6383 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6384 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6385 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6386 [EXIT_REASON_INVD] = handle_invd,
a7052897 6387 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6388 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6389 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6390 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6391 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6392 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6393 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6394 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6395 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6396 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6397 [EXIT_REASON_VMOFF] = handle_vmoff,
6398 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6399 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6400 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6401 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6402 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6403 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6404 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6405 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6406 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6407 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6408 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6409 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6410 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6411 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6412 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6413};
6414
6415static const int kvm_vmx_max_exit_handlers =
50a3485c 6416 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6417
908a7bdd
JK		 6418static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6419 struct vmcs12 *vmcs12)
6420{
6421 unsigned long exit_qualification;
6422 gpa_t bitmap, last_bitmap;
6423 unsigned int port;
6424 int size;
6425 u8 b;
6426
6427 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6428 return 1;
6429
6430 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6431 return 0;
6432
6433 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6434
6435 port = exit_qualification >> 16;
6436 size = (exit_qualification & 7) + 1;
6437
6438 last_bitmap = (gpa_t)-1;
6439 b = -1;
6440
6441 while (size > 0) {
6442 if (port < 0x8000)
6443 bitmap = vmcs12->io_bitmap_a;
6444 else if (port < 0x10000)
6445 bitmap = vmcs12->io_bitmap_b;
6446 else
6447 return 1;
6448 bitmap += (port & 0x7fff) / 8;
6449
6450 if (last_bitmap != bitmap)
6451 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6452 return 1;
6453 if (b & (1 << (port & 7)))
6454 return 1;
6455
6456 port++;
6457 size--;
6458 last_bitmap = bitmap;
6459 }
6460
6461 return 0;
6462}
6463
644d711a
NHE		 6464/*
6465 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6466 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6467 * disinterest in the current event (read or write a specific MSR) by using an
6468 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6469 */
6470static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6471 struct vmcs12 *vmcs12, u32 exit_reason)
6472{
6473 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6474 gpa_t bitmap;
6475
cbd29cb6 6476 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6477 return 1;
6478
6479 /*
6480 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6481 * for the four combinations of read/write and low/high MSR numbers.
6482 * First we need to figure out which of the four to use:
6483 */
6484 bitmap = vmcs12->msr_bitmap;
6485 if (exit_reason == EXIT_REASON_MSR_WRITE)
6486 bitmap += 2048;
6487 if (msr_index >= 0xc0000000) {
6488 msr_index -= 0xc0000000;
6489 bitmap += 1024;
6490 }
6491
6492 /* Then read the msr_index'th bit from this bitmap: */
6493 if (msr_index < 1024*8) {
6494 unsigned char b;
bd31a7f5
JK		 6495 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6496 return 1;
644d711a
NHE		 6497 return 1 & (b >> (msr_index & 7));
6498 } else
6499 return 1; /* let L1 handle the wrong parameter */
6500}
6501
6502/*
6503 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6504 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6505 * intercept (via guest_host_mask etc.) the current event.
6506 */
6507static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6508 struct vmcs12 *vmcs12)
6509{
6510 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6511 int cr = exit_qualification & 15;
6512 int reg = (exit_qualification >> 8) & 15;
6513 unsigned long val = kvm_register_read(vcpu, reg);
6514
6515 switch ((exit_qualification >> 4) & 3) {
6516 case 0: /* mov to cr */
6517 switch (cr) {
6518 case 0:
6519 if (vmcs12->cr0_guest_host_mask &
6520 (val ^ vmcs12->cr0_read_shadow))
6521 return 1;
6522 break;
6523 case 3:
6524 if ((vmcs12->cr3_target_count >= 1 &&
6525 vmcs12->cr3_target_value0 == val) ||
6526 (vmcs12->cr3_target_count >= 2 &&
6527 vmcs12->cr3_target_value1 == val) ||
6528 (vmcs12->cr3_target_count >= 3 &&
6529 vmcs12->cr3_target_value2 == val) ||
6530 (vmcs12->cr3_target_count >= 4 &&
6531 vmcs12->cr3_target_value3 == val))
6532 return 0;
6533 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6534 return 1;
6535 break;
6536 case 4:
6537 if (vmcs12->cr4_guest_host_mask &
6538 (vmcs12->cr4_read_shadow ^ val))
6539 return 1;
6540 break;
6541 case 8:
6542 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6543 return 1;
6544 break;
6545 }
6546 break;
6547 case 2: /* clts */
6548 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6549 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6550 return 1;
6551 break;
6552 case 1: /* mov from cr */
6553 switch (cr) {
6554 case 3:
6555 if (vmcs12->cpu_based_vm_exec_control &
6556 CPU_BASED_CR3_STORE_EXITING)
6557 return 1;
6558 break;
6559 case 8:
6560 if (vmcs12->cpu_based_vm_exec_control &
6561 CPU_BASED_CR8_STORE_EXITING)
6562 return 1;
6563 break;
6564 }
6565 break;
6566 case 3: /* lmsw */
6567 /*
6568 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6569 * cr0. Other attempted changes are ignored, with no exit.
6570 */
6571 if (vmcs12->cr0_guest_host_mask & 0xe &
6572 (val ^ vmcs12->cr0_read_shadow))
6573 return 1;
6574 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6575 !(vmcs12->cr0_read_shadow & 0x1) &&
6576 (val & 0x1))
6577 return 1;
6578 break;
6579 }
6580 return 0;
6581}
6582
6583/*
6584 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6585 * should handle it ourselves in L0 (and then continue L2). Only call this
6586 * when in is_guest_mode (L2).
6587 */
6588static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6589{
644d711a
NHE		 6590 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6591 struct vcpu_vmx *vmx = to_vmx(vcpu);
6592 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6593 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6594
6595 if (vmx->nested.nested_run_pending)
6596 return 0;
6597
6598 if (unlikely(vmx->fail)) {
bd80158a
JK		 6599 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6600 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6601 return 1;
6602 }
6603
6604 switch (exit_reason) {
6605 case EXIT_REASON_EXCEPTION_NMI:
6606 if (!is_exception(intr_info))
6607 return 0;
6608 else if (is_page_fault(intr_info))
6609 return enable_ept;
6610 return vmcs12->exception_bitmap &
6611 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6612 case EXIT_REASON_EXTERNAL_INTERRUPT:
6613 return 0;
6614 case EXIT_REASON_TRIPLE_FAULT:
6615 return 1;
6616 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6617 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6618 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6619 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6620 case EXIT_REASON_TASK_SWITCH:
6621 return 1;
6622 case EXIT_REASON_CPUID:
6623 return 1;
6624 case EXIT_REASON_HLT:
6625 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6626 case EXIT_REASON_INVD:
6627 return 1;
6628 case EXIT_REASON_INVLPG:
6629 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6630 case EXIT_REASON_RDPMC:
6631 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6632 case EXIT_REASON_RDTSC:
6633 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6634 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6635 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6636 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6637 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6638 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6639 case EXIT_REASON_INVEPT:
644d711a
NHE		 6640 /*
6641 * VMX instructions trap unconditionally. This allows L1 to
6642 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6643 */
6644 return 1;
6645 case EXIT_REASON_CR_ACCESS:
6646 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6647 case EXIT_REASON_DR_ACCESS:
6648 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6649 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6650 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6651 case EXIT_REASON_MSR_READ:
6652 case EXIT_REASON_MSR_WRITE:
6653 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6654 case EXIT_REASON_INVALID_STATE:
6655 return 1;
6656 case EXIT_REASON_MWAIT_INSTRUCTION:
6657 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6658 case EXIT_REASON_MONITOR_INSTRUCTION:
6659 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6660 case EXIT_REASON_PAUSE_INSTRUCTION:
6661 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6662 nested_cpu_has2(vmcs12,
6663 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6664 case EXIT_REASON_MCE_DURING_VMENTRY:
6665 return 0;
6666 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6667 return 1;
6668 case EXIT_REASON_APIC_ACCESS:
6669 return nested_cpu_has2(vmcs12,
6670 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6671 case EXIT_REASON_EPT_VIOLATION:
6672 case EXIT_REASON_EPT_MISCONFIG:
6673 return 0;
0238ea91
JK		 6674 case EXIT_REASON_PREEMPTION_TIMER:
6675 return vmcs12->pin_based_vm_exec_control &
6676 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6677 case EXIT_REASON_WBINVD:
6678 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6679 case EXIT_REASON_XSETBV:
6680 return 1;
6681 default:
6682 return 1;
6683 }
6684}
6685
586f9607
AK		 6686static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6687{
6688 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6689 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6690}
6691
6aa8b732
AK		 6692/*
6693 * The guest has exited. See if we can fix it or if we need userspace
6694 * assistance.
6695 */
851ba692 6696static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6697{
29bd8a78 6698 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6699 u32 exit_reason = vmx->exit_reason;
1155f76a 6700 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6701
80ced186 6702 /* If guest state is invalid, start emulating */
14168786 6703 if (vmx->emulation_required)
80ced186 6704 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6705
b6f1250e
NHE		 6706 /*
6707 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6708 * we did not inject a still-pending event to L1 now because of
6709 * nested_run_pending, we need to re-enable this bit.
6710 */
6711 if (vmx->nested.nested_run_pending)
6712 kvm_make_request(KVM_REQ_EVENT, vcpu);
6713
509c75ea
NHE		 6714 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6715 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6716 vmx->nested.nested_run_pending = 1;
6717 else
6718 vmx->nested.nested_run_pending = 0;
6719
6720 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6721 nested_vmx_vmexit(vcpu);
6722 return 1;
6723 }
6724
5120702e
MG		 6725 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6726 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6727 vcpu->run->fail_entry.hardware_entry_failure_reason
6728 = exit_reason;
6729 return 0;
6730 }
6731
29bd8a78 6732 if (unlikely(vmx->fail)) {
851ba692
AK		 6733 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6734 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6735 = vmcs_read32(VM_INSTRUCTION_ERROR);
6736 return 0;
6737 }
6aa8b732 6738
b9bf6882
XG		 6739 /*
6740 * Note:
6741 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6742 * delivery event since it indicates guest is accessing MMIO.
6743 * The vm-exit can be triggered again after return to guest that
6744 * will cause infinite loop.
6745 */
d77c26fc 6746 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6747 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6748 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6749 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6750 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6751 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6752 vcpu->run->internal.ndata = 2;
6753 vcpu->run->internal.data[0] = vectoring_info;
6754 vcpu->run->internal.data[1] = exit_reason;
6755 return 0;
6756 }
3b86cd99 6757
644d711a
NHE		 6758 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6759 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6760 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6761 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6762 vmx->soft_vnmi_blocked = 0;
3b86cd99 6763 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6764 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6765 /*
6766 * This CPU don't support us in finding the end of an
6767 * NMI-blocked window if the guest runs with IRQs
6768 * disabled. So we pull the trigger after 1 s of
6769 * futile waiting, but inform the user about this.
6770 */
6771 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6772 "state on VCPU %d after 1 s timeout\n",
6773 __func__, vcpu->vcpu_id);
6774 vmx->soft_vnmi_blocked = 0;
3b86cd99 6775 }
3b86cd99
JK		 6776 }
6777
6aa8b732
AK		 6778 if (exit_reason < kvm_vmx_max_exit_handlers
6779 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6780 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6781 else {
851ba692
AK		 6782 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6783 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6784 }
6785 return 0;
6786}
6787
95ba8273 6788static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6789{
95ba8273 6790 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6791 vmcs_write32(TPR_THRESHOLD, 0);
6792 return;
6793 }
6794
95ba8273 6795 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6796}
6797
8d14695f
YZ		 6798static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6799{
6800 u32 sec_exec_control;
6801
6802 /*
6803 * There is not point to enable virtualize x2apic without enable
6804 * apicv
6805 */
c7c9c56c
YZ		 6806 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6807 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6808 return;
6809
6810 if (!vm_need_tpr_shadow(vcpu->kvm))
6811 return;
6812
6813 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6814
6815 if (set) {
6816 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6817 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6818 } else {
6819 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6820 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6821 }
6822 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6823
6824 vmx_set_msr_bitmap(vcpu);
6825}
6826
c7c9c56c
YZ		 6827static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6828{
6829 u16 status;
6830 u8 old;
6831
6832 if (!vmx_vm_has_apicv(kvm))
6833 return;
6834
6835 if (isr == -1)
6836 isr = 0;
6837
6838 status = vmcs_read16(GUEST_INTR_STATUS);
6839 old = status >> 8;
6840 if (isr != old) {
6841 status &= 0xff;
6842 status |= isr << 8;
6843 vmcs_write16(GUEST_INTR_STATUS, status);
6844 }
6845}
6846
6847static void vmx_set_rvi(int vector)
6848{
6849 u16 status;
6850 u8 old;
6851
6852 status = vmcs_read16(GUEST_INTR_STATUS);
6853 old = (u8)status & 0xff;
6854 if ((u8)vector != old) {
6855 status &= ~0xff;
6856 status |= (u8)vector;
6857 vmcs_write16(GUEST_INTR_STATUS, status);
6858 }
6859}
6860
6861static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6862{
6863 if (max_irr == -1)
6864 return;
6865
6866 vmx_set_rvi(max_irr);
6867}
6868
6869static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6870{
3d81bc7e
YZ		 6871 if (!vmx_vm_has_apicv(vcpu->kvm))
6872 return;
6873
c7c9c56c
YZ		 6874 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6875 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6876 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6877 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6878}
6879
51aa01d1 6880static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6881{
00eba012
AK		 6882 u32 exit_intr_info;
6883
6884 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6885 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6886 return;
6887
c5ca8e57 6888 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6889 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6890
6891 /* Handle machine checks before interrupts are enabled */
00eba012 6892 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6893 kvm_machine_check();
6894
20f65983 6895 /* We need to handle NMIs before interrupts are enabled */
00eba012 6896 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6897 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6898 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6899 asm("int $2");
ff9d07a0
ZY		 6900 kvm_after_handle_nmi(&vmx->vcpu);
6901 }
51aa01d1 6902}
20f65983 6903
a547c6db
YZ		 6904static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6905{
6906 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6907
6908 /*
6909 * If external interrupt exists, IF bit is set in rflags/eflags on the
6910 * interrupt stack frame, and interrupt will be enabled on a return
6911 * from interrupt handler.
6912 */
6913 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6914 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6915 unsigned int vector;
6916 unsigned long entry;
6917 gate_desc *desc;
6918 struct vcpu_vmx *vmx = to_vmx(vcpu);
6919#ifdef CONFIG_X86_64
6920 unsigned long tmp;
6921#endif
6922
6923 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6924 desc = (gate_desc *)vmx->host_idt_base + vector;
6925 entry = gate_offset(*desc);
6926 asm volatile(
6927#ifdef CONFIG_X86_64
6928 "mov %%" _ASM_SP ", %[sp]\n\t"
6929 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6930 "push $%c[ss]\n\t"
6931 "push %[sp]\n\t"
6932#endif
6933 "pushf\n\t"
6934 "orl $0x200, (%%" _ASM_SP ")\n\t"
6935 __ASM_SIZE(push) " $%c[cs]\n\t"
6936 "call *%[entry]\n\t"
6937 :
6938#ifdef CONFIG_X86_64
6939 [sp]"=&r"(tmp)
6940#endif
6941 :
6942 [entry]"r"(entry),
6943 [ss]"i"(__KERNEL_DS),
6944 [cs]"i"(__KERNEL_CS)
6945 );
6946 } else
6947 local_irq_enable();
6948}
6949
51aa01d1
AK		 6950static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6951{
c5ca8e57 6952 u32 exit_intr_info;
51aa01d1
AK		 6953 bool unblock_nmi;
6954 u8 vector;
6955 bool idtv_info_valid;
6956
6957 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6958
cf393f75 6959 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6960 if (vmx->nmi_known_unmasked)
6961 return;
c5ca8e57
AK		 6962 /*
6963 * Can't use vmx->exit_intr_info since we're not sure what
6964 * the exit reason is.
6965 */
6966 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6967 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6968 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6969 /*
7b4a25cb 6970 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6971 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6972 * a guest IRET fault.
7b4a25cb
GN		 6973 * SDM 3: 23.2.2 (September 2008)
6974 * Bit 12 is undefined in any of the following cases:
6975 * If the VM exit sets the valid bit in the IDT-vectoring
6976 * information field.
6977 * If the VM exit is due to a double fault.
cf393f75 6978 */
7b4a25cb
GN		 6979 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6980 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6981 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6982 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6983 else
6984 vmx->nmi_known_unmasked =
6985 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6986 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6987 } else if (unlikely(vmx->soft_vnmi_blocked))
6988 vmx->vnmi_blocked_time +=
6989 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6990}
6991
3ab66e8a 6992static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6993 u32 idt_vectoring_info,
6994 int instr_len_field,
6995 int error_code_field)
51aa01d1 6996{
51aa01d1
AK		 6997 u8 vector;
6998 int type;
6999 bool idtv_info_valid;
7000
7001 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7002
3ab66e8a
JK		 7003 vcpu->arch.nmi_injected = false;
7004 kvm_clear_exception_queue(vcpu);
7005 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7006
7007 if (!idtv_info_valid)
7008 return;
7009
3ab66e8a 7010 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7011
668f612f
AK		 7012 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7013 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7014
64a7ec06 7015 switch (type) {
37b96e98 7016 case INTR_TYPE_NMI_INTR:
3ab66e8a 7017 vcpu->arch.nmi_injected = true;
668f612f 7018 /*
7b4a25cb 7019 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7020 * Clear bit "block by NMI" before VM entry if a NMI
7021 * delivery faulted.
668f612f 7022 */
3ab66e8a 7023 vmx_set_nmi_mask(vcpu, false);
37b96e98 7024 break;
37b96e98 7025 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7026 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7027 /* fall through */
7028 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7029 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7030 u32 err = vmcs_read32(error_code_field);
3ab66e8a 7031 kvm_queue_exception_e(vcpu, vector, err);
35920a35 7032 } else
3ab66e8a 7033 kvm_queue_exception(vcpu, vector);
37b96e98 7034 break;
66fd3f7f 7035 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7036 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7037 /* fall through */
37b96e98 7038 case INTR_TYPE_EXT_INTR:
3ab66e8a 7039 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7040 break;
7041 default:
7042 break;
f7d9238f 7043 }
cf393f75
AK		 7044}
7045
83422e17
AK		 7046static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7047{
3ab66e8a 7048 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7049 VM_EXIT_INSTRUCTION_LEN,
7050 IDT_VECTORING_ERROR_CODE);
7051}
7052
b463a6f7
AK		 7053static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7054{
3ab66e8a 7055 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7056 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7057 VM_ENTRY_INSTRUCTION_LEN,
7058 VM_ENTRY_EXCEPTION_ERROR_CODE);
7059
7060 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7061}
7062
d7cd9796
GN		 7063static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7064{
7065 int i, nr_msrs;
7066 struct perf_guest_switch_msr *msrs;
7067
7068 msrs = perf_guest_get_msrs(&nr_msrs);
7069
7070 if (!msrs)
7071 return;
7072
7073 for (i = 0; i < nr_msrs; i++)
7074 if (msrs[i].host == msrs[i].guest)
7075 clear_atomic_switch_msr(vmx, msrs[i].msr);
7076 else
7077 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7078 msrs[i].host);
7079}
7080
a3b5ba49 7081static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7082{
a2fa3e9f 7083 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7084 unsigned long debugctlmsr;
104f226b
AK		 7085
7086 /* Record the guest's net vcpu time for enforced NMI injections. */
7087 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7088 vmx->entry_time = ktime_get();
7089
7090 /* Don't enter VMX if guest state is invalid, let the exit handler
7091 start emulation until we arrive back to a valid state */
14168786 7092 if (vmx->emulation_required)
104f226b
AK		 7093 return;
7094
012f83cb
AG		 7095 if (vmx->nested.sync_shadow_vmcs) {
7096 copy_vmcs12_to_shadow(vmx);
7097 vmx->nested.sync_shadow_vmcs = false;
7098 }
7099
104f226b
AK		 7100 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7101 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7102 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7103 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7104
7105 /* When single-stepping over STI and MOV SS, we must clear the
7106 * corresponding interruptibility bits in the guest state. Otherwise
7107 * vmentry fails as it then expects bit 14 (BS) in pending debug
7108 * exceptions being set, but that's not correct for the guest debugging
7109 * case. */
7110 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7111 vmx_set_interrupt_shadow(vcpu, 0);
7112
d7cd9796 7113 atomic_switch_perf_msrs(vmx);
2a7921b7 7114 debugctlmsr = get_debugctlmsr();
d7cd9796 7115
d462b819 7116 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7117 asm(
6aa8b732 7118 /* Store host registers */
b188c81f
AK		 7119 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7120 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7121 "push %%" _ASM_CX " \n\t"
7122 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7123 "je 1f \n\t"
b188c81f 7124 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7125 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7126 "1: \n\t"
d3edefc0 7127 /* Reload cr2 if changed */
b188c81f
AK		 7128 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7129 "mov %%cr2, %%" _ASM_DX " \n\t"
7130 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7131 "je 2f \n\t"
b188c81f 7132 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7133 "2: \n\t"
6aa8b732 7134 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7135 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7136 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7137 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7138 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7139 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7140 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7141 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7142 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7143#ifdef CONFIG_X86_64
e08aa78a
AK		 7144 "mov %c[r8](%0), %%r8 \n\t"
7145 "mov %c[r9](%0), %%r9 \n\t"
7146 "mov %c[r10](%0), %%r10 \n\t"
7147 "mov %c[r11](%0), %%r11 \n\t"
7148 "mov %c[r12](%0), %%r12 \n\t"
7149 "mov %c[r13](%0), %%r13 \n\t"
7150 "mov %c[r14](%0), %%r14 \n\t"
7151 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7152#endif
b188c81f 7153 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7154
6aa8b732 7155 /* Enter guest mode */
83287ea4 7156 "jne 1f \n\t"
4ecac3fd 7157 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7158 "jmp 2f \n\t"
7159 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7160 "2: "
6aa8b732 7161 /* Save guest registers, load host registers, keep flags */
b188c81f 7162 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7163 "pop %0 \n\t"
b188c81f
AK		 7164 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7165 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7166 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7167 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7168 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7169 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7170 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7171#ifdef CONFIG_X86_64
e08aa78a
AK		 7172 "mov %%r8, %c[r8](%0) \n\t"
7173 "mov %%r9, %c[r9](%0) \n\t"
7174 "mov %%r10, %c[r10](%0) \n\t"
7175 "mov %%r11, %c[r11](%0) \n\t"
7176 "mov %%r12, %c[r12](%0) \n\t"
7177 "mov %%r13, %c[r13](%0) \n\t"
7178 "mov %%r14, %c[r14](%0) \n\t"
7179 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7180#endif
b188c81f
AK		 7181 "mov %%cr2, %%" _ASM_AX " \n\t"
7182 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7183
b188c81f 7184 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7185 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7186 ".pushsection .rodata \n\t"
7187 ".global vmx_return \n\t"
7188 "vmx_return: " _ASM_PTR " 2b \n\t"
7189 ".popsection"
e08aa78a 7190 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7191 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7192 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7193 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7194 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7195 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7196 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7197 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7198 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7199 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7200 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7201#ifdef CONFIG_X86_64
ad312c7c
ZX		 7202 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7203 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7204 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7205 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7206 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7207 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7208 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7209 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7210#endif
40712fae
AK		 7211 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7212 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7213 : "cc", "memory"
7214#ifdef CONFIG_X86_64
b188c81f 7215 , "rax", "rbx", "rdi", "rsi"
c2036300 7216 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7217#else
7218 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7219#endif
7220 );
6aa8b732 7221
2a7921b7
GN		 7222 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7223 if (debugctlmsr)
7224 update_debugctlmsr(debugctlmsr);
7225
aa67f609
AK		 7226#ifndef CONFIG_X86_64
7227 /*
7228 * The sysexit path does not restore ds/es, so we must set them to
7229 * a reasonable value ourselves.
7230 *
7231 * We can't defer this to vmx_load_host_state() since that function
7232 * may be executed in interrupt context, which saves and restore segments
7233 * around it, nullifying its effect.
7234 */
7235 loadsegment(ds, __USER_DS);
7236 loadsegment(es, __USER_DS);
7237#endif
7238
6de4f3ad 7239 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7240 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7241 | (1 << VCPU_EXREG_CPL)
aff48baa 7242 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7243 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7244 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7245 vcpu->arch.regs_dirty = 0;
7246
1155f76a
AK		 7247 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7248
d462b819 7249 vmx->loaded_vmcs->launched = 1;
1b6269db 7250
51aa01d1 7251 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7252 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7253
7254 vmx_complete_atomic_exit(vmx);
7255 vmx_recover_nmi_blocking(vmx);
cf393f75 7256 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7257}
7258
6aa8b732
AK		 7259static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7260{
fb3f0f51
RR		 7261 struct vcpu_vmx *vmx = to_vmx(vcpu);
7262
cdbecfc3 7263 free_vpid(vmx);
ec378aee 7264 free_nested(vmx);
d462b819 7265 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7266 kfree(vmx->guest_msrs);
7267 kvm_vcpu_uninit(vcpu);
a4770347 7268 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7269}
7270
fb3f0f51 7271static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7272{
fb3f0f51 7273 int err;
c16f862d 7274 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7275 int cpu;
6aa8b732 7276
a2fa3e9f 7277 if (!vmx)
fb3f0f51
RR		 7278 return ERR_PTR(-ENOMEM);
7279
2384d2b3
SY		 7280 allocate_vpid(vmx);
7281
fb3f0f51
RR		 7282 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7283 if (err)
7284 goto free_vcpu;
965b58a5 7285
a2fa3e9f 7286 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7287 err = -ENOMEM;
fb3f0f51 7288 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7289 goto uninit_vcpu;
7290 }
965b58a5 7291
d462b819
NHE		 7292 vmx->loaded_vmcs = &vmx->vmcs01;
7293 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7294 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7295 goto free_msrs;
d462b819
NHE		 7296 if (!vmm_exclusive)
7297 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7298 loaded_vmcs_init(vmx->loaded_vmcs);
7299 if (!vmm_exclusive)
7300 kvm_cpu_vmxoff();
a2fa3e9f 7301
15ad7146
AK		 7302 cpu = get_cpu();
7303 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7304 vmx->vcpu.cpu = cpu;
8b9cf98c 7305 err = vmx_vcpu_setup(vmx);
fb3f0f51 7306 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7307 put_cpu();
fb3f0f51
RR		 7308 if (err)
7309 goto free_vmcs;
a63cb560 7310 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7311 err = alloc_apic_access_page(kvm);
7312 if (err)
5e4a0b3c 7313 goto free_vmcs;
a63cb560 7314 }
fb3f0f51 7315
b927a3ce
SY		 7316 if (enable_ept) {
7317 if (!kvm->arch.ept_identity_map_addr)
7318 kvm->arch.ept_identity_map_addr =
7319 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7320 err = -ENOMEM;
b7ebfb05
SY		 7321 if (alloc_identity_pagetable(kvm) != 0)
7322 goto free_vmcs;
93ea5388
GN		 7323 if (!init_rmode_identity_map(kvm))
7324 goto free_vmcs;
b927a3ce 7325 }
b7ebfb05 7326
a9d30f33
NHE		 7327 vmx->nested.current_vmptr = -1ull;
7328 vmx->nested.current_vmcs12 = NULL;
7329
fb3f0f51
RR		 7330 return &vmx->vcpu;
7331
7332free_vmcs:
5f3fbc34 7333 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7334free_msrs:
fb3f0f51
RR		 7335 kfree(vmx->guest_msrs);
7336uninit_vcpu:
7337 kvm_vcpu_uninit(&vmx->vcpu);
7338free_vcpu:
cdbecfc3 7339 free_vpid(vmx);
a4770347 7340 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7341 return ERR_PTR(err);
6aa8b732
AK		 7342}
7343
002c7f7c
YS		 7344static void __init vmx_check_processor_compat(void *rtn)
7345{
7346 struct vmcs_config vmcs_conf;
7347
7348 *(int *)rtn = 0;
7349 if (setup_vmcs_config(&vmcs_conf) < 0)
7350 *(int *)rtn = -EIO;
7351 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7352 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7353 smp_processor_id());
7354 *(int *)rtn = -EIO;
7355 }
7356}
7357
67253af5
SY		 7358static int get_ept_level(void)
7359{
7360 return VMX_EPT_DEFAULT_GAW + 1;
7361}
7362
4b12f0de 7363static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7364{
4b12f0de
SY		 7365 u64 ret;
7366
522c68c4
SY		 7367 /* For VT-d and EPT combination
7368 * 1. MMIO: always map as UC
7369 * 2. EPT with VT-d:
7370 * a. VT-d without snooping control feature: can't guarantee the
7371 * result, try to trust guest.
7372 * b. VT-d with snooping control feature: snooping control feature of
7373 * VT-d engine can guarantee the cache correctness. Just set it
7374 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7375 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7376 * consistent with host MTRR
7377 */
4b12f0de
SY		 7378 if (is_mmio)
7379 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7380 else if (vcpu->kvm->arch.iommu_domain &&
7381 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7382 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7383 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7384 else
522c68c4 7385 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7386 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7387
7388 return ret;
64d4d521
SY		 7389}
7390
17cc3935 7391static int vmx_get_lpage_level(void)
344f414f 7392{
878403b7
SY		 7393 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7394 return PT_DIRECTORY_LEVEL;
7395 else
7396 /* For shadow and EPT supported 1GB page */
7397 return PT_PDPE_LEVEL;
344f414f
JR		 7398}
7399
0e851880
SY		 7400static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7401{
4e47c7a6
SY		 7402 struct kvm_cpuid_entry2 *best;
7403 struct vcpu_vmx *vmx = to_vmx(vcpu);
7404 u32 exec_control;
7405
7406 vmx->rdtscp_enabled = false;
7407 if (vmx_rdtscp_supported()) {
7408 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7409 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7410 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7411 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7412 vmx->rdtscp_enabled = true;
7413 else {
7414 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7415 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7416 exec_control);
7417 }
7418 }
7419 }
ad756a16 7420
ad756a16
MJ		 7421 /* Exposing INVPCID only when PCID is exposed */
7422 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7423 if (vmx_invpcid_supported() &&
4f977045 7424 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7425 guest_cpuid_has_pcid(vcpu)) {
29282fde 7426 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7427 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7428 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7429 exec_control);
7430 } else {
29282fde
TI		 7431 if (cpu_has_secondary_exec_ctrls()) {
7432 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7433 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7434 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7435 exec_control);
7436 }
ad756a16 7437 if (best)
4f977045 7438 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7439 }
0e851880
SY		 7440}
7441
d4330ef2
JR		 7442static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7443{
7b8050f5
NHE		 7444 if (func == 1 && nested)
7445 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7446}
7447
25d92081
YZ		 7448static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7449 struct x86_exception *fault)
7450{
7451 struct vmcs12 *vmcs12;
7452 nested_vmx_vmexit(vcpu);
7453 vmcs12 = get_vmcs12(vcpu);
7454
7455 if (fault->error_code & PFERR_RSVD_MASK)
7456 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7457 else
7458 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7459 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7460 vmcs12->guest_physical_address = fault->address;
7461}
7462
155a97a3
NHE		 7463/* Callbacks for nested_ept_init_mmu_context: */
7464
7465static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7466{
7467 /* return the page table to be shadowed - in our case, EPT12 */
7468 return get_vmcs12(vcpu)->ept_pointer;
7469}
7470
7471static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7472{
7473 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7474 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7475
7476 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7477 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7478 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7479
7480 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7481
7482 return r;
7483}
7484
7485static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7486{
7487 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7488}
7489
fe3ef05c
NHE		 7490/*
7491 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7492 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7493 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7494 * guest in a way that will both be appropriate to L1's requests, and our
7495 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7496 * function also has additional necessary side-effects, like setting various
7497 * vcpu->arch fields.
7498 */
7499static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7500{
7501 struct vcpu_vmx *vmx = to_vmx(vcpu);
7502 u32 exec_control;
7503
7504 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7505 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7506 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7507 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7508 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7509 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7510 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7511 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7512 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7513 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7514 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7515 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7516 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7517 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7518 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7519 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7520 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7521 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7522 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7523 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7524 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7525 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7526 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7527 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7528 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7529 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7530 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7531 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7532 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7533 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7534 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7535 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7536 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7537 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7538 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7539 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7540
7541 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7542 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7543 vmcs12->vm_entry_intr_info_field);
7544 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7545 vmcs12->vm_entry_exception_error_code);
7546 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7547 vmcs12->vm_entry_instruction_len);
7548 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7549 vmcs12->guest_interruptibility_info);
fe3ef05c 7550 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7551 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7552 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7553 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7554 vmcs12->guest_pending_dbg_exceptions);
7555 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7556 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7557
7558 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7559
7560 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7561 (vmcs_config.pin_based_exec_ctrl |
7562 vmcs12->pin_based_vm_exec_control));
7563
0238ea91
JK		 7564 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7565 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7566 vmcs12->vmx_preemption_timer_value);
7567
fe3ef05c
NHE		 7568 /*
7569 * Whether page-faults are trapped is determined by a combination of
7570 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7571 * If enable_ept, L0 doesn't care about page faults and we should
7572 * set all of these to L1's desires. However, if !enable_ept, L0 does
7573 * care about (at least some) page faults, and because it is not easy
7574 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7575 * to exit on each and every L2 page fault. This is done by setting
7576 * MASK=MATCH=0 and (see below) EB.PF=1.
7577 * Note that below we don't need special code to set EB.PF beyond the
7578 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7579 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7580 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7581 *
7582 * A problem with this approach (when !enable_ept) is that L1 may be
7583 * injected with more page faults than it asked for. This could have
7584 * caused problems, but in practice existing hypervisors don't care.
7585 * To fix this, we will need to emulate the PFEC checking (on the L1
7586 * page tables), using walk_addr(), when injecting PFs to L1.
7587 */
7588 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7589 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7590 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7591 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7592
7593 if (cpu_has_secondary_exec_ctrls()) {
7594 u32 exec_control = vmx_secondary_exec_control(vmx);
7595 if (!vmx->rdtscp_enabled)
7596 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7597 /* Take the following fields only from vmcs12 */
7598 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7599 if (nested_cpu_has(vmcs12,
7600 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7601 exec_control |= vmcs12->secondary_vm_exec_control;
7602
7603 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7604 /*
7605 * Translate L1 physical address to host physical
7606 * address for vmcs02. Keep the page pinned, so this
7607 * physical address remains valid. We keep a reference
7608 * to it so we can release it later.
7609 */
7610 if (vmx->nested.apic_access_page) /* shouldn't happen */
7611 nested_release_page(vmx->nested.apic_access_page);
7612 vmx->nested.apic_access_page =
7613 nested_get_page(vcpu, vmcs12->apic_access_addr);
7614 /*
7615 * If translation failed, no matter: This feature asks
7616 * to exit when accessing the given address, and if it
7617 * can never be accessed, this feature won't do
7618 * anything anyway.
7619 */
7620 if (!vmx->nested.apic_access_page)
7621 exec_control &=
7622 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7623 else
7624 vmcs_write64(APIC_ACCESS_ADDR,
7625 page_to_phys(vmx->nested.apic_access_page));
7626 }
7627
7628 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7629 }
7630
7631
7632 /*
7633 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7634 * Some constant fields are set here by vmx_set_constant_host_state().
7635 * Other fields are different per CPU, and will be set later when
7636 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7637 */
a547c6db 7638 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7639
7640 /*
7641 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7642 * entry, but only if the current (host) sp changed from the value
7643 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7644 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7645 * here we just force the write to happen on entry.
7646 */
7647 vmx->host_rsp = 0;
7648
7649 exec_control = vmx_exec_control(vmx); /* L0's desires */
7650 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7651 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7652 exec_control &= ~CPU_BASED_TPR_SHADOW;
7653 exec_control |= vmcs12->cpu_based_vm_exec_control;
7654 /*
7655 * Merging of IO and MSR bitmaps not currently supported.
7656 * Rather, exit every time.
7657 */
7658 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7659 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7660 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7661
7662 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7663
7664 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7665 * bitwise-or of what L1 wants to trap for L2, and what we want to
7666 * trap. Note that CR0.TS also needs updating - we do this later.
7667 */
7668 update_exception_bitmap(vcpu);
7669 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7670 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7671
8049d651
NHE		 7672 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7673 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7674 * bits are further modified by vmx_set_efer() below.
7675 */
7676 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7677
7678 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7679 * emulated by vmx_set_efer(), below.
7680 */
7681 vmcs_write32(VM_ENTRY_CONTROLS,
7682 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7683 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7684 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7685
7686 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7687 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7688 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7689 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7690
7691
7692 set_cr4_guest_host_mask(vmx);
7693
27fc51b2
NHE		 7694 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7695 vmcs_write64(TSC_OFFSET,
7696 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7697 else
7698 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7699
7700 if (enable_vpid) {
7701 /*
7702 * Trivially support vpid by letting L2s share their parent
7703 * L1's vpid. TODO: move to a more elaborate solution, giving
7704 * each L2 its own vpid and exposing the vpid feature to L1.
7705 */
7706 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7707 vmx_flush_tlb(vcpu);
7708 }
7709
155a97a3
NHE		 7710 if (nested_cpu_has_ept(vmcs12)) {
7711 kvm_mmu_unload(vcpu);
7712 nested_ept_init_mmu_context(vcpu);
7713 }
7714
fe3ef05c
NHE		 7715 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7716 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7717 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7718 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7719 else
7720 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7721 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7722 vmx_set_efer(vcpu, vcpu->arch.efer);
7723
7724 /*
7725 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7726 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7727 * The CR0_READ_SHADOW is what L2 should have expected to read given
7728 * the specifications by L1; It's not enough to take
7729 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7730 * have more bits than L1 expected.
7731 */
7732 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7733 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7734
7735 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7736 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7737
7738 /* shadow page tables on either EPT or shadow page tables */
7739 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7740 kvm_mmu_reset_context(vcpu);
7741
3633cfc3
NHE		 7742 /*
7743 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7744 */
7745 if (enable_ept) {
7746 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7747 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7748 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7749 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7750 }
7751
fe3ef05c
NHE		 7752 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7753 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7754}
7755
cd232ad0
NHE		 7756/*
7757 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7758 * for running an L2 nested guest.
7759 */
7760static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7761{
7762 struct vmcs12 *vmcs12;
7763 struct vcpu_vmx *vmx = to_vmx(vcpu);
7764 int cpu;
7765 struct loaded_vmcs *vmcs02;
384bb783 7766 bool ia32e;
cd232ad0
NHE		 7767
7768 if (!nested_vmx_check_permission(vcpu) ||
7769 !nested_vmx_check_vmcs12(vcpu))
7770 return 1;
7771
7772 skip_emulated_instruction(vcpu);
7773 vmcs12 = get_vmcs12(vcpu);
7774
012f83cb
AG		 7775 if (enable_shadow_vmcs)
7776 copy_shadow_to_vmcs12(vmx);
7777
7c177938
NHE		 7778 /*
7779 * The nested entry process starts with enforcing various prerequisites
7780 * on vmcs12 as required by the Intel SDM, and act appropriately when
7781 * they fail: As the SDM explains, some conditions should cause the
7782 * instruction to fail, while others will cause the instruction to seem
7783 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7784 * To speed up the normal (success) code path, we should avoid checking
7785 * for misconfigurations which will anyway be caught by the processor
7786 * when using the merged vmcs02.
7787 */
7788 if (vmcs12->launch_state == launch) {
7789 nested_vmx_failValid(vcpu,
7790 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7791 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7792 return 1;
7793 }
7794
26539bd0
PB		 7795 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7796 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7797 return 1;
7798 }
7799
7c177938
NHE		 7800 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7801 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7802 /*TODO: Also verify bits beyond physical address width are 0*/
7803 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7804 return 1;
7805 }
7806
7807 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7808 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7809 /*TODO: Also verify bits beyond physical address width are 0*/
7810 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7811 return 1;
7812 }
7813
7814 if (vmcs12->vm_entry_msr_load_count > 0 ||
7815 vmcs12->vm_exit_msr_load_count > 0 ||
7816 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7817 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7818 __func__);
7c177938
NHE		 7819 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7820 return 1;
7821 }
7822
7823 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7824 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7825 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7826 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7827 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7828 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7829 !vmx_control_verify(vmcs12->vm_exit_controls,
7830 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7831 !vmx_control_verify(vmcs12->vm_entry_controls,
7832 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7833 {
7834 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7835 return 1;
7836 }
7837
7838 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7839 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7840 nested_vmx_failValid(vcpu,
7841 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7842 return 1;
7843 }
7844
7845 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7846 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7847 nested_vmx_entry_failure(vcpu, vmcs12,
7848 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7849 return 1;
7850 }
7851 if (vmcs12->vmcs_link_pointer != -1ull) {
7852 nested_vmx_entry_failure(vcpu, vmcs12,
7853 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7854 return 1;
7855 }
7856
384bb783 7857 /*
cb0c8cda 7858 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7859 * are performed on the field for the IA32_EFER MSR:
7860 * - Bits reserved in the IA32_EFER MSR must be 0.
7861 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7862 * the IA-32e mode guest VM-exit control. It must also be identical
7863 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7864 * CR0.PG) is 1.
7865 */
7866 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7867 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7868 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7869 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7870 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7871 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7872 nested_vmx_entry_failure(vcpu, vmcs12,
7873 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7874 return 1;
7875 }
7876 }
7877
7878 /*
7879 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7880 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7881 * the values of the LMA and LME bits in the field must each be that of
7882 * the host address-space size VM-exit control.
7883 */
7884 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7885 ia32e = (vmcs12->vm_exit_controls &
7886 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7887 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7888 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7889 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7890 nested_vmx_entry_failure(vcpu, vmcs12,
7891 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7892 return 1;
7893 }
7894 }
7895
7c177938
NHE		 7896 /*
7897 * We're finally done with prerequisite checking, and can start with
7898 * the nested entry.
7899 */
7900
cd232ad0
NHE		 7901 vmcs02 = nested_get_current_vmcs02(vmx);
7902 if (!vmcs02)
7903 return -ENOMEM;
7904
7905 enter_guest_mode(vcpu);
7906
7907 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7908
7909 cpu = get_cpu();
7910 vmx->loaded_vmcs = vmcs02;
7911 vmx_vcpu_put(vcpu);
7912 vmx_vcpu_load(vcpu, cpu);
7913 vcpu->cpu = cpu;
7914 put_cpu();
7915
36c3cc42
JK		 7916 vmx_segment_cache_clear(vmx);
7917
cd232ad0
NHE		 7918 vmcs12->launch_state = 1;
7919
7920 prepare_vmcs02(vcpu, vmcs12);
7921
7922 /*
7923 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7924 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7925 * returned as far as L1 is concerned. It will only return (and set
7926 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7927 */
7928 return 1;
7929}
7930
4704d0be
NHE		 7931/*
7932 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7933 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7934 * This function returns the new value we should put in vmcs12.guest_cr0.
7935 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7936 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7937 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7938 * didn't trap the bit, because if L1 did, so would L0).
7939 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7940 * been modified by L2, and L1 knows it. So just leave the old value of
7941 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7942 * isn't relevant, because if L0 traps this bit it can set it to anything.
7943 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7944 * changed these bits, and therefore they need to be updated, but L0
7945 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7946 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7947 */
7948static inline unsigned long
7949vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7950{
7951 return
7952 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7953 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7954 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7955 vcpu->arch.cr0_guest_owned_bits));
7956}
7957
7958static inline unsigned long
7959vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7960{
7961 return
7962 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7963 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7964 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7965 vcpu->arch.cr4_guest_owned_bits));
7966}
7967
5f3d5799
JK		 7968static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7969 struct vmcs12 *vmcs12)
7970{
7971 u32 idt_vectoring;
7972 unsigned int nr;
7973
7974 if (vcpu->arch.exception.pending) {
7975 nr = vcpu->arch.exception.nr;
7976 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7977
7978 if (kvm_exception_is_soft(nr)) {
7979 vmcs12->vm_exit_instruction_len =
7980 vcpu->arch.event_exit_inst_len;
7981 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7982 } else
7983 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7984
7985 if (vcpu->arch.exception.has_error_code) {
7986 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7987 vmcs12->idt_vectoring_error_code =
7988 vcpu->arch.exception.error_code;
7989 }
7990
7991 vmcs12->idt_vectoring_info_field = idt_vectoring;
7992 } else if (vcpu->arch.nmi_pending) {
7993 vmcs12->idt_vectoring_info_field =
7994 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7995 } else if (vcpu->arch.interrupt.pending) {
7996 nr = vcpu->arch.interrupt.nr;
7997 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7998
7999 if (vcpu->arch.interrupt.soft) {
8000 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8001 vmcs12->vm_entry_instruction_len =
8002 vcpu->arch.event_exit_inst_len;
8003 } else
8004 idt_vectoring |= INTR_TYPE_EXT_INTR;
8005
8006 vmcs12->idt_vectoring_info_field = idt_vectoring;
8007 }
8008}
8009
4704d0be
NHE		 8010/*
8011 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8012 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8013 * and this function updates it to reflect the changes to the guest state while
8014 * L2 was running (and perhaps made some exits which were handled directly by L0
8015 * without going back to L1), and to reflect the exit reason.
8016 * Note that we do not have to copy here all VMCS fields, just those that
8017 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8018 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8019 * which already writes to vmcs12 directly.
8020 */
733568f9 8021static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8022{
8023 /* update guest state fields: */
8024 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8025 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8026
8027 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8028 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8029 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8030 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8031
8032 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8033 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8034 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8035 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8036 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8037 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8038 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8039 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8040 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8041 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8042 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8043 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8044 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8045 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8046 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8047 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8048 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8049 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8050 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8051 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8052 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8053 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8054 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8055 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8056 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8057 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8058 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8059 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8060 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8061 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8062 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8063 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8064 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8065 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8066 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8067 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8068
4704d0be
NHE		 8069 vmcs12->guest_interruptibility_info =
8070 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8071 vmcs12->guest_pending_dbg_exceptions =
8072 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8073
3633cfc3
NHE		 8074 /*
8075 * In some cases (usually, nested EPT), L2 is allowed to change its
8076 * own CR3 without exiting. If it has changed it, we must keep it.
8077 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8078 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8079 *
8080 * Additionally, restore L2's PDPTR to vmcs12.
8081 */
8082 if (enable_ept) {
8083 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8084 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8085 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8086 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8087 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8088 }
8089
c18911a2
JK		 8090 vmcs12->vm_entry_controls =
8091 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8092 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8093
4704d0be
NHE		 8094 /* TODO: These cannot have changed unless we have MSR bitmaps and
8095 * the relevant bit asks not to trap the change */
8096 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8097 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 8098 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8099 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8100 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8101 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8102
8103 /* update exit information fields: */
8104
957c897e 8105 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8106 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8107
8108 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8109 if ((vmcs12->vm_exit_intr_info &
8110 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8111 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8112 vmcs12->vm_exit_intr_error_code =
8113 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8114 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8115 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8116 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8117
5f3d5799
JK		 8118 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8119 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8120 * instead of reading the real value. */
4704d0be 8121 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8122
8123 /*
8124 * Transfer the event that L0 or L1 may wanted to inject into
8125 * L2 to IDT_VECTORING_INFO_FIELD.
8126 */
8127 vmcs12_save_pending_event(vcpu, vmcs12);
8128 }
8129
8130 /*
8131 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8132 * preserved above and would only end up incorrectly in L1.
8133 */
8134 vcpu->arch.nmi_injected = false;
8135 kvm_clear_exception_queue(vcpu);
8136 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8137}
8138
8139/*
8140 * A part of what we need to when the nested L2 guest exits and we want to
8141 * run its L1 parent, is to reset L1's guest state to the host state specified
8142 * in vmcs12.
8143 * This function is to be called not only on normal nested exit, but also on
8144 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8145 * Failures During or After Loading Guest State").
8146 * This function should be called when the active VMCS is L1's (vmcs01).
8147 */
733568f9
JK		 8148static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8149 struct vmcs12 *vmcs12)
4704d0be 8150{
21feb4eb
ACL		 8151 struct kvm_segment seg;
8152
4704d0be
NHE		 8153 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8154 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8155 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8156 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8157 else
8158 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8159 vmx_set_efer(vcpu, vcpu->arch.efer);
8160
8161 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8162 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8163 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8164 /*
8165 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8166 * actually changed, because it depends on the current state of
8167 * fpu_active (which may have changed).
8168 * Note that vmx_set_cr0 refers to efer set above.
8169 */
8170 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8171 /*
8172 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8173 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8174 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8175 */
8176 update_exception_bitmap(vcpu);
8177 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8178 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8179
8180 /*
8181 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8182 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8183 */
8184 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8185 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8186
155a97a3
NHE		 8187 if (nested_cpu_has_ept(vmcs12))
8188 nested_ept_uninit_mmu_context(vcpu);
8189
4704d0be
NHE		 8190 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8191 kvm_mmu_reset_context(vcpu);
8192
8193 if (enable_vpid) {
8194 /*
8195 * Trivially support vpid by letting L2s share their parent
8196 * L1's vpid. TODO: move to a more elaborate solution, giving
8197 * each L2 its own vpid and exposing the vpid feature to L1.
8198 */
8199 vmx_flush_tlb(vcpu);
8200 }
8201
8202
8203 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8204 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8205 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8206 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8207 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be
NHE		 8208
8209 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8210 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8211 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8212 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8213 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8214
21feb4eb
ACL		 8215 /* Set L1 segment info according to Intel SDM
8216 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8217 seg = (struct kvm_segment) {
8218 .base = 0,
8219 .limit = 0xFFFFFFFF,
8220 .selector = vmcs12->host_cs_selector,
8221 .type = 11,
8222 .present = 1,
8223 .s = 1,
8224 .g = 1
8225 };
8226 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8227 seg.l = 1;
8228 else
8229 seg.db = 1;
8230 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8231 seg = (struct kvm_segment) {
8232 .base = 0,
8233 .limit = 0xFFFFFFFF,
8234 .type = 3,
8235 .present = 1,
8236 .s = 1,
8237 .db = 1,
8238 .g = 1
8239 };
8240 seg.selector = vmcs12->host_ds_selector;
8241 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8242 seg.selector = vmcs12->host_es_selector;
8243 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8244 seg.selector = vmcs12->host_ss_selector;
8245 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8246 seg.selector = vmcs12->host_fs_selector;
8247 seg.base = vmcs12->host_fs_base;
8248 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8249 seg.selector = vmcs12->host_gs_selector;
8250 seg.base = vmcs12->host_gs_base;
8251 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8252 seg = (struct kvm_segment) {
205befd9 8253 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8254 .limit = 0x67,
8255 .selector = vmcs12->host_tr_selector,
8256 .type = 11,
8257 .present = 1
8258 };
8259 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8260
503cd0c5
JK		 8261 kvm_set_dr(vcpu, 7, 0x400);
8262 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8263}
8264
8265/*
8266 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8267 * and modify vmcs12 to make it see what it would expect to see there if
8268 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8269 */
8270static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8271{
8272 struct vcpu_vmx *vmx = to_vmx(vcpu);
8273 int cpu;
8274 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8275
5f3d5799
JK		 8276 /* trying to cancel vmlaunch/vmresume is a bug */
8277 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8278
4704d0be
NHE		 8279 leave_guest_mode(vcpu);
8280 prepare_vmcs12(vcpu, vmcs12);
8281
8282 cpu = get_cpu();
8283 vmx->loaded_vmcs = &vmx->vmcs01;
8284 vmx_vcpu_put(vcpu);
8285 vmx_vcpu_load(vcpu, cpu);
8286 vcpu->cpu = cpu;
8287 put_cpu();
8288
36c3cc42
JK		 8289 vmx_segment_cache_clear(vmx);
8290
4704d0be
NHE		 8291 /* if no vmcs02 cache requested, remove the one we used */
8292 if (VMCS02_POOL_SIZE == 0)
8293 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8294
8295 load_vmcs12_host_state(vcpu, vmcs12);
8296
27fc51b2 8297 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8298 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8299
8300 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8301 vmx->host_rsp = 0;
8302
8303 /* Unpin physical memory we referred to in vmcs02 */
8304 if (vmx->nested.apic_access_page) {
8305 nested_release_page(vmx->nested.apic_access_page);
8306 vmx->nested.apic_access_page = 0;
8307 }
8308
8309 /*
8310 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8311 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8312 * success or failure flag accordingly.
8313 */
8314 if (unlikely(vmx->fail)) {
8315 vmx->fail = 0;
8316 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8317 } else
8318 nested_vmx_succeed(vcpu);
012f83cb
AG		 8319 if (enable_shadow_vmcs)
8320 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8321}
8322
7c177938
NHE		 8323/*
8324 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8325 * 23.7 "VM-entry failures during or after loading guest state" (this also
8326 * lists the acceptable exit-reason and exit-qualification parameters).
8327 * It should only be called before L2 actually succeeded to run, and when
8328 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8329 */
8330static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8331 struct vmcs12 *vmcs12,
8332 u32 reason, unsigned long qualification)
8333{
8334 load_vmcs12_host_state(vcpu, vmcs12);
8335 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8336 vmcs12->exit_qualification = qualification;
8337 nested_vmx_succeed(vcpu);
012f83cb
AG		 8338 if (enable_shadow_vmcs)
8339 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8340}
8341
8a76d7f2
JR		 8342static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8343 struct x86_instruction_info *info,
8344 enum x86_intercept_stage stage)
8345{
8346 return X86EMUL_CONTINUE;
8347}
8348
cbdd1bea 8349static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8350 .cpu_has_kvm_support = cpu_has_kvm_support,
8351 .disabled_by_bios = vmx_disabled_by_bios,
8352 .hardware_setup = hardware_setup,
8353 .hardware_unsetup = hardware_unsetup,
002c7f7c 8354 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8355 .hardware_enable = hardware_enable,
8356 .hardware_disable = hardware_disable,
04547156 8357 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8358
8359 .vcpu_create = vmx_create_vcpu,
8360 .vcpu_free = vmx_free_vcpu,
04d2cc77 8361 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8362
04d2cc77 8363 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8364 .vcpu_load = vmx_vcpu_load,
8365 .vcpu_put = vmx_vcpu_put,
8366
c8639010 8367 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8368 .get_msr = vmx_get_msr,
8369 .set_msr = vmx_set_msr,
8370 .get_segment_base = vmx_get_segment_base,
8371 .get_segment = vmx_get_segment,
8372 .set_segment = vmx_set_segment,
2e4d2653 8373 .get_cpl = vmx_get_cpl,
6aa8b732 8374 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8375 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8376 .decache_cr3 = vmx_decache_cr3,
25c4c276 8377 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8378 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8379 .set_cr3 = vmx_set_cr3,
8380 .set_cr4 = vmx_set_cr4,
6aa8b732 8381 .set_efer = vmx_set_efer,
6aa8b732
AK		 8382 .get_idt = vmx_get_idt,
8383 .set_idt = vmx_set_idt,
8384 .get_gdt = vmx_get_gdt,
8385 .set_gdt = vmx_set_gdt,
020df079 8386 .set_dr7 = vmx_set_dr7,
5fdbf976 8387 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8388 .get_rflags = vmx_get_rflags,
8389 .set_rflags = vmx_set_rflags,
ebcbab4c 8390 .fpu_activate = vmx_fpu_activate,
02daab21 8391 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8392
8393 .tlb_flush = vmx_flush_tlb,
6aa8b732 8394
6aa8b732 8395 .run = vmx_vcpu_run,
6062d012 8396 .handle_exit = vmx_handle_exit,
6aa8b732 8397 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8398 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8399 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8400 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8401 .set_irq = vmx_inject_irq,
95ba8273 8402 .set_nmi = vmx_inject_nmi,
298101da 8403 .queue_exception = vmx_queue_exception,
b463a6f7 8404 .cancel_injection = vmx_cancel_injection,
78646121 8405 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8406 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8407 .get_nmi_mask = vmx_get_nmi_mask,
8408 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8409 .enable_nmi_window = enable_nmi_window,
8410 .enable_irq_window = enable_irq_window,
8411 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8412 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8413 .vm_has_apicv = vmx_vm_has_apicv,
8414 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8415 .hwapic_irr_update = vmx_hwapic_irr_update,
8416 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8417 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8418 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8419
cbc94022 8420 .set_tss_addr = vmx_set_tss_addr,
67253af5 8421 .get_tdp_level = get_ept_level,
4b12f0de 8422 .get_mt_mask = vmx_get_mt_mask,
229456fc 8423
586f9607 8424 .get_exit_info = vmx_get_exit_info,
586f9607 8425
17cc3935 8426 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8427
8428 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8429
8430 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8431 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8432
8433 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8434
8435 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8436
4051b188 8437 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8438 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8439 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8440 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8441 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8442 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8443
8444 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8445
8446 .check_intercept = vmx_check_intercept,
a547c6db 8447 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8448};
8449
8450static int __init vmx_init(void)
8451{
8d14695f 8452 int r, i, msr;
26bb0981
AK		 8453
8454 rdmsrl_safe(MSR_EFER, &host_efer);
8455
8456 for (i = 0; i < NR_VMX_MSR; ++i)
8457 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8458
3e7c73e9 8459 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8460 if (!vmx_io_bitmap_a)
8461 return -ENOMEM;
8462
2106a548
GC		 8463 r = -ENOMEM;
8464
3e7c73e9 8465 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8466 if (!vmx_io_bitmap_b)
fdef3ad1 8467 goto out;
fdef3ad1 8468
5897297b 8469 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8470 if (!vmx_msr_bitmap_legacy)
25c5f225 8471 goto out1;
2106a548 8472
8d14695f
YZ		 8473 vmx_msr_bitmap_legacy_x2apic =
8474 (unsigned long *)__get_free_page(GFP_KERNEL);
8475 if (!vmx_msr_bitmap_legacy_x2apic)
8476 goto out2;
25c5f225 8477
5897297b 8478 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8479 if (!vmx_msr_bitmap_longmode)
8d14695f 8480 goto out3;
2106a548 8481
8d14695f
YZ		 8482 vmx_msr_bitmap_longmode_x2apic =
8483 (unsigned long *)__get_free_page(GFP_KERNEL);
8484 if (!vmx_msr_bitmap_longmode_x2apic)
8485 goto out4;
4607c2d7
AG		 8486 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8487 if (!vmx_vmread_bitmap)
8488 goto out5;
8489
8490 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8491 if (!vmx_vmwrite_bitmap)
8492 goto out6;
8493
8494 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8495 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8496 /* shadowed read/write fields */
8497 for (i = 0; i < max_shadow_read_write_fields; i++) {
8498 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8499 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8500 }
8501 /* shadowed read only fields */
8502 for (i = 0; i < max_shadow_read_only_fields; i++)
8503 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8504
fdef3ad1
HQ		 8505 /*
8506 * Allow direct access to the PC debug port (it is often used for I/O
8507 * delays, but the vmexits simply slow things down).
8508 */
3e7c73e9
AK		 8509 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8510 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8511
3e7c73e9 8512 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8513
5897297b
AK		 8514 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8515 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8516
2384d2b3
SY		 8517 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8518
0ee75bea
AK		 8519 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8520 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8521 if (r)
4607c2d7 8522 goto out7;
25c5f225 8523
8f536b76
ZY		 8524#ifdef CONFIG_KEXEC
8525 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8526 crash_vmclear_local_loaded_vmcss);
8527#endif
8528
5897297b
AK		 8529 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8530 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8531 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8532 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8533 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8534 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8535 memcpy(vmx_msr_bitmap_legacy_x2apic,
8536 vmx_msr_bitmap_legacy, PAGE_SIZE);
8537 memcpy(vmx_msr_bitmap_longmode_x2apic,
8538 vmx_msr_bitmap_longmode, PAGE_SIZE);
8539
01e439be 8540 if (enable_apicv) {
8d14695f
YZ		 8541 for (msr = 0x800; msr <= 0x8ff; msr++)
8542 vmx_disable_intercept_msr_read_x2apic(msr);
8543
8544 /* According SDM, in x2apic mode, the whole id reg is used.
8545 * But in KVM, it only use the highest eight bits. Need to
8546 * intercept it */
8547 vmx_enable_intercept_msr_read_x2apic(0x802);
8548 /* TMCCT */
8549 vmx_enable_intercept_msr_read_x2apic(0x839);
8550 /* TPR */
8551 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8552 /* EOI */
8553 vmx_disable_intercept_msr_write_x2apic(0x80b);
8554 /* SELF-IPI */
8555 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8556 }
fdef3ad1 8557
089d034e 8558 if (enable_ept) {
3f6d8c8a
XH		 8559 kvm_mmu_set_mask_ptes(0ull,
8560 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8561 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8562 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8563 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8564 kvm_enable_tdp();
8565 } else
8566 kvm_disable_tdp();
1439442c 8567
fdef3ad1
HQ		 8568 return 0;
8569
4607c2d7
AG		 8570out7:
8571 free_page((unsigned long)vmx_vmwrite_bitmap);
8572out6:
8573 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8574out5:
8575 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8576out4:
5897297b 8577 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8578out3:
8579 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8580out2:
5897297b 8581 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8582out1:
3e7c73e9 8583 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8584out:
3e7c73e9 8585 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8586 return r;
6aa8b732
AK		 8587}
8588
8589static void __exit vmx_exit(void)
8590{
8d14695f
YZ		 8591 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8592 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8593 free_page((unsigned long)vmx_msr_bitmap_legacy);
8594 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8595 free_page((unsigned long)vmx_io_bitmap_b);
8596 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8597 free_page((unsigned long)vmx_vmwrite_bitmap);
8598 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8599
8f536b76
ZY		 8600#ifdef CONFIG_KEXEC
8601 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8602 synchronize_rcu();
8603#endif
8604
cb498ea2 8605 kvm_exit();
6aa8b732
AK		 8606}
8607
8608module_init(vmx_init)
8609module_exit(vmx_exit)
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