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KVM: x86: Sync DR7 on KVM_SET_DEBUGREGS
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
d77c26fc 444 } host_state;
9c8cba37 445 struct {
7ffd92c5 446 int vm86_active;
78ac8b47 447 ulong save_rflags;
f5f7b2fe
AK		 448 struct kvm_segment segs[8];
449 } rmode;
450 struct {
451 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 452 struct kvm_save_segment {
453 u16 selector;
454 unsigned long base;
455 u32 limit;
456 u32 ar;
f5f7b2fe 457 } seg[8];
2fb92db1 458 } segment_cache;
2384d2b3 459 int vpid;
04fa4d32 460 bool emulation_required;
3b86cd99
JK		 461
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked;
464 ktime_t entry_time;
465 s64 vnmi_blocked_time;
a0861c02 466 u32 exit_reason;
4e47c7a6
SY		 467
468 bool rdtscp_enabled;
ec378aee 469
01e439be
YZ		 470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc;
472
ec378aee
NHE		 473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested;
a2fa3e9f
GH		 475};
476
2fb92db1
AK		 477enum segment_cache_field {
478 SEG_FIELD_SEL = 0,
479 SEG_FIELD_BASE = 1,
480 SEG_FIELD_LIMIT = 2,
481 SEG_FIELD_AR = 3,
482
483 SEG_FIELD_NR = 4
484};
485
a2fa3e9f
GH		 486static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
487{
fb3f0f51 488 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 489}
490
22bd0358
NHE		 491#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
495
4607c2d7
AG		 496
497static const unsigned long shadow_read_only_fields[] = {
498 /*
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
509 */
510 VM_EXIT_REASON,
511 VM_EXIT_INTR_INFO,
512 VM_EXIT_INSTRUCTION_LEN,
513 IDT_VECTORING_INFO_FIELD,
514 IDT_VECTORING_ERROR_CODE,
515 VM_EXIT_INTR_ERROR_CODE,
516 EXIT_QUALIFICATION,
517 GUEST_LINEAR_ADDRESS,
518 GUEST_PHYSICAL_ADDRESS
519};
520static const int max_shadow_read_only_fields =
521 ARRAY_SIZE(shadow_read_only_fields);
522
523static const unsigned long shadow_read_write_fields[] = {
524 GUEST_RIP,
525 GUEST_RSP,
526 GUEST_CR0,
527 GUEST_CR3,
528 GUEST_CR4,
529 GUEST_INTERRUPTIBILITY_INFO,
530 GUEST_RFLAGS,
531 GUEST_CS_SELECTOR,
532 GUEST_CS_AR_BYTES,
533 GUEST_CS_LIMIT,
534 GUEST_CS_BASE,
535 GUEST_ES_BASE,
536 CR0_GUEST_HOST_MASK,
537 CR0_READ_SHADOW,
538 CR4_READ_SHADOW,
539 TSC_OFFSET,
540 EXCEPTION_BITMAP,
541 CPU_BASED_VM_EXEC_CONTROL,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 VM_ENTRY_INTR_INFO_FIELD,
544 VM_ENTRY_INSTRUCTION_LEN,
545 VM_ENTRY_EXCEPTION_ERROR_CODE,
546 HOST_FS_BASE,
547 HOST_GS_BASE,
548 HOST_FS_SELECTOR,
549 HOST_GS_SELECTOR
550};
551static const int max_shadow_read_write_fields =
552 ARRAY_SIZE(shadow_read_write_fields);
553
772e0318 554static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 555 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
556 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
557 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
558 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
559 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
560 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
561 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
562 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
563 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
564 FIELD(HOST_ES_SELECTOR, host_es_selector),
565 FIELD(HOST_CS_SELECTOR, host_cs_selector),
566 FIELD(HOST_SS_SELECTOR, host_ss_selector),
567 FIELD(HOST_DS_SELECTOR, host_ds_selector),
568 FIELD(HOST_FS_SELECTOR, host_fs_selector),
569 FIELD(HOST_GS_SELECTOR, host_gs_selector),
570 FIELD(HOST_TR_SELECTOR, host_tr_selector),
571 FIELD64(IO_BITMAP_A, io_bitmap_a),
572 FIELD64(IO_BITMAP_B, io_bitmap_b),
573 FIELD64(MSR_BITMAP, msr_bitmap),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
577 FIELD64(TSC_OFFSET, tsc_offset),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
579 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
580 FIELD64(EPT_POINTER, ept_pointer),
581 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
582 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
583 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
584 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
585 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
587 FIELD64(GUEST_PDPTR0, guest_pdptr0),
588 FIELD64(GUEST_PDPTR1, guest_pdptr1),
589 FIELD64(GUEST_PDPTR2, guest_pdptr2),
590 FIELD64(GUEST_PDPTR3, guest_pdptr3),
591 FIELD64(HOST_IA32_PAT, host_ia32_pat),
592 FIELD64(HOST_IA32_EFER, host_ia32_efer),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
596 FIELD(EXCEPTION_BITMAP, exception_bitmap),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
599 FIELD(CR3_TARGET_COUNT, cr3_target_count),
600 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
601 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
603 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
608 FIELD(TPR_THRESHOLD, tpr_threshold),
609 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
610 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
611 FIELD(VM_EXIT_REASON, vm_exit_reason),
612 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
613 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
614 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
615 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
616 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
617 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
618 FIELD(GUEST_ES_LIMIT, guest_es_limit),
619 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
620 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
621 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
622 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
623 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
624 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
625 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
626 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
627 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
628 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
629 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
630 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
631 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
632 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
633 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
634 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
635 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
637 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
638 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
639 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 640 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 641 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
642 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
643 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
644 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
645 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
646 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
647 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
648 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
649 FIELD(EXIT_QUALIFICATION, exit_qualification),
650 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
651 FIELD(GUEST_CR0, guest_cr0),
652 FIELD(GUEST_CR3, guest_cr3),
653 FIELD(GUEST_CR4, guest_cr4),
654 FIELD(GUEST_ES_BASE, guest_es_base),
655 FIELD(GUEST_CS_BASE, guest_cs_base),
656 FIELD(GUEST_SS_BASE, guest_ss_base),
657 FIELD(GUEST_DS_BASE, guest_ds_base),
658 FIELD(GUEST_FS_BASE, guest_fs_base),
659 FIELD(GUEST_GS_BASE, guest_gs_base),
660 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
661 FIELD(GUEST_TR_BASE, guest_tr_base),
662 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
663 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
664 FIELD(GUEST_DR7, guest_dr7),
665 FIELD(GUEST_RSP, guest_rsp),
666 FIELD(GUEST_RIP, guest_rip),
667 FIELD(GUEST_RFLAGS, guest_rflags),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
669 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
670 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
671 FIELD(HOST_CR0, host_cr0),
672 FIELD(HOST_CR3, host_cr3),
673 FIELD(HOST_CR4, host_cr4),
674 FIELD(HOST_FS_BASE, host_fs_base),
675 FIELD(HOST_GS_BASE, host_gs_base),
676 FIELD(HOST_TR_BASE, host_tr_base),
677 FIELD(HOST_GDTR_BASE, host_gdtr_base),
678 FIELD(HOST_IDTR_BASE, host_idtr_base),
679 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
680 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
681 FIELD(HOST_RSP, host_rsp),
682 FIELD(HOST_RIP, host_rip),
683};
684static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
685
686static inline short vmcs_field_to_offset(unsigned long field)
687{
688 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
689 return -1;
690 return vmcs_field_to_offset_table[field];
691}
692
a9d30f33
NHE		 693static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
694{
695 return to_vmx(vcpu)->nested.current_vmcs12;
696}
697
698static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
699{
700 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 701 if (is_error_page(page))
a9d30f33 702 return NULL;
32cad84f 703
a9d30f33
NHE		 704 return page;
705}
706
707static void nested_release_page(struct page *page)
708{
709 kvm_release_page_dirty(page);
710}
711
712static void nested_release_page_clean(struct page *page)
713{
714 kvm_release_page_clean(page);
715}
716
bfd0a56b 717static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 718static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 719static void kvm_cpu_vmxon(u64 addr);
720static void kvm_cpu_vmxoff(void);
776e58ea 721static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 722static void vmx_set_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724static void vmx_get_segment(struct kvm_vcpu *vcpu,
725 struct kvm_segment *var, int seg);
d99e4152
GN		 726static bool guest_state_valid(struct kvm_vcpu *vcpu);
727static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 728static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 729static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 730static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 731
6aa8b732
AK		 732static DEFINE_PER_CPU(struct vmcs *, vmxarea);
733static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 734/*
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 */
738static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 739static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 740
3e7c73e9
AK		 741static unsigned long *vmx_io_bitmap_a;
742static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 743static unsigned long *vmx_msr_bitmap_legacy;
744static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 745static unsigned long *vmx_msr_bitmap_legacy_x2apic;
746static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 747static unsigned long *vmx_vmread_bitmap;
748static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 749
110312c8 750static bool cpu_has_load_ia32_efer;
8bf00a52 751static bool cpu_has_load_perf_global_ctrl;
110312c8 752
2384d2b3
SY		 753static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
754static DEFINE_SPINLOCK(vmx_vpid_lock);
755
1c3d14fe 756static struct vmcs_config {
6aa8b732
AK		 757 int size;
758 int order;
759 u32 revision_id;
1c3d14fe
YS		 760 u32 pin_based_exec_ctrl;
761 u32 cpu_based_exec_ctrl;
f78e0e2e 762 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 763 u32 vmexit_ctrl;
764 u32 vmentry_ctrl;
765} vmcs_config;
6aa8b732 766
efff9e53 767static struct vmx_capability {
d56f546d
SY		 768 u32 ept;
769 u32 vpid;
770} vmx_capability;
771
6aa8b732
AK		 772#define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 }
779
772e0318 780static const struct kvm_vmx_segment_field {
6aa8b732
AK		 781 unsigned selector;
782 unsigned base;
783 unsigned limit;
784 unsigned ar_bytes;
785} kvm_vmx_segment_fields[] = {
786 VMX_SEGMENT_FIELD(CS),
787 VMX_SEGMENT_FIELD(DS),
788 VMX_SEGMENT_FIELD(ES),
789 VMX_SEGMENT_FIELD(FS),
790 VMX_SEGMENT_FIELD(GS),
791 VMX_SEGMENT_FIELD(SS),
792 VMX_SEGMENT_FIELD(TR),
793 VMX_SEGMENT_FIELD(LDTR),
794};
795
26bb0981
AK		 796static u64 host_efer;
797
6de4f3ad
AK		 798static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799
4d56c8a7 800/*
8c06585d 801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 802 * away by decrementing the array size.
803 */
6aa8b732 804static const u32 vmx_msr_index[] = {
05b3e0c2 805#ifdef CONFIG_X86_64
44ea2b17 806 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 807#endif
8c06585d 808 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 809};
9d8f549d 810#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 811
31299944 812static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 813{
814 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
815 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 816 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 817}
818
31299944 819static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 824}
825
31299944 826static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 831}
832
31299944 833static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
836 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837}
838
31299944 839static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 847{
04547156 848 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 852{
04547156 853 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 854}
855
31299944 856static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 857{
04547156 858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 859}
860
31299944 861static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 862{
04547156
SY		 863 return vmcs_config.cpu_based_exec_ctrl &
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 865}
866
774ead3a 867static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 868{
04547156
SY		 869 return vmcs_config.cpu_based_2nd_exec_ctrl &
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871}
872
8d14695f
YZ		 873static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874{
875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877}
878
83d4c286
YZ		 879static inline bool cpu_has_vmx_apic_register_virt(void)
880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883}
884
c7c9c56c
YZ		 885static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889}
890
01e439be
YZ		 891static inline bool cpu_has_vmx_posted_intr(void)
892{
893 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894}
895
896static inline bool cpu_has_vmx_apicv(void)
897{
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
901}
902
04547156
SY		 903static inline bool cpu_has_vmx_flexpriority(void)
904{
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 907}
908
e799794e
MT		 909static inline bool cpu_has_vmx_ept_execute_only(void)
910{
31299944 911 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 912}
913
914static inline bool cpu_has_vmx_eptp_uncacheable(void)
915{
31299944 916 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 917}
918
919static inline bool cpu_has_vmx_eptp_writeback(void)
920{
31299944 921 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 922}
923
924static inline bool cpu_has_vmx_ept_2m_page(void)
925{
31299944 926 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 927}
928
878403b7
SY		 929static inline bool cpu_has_vmx_ept_1g_page(void)
930{
31299944 931 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 932}
933
4bc9b982
SY		 934static inline bool cpu_has_vmx_ept_4levels(void)
935{
936 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937}
938
83c3a331
XH		 939static inline bool cpu_has_vmx_ept_ad_bits(void)
940{
941 return vmx_capability.ept & VMX_EPT_AD_BIT;
942}
943
31299944 944static inline bool cpu_has_vmx_invept_context(void)
d56f546d 945{
31299944 946 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 947}
948
31299944 949static inline bool cpu_has_vmx_invept_global(void)
d56f546d 950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 952}
953
518c8aee
GJ		 954static inline bool cpu_has_vmx_invvpid_single(void)
955{
956 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957}
958
b9d762fa
GJ		 959static inline bool cpu_has_vmx_invvpid_global(void)
960{
961 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962}
963
31299944 964static inline bool cpu_has_vmx_ept(void)
d56f546d 965{
04547156
SY		 966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 968}
969
31299944 970static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974}
975
31299944 976static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980}
981
31299944 982static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 983{
6d3e435e 984 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_vpid(void)
2384d2b3 988{
04547156
SY		 989 return vmcs_config.cpu_based_2nd_exec_ctrl &
990 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 991}
992
31299944 993static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 994{
995 return vmcs_config.cpu_based_2nd_exec_ctrl &
996 SECONDARY_EXEC_RDTSCP;
997}
998
ad756a16
MJ		 999static inline bool cpu_has_vmx_invpcid(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_INVPCID;
1003}
1004
31299944 1005static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1006{
1007 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008}
1009
f5f48ee1
SY		 1010static inline bool cpu_has_vmx_wbinvd_exit(void)
1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_WBINVD_EXITING;
1014}
1015
abc4fc58
AG		 1016static inline bool cpu_has_vmx_shadow_vmcs(void)
1017{
1018 u64 vmx_msr;
1019 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return false;
1023
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_SHADOW_VMCS;
1026}
1027
04547156
SY		 1028static inline bool report_flexpriority(void)
1029{
1030 return flexpriority_enabled;
1031}
1032
fe3ef05c
NHE		 1033static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034{
1035 return vmcs12->cpu_based_vm_exec_control & bit;
1036}
1037
1038static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039{
1040 return (vmcs12->cpu_based_vm_exec_control &
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042 (vmcs12->secondary_vm_exec_control & bit);
1043}
1044
f5c4368f 1045static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1062static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063 struct vmcs12 *vmcs12,
1064 u32 reason, unsigned long qualification);
1065
8b9cf98c 1066static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1067{
1068 int i;
1069
a2fa3e9f 1070 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1071 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1072 return i;
1073 return -1;
1074}
1075
2384d2b3
SY		 1076static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077{
1078 struct {
1079 u64 vpid : 16;
1080 u64 rsvd : 48;
1081 u64 gva;
1082 } operand = { vpid, 0, gva };
1083
4ecac3fd 1084 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:"
1087 : : "a"(&operand), "c"(ext) : "cc", "memory");
1088}
1089
1439442c
SY		 1090static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091{
1092 struct {
1093 u64 eptp, gpa;
1094 } operand = {eptp, gpa};
1095
4ecac3fd 1096 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1097 /* CF==1 or ZF==1 --> rc = -1 */
1098 "; ja 1f ; ud2 ; 1:\n"
1099 : : "a" (&operand), "c" (ext) : "cc", "memory");
1100}
1101
26bb0981 1102static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1103{
1104 int i;
1105
8b9cf98c 1106 i = __find_msr_index(vmx, msr);
a75beee6 1107 if (i >= 0)
a2fa3e9f 1108 return &vmx->guest_msrs[i];
8b6d44c7 1109 return NULL;
7725f0ba
AK		 1110}
1111
6aa8b732
AK		 1112static void vmcs_clear(struct vmcs *vmcs)
1113{
1114 u64 phys_addr = __pa(vmcs);
1115 u8 error;
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1118 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1119 : "cc", "memory");
1120 if (error)
1121 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122 vmcs, phys_addr);
1123}
1124
d462b819
NHE		 1125static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126{
1127 vmcs_clear(loaded_vmcs->vmcs);
1128 loaded_vmcs->cpu = -1;
1129 loaded_vmcs->launched = 0;
1130}
1131
7725b894
DX		 1132static void vmcs_load(struct vmcs *vmcs)
1133{
1134 u64 phys_addr = __pa(vmcs);
1135 u8 error;
1136
1137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1138 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1139 : "cc", "memory");
1140 if (error)
2844d849 1141 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1142 vmcs, phys_addr);
1143}
1144
8f536b76
ZY		 1145#ifdef CONFIG_KEXEC
1146/*
1147 * This bitmap is used to indicate whether the vmclear
1148 * operation is enabled on all cpus. All disabled by
1149 * default.
1150 */
1151static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153static inline void crash_enable_local_vmclear(int cpu)
1154{
1155 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156}
1157
1158static inline void crash_disable_local_vmclear(int cpu)
1159{
1160 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161}
1162
1163static inline int crash_local_vmclear_enabled(int cpu)
1164{
1165 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166}
1167
1168static void crash_vmclear_local_loaded_vmcss(void)
1169{
1170 int cpu = raw_smp_processor_id();
1171 struct loaded_vmcs *v;
1172
1173 if (!crash_local_vmclear_enabled(cpu))
1174 return;
1175
1176 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177 loaded_vmcss_on_cpu_link)
1178 vmcs_clear(v->vmcs);
1179}
1180#else
1181static inline void crash_enable_local_vmclear(int cpu) { }
1182static inline void crash_disable_local_vmclear(int cpu) { }
1183#endif /* CONFIG_KEXEC */
1184
d462b819 1185static void __loaded_vmcs_clear(void *arg)
6aa8b732 1186{
d462b819 1187 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1188 int cpu = raw_smp_processor_id();
6aa8b732 1189
d462b819
NHE		 1190 if (loaded_vmcs->cpu != cpu)
1191 return; /* vcpu migration can race with cpu offline */
1192 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1193 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1194 crash_disable_local_vmclear(cpu);
d462b819 1195 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1196
1197 /*
1198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199 * is before setting loaded_vmcs->vcpu to -1 which is done in
1200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201 * then adds the vmcs into percpu list before it is deleted.
1202 */
1203 smp_wmb();
1204
d462b819 1205 loaded_vmcs_init(loaded_vmcs);
8f536b76 1206 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1207}
1208
d462b819 1209static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1210{
e6c7d321
XG		 1211 int cpu = loaded_vmcs->cpu;
1212
1213 if (cpu != -1)
1214 smp_call_function_single(cpu,
1215 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1216}
1217
1760dd49 1218static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1219{
1220 if (vmx->vpid == 0)
1221 return;
1222
518c8aee
GJ		 1223 if (cpu_has_vmx_invvpid_single())
1224 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1225}
1226
b9d762fa
GJ		 1227static inline void vpid_sync_vcpu_global(void)
1228{
1229 if (cpu_has_vmx_invvpid_global())
1230 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231}
1232
1233static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234{
1235 if (cpu_has_vmx_invvpid_single())
1760dd49 1236 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1237 else
1238 vpid_sync_vcpu_global();
1239}
1240
1439442c
SY		 1241static inline void ept_sync_global(void)
1242{
1243 if (cpu_has_vmx_invept_global())
1244 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245}
1246
1247static inline void ept_sync_context(u64 eptp)
1248{
089d034e 1249 if (enable_ept) {
1439442c
SY		 1250 if (cpu_has_vmx_invept_context())
1251 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252 else
1253 ept_sync_global();
1254 }
1255}
1256
96304217 1257static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1258{
5e520e62 1259 unsigned long value;
6aa8b732 1260
5e520e62
AK		 1261 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1263 return value;
1264}
1265
96304217 1266static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1267{
1268 return vmcs_readl(field);
1269}
1270
96304217 1271static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1272{
1273 return vmcs_readl(field);
1274}
1275
96304217 1276static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1277{
05b3e0c2 1278#ifdef CONFIG_X86_64
6aa8b732
AK		 1279 return vmcs_readl(field);
1280#else
1281 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282#endif
1283}
1284
e52de1b8
AK		 1285static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286{
1287 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289 dump_stack();
1290}
1291
6aa8b732
AK		 1292static void vmcs_writel(unsigned long field, unsigned long value)
1293{
1294 u8 error;
1295
4ecac3fd 1296 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1297 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1298 if (unlikely(error))
1299 vmwrite_error(field, value);
6aa8b732
AK		 1300}
1301
1302static void vmcs_write16(unsigned long field, u16 value)
1303{
1304 vmcs_writel(field, value);
1305}
1306
1307static void vmcs_write32(unsigned long field, u32 value)
1308{
1309 vmcs_writel(field, value);
1310}
1311
1312static void vmcs_write64(unsigned long field, u64 value)
1313{
6aa8b732 1314 vmcs_writel(field, value);
7682f2d0 1315#ifndef CONFIG_X86_64
6aa8b732
AK		 1316 asm volatile ("");
1317 vmcs_writel(field+1, value >> 32);
1318#endif
1319}
1320
2ab455cc
AL		 1321static void vmcs_clear_bits(unsigned long field, u32 mask)
1322{
1323 vmcs_writel(field, vmcs_readl(field) & ~mask);
1324}
1325
1326static void vmcs_set_bits(unsigned long field, u32 mask)
1327{
1328 vmcs_writel(field, vmcs_readl(field) | mask);
1329}
1330
2961e876
GN		 1331static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1332{
1333 vmcs_write32(VM_ENTRY_CONTROLS, val);
1334 vmx->vm_entry_controls_shadow = val;
1335}
1336
1337static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1338{
1339 if (vmx->vm_entry_controls_shadow != val)
1340 vm_entry_controls_init(vmx, val);
1341}
1342
1343static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1344{
1345 return vmx->vm_entry_controls_shadow;
1346}
1347
1348
1349static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1350{
1351 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1352}
1353
1354static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1355{
1356 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1357}
1358
1359static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1360{
1361 vmcs_write32(VM_EXIT_CONTROLS, val);
1362 vmx->vm_exit_controls_shadow = val;
1363}
1364
1365static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1366{
1367 if (vmx->vm_exit_controls_shadow != val)
1368 vm_exit_controls_init(vmx, val);
1369}
1370
1371static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1372{
1373 return vmx->vm_exit_controls_shadow;
1374}
1375
1376
1377static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1378{
1379 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1380}
1381
1382static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1385}
1386
2fb92db1
AK		 1387static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1388{
1389 vmx->segment_cache.bitmask = 0;
1390}
1391
1392static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1393 unsigned field)
1394{
1395 bool ret;
1396 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1397
1398 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1399 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1400 vmx->segment_cache.bitmask = 0;
1401 }
1402 ret = vmx->segment_cache.bitmask & mask;
1403 vmx->segment_cache.bitmask |= mask;
1404 return ret;
1405}
1406
1407static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1408{
1409 u16 *p = &vmx->segment_cache.seg[seg].selector;
1410
1411 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1412 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1413 return *p;
1414}
1415
1416static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1417{
1418 ulong *p = &vmx->segment_cache.seg[seg].base;
1419
1420 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1421 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1422 return *p;
1423}
1424
1425static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1426{
1427 u32 *p = &vmx->segment_cache.seg[seg].limit;
1428
1429 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1430 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1431 return *p;
1432}
1433
1434static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1435{
1436 u32 *p = &vmx->segment_cache.seg[seg].ar;
1437
1438 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1439 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1440 return *p;
1441}
1442
abd3f2d6
AK		 1443static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1444{
1445 u32 eb;
1446
fd7373cc
JK		 1447 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1448 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1449 if ((vcpu->guest_debug &
1450 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1451 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1452 eb |= 1u << BP_VECTOR;
7ffd92c5 1453 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1454 eb = ~0;
089d034e 1455 if (enable_ept)
1439442c 1456 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1457 if (vcpu->fpu_active)
1458 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1459
1460 /* When we are running a nested L2 guest and L1 specified for it a
1461 * certain exception bitmap, we must trap the same exceptions and pass
1462 * them to L1. When running L2, we will only handle the exceptions
1463 * specified above if L1 did not want them.
1464 */
1465 if (is_guest_mode(vcpu))
1466 eb |= get_vmcs12(vcpu)->exception_bitmap;
1467
abd3f2d6
AK		 1468 vmcs_write32(EXCEPTION_BITMAP, eb);
1469}
1470
2961e876
GN		 1471static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1472 unsigned long entry, unsigned long exit)
8bf00a52 1473{
2961e876
GN		 1474 vm_entry_controls_clearbit(vmx, entry);
1475 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1476}
1477
61d2ef2c
AK		 1478static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1479{
1480 unsigned i;
1481 struct msr_autoload *m = &vmx->msr_autoload;
1482
8bf00a52
GN		 1483 switch (msr) {
1484 case MSR_EFER:
1485 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1486 clear_atomic_switch_msr_special(vmx,
1487 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1488 VM_EXIT_LOAD_IA32_EFER);
1489 return;
1490 }
1491 break;
1492 case MSR_CORE_PERF_GLOBAL_CTRL:
1493 if (cpu_has_load_perf_global_ctrl) {
2961e876 1494 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1495 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1496 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1497 return;
1498 }
1499 break;
110312c8
AK		 1500 }
1501
61d2ef2c
AK		 1502 for (i = 0; i < m->nr; ++i)
1503 if (m->guest[i].index == msr)
1504 break;
1505
1506 if (i == m->nr)
1507 return;
1508 --m->nr;
1509 m->guest[i] = m->guest[m->nr];
1510 m->host[i] = m->host[m->nr];
1511 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1512 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1513}
1514
2961e876
GN		 1515static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1516 unsigned long entry, unsigned long exit,
1517 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1518 u64 guest_val, u64 host_val)
8bf00a52
GN		 1519{
1520 vmcs_write64(guest_val_vmcs, guest_val);
1521 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1522 vm_entry_controls_setbit(vmx, entry);
1523 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1524}
1525
61d2ef2c
AK		 1526static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1527 u64 guest_val, u64 host_val)
1528{
1529 unsigned i;
1530 struct msr_autoload *m = &vmx->msr_autoload;
1531
8bf00a52
GN		 1532 switch (msr) {
1533 case MSR_EFER:
1534 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1535 add_atomic_switch_msr_special(vmx,
1536 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1537 VM_EXIT_LOAD_IA32_EFER,
1538 GUEST_IA32_EFER,
1539 HOST_IA32_EFER,
1540 guest_val, host_val);
1541 return;
1542 }
1543 break;
1544 case MSR_CORE_PERF_GLOBAL_CTRL:
1545 if (cpu_has_load_perf_global_ctrl) {
2961e876 1546 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1547 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1548 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1549 GUEST_IA32_PERF_GLOBAL_CTRL,
1550 HOST_IA32_PERF_GLOBAL_CTRL,
1551 guest_val, host_val);
1552 return;
1553 }
1554 break;
110312c8
AK		 1555 }
1556
61d2ef2c
AK		 1557 for (i = 0; i < m->nr; ++i)
1558 if (m->guest[i].index == msr)
1559 break;
1560
e7fc6f93 1561 if (i == NR_AUTOLOAD_MSRS) {
60266204 1562 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1563 "Can't add msr %x\n", msr);
1564 return;
1565 } else if (i == m->nr) {
61d2ef2c
AK		 1566 ++m->nr;
1567 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1568 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1569 }
1570
1571 m->guest[i].index = msr;
1572 m->guest[i].value = guest_val;
1573 m->host[i].index = msr;
1574 m->host[i].value = host_val;
1575}
1576
33ed6329
AK		 1577static void reload_tss(void)
1578{
33ed6329
AK		 1579 /*
1580 * VT restores TR but not its size. Useless.
1581 */
d359192f 1582 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1583 struct desc_struct *descs;
33ed6329 1584
d359192f 1585 descs = (void *)gdt->address;
33ed6329
AK		 1586 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1587 load_TR_desc();
33ed6329
AK		 1588}
1589
92c0d900 1590static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1591{
3a34a881 1592 u64 guest_efer;
51c6cf66
AK		 1593 u64 ignore_bits;
1594
f6801dff 1595 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1596
51c6cf66 1597 /*
0fa06071 1598 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1599 * outside long mode
1600 */
1601 ignore_bits = EFER_NX | EFER_SCE;
1602#ifdef CONFIG_X86_64
1603 ignore_bits |= EFER_LMA | EFER_LME;
1604 /* SCE is meaningful only in long mode on Intel */
1605 if (guest_efer & EFER_LMA)
1606 ignore_bits &= ~(u64)EFER_SCE;
1607#endif
51c6cf66
AK		 1608 guest_efer &= ~ignore_bits;
1609 guest_efer |= host_efer & ignore_bits;
26bb0981 1610 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1611 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1612
1613 clear_atomic_switch_msr(vmx, MSR_EFER);
1614 /* On ept, can't emulate nx, and must switch nx atomically */
1615 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1616 guest_efer = vmx->vcpu.arch.efer;
1617 if (!(guest_efer & EFER_LMA))
1618 guest_efer &= ~EFER_LME;
1619 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1620 return false;
1621 }
1622
26bb0981 1623 return true;
51c6cf66
AK		 1624}
1625
2d49ec72
GN		 1626static unsigned long segment_base(u16 selector)
1627{
d359192f 1628 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1629 struct desc_struct *d;
1630 unsigned long table_base;
1631 unsigned long v;
1632
1633 if (!(selector & ~3))
1634 return 0;
1635
d359192f 1636 table_base = gdt->address;
2d49ec72
GN		 1637
1638 if (selector & 4) { /* from ldt */
1639 u16 ldt_selector = kvm_read_ldt();
1640
1641 if (!(ldt_selector & ~3))
1642 return 0;
1643
1644 table_base = segment_base(ldt_selector);
1645 }
1646 d = (struct desc_struct *)(table_base + (selector & ~7));
1647 v = get_desc_base(d);
1648#ifdef CONFIG_X86_64
1649 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1650 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1651#endif
1652 return v;
1653}
1654
1655static inline unsigned long kvm_read_tr_base(void)
1656{
1657 u16 tr;
1658 asm("str %0" : "=g"(tr));
1659 return segment_base(tr);
1660}
1661
04d2cc77 1662static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1663{
04d2cc77 1664 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1665 int i;
04d2cc77 1666
a2fa3e9f 1667 if (vmx->host_state.loaded)
33ed6329
AK		 1668 return;
1669
a2fa3e9f 1670 vmx->host_state.loaded = 1;
33ed6329
AK		 1671 /*
1672 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1673 * allow segment selectors with cpl > 0 or ti == 1.
1674 */
d6e88aec 1675 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1676 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1677 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1678 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1679 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1680 vmx->host_state.fs_reload_needed = 0;
1681 } else {
33ed6329 1682 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1683 vmx->host_state.fs_reload_needed = 1;
33ed6329 1684 }
9581d442 1685 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1686 if (!(vmx->host_state.gs_sel & 7))
1687 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1688 else {
1689 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1690 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1691 }
1692
b2da15ac
AK		 1693#ifdef CONFIG_X86_64
1694 savesegment(ds, vmx->host_state.ds_sel);
1695 savesegment(es, vmx->host_state.es_sel);
1696#endif
1697
33ed6329
AK		 1698#ifdef CONFIG_X86_64
1699 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1700 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1701#else
a2fa3e9f
GH		 1702 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1703 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1704#endif
707c0874
AK		 1705
1706#ifdef CONFIG_X86_64
c8770e7b
AK		 1707 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1708 if (is_long_mode(&vmx->vcpu))
44ea2b17 1709 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1710#endif
26bb0981
AK		 1711 for (i = 0; i < vmx->save_nmsrs; ++i)
1712 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1713 vmx->guest_msrs[i].data,
1714 vmx->guest_msrs[i].mask);
33ed6329
AK		 1715}
1716
a9b21b62 1717static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1718{
a2fa3e9f 1719 if (!vmx->host_state.loaded)
33ed6329
AK		 1720 return;
1721
e1beb1d3 1722 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1723 vmx->host_state.loaded = 0;
c8770e7b
AK		 1724#ifdef CONFIG_X86_64
1725 if (is_long_mode(&vmx->vcpu))
1726 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1727#endif
152d3f2f 1728 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1729 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1730#ifdef CONFIG_X86_64
9581d442 1731 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1732#else
1733 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1734#endif
33ed6329 1735 }
0a77fe4c
AK		 1736 if (vmx->host_state.fs_reload_needed)
1737 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1738#ifdef CONFIG_X86_64
1739 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1740 loadsegment(ds, vmx->host_state.ds_sel);
1741 loadsegment(es, vmx->host_state.es_sel);
1742 }
b2da15ac 1743#endif
152d3f2f 1744 reload_tss();
44ea2b17 1745#ifdef CONFIG_X86_64
c8770e7b 1746 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1747#endif
b1a74bf8
SS		 1748 /*
1749 * If the FPU is not active (through the host task or
1750 * the guest vcpu), then restore the cr0.TS bit.
1751 */
1752 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1753 stts();
3444d7da 1754 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1755}
1756
a9b21b62
AK		 1757static void vmx_load_host_state(struct vcpu_vmx *vmx)
1758{
1759 preempt_disable();
1760 __vmx_load_host_state(vmx);
1761 preempt_enable();
1762}
1763
6aa8b732
AK		 1764/*
1765 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1766 * vcpu mutex is already taken.
1767 */
15ad7146 1768static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1769{
a2fa3e9f 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1771 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1772
4610c9cc
DX		 1773 if (!vmm_exclusive)
1774 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1775 else if (vmx->loaded_vmcs->cpu != cpu)
1776 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1777
d462b819
NHE		 1778 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1779 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1780 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1781 }
1782
d462b819 1783 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1784 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1785 unsigned long sysenter_esp;
1786
a8eeb04a 1787 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1788 local_irq_disable();
8f536b76 1789 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1790
1791 /*
1792 * Read loaded_vmcs->cpu should be before fetching
1793 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1794 * See the comments in __loaded_vmcs_clear().
1795 */
1796 smp_rmb();
1797
d462b819
NHE		 1798 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1799 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1800 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1801 local_irq_enable();
1802
6aa8b732
AK		 1803 /*
1804 * Linux uses per-cpu TSS and GDT, so set these when switching
1805 * processors.
1806 */
d6e88aec 1807 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1808 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1809
1810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1812 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1813 }
6aa8b732
AK		 1814}
1815
1816static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1817{
a9b21b62 1818 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1819 if (!vmm_exclusive) {
d462b819
NHE		 1820 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1821 vcpu->cpu = -1;
4610c9cc
DX		 1822 kvm_cpu_vmxoff();
1823 }
6aa8b732
AK		 1824}
1825
5fd86fcf
AK		 1826static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1827{
81231c69
AK		 1828 ulong cr0;
1829
5fd86fcf
AK		 1830 if (vcpu->fpu_active)
1831 return;
1832 vcpu->fpu_active = 1;
81231c69
AK		 1833 cr0 = vmcs_readl(GUEST_CR0);
1834 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1835 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1836 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1837 update_exception_bitmap(vcpu);
edcafe3c 1838 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1839 if (is_guest_mode(vcpu))
1840 vcpu->arch.cr0_guest_owned_bits &=
1841 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1842 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1843}
1844
edcafe3c
AK		 1845static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1846
fe3ef05c
NHE		 1847/*
1848 * Return the cr0 value that a nested guest would read. This is a combination
1849 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1850 * its hypervisor (cr0_read_shadow).
1851 */
1852static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1853{
1854 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1855 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1856}
1857static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1858{
1859 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1860 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1861}
1862
5fd86fcf
AK		 1863static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1864{
36cf24e0
NHE		 1865 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1866 * set this *before* calling this function.
1867 */
edcafe3c 1868 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1869 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1870 update_exception_bitmap(vcpu);
edcafe3c
AK		 1871 vcpu->arch.cr0_guest_owned_bits = 0;
1872 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1873 if (is_guest_mode(vcpu)) {
1874 /*
1875 * L1's specified read shadow might not contain the TS bit,
1876 * so now that we turned on shadowing of this bit, we need to
1877 * set this bit of the shadow. Like in nested_vmx_run we need
1878 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1879 * up-to-date here because we just decached cr0.TS (and we'll
1880 * only update vmcs12->guest_cr0 on nested exit).
1881 */
1882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1883 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1884 (vcpu->arch.cr0 & X86_CR0_TS);
1885 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1886 } else
1887 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1888}
1889
6aa8b732
AK		 1890static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1891{
78ac8b47 1892 unsigned long rflags, save_rflags;
345dcaa8 1893
6de12732
AK		 1894 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1895 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1896 rflags = vmcs_readl(GUEST_RFLAGS);
1897 if (to_vmx(vcpu)->rmode.vm86_active) {
1898 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1899 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1900 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1901 }
1902 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1903 }
6de12732 1904 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1905}
1906
1907static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1908{
6de12732
AK		 1909 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1910 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1911 if (to_vmx(vcpu)->rmode.vm86_active) {
1912 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1913 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1914 }
6aa8b732
AK		 1915 vmcs_writel(GUEST_RFLAGS, rflags);
1916}
1917
2809f5d2
GC		 1918static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1919{
1920 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1921 int ret = 0;
1922
1923 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1924 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1925 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1926 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1927
1928 return ret & mask;
1929}
1930
1931static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1932{
1933 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1934 u32 interruptibility = interruptibility_old;
1935
1936 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1937
48005f64 1938 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1939 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1940 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1941 interruptibility |= GUEST_INTR_STATE_STI;
1942
1943 if ((interruptibility != interruptibility_old))
1944 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1945}
1946
6aa8b732
AK		 1947static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1948{
1949 unsigned long rip;
6aa8b732 1950
5fdbf976 1951 rip = kvm_rip_read(vcpu);
6aa8b732 1952 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1953 kvm_rip_write(vcpu, rip);
6aa8b732 1954
2809f5d2
GC		 1955 /* skipping an emulated instruction also counts */
1956 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1957}
1958
0b6ac343
NHE		 1959/*
1960 * KVM wants to inject page-faults which it got to the guest. This function
1961 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1962 */
e011c663 1963static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1964{
1965 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1966
e011c663 1967 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1968 return 0;
1969
1970 nested_vmx_vmexit(vcpu);
1971 return 1;
1972}
1973
298101da 1974static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1975 bool has_error_code, u32 error_code,
1976 bool reinject)
298101da 1977{
77ab6db0 1978 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1979 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1980
e011c663
GN		 1981 if (!reinject && is_guest_mode(vcpu) &&
1982 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1983 return;
1984
8ab2d2e2 1985 if (has_error_code) {
77ab6db0 1986 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1987 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1988 }
77ab6db0 1989
7ffd92c5 1990 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1991 int inc_eip = 0;
1992 if (kvm_exception_is_soft(nr))
1993 inc_eip = vcpu->arch.event_exit_inst_len;
1994 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1996 return;
1997 }
1998
66fd3f7f
GN		 1999 if (kvm_exception_is_soft(nr)) {
2000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2001 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2002 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2003 } else
2004 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2005
2006 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2007}
2008
4e47c7a6
SY		 2009static bool vmx_rdtscp_supported(void)
2010{
2011 return cpu_has_vmx_rdtscp();
2012}
2013
ad756a16
MJ		 2014static bool vmx_invpcid_supported(void)
2015{
2016 return cpu_has_vmx_invpcid() && enable_ept;
2017}
2018
a75beee6
ED		 2019/*
2020 * Swap MSR entry in host/guest MSR entry array.
2021 */
8b9cf98c 2022static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2023{
26bb0981 2024 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2025
2026 tmp = vmx->guest_msrs[to];
2027 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2028 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2029}
2030
8d14695f
YZ		 2031static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2032{
2033 unsigned long *msr_bitmap;
2034
2035 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2036 if (is_long_mode(vcpu))
2037 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2038 else
2039 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2040 } else {
2041 if (is_long_mode(vcpu))
2042 msr_bitmap = vmx_msr_bitmap_longmode;
2043 else
2044 msr_bitmap = vmx_msr_bitmap_legacy;
2045 }
2046
2047 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2048}
2049
e38aea3e
AK		 2050/*
2051 * Set up the vmcs to automatically save and restore system
2052 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2053 * mode, as fiddling with msrs is very expensive.
2054 */
8b9cf98c 2055static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2056{
26bb0981 2057 int save_nmsrs, index;
e38aea3e 2058
a75beee6
ED		 2059 save_nmsrs = 0;
2060#ifdef CONFIG_X86_64
8b9cf98c 2061 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2062 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2063 if (index >= 0)
8b9cf98c
RR		 2064 move_msr_up(vmx, index, save_nmsrs++);
2065 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2066 if (index >= 0)
8b9cf98c
RR		 2067 move_msr_up(vmx, index, save_nmsrs++);
2068 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2069 if (index >= 0)
8b9cf98c 2070 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2071 index = __find_msr_index(vmx, MSR_TSC_AUX);
2072 if (index >= 0 && vmx->rdtscp_enabled)
2073 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2074 /*
8c06585d 2075 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2076 * if efer.sce is enabled.
2077 */
8c06585d 2078 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2079 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2080 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2081 }
2082#endif
92c0d900
AK		 2083 index = __find_msr_index(vmx, MSR_EFER);
2084 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2085 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2086
26bb0981 2087 vmx->save_nmsrs = save_nmsrs;
5897297b 2088
8d14695f
YZ		 2089 if (cpu_has_vmx_msr_bitmap())
2090 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2091}
2092
6aa8b732
AK		 2093/*
2094 * reads and returns guest's timestamp counter "register"
2095 * guest_tsc = host_tsc + tsc_offset -- 21.3
2096 */
2097static u64 guest_read_tsc(void)
2098{
2099 u64 host_tsc, tsc_offset;
2100
2101 rdtscll(host_tsc);
2102 tsc_offset = vmcs_read64(TSC_OFFSET);
2103 return host_tsc + tsc_offset;
2104}
2105
d5c1785d
NHE		 2106/*
2107 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2108 * counter, even if a nested guest (L2) is currently running.
2109 */
886b470c 2110u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2111{
886b470c 2112 u64 tsc_offset;
d5c1785d 2113
d5c1785d
NHE		 2114 tsc_offset = is_guest_mode(vcpu) ?
2115 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2116 vmcs_read64(TSC_OFFSET);
2117 return host_tsc + tsc_offset;
2118}
2119
4051b188 2120/*
cc578287
ZA		 2121 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2122 * software catchup for faster rates on slower CPUs.
4051b188 2123 */
cc578287 2124static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2125{
cc578287
ZA		 2126 if (!scale)
2127 return;
2128
2129 if (user_tsc_khz > tsc_khz) {
2130 vcpu->arch.tsc_catchup = 1;
2131 vcpu->arch.tsc_always_catchup = 1;
2132 } else
2133 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2134}
2135
ba904635
WA		 2136static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2137{
2138 return vmcs_read64(TSC_OFFSET);
2139}
2140
6aa8b732 2141/*
99e3e30a 2142 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2143 */
99e3e30a 2144static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2145{
27fc51b2 2146 if (is_guest_mode(vcpu)) {
7991825b 2147 /*
27fc51b2
NHE		 2148 * We're here if L1 chose not to trap WRMSR to TSC. According
2149 * to the spec, this should set L1's TSC; The offset that L1
2150 * set for L2 remains unchanged, and still needs to be added
2151 * to the newly set TSC to get L2's TSC.
7991825b 2152 */
27fc51b2
NHE		 2153 struct vmcs12 *vmcs12;
2154 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2155 /* recalculate vmcs02.TSC_OFFSET: */
2156 vmcs12 = get_vmcs12(vcpu);
2157 vmcs_write64(TSC_OFFSET, offset +
2158 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2159 vmcs12->tsc_offset : 0));
2160 } else {
489223ed
YY		 2161 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2162 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2163 vmcs_write64(TSC_OFFSET, offset);
2164 }
6aa8b732
AK		 2165}
2166
f1e2b260 2167static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2168{
2169 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2170
e48672fa 2171 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2172 if (is_guest_mode(vcpu)) {
2173 /* Even when running L2, the adjustment needs to apply to L1 */
2174 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2175 } else
2176 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2177 offset + adjustment);
e48672fa
ZA		 2178}
2179
857e4099
JR		 2180static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2181{
2182 return target_tsc - native_read_tsc();
2183}
2184
801d3424
NHE		 2185static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2186{
2187 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2188 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2189}
2190
2191/*
2192 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2193 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2194 * all guests if the "nested" module option is off, and can also be disabled
2195 * for a single guest by disabling its VMX cpuid bit.
2196 */
2197static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2198{
2199 return nested && guest_cpuid_has_vmx(vcpu);
2200}
2201
b87a51ae
NHE		 2202/*
2203 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2204 * returned for the various VMX controls MSRs when nested VMX is enabled.
2205 * The same values should also be used to verify that vmcs12 control fields are
2206 * valid during nested entry from L1 to L2.
2207 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2208 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2209 * bit in the high half is on if the corresponding bit in the control field
2210 * may be on. See also vmx_control_verify().
2211 * TODO: allow these variables to be modified (downgraded) by module options
2212 * or other means.
2213 */
2214static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2215static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2216static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2217static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2218static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2219static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2220static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2221static __init void nested_vmx_setup_ctls_msrs(void)
2222{
2223 /*
2224 * Note that as a general rule, the high half of the MSRs (bits in
2225 * the control fields which may be 1) should be initialized by the
2226 * intersection of the underlying hardware's MSR (i.e., features which
2227 * can be supported) and the list of features we want to expose -
2228 * because they are known to be properly supported in our code.
2229 * Also, usually, the low half of the MSRs (bits which must be 1) can
2230 * be set to 0, meaning that L1 may turn off any of these bits. The
2231 * reason is that if one of these bits is necessary, it will appear
2232 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2233 * fields of vmcs01 and vmcs02, will turn these bits off - and
2234 * nested_vmx_exit_handled() will not pass related exits to L1.
2235 * These rules have exceptions below.
2236 */
2237
2238 /* pin-based controls */
eabeaacc
JK		 2239 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2240 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2241 /*
2242 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2243 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2244 */
eabeaacc
JK		 2245 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2246 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2247 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2248 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2249 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2250
33fb20c3
JK		 2251 /*
2252 * Exit controls
2253 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2254 * 17 must be 1.
2255 */
c0dfee58
ACL		 2256 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2257 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2258 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2259 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2260 nested_vmx_exit_ctls_high &=
b87a51ae 2261#ifdef CONFIG_X86_64
c0dfee58 2262 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2263#endif
7854cbca
ACL		 2264 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2265 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2266 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2267 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2268 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2269 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2270 }
8049d651 2271 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2272 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2273
2274 /* entry controls */
2275 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2276 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2277 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2278 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2279 nested_vmx_entry_ctls_high &=
57435349
JK		 2280#ifdef CONFIG_X86_64
2281 VM_ENTRY_IA32E_MODE |
2282#endif
2283 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2284 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2285 VM_ENTRY_LOAD_IA32_EFER);
57435349 2286
b87a51ae
NHE		 2287 /* cpu-based controls */
2288 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2289 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2290 nested_vmx_procbased_ctls_low = 0;
2291 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2292 CPU_BASED_VIRTUAL_INTR_PENDING |
2293 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2294 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2295 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2296 CPU_BASED_CR3_STORE_EXITING |
2297#ifdef CONFIG_X86_64
2298 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2299#endif
2300 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2301 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2302 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2303 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2304 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2305 /*
2306 * We can allow some features even when not supported by the
2307 * hardware. For example, L1 can specify an MSR bitmap - and we
2308 * can use it to avoid exits to L1 - even when L0 runs L2
2309 * without MSR bitmaps.
2310 */
2311 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2312
2313 /* secondary cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2315 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2316 nested_vmx_secondary_ctls_low = 0;
2317 nested_vmx_secondary_ctls_high &=
d6851fbe 2318 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2319 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2320 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2321
afa61f75
NHE		 2322 if (enable_ept) {
2323 /* nested EPT: emulate EPT also to L1 */
2324 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2325 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2326 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2327 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2328 nested_vmx_ept_caps &= vmx_capability.ept;
2329 /*
2330 * Since invept is completely emulated we support both global
2331 * and context invalidation independent of what host cpu
2332 * supports
2333 */
2334 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2335 VMX_EPT_EXTENT_CONTEXT_BIT;
2336 } else
2337 nested_vmx_ept_caps = 0;
2338
c18911a2
JK		 2339 /* miscellaneous data */
2340 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2341 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2342 VMX_MISC_SAVE_EFER_LMA;
6dfacadd 2343 nested_vmx_misc_low |= VMX_MISC_ACTIVITY_HLT;
c18911a2 2344 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2345}
2346
2347static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2348{
2349 /*
2350 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2351 */
2352 return ((control & high) | low) == control;
2353}
2354
2355static inline u64 vmx_control_msr(u32 low, u32 high)
2356{
2357 return low | ((u64)high << 32);
2358}
2359
2360/*
2361 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2362 * also let it use VMX-specific MSRs.
2363 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2364 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2365 * like all other MSRs).
2366 */
2367static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2368{
2369 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2370 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2371 /*
2372 * According to the spec, processors which do not support VMX
2373 * should throw a #GP(0) when VMX capability MSRs are read.
2374 */
2375 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2376 return 1;
2377 }
2378
2379 switch (msr_index) {
2380 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2381 if (nested_vmx_allowed(vcpu)) {
2382 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2383 break;
2384 }
2385 return 0;
b87a51ae
NHE		 2386 case MSR_IA32_VMX_BASIC:
2387 /*
2388 * This MSR reports some information about VMX support. We
2389 * should return information about the VMX we emulate for the
2390 * guest, and the VMCS structure we give it - not about the
2391 * VMX support of the underlying hardware.
2392 */
2393 *pdata = VMCS12_REVISION |
2394 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2395 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2396 break;
2397 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2398 case MSR_IA32_VMX_PINBASED_CTLS:
2399 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2400 nested_vmx_pinbased_ctls_high);
2401 break;
2402 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2403 case MSR_IA32_VMX_PROCBASED_CTLS:
2404 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2405 nested_vmx_procbased_ctls_high);
2406 break;
2407 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2408 case MSR_IA32_VMX_EXIT_CTLS:
2409 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2410 nested_vmx_exit_ctls_high);
2411 break;
2412 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2413 case MSR_IA32_VMX_ENTRY_CTLS:
2414 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2415 nested_vmx_entry_ctls_high);
2416 break;
2417 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2418 *pdata = vmx_control_msr(nested_vmx_misc_low,
2419 nested_vmx_misc_high);
b87a51ae
NHE		 2420 break;
2421 /*
2422 * These MSRs specify bits which the guest must keep fixed (on or off)
2423 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2424 * We picked the standard core2 setting.
2425 */
2426#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2427#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2428 case MSR_IA32_VMX_CR0_FIXED0:
2429 *pdata = VMXON_CR0_ALWAYSON;
2430 break;
2431 case MSR_IA32_VMX_CR0_FIXED1:
2432 *pdata = -1ULL;
2433 break;
2434 case MSR_IA32_VMX_CR4_FIXED0:
2435 *pdata = VMXON_CR4_ALWAYSON;
2436 break;
2437 case MSR_IA32_VMX_CR4_FIXED1:
2438 *pdata = -1ULL;
2439 break;
2440 case MSR_IA32_VMX_VMCS_ENUM:
2441 *pdata = 0x1f;
2442 break;
2443 case MSR_IA32_VMX_PROCBASED_CTLS2:
2444 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2445 nested_vmx_secondary_ctls_high);
2446 break;
2447 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2448 /* Currently, no nested vpid support */
2449 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2450 break;
2451 default:
2452 return 0;
2453 }
2454
2455 return 1;
2456}
2457
b3897a49 2458static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2459{
b3897a49
NHE		 2460 u32 msr_index = msr_info->index;
2461 u64 data = msr_info->data;
2462 bool host_initialized = msr_info->host_initiated;
2463
b87a51ae
NHE		 2464 if (!nested_vmx_allowed(vcpu))
2465 return 0;
2466
b3897a49
NHE		 2467 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2468 if (!host_initialized &&
2469 to_vmx(vcpu)->nested.msr_ia32_feature_control
2470 & FEATURE_CONTROL_LOCKED)
2471 return 0;
2472 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2473 return 1;
b3897a49
NHE		 2474 }
2475
b87a51ae
NHE		 2476 /*
2477 * No need to treat VMX capability MSRs specially: If we don't handle
2478 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2479 */
2480 return 0;
2481}
2482
6aa8b732
AK		 2483/*
2484 * Reads an msr value (of 'msr_index') into 'pdata'.
2485 * Returns 0 on success, non-0 otherwise.
2486 * Assumes vcpu_load() was already called.
2487 */
2488static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2489{
2490 u64 data;
26bb0981 2491 struct shared_msr_entry *msr;
6aa8b732
AK		 2492
2493 if (!pdata) {
2494 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2495 return -EINVAL;
2496 }
2497
2498 switch (msr_index) {
05b3e0c2 2499#ifdef CONFIG_X86_64
6aa8b732
AK		 2500 case MSR_FS_BASE:
2501 data = vmcs_readl(GUEST_FS_BASE);
2502 break;
2503 case MSR_GS_BASE:
2504 data = vmcs_readl(GUEST_GS_BASE);
2505 break;
44ea2b17
AK		 2506 case MSR_KERNEL_GS_BASE:
2507 vmx_load_host_state(to_vmx(vcpu));
2508 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2509 break;
26bb0981 2510#endif
6aa8b732 2511 case MSR_EFER:
3bab1f5d 2512 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2513 case MSR_IA32_TSC:
6aa8b732
AK		 2514 data = guest_read_tsc();
2515 break;
2516 case MSR_IA32_SYSENTER_CS:
2517 data = vmcs_read32(GUEST_SYSENTER_CS);
2518 break;
2519 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2520 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2521 break;
2522 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2523 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2524 break;
4e47c7a6
SY		 2525 case MSR_TSC_AUX:
2526 if (!to_vmx(vcpu)->rdtscp_enabled)
2527 return 1;
2528 /* Otherwise falls through */
6aa8b732 2529 default:
b87a51ae
NHE		 2530 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2531 return 0;
8b9cf98c 2532 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2533 if (msr) {
2534 data = msr->data;
2535 break;
6aa8b732 2536 }
3bab1f5d 2537 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2538 }
2539
2540 *pdata = data;
2541 return 0;
2542}
2543
2544/*
2545 * Writes msr value into into the appropriate "register".
2546 * Returns 0 on success, non-0 otherwise.
2547 * Assumes vcpu_load() was already called.
2548 */
8fe8ab46 2549static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2550{
a2fa3e9f 2551 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2552 struct shared_msr_entry *msr;
2cc51560 2553 int ret = 0;
8fe8ab46
WA		 2554 u32 msr_index = msr_info->index;
2555 u64 data = msr_info->data;
2cc51560 2556
6aa8b732 2557 switch (msr_index) {
3bab1f5d 2558 case MSR_EFER:
8fe8ab46 2559 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2560 break;
16175a79 2561#ifdef CONFIG_X86_64
6aa8b732 2562 case MSR_FS_BASE:
2fb92db1 2563 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2564 vmcs_writel(GUEST_FS_BASE, data);
2565 break;
2566 case MSR_GS_BASE:
2fb92db1 2567 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2568 vmcs_writel(GUEST_GS_BASE, data);
2569 break;
44ea2b17
AK		 2570 case MSR_KERNEL_GS_BASE:
2571 vmx_load_host_state(vmx);
2572 vmx->msr_guest_kernel_gs_base = data;
2573 break;
6aa8b732
AK		 2574#endif
2575 case MSR_IA32_SYSENTER_CS:
2576 vmcs_write32(GUEST_SYSENTER_CS, data);
2577 break;
2578 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2579 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2580 break;
2581 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2582 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2583 break;
af24a4e4 2584 case MSR_IA32_TSC:
8fe8ab46 2585 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2586 break;
468d472f
SY		 2587 case MSR_IA32_CR_PAT:
2588 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2589 vmcs_write64(GUEST_IA32_PAT, data);
2590 vcpu->arch.pat = data;
2591 break;
2592 }
8fe8ab46 2593 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2594 break;
ba904635
WA		 2595 case MSR_IA32_TSC_ADJUST:
2596 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2597 break;
2598 case MSR_TSC_AUX:
2599 if (!vmx->rdtscp_enabled)
2600 return 1;
2601 /* Check reserved bit, higher 32 bits should be zero */
2602 if ((data >> 32) != 0)
2603 return 1;
2604 /* Otherwise falls through */
6aa8b732 2605 default:
b3897a49 2606 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2607 break;
8b9cf98c 2608 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2609 if (msr) {
2610 msr->data = data;
2225fd56
AK		 2611 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2612 preempt_disable();
9ee73970
AK		 2613 kvm_set_shared_msr(msr->index, msr->data,
2614 msr->mask);
2225fd56
AK		 2615 preempt_enable();
2616 }
3bab1f5d 2617 break;
6aa8b732 2618 }
8fe8ab46 2619 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2620 }
2621
2cc51560 2622 return ret;
6aa8b732
AK		 2623}
2624
5fdbf976 2625static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2626{
5fdbf976
MT		 2627 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2628 switch (reg) {
2629 case VCPU_REGS_RSP:
2630 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2631 break;
2632 case VCPU_REGS_RIP:
2633 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2634 break;
6de4f3ad
AK		 2635 case VCPU_EXREG_PDPTR:
2636 if (enable_ept)
2637 ept_save_pdptrs(vcpu);
2638 break;
5fdbf976
MT		 2639 default:
2640 break;
2641 }
6aa8b732
AK		 2642}
2643
6aa8b732
AK		 2644static __init int cpu_has_kvm_support(void)
2645{
6210e37b 2646 return cpu_has_vmx();
6aa8b732
AK		 2647}
2648
2649static __init int vmx_disabled_by_bios(void)
2650{
2651 u64 msr;
2652
2653 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2654 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2655 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2656 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2657 && tboot_enabled())
2658 return 1;
23f3e991 2659 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2660 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2661 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2662 && !tboot_enabled()) {
2663 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2664 "activate TXT before enabling KVM\n");
cafd6659 2665 return 1;
f9335afe 2666 }
23f3e991
JC		 2667 /* launched w/o TXT and VMX disabled */
2668 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2669 && !tboot_enabled())
2670 return 1;
cafd6659
SW		 2671 }
2672
2673 return 0;
6aa8b732
AK		 2674}
2675
7725b894
DX		 2676static void kvm_cpu_vmxon(u64 addr)
2677{
2678 asm volatile (ASM_VMX_VMXON_RAX
2679 : : "a"(&addr), "m"(addr)
2680 : "memory", "cc");
2681}
2682
10474ae8 2683static int hardware_enable(void *garbage)
6aa8b732
AK		 2684{
2685 int cpu = raw_smp_processor_id();
2686 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2687 u64 old, test_bits;
6aa8b732 2688
10474ae8
AG		 2689 if (read_cr4() & X86_CR4_VMXE)
2690 return -EBUSY;
2691
d462b819 2692 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2693
2694 /*
2695 * Now we can enable the vmclear operation in kdump
2696 * since the loaded_vmcss_on_cpu list on this cpu
2697 * has been initialized.
2698 *
2699 * Though the cpu is not in VMX operation now, there
2700 * is no problem to enable the vmclear operation
2701 * for the loaded_vmcss_on_cpu list is empty!
2702 */
2703 crash_enable_local_vmclear(cpu);
2704
6aa8b732 2705 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2706
2707 test_bits = FEATURE_CONTROL_LOCKED;
2708 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2709 if (tboot_enabled())
2710 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2711
2712 if ((old & test_bits) != test_bits) {
6aa8b732 2713 /* enable and lock */
cafd6659
SW		 2714 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2715 }
66aee91a 2716 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2717
4610c9cc
DX		 2718 if (vmm_exclusive) {
2719 kvm_cpu_vmxon(phys_addr);
2720 ept_sync_global();
2721 }
10474ae8 2722
357d1226 2723 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2724
10474ae8 2725 return 0;
6aa8b732
AK		 2726}
2727
d462b819 2728static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2729{
2730 int cpu = raw_smp_processor_id();
d462b819 2731 struct loaded_vmcs *v, *n;
543e4243 2732
d462b819
NHE		 2733 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2734 loaded_vmcss_on_cpu_link)
2735 __loaded_vmcs_clear(v);
543e4243
AK		 2736}
2737
710ff4a8
EH		 2738
2739/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2740 * tricks.
2741 */
2742static void kvm_cpu_vmxoff(void)
6aa8b732 2743{
4ecac3fd 2744 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2745}
2746
710ff4a8
EH		 2747static void hardware_disable(void *garbage)
2748{
4610c9cc 2749 if (vmm_exclusive) {
d462b819 2750 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2751 kvm_cpu_vmxoff();
2752 }
7725b894 2753 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2754}
2755
1c3d14fe 2756static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2757 u32 msr, u32 *result)
1c3d14fe
YS		 2758{
2759 u32 vmx_msr_low, vmx_msr_high;
2760 u32 ctl = ctl_min | ctl_opt;
2761
2762 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2763
2764 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2765 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2766
2767 /* Ensure minimum (required) set of control bits are supported. */
2768 if (ctl_min & ~ctl)
002c7f7c 2769 return -EIO;
1c3d14fe
YS		 2770
2771 *result = ctl;
2772 return 0;
2773}
2774
110312c8
AK		 2775static __init bool allow_1_setting(u32 msr, u32 ctl)
2776{
2777 u32 vmx_msr_low, vmx_msr_high;
2778
2779 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2780 return vmx_msr_high & ctl;
2781}
2782
002c7f7c 2783static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2784{
2785 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2786 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2787 u32 _pin_based_exec_control = 0;
2788 u32 _cpu_based_exec_control = 0;
f78e0e2e 2789 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2790 u32 _vmexit_control = 0;
2791 u32 _vmentry_control = 0;
2792
10166744 2793 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2794#ifdef CONFIG_X86_64
2795 CPU_BASED_CR8_LOAD_EXITING |
2796 CPU_BASED_CR8_STORE_EXITING |
2797#endif
d56f546d
SY		 2798 CPU_BASED_CR3_LOAD_EXITING |
2799 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2800 CPU_BASED_USE_IO_BITMAPS |
2801 CPU_BASED_MOV_DR_EXITING |
a7052897 2802 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2803 CPU_BASED_MWAIT_EXITING |
2804 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2805 CPU_BASED_INVLPG_EXITING |
2806 CPU_BASED_RDPMC_EXITING;
443381a8 2807
f78e0e2e 2808 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2809 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2810 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2811 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2812 &_cpu_based_exec_control) < 0)
002c7f7c 2813 return -EIO;
6e5d865c
YS		 2814#ifdef CONFIG_X86_64
2815 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2816 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2817 ~CPU_BASED_CR8_STORE_EXITING;
2818#endif
f78e0e2e 2819 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2820 min2 = 0;
2821 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2822 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2823 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2824 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2825 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2826 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2827 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2828 SECONDARY_EXEC_RDTSCP |
83d4c286 2829 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2830 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2831 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2832 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2833 if (adjust_vmx_controls(min2, opt2,
2834 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2835 &_cpu_based_2nd_exec_control) < 0)
2836 return -EIO;
2837 }
2838#ifndef CONFIG_X86_64
2839 if (!(_cpu_based_2nd_exec_control &
2840 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2841 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2842#endif
83d4c286
YZ		 2843
2844 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2845 _cpu_based_2nd_exec_control &= ~(
8d14695f 2846 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2847 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2848 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2849
d56f546d 2850 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2851 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2852 enabled */
5fff7d27
GN		 2853 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2854 CPU_BASED_CR3_STORE_EXITING |
2855 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2856 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2857 vmx_capability.ept, vmx_capability.vpid);
2858 }
1c3d14fe
YS		 2859
2860 min = 0;
2861#ifdef CONFIG_X86_64
2862 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2863#endif
a547c6db
YZ		 2864 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2865 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2866 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2867 &_vmexit_control) < 0)
002c7f7c 2868 return -EIO;
1c3d14fe 2869
01e439be
YZ		 2870 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2871 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2872 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2873 &_pin_based_exec_control) < 0)
2874 return -EIO;
2875
2876 if (!(_cpu_based_2nd_exec_control &
2877 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2878 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2879 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2880
468d472f
SY		 2881 min = 0;
2882 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2883 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2884 &_vmentry_control) < 0)
002c7f7c 2885 return -EIO;
6aa8b732 2886
c68876fd 2887 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2888
2889 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2890 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2891 return -EIO;
1c3d14fe
YS		 2892
2893#ifdef CONFIG_X86_64
2894 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2895 if (vmx_msr_high & (1u<<16))
002c7f7c 2896 return -EIO;
1c3d14fe
YS		 2897#endif
2898
2899 /* Require Write-Back (WB) memory type for VMCS accesses. */
2900 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2901 return -EIO;
1c3d14fe 2902
002c7f7c
YS		 2903 vmcs_conf->size = vmx_msr_high & 0x1fff;
2904 vmcs_conf->order = get_order(vmcs_config.size);
2905 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2906
002c7f7c
YS		 2907 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2908 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2909 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2910 vmcs_conf->vmexit_ctrl = _vmexit_control;
2911 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2912
110312c8
AK		 2913 cpu_has_load_ia32_efer =
2914 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2915 VM_ENTRY_LOAD_IA32_EFER)
2916 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2917 VM_EXIT_LOAD_IA32_EFER);
2918
8bf00a52
GN		 2919 cpu_has_load_perf_global_ctrl =
2920 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2921 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2922 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2923 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2924
2925 /*
2926 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2927 * but due to arrata below it can't be used. Workaround is to use
2928 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2929 *
2930 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2931 *
2932 * AAK155 (model 26)
2933 * AAP115 (model 30)
2934 * AAT100 (model 37)
2935 * BC86,AAY89,BD102 (model 44)
2936 * BA97 (model 46)
2937 *
2938 */
2939 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2940 switch (boot_cpu_data.x86_model) {
2941 case 26:
2942 case 30:
2943 case 37:
2944 case 44:
2945 case 46:
2946 cpu_has_load_perf_global_ctrl = false;
2947 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2948 "does not work properly. Using workaround\n");
2949 break;
2950 default:
2951 break;
2952 }
2953 }
2954
1c3d14fe 2955 return 0;
c68876fd 2956}
6aa8b732
AK		 2957
2958static struct vmcs *alloc_vmcs_cpu(int cpu)
2959{
2960 int node = cpu_to_node(cpu);
2961 struct page *pages;
2962 struct vmcs *vmcs;
2963
6484eb3e 2964 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2965 if (!pages)
2966 return NULL;
2967 vmcs = page_address(pages);
1c3d14fe
YS		 2968 memset(vmcs, 0, vmcs_config.size);
2969 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2970 return vmcs;
2971}
2972
2973static struct vmcs *alloc_vmcs(void)
2974{
d3b2c338 2975 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2976}
2977
2978static void free_vmcs(struct vmcs *vmcs)
2979{
1c3d14fe 2980 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2981}
2982
d462b819
NHE		 2983/*
2984 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2985 */
2986static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2987{
2988 if (!loaded_vmcs->vmcs)
2989 return;
2990 loaded_vmcs_clear(loaded_vmcs);
2991 free_vmcs(loaded_vmcs->vmcs);
2992 loaded_vmcs->vmcs = NULL;
2993}
2994
39959588 2995static void free_kvm_area(void)
6aa8b732
AK		 2996{
2997 int cpu;
2998
3230bb47 2999 for_each_possible_cpu(cpu) {
6aa8b732 3000 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3001 per_cpu(vmxarea, cpu) = NULL;
3002 }
6aa8b732
AK		 3003}
3004
6aa8b732
AK		 3005static __init int alloc_kvm_area(void)
3006{
3007 int cpu;
3008
3230bb47 3009 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3010 struct vmcs *vmcs;
3011
3012 vmcs = alloc_vmcs_cpu(cpu);
3013 if (!vmcs) {
3014 free_kvm_area();
3015 return -ENOMEM;
3016 }
3017
3018 per_cpu(vmxarea, cpu) = vmcs;
3019 }
3020 return 0;
3021}
3022
3023static __init int hardware_setup(void)
3024{
002c7f7c
YS		 3025 if (setup_vmcs_config(&vmcs_config) < 0)
3026 return -EIO;
50a37eb4
JR		 3027
3028 if (boot_cpu_has(X86_FEATURE_NX))
3029 kvm_enable_efer_bits(EFER_NX);
3030
93ba03c2
SY		 3031 if (!cpu_has_vmx_vpid())
3032 enable_vpid = 0;
abc4fc58
AG		 3033 if (!cpu_has_vmx_shadow_vmcs())
3034 enable_shadow_vmcs = 0;
93ba03c2 3035
4bc9b982
SY		 3036 if (!cpu_has_vmx_ept() ||
3037 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3038 enable_ept = 0;
3a624e29 3039 enable_unrestricted_guest = 0;
83c3a331 3040 enable_ept_ad_bits = 0;
3a624e29
NK		 3041 }
3042
83c3a331
XH		 3043 if (!cpu_has_vmx_ept_ad_bits())
3044 enable_ept_ad_bits = 0;
3045
3a624e29
NK		 3046 if (!cpu_has_vmx_unrestricted_guest())
3047 enable_unrestricted_guest = 0;
93ba03c2
SY		 3048
3049 if (!cpu_has_vmx_flexpriority())
3050 flexpriority_enabled = 0;
3051
95ba8273
GN		 3052 if (!cpu_has_vmx_tpr_shadow())
3053 kvm_x86_ops->update_cr8_intercept = NULL;
3054
54dee993
MT		 3055 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3056 kvm_disable_largepages();
3057
4b8d54f9
ZE		 3058 if (!cpu_has_vmx_ple())
3059 ple_gap = 0;
3060
01e439be
YZ		 3061 if (!cpu_has_vmx_apicv())
3062 enable_apicv = 0;
c7c9c56c 3063
01e439be 3064 if (enable_apicv)
c7c9c56c 3065 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3066 else {
c7c9c56c 3067 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3068 kvm_x86_ops->deliver_posted_interrupt = NULL;
3069 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3070 }
83d4c286 3071
b87a51ae
NHE		 3072 if (nested)
3073 nested_vmx_setup_ctls_msrs();
3074
6aa8b732
AK		 3075 return alloc_kvm_area();
3076}
3077
3078static __exit void hardware_unsetup(void)
3079{
3080 free_kvm_area();
3081}
3082
14168786
GN		 3083static bool emulation_required(struct kvm_vcpu *vcpu)
3084{
3085 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3086}
3087
91b0aa2c 3088static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3089 struct kvm_segment *save)
6aa8b732 3090{
d99e4152
GN		 3091 if (!emulate_invalid_guest_state) {
3092 /*
3093 * CS and SS RPL should be equal during guest entry according
3094 * to VMX spec, but in reality it is not always so. Since vcpu
3095 * is in the middle of the transition from real mode to
3096 * protected mode it is safe to assume that RPL 0 is a good
3097 * default value.
3098 */
3099 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3100 save->selector &= ~SELECTOR_RPL_MASK;
3101 save->dpl = save->selector & SELECTOR_RPL_MASK;
3102 save->s = 1;
6aa8b732 3103 }
d99e4152 3104 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3105}
3106
3107static void enter_pmode(struct kvm_vcpu *vcpu)
3108{
3109 unsigned long flags;
a89a8fb9 3110 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3111
d99e4152
GN		 3112 /*
3113 * Update real mode segment cache. It may be not up-to-date if sement
3114 * register was written while vcpu was in a guest mode.
3115 */
3116 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3117 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3122
7ffd92c5 3123 vmx->rmode.vm86_active = 0;
6aa8b732 3124
2fb92db1
AK		 3125 vmx_segment_cache_clear(vmx);
3126
f5f7b2fe 3127 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3128
3129 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3130 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3131 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3132 vmcs_writel(GUEST_RFLAGS, flags);
3133
66aee91a
RR		 3134 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3135 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3136
3137 update_exception_bitmap(vcpu);
3138
91b0aa2c
GN		 3139 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3140 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3141 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3142 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3143 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3144 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3145
3146 /* CPL is always 0 when CPU enters protected mode */
3147 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3148 vmx->cpl = 0;
6aa8b732
AK		 3149}
3150
f5f7b2fe 3151static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3152{
772e0318 3153 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3154 struct kvm_segment var = *save;
3155
3156 var.dpl = 0x3;
3157 if (seg == VCPU_SREG_CS)
3158 var.type = 0x3;
3159
3160 if (!emulate_invalid_guest_state) {
3161 var.selector = var.base >> 4;
3162 var.base = var.base & 0xffff0;
3163 var.limit = 0xffff;
3164 var.g = 0;
3165 var.db = 0;
3166 var.present = 1;
3167 var.s = 1;
3168 var.l = 0;
3169 var.unusable = 0;
3170 var.type = 0x3;
3171 var.avl = 0;
3172 if (save->base & 0xf)
3173 printk_once(KERN_WARNING "kvm: segment base is not "
3174 "paragraph aligned when entering "
3175 "protected mode (seg=%d)", seg);
3176 }
6aa8b732 3177
d99e4152
GN		 3178 vmcs_write16(sf->selector, var.selector);
3179 vmcs_write32(sf->base, var.base);
3180 vmcs_write32(sf->limit, var.limit);
3181 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3182}
3183
3184static void enter_rmode(struct kvm_vcpu *vcpu)
3185{
3186 unsigned long flags;
a89a8fb9 3187 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3188
f5f7b2fe
AK		 3189 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3190 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3191 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3192 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3193 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3194 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3195 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3196
7ffd92c5 3197 vmx->rmode.vm86_active = 1;
6aa8b732 3198
776e58ea
GN		 3199 /*
3200 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3201 * vcpu. Warn the user that an update is overdue.
776e58ea 3202 */
4918c6ca 3203 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3204 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3205 "called before entering vcpu\n");
776e58ea 3206
2fb92db1
AK		 3207 vmx_segment_cache_clear(vmx);
3208
4918c6ca 3209 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3210 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3211 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3212
3213 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3214 vmx->rmode.save_rflags = flags;
6aa8b732 3215
053de044 3216 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3217
3218 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3219 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3220 update_exception_bitmap(vcpu);
3221
d99e4152
GN		 3222 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3223 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3224 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3225 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3226 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3227 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3228
8668a3c4 3229 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3230}
3231
401d10de
AS		 3232static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3233{
3234 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3235 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3236
3237 if (!msr)
3238 return;
401d10de 3239
44ea2b17
AK		 3240 /*
3241 * Force kernel_gs_base reloading before EFER changes, as control
3242 * of this msr depends on is_long_mode().
3243 */
3244 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3245 vcpu->arch.efer = efer;
401d10de 3246 if (efer & EFER_LMA) {
2961e876 3247 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3248 msr->data = efer;
3249 } else {
2961e876 3250 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3251
3252 msr->data = efer & ~EFER_LME;
3253 }
3254 setup_msrs(vmx);
3255}
3256
05b3e0c2 3257#ifdef CONFIG_X86_64
6aa8b732
AK		 3258
3259static void enter_lmode(struct kvm_vcpu *vcpu)
3260{
3261 u32 guest_tr_ar;
3262
2fb92db1
AK		 3263 vmx_segment_cache_clear(to_vmx(vcpu));
3264
6aa8b732
AK		 3265 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3266 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3267 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3268 __func__);
6aa8b732
AK		 3269 vmcs_write32(GUEST_TR_AR_BYTES,
3270 (guest_tr_ar & ~AR_TYPE_MASK)
3271 | AR_TYPE_BUSY_64_TSS);
3272 }
da38f438 3273 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3274}
3275
3276static void exit_lmode(struct kvm_vcpu *vcpu)
3277{
2961e876 3278 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3279 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3280}
3281
3282#endif
3283
2384d2b3
SY		 3284static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3285{
b9d762fa 3286 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3287 if (enable_ept) {
3288 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3289 return;
4e1096d2 3290 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3291 }
2384d2b3
SY		 3292}
3293
e8467fda
AK		 3294static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3295{
3296 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3297
3298 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3299 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3300}
3301
aff48baa
AK		 3302static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3303{
3304 if (enable_ept && is_paging(vcpu))
3305 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3306 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3307}
3308
25c4c276 3309static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3310{
fc78f519
AK		 3311 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3312
3313 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3314 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3315}
3316
1439442c
SY		 3317static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3318{
d0d538b9
GN		 3319 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3320
6de4f3ad
AK		 3321 if (!test_bit(VCPU_EXREG_PDPTR,
3322 (unsigned long *)&vcpu->arch.regs_dirty))
3323 return;
3324
1439442c 3325 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3326 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3327 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3328 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3329 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3330 }
3331}
3332
8f5d549f
AK		 3333static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3334{
d0d538b9
GN		 3335 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3336
8f5d549f 3337 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3338 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3339 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3340 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3341 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3342 }
6de4f3ad
AK		 3343
3344 __set_bit(VCPU_EXREG_PDPTR,
3345 (unsigned long *)&vcpu->arch.regs_avail);
3346 __set_bit(VCPU_EXREG_PDPTR,
3347 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3348}
3349
5e1746d6 3350static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3351
3352static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3353 unsigned long cr0,
3354 struct kvm_vcpu *vcpu)
3355{
5233dd51
MT		 3356 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3357 vmx_decache_cr3(vcpu);
1439442c
SY		 3358 if (!(cr0 & X86_CR0_PG)) {
3359 /* From paging/starting to nonpaging */
3360 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3361 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3362 (CPU_BASED_CR3_LOAD_EXITING |
3363 CPU_BASED_CR3_STORE_EXITING));
3364 vcpu->arch.cr0 = cr0;
fc78f519 3365 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3366 } else if (!is_paging(vcpu)) {
3367 /* From nonpaging to paging */
3368 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3369 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3370 ~(CPU_BASED_CR3_LOAD_EXITING |
3371 CPU_BASED_CR3_STORE_EXITING));
3372 vcpu->arch.cr0 = cr0;
fc78f519 3373 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3374 }
95eb84a7
SY		 3375
3376 if (!(cr0 & X86_CR0_WP))
3377 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3378}
3379
6aa8b732
AK		 3380static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3381{
7ffd92c5 3382 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3383 unsigned long hw_cr0;
3384
5037878e 3385 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3386 if (enable_unrestricted_guest)
5037878e 3387 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3388 else {
5037878e 3389 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3390
218e763f
GN		 3391 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3392 enter_pmode(vcpu);
6aa8b732 3393
218e763f
GN		 3394 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3395 enter_rmode(vcpu);
3396 }
6aa8b732 3397
05b3e0c2 3398#ifdef CONFIG_X86_64
f6801dff 3399 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3400 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3401 enter_lmode(vcpu);
707d92fa 3402 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3403 exit_lmode(vcpu);
3404 }
3405#endif
3406
089d034e 3407 if (enable_ept)
1439442c
SY		 3408 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3409
02daab21 3410 if (!vcpu->fpu_active)
81231c69 3411 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3412
6aa8b732 3413 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3414 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3415 vcpu->arch.cr0 = cr0;
14168786
GN		 3416
3417 /* depends on vcpu->arch.cr0 to be set to a new value */
3418 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3419}
3420
1439442c
SY		 3421static u64 construct_eptp(unsigned long root_hpa)
3422{
3423 u64 eptp;
3424
3425 /* TODO write the value reading from MSR */
3426 eptp = VMX_EPT_DEFAULT_MT |
3427 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3428 if (enable_ept_ad_bits)
3429 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3430 eptp |= (root_hpa & PAGE_MASK);
3431
3432 return eptp;
3433}
3434
6aa8b732
AK		 3435static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3436{
1439442c
SY		 3437 unsigned long guest_cr3;
3438 u64 eptp;
3439
3440 guest_cr3 = cr3;
089d034e 3441 if (enable_ept) {
1439442c
SY		 3442 eptp = construct_eptp(cr3);
3443 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3444 if (is_paging(vcpu) || is_guest_mode(vcpu))
3445 guest_cr3 = kvm_read_cr3(vcpu);
3446 else
3447 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3448 ept_load_pdptrs(vcpu);
1439442c
SY		 3449 }
3450
2384d2b3 3451 vmx_flush_tlb(vcpu);
1439442c 3452 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3453}
3454
5e1746d6 3455static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3456{
7ffd92c5 3457 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3458 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3459
5e1746d6
NHE		 3460 if (cr4 & X86_CR4_VMXE) {
3461 /*
3462 * To use VMXON (and later other VMX instructions), a guest
3463 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3464 * So basically the check on whether to allow nested VMX
3465 * is here.
3466 */
3467 if (!nested_vmx_allowed(vcpu))
3468 return 1;
1a0d74e6
JK		 3469 }
3470 if (to_vmx(vcpu)->nested.vmxon &&
3471 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3472 return 1;
3473
ad312c7c 3474 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3475 if (enable_ept) {
3476 if (!is_paging(vcpu)) {
3477 hw_cr4 &= ~X86_CR4_PAE;
3478 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3479 /*
3480 * SMEP is disabled if CPU is in non-paging mode in
3481 * hardware. However KVM always uses paging mode to
3482 * emulate guest non-paging mode with TDP.
3483 * To emulate this behavior, SMEP needs to be manually
3484 * disabled when guest switches to non-paging mode.
3485 */
3486 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3487 } else if (!(cr4 & X86_CR4_PAE)) {
3488 hw_cr4 &= ~X86_CR4_PAE;
3489 }
3490 }
1439442c
SY		 3491
3492 vmcs_writel(CR4_READ_SHADOW, cr4);
3493 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3494 return 0;
6aa8b732
AK		 3495}
3496
6aa8b732
AK		 3497static void vmx_get_segment(struct kvm_vcpu *vcpu,
3498 struct kvm_segment *var, int seg)
3499{
a9179499 3500 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3501 u32 ar;
3502
c6ad1153 3503 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3504 *var = vmx->rmode.segs[seg];
a9179499 3505 if (seg == VCPU_SREG_TR
2fb92db1 3506 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3507 return;
1390a28b
AK		 3508 var->base = vmx_read_guest_seg_base(vmx, seg);
3509 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3510 return;
a9179499 3511 }
2fb92db1
AK		 3512 var->base = vmx_read_guest_seg_base(vmx, seg);
3513 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3514 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3515 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3516 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3517 var->type = ar & 15;
3518 var->s = (ar >> 4) & 1;
3519 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3520 /*
3521 * Some userspaces do not preserve unusable property. Since usable
3522 * segment has to be present according to VMX spec we can use present
3523 * property to amend userspace bug by making unusable segment always
3524 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3525 * segment as unusable.
3526 */
3527 var->present = !var->unusable;
6aa8b732
AK		 3528 var->avl = (ar >> 12) & 1;
3529 var->l = (ar >> 13) & 1;
3530 var->db = (ar >> 14) & 1;
3531 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3532}
3533
a9179499
AK		 3534static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3535{
a9179499
AK		 3536 struct kvm_segment s;
3537
3538 if (to_vmx(vcpu)->rmode.vm86_active) {
3539 vmx_get_segment(vcpu, &s, seg);
3540 return s.base;
3541 }
2fb92db1 3542 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3543}
3544
b09408d0 3545static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3546{
b09408d0
MT		 3547 struct vcpu_vmx *vmx = to_vmx(vcpu);
3548
3eeb3288 3549 if (!is_protmode(vcpu))
2e4d2653
IE		 3550 return 0;
3551
f4c63e5d
AK		 3552 if (!is_long_mode(vcpu)
3553 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3554 return 3;
3555
69c73028
AK		 3556 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3557 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3558 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3559 }
d881e6f6
AK		 3560
3561 return vmx->cpl;
69c73028
AK		 3562}
3563
3564
653e3108 3565static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3566{
6aa8b732
AK		 3567 u32 ar;
3568
f0495f9b 3569 if (var->unusable || !var->present)
6aa8b732
AK		 3570 ar = 1 << 16;
3571 else {
3572 ar = var->type & 15;
3573 ar |= (var->s & 1) << 4;
3574 ar |= (var->dpl & 3) << 5;
3575 ar |= (var->present & 1) << 7;
3576 ar |= (var->avl & 1) << 12;
3577 ar |= (var->l & 1) << 13;
3578 ar |= (var->db & 1) << 14;
3579 ar |= (var->g & 1) << 15;
3580 }
653e3108
AK		 3581
3582 return ar;
3583}
3584
3585static void vmx_set_segment(struct kvm_vcpu *vcpu,
3586 struct kvm_segment *var, int seg)
3587{
7ffd92c5 3588 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3589 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3590
2fb92db1 3591 vmx_segment_cache_clear(vmx);
2f143240
GN		 3592 if (seg == VCPU_SREG_CS)
3593 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3594
1ecd50a9
GN		 3595 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3596 vmx->rmode.segs[seg] = *var;
3597 if (seg == VCPU_SREG_TR)
3598 vmcs_write16(sf->selector, var->selector);
3599 else if (var->s)
3600 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3601 goto out;
653e3108 3602 }
1ecd50a9 3603
653e3108
AK		 3604 vmcs_writel(sf->base, var->base);
3605 vmcs_write32(sf->limit, var->limit);
3606 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3607
3608 /*
3609 * Fix the "Accessed" bit in AR field of segment registers for older
3610 * qemu binaries.
3611 * IA32 arch specifies that at the time of processor reset the
3612 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3613 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3614 * state vmexit when "unrestricted guest" mode is turned on.
3615 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3616 * tree. Newer qemu binaries with that qemu fix would not need this
3617 * kvm hack.
3618 */
3619 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3620 var->type |= 0x1; /* Accessed */
3a624e29 3621
f924d66d 3622 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3623
3624out:
14168786 3625 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3626}
3627
6aa8b732
AK		 3628static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3629{
2fb92db1 3630 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3631
3632 *db = (ar >> 14) & 1;
3633 *l = (ar >> 13) & 1;
3634}
3635
89a27f4d 3636static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3637{
89a27f4d
GN		 3638 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3639 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3640}
3641
89a27f4d 3642static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3643{
89a27f4d
GN		 3644 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3645 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3646}
3647
89a27f4d 3648static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3649{
89a27f4d
GN		 3650 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3651 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3652}
3653
89a27f4d 3654static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3655{
89a27f4d
GN		 3656 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3657 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3658}
3659
648dfaa7
MG		 3660static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3661{
3662 struct kvm_segment var;
3663 u32 ar;
3664
3665 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3666 var.dpl = 0x3;
0647f4aa
GN		 3667 if (seg == VCPU_SREG_CS)
3668 var.type = 0x3;
648dfaa7
MG		 3669 ar = vmx_segment_access_rights(&var);
3670
3671 if (var.base != (var.selector << 4))
3672 return false;
89efbed0 3673 if (var.limit != 0xffff)
648dfaa7 3674 return false;
07f42f5f 3675 if (ar != 0xf3)
648dfaa7
MG		 3676 return false;
3677
3678 return true;
3679}
3680
3681static bool code_segment_valid(struct kvm_vcpu *vcpu)
3682{
3683 struct kvm_segment cs;
3684 unsigned int cs_rpl;
3685
3686 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3687 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3688
1872a3f4
AK		 3689 if (cs.unusable)
3690 return false;
648dfaa7
MG		 3691 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3692 return false;
3693 if (!cs.s)
3694 return false;
1872a3f4 3695 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3696 if (cs.dpl > cs_rpl)
3697 return false;
1872a3f4 3698 } else {
648dfaa7
MG		 3699 if (cs.dpl != cs_rpl)
3700 return false;
3701 }
3702 if (!cs.present)
3703 return false;
3704
3705 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3706 return true;
3707}
3708
3709static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3710{
3711 struct kvm_segment ss;
3712 unsigned int ss_rpl;
3713
3714 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3715 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3716
1872a3f4
AK		 3717 if (ss.unusable)
3718 return true;
3719 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3720 return false;
3721 if (!ss.s)
3722 return false;
3723 if (ss.dpl != ss_rpl) /* DPL != RPL */
3724 return false;
3725 if (!ss.present)
3726 return false;
3727
3728 return true;
3729}
3730
3731static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3732{
3733 struct kvm_segment var;
3734 unsigned int rpl;
3735
3736 vmx_get_segment(vcpu, &var, seg);
3737 rpl = var.selector & SELECTOR_RPL_MASK;
3738
1872a3f4
AK		 3739 if (var.unusable)
3740 return true;
648dfaa7
MG		 3741 if (!var.s)
3742 return false;
3743 if (!var.present)
3744 return false;
3745 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3746 if (var.dpl < rpl) /* DPL < RPL */
3747 return false;
3748 }
3749
3750 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3751 * rights flags
3752 */
3753 return true;
3754}
3755
3756static bool tr_valid(struct kvm_vcpu *vcpu)
3757{
3758 struct kvm_segment tr;
3759
3760 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3761
1872a3f4
AK		 3762 if (tr.unusable)
3763 return false;
648dfaa7
MG		 3764 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3765 return false;
1872a3f4 3766 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3767 return false;
3768 if (!tr.present)
3769 return false;
3770
3771 return true;
3772}
3773
3774static bool ldtr_valid(struct kvm_vcpu *vcpu)
3775{
3776 struct kvm_segment ldtr;
3777
3778 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3779
1872a3f4
AK		 3780 if (ldtr.unusable)
3781 return true;
648dfaa7
MG		 3782 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3783 return false;
3784 if (ldtr.type != 2)
3785 return false;
3786 if (!ldtr.present)
3787 return false;
3788
3789 return true;
3790}
3791
3792static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3793{
3794 struct kvm_segment cs, ss;
3795
3796 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3797 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3798
3799 return ((cs.selector & SELECTOR_RPL_MASK) ==
3800 (ss.selector & SELECTOR_RPL_MASK));
3801}
3802
3803/*
3804 * Check if guest state is valid. Returns true if valid, false if
3805 * not.
3806 * We assume that registers are always usable
3807 */
3808static bool guest_state_valid(struct kvm_vcpu *vcpu)
3809{
c5e97c80
GN		 3810 if (enable_unrestricted_guest)
3811 return true;
3812
648dfaa7 3813 /* real mode guest state checks */
f13882d8 3814 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3815 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3816 return false;
3817 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3818 return false;
3819 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3820 return false;
3821 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3822 return false;
3823 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3824 return false;
3825 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3826 return false;
3827 } else {
3828 /* protected mode guest state checks */
3829 if (!cs_ss_rpl_check(vcpu))
3830 return false;
3831 if (!code_segment_valid(vcpu))
3832 return false;
3833 if (!stack_segment_valid(vcpu))
3834 return false;
3835 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3836 return false;
3837 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3838 return false;
3839 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3840 return false;
3841 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3842 return false;
3843 if (!tr_valid(vcpu))
3844 return false;
3845 if (!ldtr_valid(vcpu))
3846 return false;
3847 }
3848 /* TODO:
3849 * - Add checks on RIP
3850 * - Add checks on RFLAGS
3851 */
3852
3853 return true;
3854}
3855
d77c26fc 3856static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3857{
40dcaa9f 3858 gfn_t fn;
195aefde 3859 u16 data = 0;
40dcaa9f 3860 int r, idx, ret = 0;
6aa8b732 3861
40dcaa9f 3862 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3863 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3864 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3865 if (r < 0)
10589a46 3866 goto out;
195aefde 3867 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3868 r = kvm_write_guest_page(kvm, fn++, &data,
3869 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3870 if (r < 0)
10589a46 3871 goto out;
195aefde
IE		 3872 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3873 if (r < 0)
10589a46 3874 goto out;
195aefde
IE		 3875 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3876 if (r < 0)
10589a46 3877 goto out;
195aefde 3878 data = ~0;
10589a46
MT		 3879 r = kvm_write_guest_page(kvm, fn, &data,
3880 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3881 sizeof(u8));
195aefde 3882 if (r < 0)
10589a46
MT		 3883 goto out;
3884
3885 ret = 1;
3886out:
40dcaa9f 3887 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3888 return ret;
6aa8b732
AK		 3889}
3890
b7ebfb05
SY		 3891static int init_rmode_identity_map(struct kvm *kvm)
3892{
40dcaa9f 3893 int i, idx, r, ret;
b7ebfb05
SY		 3894 pfn_t identity_map_pfn;
3895 u32 tmp;
3896
089d034e 3897 if (!enable_ept)
b7ebfb05
SY		 3898 return 1;
3899 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3900 printk(KERN_ERR "EPT: identity-mapping pagetable "
3901 "haven't been allocated!\n");
3902 return 0;
3903 }
3904 if (likely(kvm->arch.ept_identity_pagetable_done))
3905 return 1;
3906 ret = 0;
b927a3ce 3907 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3908 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3909 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3910 if (r < 0)
3911 goto out;
3912 /* Set up identity-mapping pagetable for EPT in real mode */
3913 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3914 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3915 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3916 r = kvm_write_guest_page(kvm, identity_map_pfn,
3917 &tmp, i * sizeof(tmp), sizeof(tmp));
3918 if (r < 0)
3919 goto out;
3920 }
3921 kvm->arch.ept_identity_pagetable_done = true;
3922 ret = 1;
3923out:
40dcaa9f 3924 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3925 return ret;
3926}
3927
6aa8b732
AK		 3928static void seg_setup(int seg)
3929{
772e0318 3930 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3931 unsigned int ar;
6aa8b732
AK		 3932
3933 vmcs_write16(sf->selector, 0);
3934 vmcs_writel(sf->base, 0);
3935 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3936 ar = 0x93;
3937 if (seg == VCPU_SREG_CS)
3938 ar |= 0x08; /* code segment */
3a624e29
NK		 3939
3940 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3941}
3942
f78e0e2e
SY		 3943static int alloc_apic_access_page(struct kvm *kvm)
3944{
4484141a 3945 struct page *page;
f78e0e2e
SY		 3946 struct kvm_userspace_memory_region kvm_userspace_mem;
3947 int r = 0;
3948
79fac95e 3949 mutex_lock(&kvm->slots_lock);
bfc6d222 3950 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3951 goto out;
3952 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3953 kvm_userspace_mem.flags = 0;
3954 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3955 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3956 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3957 if (r)
3958 goto out;
72dc67a6 3959
4484141a
XG		 3960 page = gfn_to_page(kvm, 0xfee00);
3961 if (is_error_page(page)) {
3962 r = -EFAULT;
3963 goto out;
3964 }
3965
3966 kvm->arch.apic_access_page = page;
f78e0e2e 3967out:
79fac95e 3968 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3969 return r;
3970}
3971
b7ebfb05
SY		 3972static int alloc_identity_pagetable(struct kvm *kvm)
3973{
4484141a 3974 struct page *page;
b7ebfb05
SY		 3975 struct kvm_userspace_memory_region kvm_userspace_mem;
3976 int r = 0;
3977
79fac95e 3978 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3979 if (kvm->arch.ept_identity_pagetable)
3980 goto out;
3981 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3982 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3983 kvm_userspace_mem.guest_phys_addr =
3984 kvm->arch.ept_identity_map_addr;
b7ebfb05 3985 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3986 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3987 if (r)
3988 goto out;
3989
4484141a
XG		 3990 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3991 if (is_error_page(page)) {
3992 r = -EFAULT;
3993 goto out;
3994 }
3995
3996 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3997out:
79fac95e 3998 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3999 return r;
4000}
4001
2384d2b3
SY		 4002static void allocate_vpid(struct vcpu_vmx *vmx)
4003{
4004 int vpid;
4005
4006 vmx->vpid = 0;
919818ab 4007 if (!enable_vpid)
2384d2b3
SY		 4008 return;
4009 spin_lock(&vmx_vpid_lock);
4010 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4011 if (vpid < VMX_NR_VPIDS) {
4012 vmx->vpid = vpid;
4013 __set_bit(vpid, vmx_vpid_bitmap);
4014 }
4015 spin_unlock(&vmx_vpid_lock);
4016}
4017
cdbecfc3
LJ		 4018static void free_vpid(struct vcpu_vmx *vmx)
4019{
4020 if (!enable_vpid)
4021 return;
4022 spin_lock(&vmx_vpid_lock);
4023 if (vmx->vpid != 0)
4024 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4025 spin_unlock(&vmx_vpid_lock);
4026}
4027
8d14695f
YZ		 4028#define MSR_TYPE_R 1
4029#define MSR_TYPE_W 2
4030static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4031 u32 msr, int type)
25c5f225 4032{
3e7c73e9 4033 int f = sizeof(unsigned long);
25c5f225
SY		 4034
4035 if (!cpu_has_vmx_msr_bitmap())
4036 return;
4037
4038 /*
4039 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4040 * have the write-low and read-high bitmap offsets the wrong way round.
4041 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4042 */
25c5f225 4043 if (msr <= 0x1fff) {
8d14695f
YZ		 4044 if (type & MSR_TYPE_R)
4045 /* read-low */
4046 __clear_bit(msr, msr_bitmap + 0x000 / f);
4047
4048 if (type & MSR_TYPE_W)
4049 /* write-low */
4050 __clear_bit(msr, msr_bitmap + 0x800 / f);
4051
25c5f225
SY		 4052 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4053 msr &= 0x1fff;
8d14695f
YZ		 4054 if (type & MSR_TYPE_R)
4055 /* read-high */
4056 __clear_bit(msr, msr_bitmap + 0x400 / f);
4057
4058 if (type & MSR_TYPE_W)
4059 /* write-high */
4060 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4061
4062 }
4063}
4064
4065static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4066 u32 msr, int type)
4067{
4068 int f = sizeof(unsigned long);
4069
4070 if (!cpu_has_vmx_msr_bitmap())
4071 return;
4072
4073 /*
4074 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4075 * have the write-low and read-high bitmap offsets the wrong way round.
4076 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4077 */
4078 if (msr <= 0x1fff) {
4079 if (type & MSR_TYPE_R)
4080 /* read-low */
4081 __set_bit(msr, msr_bitmap + 0x000 / f);
4082
4083 if (type & MSR_TYPE_W)
4084 /* write-low */
4085 __set_bit(msr, msr_bitmap + 0x800 / f);
4086
4087 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4088 msr &= 0x1fff;
4089 if (type & MSR_TYPE_R)
4090 /* read-high */
4091 __set_bit(msr, msr_bitmap + 0x400 / f);
4092
4093 if (type & MSR_TYPE_W)
4094 /* write-high */
4095 __set_bit(msr, msr_bitmap + 0xc00 / f);
4096
25c5f225 4097 }
25c5f225
SY		 4098}
4099
5897297b
AK		 4100static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4101{
4102 if (!longmode_only)
8d14695f
YZ		 4103 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4104 msr, MSR_TYPE_R | MSR_TYPE_W);
4105 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4106 msr, MSR_TYPE_R | MSR_TYPE_W);
4107}
4108
4109static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4110{
4111 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4112 msr, MSR_TYPE_R);
4113 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4114 msr, MSR_TYPE_R);
4115}
4116
4117static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4118{
4119 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4120 msr, MSR_TYPE_R);
4121 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4122 msr, MSR_TYPE_R);
4123}
4124
4125static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4126{
4127 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4128 msr, MSR_TYPE_W);
4129 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4130 msr, MSR_TYPE_W);
5897297b
AK		 4131}
4132
01e439be
YZ		 4133static int vmx_vm_has_apicv(struct kvm *kvm)
4134{
4135 return enable_apicv && irqchip_in_kernel(kvm);
4136}
4137
a20ed54d
YZ		 4138/*
4139 * Send interrupt to vcpu via posted interrupt way.
4140 * 1. If target vcpu is running(non-root mode), send posted interrupt
4141 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4142 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4143 * interrupt from PIR in next vmentry.
4144 */
4145static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4146{
4147 struct vcpu_vmx *vmx = to_vmx(vcpu);
4148 int r;
4149
4150 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4151 return;
4152
4153 r = pi_test_and_set_on(&vmx->pi_desc);
4154 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4155#ifdef CONFIG_SMP
a20ed54d
YZ		 4156 if (!r && (vcpu->mode == IN_GUEST_MODE))
4157 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4158 POSTED_INTR_VECTOR);
4159 else
6ffbbbba 4160#endif
a20ed54d
YZ		 4161 kvm_vcpu_kick(vcpu);
4162}
4163
4164static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4165{
4166 struct vcpu_vmx *vmx = to_vmx(vcpu);
4167
4168 if (!pi_test_and_clear_on(&vmx->pi_desc))
4169 return;
4170
4171 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4172}
4173
4174static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4175{
4176 return;
4177}
4178
a3a8ff8e
NHE		 4179/*
4180 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4181 * will not change in the lifetime of the guest.
4182 * Note that host-state that does change is set elsewhere. E.g., host-state
4183 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4184 */
a547c6db 4185static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4186{
4187 u32 low32, high32;
4188 unsigned long tmpl;
4189 struct desc_ptr dt;
4190
b1a74bf8 4191 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4192 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4193 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4194
4195 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4196#ifdef CONFIG_X86_64
4197 /*
4198 * Load null selectors, so we can avoid reloading them in
4199 * __vmx_load_host_state(), in case userspace uses the null selectors
4200 * too (the expected case).
4201 */
4202 vmcs_write16(HOST_DS_SELECTOR, 0);
4203 vmcs_write16(HOST_ES_SELECTOR, 0);
4204#else
a3a8ff8e
NHE		 4205 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4206 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4207#endif
a3a8ff8e
NHE		 4208 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4209 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4210
4211 native_store_idt(&dt);
4212 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4213 vmx->host_idt_base = dt.address;
a3a8ff8e 4214
83287ea4 4215 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4216
4217 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4218 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4219 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4220 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4221
4222 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4223 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4224 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4225 }
4226}
4227
bf8179a0
NHE		 4228static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4229{
4230 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4231 if (enable_ept)
4232 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4233 if (is_guest_mode(&vmx->vcpu))
4234 vmx->vcpu.arch.cr4_guest_owned_bits &=
4235 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4236 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4237}
4238
01e439be
YZ		 4239static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4240{
4241 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4242
4243 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4244 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4245 return pin_based_exec_ctrl;
4246}
4247
bf8179a0
NHE		 4248static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4249{
4250 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4251 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4252 exec_control &= ~CPU_BASED_TPR_SHADOW;
4253#ifdef CONFIG_X86_64
4254 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4255 CPU_BASED_CR8_LOAD_EXITING;
4256#endif
4257 }
4258 if (!enable_ept)
4259 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4260 CPU_BASED_CR3_LOAD_EXITING |
4261 CPU_BASED_INVLPG_EXITING;
4262 return exec_control;
4263}
4264
4265static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4266{
4267 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4268 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4269 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4270 if (vmx->vpid == 0)
4271 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4272 if (!enable_ept) {
4273 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4274 enable_unrestricted_guest = 0;
ad756a16
MJ		 4275 /* Enable INVPCID for non-ept guests may cause performance regression. */
4276 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4277 }
4278 if (!enable_unrestricted_guest)
4279 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4280 if (!ple_gap)
4281 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4282 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4283 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4284 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4285 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4286 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4287 (handle_vmptrld).
4288 We can NOT enable shadow_vmcs here because we don't have yet
4289 a current VMCS12
4290 */
4291 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4292 return exec_control;
4293}
4294
ce88decf
XG		 4295static void ept_set_mmio_spte_mask(void)
4296{
4297 /*
4298 * EPT Misconfigurations can be generated if the value of bits 2:0
4299 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4300 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4301 * spte.
4302 */
885032b9 4303 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4304}
4305
6aa8b732
AK		 4306/*
4307 * Sets up the vmcs for emulated real mode.
4308 */
8b9cf98c 4309static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4310{
2e4ce7f5 4311#ifdef CONFIG_X86_64
6aa8b732 4312 unsigned long a;
2e4ce7f5 4313#endif
6aa8b732 4314 int i;
6aa8b732 4315
6aa8b732 4316 /* I/O */
3e7c73e9
AK		 4317 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4318 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4319
4607c2d7
AG		 4320 if (enable_shadow_vmcs) {
4321 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4322 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4323 }
25c5f225 4324 if (cpu_has_vmx_msr_bitmap())
5897297b 4325 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4326
6aa8b732
AK		 4327 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4328
6aa8b732 4329 /* Control */
01e439be 4330 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4331
bf8179a0 4332 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4333
83ff3b9d 4334 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4335 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4336 vmx_secondary_exec_control(vmx));
83ff3b9d 4337 }
f78e0e2e 4338
01e439be 4339 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4340 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4341 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4342 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4343 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4344
4345 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4346
4347 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4348 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4349 }
4350
4b8d54f9
ZE		 4351 if (ple_gap) {
4352 vmcs_write32(PLE_GAP, ple_gap);
4353 vmcs_write32(PLE_WINDOW, ple_window);
4354 }
4355
c3707958
XG		 4356 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4357 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4358 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4359
9581d442
AK		 4360 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4361 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4362 vmx_set_constant_host_state(vmx);
05b3e0c2 4363#ifdef CONFIG_X86_64
6aa8b732
AK		 4364 rdmsrl(MSR_FS_BASE, a);
4365 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4366 rdmsrl(MSR_GS_BASE, a);
4367 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4368#else
4369 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4370 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4371#endif
4372
2cc51560
ED		 4373 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4374 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4375 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4376 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4377 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4378
468d472f 4379 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4380 u32 msr_low, msr_high;
4381 u64 host_pat;
468d472f
SY		 4382 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4383 host_pat = msr_low | ((u64) msr_high << 32);
4384 /* Write the default value follow host pat */
4385 vmcs_write64(GUEST_IA32_PAT, host_pat);
4386 /* Keep arch.pat sync with GUEST_IA32_PAT */
4387 vmx->vcpu.arch.pat = host_pat;
4388 }
4389
6aa8b732
AK		 4390 for (i = 0; i < NR_VMX_MSR; ++i) {
4391 u32 index = vmx_msr_index[i];
4392 u32 data_low, data_high;
a2fa3e9f 4393 int j = vmx->nmsrs;
6aa8b732
AK		 4394
4395 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4396 continue;
432bd6cb
AK		 4397 if (wrmsr_safe(index, data_low, data_high) < 0)
4398 continue;
26bb0981
AK		 4399 vmx->guest_msrs[j].index = i;
4400 vmx->guest_msrs[j].data = 0;
d5696725 4401 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4402 ++vmx->nmsrs;
6aa8b732 4403 }
6aa8b732 4404
2961e876
GN		 4405
4406 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4407
4408 /* 22.2.1, 20.8.1 */
2961e876 4409 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4410
e00c8cf2 4411 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4412 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4413
4414 return 0;
4415}
4416
57f252f2 4417static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4418{
4419 struct vcpu_vmx *vmx = to_vmx(vcpu);
4420 u64 msr;
e00c8cf2 4421
7ffd92c5 4422 vmx->rmode.vm86_active = 0;
e00c8cf2 4423
3b86cd99
JK		 4424 vmx->soft_vnmi_blocked = 0;
4425
ad312c7c 4426 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4427 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4428 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4429 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4430 msr |= MSR_IA32_APICBASE_BSP;
4431 kvm_set_apic_base(&vmx->vcpu, msr);
4432
2fb92db1
AK		 4433 vmx_segment_cache_clear(vmx);
4434
5706be0d 4435 seg_setup(VCPU_SREG_CS);
66450a21 4436 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4437 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4438
4439 seg_setup(VCPU_SREG_DS);
4440 seg_setup(VCPU_SREG_ES);
4441 seg_setup(VCPU_SREG_FS);
4442 seg_setup(VCPU_SREG_GS);
4443 seg_setup(VCPU_SREG_SS);
4444
4445 vmcs_write16(GUEST_TR_SELECTOR, 0);
4446 vmcs_writel(GUEST_TR_BASE, 0);
4447 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4448 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4449
4450 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4451 vmcs_writel(GUEST_LDTR_BASE, 0);
4452 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4453 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4454
4455 vmcs_write32(GUEST_SYSENTER_CS, 0);
4456 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4457 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4458
4459 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4460 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4461
e00c8cf2
AK		 4462 vmcs_writel(GUEST_GDTR_BASE, 0);
4463 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4464
4465 vmcs_writel(GUEST_IDTR_BASE, 0);
4466 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4467
443381a8 4468 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4469 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4470 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4471
e00c8cf2
AK		 4472 /* Special registers */
4473 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4474
4475 setup_msrs(vmx);
4476
6aa8b732
AK		 4477 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4478
f78e0e2e
SY		 4479 if (cpu_has_vmx_tpr_shadow()) {
4480 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4481 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4482 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4483 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4484 vmcs_write32(TPR_THRESHOLD, 0);
4485 }
4486
4487 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4488 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4489 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4490
01e439be
YZ		 4491 if (vmx_vm_has_apicv(vcpu->kvm))
4492 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4493
2384d2b3
SY		 4494 if (vmx->vpid != 0)
4495 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4496
fa40052c 4497 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4498 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4499 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4500 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4501 vmx_fpu_activate(&vmx->vcpu);
4502 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4503
b9d762fa 4504 vpid_sync_context(vmx);
6aa8b732
AK		 4505}
4506
b6f1250e
NHE		 4507/*
4508 * In nested virtualization, check if L1 asked to exit on external interrupts.
4509 * For most existing hypervisors, this will always return true.
4510 */
4511static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4512{
4513 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4514 PIN_BASED_EXT_INTR_MASK;
4515}
4516
ea8ceb83
JK		 4517static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4518{
4519 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4520 PIN_BASED_NMI_EXITING;
4521}
4522
730dca42 4523static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4524{
4525 u32 cpu_based_vm_exec_control;
730dca42
JK		 4526
4527 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4528 /*
4529 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4530 * inject to L1 now because L2 must run. The caller will have
4531 * to make L2 exit right after entry, so we can inject to L1
4532 * more promptly.
b6f1250e 4533 */
730dca42 4534 return -EBUSY;
3b86cd99
JK		 4535
4536 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4537 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4538 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4539 return 0;
3b86cd99
JK		 4540}
4541
03b28f81 4542static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4543{
4544 u32 cpu_based_vm_exec_control;
4545
03b28f81
JK		 4546 if (!cpu_has_virtual_nmis())
4547 return enable_irq_window(vcpu);
4548
4549 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4550 return enable_irq_window(vcpu);
3b86cd99
JK		 4551
4552 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4553 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4554 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4555 return 0;
3b86cd99
JK		 4556}
4557
66fd3f7f 4558static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4559{
9c8cba37 4560 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4561 uint32_t intr;
4562 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4563
229456fc 4564 trace_kvm_inj_virq(irq);
2714d1d3 4565
fa89a817 4566 ++vcpu->stat.irq_injections;
7ffd92c5 4567 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4568 int inc_eip = 0;
4569 if (vcpu->arch.interrupt.soft)
4570 inc_eip = vcpu->arch.event_exit_inst_len;
4571 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4572 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4573 return;
4574 }
66fd3f7f
GN		 4575 intr = irq | INTR_INFO_VALID_MASK;
4576 if (vcpu->arch.interrupt.soft) {
4577 intr |= INTR_TYPE_SOFT_INTR;
4578 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4579 vmx->vcpu.arch.event_exit_inst_len);
4580 } else
4581 intr |= INTR_TYPE_EXT_INTR;
4582 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4583}
4584
f08864b4
SY		 4585static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4586{
66a5a347
JK		 4587 struct vcpu_vmx *vmx = to_vmx(vcpu);
4588
0b6ac343
NHE		 4589 if (is_guest_mode(vcpu))
4590 return;
4591
3b86cd99
JK		 4592 if (!cpu_has_virtual_nmis()) {
4593 /*
4594 * Tracking the NMI-blocked state in software is built upon
4595 * finding the next open IRQ window. This, in turn, depends on
4596 * well-behaving guests: They have to keep IRQs disabled at
4597 * least as long as the NMI handler runs. Otherwise we may
4598 * cause NMI nesting, maybe breaking the guest. But as this is
4599 * highly unlikely, we can live with the residual risk.
4600 */
4601 vmx->soft_vnmi_blocked = 1;
4602 vmx->vnmi_blocked_time = 0;
4603 }
4604
487b391d 4605 ++vcpu->stat.nmi_injections;
9d58b931 4606 vmx->nmi_known_unmasked = false;
7ffd92c5 4607 if (vmx->rmode.vm86_active) {
71f9833b 4608 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4609 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4610 return;
4611 }
f08864b4
SY		 4612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4613 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4614}
4615
3cfc3092
JK		 4616static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4617{
4618 if (!cpu_has_virtual_nmis())
4619 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4620 if (to_vmx(vcpu)->nmi_known_unmasked)
4621 return false;
c332c83a 4622 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4623}
4624
4625static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4626{
4627 struct vcpu_vmx *vmx = to_vmx(vcpu);
4628
4629 if (!cpu_has_virtual_nmis()) {
4630 if (vmx->soft_vnmi_blocked != masked) {
4631 vmx->soft_vnmi_blocked = masked;
4632 vmx->vnmi_blocked_time = 0;
4633 }
4634 } else {
9d58b931 4635 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4636 if (masked)
4637 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4638 GUEST_INTR_STATE_NMI);
4639 else
4640 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4641 GUEST_INTR_STATE_NMI);
4642 }
4643}
4644
2505dc9f
JK		 4645static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4646{
ea8ceb83
JK		 4647 if (is_guest_mode(vcpu)) {
4648 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4649
4650 if (to_vmx(vcpu)->nested.nested_run_pending)
4651 return 0;
4652 if (nested_exit_on_nmi(vcpu)) {
4653 nested_vmx_vmexit(vcpu);
4654 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4655 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4656 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4657 /*
4658 * The NMI-triggered VM exit counts as injection:
4659 * clear this one and block further NMIs.
4660 */
4661 vcpu->arch.nmi_pending = 0;
4662 vmx_set_nmi_mask(vcpu, true);
4663 return 0;
4664 }
4665 }
4666
2505dc9f
JK		 4667 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4668 return 0;
4669
4670 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4671 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4672 | GUEST_INTR_STATE_NMI));
4673}
4674
78646121
GN		 4675static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4676{
e8457c67 4677 if (is_guest_mode(vcpu)) {
51cfe38e 4678 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4679
4680 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4681 return 0;
e8457c67
JK		 4682 if (nested_exit_on_intr(vcpu)) {
4683 nested_vmx_vmexit(vcpu);
4684 vmcs12->vm_exit_reason =
4685 EXIT_REASON_EXTERNAL_INTERRUPT;
4686 vmcs12->vm_exit_intr_info = 0;
4687 /*
4688 * fall through to normal code, but now in L1, not L2
4689 */
4690 }
b6f1250e
NHE		 4691 }
4692
c4282df9
GN		 4693 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4694 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4695 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4696}
4697
cbc94022
IE		 4698static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4699{
4700 int ret;
4701 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4702 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4703 .guest_phys_addr = addr,
4704 .memory_size = PAGE_SIZE * 3,
4705 .flags = 0,
4706 };
4707
47ae31e2 4708 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4709 if (ret)
4710 return ret;
bfc6d222 4711 kvm->arch.tss_addr = addr;
93ea5388
GN		 4712 if (!init_rmode_tss(kvm))
4713 return -ENOMEM;
4714
cbc94022
IE		 4715 return 0;
4716}
4717
0ca1b4f4 4718static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4719{
77ab6db0 4720 switch (vec) {
77ab6db0 4721 case BP_VECTOR:
c573cd22
JK		 4722 /*
4723 * Update instruction length as we may reinject the exception
4724 * from user space while in guest debugging mode.
4725 */
4726 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4727 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4729 return false;
4730 /* fall through */
4731 case DB_VECTOR:
4732 if (vcpu->guest_debug &
4733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4734 return false;
d0bfb940
JK		 4735 /* fall through */
4736 case DE_VECTOR:
77ab6db0
JK		 4737 case OF_VECTOR:
4738 case BR_VECTOR:
4739 case UD_VECTOR:
4740 case DF_VECTOR:
4741 case SS_VECTOR:
4742 case GP_VECTOR:
4743 case MF_VECTOR:
0ca1b4f4
GN		 4744 return true;
4745 break;
77ab6db0 4746 }
0ca1b4f4
GN		 4747 return false;
4748}
4749
4750static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4751 int vec, u32 err_code)
4752{
4753 /*
4754 * Instruction with address size override prefix opcode 0x67
4755 * Cause the #SS fault with 0 error code in VM86 mode.
4756 */
4757 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4758 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4759 if (vcpu->arch.halt_request) {
4760 vcpu->arch.halt_request = 0;
4761 return kvm_emulate_halt(vcpu);
4762 }
4763 return 1;
4764 }
4765 return 0;
4766 }
4767
4768 /*
4769 * Forward all other exceptions that are valid in real mode.
4770 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4771 * the required debugging infrastructure rework.
4772 */
4773 kvm_queue_exception(vcpu, vec);
4774 return 1;
6aa8b732
AK		 4775}
4776
a0861c02
AK		 4777/*
4778 * Trigger machine check on the host. We assume all the MSRs are already set up
4779 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4780 * We pass a fake environment to the machine check handler because we want
4781 * the guest to be always treated like user space, no matter what context
4782 * it used internally.
4783 */
4784static void kvm_machine_check(void)
4785{
4786#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4787 struct pt_regs regs = {
4788 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4789 .flags = X86_EFLAGS_IF,
4790 };
4791
4792 do_machine_check(&regs, 0);
4793#endif
4794}
4795
851ba692 4796static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4797{
4798 /* already handled by vcpu_run */
4799 return 1;
4800}
4801
851ba692 4802static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4803{
1155f76a 4804 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4805 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4806 u32 intr_info, ex_no, error_code;
42dbaa5a 4807 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4808 u32 vect_info;
4809 enum emulation_result er;
4810
1155f76a 4811 vect_info = vmx->idt_vectoring_info;
88786475 4812 intr_info = vmx->exit_intr_info;
6aa8b732 4813
a0861c02 4814 if (is_machine_check(intr_info))
851ba692 4815 return handle_machine_check(vcpu);
a0861c02 4816
e4a41889 4817 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4818 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4819
4820 if (is_no_device(intr_info)) {
5fd86fcf 4821 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4822 return 1;
4823 }
4824
7aa81cc0 4825 if (is_invalid_opcode(intr_info)) {
51d8b661 4826 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4827 if (er != EMULATE_DONE)
7ee5d940 4828 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4829 return 1;
4830 }
4831
6aa8b732 4832 error_code = 0;
2e11384c 4833 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4834 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4835
4836 /*
4837 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4838 * MMIO, it is better to report an internal error.
4839 * See the comments in vmx_handle_exit.
4840 */
4841 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4842 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4843 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4844 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4845 vcpu->run->internal.ndata = 2;
4846 vcpu->run->internal.data[0] = vect_info;
4847 vcpu->run->internal.data[1] = intr_info;
4848 return 0;
4849 }
4850
6aa8b732 4851 if (is_page_fault(intr_info)) {
1439442c 4852 /* EPT won't cause page fault directly */
cf3ace79 4853 BUG_ON(enable_ept);
6aa8b732 4854 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4855 trace_kvm_page_fault(cr2, error_code);
4856
3298b75c 4857 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4858 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4859 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4860 }
4861
d0bfb940 4862 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4863
4864 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4865 return handle_rmode_exception(vcpu, ex_no, error_code);
4866
42dbaa5a
JK		 4867 switch (ex_no) {
4868 case DB_VECTOR:
4869 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4870 if (!(vcpu->guest_debug &
4871 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4872 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4873 kvm_queue_exception(vcpu, DB_VECTOR);
4874 return 1;
4875 }
4876 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4877 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4878 /* fall through */
4879 case BP_VECTOR:
c573cd22
JK		 4880 /*
4881 * Update instruction length as we may reinject #BP from
4882 * user space while in guest debugging mode. Reading it for
4883 * #DB as well causes no harm, it is not used in that case.
4884 */
4885 vmx->vcpu.arch.event_exit_inst_len =
4886 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4887 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4888 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4889 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4890 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4891 break;
4892 default:
d0bfb940
JK		 4893 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4894 kvm_run->ex.exception = ex_no;
4895 kvm_run->ex.error_code = error_code;
42dbaa5a 4896 break;
6aa8b732 4897 }
6aa8b732
AK		 4898 return 0;
4899}
4900
851ba692 4901static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4902{
1165f5fe 4903 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4904 return 1;
4905}
4906
851ba692 4907static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4908{
851ba692 4909 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4910 return 0;
4911}
6aa8b732 4912
851ba692 4913static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4914{
bfdaab09 4915 unsigned long exit_qualification;
34c33d16 4916 int size, in, string;
039576c0 4917 unsigned port;
6aa8b732 4918
bfdaab09 4919 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4920 string = (exit_qualification & 16) != 0;
cf8f70bf 4921 in = (exit_qualification & 8) != 0;
e70669ab 4922
cf8f70bf 4923 ++vcpu->stat.io_exits;
e70669ab 4924
cf8f70bf 4925 if (string || in)
51d8b661 4926 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4927
cf8f70bf
GN		 4928 port = exit_qualification >> 16;
4929 size = (exit_qualification & 7) + 1;
e93f36bc 4930 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4931
4932 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4933}
4934
102d8325
IM		 4935static void
4936vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4937{
4938 /*
4939 * Patch in the VMCALL instruction:
4940 */
4941 hypercall[0] = 0x0f;
4942 hypercall[1] = 0x01;
4943 hypercall[2] = 0xc1;
102d8325
IM		 4944}
4945
92fbc7b1
JK		 4946static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4947{
4948 unsigned long always_on = VMXON_CR0_ALWAYSON;
4949
4950 if (nested_vmx_secondary_ctls_high &
4951 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4952 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4953 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4954 return (val & always_on) == always_on;
4955}
4956
0fa06071 4957/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4958static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4959{
eeadf9e7 4960 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4961 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4962 unsigned long orig_val = val;
4963
eeadf9e7
NHE		 4964 /*
4965 * We get here when L2 changed cr0 in a way that did not change
4966 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4967 * but did change L0 shadowed bits. So we first calculate the
4968 * effective cr0 value that L1 would like to write into the
4969 * hardware. It consists of the L2-owned bits from the new
4970 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4971 */
1a0d74e6
JK		 4972 val = (val & ~vmcs12->cr0_guest_host_mask) |
4973 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4974
92fbc7b1 4975 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4976 return 1;
1a0d74e6
JK		 4977
4978 if (kvm_set_cr0(vcpu, val))
4979 return 1;
4980 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4981 return 0;
1a0d74e6
JK		 4982 } else {
4983 if (to_vmx(vcpu)->nested.vmxon &&
4984 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4985 return 1;
eeadf9e7 4986 return kvm_set_cr0(vcpu, val);
1a0d74e6 4987 }
eeadf9e7
NHE		 4988}
4989
4990static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4991{
4992 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4993 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4994 unsigned long orig_val = val;
4995
4996 /* analogously to handle_set_cr0 */
4997 val = (val & ~vmcs12->cr4_guest_host_mask) |
4998 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4999 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5000 return 1;
1a0d74e6 5001 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5002 return 0;
5003 } else
5004 return kvm_set_cr4(vcpu, val);
5005}
5006
5007/* called to set cr0 as approriate for clts instruction exit. */
5008static void handle_clts(struct kvm_vcpu *vcpu)
5009{
5010 if (is_guest_mode(vcpu)) {
5011 /*
5012 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5013 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5014 * just pretend it's off (also in arch.cr0 for fpu_activate).
5015 */
5016 vmcs_writel(CR0_READ_SHADOW,
5017 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5018 vcpu->arch.cr0 &= ~X86_CR0_TS;
5019 } else
5020 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5021}
5022
851ba692 5023static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5024{
229456fc 5025 unsigned long exit_qualification, val;
6aa8b732
AK		 5026 int cr;
5027 int reg;
49a9b07e 5028 int err;
6aa8b732 5029
bfdaab09 5030 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5031 cr = exit_qualification & 15;
5032 reg = (exit_qualification >> 8) & 15;
5033 switch ((exit_qualification >> 4) & 3) {
5034 case 0: /* mov to cr */
229456fc
MT		 5035 val = kvm_register_read(vcpu, reg);
5036 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5037 switch (cr) {
5038 case 0:
eeadf9e7 5039 err = handle_set_cr0(vcpu, val);
db8fcefa 5040 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5041 return 1;
5042 case 3:
2390218b 5043 err = kvm_set_cr3(vcpu, val);
db8fcefa 5044 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5045 return 1;
5046 case 4:
eeadf9e7 5047 err = handle_set_cr4(vcpu, val);
db8fcefa 5048 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5049 return 1;
0a5fff19
GN		 5050 case 8: {
5051 u8 cr8_prev = kvm_get_cr8(vcpu);
5052 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5053 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5054 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5055 if (irqchip_in_kernel(vcpu->kvm))
5056 return 1;
5057 if (cr8_prev <= cr8)
5058 return 1;
851ba692 5059 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5060 return 0;
5061 }
4b8073e4 5062 }
6aa8b732 5063 break;
25c4c276 5064 case 2: /* clts */
eeadf9e7 5065 handle_clts(vcpu);
4d4ec087 5066 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5067 skip_emulated_instruction(vcpu);
6b52d186 5068 vmx_fpu_activate(vcpu);
25c4c276 5069 return 1;
6aa8b732
AK		 5070 case 1: /*mov from cr*/
5071 switch (cr) {
5072 case 3:
9f8fe504
AK		 5073 val = kvm_read_cr3(vcpu);
5074 kvm_register_write(vcpu, reg, val);
5075 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5076 skip_emulated_instruction(vcpu);
5077 return 1;
5078 case 8:
229456fc
MT		 5079 val = kvm_get_cr8(vcpu);
5080 kvm_register_write(vcpu, reg, val);
5081 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5082 skip_emulated_instruction(vcpu);
5083 return 1;
5084 }
5085 break;
5086 case 3: /* lmsw */
a1f83a74 5087 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5088 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5089 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5090
5091 skip_emulated_instruction(vcpu);
5092 return 1;
5093 default:
5094 break;
5095 }
851ba692 5096 vcpu->run->exit_reason = 0;
a737f256 5097 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5098 (int)(exit_qualification >> 4) & 3, cr);
5099 return 0;
5100}
5101
851ba692 5102static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5103{
bfdaab09 5104 unsigned long exit_qualification;
6aa8b732
AK		 5105 int dr, reg;
5106
f2483415 5107 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5108 if (!kvm_require_cpl(vcpu, 0))
5109 return 1;
42dbaa5a
JK		 5110 dr = vmcs_readl(GUEST_DR7);
5111 if (dr & DR7_GD) {
5112 /*
5113 * As the vm-exit takes precedence over the debug trap, we
5114 * need to emulate the latter, either for the host or the
5115 * guest debugging itself.
5116 */
5117 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5118 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5119 vcpu->run->debug.arch.dr7 = dr;
5120 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5121 vmcs_readl(GUEST_CS_BASE) +
5122 vmcs_readl(GUEST_RIP);
851ba692
AK		 5123 vcpu->run->debug.arch.exception = DB_VECTOR;
5124 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5125 return 0;
5126 } else {
5127 vcpu->arch.dr7 &= ~DR7_GD;
5128 vcpu->arch.dr6 |= DR6_BD;
5129 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5130 kvm_queue_exception(vcpu, DB_VECTOR);
5131 return 1;
5132 }
5133 }
5134
bfdaab09 5135 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5136 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5137 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5138 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5139 unsigned long val;
4c4d563b
JK		 5140
5141 if (kvm_get_dr(vcpu, dr, &val))
5142 return 1;
5143 kvm_register_write(vcpu, reg, val);
020df079 5144 } else
4c4d563b
JK		 5145 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5146 return 1;
5147
6aa8b732
AK		 5148 skip_emulated_instruction(vcpu);
5149 return 1;
5150}
5151
020df079
GN		 5152static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5153{
5154 vmcs_writel(GUEST_DR7, val);
5155}
5156
851ba692 5157static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5158{
06465c5a
AK		 5159 kvm_emulate_cpuid(vcpu);
5160 return 1;
6aa8b732
AK		 5161}
5162
851ba692 5163static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5164{
ad312c7c 5165 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5166 u64 data;
5167
5168 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5169 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5170 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5171 return 1;
5172 }
5173
229456fc 5174 trace_kvm_msr_read(ecx, data);
2714d1d3 5175
6aa8b732 5176 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5177 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5178 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5179 skip_emulated_instruction(vcpu);
5180 return 1;
5181}
5182
851ba692 5183static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5184{
8fe8ab46 5185 struct msr_data msr;
ad312c7c
ZX		 5186 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5187 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5188 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5189
8fe8ab46
WA		 5190 msr.data = data;
5191 msr.index = ecx;
5192 msr.host_initiated = false;
5193 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5194 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5195 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5196 return 1;
5197 }
5198
59200273 5199 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5200 skip_emulated_instruction(vcpu);
5201 return 1;
5202}
5203
851ba692 5204static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5205{
3842d135 5206 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5207 return 1;
5208}
5209
851ba692 5210static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5211{
85f455f7
ED		 5212 u32 cpu_based_vm_exec_control;
5213
5214 /* clear pending irq */
5215 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5216 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5217 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5218
3842d135
AK		 5219 kvm_make_request(KVM_REQ_EVENT, vcpu);
5220
a26bf12a 5221 ++vcpu->stat.irq_window_exits;
2714d1d3 5222
c1150d8c
DL		 5223 /*
5224 * If the user space waits to inject interrupts, exit as soon as
5225 * possible
5226 */
8061823a 5227 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5228 vcpu->run->request_interrupt_window &&
8061823a 5229 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5230 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5231 return 0;
5232 }
6aa8b732
AK		 5233 return 1;
5234}
5235
851ba692 5236static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5237{
5238 skip_emulated_instruction(vcpu);
d3bef15f 5239 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5240}
5241
851ba692 5242static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5243{
510043da 5244 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5245 kvm_emulate_hypercall(vcpu);
5246 return 1;
c21415e8
IM		 5247}
5248
ec25d5e6
GN		 5249static int handle_invd(struct kvm_vcpu *vcpu)
5250{
51d8b661 5251 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5252}
5253
851ba692 5254static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5255{
f9c617f6 5256 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5257
5258 kvm_mmu_invlpg(vcpu, exit_qualification);
5259 skip_emulated_instruction(vcpu);
5260 return 1;
5261}
5262
fee84b07
AK		 5263static int handle_rdpmc(struct kvm_vcpu *vcpu)
5264{
5265 int err;
5266
5267 err = kvm_rdpmc(vcpu);
5268 kvm_complete_insn_gp(vcpu, err);
5269
5270 return 1;
5271}
5272
851ba692 5273static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5274{
5275 skip_emulated_instruction(vcpu);
f5f48ee1 5276 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5277 return 1;
5278}
5279
2acf923e
DC		 5280static int handle_xsetbv(struct kvm_vcpu *vcpu)
5281{
5282 u64 new_bv = kvm_read_edx_eax(vcpu);
5283 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5284
5285 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5286 skip_emulated_instruction(vcpu);
5287 return 1;
5288}
5289
851ba692 5290static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5291{
58fbbf26
KT		 5292 if (likely(fasteoi)) {
5293 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5294 int access_type, offset;
5295
5296 access_type = exit_qualification & APIC_ACCESS_TYPE;
5297 offset = exit_qualification & APIC_ACCESS_OFFSET;
5298 /*
5299 * Sane guest uses MOV to write EOI, with written value
5300 * not cared. So make a short-circuit here by avoiding
5301 * heavy instruction emulation.
5302 */
5303 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5304 (offset == APIC_EOI)) {
5305 kvm_lapic_set_eoi(vcpu);
5306 skip_emulated_instruction(vcpu);
5307 return 1;
5308 }
5309 }
51d8b661 5310 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5311}
5312
c7c9c56c
YZ		 5313static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5314{
5315 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5316 int vector = exit_qualification & 0xff;
5317
5318 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5319 kvm_apic_set_eoi_accelerated(vcpu, vector);
5320 return 1;
5321}
5322
83d4c286
YZ		 5323static int handle_apic_write(struct kvm_vcpu *vcpu)
5324{
5325 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5326 u32 offset = exit_qualification & 0xfff;
5327
5328 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5329 kvm_apic_write_nodecode(vcpu, offset);
5330 return 1;
5331}
5332
851ba692 5333static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5334{
60637aac 5335 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5336 unsigned long exit_qualification;
e269fb21
JK		 5337 bool has_error_code = false;
5338 u32 error_code = 0;
37817f29 5339 u16 tss_selector;
7f3d35fd 5340 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5341
5342 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5343 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5344 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5345
5346 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5347
5348 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5349 if (reason == TASK_SWITCH_GATE && idt_v) {
5350 switch (type) {
5351 case INTR_TYPE_NMI_INTR:
5352 vcpu->arch.nmi_injected = false;
654f06fc 5353 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5354 break;
5355 case INTR_TYPE_EXT_INTR:
66fd3f7f 5356 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5357 kvm_clear_interrupt_queue(vcpu);
5358 break;
5359 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5360 if (vmx->idt_vectoring_info &
5361 VECTORING_INFO_DELIVER_CODE_MASK) {
5362 has_error_code = true;
5363 error_code =
5364 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5365 }
5366 /* fall through */
64a7ec06
GN		 5367 case INTR_TYPE_SOFT_EXCEPTION:
5368 kvm_clear_exception_queue(vcpu);
5369 break;
5370 default:
5371 break;
5372 }
60637aac 5373 }
37817f29
IE		 5374 tss_selector = exit_qualification;
5375
64a7ec06
GN		 5376 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5377 type != INTR_TYPE_EXT_INTR &&
5378 type != INTR_TYPE_NMI_INTR))
5379 skip_emulated_instruction(vcpu);
5380
7f3d35fd
KW		 5381 if (kvm_task_switch(vcpu, tss_selector,
5382 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5383 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5384 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5385 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5386 vcpu->run->internal.ndata = 0;
42dbaa5a 5387 return 0;
acb54517 5388 }
42dbaa5a
JK		 5389
5390 /* clear all local breakpoint enable flags */
5391 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5392
5393 /*
5394 * TODO: What about debug traps on tss switch?
5395 * Are we supposed to inject them and update dr6?
5396 */
5397
5398 return 1;
37817f29
IE		 5399}
5400
851ba692 5401static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5402{
f9c617f6 5403 unsigned long exit_qualification;
1439442c 5404 gpa_t gpa;
4f5982a5 5405 u32 error_code;
1439442c 5406 int gla_validity;
1439442c 5407
f9c617f6 5408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5409
1439442c
SY		 5410 gla_validity = (exit_qualification >> 7) & 0x3;
5411 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5412 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5413 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5414 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5415 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5416 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5417 (long unsigned int)exit_qualification);
851ba692
AK		 5418 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5419 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5420 return 0;
1439442c
SY		 5421 }
5422
0be9c7a8
GN		 5423 /*
5424 * EPT violation happened while executing iret from NMI,
5425 * "blocked by NMI" bit has to be set before next VM entry.
5426 * There are errata that may cause this bit to not be set:
5427 * AAK134, BY25.
5428 */
bcd1c294
GN		 5429 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5430 cpu_has_virtual_nmis() &&
5431 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5432 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5433
1439442c 5434 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5435 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5436
5437 /* It is a write fault? */
5438 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5439 /* It is a fetch fault? */
5440 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5441 /* ept page table is present? */
5442 error_code |= (exit_qualification >> 3) & 0x1;
5443
25d92081
YZ		 5444 vcpu->arch.exit_qualification = exit_qualification;
5445
4f5982a5 5446 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5447}
5448
68f89400
MT		 5449static u64 ept_rsvd_mask(u64 spte, int level)
5450{
5451 int i;
5452 u64 mask = 0;
5453
5454 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5455 mask |= (1ULL << i);
5456
5457 if (level > 2)
5458 /* bits 7:3 reserved */
5459 mask |= 0xf8;
5460 else if (level == 2) {
5461 if (spte & (1ULL << 7))
5462 /* 2MB ref, bits 20:12 reserved */
5463 mask |= 0x1ff000;
5464 else
5465 /* bits 6:3 reserved */
5466 mask |= 0x78;
5467 }
5468
5469 return mask;
5470}
5471
5472static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5473 int level)
5474{
5475 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5476
5477 /* 010b (write-only) */
5478 WARN_ON((spte & 0x7) == 0x2);
5479
5480 /* 110b (write/execute) */
5481 WARN_ON((spte & 0x7) == 0x6);
5482
5483 /* 100b (execute-only) and value not supported by logical processor */
5484 if (!cpu_has_vmx_ept_execute_only())
5485 WARN_ON((spte & 0x7) == 0x4);
5486
5487 /* not 000b */
5488 if ((spte & 0x7)) {
5489 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5490
5491 if (rsvd_bits != 0) {
5492 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5493 __func__, rsvd_bits);
5494 WARN_ON(1);
5495 }
5496
5497 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5498 u64 ept_mem_type = (spte & 0x38) >> 3;
5499
5500 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5501 ept_mem_type == 7) {
5502 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5503 __func__, ept_mem_type);
5504 WARN_ON(1);
5505 }
5506 }
5507 }
5508}
5509
851ba692 5510static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5511{
5512 u64 sptes[4];
ce88decf 5513 int nr_sptes, i, ret;
68f89400
MT		 5514 gpa_t gpa;
5515
5516 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5517
ce88decf 5518 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5519 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5520 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5521 EMULATE_DONE;
f8f55942
XG		 5522
5523 if (unlikely(ret == RET_MMIO_PF_INVALID))
5524 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5525
b37fbea6 5526 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5527 return 1;
5528
5529 /* It is the real ept misconfig */
68f89400
MT		 5530 printk(KERN_ERR "EPT: Misconfiguration.\n");
5531 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5532
5533 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5534
5535 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5536 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5537
851ba692
AK		 5538 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5539 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5540
5541 return 0;
5542}
5543
851ba692 5544static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5545{
5546 u32 cpu_based_vm_exec_control;
5547
5548 /* clear pending NMI */
5549 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5550 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5552 ++vcpu->stat.nmi_window_exits;
3842d135 5553 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5554
5555 return 1;
5556}
5557
80ced186 5558static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5559{
8b3079a5
AK		 5560 struct vcpu_vmx *vmx = to_vmx(vcpu);
5561 enum emulation_result err = EMULATE_DONE;
80ced186 5562 int ret = 1;
49e9d557
AK		 5563 u32 cpu_exec_ctrl;
5564 bool intr_window_requested;
b8405c18 5565 unsigned count = 130;
49e9d557
AK		 5566
5567 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5568 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5569
b8405c18 5570 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5571 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5572 return handle_interrupt_window(&vmx->vcpu);
5573
de87dcdd
AK		 5574 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5575 return 1;
5576
991eebf9 5577 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5578
ac0a48c3 5579 if (err == EMULATE_USER_EXIT) {
94452b9e 5580 ++vcpu->stat.mmio_exits;
80ced186
MG		 5581 ret = 0;
5582 goto out;
5583 }
1d5a4d9b 5584
de5f70e0
AK		 5585 if (err != EMULATE_DONE) {
5586 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5587 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5588 vcpu->run->internal.ndata = 0;
6d77dbfc 5589 return 0;
de5f70e0 5590 }
ea953ef0 5591
8d76c49e
GN		 5592 if (vcpu->arch.halt_request) {
5593 vcpu->arch.halt_request = 0;
5594 ret = kvm_emulate_halt(vcpu);
5595 goto out;
5596 }
5597
ea953ef0 5598 if (signal_pending(current))
80ced186 5599 goto out;
ea953ef0
MG		 5600 if (need_resched())
5601 schedule();
5602 }
5603
14168786 5604 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5605out:
5606 return ret;
ea953ef0
MG		 5607}
5608
4b8d54f9
ZE		 5609/*
5610 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5611 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5612 */
9fb41ba8 5613static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5614{
5615 skip_emulated_instruction(vcpu);
5616 kvm_vcpu_on_spin(vcpu);
5617
5618 return 1;
5619}
5620
59708670
SY		 5621static int handle_invalid_op(struct kvm_vcpu *vcpu)
5622{
5623 kvm_queue_exception(vcpu, UD_VECTOR);
5624 return 1;
5625}
5626
ff2f6fe9
NHE		 5627/*
5628 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5629 * We could reuse a single VMCS for all the L2 guests, but we also want the
5630 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5631 * allows keeping them loaded on the processor, and in the future will allow
5632 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5633 * every entry if they never change.
5634 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5635 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5636 *
5637 * The following functions allocate and free a vmcs02 in this pool.
5638 */
5639
5640/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5641static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5642{
5643 struct vmcs02_list *item;
5644 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5645 if (item->vmptr == vmx->nested.current_vmptr) {
5646 list_move(&item->list, &vmx->nested.vmcs02_pool);
5647 return &item->vmcs02;
5648 }
5649
5650 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5651 /* Recycle the least recently used VMCS. */
5652 item = list_entry(vmx->nested.vmcs02_pool.prev,
5653 struct vmcs02_list, list);
5654 item->vmptr = vmx->nested.current_vmptr;
5655 list_move(&item->list, &vmx->nested.vmcs02_pool);
5656 return &item->vmcs02;
5657 }
5658
5659 /* Create a new VMCS */
0fa24ce3 5660 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5661 if (!item)
5662 return NULL;
5663 item->vmcs02.vmcs = alloc_vmcs();
5664 if (!item->vmcs02.vmcs) {
5665 kfree(item);
5666 return NULL;
5667 }
5668 loaded_vmcs_init(&item->vmcs02);
5669 item->vmptr = vmx->nested.current_vmptr;
5670 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5671 vmx->nested.vmcs02_num++;
5672 return &item->vmcs02;
5673}
5674
5675/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5676static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5677{
5678 struct vmcs02_list *item;
5679 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5680 if (item->vmptr == vmptr) {
5681 free_loaded_vmcs(&item->vmcs02);
5682 list_del(&item->list);
5683 kfree(item);
5684 vmx->nested.vmcs02_num--;
5685 return;
5686 }
5687}
5688
5689/*
5690 * Free all VMCSs saved for this vcpu, except the one pointed by
5691 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5692 * currently used, if running L2), and vmcs01 when running L2.
5693 */
5694static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5695{
5696 struct vmcs02_list *item, *n;
5697 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5698 if (vmx->loaded_vmcs != &item->vmcs02)
5699 free_loaded_vmcs(&item->vmcs02);
5700 list_del(&item->list);
5701 kfree(item);
5702 }
5703 vmx->nested.vmcs02_num = 0;
5704
5705 if (vmx->loaded_vmcs != &vmx->vmcs01)
5706 free_loaded_vmcs(&vmx->vmcs01);
5707}
5708
0658fbaa
ACL		 5709/*
5710 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5711 * set the success or error code of an emulated VMX instruction, as specified
5712 * by Vol 2B, VMX Instruction Reference, "Conventions".
5713 */
5714static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5715{
5716 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5717 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5718 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5719}
5720
5721static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5722{
5723 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5724 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5725 X86_EFLAGS_SF | X86_EFLAGS_OF))
5726 | X86_EFLAGS_CF);
5727}
5728
145c28dd 5729static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5730 u32 vm_instruction_error)
5731{
5732 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5733 /*
5734 * failValid writes the error number to the current VMCS, which
5735 * can't be done there isn't a current VMCS.
5736 */
5737 nested_vmx_failInvalid(vcpu);
5738 return;
5739 }
5740 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5741 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5742 X86_EFLAGS_SF | X86_EFLAGS_OF))
5743 | X86_EFLAGS_ZF);
5744 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5745 /*
5746 * We don't need to force a shadow sync because
5747 * VM_INSTRUCTION_ERROR is not shadowed
5748 */
5749}
145c28dd 5750
ec378aee
NHE		 5751/*
5752 * Emulate the VMXON instruction.
5753 * Currently, we just remember that VMX is active, and do not save or even
5754 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5755 * do not currently need to store anything in that guest-allocated memory
5756 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5757 * argument is different from the VMXON pointer (which the spec says they do).
5758 */
5759static int handle_vmon(struct kvm_vcpu *vcpu)
5760{
5761 struct kvm_segment cs;
5762 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5763 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5764 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5765 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5766
5767 /* The Intel VMX Instruction Reference lists a bunch of bits that
5768 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5769 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5770 * Otherwise, we should fail with #UD. We test these now:
5771 */
5772 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5773 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5774 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5775 kvm_queue_exception(vcpu, UD_VECTOR);
5776 return 1;
5777 }
5778
5779 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5780 if (is_long_mode(vcpu) && !cs.l) {
5781 kvm_queue_exception(vcpu, UD_VECTOR);
5782 return 1;
5783 }
5784
5785 if (vmx_get_cpl(vcpu)) {
5786 kvm_inject_gp(vcpu, 0);
5787 return 1;
5788 }
145c28dd
AG		 5789 if (vmx->nested.vmxon) {
5790 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5791 skip_emulated_instruction(vcpu);
5792 return 1;
5793 }
b3897a49
NHE		 5794
5795 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5796 != VMXON_NEEDED_FEATURES) {
5797 kvm_inject_gp(vcpu, 0);
5798 return 1;
5799 }
5800
8de48833
AG		 5801 if (enable_shadow_vmcs) {
5802 shadow_vmcs = alloc_vmcs();
5803 if (!shadow_vmcs)
5804 return -ENOMEM;
5805 /* mark vmcs as shadow */
5806 shadow_vmcs->revision_id |= (1u << 31);
5807 /* init shadow vmcs */
5808 vmcs_clear(shadow_vmcs);
5809 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5810 }
ec378aee 5811
ff2f6fe9
NHE		 5812 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5813 vmx->nested.vmcs02_num = 0;
5814
ec378aee
NHE		 5815 vmx->nested.vmxon = true;
5816
5817 skip_emulated_instruction(vcpu);
a25eb114 5818 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5819 return 1;
5820}
5821
5822/*
5823 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5824 * for running VMX instructions (except VMXON, whose prerequisites are
5825 * slightly different). It also specifies what exception to inject otherwise.
5826 */
5827static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5828{
5829 struct kvm_segment cs;
5830 struct vcpu_vmx *vmx = to_vmx(vcpu);
5831
5832 if (!vmx->nested.vmxon) {
5833 kvm_queue_exception(vcpu, UD_VECTOR);
5834 return 0;
5835 }
5836
5837 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5838 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5839 (is_long_mode(vcpu) && !cs.l)) {
5840 kvm_queue_exception(vcpu, UD_VECTOR);
5841 return 0;
5842 }
5843
5844 if (vmx_get_cpl(vcpu)) {
5845 kvm_inject_gp(vcpu, 0);
5846 return 0;
5847 }
5848
5849 return 1;
5850}
5851
e7953d7f
AG		 5852static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5853{
8a1b9dd0 5854 u32 exec_control;
012f83cb
AG		 5855 if (enable_shadow_vmcs) {
5856 if (vmx->nested.current_vmcs12 != NULL) {
5857 /* copy to memory all shadowed fields in case
5858 they were modified */
5859 copy_shadow_to_vmcs12(vmx);
5860 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5861 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5862 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5863 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5864 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5865 }
5866 }
e7953d7f
AG		 5867 kunmap(vmx->nested.current_vmcs12_page);
5868 nested_release_page(vmx->nested.current_vmcs12_page);
5869}
5870
ec378aee
NHE		 5871/*
5872 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5873 * just stops using VMX.
5874 */
5875static void free_nested(struct vcpu_vmx *vmx)
5876{
5877 if (!vmx->nested.vmxon)
5878 return;
5879 vmx->nested.vmxon = false;
a9d30f33 5880 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5881 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5882 vmx->nested.current_vmptr = -1ull;
5883 vmx->nested.current_vmcs12 = NULL;
5884 }
e7953d7f
AG		 5885 if (enable_shadow_vmcs)
5886 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5887 /* Unpin physical memory we referred to in current vmcs02 */
5888 if (vmx->nested.apic_access_page) {
5889 nested_release_page(vmx->nested.apic_access_page);
5890 vmx->nested.apic_access_page = 0;
5891 }
ff2f6fe9
NHE		 5892
5893 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5894}
5895
5896/* Emulate the VMXOFF instruction */
5897static int handle_vmoff(struct kvm_vcpu *vcpu)
5898{
5899 if (!nested_vmx_check_permission(vcpu))
5900 return 1;
5901 free_nested(to_vmx(vcpu));
5902 skip_emulated_instruction(vcpu);
a25eb114 5903 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5904 return 1;
5905}
5906
064aea77
NHE		 5907/*
5908 * Decode the memory-address operand of a vmx instruction, as recorded on an
5909 * exit caused by such an instruction (run by a guest hypervisor).
5910 * On success, returns 0. When the operand is invalid, returns 1 and throws
5911 * #UD or #GP.
5912 */
5913static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5914 unsigned long exit_qualification,
5915 u32 vmx_instruction_info, gva_t *ret)
5916{
5917 /*
5918 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5919 * Execution", on an exit, vmx_instruction_info holds most of the
5920 * addressing components of the operand. Only the displacement part
5921 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5922 * For how an actual address is calculated from all these components,
5923 * refer to Vol. 1, "Operand Addressing".
5924 */
5925 int scaling = vmx_instruction_info & 3;
5926 int addr_size = (vmx_instruction_info >> 7) & 7;
5927 bool is_reg = vmx_instruction_info & (1u << 10);
5928 int seg_reg = (vmx_instruction_info >> 15) & 7;
5929 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5930 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5931 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5932 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5933
5934 if (is_reg) {
5935 kvm_queue_exception(vcpu, UD_VECTOR);
5936 return 1;
5937 }
5938
5939 /* Addr = segment_base + offset */
5940 /* offset = base + [index * scale] + displacement */
5941 *ret = vmx_get_segment_base(vcpu, seg_reg);
5942 if (base_is_valid)
5943 *ret += kvm_register_read(vcpu, base_reg);
5944 if (index_is_valid)
5945 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5946 *ret += exit_qualification; /* holds the displacement */
5947
5948 if (addr_size == 1) /* 32 bit */
5949 *ret &= 0xffffffff;
5950
5951 /*
5952 * TODO: throw #GP (and return 1) in various cases that the VM*
5953 * instructions require it - e.g., offset beyond segment limit,
5954 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5955 * address, and so on. Currently these are not checked.
5956 */
5957 return 0;
5958}
5959
27d6c865
NHE		 5960/* Emulate the VMCLEAR instruction */
5961static int handle_vmclear(struct kvm_vcpu *vcpu)
5962{
5963 struct vcpu_vmx *vmx = to_vmx(vcpu);
5964 gva_t gva;
5965 gpa_t vmptr;
5966 struct vmcs12 *vmcs12;
5967 struct page *page;
5968 struct x86_exception e;
5969
5970 if (!nested_vmx_check_permission(vcpu))
5971 return 1;
5972
5973 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5974 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5975 return 1;
5976
5977 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5978 sizeof(vmptr), &e)) {
5979 kvm_inject_page_fault(vcpu, &e);
5980 return 1;
5981 }
5982
5983 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5984 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5985 skip_emulated_instruction(vcpu);
5986 return 1;
5987 }
5988
5989 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5990 nested_release_vmcs12(vmx);
27d6c865
NHE		 5991 vmx->nested.current_vmptr = -1ull;
5992 vmx->nested.current_vmcs12 = NULL;
5993 }
5994
5995 page = nested_get_page(vcpu, vmptr);
5996 if (page == NULL) {
5997 /*
5998 * For accurate processor emulation, VMCLEAR beyond available
5999 * physical memory should do nothing at all. However, it is
6000 * possible that a nested vmx bug, not a guest hypervisor bug,
6001 * resulted in this case, so let's shut down before doing any
6002 * more damage:
6003 */
6004 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6005 return 1;
6006 }
6007 vmcs12 = kmap(page);
6008 vmcs12->launch_state = 0;
6009 kunmap(page);
6010 nested_release_page(page);
6011
6012 nested_free_vmcs02(vmx, vmptr);
6013
6014 skip_emulated_instruction(vcpu);
6015 nested_vmx_succeed(vcpu);
6016 return 1;
6017}
6018
cd232ad0
NHE		 6019static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6020
6021/* Emulate the VMLAUNCH instruction */
6022static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6023{
6024 return nested_vmx_run(vcpu, true);
6025}
6026
6027/* Emulate the VMRESUME instruction */
6028static int handle_vmresume(struct kvm_vcpu *vcpu)
6029{
6030
6031 return nested_vmx_run(vcpu, false);
6032}
6033
49f705c5
NHE		 6034enum vmcs_field_type {
6035 VMCS_FIELD_TYPE_U16 = 0,
6036 VMCS_FIELD_TYPE_U64 = 1,
6037 VMCS_FIELD_TYPE_U32 = 2,
6038 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6039};
6040
6041static inline int vmcs_field_type(unsigned long field)
6042{
6043 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6044 return VMCS_FIELD_TYPE_U32;
6045 return (field >> 13) & 0x3 ;
6046}
6047
6048static inline int vmcs_field_readonly(unsigned long field)
6049{
6050 return (((field >> 10) & 0x3) == 1);
6051}
6052
6053/*
6054 * Read a vmcs12 field. Since these can have varying lengths and we return
6055 * one type, we chose the biggest type (u64) and zero-extend the return value
6056 * to that size. Note that the caller, handle_vmread, might need to use only
6057 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6058 * 64-bit fields are to be returned).
6059 */
6060static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6061 unsigned long field, u64 *ret)
6062{
6063 short offset = vmcs_field_to_offset(field);
6064 char *p;
6065
6066 if (offset < 0)
6067 return 0;
6068
6069 p = ((char *)(get_vmcs12(vcpu))) + offset;
6070
6071 switch (vmcs_field_type(field)) {
6072 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6073 *ret = *((natural_width *)p);
6074 return 1;
6075 case VMCS_FIELD_TYPE_U16:
6076 *ret = *((u16 *)p);
6077 return 1;
6078 case VMCS_FIELD_TYPE_U32:
6079 *ret = *((u32 *)p);
6080 return 1;
6081 case VMCS_FIELD_TYPE_U64:
6082 *ret = *((u64 *)p);
6083 return 1;
6084 default:
6085 return 0; /* can never happen. */
6086 }
6087}
6088
20b97fea
AG		 6089
6090static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6091 unsigned long field, u64 field_value){
6092 short offset = vmcs_field_to_offset(field);
6093 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6094 if (offset < 0)
6095 return false;
6096
6097 switch (vmcs_field_type(field)) {
6098 case VMCS_FIELD_TYPE_U16:
6099 *(u16 *)p = field_value;
6100 return true;
6101 case VMCS_FIELD_TYPE_U32:
6102 *(u32 *)p = field_value;
6103 return true;
6104 case VMCS_FIELD_TYPE_U64:
6105 *(u64 *)p = field_value;
6106 return true;
6107 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6108 *(natural_width *)p = field_value;
6109 return true;
6110 default:
6111 return false; /* can never happen. */
6112 }
6113
6114}
6115
16f5b903
AG		 6116static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6117{
6118 int i;
6119 unsigned long field;
6120 u64 field_value;
6121 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6122 const unsigned long *fields = shadow_read_write_fields;
6123 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6124
6125 vmcs_load(shadow_vmcs);
6126
6127 for (i = 0; i < num_fields; i++) {
6128 field = fields[i];
6129 switch (vmcs_field_type(field)) {
6130 case VMCS_FIELD_TYPE_U16:
6131 field_value = vmcs_read16(field);
6132 break;
6133 case VMCS_FIELD_TYPE_U32:
6134 field_value = vmcs_read32(field);
6135 break;
6136 case VMCS_FIELD_TYPE_U64:
6137 field_value = vmcs_read64(field);
6138 break;
6139 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6140 field_value = vmcs_readl(field);
6141 break;
6142 }
6143 vmcs12_write_any(&vmx->vcpu, field, field_value);
6144 }
6145
6146 vmcs_clear(shadow_vmcs);
6147 vmcs_load(vmx->loaded_vmcs->vmcs);
6148}
6149
c3114420
AG		 6150static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6151{
c2bae893
MK		 6152 const unsigned long *fields[] = {
6153 shadow_read_write_fields,
6154 shadow_read_only_fields
c3114420 6155 };
c2bae893 6156 const int max_fields[] = {
c3114420
AG		 6157 max_shadow_read_write_fields,
6158 max_shadow_read_only_fields
6159 };
6160 int i, q;
6161 unsigned long field;
6162 u64 field_value = 0;
6163 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6164
6165 vmcs_load(shadow_vmcs);
6166
c2bae893 6167 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6168 for (i = 0; i < max_fields[q]; i++) {
6169 field = fields[q][i];
6170 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6171
6172 switch (vmcs_field_type(field)) {
6173 case VMCS_FIELD_TYPE_U16:
6174 vmcs_write16(field, (u16)field_value);
6175 break;
6176 case VMCS_FIELD_TYPE_U32:
6177 vmcs_write32(field, (u32)field_value);
6178 break;
6179 case VMCS_FIELD_TYPE_U64:
6180 vmcs_write64(field, (u64)field_value);
6181 break;
6182 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6183 vmcs_writel(field, (long)field_value);
6184 break;
6185 }
6186 }
6187 }
6188
6189 vmcs_clear(shadow_vmcs);
6190 vmcs_load(vmx->loaded_vmcs->vmcs);
6191}
6192
49f705c5
NHE		 6193/*
6194 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6195 * used before) all generate the same failure when it is missing.
6196 */
6197static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6198{
6199 struct vcpu_vmx *vmx = to_vmx(vcpu);
6200 if (vmx->nested.current_vmptr == -1ull) {
6201 nested_vmx_failInvalid(vcpu);
6202 skip_emulated_instruction(vcpu);
6203 return 0;
6204 }
6205 return 1;
6206}
6207
6208static int handle_vmread(struct kvm_vcpu *vcpu)
6209{
6210 unsigned long field;
6211 u64 field_value;
6212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6213 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6214 gva_t gva = 0;
6215
6216 if (!nested_vmx_check_permission(vcpu) ||
6217 !nested_vmx_check_vmcs12(vcpu))
6218 return 1;
6219
6220 /* Decode instruction info and find the field to read */
6221 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6222 /* Read the field, zero-extended to a u64 field_value */
6223 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6224 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6225 skip_emulated_instruction(vcpu);
6226 return 1;
6227 }
6228 /*
6229 * Now copy part of this value to register or memory, as requested.
6230 * Note that the number of bits actually copied is 32 or 64 depending
6231 * on the guest's mode (32 or 64 bit), not on the given field's length.
6232 */
6233 if (vmx_instruction_info & (1u << 10)) {
6234 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6235 field_value);
6236 } else {
6237 if (get_vmx_mem_address(vcpu, exit_qualification,
6238 vmx_instruction_info, &gva))
6239 return 1;
6240 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6241 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6242 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6243 }
6244
6245 nested_vmx_succeed(vcpu);
6246 skip_emulated_instruction(vcpu);
6247 return 1;
6248}
6249
6250
6251static int handle_vmwrite(struct kvm_vcpu *vcpu)
6252{
6253 unsigned long field;
6254 gva_t gva;
6255 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6256 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6257 /* The value to write might be 32 or 64 bits, depending on L1's long
6258 * mode, and eventually we need to write that into a field of several
6259 * possible lengths. The code below first zero-extends the value to 64
6260 * bit (field_value), and then copies only the approriate number of
6261 * bits into the vmcs12 field.
6262 */
6263 u64 field_value = 0;
6264 struct x86_exception e;
6265
6266 if (!nested_vmx_check_permission(vcpu) ||
6267 !nested_vmx_check_vmcs12(vcpu))
6268 return 1;
6269
6270 if (vmx_instruction_info & (1u << 10))
6271 field_value = kvm_register_read(vcpu,
6272 (((vmx_instruction_info) >> 3) & 0xf));
6273 else {
6274 if (get_vmx_mem_address(vcpu, exit_qualification,
6275 vmx_instruction_info, &gva))
6276 return 1;
6277 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6278 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6279 kvm_inject_page_fault(vcpu, &e);
6280 return 1;
6281 }
6282 }
6283
6284
6285 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6286 if (vmcs_field_readonly(field)) {
6287 nested_vmx_failValid(vcpu,
6288 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6289 skip_emulated_instruction(vcpu);
6290 return 1;
6291 }
6292
20b97fea 6293 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6294 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6295 skip_emulated_instruction(vcpu);
6296 return 1;
6297 }
6298
6299 nested_vmx_succeed(vcpu);
6300 skip_emulated_instruction(vcpu);
6301 return 1;
6302}
6303
63846663
NHE		 6304/* Emulate the VMPTRLD instruction */
6305static int handle_vmptrld(struct kvm_vcpu *vcpu)
6306{
6307 struct vcpu_vmx *vmx = to_vmx(vcpu);
6308 gva_t gva;
6309 gpa_t vmptr;
6310 struct x86_exception e;
8a1b9dd0 6311 u32 exec_control;
63846663
NHE		 6312
6313 if (!nested_vmx_check_permission(vcpu))
6314 return 1;
6315
6316 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6317 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6318 return 1;
6319
6320 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6321 sizeof(vmptr), &e)) {
6322 kvm_inject_page_fault(vcpu, &e);
6323 return 1;
6324 }
6325
6326 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6327 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6328 skip_emulated_instruction(vcpu);
6329 return 1;
6330 }
6331
6332 if (vmx->nested.current_vmptr != vmptr) {
6333 struct vmcs12 *new_vmcs12;
6334 struct page *page;
6335 page = nested_get_page(vcpu, vmptr);
6336 if (page == NULL) {
6337 nested_vmx_failInvalid(vcpu);
6338 skip_emulated_instruction(vcpu);
6339 return 1;
6340 }
6341 new_vmcs12 = kmap(page);
6342 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6343 kunmap(page);
6344 nested_release_page_clean(page);
6345 nested_vmx_failValid(vcpu,
6346 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6347 skip_emulated_instruction(vcpu);
6348 return 1;
6349 }
e7953d7f
AG		 6350 if (vmx->nested.current_vmptr != -1ull)
6351 nested_release_vmcs12(vmx);
63846663
NHE		 6352
6353 vmx->nested.current_vmptr = vmptr;
6354 vmx->nested.current_vmcs12 = new_vmcs12;
6355 vmx->nested.current_vmcs12_page = page;
012f83cb 6356 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6357 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6358 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6359 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6360 vmcs_write64(VMCS_LINK_POINTER,
6361 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6362 vmx->nested.sync_shadow_vmcs = true;
6363 }
63846663
NHE		 6364 }
6365
6366 nested_vmx_succeed(vcpu);
6367 skip_emulated_instruction(vcpu);
6368 return 1;
6369}
6370
6a4d7550
NHE		 6371/* Emulate the VMPTRST instruction */
6372static int handle_vmptrst(struct kvm_vcpu *vcpu)
6373{
6374 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6375 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6376 gva_t vmcs_gva;
6377 struct x86_exception e;
6378
6379 if (!nested_vmx_check_permission(vcpu))
6380 return 1;
6381
6382 if (get_vmx_mem_address(vcpu, exit_qualification,
6383 vmx_instruction_info, &vmcs_gva))
6384 return 1;
6385 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6386 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6387 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6388 sizeof(u64), &e)) {
6389 kvm_inject_page_fault(vcpu, &e);
6390 return 1;
6391 }
6392 nested_vmx_succeed(vcpu);
6393 skip_emulated_instruction(vcpu);
6394 return 1;
6395}
6396
bfd0a56b
NHE		 6397/* Emulate the INVEPT instruction */
6398static int handle_invept(struct kvm_vcpu *vcpu)
6399{
6400 u32 vmx_instruction_info, types;
6401 unsigned long type;
6402 gva_t gva;
6403 struct x86_exception e;
6404 struct {
6405 u64 eptp, gpa;
6406 } operand;
6407 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6408
6409 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6410 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6411 kvm_queue_exception(vcpu, UD_VECTOR);
6412 return 1;
6413 }
6414
6415 if (!nested_vmx_check_permission(vcpu))
6416 return 1;
6417
6418 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6419 kvm_queue_exception(vcpu, UD_VECTOR);
6420 return 1;
6421 }
6422
6423 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6424 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6425
6426 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6427
6428 if (!(types & (1UL << type))) {
6429 nested_vmx_failValid(vcpu,
6430 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6431 return 1;
6432 }
6433
6434 /* According to the Intel VMX instruction reference, the memory
6435 * operand is read even if it isn't needed (e.g., for type==global)
6436 */
6437 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6438 vmx_instruction_info, &gva))
6439 return 1;
6440 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6441 sizeof(operand), &e)) {
6442 kvm_inject_page_fault(vcpu, &e);
6443 return 1;
6444 }
6445
6446 switch (type) {
6447 case VMX_EPT_EXTENT_CONTEXT:
6448 if ((operand.eptp & eptp_mask) !=
6449 (nested_ept_get_cr3(vcpu) & eptp_mask))
6450 break;
6451 case VMX_EPT_EXTENT_GLOBAL:
6452 kvm_mmu_sync_roots(vcpu);
6453 kvm_mmu_flush_tlb(vcpu);
6454 nested_vmx_succeed(vcpu);
6455 break;
6456 default:
6457 BUG_ON(1);
6458 break;
6459 }
6460
6461 skip_emulated_instruction(vcpu);
6462 return 1;
6463}
6464
6aa8b732
AK		 6465/*
6466 * The exit handlers return 1 if the exit was handled fully and guest execution
6467 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6468 * to be done to userspace and return 0.
6469 */
772e0318 6470static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6471 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6472 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6473 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6474 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6475 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6476 [EXIT_REASON_CR_ACCESS] = handle_cr,
6477 [EXIT_REASON_DR_ACCESS] = handle_dr,
6478 [EXIT_REASON_CPUID] = handle_cpuid,
6479 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6480 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6481 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6482 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6483 [EXIT_REASON_INVD] = handle_invd,
a7052897 6484 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6485 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6486 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6487 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6488 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6489 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6490 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6491 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6492 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6493 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6494 [EXIT_REASON_VMOFF] = handle_vmoff,
6495 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6496 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6497 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6498 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6499 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6500 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6501 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6502 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6503 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6504 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6505 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6506 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6507 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6508 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6509 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6510};
6511
6512static const int kvm_vmx_max_exit_handlers =
50a3485c 6513 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6514
908a7bdd
JK		 6515static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6516 struct vmcs12 *vmcs12)
6517{
6518 unsigned long exit_qualification;
6519 gpa_t bitmap, last_bitmap;
6520 unsigned int port;
6521 int size;
6522 u8 b;
6523
908a7bdd 6524 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6525 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6526
6527 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6528
6529 port = exit_qualification >> 16;
6530 size = (exit_qualification & 7) + 1;
6531
6532 last_bitmap = (gpa_t)-1;
6533 b = -1;
6534
6535 while (size > 0) {
6536 if (port < 0x8000)
6537 bitmap = vmcs12->io_bitmap_a;
6538 else if (port < 0x10000)
6539 bitmap = vmcs12->io_bitmap_b;
6540 else
6541 return 1;
6542 bitmap += (port & 0x7fff) / 8;
6543
6544 if (last_bitmap != bitmap)
6545 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6546 return 1;
6547 if (b & (1 << (port & 7)))
6548 return 1;
6549
6550 port++;
6551 size--;
6552 last_bitmap = bitmap;
6553 }
6554
6555 return 0;
6556}
6557
644d711a
NHE		 6558/*
6559 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6560 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6561 * disinterest in the current event (read or write a specific MSR) by using an
6562 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6563 */
6564static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6565 struct vmcs12 *vmcs12, u32 exit_reason)
6566{
6567 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6568 gpa_t bitmap;
6569
cbd29cb6 6570 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6571 return 1;
6572
6573 /*
6574 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6575 * for the four combinations of read/write and low/high MSR numbers.
6576 * First we need to figure out which of the four to use:
6577 */
6578 bitmap = vmcs12->msr_bitmap;
6579 if (exit_reason == EXIT_REASON_MSR_WRITE)
6580 bitmap += 2048;
6581 if (msr_index >= 0xc0000000) {
6582 msr_index -= 0xc0000000;
6583 bitmap += 1024;
6584 }
6585
6586 /* Then read the msr_index'th bit from this bitmap: */
6587 if (msr_index < 1024*8) {
6588 unsigned char b;
bd31a7f5
JK		 6589 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6590 return 1;
644d711a
NHE		 6591 return 1 & (b >> (msr_index & 7));
6592 } else
6593 return 1; /* let L1 handle the wrong parameter */
6594}
6595
6596/*
6597 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6598 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6599 * intercept (via guest_host_mask etc.) the current event.
6600 */
6601static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6602 struct vmcs12 *vmcs12)
6603{
6604 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6605 int cr = exit_qualification & 15;
6606 int reg = (exit_qualification >> 8) & 15;
6607 unsigned long val = kvm_register_read(vcpu, reg);
6608
6609 switch ((exit_qualification >> 4) & 3) {
6610 case 0: /* mov to cr */
6611 switch (cr) {
6612 case 0:
6613 if (vmcs12->cr0_guest_host_mask &
6614 (val ^ vmcs12->cr0_read_shadow))
6615 return 1;
6616 break;
6617 case 3:
6618 if ((vmcs12->cr3_target_count >= 1 &&
6619 vmcs12->cr3_target_value0 == val) ||
6620 (vmcs12->cr3_target_count >= 2 &&
6621 vmcs12->cr3_target_value1 == val) ||
6622 (vmcs12->cr3_target_count >= 3 &&
6623 vmcs12->cr3_target_value2 == val) ||
6624 (vmcs12->cr3_target_count >= 4 &&
6625 vmcs12->cr3_target_value3 == val))
6626 return 0;
6627 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6628 return 1;
6629 break;
6630 case 4:
6631 if (vmcs12->cr4_guest_host_mask &
6632 (vmcs12->cr4_read_shadow ^ val))
6633 return 1;
6634 break;
6635 case 8:
6636 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6637 return 1;
6638 break;
6639 }
6640 break;
6641 case 2: /* clts */
6642 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6643 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6644 return 1;
6645 break;
6646 case 1: /* mov from cr */
6647 switch (cr) {
6648 case 3:
6649 if (vmcs12->cpu_based_vm_exec_control &
6650 CPU_BASED_CR3_STORE_EXITING)
6651 return 1;
6652 break;
6653 case 8:
6654 if (vmcs12->cpu_based_vm_exec_control &
6655 CPU_BASED_CR8_STORE_EXITING)
6656 return 1;
6657 break;
6658 }
6659 break;
6660 case 3: /* lmsw */
6661 /*
6662 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6663 * cr0. Other attempted changes are ignored, with no exit.
6664 */
6665 if (vmcs12->cr0_guest_host_mask & 0xe &
6666 (val ^ vmcs12->cr0_read_shadow))
6667 return 1;
6668 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6669 !(vmcs12->cr0_read_shadow & 0x1) &&
6670 (val & 0x1))
6671 return 1;
6672 break;
6673 }
6674 return 0;
6675}
6676
6677/*
6678 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6679 * should handle it ourselves in L0 (and then continue L2). Only call this
6680 * when in is_guest_mode (L2).
6681 */
6682static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6683{
644d711a
NHE		 6684 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6685 struct vcpu_vmx *vmx = to_vmx(vcpu);
6686 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6687 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6688
6689 if (vmx->nested.nested_run_pending)
6690 return 0;
6691
6692 if (unlikely(vmx->fail)) {
bd80158a
JK		 6693 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6694 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6695 return 1;
6696 }
6697
6698 switch (exit_reason) {
6699 case EXIT_REASON_EXCEPTION_NMI:
6700 if (!is_exception(intr_info))
6701 return 0;
6702 else if (is_page_fault(intr_info))
6703 return enable_ept;
e504c909
AB		 6704 else if (is_no_device(intr_info) &&
6705 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6706 return 0;
644d711a
NHE		 6707 return vmcs12->exception_bitmap &
6708 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6709 case EXIT_REASON_EXTERNAL_INTERRUPT:
6710 return 0;
6711 case EXIT_REASON_TRIPLE_FAULT:
6712 return 1;
6713 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6714 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6715 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6716 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6717 case EXIT_REASON_TASK_SWITCH:
6718 return 1;
6719 case EXIT_REASON_CPUID:
6720 return 1;
6721 case EXIT_REASON_HLT:
6722 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6723 case EXIT_REASON_INVD:
6724 return 1;
6725 case EXIT_REASON_INVLPG:
6726 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6727 case EXIT_REASON_RDPMC:
6728 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6729 case EXIT_REASON_RDTSC:
6730 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6731 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6732 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6733 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6734 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6735 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6736 case EXIT_REASON_INVEPT:
644d711a
NHE		 6737 /*
6738 * VMX instructions trap unconditionally. This allows L1 to
6739 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6740 */
6741 return 1;
6742 case EXIT_REASON_CR_ACCESS:
6743 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6744 case EXIT_REASON_DR_ACCESS:
6745 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6746 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6747 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6748 case EXIT_REASON_MSR_READ:
6749 case EXIT_REASON_MSR_WRITE:
6750 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6751 case EXIT_REASON_INVALID_STATE:
6752 return 1;
6753 case EXIT_REASON_MWAIT_INSTRUCTION:
6754 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6755 case EXIT_REASON_MONITOR_INSTRUCTION:
6756 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6757 case EXIT_REASON_PAUSE_INSTRUCTION:
6758 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6759 nested_cpu_has2(vmcs12,
6760 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6761 case EXIT_REASON_MCE_DURING_VMENTRY:
6762 return 0;
6763 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6764 return 1;
6765 case EXIT_REASON_APIC_ACCESS:
6766 return nested_cpu_has2(vmcs12,
6767 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6768 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6769 /*
6770 * L0 always deals with the EPT violation. If nested EPT is
6771 * used, and the nested mmu code discovers that the address is
6772 * missing in the guest EPT table (EPT12), the EPT violation
6773 * will be injected with nested_ept_inject_page_fault()
6774 */
6775 return 0;
644d711a 6776 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6777 /*
6778 * L2 never uses directly L1's EPT, but rather L0's own EPT
6779 * table (shadow on EPT) or a merged EPT table that L0 built
6780 * (EPT on EPT). So any problems with the structure of the
6781 * table is L0's fault.
6782 */
644d711a 6783 return 0;
0238ea91
JK		 6784 case EXIT_REASON_PREEMPTION_TIMER:
6785 return vmcs12->pin_based_vm_exec_control &
6786 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6787 case EXIT_REASON_WBINVD:
6788 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6789 case EXIT_REASON_XSETBV:
6790 return 1;
6791 default:
6792 return 1;
6793 }
6794}
6795
586f9607
AK		 6796static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6797{
6798 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6799 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6800}
6801
7854cbca
ACL		 6802static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6803{
6804 u64 delta_tsc_l1;
6805 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6806
6807 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6808 PIN_BASED_VMX_PREEMPTION_TIMER))
6809 return;
6810 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6811 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6812 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6813 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6814 - vcpu->arch.last_guest_tsc;
6815 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6816 if (preempt_val_l2 <= preempt_val_l1)
6817 preempt_val_l2 = 0;
6818 else
6819 preempt_val_l2 -= preempt_val_l1;
6820 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6821}
6822
6aa8b732
AK		 6823/*
6824 * The guest has exited. See if we can fix it or if we need userspace
6825 * assistance.
6826 */
851ba692 6827static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6828{
29bd8a78 6829 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6830 u32 exit_reason = vmx->exit_reason;
1155f76a 6831 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6832
80ced186 6833 /* If guest state is invalid, start emulating */
14168786 6834 if (vmx->emulation_required)
80ced186 6835 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6836
644d711a
NHE		 6837 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6838 nested_vmx_vmexit(vcpu);
6839 return 1;
6840 }
6841
5120702e
MG		 6842 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6843 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6844 vcpu->run->fail_entry.hardware_entry_failure_reason
6845 = exit_reason;
6846 return 0;
6847 }
6848
29bd8a78 6849 if (unlikely(vmx->fail)) {
851ba692
AK		 6850 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6851 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6852 = vmcs_read32(VM_INSTRUCTION_ERROR);
6853 return 0;
6854 }
6aa8b732 6855
b9bf6882
XG		 6856 /*
6857 * Note:
6858 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6859 * delivery event since it indicates guest is accessing MMIO.
6860 * The vm-exit can be triggered again after return to guest that
6861 * will cause infinite loop.
6862 */
d77c26fc 6863 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6864 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6865 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6866 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6867 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6868 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6869 vcpu->run->internal.ndata = 2;
6870 vcpu->run->internal.data[0] = vectoring_info;
6871 vcpu->run->internal.data[1] = exit_reason;
6872 return 0;
6873 }
3b86cd99 6874
644d711a
NHE		 6875 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6876 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6877 get_vmcs12(vcpu))))) {
c4282df9 6878 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6879 vmx->soft_vnmi_blocked = 0;
3b86cd99 6880 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6881 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6882 /*
6883 * This CPU don't support us in finding the end of an
6884 * NMI-blocked window if the guest runs with IRQs
6885 * disabled. So we pull the trigger after 1 s of
6886 * futile waiting, but inform the user about this.
6887 */
6888 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6889 "state on VCPU %d after 1 s timeout\n",
6890 __func__, vcpu->vcpu_id);
6891 vmx->soft_vnmi_blocked = 0;
3b86cd99 6892 }
3b86cd99
JK		 6893 }
6894
6aa8b732
AK		 6895 if (exit_reason < kvm_vmx_max_exit_handlers
6896 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6897 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6898 else {
851ba692
AK		 6899 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6900 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6901 }
6902 return 0;
6903}
6904
95ba8273 6905static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6906{
95ba8273 6907 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6908 vmcs_write32(TPR_THRESHOLD, 0);
6909 return;
6910 }
6911
95ba8273 6912 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6913}
6914
8d14695f
YZ		 6915static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6916{
6917 u32 sec_exec_control;
6918
6919 /*
6920 * There is not point to enable virtualize x2apic without enable
6921 * apicv
6922 */
c7c9c56c
YZ		 6923 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6924 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6925 return;
6926
6927 if (!vm_need_tpr_shadow(vcpu->kvm))
6928 return;
6929
6930 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6931
6932 if (set) {
6933 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6934 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6935 } else {
6936 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6937 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6938 }
6939 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6940
6941 vmx_set_msr_bitmap(vcpu);
6942}
6943
c7c9c56c
YZ		 6944static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6945{
6946 u16 status;
6947 u8 old;
6948
6949 if (!vmx_vm_has_apicv(kvm))
6950 return;
6951
6952 if (isr == -1)
6953 isr = 0;
6954
6955 status = vmcs_read16(GUEST_INTR_STATUS);
6956 old = status >> 8;
6957 if (isr != old) {
6958 status &= 0xff;
6959 status |= isr << 8;
6960 vmcs_write16(GUEST_INTR_STATUS, status);
6961 }
6962}
6963
6964static void vmx_set_rvi(int vector)
6965{
6966 u16 status;
6967 u8 old;
6968
6969 status = vmcs_read16(GUEST_INTR_STATUS);
6970 old = (u8)status & 0xff;
6971 if ((u8)vector != old) {
6972 status &= ~0xff;
6973 status |= (u8)vector;
6974 vmcs_write16(GUEST_INTR_STATUS, status);
6975 }
6976}
6977
6978static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6979{
6980 if (max_irr == -1)
6981 return;
6982
6983 vmx_set_rvi(max_irr);
6984}
6985
6986static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6987{
3d81bc7e
YZ		 6988 if (!vmx_vm_has_apicv(vcpu->kvm))
6989 return;
6990
c7c9c56c
YZ		 6991 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6992 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6993 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6994 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6995}
6996
51aa01d1 6997static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6998{
00eba012
AK		 6999 u32 exit_intr_info;
7000
7001 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7002 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7003 return;
7004
c5ca8e57 7005 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7006 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7007
7008 /* Handle machine checks before interrupts are enabled */
00eba012 7009 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7010 kvm_machine_check();
7011
20f65983 7012 /* We need to handle NMIs before interrupts are enabled */
00eba012 7013 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7014 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7015 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7016 asm("int $2");
ff9d07a0
ZY		 7017 kvm_after_handle_nmi(&vmx->vcpu);
7018 }
51aa01d1 7019}
20f65983 7020
a547c6db
YZ		 7021static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7022{
7023 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7024
7025 /*
7026 * If external interrupt exists, IF bit is set in rflags/eflags on the
7027 * interrupt stack frame, and interrupt will be enabled on a return
7028 * from interrupt handler.
7029 */
7030 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7031 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7032 unsigned int vector;
7033 unsigned long entry;
7034 gate_desc *desc;
7035 struct vcpu_vmx *vmx = to_vmx(vcpu);
7036#ifdef CONFIG_X86_64
7037 unsigned long tmp;
7038#endif
7039
7040 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7041 desc = (gate_desc *)vmx->host_idt_base + vector;
7042 entry = gate_offset(*desc);
7043 asm volatile(
7044#ifdef CONFIG_X86_64
7045 "mov %%" _ASM_SP ", %[sp]\n\t"
7046 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7047 "push $%c[ss]\n\t"
7048 "push %[sp]\n\t"
7049#endif
7050 "pushf\n\t"
7051 "orl $0x200, (%%" _ASM_SP ")\n\t"
7052 __ASM_SIZE(push) " $%c[cs]\n\t"
7053 "call *%[entry]\n\t"
7054 :
7055#ifdef CONFIG_X86_64
7056 [sp]"=&r"(tmp)
7057#endif
7058 :
7059 [entry]"r"(entry),
7060 [ss]"i"(__KERNEL_DS),
7061 [cs]"i"(__KERNEL_CS)
7062 );
7063 } else
7064 local_irq_enable();
7065}
7066
51aa01d1
AK		 7067static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7068{
c5ca8e57 7069 u32 exit_intr_info;
51aa01d1
AK		 7070 bool unblock_nmi;
7071 u8 vector;
7072 bool idtv_info_valid;
7073
7074 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7075
cf393f75 7076 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7077 if (vmx->nmi_known_unmasked)
7078 return;
c5ca8e57
AK		 7079 /*
7080 * Can't use vmx->exit_intr_info since we're not sure what
7081 * the exit reason is.
7082 */
7083 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7084 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7085 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7086 /*
7b4a25cb 7087 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7088 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7089 * a guest IRET fault.
7b4a25cb
GN		 7090 * SDM 3: 23.2.2 (September 2008)
7091 * Bit 12 is undefined in any of the following cases:
7092 * If the VM exit sets the valid bit in the IDT-vectoring
7093 * information field.
7094 * If the VM exit is due to a double fault.
cf393f75 7095 */
7b4a25cb
GN		 7096 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7097 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7098 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7099 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7100 else
7101 vmx->nmi_known_unmasked =
7102 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7103 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7104 } else if (unlikely(vmx->soft_vnmi_blocked))
7105 vmx->vnmi_blocked_time +=
7106 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7107}
7108
3ab66e8a 7109static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7110 u32 idt_vectoring_info,
7111 int instr_len_field,
7112 int error_code_field)
51aa01d1 7113{
51aa01d1
AK		 7114 u8 vector;
7115 int type;
7116 bool idtv_info_valid;
7117
7118 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7119
3ab66e8a
JK		 7120 vcpu->arch.nmi_injected = false;
7121 kvm_clear_exception_queue(vcpu);
7122 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7123
7124 if (!idtv_info_valid)
7125 return;
7126
3ab66e8a 7127 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7128
668f612f
AK		 7129 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7130 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7131
64a7ec06 7132 switch (type) {
37b96e98 7133 case INTR_TYPE_NMI_INTR:
3ab66e8a 7134 vcpu->arch.nmi_injected = true;
668f612f 7135 /*
7b4a25cb 7136 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7137 * Clear bit "block by NMI" before VM entry if a NMI
7138 * delivery faulted.
668f612f 7139 */
3ab66e8a 7140 vmx_set_nmi_mask(vcpu, false);
37b96e98 7141 break;
37b96e98 7142 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7143 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7144 /* fall through */
7145 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7146 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7147 u32 err = vmcs_read32(error_code_field);
851eb667 7148 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7149 } else
851eb667 7150 kvm_requeue_exception(vcpu, vector);
37b96e98 7151 break;
66fd3f7f 7152 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7153 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7154 /* fall through */
37b96e98 7155 case INTR_TYPE_EXT_INTR:
3ab66e8a 7156 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7157 break;
7158 default:
7159 break;
f7d9238f 7160 }
cf393f75
AK		 7161}
7162
83422e17
AK		 7163static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7164{
3ab66e8a 7165 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7166 VM_EXIT_INSTRUCTION_LEN,
7167 IDT_VECTORING_ERROR_CODE);
7168}
7169
b463a6f7
AK		 7170static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7171{
3ab66e8a 7172 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7173 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7174 VM_ENTRY_INSTRUCTION_LEN,
7175 VM_ENTRY_EXCEPTION_ERROR_CODE);
7176
7177 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7178}
7179
d7cd9796
GN		 7180static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7181{
7182 int i, nr_msrs;
7183 struct perf_guest_switch_msr *msrs;
7184
7185 msrs = perf_guest_get_msrs(&nr_msrs);
7186
7187 if (!msrs)
7188 return;
7189
7190 for (i = 0; i < nr_msrs; i++)
7191 if (msrs[i].host == msrs[i].guest)
7192 clear_atomic_switch_msr(vmx, msrs[i].msr);
7193 else
7194 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7195 msrs[i].host);
7196}
7197
a3b5ba49 7198static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7199{
a2fa3e9f 7200 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7201 unsigned long debugctlmsr;
104f226b
AK		 7202
7203 /* Record the guest's net vcpu time for enforced NMI injections. */
7204 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7205 vmx->entry_time = ktime_get();
7206
7207 /* Don't enter VMX if guest state is invalid, let the exit handler
7208 start emulation until we arrive back to a valid state */
14168786 7209 if (vmx->emulation_required)
104f226b
AK		 7210 return;
7211
012f83cb
AG		 7212 if (vmx->nested.sync_shadow_vmcs) {
7213 copy_vmcs12_to_shadow(vmx);
7214 vmx->nested.sync_shadow_vmcs = false;
7215 }
7216
104f226b
AK		 7217 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7218 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7219 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7220 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7221
7222 /* When single-stepping over STI and MOV SS, we must clear the
7223 * corresponding interruptibility bits in the guest state. Otherwise
7224 * vmentry fails as it then expects bit 14 (BS) in pending debug
7225 * exceptions being set, but that's not correct for the guest debugging
7226 * case. */
7227 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7228 vmx_set_interrupt_shadow(vcpu, 0);
7229
d7cd9796 7230 atomic_switch_perf_msrs(vmx);
2a7921b7 7231 debugctlmsr = get_debugctlmsr();
d7cd9796 7232
7854cbca
ACL		 7233 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7234 nested_adjust_preemption_timer(vcpu);
d462b819 7235 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7236 asm(
6aa8b732 7237 /* Store host registers */
b188c81f
AK		 7238 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7239 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7240 "push %%" _ASM_CX " \n\t"
7241 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7242 "je 1f \n\t"
b188c81f 7243 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7244 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7245 "1: \n\t"
d3edefc0 7246 /* Reload cr2 if changed */
b188c81f
AK		 7247 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7248 "mov %%cr2, %%" _ASM_DX " \n\t"
7249 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7250 "je 2f \n\t"
b188c81f 7251 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7252 "2: \n\t"
6aa8b732 7253 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7254 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7255 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7256 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7257 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7258 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7259 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7260 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7261 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7262#ifdef CONFIG_X86_64
e08aa78a
AK		 7263 "mov %c[r8](%0), %%r8 \n\t"
7264 "mov %c[r9](%0), %%r9 \n\t"
7265 "mov %c[r10](%0), %%r10 \n\t"
7266 "mov %c[r11](%0), %%r11 \n\t"
7267 "mov %c[r12](%0), %%r12 \n\t"
7268 "mov %c[r13](%0), %%r13 \n\t"
7269 "mov %c[r14](%0), %%r14 \n\t"
7270 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7271#endif
b188c81f 7272 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7273
6aa8b732 7274 /* Enter guest mode */
83287ea4 7275 "jne 1f \n\t"
4ecac3fd 7276 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7277 "jmp 2f \n\t"
7278 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7279 "2: "
6aa8b732 7280 /* Save guest registers, load host registers, keep flags */
b188c81f 7281 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7282 "pop %0 \n\t"
b188c81f
AK		 7283 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7284 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7285 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7286 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7287 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7288 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7289 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7290#ifdef CONFIG_X86_64
e08aa78a
AK		 7291 "mov %%r8, %c[r8](%0) \n\t"
7292 "mov %%r9, %c[r9](%0) \n\t"
7293 "mov %%r10, %c[r10](%0) \n\t"
7294 "mov %%r11, %c[r11](%0) \n\t"
7295 "mov %%r12, %c[r12](%0) \n\t"
7296 "mov %%r13, %c[r13](%0) \n\t"
7297 "mov %%r14, %c[r14](%0) \n\t"
7298 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7299#endif
b188c81f
AK		 7300 "mov %%cr2, %%" _ASM_AX " \n\t"
7301 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7302
b188c81f 7303 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7304 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7305 ".pushsection .rodata \n\t"
7306 ".global vmx_return \n\t"
7307 "vmx_return: " _ASM_PTR " 2b \n\t"
7308 ".popsection"
e08aa78a 7309 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7310 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7311 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7312 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7313 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7314 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7315 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7316 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7317 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7318 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7319 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7320#ifdef CONFIG_X86_64
ad312c7c
ZX		 7321 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7322 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7323 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7324 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7325 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7326 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7327 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7328 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7329#endif
40712fae
AK		 7330 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7331 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7332 : "cc", "memory"
7333#ifdef CONFIG_X86_64
b188c81f 7334 , "rax", "rbx", "rdi", "rsi"
c2036300 7335 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7336#else
7337 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7338#endif
7339 );
6aa8b732 7340
2a7921b7
GN		 7341 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7342 if (debugctlmsr)
7343 update_debugctlmsr(debugctlmsr);
7344
aa67f609
AK		 7345#ifndef CONFIG_X86_64
7346 /*
7347 * The sysexit path does not restore ds/es, so we must set them to
7348 * a reasonable value ourselves.
7349 *
7350 * We can't defer this to vmx_load_host_state() since that function
7351 * may be executed in interrupt context, which saves and restore segments
7352 * around it, nullifying its effect.
7353 */
7354 loadsegment(ds, __USER_DS);
7355 loadsegment(es, __USER_DS);
7356#endif
7357
6de4f3ad 7358 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7359 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7360 | (1 << VCPU_EXREG_CPL)
aff48baa 7361 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7362 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7363 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7364 vcpu->arch.regs_dirty = 0;
7365
1155f76a
AK		 7366 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7367
d462b819 7368 vmx->loaded_vmcs->launched = 1;
1b6269db 7369
51aa01d1 7370 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7371 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7372
e0b890d3
GN		 7373 /*
7374 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7375 * we did not inject a still-pending event to L1 now because of
7376 * nested_run_pending, we need to re-enable this bit.
7377 */
7378 if (vmx->nested.nested_run_pending)
7379 kvm_make_request(KVM_REQ_EVENT, vcpu);
7380
7381 vmx->nested.nested_run_pending = 0;
7382
51aa01d1
AK		 7383 vmx_complete_atomic_exit(vmx);
7384 vmx_recover_nmi_blocking(vmx);
cf393f75 7385 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7386}
7387
6aa8b732
AK		 7388static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7389{
fb3f0f51
RR		 7390 struct vcpu_vmx *vmx = to_vmx(vcpu);
7391
cdbecfc3 7392 free_vpid(vmx);
d462b819 7393 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7394 free_nested(vmx);
fb3f0f51
RR		 7395 kfree(vmx->guest_msrs);
7396 kvm_vcpu_uninit(vcpu);
a4770347 7397 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7398}
7399
fb3f0f51 7400static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7401{
fb3f0f51 7402 int err;
c16f862d 7403 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7404 int cpu;
6aa8b732 7405
a2fa3e9f 7406 if (!vmx)
fb3f0f51
RR		 7407 return ERR_PTR(-ENOMEM);
7408
2384d2b3
SY		 7409 allocate_vpid(vmx);
7410
fb3f0f51
RR		 7411 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7412 if (err)
7413 goto free_vcpu;
965b58a5 7414
a2fa3e9f 7415 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7416 err = -ENOMEM;
fb3f0f51 7417 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7418 goto uninit_vcpu;
7419 }
965b58a5 7420
d462b819
NHE		 7421 vmx->loaded_vmcs = &vmx->vmcs01;
7422 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7423 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7424 goto free_msrs;
d462b819
NHE		 7425 if (!vmm_exclusive)
7426 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7427 loaded_vmcs_init(vmx->loaded_vmcs);
7428 if (!vmm_exclusive)
7429 kvm_cpu_vmxoff();
a2fa3e9f 7430
15ad7146
AK		 7431 cpu = get_cpu();
7432 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7433 vmx->vcpu.cpu = cpu;
8b9cf98c 7434 err = vmx_vcpu_setup(vmx);
fb3f0f51 7435 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7436 put_cpu();
fb3f0f51
RR		 7437 if (err)
7438 goto free_vmcs;
a63cb560 7439 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7440 err = alloc_apic_access_page(kvm);
7441 if (err)
5e4a0b3c 7442 goto free_vmcs;
a63cb560 7443 }
fb3f0f51 7444
b927a3ce
SY		 7445 if (enable_ept) {
7446 if (!kvm->arch.ept_identity_map_addr)
7447 kvm->arch.ept_identity_map_addr =
7448 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7449 err = -ENOMEM;
b7ebfb05
SY		 7450 if (alloc_identity_pagetable(kvm) != 0)
7451 goto free_vmcs;
93ea5388
GN		 7452 if (!init_rmode_identity_map(kvm))
7453 goto free_vmcs;
b927a3ce 7454 }
b7ebfb05 7455
a9d30f33
NHE		 7456 vmx->nested.current_vmptr = -1ull;
7457 vmx->nested.current_vmcs12 = NULL;
7458
fb3f0f51
RR		 7459 return &vmx->vcpu;
7460
7461free_vmcs:
5f3fbc34 7462 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7463free_msrs:
fb3f0f51
RR		 7464 kfree(vmx->guest_msrs);
7465uninit_vcpu:
7466 kvm_vcpu_uninit(&vmx->vcpu);
7467free_vcpu:
cdbecfc3 7468 free_vpid(vmx);
a4770347 7469 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7470 return ERR_PTR(err);
6aa8b732
AK		 7471}
7472
002c7f7c
YS		 7473static void __init vmx_check_processor_compat(void *rtn)
7474{
7475 struct vmcs_config vmcs_conf;
7476
7477 *(int *)rtn = 0;
7478 if (setup_vmcs_config(&vmcs_conf) < 0)
7479 *(int *)rtn = -EIO;
7480 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7481 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7482 smp_processor_id());
7483 *(int *)rtn = -EIO;
7484 }
7485}
7486
67253af5
SY		 7487static int get_ept_level(void)
7488{
7489 return VMX_EPT_DEFAULT_GAW + 1;
7490}
7491
4b12f0de 7492static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7493{
4b12f0de
SY		 7494 u64 ret;
7495
522c68c4
SY		 7496 /* For VT-d and EPT combination
7497 * 1. MMIO: always map as UC
7498 * 2. EPT with VT-d:
7499 * a. VT-d without snooping control feature: can't guarantee the
7500 * result, try to trust guest.
7501 * b. VT-d with snooping control feature: snooping control feature of
7502 * VT-d engine can guarantee the cache correctness. Just set it
7503 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7504 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7505 * consistent with host MTRR
7506 */
4b12f0de
SY		 7507 if (is_mmio)
7508 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7509 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7510 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7511 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7512 else
522c68c4 7513 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7514 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7515
7516 return ret;
64d4d521
SY		 7517}
7518
17cc3935 7519static int vmx_get_lpage_level(void)
344f414f 7520{
878403b7
SY		 7521 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7522 return PT_DIRECTORY_LEVEL;
7523 else
7524 /* For shadow and EPT supported 1GB page */
7525 return PT_PDPE_LEVEL;
344f414f
JR		 7526}
7527
0e851880
SY		 7528static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7529{
4e47c7a6
SY		 7530 struct kvm_cpuid_entry2 *best;
7531 struct vcpu_vmx *vmx = to_vmx(vcpu);
7532 u32 exec_control;
7533
7534 vmx->rdtscp_enabled = false;
7535 if (vmx_rdtscp_supported()) {
7536 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7537 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7538 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7539 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7540 vmx->rdtscp_enabled = true;
7541 else {
7542 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7543 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7544 exec_control);
7545 }
7546 }
7547 }
ad756a16 7548
ad756a16
MJ		 7549 /* Exposing INVPCID only when PCID is exposed */
7550 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7551 if (vmx_invpcid_supported() &&
4f977045 7552 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7553 guest_cpuid_has_pcid(vcpu)) {
29282fde 7554 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7555 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7556 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7557 exec_control);
7558 } else {
29282fde
TI		 7559 if (cpu_has_secondary_exec_ctrls()) {
7560 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7561 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7562 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7563 exec_control);
7564 }
ad756a16 7565 if (best)
4f977045 7566 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7567 }
0e851880
SY		 7568}
7569
d4330ef2
JR		 7570static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7571{
7b8050f5
NHE		 7572 if (func == 1 && nested)
7573 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7574}
7575
25d92081
YZ		 7576static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7577 struct x86_exception *fault)
7578{
7579 struct vmcs12 *vmcs12;
7580 nested_vmx_vmexit(vcpu);
7581 vmcs12 = get_vmcs12(vcpu);
7582
7583 if (fault->error_code & PFERR_RSVD_MASK)
7584 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7585 else
7586 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7587 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7588 vmcs12->guest_physical_address = fault->address;
7589}
7590
155a97a3
NHE		 7591/* Callbacks for nested_ept_init_mmu_context: */
7592
7593static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7594{
7595 /* return the page table to be shadowed - in our case, EPT12 */
7596 return get_vmcs12(vcpu)->ept_pointer;
7597}
7598
8a3c1a33 7599static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7600{
8a3c1a33 7601 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7602 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7603
7604 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7605 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7606 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7607
7608 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7609}
7610
7611static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7612{
7613 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7614}
7615
feaf0c7d
GN		 7616static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7617 struct x86_exception *fault)
7618{
7619 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7620
7621 WARN_ON(!is_guest_mode(vcpu));
7622
7623 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7624 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7625 nested_vmx_vmexit(vcpu);
7626 else
7627 kvm_inject_page_fault(vcpu, fault);
7628}
7629
fe3ef05c
NHE		 7630/*
7631 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7632 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7633 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7634 * guest in a way that will both be appropriate to L1's requests, and our
7635 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7636 * function also has additional necessary side-effects, like setting various
7637 * vcpu->arch fields.
7638 */
7639static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7640{
7641 struct vcpu_vmx *vmx = to_vmx(vcpu);
7642 u32 exec_control;
7854cbca 7643 u32 exit_control;
fe3ef05c
NHE		 7644
7645 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7646 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7647 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7648 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7649 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7650 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7651 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7652 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7653 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7654 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7655 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7656 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7657 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7658 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7659 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7660 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7661 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7662 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7663 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7664 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7665 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7666 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7667 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7668 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7669 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7670 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7671 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7672 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7673 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7674 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7675 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7676 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7677 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7678 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7679 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7680 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7681
7682 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7684 vmcs12->vm_entry_intr_info_field);
7685 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7686 vmcs12->vm_entry_exception_error_code);
7687 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7688 vmcs12->vm_entry_instruction_len);
7689 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7690 vmcs12->guest_interruptibility_info);
fe3ef05c 7691 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7692 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7693 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7694 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7695 vmcs12->guest_pending_dbg_exceptions);
7696 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7697 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7698
7699 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7700
7701 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7702 (vmcs_config.pin_based_exec_ctrl |
7703 vmcs12->pin_based_vm_exec_control));
7704
0238ea91
JK		 7705 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7706 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7707 vmcs12->vmx_preemption_timer_value);
7708
fe3ef05c
NHE		 7709 /*
7710 * Whether page-faults are trapped is determined by a combination of
7711 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7712 * If enable_ept, L0 doesn't care about page faults and we should
7713 * set all of these to L1's desires. However, if !enable_ept, L0 does
7714 * care about (at least some) page faults, and because it is not easy
7715 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7716 * to exit on each and every L2 page fault. This is done by setting
7717 * MASK=MATCH=0 and (see below) EB.PF=1.
7718 * Note that below we don't need special code to set EB.PF beyond the
7719 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7720 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7721 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7722 *
7723 * A problem with this approach (when !enable_ept) is that L1 may be
7724 * injected with more page faults than it asked for. This could have
7725 * caused problems, but in practice existing hypervisors don't care.
7726 * To fix this, we will need to emulate the PFEC checking (on the L1
7727 * page tables), using walk_addr(), when injecting PFs to L1.
7728 */
7729 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7730 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7731 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7732 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7733
7734 if (cpu_has_secondary_exec_ctrls()) {
7735 u32 exec_control = vmx_secondary_exec_control(vmx);
7736 if (!vmx->rdtscp_enabled)
7737 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7738 /* Take the following fields only from vmcs12 */
7739 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7740 if (nested_cpu_has(vmcs12,
7741 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7742 exec_control |= vmcs12->secondary_vm_exec_control;
7743
7744 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7745 /*
7746 * Translate L1 physical address to host physical
7747 * address for vmcs02. Keep the page pinned, so this
7748 * physical address remains valid. We keep a reference
7749 * to it so we can release it later.
7750 */
7751 if (vmx->nested.apic_access_page) /* shouldn't happen */
7752 nested_release_page(vmx->nested.apic_access_page);
7753 vmx->nested.apic_access_page =
7754 nested_get_page(vcpu, vmcs12->apic_access_addr);
7755 /*
7756 * If translation failed, no matter: This feature asks
7757 * to exit when accessing the given address, and if it
7758 * can never be accessed, this feature won't do
7759 * anything anyway.
7760 */
7761 if (!vmx->nested.apic_access_page)
7762 exec_control &=
7763 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7764 else
7765 vmcs_write64(APIC_ACCESS_ADDR,
7766 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7767 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7768 exec_control |=
7769 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7770 vmcs_write64(APIC_ACCESS_ADDR,
7771 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7772 }
7773
7774 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7775 }
7776
7777
7778 /*
7779 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7780 * Some constant fields are set here by vmx_set_constant_host_state().
7781 * Other fields are different per CPU, and will be set later when
7782 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7783 */
a547c6db 7784 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7785
7786 /*
7787 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7788 * entry, but only if the current (host) sp changed from the value
7789 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7790 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7791 * here we just force the write to happen on entry.
7792 */
7793 vmx->host_rsp = 0;
7794
7795 exec_control = vmx_exec_control(vmx); /* L0's desires */
7796 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7797 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7798 exec_control &= ~CPU_BASED_TPR_SHADOW;
7799 exec_control |= vmcs12->cpu_based_vm_exec_control;
7800 /*
7801 * Merging of IO and MSR bitmaps not currently supported.
7802 * Rather, exit every time.
7803 */
7804 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7805 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7806 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7807
7808 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7809
7810 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7811 * bitwise-or of what L1 wants to trap for L2, and what we want to
7812 * trap. Note that CR0.TS also needs updating - we do this later.
7813 */
7814 update_exception_bitmap(vcpu);
7815 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7816 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7817
8049d651
NHE		 7818 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7819 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7820 * bits are further modified by vmx_set_efer() below.
7821 */
7854cbca
ACL		 7822 exit_control = vmcs_config.vmexit_ctrl;
7823 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7824 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7825 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7826
7827 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7828 * emulated by vmx_set_efer(), below.
7829 */
2961e876 7830 vm_entry_controls_init(vmx,
8049d651
NHE		 7831 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7832 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7833 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7834
44811c02 7835 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7836 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7837 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7838 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7839 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7840
7841
7842 set_cr4_guest_host_mask(vmx);
7843
27fc51b2
NHE		 7844 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7845 vmcs_write64(TSC_OFFSET,
7846 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7847 else
7848 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7849
7850 if (enable_vpid) {
7851 /*
7852 * Trivially support vpid by letting L2s share their parent
7853 * L1's vpid. TODO: move to a more elaborate solution, giving
7854 * each L2 its own vpid and exposing the vpid feature to L1.
7855 */
7856 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7857 vmx_flush_tlb(vcpu);
7858 }
7859
155a97a3
NHE		 7860 if (nested_cpu_has_ept(vmcs12)) {
7861 kvm_mmu_unload(vcpu);
7862 nested_ept_init_mmu_context(vcpu);
7863 }
7864
fe3ef05c
NHE		 7865 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7866 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7867 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7868 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7869 else
7870 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7871 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7872 vmx_set_efer(vcpu, vcpu->arch.efer);
7873
7874 /*
7875 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7876 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7877 * The CR0_READ_SHADOW is what L2 should have expected to read given
7878 * the specifications by L1; It's not enough to take
7879 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7880 * have more bits than L1 expected.
7881 */
7882 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7883 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7884
7885 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7886 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7887
7888 /* shadow page tables on either EPT or shadow page tables */
7889 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7890 kvm_mmu_reset_context(vcpu);
7891
feaf0c7d
GN		 7892 if (!enable_ept)
7893 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7894
3633cfc3
NHE		 7895 /*
7896 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7897 */
7898 if (enable_ept) {
7899 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7900 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7901 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7902 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7903 }
7904
fe3ef05c
NHE		 7905 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7906 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7907}
7908
cd232ad0
NHE		 7909/*
7910 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7911 * for running an L2 nested guest.
7912 */
7913static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7914{
7915 struct vmcs12 *vmcs12;
7916 struct vcpu_vmx *vmx = to_vmx(vcpu);
7917 int cpu;
7918 struct loaded_vmcs *vmcs02;
384bb783 7919 bool ia32e;
cd232ad0
NHE		 7920
7921 if (!nested_vmx_check_permission(vcpu) ||
7922 !nested_vmx_check_vmcs12(vcpu))
7923 return 1;
7924
7925 skip_emulated_instruction(vcpu);
7926 vmcs12 = get_vmcs12(vcpu);
7927
012f83cb
AG		 7928 if (enable_shadow_vmcs)
7929 copy_shadow_to_vmcs12(vmx);
7930
7c177938
NHE		 7931 /*
7932 * The nested entry process starts with enforcing various prerequisites
7933 * on vmcs12 as required by the Intel SDM, and act appropriately when
7934 * they fail: As the SDM explains, some conditions should cause the
7935 * instruction to fail, while others will cause the instruction to seem
7936 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7937 * To speed up the normal (success) code path, we should avoid checking
7938 * for misconfigurations which will anyway be caught by the processor
7939 * when using the merged vmcs02.
7940 */
7941 if (vmcs12->launch_state == launch) {
7942 nested_vmx_failValid(vcpu,
7943 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7944 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7945 return 1;
7946 }
7947
6dfacadd
JK		 7948 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7949 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7950 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7951 return 1;
7952 }
7953
7c177938
NHE		 7954 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7955 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7956 /*TODO: Also verify bits beyond physical address width are 0*/
7957 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7958 return 1;
7959 }
7960
7961 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7962 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7963 /*TODO: Also verify bits beyond physical address width are 0*/
7964 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7965 return 1;
7966 }
7967
7968 if (vmcs12->vm_entry_msr_load_count > 0 ||
7969 vmcs12->vm_exit_msr_load_count > 0 ||
7970 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7971 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7972 __func__);
7c177938
NHE		 7973 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7974 return 1;
7975 }
7976
7977 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7978 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7979 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7980 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7981 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7982 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7983 !vmx_control_verify(vmcs12->vm_exit_controls,
7984 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7985 !vmx_control_verify(vmcs12->vm_entry_controls,
7986 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7987 {
7988 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7989 return 1;
7990 }
7991
7992 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7993 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7994 nested_vmx_failValid(vcpu,
7995 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7996 return 1;
7997 }
7998
92fbc7b1 7999 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8000 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8001 nested_vmx_entry_failure(vcpu, vmcs12,
8002 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8003 return 1;
8004 }
8005 if (vmcs12->vmcs_link_pointer != -1ull) {
8006 nested_vmx_entry_failure(vcpu, vmcs12,
8007 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8008 return 1;
8009 }
8010
384bb783 8011 /*
cb0c8cda 8012 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8013 * are performed on the field for the IA32_EFER MSR:
8014 * - Bits reserved in the IA32_EFER MSR must be 0.
8015 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8016 * the IA-32e mode guest VM-exit control. It must also be identical
8017 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8018 * CR0.PG) is 1.
8019 */
8020 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8021 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8022 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8023 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8024 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8025 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8026 nested_vmx_entry_failure(vcpu, vmcs12,
8027 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8028 return 1;
8029 }
8030 }
8031
8032 /*
8033 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8034 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8035 * the values of the LMA and LME bits in the field must each be that of
8036 * the host address-space size VM-exit control.
8037 */
8038 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8039 ia32e = (vmcs12->vm_exit_controls &
8040 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8041 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8042 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8043 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8044 nested_vmx_entry_failure(vcpu, vmcs12,
8045 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8046 return 1;
8047 }
8048 }
8049
7c177938
NHE		 8050 /*
8051 * We're finally done with prerequisite checking, and can start with
8052 * the nested entry.
8053 */
8054
cd232ad0
NHE		 8055 vmcs02 = nested_get_current_vmcs02(vmx);
8056 if (!vmcs02)
8057 return -ENOMEM;
8058
8059 enter_guest_mode(vcpu);
8060
e0b890d3
GN		 8061 vmx->nested.nested_run_pending = 1;
8062
cd232ad0
NHE		 8063 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8064
8065 cpu = get_cpu();
8066 vmx->loaded_vmcs = vmcs02;
8067 vmx_vcpu_put(vcpu);
8068 vmx_vcpu_load(vcpu, cpu);
8069 vcpu->cpu = cpu;
8070 put_cpu();
8071
36c3cc42
JK		 8072 vmx_segment_cache_clear(vmx);
8073
cd232ad0
NHE		 8074 vmcs12->launch_state = 1;
8075
8076 prepare_vmcs02(vcpu, vmcs12);
8077
6dfacadd
JK		 8078 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8079 return kvm_emulate_halt(vcpu);
8080
cd232ad0
NHE		 8081 /*
8082 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8083 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8084 * returned as far as L1 is concerned. It will only return (and set
8085 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8086 */
8087 return 1;
8088}
8089
4704d0be
NHE		 8090/*
8091 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8092 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8093 * This function returns the new value we should put in vmcs12.guest_cr0.
8094 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8095 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8096 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8097 * didn't trap the bit, because if L1 did, so would L0).
8098 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8099 * been modified by L2, and L1 knows it. So just leave the old value of
8100 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8101 * isn't relevant, because if L0 traps this bit it can set it to anything.
8102 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8103 * changed these bits, and therefore they need to be updated, but L0
8104 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8105 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8106 */
8107static inline unsigned long
8108vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8109{
8110 return
8111 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8112 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8113 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8114 vcpu->arch.cr0_guest_owned_bits));
8115}
8116
8117static inline unsigned long
8118vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8119{
8120 return
8121 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8122 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8123 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8124 vcpu->arch.cr4_guest_owned_bits));
8125}
8126
5f3d5799
JK		 8127static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8128 struct vmcs12 *vmcs12)
8129{
8130 u32 idt_vectoring;
8131 unsigned int nr;
8132
851eb667 8133 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8134 nr = vcpu->arch.exception.nr;
8135 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8136
8137 if (kvm_exception_is_soft(nr)) {
8138 vmcs12->vm_exit_instruction_len =
8139 vcpu->arch.event_exit_inst_len;
8140 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8141 } else
8142 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8143
8144 if (vcpu->arch.exception.has_error_code) {
8145 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8146 vmcs12->idt_vectoring_error_code =
8147 vcpu->arch.exception.error_code;
8148 }
8149
8150 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8151 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8152 vmcs12->idt_vectoring_info_field =
8153 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8154 } else if (vcpu->arch.interrupt.pending) {
8155 nr = vcpu->arch.interrupt.nr;
8156 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8157
8158 if (vcpu->arch.interrupt.soft) {
8159 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8160 vmcs12->vm_entry_instruction_len =
8161 vcpu->arch.event_exit_inst_len;
8162 } else
8163 idt_vectoring |= INTR_TYPE_EXT_INTR;
8164
8165 vmcs12->idt_vectoring_info_field = idt_vectoring;
8166 }
8167}
8168
4704d0be
NHE		 8169/*
8170 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8171 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8172 * and this function updates it to reflect the changes to the guest state while
8173 * L2 was running (and perhaps made some exits which were handled directly by L0
8174 * without going back to L1), and to reflect the exit reason.
8175 * Note that we do not have to copy here all VMCS fields, just those that
8176 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8177 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8178 * which already writes to vmcs12 directly.
8179 */
733568f9 8180static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8181{
8182 /* update guest state fields: */
8183 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8184 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8185
8186 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8187 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8188 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8189 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8190
8191 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8192 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8193 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8194 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8195 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8196 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8197 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8198 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8199 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8200 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8201 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8202 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8203 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8204 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8205 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8206 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8207 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8208 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8209 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8210 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8211 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8212 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8213 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8214 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8215 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8216 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8217 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8218 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8219 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8220 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8221 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8222 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8223 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8224 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8225 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8226 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8227
4704d0be
NHE		 8228 vmcs12->guest_interruptibility_info =
8229 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8230 vmcs12->guest_pending_dbg_exceptions =
8231 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8232
7854cbca
ACL		 8233 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8234 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8235 vmcs12->vmx_preemption_timer_value =
8236 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8237
3633cfc3
NHE		 8238 /*
8239 * In some cases (usually, nested EPT), L2 is allowed to change its
8240 * own CR3 without exiting. If it has changed it, we must keep it.
8241 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8242 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8243 *
8244 * Additionally, restore L2's PDPTR to vmcs12.
8245 */
8246 if (enable_ept) {
8247 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8248 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8249 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8250 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8251 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8252 }
8253
c18911a2
JK		 8254 vmcs12->vm_entry_controls =
8255 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8256 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8257
4704d0be
NHE		 8258 /* TODO: These cannot have changed unless we have MSR bitmaps and
8259 * the relevant bit asks not to trap the change */
8260 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8261 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8262 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8263 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8264 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8265 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8266 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8267 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8268
8269 /* update exit information fields: */
8270
957c897e 8271 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8272 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8273
8274 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8275 if ((vmcs12->vm_exit_intr_info &
8276 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8277 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8278 vmcs12->vm_exit_intr_error_code =
8279 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8280 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8281 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8282 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8283
5f3d5799
JK		 8284 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8285 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8286 * instead of reading the real value. */
4704d0be 8287 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8288
8289 /*
8290 * Transfer the event that L0 or L1 may wanted to inject into
8291 * L2 to IDT_VECTORING_INFO_FIELD.
8292 */
8293 vmcs12_save_pending_event(vcpu, vmcs12);
8294 }
8295
8296 /*
8297 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8298 * preserved above and would only end up incorrectly in L1.
8299 */
8300 vcpu->arch.nmi_injected = false;
8301 kvm_clear_exception_queue(vcpu);
8302 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8303}
8304
8305/*
8306 * A part of what we need to when the nested L2 guest exits and we want to
8307 * run its L1 parent, is to reset L1's guest state to the host state specified
8308 * in vmcs12.
8309 * This function is to be called not only on normal nested exit, but also on
8310 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8311 * Failures During or After Loading Guest State").
8312 * This function should be called when the active VMCS is L1's (vmcs01).
8313 */
733568f9
JK		 8314static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8315 struct vmcs12 *vmcs12)
4704d0be 8316{
21feb4eb
ACL		 8317 struct kvm_segment seg;
8318
4704d0be
NHE		 8319 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8320 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8321 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8322 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8323 else
8324 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8325 vmx_set_efer(vcpu, vcpu->arch.efer);
8326
8327 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8328 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8329 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8330 /*
8331 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8332 * actually changed, because it depends on the current state of
8333 * fpu_active (which may have changed).
8334 * Note that vmx_set_cr0 refers to efer set above.
8335 */
9e3e4dbf 8336 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8337 /*
8338 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8339 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8340 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8341 */
8342 update_exception_bitmap(vcpu);
8343 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8344 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8345
8346 /*
8347 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8348 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8349 */
8350 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8351 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8352
155a97a3
NHE		 8353 if (nested_cpu_has_ept(vmcs12))
8354 nested_ept_uninit_mmu_context(vcpu);
8355
4704d0be
NHE		 8356 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8357 kvm_mmu_reset_context(vcpu);
8358
feaf0c7d
GN		 8359 if (!enable_ept)
8360 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8361
4704d0be
NHE		 8362 if (enable_vpid) {
8363 /*
8364 * Trivially support vpid by letting L2s share their parent
8365 * L1's vpid. TODO: move to a more elaborate solution, giving
8366 * each L2 its own vpid and exposing the vpid feature to L1.
8367 */
8368 vmx_flush_tlb(vcpu);
8369 }
8370
8371
8372 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8373 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8374 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8375 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8376 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8377
44811c02 8378 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8379 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8380 vcpu->arch.pat = vmcs12->host_ia32_pat;
8381 }
4704d0be
NHE		 8382 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8383 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8384 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8385
21feb4eb
ACL		 8386 /* Set L1 segment info according to Intel SDM
8387 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8388 seg = (struct kvm_segment) {
8389 .base = 0,
8390 .limit = 0xFFFFFFFF,
8391 .selector = vmcs12->host_cs_selector,
8392 .type = 11,
8393 .present = 1,
8394 .s = 1,
8395 .g = 1
8396 };
8397 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8398 seg.l = 1;
8399 else
8400 seg.db = 1;
8401 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8402 seg = (struct kvm_segment) {
8403 .base = 0,
8404 .limit = 0xFFFFFFFF,
8405 .type = 3,
8406 .present = 1,
8407 .s = 1,
8408 .db = 1,
8409 .g = 1
8410 };
8411 seg.selector = vmcs12->host_ds_selector;
8412 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8413 seg.selector = vmcs12->host_es_selector;
8414 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8415 seg.selector = vmcs12->host_ss_selector;
8416 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8417 seg.selector = vmcs12->host_fs_selector;
8418 seg.base = vmcs12->host_fs_base;
8419 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8420 seg.selector = vmcs12->host_gs_selector;
8421 seg.base = vmcs12->host_gs_base;
8422 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8423 seg = (struct kvm_segment) {
205befd9 8424 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8425 .limit = 0x67,
8426 .selector = vmcs12->host_tr_selector,
8427 .type = 11,
8428 .present = 1
8429 };
8430 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8431
503cd0c5
JK		 8432 kvm_set_dr(vcpu, 7, 0x400);
8433 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8434}
8435
8436/*
8437 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8438 * and modify vmcs12 to make it see what it would expect to see there if
8439 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8440 */
8441static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8442{
8443 struct vcpu_vmx *vmx = to_vmx(vcpu);
8444 int cpu;
8445 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8446
5f3d5799
JK		 8447 /* trying to cancel vmlaunch/vmresume is a bug */
8448 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8449
4704d0be
NHE		 8450 leave_guest_mode(vcpu);
8451 prepare_vmcs12(vcpu, vmcs12);
8452
8453 cpu = get_cpu();
8454 vmx->loaded_vmcs = &vmx->vmcs01;
8455 vmx_vcpu_put(vcpu);
8456 vmx_vcpu_load(vcpu, cpu);
8457 vcpu->cpu = cpu;
8458 put_cpu();
8459
2961e876
GN		 8460 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8461 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8462 vmx_segment_cache_clear(vmx);
8463
4704d0be
NHE		 8464 /* if no vmcs02 cache requested, remove the one we used */
8465 if (VMCS02_POOL_SIZE == 0)
8466 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8467
8468 load_vmcs12_host_state(vcpu, vmcs12);
8469
27fc51b2 8470 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8471 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8472
8473 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8474 vmx->host_rsp = 0;
8475
8476 /* Unpin physical memory we referred to in vmcs02 */
8477 if (vmx->nested.apic_access_page) {
8478 nested_release_page(vmx->nested.apic_access_page);
8479 vmx->nested.apic_access_page = 0;
8480 }
8481
8482 /*
8483 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8484 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8485 * success or failure flag accordingly.
8486 */
8487 if (unlikely(vmx->fail)) {
8488 vmx->fail = 0;
8489 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8490 } else
8491 nested_vmx_succeed(vcpu);
012f83cb
AG		 8492 if (enable_shadow_vmcs)
8493 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8494}
8495
7c177938
NHE		 8496/*
8497 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8498 * 23.7 "VM-entry failures during or after loading guest state" (this also
8499 * lists the acceptable exit-reason and exit-qualification parameters).
8500 * It should only be called before L2 actually succeeded to run, and when
8501 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8502 */
8503static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8504 struct vmcs12 *vmcs12,
8505 u32 reason, unsigned long qualification)
8506{
8507 load_vmcs12_host_state(vcpu, vmcs12);
8508 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8509 vmcs12->exit_qualification = qualification;
8510 nested_vmx_succeed(vcpu);
012f83cb
AG		 8511 if (enable_shadow_vmcs)
8512 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8513}
8514
8a76d7f2
JR		 8515static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8516 struct x86_instruction_info *info,
8517 enum x86_intercept_stage stage)
8518{
8519 return X86EMUL_CONTINUE;
8520}
8521
cbdd1bea 8522static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8523 .cpu_has_kvm_support = cpu_has_kvm_support,
8524 .disabled_by_bios = vmx_disabled_by_bios,
8525 .hardware_setup = hardware_setup,
8526 .hardware_unsetup = hardware_unsetup,
002c7f7c 8527 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8528 .hardware_enable = hardware_enable,
8529 .hardware_disable = hardware_disable,
04547156 8530 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8531
8532 .vcpu_create = vmx_create_vcpu,
8533 .vcpu_free = vmx_free_vcpu,
04d2cc77 8534 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8535
04d2cc77 8536 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8537 .vcpu_load = vmx_vcpu_load,
8538 .vcpu_put = vmx_vcpu_put,
8539
c8639010 8540 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8541 .get_msr = vmx_get_msr,
8542 .set_msr = vmx_set_msr,
8543 .get_segment_base = vmx_get_segment_base,
8544 .get_segment = vmx_get_segment,
8545 .set_segment = vmx_set_segment,
2e4d2653 8546 .get_cpl = vmx_get_cpl,
6aa8b732 8547 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8548 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8549 .decache_cr3 = vmx_decache_cr3,
25c4c276 8550 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8551 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8552 .set_cr3 = vmx_set_cr3,
8553 .set_cr4 = vmx_set_cr4,
6aa8b732 8554 .set_efer = vmx_set_efer,
6aa8b732
AK		 8555 .get_idt = vmx_get_idt,
8556 .set_idt = vmx_set_idt,
8557 .get_gdt = vmx_get_gdt,
8558 .set_gdt = vmx_set_gdt,
020df079 8559 .set_dr7 = vmx_set_dr7,
5fdbf976 8560 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8561 .get_rflags = vmx_get_rflags,
8562 .set_rflags = vmx_set_rflags,
ebcbab4c 8563 .fpu_activate = vmx_fpu_activate,
02daab21 8564 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8565
8566 .tlb_flush = vmx_flush_tlb,
6aa8b732 8567
6aa8b732 8568 .run = vmx_vcpu_run,
6062d012 8569 .handle_exit = vmx_handle_exit,
6aa8b732 8570 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8571 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8572 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8573 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8574 .set_irq = vmx_inject_irq,
95ba8273 8575 .set_nmi = vmx_inject_nmi,
298101da 8576 .queue_exception = vmx_queue_exception,
b463a6f7 8577 .cancel_injection = vmx_cancel_injection,
78646121 8578 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8579 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8580 .get_nmi_mask = vmx_get_nmi_mask,
8581 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8582 .enable_nmi_window = enable_nmi_window,
8583 .enable_irq_window = enable_irq_window,
8584 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8585 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8586 .vm_has_apicv = vmx_vm_has_apicv,
8587 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8588 .hwapic_irr_update = vmx_hwapic_irr_update,
8589 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8590 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8591 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8592
cbc94022 8593 .set_tss_addr = vmx_set_tss_addr,
67253af5 8594 .get_tdp_level = get_ept_level,
4b12f0de 8595 .get_mt_mask = vmx_get_mt_mask,
229456fc 8596
586f9607 8597 .get_exit_info = vmx_get_exit_info,
586f9607 8598
17cc3935 8599 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8600
8601 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8602
8603 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8604 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8605
8606 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8607
8608 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8609
4051b188 8610 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8611 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8612 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8613 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8614 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8615 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8616
8617 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8618
8619 .check_intercept = vmx_check_intercept,
a547c6db 8620 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8621};
8622
8623static int __init vmx_init(void)
8624{
8d14695f 8625 int r, i, msr;
26bb0981
AK		 8626
8627 rdmsrl_safe(MSR_EFER, &host_efer);
8628
8629 for (i = 0; i < NR_VMX_MSR; ++i)
8630 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8631
3e7c73e9 8632 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8633 if (!vmx_io_bitmap_a)
8634 return -ENOMEM;
8635
2106a548
GC		 8636 r = -ENOMEM;
8637
3e7c73e9 8638 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8639 if (!vmx_io_bitmap_b)
fdef3ad1 8640 goto out;
fdef3ad1 8641
5897297b 8642 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8643 if (!vmx_msr_bitmap_legacy)
25c5f225 8644 goto out1;
2106a548 8645
8d14695f
YZ		 8646 vmx_msr_bitmap_legacy_x2apic =
8647 (unsigned long *)__get_free_page(GFP_KERNEL);
8648 if (!vmx_msr_bitmap_legacy_x2apic)
8649 goto out2;
25c5f225 8650
5897297b 8651 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8652 if (!vmx_msr_bitmap_longmode)
8d14695f 8653 goto out3;
2106a548 8654
8d14695f
YZ		 8655 vmx_msr_bitmap_longmode_x2apic =
8656 (unsigned long *)__get_free_page(GFP_KERNEL);
8657 if (!vmx_msr_bitmap_longmode_x2apic)
8658 goto out4;
4607c2d7
AG		 8659 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8660 if (!vmx_vmread_bitmap)
8661 goto out5;
8662
8663 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8664 if (!vmx_vmwrite_bitmap)
8665 goto out6;
8666
8667 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8668 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8669 /* shadowed read/write fields */
8670 for (i = 0; i < max_shadow_read_write_fields; i++) {
8671 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8672 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8673 }
8674 /* shadowed read only fields */
8675 for (i = 0; i < max_shadow_read_only_fields; i++)
8676 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8677
fdef3ad1
HQ		 8678 /*
8679 * Allow direct access to the PC debug port (it is often used for I/O
8680 * delays, but the vmexits simply slow things down).
8681 */
3e7c73e9
AK		 8682 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8683 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8684
3e7c73e9 8685 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8686
5897297b
AK		 8687 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8688 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8689
2384d2b3
SY		 8690 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8691
0ee75bea
AK		 8692 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8693 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8694 if (r)
4607c2d7 8695 goto out7;
25c5f225 8696
8f536b76
ZY		 8697#ifdef CONFIG_KEXEC
8698 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8699 crash_vmclear_local_loaded_vmcss);
8700#endif
8701
5897297b
AK		 8702 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8703 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8704 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8705 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8706 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8707 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8708 memcpy(vmx_msr_bitmap_legacy_x2apic,
8709 vmx_msr_bitmap_legacy, PAGE_SIZE);
8710 memcpy(vmx_msr_bitmap_longmode_x2apic,
8711 vmx_msr_bitmap_longmode, PAGE_SIZE);
8712
01e439be 8713 if (enable_apicv) {
8d14695f
YZ		 8714 for (msr = 0x800; msr <= 0x8ff; msr++)
8715 vmx_disable_intercept_msr_read_x2apic(msr);
8716
8717 /* According SDM, in x2apic mode, the whole id reg is used.
8718 * But in KVM, it only use the highest eight bits. Need to
8719 * intercept it */
8720 vmx_enable_intercept_msr_read_x2apic(0x802);
8721 /* TMCCT */
8722 vmx_enable_intercept_msr_read_x2apic(0x839);
8723 /* TPR */
8724 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8725 /* EOI */
8726 vmx_disable_intercept_msr_write_x2apic(0x80b);
8727 /* SELF-IPI */
8728 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8729 }
fdef3ad1 8730
089d034e 8731 if (enable_ept) {
3f6d8c8a
XH		 8732 kvm_mmu_set_mask_ptes(0ull,
8733 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8734 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8735 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8736 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8737 kvm_enable_tdp();
8738 } else
8739 kvm_disable_tdp();
1439442c 8740
fdef3ad1
HQ		 8741 return 0;
8742
4607c2d7
AG		 8743out7:
8744 free_page((unsigned long)vmx_vmwrite_bitmap);
8745out6:
8746 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8747out5:
8748 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8749out4:
5897297b 8750 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8751out3:
8752 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8753out2:
5897297b 8754 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8755out1:
3e7c73e9 8756 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8757out:
3e7c73e9 8758 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8759 return r;
6aa8b732
AK		 8760}
8761
8762static void __exit vmx_exit(void)
8763{
8d14695f
YZ		 8764 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8765 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8766 free_page((unsigned long)vmx_msr_bitmap_legacy);
8767 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8768 free_page((unsigned long)vmx_io_bitmap_b);
8769 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8770 free_page((unsigned long)vmx_vmwrite_bitmap);
8771 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8772
8f536b76
ZY		 8773#ifdef CONFIG_KEXEC
8774 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8775 synchronize_rcu();
8776#endif
8777
cb498ea2 8778 kvm_exit();
6aa8b732
AK		 8779}
8780
8781module_init(vmx_init)
8782module_exit(vmx_exit)
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