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Merge remote-tracking branch 'tip/x86/cpufeature' into kvm-next
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93 1500 if (i == NR_AUTOLOAD_MSRS) {
60266204 1501 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1901 */
e011c663 1902static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1903{
1904 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1905
e011c663 1906 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1907 return 0;
1908
1909 nested_vmx_vmexit(vcpu);
1910 return 1;
1911}
1912
298101da 1913static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1914 bool has_error_code, u32 error_code,
1915 bool reinject)
298101da 1916{
77ab6db0 1917 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1918 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1919
e011c663
GN		 1920 if (!reinject && is_guest_mode(vcpu) &&
1921 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1922 return;
1923
8ab2d2e2 1924 if (has_error_code) {
77ab6db0 1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1926 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1927 }
77ab6db0 1928
7ffd92c5 1929 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1930 int inc_eip = 0;
1931 if (kvm_exception_is_soft(nr))
1932 inc_eip = vcpu->arch.event_exit_inst_len;
1933 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1935 return;
1936 }
1937
66fd3f7f
GN		 1938 if (kvm_exception_is_soft(nr)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1940 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1941 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1942 } else
1943 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1944
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1946}
1947
4e47c7a6
SY		 1948static bool vmx_rdtscp_supported(void)
1949{
1950 return cpu_has_vmx_rdtscp();
1951}
1952
ad756a16
MJ		 1953static bool vmx_invpcid_supported(void)
1954{
1955 return cpu_has_vmx_invpcid() && enable_ept;
1956}
1957
a75beee6
ED		 1958/*
1959 * Swap MSR entry in host/guest MSR entry array.
1960 */
8b9cf98c 1961static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1962{
26bb0981 1963 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1964
1965 tmp = vmx->guest_msrs[to];
1966 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1967 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1968}
1969
8d14695f
YZ		 1970static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1971{
1972 unsigned long *msr_bitmap;
1973
1974 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1975 if (is_long_mode(vcpu))
1976 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1977 else
1978 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1979 } else {
1980 if (is_long_mode(vcpu))
1981 msr_bitmap = vmx_msr_bitmap_longmode;
1982 else
1983 msr_bitmap = vmx_msr_bitmap_legacy;
1984 }
1985
1986 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1987}
1988
e38aea3e
AK		 1989/*
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1993 */
8b9cf98c 1994static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1995{
26bb0981 1996 int save_nmsrs, index;
e38aea3e 1997
a75beee6
ED		 1998 save_nmsrs = 0;
1999#ifdef CONFIG_X86_64
8b9cf98c 2000 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2001 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2002 if (index >= 0)
8b9cf98c
RR		 2003 move_msr_up(vmx, index, save_nmsrs++);
2004 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2005 if (index >= 0)
8b9cf98c
RR		 2006 move_msr_up(vmx, index, save_nmsrs++);
2007 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2008 if (index >= 0)
8b9cf98c 2009 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2010 index = __find_msr_index(vmx, MSR_TSC_AUX);
2011 if (index >= 0 && vmx->rdtscp_enabled)
2012 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2013 /*
8c06585d 2014 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2015 * if efer.sce is enabled.
2016 */
8c06585d 2017 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2018 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2019 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2020 }
2021#endif
92c0d900
AK		 2022 index = __find_msr_index(vmx, MSR_EFER);
2023 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2024 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2025
26bb0981 2026 vmx->save_nmsrs = save_nmsrs;
5897297b 2027
8d14695f
YZ		 2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2030}
2031
6aa8b732
AK		 2032/*
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2035 */
2036static u64 guest_read_tsc(void)
2037{
2038 u64 host_tsc, tsc_offset;
2039
2040 rdtscll(host_tsc);
2041 tsc_offset = vmcs_read64(TSC_OFFSET);
2042 return host_tsc + tsc_offset;
2043}
2044
d5c1785d
NHE		 2045/*
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2048 */
886b470c 2049u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2050{
886b470c 2051 u64 tsc_offset;
d5c1785d 2052
d5c1785d
NHE		 2053 tsc_offset = is_guest_mode(vcpu) ?
2054 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2055 vmcs_read64(TSC_OFFSET);
2056 return host_tsc + tsc_offset;
2057}
2058
4051b188 2059/*
cc578287
ZA		 2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
4051b188 2062 */
cc578287 2063static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2064{
cc578287
ZA		 2065 if (!scale)
2066 return;
2067
2068 if (user_tsc_khz > tsc_khz) {
2069 vcpu->arch.tsc_catchup = 1;
2070 vcpu->arch.tsc_always_catchup = 1;
2071 } else
2072 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2073}
2074
ba904635
WA		 2075static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2076{
2077 return vmcs_read64(TSC_OFFSET);
2078}
2079
6aa8b732 2080/*
99e3e30a 2081 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2082 */
99e3e30a 2083static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2084{
27fc51b2 2085 if (is_guest_mode(vcpu)) {
7991825b 2086 /*
27fc51b2
NHE		 2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
7991825b 2091 */
27fc51b2
NHE		 2092 struct vmcs12 *vmcs12;
2093 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12 = get_vmcs12(vcpu);
2096 vmcs_write64(TSC_OFFSET, offset +
2097 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2098 vmcs12->tsc_offset : 0));
2099 } else {
489223ed
YY		 2100 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2101 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2102 vmcs_write64(TSC_OFFSET, offset);
2103 }
6aa8b732
AK		 2104}
2105
f1e2b260 2106static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2107{
2108 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2109
e48672fa 2110 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2111 if (is_guest_mode(vcpu)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2114 } else
2115 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2116 offset + adjustment);
e48672fa
ZA		 2117}
2118
857e4099
JR		 2119static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2120{
2121 return target_tsc - native_read_tsc();
2122}
2123
801d3424
NHE		 2124static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2125{
2126 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2127 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2128}
2129
2130/*
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2135 */
2136static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2137{
2138 return nested && guest_cpuid_has_vmx(vcpu);
2139}
2140
b87a51ae
NHE		 2141/*
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2151 * or other means.
2152 */
2153static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2154static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2155static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2156static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2157static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2158static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2159static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2160static __init void nested_vmx_setup_ctls_msrs(void)
2161{
2162 /*
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2175 */
2176
2177 /* pin-based controls */
eabeaacc
JK		 2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2179 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2180 /*
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2183 */
eabeaacc
JK		 2184 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2185 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2186 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2187 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2188 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2189
33fb20c3
JK		 2190 /*
2191 * Exit controls
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2193 * 17 must be 1.
2194 */
c0dfee58
ACL		 2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2196 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2197 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2199 nested_vmx_exit_ctls_high &=
b87a51ae 2200#ifdef CONFIG_X86_64
c0dfee58 2201 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2202#endif
7854cbca
ACL		 2203 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2204 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2205 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2206 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2207 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2208 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2209 }
8049d651 2210 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2211 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2212
2213 /* entry controls */
2214 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2215 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2216 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2217 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2218 nested_vmx_entry_ctls_high &=
57435349
JK		 2219#ifdef CONFIG_X86_64
2220 VM_ENTRY_IA32E_MODE |
2221#endif
2222 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2223 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2224 VM_ENTRY_LOAD_IA32_EFER);
57435349 2225
b87a51ae
NHE		 2226 /* cpu-based controls */
2227 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2228 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2229 nested_vmx_procbased_ctls_low = 0;
2230 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2231 CPU_BASED_VIRTUAL_INTR_PENDING |
2232 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2233 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2234 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2235 CPU_BASED_CR3_STORE_EXITING |
2236#ifdef CONFIG_X86_64
2237 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2238#endif
2239 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2240 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2241 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2242 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2243 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2244 /*
2245 * We can allow some features even when not supported by the
2246 * hardware. For example, L1 can specify an MSR bitmap - and we
2247 * can use it to avoid exits to L1 - even when L0 runs L2
2248 * without MSR bitmaps.
2249 */
2250 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2251
2252 /* secondary cpu-based controls */
2253 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2254 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2255 nested_vmx_secondary_ctls_low = 0;
2256 nested_vmx_secondary_ctls_high &=
d6851fbe 2257 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2258 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2259 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2260
afa61f75
NHE		 2261 if (enable_ept) {
2262 /* nested EPT: emulate EPT also to L1 */
2263 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2264 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2265 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2266 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2267 nested_vmx_ept_caps &= vmx_capability.ept;
2268 /*
2269 * Since invept is completely emulated we support both global
2270 * and context invalidation independent of what host cpu
2271 * supports
2272 */
2273 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2274 VMX_EPT_EXTENT_CONTEXT_BIT;
2275 } else
2276 nested_vmx_ept_caps = 0;
2277
c18911a2
JK		 2278 /* miscellaneous data */
2279 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2280 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2281 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2282 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2283}
2284
2285static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2286{
2287 /*
2288 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2289 */
2290 return ((control & high) | low) == control;
2291}
2292
2293static inline u64 vmx_control_msr(u32 low, u32 high)
2294{
2295 return low | ((u64)high << 32);
2296}
2297
2298/*
2299 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2300 * also let it use VMX-specific MSRs.
2301 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2302 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2303 * like all other MSRs).
2304 */
2305static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2306{
2307 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2308 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2309 /*
2310 * According to the spec, processors which do not support VMX
2311 * should throw a #GP(0) when VMX capability MSRs are read.
2312 */
2313 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2314 return 1;
2315 }
2316
2317 switch (msr_index) {
2318 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2319 if (nested_vmx_allowed(vcpu)) {
2320 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2321 break;
2322 }
2323 return 0;
b87a51ae
NHE		 2324 case MSR_IA32_VMX_BASIC:
2325 /*
2326 * This MSR reports some information about VMX support. We
2327 * should return information about the VMX we emulate for the
2328 * guest, and the VMCS structure we give it - not about the
2329 * VMX support of the underlying hardware.
2330 */
2331 *pdata = VMCS12_REVISION |
2332 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2333 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2334 break;
2335 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2336 case MSR_IA32_VMX_PINBASED_CTLS:
2337 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2338 nested_vmx_pinbased_ctls_high);
2339 break;
2340 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2341 case MSR_IA32_VMX_PROCBASED_CTLS:
2342 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2343 nested_vmx_procbased_ctls_high);
2344 break;
2345 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2346 case MSR_IA32_VMX_EXIT_CTLS:
2347 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2348 nested_vmx_exit_ctls_high);
2349 break;
2350 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2351 case MSR_IA32_VMX_ENTRY_CTLS:
2352 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2353 nested_vmx_entry_ctls_high);
2354 break;
2355 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2356 *pdata = vmx_control_msr(nested_vmx_misc_low,
2357 nested_vmx_misc_high);
b87a51ae
NHE		 2358 break;
2359 /*
2360 * These MSRs specify bits which the guest must keep fixed (on or off)
2361 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2362 * We picked the standard core2 setting.
2363 */
2364#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2365#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2366 case MSR_IA32_VMX_CR0_FIXED0:
2367 *pdata = VMXON_CR0_ALWAYSON;
2368 break;
2369 case MSR_IA32_VMX_CR0_FIXED1:
2370 *pdata = -1ULL;
2371 break;
2372 case MSR_IA32_VMX_CR4_FIXED0:
2373 *pdata = VMXON_CR4_ALWAYSON;
2374 break;
2375 case MSR_IA32_VMX_CR4_FIXED1:
2376 *pdata = -1ULL;
2377 break;
2378 case MSR_IA32_VMX_VMCS_ENUM:
2379 *pdata = 0x1f;
2380 break;
2381 case MSR_IA32_VMX_PROCBASED_CTLS2:
2382 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2383 nested_vmx_secondary_ctls_high);
2384 break;
2385 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2386 /* Currently, no nested vpid support */
2387 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2388 break;
2389 default:
2390 return 0;
2391 }
2392
2393 return 1;
2394}
2395
b3897a49 2396static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2397{
b3897a49
NHE		 2398 u32 msr_index = msr_info->index;
2399 u64 data = msr_info->data;
2400 bool host_initialized = msr_info->host_initiated;
2401
b87a51ae
NHE		 2402 if (!nested_vmx_allowed(vcpu))
2403 return 0;
2404
b3897a49
NHE		 2405 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2406 if (!host_initialized &&
2407 to_vmx(vcpu)->nested.msr_ia32_feature_control
2408 & FEATURE_CONTROL_LOCKED)
2409 return 0;
2410 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2411 return 1;
b3897a49
NHE		 2412 }
2413
b87a51ae
NHE		 2414 /*
2415 * No need to treat VMX capability MSRs specially: If we don't handle
2416 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2417 */
2418 return 0;
2419}
2420
6aa8b732
AK		 2421/*
2422 * Reads an msr value (of 'msr_index') into 'pdata'.
2423 * Returns 0 on success, non-0 otherwise.
2424 * Assumes vcpu_load() was already called.
2425 */
2426static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2427{
2428 u64 data;
26bb0981 2429 struct shared_msr_entry *msr;
6aa8b732
AK		 2430
2431 if (!pdata) {
2432 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2433 return -EINVAL;
2434 }
2435
2436 switch (msr_index) {
05b3e0c2 2437#ifdef CONFIG_X86_64
6aa8b732
AK		 2438 case MSR_FS_BASE:
2439 data = vmcs_readl(GUEST_FS_BASE);
2440 break;
2441 case MSR_GS_BASE:
2442 data = vmcs_readl(GUEST_GS_BASE);
2443 break;
44ea2b17
AK		 2444 case MSR_KERNEL_GS_BASE:
2445 vmx_load_host_state(to_vmx(vcpu));
2446 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2447 break;
26bb0981 2448#endif
6aa8b732 2449 case MSR_EFER:
3bab1f5d 2450 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2451 case MSR_IA32_TSC:
6aa8b732
AK		 2452 data = guest_read_tsc();
2453 break;
2454 case MSR_IA32_SYSENTER_CS:
2455 data = vmcs_read32(GUEST_SYSENTER_CS);
2456 break;
2457 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2458 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2459 break;
2460 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2461 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2462 break;
4e47c7a6
SY		 2463 case MSR_TSC_AUX:
2464 if (!to_vmx(vcpu)->rdtscp_enabled)
2465 return 1;
2466 /* Otherwise falls through */
6aa8b732 2467 default:
b87a51ae
NHE		 2468 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2469 return 0;
8b9cf98c 2470 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2471 if (msr) {
2472 data = msr->data;
2473 break;
6aa8b732 2474 }
3bab1f5d 2475 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2476 }
2477
2478 *pdata = data;
2479 return 0;
2480}
2481
2482/*
2483 * Writes msr value into into the appropriate "register".
2484 * Returns 0 on success, non-0 otherwise.
2485 * Assumes vcpu_load() was already called.
2486 */
8fe8ab46 2487static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2488{
a2fa3e9f 2489 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2490 struct shared_msr_entry *msr;
2cc51560 2491 int ret = 0;
8fe8ab46
WA		 2492 u32 msr_index = msr_info->index;
2493 u64 data = msr_info->data;
2cc51560 2494
6aa8b732 2495 switch (msr_index) {
3bab1f5d 2496 case MSR_EFER:
8fe8ab46 2497 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2498 break;
16175a79 2499#ifdef CONFIG_X86_64
6aa8b732 2500 case MSR_FS_BASE:
2fb92db1 2501 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2502 vmcs_writel(GUEST_FS_BASE, data);
2503 break;
2504 case MSR_GS_BASE:
2fb92db1 2505 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2506 vmcs_writel(GUEST_GS_BASE, data);
2507 break;
44ea2b17
AK		 2508 case MSR_KERNEL_GS_BASE:
2509 vmx_load_host_state(vmx);
2510 vmx->msr_guest_kernel_gs_base = data;
2511 break;
6aa8b732
AK		 2512#endif
2513 case MSR_IA32_SYSENTER_CS:
2514 vmcs_write32(GUEST_SYSENTER_CS, data);
2515 break;
2516 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2517 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2518 break;
2519 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2520 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2521 break;
af24a4e4 2522 case MSR_IA32_TSC:
8fe8ab46 2523 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2524 break;
468d472f
SY		 2525 case MSR_IA32_CR_PAT:
2526 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2527 vmcs_write64(GUEST_IA32_PAT, data);
2528 vcpu->arch.pat = data;
2529 break;
2530 }
8fe8ab46 2531 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2532 break;
ba904635
WA		 2533 case MSR_IA32_TSC_ADJUST:
2534 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2535 break;
2536 case MSR_TSC_AUX:
2537 if (!vmx->rdtscp_enabled)
2538 return 1;
2539 /* Check reserved bit, higher 32 bits should be zero */
2540 if ((data >> 32) != 0)
2541 return 1;
2542 /* Otherwise falls through */
6aa8b732 2543 default:
b3897a49 2544 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2545 break;
8b9cf98c 2546 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2547 if (msr) {
2548 msr->data = data;
2225fd56
AK		 2549 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2550 preempt_disable();
9ee73970
AK		 2551 kvm_set_shared_msr(msr->index, msr->data,
2552 msr->mask);
2225fd56
AK		 2553 preempt_enable();
2554 }
3bab1f5d 2555 break;
6aa8b732 2556 }
8fe8ab46 2557 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2558 }
2559
2cc51560 2560 return ret;
6aa8b732
AK		 2561}
2562
5fdbf976 2563static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2564{
5fdbf976
MT		 2565 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2566 switch (reg) {
2567 case VCPU_REGS_RSP:
2568 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2569 break;
2570 case VCPU_REGS_RIP:
2571 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2572 break;
6de4f3ad
AK		 2573 case VCPU_EXREG_PDPTR:
2574 if (enable_ept)
2575 ept_save_pdptrs(vcpu);
2576 break;
5fdbf976
MT		 2577 default:
2578 break;
2579 }
6aa8b732
AK		 2580}
2581
6aa8b732
AK		 2582static __init int cpu_has_kvm_support(void)
2583{
6210e37b 2584 return cpu_has_vmx();
6aa8b732
AK		 2585}
2586
2587static __init int vmx_disabled_by_bios(void)
2588{
2589 u64 msr;
2590
2591 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2592 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2593 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2594 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2595 && tboot_enabled())
2596 return 1;
23f3e991 2597 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2598 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2599 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2600 && !tboot_enabled()) {
2601 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2602 "activate TXT before enabling KVM\n");
cafd6659 2603 return 1;
f9335afe 2604 }
23f3e991
JC		 2605 /* launched w/o TXT and VMX disabled */
2606 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2607 && !tboot_enabled())
2608 return 1;
cafd6659
SW		 2609 }
2610
2611 return 0;
6aa8b732
AK		 2612}
2613
7725b894
DX		 2614static void kvm_cpu_vmxon(u64 addr)
2615{
2616 asm volatile (ASM_VMX_VMXON_RAX
2617 : : "a"(&addr), "m"(addr)
2618 : "memory", "cc");
2619}
2620
10474ae8 2621static int hardware_enable(void *garbage)
6aa8b732
AK		 2622{
2623 int cpu = raw_smp_processor_id();
2624 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2625 u64 old, test_bits;
6aa8b732 2626
10474ae8
AG		 2627 if (read_cr4() & X86_CR4_VMXE)
2628 return -EBUSY;
2629
d462b819 2630 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2631
2632 /*
2633 * Now we can enable the vmclear operation in kdump
2634 * since the loaded_vmcss_on_cpu list on this cpu
2635 * has been initialized.
2636 *
2637 * Though the cpu is not in VMX operation now, there
2638 * is no problem to enable the vmclear operation
2639 * for the loaded_vmcss_on_cpu list is empty!
2640 */
2641 crash_enable_local_vmclear(cpu);
2642
6aa8b732 2643 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2644
2645 test_bits = FEATURE_CONTROL_LOCKED;
2646 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2647 if (tboot_enabled())
2648 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2649
2650 if ((old & test_bits) != test_bits) {
6aa8b732 2651 /* enable and lock */
cafd6659
SW		 2652 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2653 }
66aee91a 2654 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2655
4610c9cc
DX		 2656 if (vmm_exclusive) {
2657 kvm_cpu_vmxon(phys_addr);
2658 ept_sync_global();
2659 }
10474ae8 2660
357d1226 2661 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2662
10474ae8 2663 return 0;
6aa8b732
AK		 2664}
2665
d462b819 2666static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2667{
2668 int cpu = raw_smp_processor_id();
d462b819 2669 struct loaded_vmcs *v, *n;
543e4243 2670
d462b819
NHE		 2671 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2672 loaded_vmcss_on_cpu_link)
2673 __loaded_vmcs_clear(v);
543e4243
AK		 2674}
2675
710ff4a8
EH		 2676
2677/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2678 * tricks.
2679 */
2680static void kvm_cpu_vmxoff(void)
6aa8b732 2681{
4ecac3fd 2682 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2683}
2684
710ff4a8
EH		 2685static void hardware_disable(void *garbage)
2686{
4610c9cc 2687 if (vmm_exclusive) {
d462b819 2688 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2689 kvm_cpu_vmxoff();
2690 }
7725b894 2691 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2692}
2693
1c3d14fe 2694static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2695 u32 msr, u32 *result)
1c3d14fe
YS		 2696{
2697 u32 vmx_msr_low, vmx_msr_high;
2698 u32 ctl = ctl_min | ctl_opt;
2699
2700 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2701
2702 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2703 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2704
2705 /* Ensure minimum (required) set of control bits are supported. */
2706 if (ctl_min & ~ctl)
002c7f7c 2707 return -EIO;
1c3d14fe
YS		 2708
2709 *result = ctl;
2710 return 0;
2711}
2712
110312c8
AK		 2713static __init bool allow_1_setting(u32 msr, u32 ctl)
2714{
2715 u32 vmx_msr_low, vmx_msr_high;
2716
2717 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2718 return vmx_msr_high & ctl;
2719}
2720
002c7f7c 2721static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2722{
2723 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2724 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2725 u32 _pin_based_exec_control = 0;
2726 u32 _cpu_based_exec_control = 0;
f78e0e2e 2727 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2728 u32 _vmexit_control = 0;
2729 u32 _vmentry_control = 0;
2730
10166744 2731 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2732#ifdef CONFIG_X86_64
2733 CPU_BASED_CR8_LOAD_EXITING |
2734 CPU_BASED_CR8_STORE_EXITING |
2735#endif
d56f546d
SY		 2736 CPU_BASED_CR3_LOAD_EXITING |
2737 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2738 CPU_BASED_USE_IO_BITMAPS |
2739 CPU_BASED_MOV_DR_EXITING |
a7052897 2740 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2741 CPU_BASED_MWAIT_EXITING |
2742 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2743 CPU_BASED_INVLPG_EXITING |
2744 CPU_BASED_RDPMC_EXITING;
443381a8 2745
f78e0e2e 2746 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2747 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2748 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2749 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2750 &_cpu_based_exec_control) < 0)
002c7f7c 2751 return -EIO;
6e5d865c
YS		 2752#ifdef CONFIG_X86_64
2753 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2754 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2755 ~CPU_BASED_CR8_STORE_EXITING;
2756#endif
f78e0e2e 2757 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2758 min2 = 0;
2759 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2760 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2761 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2762 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2763 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2764 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2765 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2766 SECONDARY_EXEC_RDTSCP |
83d4c286 2767 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2768 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2769 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2770 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2771 if (adjust_vmx_controls(min2, opt2,
2772 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2773 &_cpu_based_2nd_exec_control) < 0)
2774 return -EIO;
2775 }
2776#ifndef CONFIG_X86_64
2777 if (!(_cpu_based_2nd_exec_control &
2778 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2779 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2780#endif
83d4c286
YZ		 2781
2782 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2783 _cpu_based_2nd_exec_control &= ~(
8d14695f 2784 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2785 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2786 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2787
d56f546d 2788 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2789 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2790 enabled */
5fff7d27
GN		 2791 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2792 CPU_BASED_CR3_STORE_EXITING |
2793 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2794 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2795 vmx_capability.ept, vmx_capability.vpid);
2796 }
1c3d14fe
YS		 2797
2798 min = 0;
2799#ifdef CONFIG_X86_64
2800 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2801#endif
a547c6db
YZ		 2802 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2803 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2804 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2805 &_vmexit_control) < 0)
002c7f7c 2806 return -EIO;
1c3d14fe 2807
01e439be
YZ		 2808 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2809 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2810 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2811 &_pin_based_exec_control) < 0)
2812 return -EIO;
2813
2814 if (!(_cpu_based_2nd_exec_control &
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2816 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2817 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2818
468d472f
SY		 2819 min = 0;
2820 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2821 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2822 &_vmentry_control) < 0)
002c7f7c 2823 return -EIO;
6aa8b732 2824
c68876fd 2825 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2826
2827 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2828 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2829 return -EIO;
1c3d14fe
YS		 2830
2831#ifdef CONFIG_X86_64
2832 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2833 if (vmx_msr_high & (1u<<16))
002c7f7c 2834 return -EIO;
1c3d14fe
YS		 2835#endif
2836
2837 /* Require Write-Back (WB) memory type for VMCS accesses. */
2838 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2839 return -EIO;
1c3d14fe 2840
002c7f7c
YS		 2841 vmcs_conf->size = vmx_msr_high & 0x1fff;
2842 vmcs_conf->order = get_order(vmcs_config.size);
2843 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2844
002c7f7c
YS		 2845 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2846 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2847 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2848 vmcs_conf->vmexit_ctrl = _vmexit_control;
2849 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2850
110312c8
AK		 2851 cpu_has_load_ia32_efer =
2852 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2853 VM_ENTRY_LOAD_IA32_EFER)
2854 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2855 VM_EXIT_LOAD_IA32_EFER);
2856
8bf00a52
GN		 2857 cpu_has_load_perf_global_ctrl =
2858 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2859 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2860 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2861 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2862
2863 /*
2864 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2865 * but due to arrata below it can't be used. Workaround is to use
2866 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2867 *
2868 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2869 *
2870 * AAK155 (model 26)
2871 * AAP115 (model 30)
2872 * AAT100 (model 37)
2873 * BC86,AAY89,BD102 (model 44)
2874 * BA97 (model 46)
2875 *
2876 */
2877 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2878 switch (boot_cpu_data.x86_model) {
2879 case 26:
2880 case 30:
2881 case 37:
2882 case 44:
2883 case 46:
2884 cpu_has_load_perf_global_ctrl = false;
2885 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2886 "does not work properly. Using workaround\n");
2887 break;
2888 default:
2889 break;
2890 }
2891 }
2892
1c3d14fe 2893 return 0;
c68876fd 2894}
6aa8b732
AK		 2895
2896static struct vmcs *alloc_vmcs_cpu(int cpu)
2897{
2898 int node = cpu_to_node(cpu);
2899 struct page *pages;
2900 struct vmcs *vmcs;
2901
6484eb3e 2902 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2903 if (!pages)
2904 return NULL;
2905 vmcs = page_address(pages);
1c3d14fe
YS		 2906 memset(vmcs, 0, vmcs_config.size);
2907 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2908 return vmcs;
2909}
2910
2911static struct vmcs *alloc_vmcs(void)
2912{
d3b2c338 2913 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2914}
2915
2916static void free_vmcs(struct vmcs *vmcs)
2917{
1c3d14fe 2918 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2919}
2920
d462b819
NHE		 2921/*
2922 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2923 */
2924static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2925{
2926 if (!loaded_vmcs->vmcs)
2927 return;
2928 loaded_vmcs_clear(loaded_vmcs);
2929 free_vmcs(loaded_vmcs->vmcs);
2930 loaded_vmcs->vmcs = NULL;
2931}
2932
39959588 2933static void free_kvm_area(void)
6aa8b732
AK		 2934{
2935 int cpu;
2936
3230bb47 2937 for_each_possible_cpu(cpu) {
6aa8b732 2938 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2939 per_cpu(vmxarea, cpu) = NULL;
2940 }
6aa8b732
AK		 2941}
2942
6aa8b732
AK		 2943static __init int alloc_kvm_area(void)
2944{
2945 int cpu;
2946
3230bb47 2947 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2948 struct vmcs *vmcs;
2949
2950 vmcs = alloc_vmcs_cpu(cpu);
2951 if (!vmcs) {
2952 free_kvm_area();
2953 return -ENOMEM;
2954 }
2955
2956 per_cpu(vmxarea, cpu) = vmcs;
2957 }
2958 return 0;
2959}
2960
2961static __init int hardware_setup(void)
2962{
002c7f7c
YS		 2963 if (setup_vmcs_config(&vmcs_config) < 0)
2964 return -EIO;
50a37eb4
JR		 2965
2966 if (boot_cpu_has(X86_FEATURE_NX))
2967 kvm_enable_efer_bits(EFER_NX);
2968
93ba03c2
SY		 2969 if (!cpu_has_vmx_vpid())
2970 enable_vpid = 0;
abc4fc58
AG		 2971 if (!cpu_has_vmx_shadow_vmcs())
2972 enable_shadow_vmcs = 0;
93ba03c2 2973
4bc9b982
SY		 2974 if (!cpu_has_vmx_ept() ||
2975 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2976 enable_ept = 0;
3a624e29 2977 enable_unrestricted_guest = 0;
83c3a331 2978 enable_ept_ad_bits = 0;
3a624e29
NK		 2979 }
2980
83c3a331
XH		 2981 if (!cpu_has_vmx_ept_ad_bits())
2982 enable_ept_ad_bits = 0;
2983
3a624e29
NK		 2984 if (!cpu_has_vmx_unrestricted_guest())
2985 enable_unrestricted_guest = 0;
93ba03c2
SY		 2986
2987 if (!cpu_has_vmx_flexpriority())
2988 flexpriority_enabled = 0;
2989
95ba8273
GN		 2990 if (!cpu_has_vmx_tpr_shadow())
2991 kvm_x86_ops->update_cr8_intercept = NULL;
2992
54dee993
MT		 2993 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2994 kvm_disable_largepages();
2995
4b8d54f9
ZE		 2996 if (!cpu_has_vmx_ple())
2997 ple_gap = 0;
2998
01e439be
YZ		 2999 if (!cpu_has_vmx_apicv())
3000 enable_apicv = 0;
c7c9c56c 3001
01e439be 3002 if (enable_apicv)
c7c9c56c 3003 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3004 else {
c7c9c56c 3005 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3006 kvm_x86_ops->deliver_posted_interrupt = NULL;
3007 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3008 }
83d4c286 3009
b87a51ae
NHE		 3010 if (nested)
3011 nested_vmx_setup_ctls_msrs();
3012
6aa8b732
AK		 3013 return alloc_kvm_area();
3014}
3015
3016static __exit void hardware_unsetup(void)
3017{
3018 free_kvm_area();
3019}
3020
14168786
GN		 3021static bool emulation_required(struct kvm_vcpu *vcpu)
3022{
3023 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3024}
3025
91b0aa2c 3026static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3027 struct kvm_segment *save)
6aa8b732 3028{
d99e4152
GN		 3029 if (!emulate_invalid_guest_state) {
3030 /*
3031 * CS and SS RPL should be equal during guest entry according
3032 * to VMX spec, but in reality it is not always so. Since vcpu
3033 * is in the middle of the transition from real mode to
3034 * protected mode it is safe to assume that RPL 0 is a good
3035 * default value.
3036 */
3037 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3038 save->selector &= ~SELECTOR_RPL_MASK;
3039 save->dpl = save->selector & SELECTOR_RPL_MASK;
3040 save->s = 1;
6aa8b732 3041 }
d99e4152 3042 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3043}
3044
3045static void enter_pmode(struct kvm_vcpu *vcpu)
3046{
3047 unsigned long flags;
a89a8fb9 3048 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3049
d99e4152
GN		 3050 /*
3051 * Update real mode segment cache. It may be not up-to-date if sement
3052 * register was written while vcpu was in a guest mode.
3053 */
3054 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3055 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3056 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3057 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3058 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3059 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3060
7ffd92c5 3061 vmx->rmode.vm86_active = 0;
6aa8b732 3062
2fb92db1
AK		 3063 vmx_segment_cache_clear(vmx);
3064
f5f7b2fe 3065 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3066
3067 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3068 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3069 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3070 vmcs_writel(GUEST_RFLAGS, flags);
3071
66aee91a
RR		 3072 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3073 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3074
3075 update_exception_bitmap(vcpu);
3076
91b0aa2c
GN		 3077 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3078 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3079 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3080 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3081 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3082 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3083
3084 /* CPL is always 0 when CPU enters protected mode */
3085 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3086 vmx->cpl = 0;
6aa8b732
AK		 3087}
3088
f5f7b2fe 3089static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3090{
772e0318 3091 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3092 struct kvm_segment var = *save;
3093
3094 var.dpl = 0x3;
3095 if (seg == VCPU_SREG_CS)
3096 var.type = 0x3;
3097
3098 if (!emulate_invalid_guest_state) {
3099 var.selector = var.base >> 4;
3100 var.base = var.base & 0xffff0;
3101 var.limit = 0xffff;
3102 var.g = 0;
3103 var.db = 0;
3104 var.present = 1;
3105 var.s = 1;
3106 var.l = 0;
3107 var.unusable = 0;
3108 var.type = 0x3;
3109 var.avl = 0;
3110 if (save->base & 0xf)
3111 printk_once(KERN_WARNING "kvm: segment base is not "
3112 "paragraph aligned when entering "
3113 "protected mode (seg=%d)", seg);
3114 }
6aa8b732 3115
d99e4152
GN		 3116 vmcs_write16(sf->selector, var.selector);
3117 vmcs_write32(sf->base, var.base);
3118 vmcs_write32(sf->limit, var.limit);
3119 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3120}
3121
3122static void enter_rmode(struct kvm_vcpu *vcpu)
3123{
3124 unsigned long flags;
a89a8fb9 3125 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3126
f5f7b2fe
AK		 3127 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3128 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3129 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3130 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3131 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3132 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3133 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3134
7ffd92c5 3135 vmx->rmode.vm86_active = 1;
6aa8b732 3136
776e58ea
GN		 3137 /*
3138 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3139 * vcpu. Warn the user that an update is overdue.
776e58ea 3140 */
4918c6ca 3141 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3142 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3143 "called before entering vcpu\n");
776e58ea 3144
2fb92db1
AK		 3145 vmx_segment_cache_clear(vmx);
3146
4918c6ca 3147 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3148 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3149 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3150
3151 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3152 vmx->rmode.save_rflags = flags;
6aa8b732 3153
053de044 3154 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3155
3156 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3157 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3158 update_exception_bitmap(vcpu);
3159
d99e4152
GN		 3160 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3161 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3162 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3163 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3164 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3165 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3166
8668a3c4 3167 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3168}
3169
401d10de
AS		 3170static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3171{
3172 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3173 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3174
3175 if (!msr)
3176 return;
401d10de 3177
44ea2b17
AK		 3178 /*
3179 * Force kernel_gs_base reloading before EFER changes, as control
3180 * of this msr depends on is_long_mode().
3181 */
3182 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3183 vcpu->arch.efer = efer;
401d10de
AS		 3184 if (efer & EFER_LMA) {
3185 vmcs_write32(VM_ENTRY_CONTROLS,
3186 vmcs_read32(VM_ENTRY_CONTROLS) |
3187 VM_ENTRY_IA32E_MODE);
3188 msr->data = efer;
3189 } else {
3190 vmcs_write32(VM_ENTRY_CONTROLS,
3191 vmcs_read32(VM_ENTRY_CONTROLS) &
3192 ~VM_ENTRY_IA32E_MODE);
3193
3194 msr->data = efer & ~EFER_LME;
3195 }
3196 setup_msrs(vmx);
3197}
3198
05b3e0c2 3199#ifdef CONFIG_X86_64
6aa8b732
AK		 3200
3201static void enter_lmode(struct kvm_vcpu *vcpu)
3202{
3203 u32 guest_tr_ar;
3204
2fb92db1
AK		 3205 vmx_segment_cache_clear(to_vmx(vcpu));
3206
6aa8b732
AK		 3207 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3208 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3209 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3210 __func__);
6aa8b732
AK		 3211 vmcs_write32(GUEST_TR_AR_BYTES,
3212 (guest_tr_ar & ~AR_TYPE_MASK)
3213 | AR_TYPE_BUSY_64_TSS);
3214 }
da38f438 3215 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3216}
3217
3218static void exit_lmode(struct kvm_vcpu *vcpu)
3219{
6aa8b732
AK		 3220 vmcs_write32(VM_ENTRY_CONTROLS,
3221 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3222 & ~VM_ENTRY_IA32E_MODE);
da38f438 3223 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3224}
3225
3226#endif
3227
2384d2b3
SY		 3228static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3229{
b9d762fa 3230 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3231 if (enable_ept) {
3232 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3233 return;
4e1096d2 3234 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3235 }
2384d2b3
SY		 3236}
3237
e8467fda
AK		 3238static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3239{
3240 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3241
3242 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3243 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3244}
3245
aff48baa
AK		 3246static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3247{
3248 if (enable_ept && is_paging(vcpu))
3249 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3250 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3251}
3252
25c4c276 3253static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3254{
fc78f519
AK		 3255 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3256
3257 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3258 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3259}
3260
1439442c
SY		 3261static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3262{
d0d538b9
GN		 3263 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3264
6de4f3ad
AK		 3265 if (!test_bit(VCPU_EXREG_PDPTR,
3266 (unsigned long *)&vcpu->arch.regs_dirty))
3267 return;
3268
1439442c 3269 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3270 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3271 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3272 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3273 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3274 }
3275}
3276
8f5d549f
AK		 3277static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3278{
d0d538b9
GN		 3279 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3280
8f5d549f 3281 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3282 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3283 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3284 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3285 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3286 }
6de4f3ad
AK		 3287
3288 __set_bit(VCPU_EXREG_PDPTR,
3289 (unsigned long *)&vcpu->arch.regs_avail);
3290 __set_bit(VCPU_EXREG_PDPTR,
3291 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3292}
3293
5e1746d6 3294static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3295
3296static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3297 unsigned long cr0,
3298 struct kvm_vcpu *vcpu)
3299{
5233dd51
MT		 3300 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3301 vmx_decache_cr3(vcpu);
1439442c
SY		 3302 if (!(cr0 & X86_CR0_PG)) {
3303 /* From paging/starting to nonpaging */
3304 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3305 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3306 (CPU_BASED_CR3_LOAD_EXITING |
3307 CPU_BASED_CR3_STORE_EXITING));
3308 vcpu->arch.cr0 = cr0;
fc78f519 3309 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3310 } else if (!is_paging(vcpu)) {
3311 /* From nonpaging to paging */
3312 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3313 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3314 ~(CPU_BASED_CR3_LOAD_EXITING |
3315 CPU_BASED_CR3_STORE_EXITING));
3316 vcpu->arch.cr0 = cr0;
fc78f519 3317 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3318 }
95eb84a7
SY		 3319
3320 if (!(cr0 & X86_CR0_WP))
3321 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3322}
3323
6aa8b732
AK		 3324static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3325{
7ffd92c5 3326 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3327 unsigned long hw_cr0;
3328
5037878e 3329 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3330 if (enable_unrestricted_guest)
5037878e 3331 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3332 else {
5037878e 3333 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3334
218e763f
GN		 3335 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3336 enter_pmode(vcpu);
6aa8b732 3337
218e763f
GN		 3338 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3339 enter_rmode(vcpu);
3340 }
6aa8b732 3341
05b3e0c2 3342#ifdef CONFIG_X86_64
f6801dff 3343 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3344 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3345 enter_lmode(vcpu);
707d92fa 3346 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3347 exit_lmode(vcpu);
3348 }
3349#endif
3350
089d034e 3351 if (enable_ept)
1439442c
SY		 3352 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3353
02daab21 3354 if (!vcpu->fpu_active)
81231c69 3355 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3356
6aa8b732 3357 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3358 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3359 vcpu->arch.cr0 = cr0;
14168786
GN		 3360
3361 /* depends on vcpu->arch.cr0 to be set to a new value */
3362 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3363}
3364
1439442c
SY		 3365static u64 construct_eptp(unsigned long root_hpa)
3366{
3367 u64 eptp;
3368
3369 /* TODO write the value reading from MSR */
3370 eptp = VMX_EPT_DEFAULT_MT |
3371 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3372 if (enable_ept_ad_bits)
3373 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3374 eptp |= (root_hpa & PAGE_MASK);
3375
3376 return eptp;
3377}
3378
6aa8b732
AK		 3379static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3380{
1439442c
SY		 3381 unsigned long guest_cr3;
3382 u64 eptp;
3383
3384 guest_cr3 = cr3;
089d034e 3385 if (enable_ept) {
1439442c
SY		 3386 eptp = construct_eptp(cr3);
3387 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3388 if (is_paging(vcpu) || is_guest_mode(vcpu))
3389 guest_cr3 = kvm_read_cr3(vcpu);
3390 else
3391 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3392 ept_load_pdptrs(vcpu);
1439442c
SY		 3393 }
3394
2384d2b3 3395 vmx_flush_tlb(vcpu);
1439442c 3396 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3397}
3398
5e1746d6 3399static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3400{
7ffd92c5 3401 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3402 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3403
5e1746d6
NHE		 3404 if (cr4 & X86_CR4_VMXE) {
3405 /*
3406 * To use VMXON (and later other VMX instructions), a guest
3407 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3408 * So basically the check on whether to allow nested VMX
3409 * is here.
3410 */
3411 if (!nested_vmx_allowed(vcpu))
3412 return 1;
1a0d74e6
JK		 3413 }
3414 if (to_vmx(vcpu)->nested.vmxon &&
3415 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3416 return 1;
3417
ad312c7c 3418 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3419 if (enable_ept) {
3420 if (!is_paging(vcpu)) {
3421 hw_cr4 &= ~X86_CR4_PAE;
3422 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3423 /*
3424 * SMEP is disabled if CPU is in non-paging mode in
3425 * hardware. However KVM always uses paging mode to
3426 * emulate guest non-paging mode with TDP.
3427 * To emulate this behavior, SMEP needs to be manually
3428 * disabled when guest switches to non-paging mode.
3429 */
3430 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3431 } else if (!(cr4 & X86_CR4_PAE)) {
3432 hw_cr4 &= ~X86_CR4_PAE;
3433 }
3434 }
1439442c
SY		 3435
3436 vmcs_writel(CR4_READ_SHADOW, cr4);
3437 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3438 return 0;
6aa8b732
AK		 3439}
3440
6aa8b732
AK		 3441static void vmx_get_segment(struct kvm_vcpu *vcpu,
3442 struct kvm_segment *var, int seg)
3443{
a9179499 3444 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3445 u32 ar;
3446
c6ad1153 3447 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3448 *var = vmx->rmode.segs[seg];
a9179499 3449 if (seg == VCPU_SREG_TR
2fb92db1 3450 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3451 return;
1390a28b
AK		 3452 var->base = vmx_read_guest_seg_base(vmx, seg);
3453 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3454 return;
a9179499 3455 }
2fb92db1
AK		 3456 var->base = vmx_read_guest_seg_base(vmx, seg);
3457 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3458 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3459 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3460 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3461 var->type = ar & 15;
3462 var->s = (ar >> 4) & 1;
3463 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3464 /*
3465 * Some userspaces do not preserve unusable property. Since usable
3466 * segment has to be present according to VMX spec we can use present
3467 * property to amend userspace bug by making unusable segment always
3468 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3469 * segment as unusable.
3470 */
3471 var->present = !var->unusable;
6aa8b732
AK		 3472 var->avl = (ar >> 12) & 1;
3473 var->l = (ar >> 13) & 1;
3474 var->db = (ar >> 14) & 1;
3475 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3476}
3477
a9179499
AK		 3478static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3479{
a9179499
AK		 3480 struct kvm_segment s;
3481
3482 if (to_vmx(vcpu)->rmode.vm86_active) {
3483 vmx_get_segment(vcpu, &s, seg);
3484 return s.base;
3485 }
2fb92db1 3486 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3487}
3488
b09408d0 3489static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3490{
b09408d0
MT		 3491 struct vcpu_vmx *vmx = to_vmx(vcpu);
3492
3eeb3288 3493 if (!is_protmode(vcpu))
2e4d2653
IE		 3494 return 0;
3495
f4c63e5d
AK		 3496 if (!is_long_mode(vcpu)
3497 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3498 return 3;
3499
69c73028
AK		 3500 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3501 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3502 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3503 }
d881e6f6
AK		 3504
3505 return vmx->cpl;
69c73028
AK		 3506}
3507
3508
653e3108 3509static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3510{
6aa8b732
AK		 3511 u32 ar;
3512
f0495f9b 3513 if (var->unusable || !var->present)
6aa8b732
AK		 3514 ar = 1 << 16;
3515 else {
3516 ar = var->type & 15;
3517 ar |= (var->s & 1) << 4;
3518 ar |= (var->dpl & 3) << 5;
3519 ar |= (var->present & 1) << 7;
3520 ar |= (var->avl & 1) << 12;
3521 ar |= (var->l & 1) << 13;
3522 ar |= (var->db & 1) << 14;
3523 ar |= (var->g & 1) << 15;
3524 }
653e3108
AK		 3525
3526 return ar;
3527}
3528
3529static void vmx_set_segment(struct kvm_vcpu *vcpu,
3530 struct kvm_segment *var, int seg)
3531{
7ffd92c5 3532 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3533 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3534
2fb92db1 3535 vmx_segment_cache_clear(vmx);
2f143240
GN		 3536 if (seg == VCPU_SREG_CS)
3537 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3538
1ecd50a9
GN		 3539 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3540 vmx->rmode.segs[seg] = *var;
3541 if (seg == VCPU_SREG_TR)
3542 vmcs_write16(sf->selector, var->selector);
3543 else if (var->s)
3544 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3545 goto out;
653e3108 3546 }
1ecd50a9 3547
653e3108
AK		 3548 vmcs_writel(sf->base, var->base);
3549 vmcs_write32(sf->limit, var->limit);
3550 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3551
3552 /*
3553 * Fix the "Accessed" bit in AR field of segment registers for older
3554 * qemu binaries.
3555 * IA32 arch specifies that at the time of processor reset the
3556 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3557 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3558 * state vmexit when "unrestricted guest" mode is turned on.
3559 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3560 * tree. Newer qemu binaries with that qemu fix would not need this
3561 * kvm hack.
3562 */
3563 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3564 var->type |= 0x1; /* Accessed */
3a624e29 3565
f924d66d 3566 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3567
3568out:
14168786 3569 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3570}
3571
6aa8b732
AK		 3572static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3573{
2fb92db1 3574 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3575
3576 *db = (ar >> 14) & 1;
3577 *l = (ar >> 13) & 1;
3578}
3579
89a27f4d 3580static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3581{
89a27f4d
GN		 3582 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3583 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3584}
3585
89a27f4d 3586static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3587{
89a27f4d
GN		 3588 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3589 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3590}
3591
89a27f4d 3592static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3593{
89a27f4d
GN		 3594 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3595 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3596}
3597
89a27f4d 3598static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3599{
89a27f4d
GN		 3600 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3601 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3602}
3603
648dfaa7
MG		 3604static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3605{
3606 struct kvm_segment var;
3607 u32 ar;
3608
3609 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3610 var.dpl = 0x3;
0647f4aa
GN		 3611 if (seg == VCPU_SREG_CS)
3612 var.type = 0x3;
648dfaa7
MG		 3613 ar = vmx_segment_access_rights(&var);
3614
3615 if (var.base != (var.selector << 4))
3616 return false;
89efbed0 3617 if (var.limit != 0xffff)
648dfaa7 3618 return false;
07f42f5f 3619 if (ar != 0xf3)
648dfaa7
MG		 3620 return false;
3621
3622 return true;
3623}
3624
3625static bool code_segment_valid(struct kvm_vcpu *vcpu)
3626{
3627 struct kvm_segment cs;
3628 unsigned int cs_rpl;
3629
3630 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3631 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3632
1872a3f4
AK		 3633 if (cs.unusable)
3634 return false;
648dfaa7
MG		 3635 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3636 return false;
3637 if (!cs.s)
3638 return false;
1872a3f4 3639 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3640 if (cs.dpl > cs_rpl)
3641 return false;
1872a3f4 3642 } else {
648dfaa7
MG		 3643 if (cs.dpl != cs_rpl)
3644 return false;
3645 }
3646 if (!cs.present)
3647 return false;
3648
3649 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3650 return true;
3651}
3652
3653static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3654{
3655 struct kvm_segment ss;
3656 unsigned int ss_rpl;
3657
3658 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3659 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3660
1872a3f4
AK		 3661 if (ss.unusable)
3662 return true;
3663 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3664 return false;
3665 if (!ss.s)
3666 return false;
3667 if (ss.dpl != ss_rpl) /* DPL != RPL */
3668 return false;
3669 if (!ss.present)
3670 return false;
3671
3672 return true;
3673}
3674
3675static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3676{
3677 struct kvm_segment var;
3678 unsigned int rpl;
3679
3680 vmx_get_segment(vcpu, &var, seg);
3681 rpl = var.selector & SELECTOR_RPL_MASK;
3682
1872a3f4
AK		 3683 if (var.unusable)
3684 return true;
648dfaa7
MG		 3685 if (!var.s)
3686 return false;
3687 if (!var.present)
3688 return false;
3689 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3690 if (var.dpl < rpl) /* DPL < RPL */
3691 return false;
3692 }
3693
3694 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3695 * rights flags
3696 */
3697 return true;
3698}
3699
3700static bool tr_valid(struct kvm_vcpu *vcpu)
3701{
3702 struct kvm_segment tr;
3703
3704 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3705
1872a3f4
AK		 3706 if (tr.unusable)
3707 return false;
648dfaa7
MG		 3708 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3709 return false;
1872a3f4 3710 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3711 return false;
3712 if (!tr.present)
3713 return false;
3714
3715 return true;
3716}
3717
3718static bool ldtr_valid(struct kvm_vcpu *vcpu)
3719{
3720 struct kvm_segment ldtr;
3721
3722 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3723
1872a3f4
AK		 3724 if (ldtr.unusable)
3725 return true;
648dfaa7
MG		 3726 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3727 return false;
3728 if (ldtr.type != 2)
3729 return false;
3730 if (!ldtr.present)
3731 return false;
3732
3733 return true;
3734}
3735
3736static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3737{
3738 struct kvm_segment cs, ss;
3739
3740 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3741 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3742
3743 return ((cs.selector & SELECTOR_RPL_MASK) ==
3744 (ss.selector & SELECTOR_RPL_MASK));
3745}
3746
3747/*
3748 * Check if guest state is valid. Returns true if valid, false if
3749 * not.
3750 * We assume that registers are always usable
3751 */
3752static bool guest_state_valid(struct kvm_vcpu *vcpu)
3753{
c5e97c80
GN		 3754 if (enable_unrestricted_guest)
3755 return true;
3756
648dfaa7 3757 /* real mode guest state checks */
f13882d8 3758 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3759 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3760 return false;
3761 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3762 return false;
3763 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3764 return false;
3765 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3766 return false;
3767 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3768 return false;
3769 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3770 return false;
3771 } else {
3772 /* protected mode guest state checks */
3773 if (!cs_ss_rpl_check(vcpu))
3774 return false;
3775 if (!code_segment_valid(vcpu))
3776 return false;
3777 if (!stack_segment_valid(vcpu))
3778 return false;
3779 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3780 return false;
3781 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3782 return false;
3783 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3784 return false;
3785 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3786 return false;
3787 if (!tr_valid(vcpu))
3788 return false;
3789 if (!ldtr_valid(vcpu))
3790 return false;
3791 }
3792 /* TODO:
3793 * - Add checks on RIP
3794 * - Add checks on RFLAGS
3795 */
3796
3797 return true;
3798}
3799
d77c26fc 3800static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3801{
40dcaa9f 3802 gfn_t fn;
195aefde 3803 u16 data = 0;
40dcaa9f 3804 int r, idx, ret = 0;
6aa8b732 3805
40dcaa9f 3806 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3807 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3808 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3809 if (r < 0)
10589a46 3810 goto out;
195aefde 3811 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3812 r = kvm_write_guest_page(kvm, fn++, &data,
3813 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3814 if (r < 0)
10589a46 3815 goto out;
195aefde
IE		 3816 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3817 if (r < 0)
10589a46 3818 goto out;
195aefde
IE		 3819 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3820 if (r < 0)
10589a46 3821 goto out;
195aefde 3822 data = ~0;
10589a46
MT		 3823 r = kvm_write_guest_page(kvm, fn, &data,
3824 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3825 sizeof(u8));
195aefde 3826 if (r < 0)
10589a46
MT		 3827 goto out;
3828
3829 ret = 1;
3830out:
40dcaa9f 3831 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3832 return ret;
6aa8b732
AK		 3833}
3834
b7ebfb05
SY		 3835static int init_rmode_identity_map(struct kvm *kvm)
3836{
40dcaa9f 3837 int i, idx, r, ret;
b7ebfb05
SY		 3838 pfn_t identity_map_pfn;
3839 u32 tmp;
3840
089d034e 3841 if (!enable_ept)
b7ebfb05
SY		 3842 return 1;
3843 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3844 printk(KERN_ERR "EPT: identity-mapping pagetable "
3845 "haven't been allocated!\n");
3846 return 0;
3847 }
3848 if (likely(kvm->arch.ept_identity_pagetable_done))
3849 return 1;
3850 ret = 0;
b927a3ce 3851 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3852 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3853 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3854 if (r < 0)
3855 goto out;
3856 /* Set up identity-mapping pagetable for EPT in real mode */
3857 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3858 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3859 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3860 r = kvm_write_guest_page(kvm, identity_map_pfn,
3861 &tmp, i * sizeof(tmp), sizeof(tmp));
3862 if (r < 0)
3863 goto out;
3864 }
3865 kvm->arch.ept_identity_pagetable_done = true;
3866 ret = 1;
3867out:
40dcaa9f 3868 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3869 return ret;
3870}
3871
6aa8b732
AK		 3872static void seg_setup(int seg)
3873{
772e0318 3874 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3875 unsigned int ar;
6aa8b732
AK		 3876
3877 vmcs_write16(sf->selector, 0);
3878 vmcs_writel(sf->base, 0);
3879 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3880 ar = 0x93;
3881 if (seg == VCPU_SREG_CS)
3882 ar |= 0x08; /* code segment */
3a624e29
NK		 3883
3884 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3885}
3886
f78e0e2e
SY		 3887static int alloc_apic_access_page(struct kvm *kvm)
3888{
4484141a 3889 struct page *page;
f78e0e2e
SY		 3890 struct kvm_userspace_memory_region kvm_userspace_mem;
3891 int r = 0;
3892
79fac95e 3893 mutex_lock(&kvm->slots_lock);
bfc6d222 3894 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3895 goto out;
3896 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3897 kvm_userspace_mem.flags = 0;
3898 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3899 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3900 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3901 if (r)
3902 goto out;
72dc67a6 3903
4484141a
XG		 3904 page = gfn_to_page(kvm, 0xfee00);
3905 if (is_error_page(page)) {
3906 r = -EFAULT;
3907 goto out;
3908 }
3909
3910 kvm->arch.apic_access_page = page;
f78e0e2e 3911out:
79fac95e 3912 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3913 return r;
3914}
3915
b7ebfb05
SY		 3916static int alloc_identity_pagetable(struct kvm *kvm)
3917{
4484141a 3918 struct page *page;
b7ebfb05
SY		 3919 struct kvm_userspace_memory_region kvm_userspace_mem;
3920 int r = 0;
3921
79fac95e 3922 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3923 if (kvm->arch.ept_identity_pagetable)
3924 goto out;
3925 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3926 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3927 kvm_userspace_mem.guest_phys_addr =
3928 kvm->arch.ept_identity_map_addr;
b7ebfb05 3929 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3930 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3931 if (r)
3932 goto out;
3933
4484141a
XG		 3934 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3935 if (is_error_page(page)) {
3936 r = -EFAULT;
3937 goto out;
3938 }
3939
3940 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3941out:
79fac95e 3942 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3943 return r;
3944}
3945
2384d2b3
SY		 3946static void allocate_vpid(struct vcpu_vmx *vmx)
3947{
3948 int vpid;
3949
3950 vmx->vpid = 0;
919818ab 3951 if (!enable_vpid)
2384d2b3
SY		 3952 return;
3953 spin_lock(&vmx_vpid_lock);
3954 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3955 if (vpid < VMX_NR_VPIDS) {
3956 vmx->vpid = vpid;
3957 __set_bit(vpid, vmx_vpid_bitmap);
3958 }
3959 spin_unlock(&vmx_vpid_lock);
3960}
3961
cdbecfc3
LJ		 3962static void free_vpid(struct vcpu_vmx *vmx)
3963{
3964 if (!enable_vpid)
3965 return;
3966 spin_lock(&vmx_vpid_lock);
3967 if (vmx->vpid != 0)
3968 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3969 spin_unlock(&vmx_vpid_lock);
3970}
3971
8d14695f
YZ		 3972#define MSR_TYPE_R 1
3973#define MSR_TYPE_W 2
3974static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3975 u32 msr, int type)
25c5f225 3976{
3e7c73e9 3977 int f = sizeof(unsigned long);
25c5f225
SY		 3978
3979 if (!cpu_has_vmx_msr_bitmap())
3980 return;
3981
3982 /*
3983 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3984 * have the write-low and read-high bitmap offsets the wrong way round.
3985 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3986 */
25c5f225 3987 if (msr <= 0x1fff) {
8d14695f
YZ		 3988 if (type & MSR_TYPE_R)
3989 /* read-low */
3990 __clear_bit(msr, msr_bitmap + 0x000 / f);
3991
3992 if (type & MSR_TYPE_W)
3993 /* write-low */
3994 __clear_bit(msr, msr_bitmap + 0x800 / f);
3995
25c5f225
SY		 3996 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3997 msr &= 0x1fff;
8d14695f
YZ		 3998 if (type & MSR_TYPE_R)
3999 /* read-high */
4000 __clear_bit(msr, msr_bitmap + 0x400 / f);
4001
4002 if (type & MSR_TYPE_W)
4003 /* write-high */
4004 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4005
4006 }
4007}
4008
4009static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4010 u32 msr, int type)
4011{
4012 int f = sizeof(unsigned long);
4013
4014 if (!cpu_has_vmx_msr_bitmap())
4015 return;
4016
4017 /*
4018 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4019 * have the write-low and read-high bitmap offsets the wrong way round.
4020 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4021 */
4022 if (msr <= 0x1fff) {
4023 if (type & MSR_TYPE_R)
4024 /* read-low */
4025 __set_bit(msr, msr_bitmap + 0x000 / f);
4026
4027 if (type & MSR_TYPE_W)
4028 /* write-low */
4029 __set_bit(msr, msr_bitmap + 0x800 / f);
4030
4031 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4032 msr &= 0x1fff;
4033 if (type & MSR_TYPE_R)
4034 /* read-high */
4035 __set_bit(msr, msr_bitmap + 0x400 / f);
4036
4037 if (type & MSR_TYPE_W)
4038 /* write-high */
4039 __set_bit(msr, msr_bitmap + 0xc00 / f);
4040
25c5f225 4041 }
25c5f225
SY		 4042}
4043
5897297b
AK		 4044static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4045{
4046 if (!longmode_only)
8d14695f
YZ		 4047 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4048 msr, MSR_TYPE_R | MSR_TYPE_W);
4049 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4050 msr, MSR_TYPE_R | MSR_TYPE_W);
4051}
4052
4053static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4054{
4055 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4056 msr, MSR_TYPE_R);
4057 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4058 msr, MSR_TYPE_R);
4059}
4060
4061static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4062{
4063 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4064 msr, MSR_TYPE_R);
4065 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4066 msr, MSR_TYPE_R);
4067}
4068
4069static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4070{
4071 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4072 msr, MSR_TYPE_W);
4073 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4074 msr, MSR_TYPE_W);
5897297b
AK		 4075}
4076
01e439be
YZ		 4077static int vmx_vm_has_apicv(struct kvm *kvm)
4078{
4079 return enable_apicv && irqchip_in_kernel(kvm);
4080}
4081
a20ed54d
YZ		 4082/*
4083 * Send interrupt to vcpu via posted interrupt way.
4084 * 1. If target vcpu is running(non-root mode), send posted interrupt
4085 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4086 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4087 * interrupt from PIR in next vmentry.
4088 */
4089static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4090{
4091 struct vcpu_vmx *vmx = to_vmx(vcpu);
4092 int r;
4093
4094 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4095 return;
4096
4097 r = pi_test_and_set_on(&vmx->pi_desc);
4098 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4099#ifdef CONFIG_SMP
a20ed54d
YZ		 4100 if (!r && (vcpu->mode == IN_GUEST_MODE))
4101 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4102 POSTED_INTR_VECTOR);
4103 else
6ffbbbba 4104#endif
a20ed54d
YZ		 4105 kvm_vcpu_kick(vcpu);
4106}
4107
4108static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4109{
4110 struct vcpu_vmx *vmx = to_vmx(vcpu);
4111
4112 if (!pi_test_and_clear_on(&vmx->pi_desc))
4113 return;
4114
4115 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4116}
4117
4118static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4119{
4120 return;
4121}
4122
a3a8ff8e
NHE		 4123/*
4124 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4125 * will not change in the lifetime of the guest.
4126 * Note that host-state that does change is set elsewhere. E.g., host-state
4127 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4128 */
a547c6db 4129static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4130{
4131 u32 low32, high32;
4132 unsigned long tmpl;
4133 struct desc_ptr dt;
4134
b1a74bf8 4135 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4136 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4137 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4138
4139 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4140#ifdef CONFIG_X86_64
4141 /*
4142 * Load null selectors, so we can avoid reloading them in
4143 * __vmx_load_host_state(), in case userspace uses the null selectors
4144 * too (the expected case).
4145 */
4146 vmcs_write16(HOST_DS_SELECTOR, 0);
4147 vmcs_write16(HOST_ES_SELECTOR, 0);
4148#else
a3a8ff8e
NHE		 4149 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4150 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4151#endif
a3a8ff8e
NHE		 4152 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4153 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4154
4155 native_store_idt(&dt);
4156 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4157 vmx->host_idt_base = dt.address;
a3a8ff8e 4158
83287ea4 4159 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4160
4161 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4162 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4163 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4164 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4165
4166 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4167 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4168 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4169 }
4170}
4171
bf8179a0
NHE		 4172static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4173{
4174 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4175 if (enable_ept)
4176 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4177 if (is_guest_mode(&vmx->vcpu))
4178 vmx->vcpu.arch.cr4_guest_owned_bits &=
4179 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4180 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4181}
4182
01e439be
YZ		 4183static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4184{
4185 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4186
4187 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4188 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4189 return pin_based_exec_ctrl;
4190}
4191
bf8179a0
NHE		 4192static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4193{
4194 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4195 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4196 exec_control &= ~CPU_BASED_TPR_SHADOW;
4197#ifdef CONFIG_X86_64
4198 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4199 CPU_BASED_CR8_LOAD_EXITING;
4200#endif
4201 }
4202 if (!enable_ept)
4203 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4204 CPU_BASED_CR3_LOAD_EXITING |
4205 CPU_BASED_INVLPG_EXITING;
4206 return exec_control;
4207}
4208
4209static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4210{
4211 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4212 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4213 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4214 if (vmx->vpid == 0)
4215 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4216 if (!enable_ept) {
4217 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4218 enable_unrestricted_guest = 0;
ad756a16
MJ		 4219 /* Enable INVPCID for non-ept guests may cause performance regression. */
4220 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4221 }
4222 if (!enable_unrestricted_guest)
4223 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4224 if (!ple_gap)
4225 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4226 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4227 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4228 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4229 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4230 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4231 (handle_vmptrld).
4232 We can NOT enable shadow_vmcs here because we don't have yet
4233 a current VMCS12
4234 */
4235 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4236 return exec_control;
4237}
4238
ce88decf
XG		 4239static void ept_set_mmio_spte_mask(void)
4240{
4241 /*
4242 * EPT Misconfigurations can be generated if the value of bits 2:0
4243 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4244 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4245 * spte.
4246 */
885032b9 4247 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4248}
4249
6aa8b732
AK		 4250/*
4251 * Sets up the vmcs for emulated real mode.
4252 */
8b9cf98c 4253static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4254{
2e4ce7f5 4255#ifdef CONFIG_X86_64
6aa8b732 4256 unsigned long a;
2e4ce7f5 4257#endif
6aa8b732 4258 int i;
6aa8b732 4259
6aa8b732 4260 /* I/O */
3e7c73e9
AK		 4261 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4262 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4263
4607c2d7
AG		 4264 if (enable_shadow_vmcs) {
4265 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4266 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4267 }
25c5f225 4268 if (cpu_has_vmx_msr_bitmap())
5897297b 4269 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4270
6aa8b732
AK		 4271 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4272
6aa8b732 4273 /* Control */
01e439be 4274 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4275
bf8179a0 4276 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4277
83ff3b9d 4278 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4279 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4280 vmx_secondary_exec_control(vmx));
83ff3b9d 4281 }
f78e0e2e 4282
01e439be 4283 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4284 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4285 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4286 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4287 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4288
4289 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4290
4291 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4292 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4293 }
4294
4b8d54f9
ZE		 4295 if (ple_gap) {
4296 vmcs_write32(PLE_GAP, ple_gap);
4297 vmcs_write32(PLE_WINDOW, ple_window);
4298 }
4299
c3707958
XG		 4300 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4301 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4302 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4303
9581d442
AK		 4304 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4305 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4306 vmx_set_constant_host_state(vmx);
05b3e0c2 4307#ifdef CONFIG_X86_64
6aa8b732
AK		 4308 rdmsrl(MSR_FS_BASE, a);
4309 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4310 rdmsrl(MSR_GS_BASE, a);
4311 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4312#else
4313 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4314 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4315#endif
4316
2cc51560
ED		 4317 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4318 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4319 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4321 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4322
468d472f 4323 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4324 u32 msr_low, msr_high;
4325 u64 host_pat;
468d472f
SY		 4326 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4327 host_pat = msr_low | ((u64) msr_high << 32);
4328 /* Write the default value follow host pat */
4329 vmcs_write64(GUEST_IA32_PAT, host_pat);
4330 /* Keep arch.pat sync with GUEST_IA32_PAT */
4331 vmx->vcpu.arch.pat = host_pat;
4332 }
4333
6aa8b732
AK		 4334 for (i = 0; i < NR_VMX_MSR; ++i) {
4335 u32 index = vmx_msr_index[i];
4336 u32 data_low, data_high;
a2fa3e9f 4337 int j = vmx->nmsrs;
6aa8b732
AK		 4338
4339 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4340 continue;
432bd6cb
AK		 4341 if (wrmsr_safe(index, data_low, data_high) < 0)
4342 continue;
26bb0981
AK		 4343 vmx->guest_msrs[j].index = i;
4344 vmx->guest_msrs[j].data = 0;
d5696725 4345 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4346 ++vmx->nmsrs;
6aa8b732 4347 }
6aa8b732 4348
1c3d14fe 4349 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4350
4351 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4352 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4353
e00c8cf2 4354 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4355 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4356
4357 return 0;
4358}
4359
57f252f2 4360static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4361{
4362 struct vcpu_vmx *vmx = to_vmx(vcpu);
4363 u64 msr;
e00c8cf2 4364
7ffd92c5 4365 vmx->rmode.vm86_active = 0;
e00c8cf2 4366
3b86cd99
JK		 4367 vmx->soft_vnmi_blocked = 0;
4368
ad312c7c 4369 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4370 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4371 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4372 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4373 msr |= MSR_IA32_APICBASE_BSP;
4374 kvm_set_apic_base(&vmx->vcpu, msr);
4375
2fb92db1
AK		 4376 vmx_segment_cache_clear(vmx);
4377
5706be0d 4378 seg_setup(VCPU_SREG_CS);
66450a21 4379 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4380 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4381
4382 seg_setup(VCPU_SREG_DS);
4383 seg_setup(VCPU_SREG_ES);
4384 seg_setup(VCPU_SREG_FS);
4385 seg_setup(VCPU_SREG_GS);
4386 seg_setup(VCPU_SREG_SS);
4387
4388 vmcs_write16(GUEST_TR_SELECTOR, 0);
4389 vmcs_writel(GUEST_TR_BASE, 0);
4390 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4391 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4392
4393 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4394 vmcs_writel(GUEST_LDTR_BASE, 0);
4395 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4396 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4397
4398 vmcs_write32(GUEST_SYSENTER_CS, 0);
4399 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4400 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4401
4402 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4403 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4404
e00c8cf2
AK		 4405 vmcs_writel(GUEST_GDTR_BASE, 0);
4406 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4407
4408 vmcs_writel(GUEST_IDTR_BASE, 0);
4409 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4410
443381a8 4411 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4412 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4413 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4414
e00c8cf2
AK		 4415 /* Special registers */
4416 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4417
4418 setup_msrs(vmx);
4419
6aa8b732
AK		 4420 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4421
f78e0e2e
SY		 4422 if (cpu_has_vmx_tpr_shadow()) {
4423 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4424 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4425 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4426 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4427 vmcs_write32(TPR_THRESHOLD, 0);
4428 }
4429
4430 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4431 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4432 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4433
01e439be
YZ		 4434 if (vmx_vm_has_apicv(vcpu->kvm))
4435 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4436
2384d2b3
SY		 4437 if (vmx->vpid != 0)
4438 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4439
fa40052c 4440 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4441 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4442 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4443 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4444 vmx_fpu_activate(&vmx->vcpu);
4445 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4446
b9d762fa 4447 vpid_sync_context(vmx);
6aa8b732
AK		 4448}
4449
b6f1250e
NHE		 4450/*
4451 * In nested virtualization, check if L1 asked to exit on external interrupts.
4452 * For most existing hypervisors, this will always return true.
4453 */
4454static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4455{
4456 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4457 PIN_BASED_EXT_INTR_MASK;
4458}
4459
ea8ceb83
JK		 4460static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4461{
4462 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4463 PIN_BASED_NMI_EXITING;
4464}
4465
730dca42 4466static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4467{
4468 u32 cpu_based_vm_exec_control;
730dca42
JK		 4469
4470 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4471 /*
4472 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4473 * inject to L1 now because L2 must run. The caller will have
4474 * to make L2 exit right after entry, so we can inject to L1
4475 * more promptly.
b6f1250e 4476 */
730dca42 4477 return -EBUSY;
3b86cd99
JK		 4478
4479 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4480 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4481 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4482 return 0;
3b86cd99
JK		 4483}
4484
03b28f81 4485static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4486{
4487 u32 cpu_based_vm_exec_control;
4488
03b28f81
JK		 4489 if (!cpu_has_virtual_nmis())
4490 return enable_irq_window(vcpu);
4491
4492 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4493 return enable_irq_window(vcpu);
3b86cd99
JK		 4494
4495 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4496 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4497 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4498 return 0;
3b86cd99
JK		 4499}
4500
66fd3f7f 4501static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4502{
9c8cba37 4503 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4504 uint32_t intr;
4505 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4506
229456fc 4507 trace_kvm_inj_virq(irq);
2714d1d3 4508
fa89a817 4509 ++vcpu->stat.irq_injections;
7ffd92c5 4510 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4511 int inc_eip = 0;
4512 if (vcpu->arch.interrupt.soft)
4513 inc_eip = vcpu->arch.event_exit_inst_len;
4514 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4515 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4516 return;
4517 }
66fd3f7f
GN		 4518 intr = irq | INTR_INFO_VALID_MASK;
4519 if (vcpu->arch.interrupt.soft) {
4520 intr |= INTR_TYPE_SOFT_INTR;
4521 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4522 vmx->vcpu.arch.event_exit_inst_len);
4523 } else
4524 intr |= INTR_TYPE_EXT_INTR;
4525 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4526}
4527
f08864b4
SY		 4528static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4529{
66a5a347
JK		 4530 struct vcpu_vmx *vmx = to_vmx(vcpu);
4531
0b6ac343
NHE		 4532 if (is_guest_mode(vcpu))
4533 return;
4534
3b86cd99
JK		 4535 if (!cpu_has_virtual_nmis()) {
4536 /*
4537 * Tracking the NMI-blocked state in software is built upon
4538 * finding the next open IRQ window. This, in turn, depends on
4539 * well-behaving guests: They have to keep IRQs disabled at
4540 * least as long as the NMI handler runs. Otherwise we may
4541 * cause NMI nesting, maybe breaking the guest. But as this is
4542 * highly unlikely, we can live with the residual risk.
4543 */
4544 vmx->soft_vnmi_blocked = 1;
4545 vmx->vnmi_blocked_time = 0;
4546 }
4547
487b391d 4548 ++vcpu->stat.nmi_injections;
9d58b931 4549 vmx->nmi_known_unmasked = false;
7ffd92c5 4550 if (vmx->rmode.vm86_active) {
71f9833b 4551 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4552 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4553 return;
4554 }
f08864b4
SY		 4555 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4556 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4557}
4558
3cfc3092
JK		 4559static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4560{
4561 if (!cpu_has_virtual_nmis())
4562 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4563 if (to_vmx(vcpu)->nmi_known_unmasked)
4564 return false;
c332c83a 4565 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4566}
4567
4568static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4569{
4570 struct vcpu_vmx *vmx = to_vmx(vcpu);
4571
4572 if (!cpu_has_virtual_nmis()) {
4573 if (vmx->soft_vnmi_blocked != masked) {
4574 vmx->soft_vnmi_blocked = masked;
4575 vmx->vnmi_blocked_time = 0;
4576 }
4577 } else {
9d58b931 4578 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4579 if (masked)
4580 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4581 GUEST_INTR_STATE_NMI);
4582 else
4583 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4584 GUEST_INTR_STATE_NMI);
4585 }
4586}
4587
2505dc9f
JK		 4588static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4589{
ea8ceb83
JK		 4590 if (is_guest_mode(vcpu)) {
4591 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4592
4593 if (to_vmx(vcpu)->nested.nested_run_pending)
4594 return 0;
4595 if (nested_exit_on_nmi(vcpu)) {
4596 nested_vmx_vmexit(vcpu);
4597 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4598 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4599 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4600 /*
4601 * The NMI-triggered VM exit counts as injection:
4602 * clear this one and block further NMIs.
4603 */
4604 vcpu->arch.nmi_pending = 0;
4605 vmx_set_nmi_mask(vcpu, true);
4606 return 0;
4607 }
4608 }
4609
2505dc9f
JK		 4610 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4611 return 0;
4612
4613 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4614 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4615 | GUEST_INTR_STATE_NMI));
4616}
4617
78646121
GN		 4618static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4619{
e8457c67 4620 if (is_guest_mode(vcpu)) {
51cfe38e 4621 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4622
4623 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4624 return 0;
e8457c67
JK		 4625 if (nested_exit_on_intr(vcpu)) {
4626 nested_vmx_vmexit(vcpu);
4627 vmcs12->vm_exit_reason =
4628 EXIT_REASON_EXTERNAL_INTERRUPT;
4629 vmcs12->vm_exit_intr_info = 0;
4630 /*
4631 * fall through to normal code, but now in L1, not L2
4632 */
4633 }
b6f1250e
NHE		 4634 }
4635
c4282df9
GN		 4636 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4637 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4638 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4639}
4640
cbc94022
IE		 4641static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4642{
4643 int ret;
4644 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4645 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4646 .guest_phys_addr = addr,
4647 .memory_size = PAGE_SIZE * 3,
4648 .flags = 0,
4649 };
4650
47ae31e2 4651 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4652 if (ret)
4653 return ret;
bfc6d222 4654 kvm->arch.tss_addr = addr;
93ea5388
GN		 4655 if (!init_rmode_tss(kvm))
4656 return -ENOMEM;
4657
cbc94022
IE		 4658 return 0;
4659}
4660
0ca1b4f4 4661static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4662{
77ab6db0 4663 switch (vec) {
77ab6db0 4664 case BP_VECTOR:
c573cd22
JK		 4665 /*
4666 * Update instruction length as we may reinject the exception
4667 * from user space while in guest debugging mode.
4668 */
4669 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4670 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4671 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4672 return false;
4673 /* fall through */
4674 case DB_VECTOR:
4675 if (vcpu->guest_debug &
4676 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4677 return false;
d0bfb940
JK		 4678 /* fall through */
4679 case DE_VECTOR:
77ab6db0
JK		 4680 case OF_VECTOR:
4681 case BR_VECTOR:
4682 case UD_VECTOR:
4683 case DF_VECTOR:
4684 case SS_VECTOR:
4685 case GP_VECTOR:
4686 case MF_VECTOR:
0ca1b4f4
GN		 4687 return true;
4688 break;
77ab6db0 4689 }
0ca1b4f4
GN		 4690 return false;
4691}
4692
4693static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4694 int vec, u32 err_code)
4695{
4696 /*
4697 * Instruction with address size override prefix opcode 0x67
4698 * Cause the #SS fault with 0 error code in VM86 mode.
4699 */
4700 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4701 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4702 if (vcpu->arch.halt_request) {
4703 vcpu->arch.halt_request = 0;
4704 return kvm_emulate_halt(vcpu);
4705 }
4706 return 1;
4707 }
4708 return 0;
4709 }
4710
4711 /*
4712 * Forward all other exceptions that are valid in real mode.
4713 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4714 * the required debugging infrastructure rework.
4715 */
4716 kvm_queue_exception(vcpu, vec);
4717 return 1;
6aa8b732
AK		 4718}
4719
a0861c02
AK		 4720/*
4721 * Trigger machine check on the host. We assume all the MSRs are already set up
4722 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4723 * We pass a fake environment to the machine check handler because we want
4724 * the guest to be always treated like user space, no matter what context
4725 * it used internally.
4726 */
4727static void kvm_machine_check(void)
4728{
4729#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4730 struct pt_regs regs = {
4731 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4732 .flags = X86_EFLAGS_IF,
4733 };
4734
4735 do_machine_check(&regs, 0);
4736#endif
4737}
4738
851ba692 4739static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4740{
4741 /* already handled by vcpu_run */
4742 return 1;
4743}
4744
851ba692 4745static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4746{
1155f76a 4747 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4748 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4749 u32 intr_info, ex_no, error_code;
42dbaa5a 4750 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4751 u32 vect_info;
4752 enum emulation_result er;
4753
1155f76a 4754 vect_info = vmx->idt_vectoring_info;
88786475 4755 intr_info = vmx->exit_intr_info;
6aa8b732 4756
a0861c02 4757 if (is_machine_check(intr_info))
851ba692 4758 return handle_machine_check(vcpu);
a0861c02 4759
e4a41889 4760 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4761 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4762
4763 if (is_no_device(intr_info)) {
5fd86fcf 4764 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4765 return 1;
4766 }
4767
7aa81cc0 4768 if (is_invalid_opcode(intr_info)) {
51d8b661 4769 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4770 if (er != EMULATE_DONE)
7ee5d940 4771 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4772 return 1;
4773 }
4774
6aa8b732 4775 error_code = 0;
2e11384c 4776 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4777 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4778
4779 /*
4780 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4781 * MMIO, it is better to report an internal error.
4782 * See the comments in vmx_handle_exit.
4783 */
4784 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4785 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4786 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4787 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4788 vcpu->run->internal.ndata = 2;
4789 vcpu->run->internal.data[0] = vect_info;
4790 vcpu->run->internal.data[1] = intr_info;
4791 return 0;
4792 }
4793
6aa8b732 4794 if (is_page_fault(intr_info)) {
1439442c 4795 /* EPT won't cause page fault directly */
cf3ace79 4796 BUG_ON(enable_ept);
6aa8b732 4797 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4798 trace_kvm_page_fault(cr2, error_code);
4799
3298b75c 4800 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4801 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4802 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4803 }
4804
d0bfb940 4805 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4806
4807 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4808 return handle_rmode_exception(vcpu, ex_no, error_code);
4809
42dbaa5a
JK		 4810 switch (ex_no) {
4811 case DB_VECTOR:
4812 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4813 if (!(vcpu->guest_debug &
4814 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4815 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4816 kvm_queue_exception(vcpu, DB_VECTOR);
4817 return 1;
4818 }
4819 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4820 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4821 /* fall through */
4822 case BP_VECTOR:
c573cd22
JK		 4823 /*
4824 * Update instruction length as we may reinject #BP from
4825 * user space while in guest debugging mode. Reading it for
4826 * #DB as well causes no harm, it is not used in that case.
4827 */
4828 vmx->vcpu.arch.event_exit_inst_len =
4829 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4830 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4831 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4832 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4833 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4834 break;
4835 default:
d0bfb940
JK		 4836 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4837 kvm_run->ex.exception = ex_no;
4838 kvm_run->ex.error_code = error_code;
42dbaa5a 4839 break;
6aa8b732 4840 }
6aa8b732
AK		 4841 return 0;
4842}
4843
851ba692 4844static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4845{
1165f5fe 4846 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4847 return 1;
4848}
4849
851ba692 4850static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4851{
851ba692 4852 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4853 return 0;
4854}
6aa8b732 4855
851ba692 4856static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4857{
bfdaab09 4858 unsigned long exit_qualification;
34c33d16 4859 int size, in, string;
039576c0 4860 unsigned port;
6aa8b732 4861
bfdaab09 4862 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4863 string = (exit_qualification & 16) != 0;
cf8f70bf 4864 in = (exit_qualification & 8) != 0;
e70669ab 4865
cf8f70bf 4866 ++vcpu->stat.io_exits;
e70669ab 4867
cf8f70bf 4868 if (string || in)
51d8b661 4869 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4870
cf8f70bf
GN		 4871 port = exit_qualification >> 16;
4872 size = (exit_qualification & 7) + 1;
e93f36bc 4873 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4874
4875 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4876}
4877
102d8325
IM		 4878static void
4879vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4880{
4881 /*
4882 * Patch in the VMCALL instruction:
4883 */
4884 hypercall[0] = 0x0f;
4885 hypercall[1] = 0x01;
4886 hypercall[2] = 0xc1;
102d8325
IM		 4887}
4888
92fbc7b1
JK		 4889static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4890{
4891 unsigned long always_on = VMXON_CR0_ALWAYSON;
4892
4893 if (nested_vmx_secondary_ctls_high &
4894 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4895 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4896 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4897 return (val & always_on) == always_on;
4898}
4899
0fa06071 4900/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4901static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4902{
eeadf9e7 4903 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4904 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4905 unsigned long orig_val = val;
4906
eeadf9e7
NHE		 4907 /*
4908 * We get here when L2 changed cr0 in a way that did not change
4909 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4910 * but did change L0 shadowed bits. So we first calculate the
4911 * effective cr0 value that L1 would like to write into the
4912 * hardware. It consists of the L2-owned bits from the new
4913 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4914 */
1a0d74e6
JK		 4915 val = (val & ~vmcs12->cr0_guest_host_mask) |
4916 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4917
92fbc7b1 4918 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4919 return 1;
1a0d74e6
JK		 4920
4921 if (kvm_set_cr0(vcpu, val))
4922 return 1;
4923 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4924 return 0;
1a0d74e6
JK		 4925 } else {
4926 if (to_vmx(vcpu)->nested.vmxon &&
4927 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4928 return 1;
eeadf9e7 4929 return kvm_set_cr0(vcpu, val);
1a0d74e6 4930 }
eeadf9e7
NHE		 4931}
4932
4933static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4934{
4935 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4936 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4937 unsigned long orig_val = val;
4938
4939 /* analogously to handle_set_cr0 */
4940 val = (val & ~vmcs12->cr4_guest_host_mask) |
4941 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4942 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4943 return 1;
1a0d74e6 4944 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4945 return 0;
4946 } else
4947 return kvm_set_cr4(vcpu, val);
4948}
4949
4950/* called to set cr0 as approriate for clts instruction exit. */
4951static void handle_clts(struct kvm_vcpu *vcpu)
4952{
4953 if (is_guest_mode(vcpu)) {
4954 /*
4955 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4956 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4957 * just pretend it's off (also in arch.cr0 for fpu_activate).
4958 */
4959 vmcs_writel(CR0_READ_SHADOW,
4960 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4961 vcpu->arch.cr0 &= ~X86_CR0_TS;
4962 } else
4963 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4964}
4965
851ba692 4966static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4967{
229456fc 4968 unsigned long exit_qualification, val;
6aa8b732
AK		 4969 int cr;
4970 int reg;
49a9b07e 4971 int err;
6aa8b732 4972
bfdaab09 4973 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4974 cr = exit_qualification & 15;
4975 reg = (exit_qualification >> 8) & 15;
4976 switch ((exit_qualification >> 4) & 3) {
4977 case 0: /* mov to cr */
229456fc
MT		 4978 val = kvm_register_read(vcpu, reg);
4979 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4980 switch (cr) {
4981 case 0:
eeadf9e7 4982 err = handle_set_cr0(vcpu, val);
db8fcefa 4983 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4984 return 1;
4985 case 3:
2390218b 4986 err = kvm_set_cr3(vcpu, val);
db8fcefa 4987 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4988 return 1;
4989 case 4:
eeadf9e7 4990 err = handle_set_cr4(vcpu, val);
db8fcefa 4991 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4992 return 1;
0a5fff19
GN		 4993 case 8: {
4994 u8 cr8_prev = kvm_get_cr8(vcpu);
4995 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4996 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4997 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4998 if (irqchip_in_kernel(vcpu->kvm))
4999 return 1;
5000 if (cr8_prev <= cr8)
5001 return 1;
851ba692 5002 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5003 return 0;
5004 }
4b8073e4 5005 }
6aa8b732 5006 break;
25c4c276 5007 case 2: /* clts */
eeadf9e7 5008 handle_clts(vcpu);
4d4ec087 5009 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5010 skip_emulated_instruction(vcpu);
6b52d186 5011 vmx_fpu_activate(vcpu);
25c4c276 5012 return 1;
6aa8b732
AK		 5013 case 1: /*mov from cr*/
5014 switch (cr) {
5015 case 3:
9f8fe504
AK		 5016 val = kvm_read_cr3(vcpu);
5017 kvm_register_write(vcpu, reg, val);
5018 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5019 skip_emulated_instruction(vcpu);
5020 return 1;
5021 case 8:
229456fc
MT		 5022 val = kvm_get_cr8(vcpu);
5023 kvm_register_write(vcpu, reg, val);
5024 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5025 skip_emulated_instruction(vcpu);
5026 return 1;
5027 }
5028 break;
5029 case 3: /* lmsw */
a1f83a74 5030 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5031 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5032 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5033
5034 skip_emulated_instruction(vcpu);
5035 return 1;
5036 default:
5037 break;
5038 }
851ba692 5039 vcpu->run->exit_reason = 0;
a737f256 5040 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5041 (int)(exit_qualification >> 4) & 3, cr);
5042 return 0;
5043}
5044
851ba692 5045static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5046{
bfdaab09 5047 unsigned long exit_qualification;
6aa8b732
AK		 5048 int dr, reg;
5049
f2483415 5050 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5051 if (!kvm_require_cpl(vcpu, 0))
5052 return 1;
42dbaa5a
JK		 5053 dr = vmcs_readl(GUEST_DR7);
5054 if (dr & DR7_GD) {
5055 /*
5056 * As the vm-exit takes precedence over the debug trap, we
5057 * need to emulate the latter, either for the host or the
5058 * guest debugging itself.
5059 */
5060 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5061 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5062 vcpu->run->debug.arch.dr7 = dr;
5063 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5064 vmcs_readl(GUEST_CS_BASE) +
5065 vmcs_readl(GUEST_RIP);
851ba692
AK		 5066 vcpu->run->debug.arch.exception = DB_VECTOR;
5067 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5068 return 0;
5069 } else {
5070 vcpu->arch.dr7 &= ~DR7_GD;
5071 vcpu->arch.dr6 |= DR6_BD;
5072 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5073 kvm_queue_exception(vcpu, DB_VECTOR);
5074 return 1;
5075 }
5076 }
5077
bfdaab09 5078 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5079 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5080 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5081 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5082 unsigned long val;
5083 if (!kvm_get_dr(vcpu, dr, &val))
5084 kvm_register_write(vcpu, reg, val);
5085 } else
5086 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5087 skip_emulated_instruction(vcpu);
5088 return 1;
5089}
5090
020df079
GN		 5091static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5092{
5093 vmcs_writel(GUEST_DR7, val);
5094}
5095
851ba692 5096static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5097{
06465c5a
AK		 5098 kvm_emulate_cpuid(vcpu);
5099 return 1;
6aa8b732
AK		 5100}
5101
851ba692 5102static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5103{
ad312c7c 5104 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5105 u64 data;
5106
5107 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5108 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5109 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5110 return 1;
5111 }
5112
229456fc 5113 trace_kvm_msr_read(ecx, data);
2714d1d3 5114
6aa8b732 5115 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5116 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5117 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5118 skip_emulated_instruction(vcpu);
5119 return 1;
5120}
5121
851ba692 5122static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5123{
8fe8ab46 5124 struct msr_data msr;
ad312c7c
ZX		 5125 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5126 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5127 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5128
8fe8ab46
WA		 5129 msr.data = data;
5130 msr.index = ecx;
5131 msr.host_initiated = false;
5132 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5133 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5134 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5135 return 1;
5136 }
5137
59200273 5138 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5139 skip_emulated_instruction(vcpu);
5140 return 1;
5141}
5142
851ba692 5143static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5144{
3842d135 5145 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5146 return 1;
5147}
5148
851ba692 5149static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5150{
85f455f7
ED		 5151 u32 cpu_based_vm_exec_control;
5152
5153 /* clear pending irq */
5154 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5155 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5156 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5157
3842d135
AK		 5158 kvm_make_request(KVM_REQ_EVENT, vcpu);
5159
a26bf12a 5160 ++vcpu->stat.irq_window_exits;
2714d1d3 5161
c1150d8c
DL		 5162 /*
5163 * If the user space waits to inject interrupts, exit as soon as
5164 * possible
5165 */
8061823a 5166 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5167 vcpu->run->request_interrupt_window &&
8061823a 5168 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5169 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5170 return 0;
5171 }
6aa8b732
AK		 5172 return 1;
5173}
5174
851ba692 5175static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5176{
5177 skip_emulated_instruction(vcpu);
d3bef15f 5178 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5179}
5180
851ba692 5181static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5182{
510043da 5183 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5184 kvm_emulate_hypercall(vcpu);
5185 return 1;
c21415e8
IM		 5186}
5187
ec25d5e6
GN		 5188static int handle_invd(struct kvm_vcpu *vcpu)
5189{
51d8b661 5190 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5191}
5192
851ba692 5193static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5194{
f9c617f6 5195 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5196
5197 kvm_mmu_invlpg(vcpu, exit_qualification);
5198 skip_emulated_instruction(vcpu);
5199 return 1;
5200}
5201
fee84b07
AK		 5202static int handle_rdpmc(struct kvm_vcpu *vcpu)
5203{
5204 int err;
5205
5206 err = kvm_rdpmc(vcpu);
5207 kvm_complete_insn_gp(vcpu, err);
5208
5209 return 1;
5210}
5211
851ba692 5212static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5213{
5214 skip_emulated_instruction(vcpu);
f5f48ee1 5215 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5216 return 1;
5217}
5218
2acf923e
DC		 5219static int handle_xsetbv(struct kvm_vcpu *vcpu)
5220{
5221 u64 new_bv = kvm_read_edx_eax(vcpu);
5222 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5223
5224 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5225 skip_emulated_instruction(vcpu);
5226 return 1;
5227}
5228
851ba692 5229static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5230{
58fbbf26
KT		 5231 if (likely(fasteoi)) {
5232 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5233 int access_type, offset;
5234
5235 access_type = exit_qualification & APIC_ACCESS_TYPE;
5236 offset = exit_qualification & APIC_ACCESS_OFFSET;
5237 /*
5238 * Sane guest uses MOV to write EOI, with written value
5239 * not cared. So make a short-circuit here by avoiding
5240 * heavy instruction emulation.
5241 */
5242 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5243 (offset == APIC_EOI)) {
5244 kvm_lapic_set_eoi(vcpu);
5245 skip_emulated_instruction(vcpu);
5246 return 1;
5247 }
5248 }
51d8b661 5249 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5250}
5251
c7c9c56c
YZ		 5252static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5253{
5254 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5255 int vector = exit_qualification & 0xff;
5256
5257 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5258 kvm_apic_set_eoi_accelerated(vcpu, vector);
5259 return 1;
5260}
5261
83d4c286
YZ		 5262static int handle_apic_write(struct kvm_vcpu *vcpu)
5263{
5264 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5265 u32 offset = exit_qualification & 0xfff;
5266
5267 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5268 kvm_apic_write_nodecode(vcpu, offset);
5269 return 1;
5270}
5271
851ba692 5272static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5273{
60637aac 5274 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5275 unsigned long exit_qualification;
e269fb21
JK		 5276 bool has_error_code = false;
5277 u32 error_code = 0;
37817f29 5278 u16 tss_selector;
7f3d35fd 5279 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5280
5281 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5282 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5283 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5284
5285 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5286
5287 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5288 if (reason == TASK_SWITCH_GATE && idt_v) {
5289 switch (type) {
5290 case INTR_TYPE_NMI_INTR:
5291 vcpu->arch.nmi_injected = false;
654f06fc 5292 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5293 break;
5294 case INTR_TYPE_EXT_INTR:
66fd3f7f 5295 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5296 kvm_clear_interrupt_queue(vcpu);
5297 break;
5298 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5299 if (vmx->idt_vectoring_info &
5300 VECTORING_INFO_DELIVER_CODE_MASK) {
5301 has_error_code = true;
5302 error_code =
5303 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5304 }
5305 /* fall through */
64a7ec06
GN		 5306 case INTR_TYPE_SOFT_EXCEPTION:
5307 kvm_clear_exception_queue(vcpu);
5308 break;
5309 default:
5310 break;
5311 }
60637aac 5312 }
37817f29
IE		 5313 tss_selector = exit_qualification;
5314
64a7ec06
GN		 5315 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5316 type != INTR_TYPE_EXT_INTR &&
5317 type != INTR_TYPE_NMI_INTR))
5318 skip_emulated_instruction(vcpu);
5319
7f3d35fd
KW		 5320 if (kvm_task_switch(vcpu, tss_selector,
5321 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5322 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5323 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5324 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5325 vcpu->run->internal.ndata = 0;
42dbaa5a 5326 return 0;
acb54517 5327 }
42dbaa5a
JK		 5328
5329 /* clear all local breakpoint enable flags */
5330 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5331
5332 /*
5333 * TODO: What about debug traps on tss switch?
5334 * Are we supposed to inject them and update dr6?
5335 */
5336
5337 return 1;
37817f29
IE		 5338}
5339
851ba692 5340static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5341{
f9c617f6 5342 unsigned long exit_qualification;
1439442c 5343 gpa_t gpa;
4f5982a5 5344 u32 error_code;
1439442c 5345 int gla_validity;
1439442c 5346
f9c617f6 5347 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5348
1439442c
SY		 5349 gla_validity = (exit_qualification >> 7) & 0x3;
5350 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5351 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5352 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5353 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5354 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5355 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5356 (long unsigned int)exit_qualification);
851ba692
AK		 5357 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5358 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5359 return 0;
1439442c
SY		 5360 }
5361
0be9c7a8
GN		 5362 /*
5363 * EPT violation happened while executing iret from NMI,
5364 * "blocked by NMI" bit has to be set before next VM entry.
5365 * There are errata that may cause this bit to not be set:
5366 * AAK134, BY25.
5367 */
bcd1c294
GN		 5368 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5369 cpu_has_virtual_nmis() &&
5370 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5371 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5372
1439442c 5373 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5374 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5375
5376 /* It is a write fault? */
5377 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5378 /* It is a fetch fault? */
5379 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5380 /* ept page table is present? */
5381 error_code |= (exit_qualification >> 3) & 0x1;
5382
25d92081
YZ		 5383 vcpu->arch.exit_qualification = exit_qualification;
5384
4f5982a5 5385 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5386}
5387
68f89400
MT		 5388static u64 ept_rsvd_mask(u64 spte, int level)
5389{
5390 int i;
5391 u64 mask = 0;
5392
5393 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5394 mask |= (1ULL << i);
5395
5396 if (level > 2)
5397 /* bits 7:3 reserved */
5398 mask |= 0xf8;
5399 else if (level == 2) {
5400 if (spte & (1ULL << 7))
5401 /* 2MB ref, bits 20:12 reserved */
5402 mask |= 0x1ff000;
5403 else
5404 /* bits 6:3 reserved */
5405 mask |= 0x78;
5406 }
5407
5408 return mask;
5409}
5410
5411static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5412 int level)
5413{
5414 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5415
5416 /* 010b (write-only) */
5417 WARN_ON((spte & 0x7) == 0x2);
5418
5419 /* 110b (write/execute) */
5420 WARN_ON((spte & 0x7) == 0x6);
5421
5422 /* 100b (execute-only) and value not supported by logical processor */
5423 if (!cpu_has_vmx_ept_execute_only())
5424 WARN_ON((spte & 0x7) == 0x4);
5425
5426 /* not 000b */
5427 if ((spte & 0x7)) {
5428 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5429
5430 if (rsvd_bits != 0) {
5431 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5432 __func__, rsvd_bits);
5433 WARN_ON(1);
5434 }
5435
5436 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5437 u64 ept_mem_type = (spte & 0x38) >> 3;
5438
5439 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5440 ept_mem_type == 7) {
5441 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5442 __func__, ept_mem_type);
5443 WARN_ON(1);
5444 }
5445 }
5446 }
5447}
5448
851ba692 5449static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5450{
5451 u64 sptes[4];
ce88decf 5452 int nr_sptes, i, ret;
68f89400
MT		 5453 gpa_t gpa;
5454
5455 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5456
ce88decf 5457 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5458 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5459 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5460 EMULATE_DONE;
f8f55942
XG		 5461
5462 if (unlikely(ret == RET_MMIO_PF_INVALID))
5463 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5464
b37fbea6 5465 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5466 return 1;
5467
5468 /* It is the real ept misconfig */
68f89400
MT		 5469 printk(KERN_ERR "EPT: Misconfiguration.\n");
5470 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5471
5472 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5473
5474 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5475 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5476
851ba692
AK		 5477 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5478 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5479
5480 return 0;
5481}
5482
851ba692 5483static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5484{
5485 u32 cpu_based_vm_exec_control;
5486
5487 /* clear pending NMI */
5488 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5489 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5490 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5491 ++vcpu->stat.nmi_window_exits;
3842d135 5492 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5493
5494 return 1;
5495}
5496
80ced186 5497static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5498{
8b3079a5
AK		 5499 struct vcpu_vmx *vmx = to_vmx(vcpu);
5500 enum emulation_result err = EMULATE_DONE;
80ced186 5501 int ret = 1;
49e9d557
AK		 5502 u32 cpu_exec_ctrl;
5503 bool intr_window_requested;
b8405c18 5504 unsigned count = 130;
49e9d557
AK		 5505
5506 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5507 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5508
b8405c18 5509 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5510 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5511 return handle_interrupt_window(&vmx->vcpu);
5512
de87dcdd
AK		 5513 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5514 return 1;
5515
991eebf9 5516 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5517
ac0a48c3 5518 if (err == EMULATE_USER_EXIT) {
94452b9e 5519 ++vcpu->stat.mmio_exits;
80ced186
MG		 5520 ret = 0;
5521 goto out;
5522 }
1d5a4d9b 5523
de5f70e0
AK		 5524 if (err != EMULATE_DONE) {
5525 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5526 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5527 vcpu->run->internal.ndata = 0;
6d77dbfc 5528 return 0;
de5f70e0 5529 }
ea953ef0 5530
8d76c49e
GN		 5531 if (vcpu->arch.halt_request) {
5532 vcpu->arch.halt_request = 0;
5533 ret = kvm_emulate_halt(vcpu);
5534 goto out;
5535 }
5536
ea953ef0 5537 if (signal_pending(current))
80ced186 5538 goto out;
ea953ef0
MG		 5539 if (need_resched())
5540 schedule();
5541 }
5542
14168786 5543 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5544out:
5545 return ret;
ea953ef0
MG		 5546}
5547
4b8d54f9
ZE		 5548/*
5549 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5550 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5551 */
9fb41ba8 5552static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5553{
5554 skip_emulated_instruction(vcpu);
5555 kvm_vcpu_on_spin(vcpu);
5556
5557 return 1;
5558}
5559
59708670
SY		 5560static int handle_invalid_op(struct kvm_vcpu *vcpu)
5561{
5562 kvm_queue_exception(vcpu, UD_VECTOR);
5563 return 1;
5564}
5565
ff2f6fe9
NHE		 5566/*
5567 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5568 * We could reuse a single VMCS for all the L2 guests, but we also want the
5569 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5570 * allows keeping them loaded on the processor, and in the future will allow
5571 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5572 * every entry if they never change.
5573 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5574 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5575 *
5576 * The following functions allocate and free a vmcs02 in this pool.
5577 */
5578
5579/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5580static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5581{
5582 struct vmcs02_list *item;
5583 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5584 if (item->vmptr == vmx->nested.current_vmptr) {
5585 list_move(&item->list, &vmx->nested.vmcs02_pool);
5586 return &item->vmcs02;
5587 }
5588
5589 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5590 /* Recycle the least recently used VMCS. */
5591 item = list_entry(vmx->nested.vmcs02_pool.prev,
5592 struct vmcs02_list, list);
5593 item->vmptr = vmx->nested.current_vmptr;
5594 list_move(&item->list, &vmx->nested.vmcs02_pool);
5595 return &item->vmcs02;
5596 }
5597
5598 /* Create a new VMCS */
0fa24ce3 5599 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5600 if (!item)
5601 return NULL;
5602 item->vmcs02.vmcs = alloc_vmcs();
5603 if (!item->vmcs02.vmcs) {
5604 kfree(item);
5605 return NULL;
5606 }
5607 loaded_vmcs_init(&item->vmcs02);
5608 item->vmptr = vmx->nested.current_vmptr;
5609 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5610 vmx->nested.vmcs02_num++;
5611 return &item->vmcs02;
5612}
5613
5614/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5615static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5616{
5617 struct vmcs02_list *item;
5618 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5619 if (item->vmptr == vmptr) {
5620 free_loaded_vmcs(&item->vmcs02);
5621 list_del(&item->list);
5622 kfree(item);
5623 vmx->nested.vmcs02_num--;
5624 return;
5625 }
5626}
5627
5628/*
5629 * Free all VMCSs saved for this vcpu, except the one pointed by
5630 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5631 * currently used, if running L2), and vmcs01 when running L2.
5632 */
5633static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5634{
5635 struct vmcs02_list *item, *n;
5636 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5637 if (vmx->loaded_vmcs != &item->vmcs02)
5638 free_loaded_vmcs(&item->vmcs02);
5639 list_del(&item->list);
5640 kfree(item);
5641 }
5642 vmx->nested.vmcs02_num = 0;
5643
5644 if (vmx->loaded_vmcs != &vmx->vmcs01)
5645 free_loaded_vmcs(&vmx->vmcs01);
5646}
5647
0658fbaa
ACL		 5648/*
5649 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5650 * set the success or error code of an emulated VMX instruction, as specified
5651 * by Vol 2B, VMX Instruction Reference, "Conventions".
5652 */
5653static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5654{
5655 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5656 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5657 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5658}
5659
5660static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5661{
5662 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5663 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5664 X86_EFLAGS_SF | X86_EFLAGS_OF))
5665 | X86_EFLAGS_CF);
5666}
5667
145c28dd 5668static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5669 u32 vm_instruction_error)
5670{
5671 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5672 /*
5673 * failValid writes the error number to the current VMCS, which
5674 * can't be done there isn't a current VMCS.
5675 */
5676 nested_vmx_failInvalid(vcpu);
5677 return;
5678 }
5679 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5680 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5681 X86_EFLAGS_SF | X86_EFLAGS_OF))
5682 | X86_EFLAGS_ZF);
5683 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5684 /*
5685 * We don't need to force a shadow sync because
5686 * VM_INSTRUCTION_ERROR is not shadowed
5687 */
5688}
145c28dd 5689
ec378aee
NHE		 5690/*
5691 * Emulate the VMXON instruction.
5692 * Currently, we just remember that VMX is active, and do not save or even
5693 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5694 * do not currently need to store anything in that guest-allocated memory
5695 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5696 * argument is different from the VMXON pointer (which the spec says they do).
5697 */
5698static int handle_vmon(struct kvm_vcpu *vcpu)
5699{
5700 struct kvm_segment cs;
5701 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5702 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5703 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5704 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5705
5706 /* The Intel VMX Instruction Reference lists a bunch of bits that
5707 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5708 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5709 * Otherwise, we should fail with #UD. We test these now:
5710 */
5711 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5712 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5713 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5714 kvm_queue_exception(vcpu, UD_VECTOR);
5715 return 1;
5716 }
5717
5718 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5719 if (is_long_mode(vcpu) && !cs.l) {
5720 kvm_queue_exception(vcpu, UD_VECTOR);
5721 return 1;
5722 }
5723
5724 if (vmx_get_cpl(vcpu)) {
5725 kvm_inject_gp(vcpu, 0);
5726 return 1;
5727 }
145c28dd
AG		 5728 if (vmx->nested.vmxon) {
5729 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5730 skip_emulated_instruction(vcpu);
5731 return 1;
5732 }
b3897a49
NHE		 5733
5734 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5735 != VMXON_NEEDED_FEATURES) {
5736 kvm_inject_gp(vcpu, 0);
5737 return 1;
5738 }
5739
8de48833
AG		 5740 if (enable_shadow_vmcs) {
5741 shadow_vmcs = alloc_vmcs();
5742 if (!shadow_vmcs)
5743 return -ENOMEM;
5744 /* mark vmcs as shadow */
5745 shadow_vmcs->revision_id |= (1u << 31);
5746 /* init shadow vmcs */
5747 vmcs_clear(shadow_vmcs);
5748 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5749 }
ec378aee 5750
ff2f6fe9
NHE		 5751 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5752 vmx->nested.vmcs02_num = 0;
5753
ec378aee
NHE		 5754 vmx->nested.vmxon = true;
5755
5756 skip_emulated_instruction(vcpu);
a25eb114 5757 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5758 return 1;
5759}
5760
5761/*
5762 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5763 * for running VMX instructions (except VMXON, whose prerequisites are
5764 * slightly different). It also specifies what exception to inject otherwise.
5765 */
5766static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5767{
5768 struct kvm_segment cs;
5769 struct vcpu_vmx *vmx = to_vmx(vcpu);
5770
5771 if (!vmx->nested.vmxon) {
5772 kvm_queue_exception(vcpu, UD_VECTOR);
5773 return 0;
5774 }
5775
5776 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5777 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5778 (is_long_mode(vcpu) && !cs.l)) {
5779 kvm_queue_exception(vcpu, UD_VECTOR);
5780 return 0;
5781 }
5782
5783 if (vmx_get_cpl(vcpu)) {
5784 kvm_inject_gp(vcpu, 0);
5785 return 0;
5786 }
5787
5788 return 1;
5789}
5790
e7953d7f
AG		 5791static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5792{
8a1b9dd0 5793 u32 exec_control;
012f83cb
AG		 5794 if (enable_shadow_vmcs) {
5795 if (vmx->nested.current_vmcs12 != NULL) {
5796 /* copy to memory all shadowed fields in case
5797 they were modified */
5798 copy_shadow_to_vmcs12(vmx);
5799 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5800 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5801 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5802 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5803 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5804 }
5805 }
e7953d7f
AG		 5806 kunmap(vmx->nested.current_vmcs12_page);
5807 nested_release_page(vmx->nested.current_vmcs12_page);
5808}
5809
ec378aee
NHE		 5810/*
5811 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5812 * just stops using VMX.
5813 */
5814static void free_nested(struct vcpu_vmx *vmx)
5815{
5816 if (!vmx->nested.vmxon)
5817 return;
5818 vmx->nested.vmxon = false;
a9d30f33 5819 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5820 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5821 vmx->nested.current_vmptr = -1ull;
5822 vmx->nested.current_vmcs12 = NULL;
5823 }
e7953d7f
AG		 5824 if (enable_shadow_vmcs)
5825 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5826 /* Unpin physical memory we referred to in current vmcs02 */
5827 if (vmx->nested.apic_access_page) {
5828 nested_release_page(vmx->nested.apic_access_page);
5829 vmx->nested.apic_access_page = 0;
5830 }
ff2f6fe9
NHE		 5831
5832 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5833}
5834
5835/* Emulate the VMXOFF instruction */
5836static int handle_vmoff(struct kvm_vcpu *vcpu)
5837{
5838 if (!nested_vmx_check_permission(vcpu))
5839 return 1;
5840 free_nested(to_vmx(vcpu));
5841 skip_emulated_instruction(vcpu);
a25eb114 5842 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5843 return 1;
5844}
5845
064aea77
NHE		 5846/*
5847 * Decode the memory-address operand of a vmx instruction, as recorded on an
5848 * exit caused by such an instruction (run by a guest hypervisor).
5849 * On success, returns 0. When the operand is invalid, returns 1 and throws
5850 * #UD or #GP.
5851 */
5852static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5853 unsigned long exit_qualification,
5854 u32 vmx_instruction_info, gva_t *ret)
5855{
5856 /*
5857 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5858 * Execution", on an exit, vmx_instruction_info holds most of the
5859 * addressing components of the operand. Only the displacement part
5860 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5861 * For how an actual address is calculated from all these components,
5862 * refer to Vol. 1, "Operand Addressing".
5863 */
5864 int scaling = vmx_instruction_info & 3;
5865 int addr_size = (vmx_instruction_info >> 7) & 7;
5866 bool is_reg = vmx_instruction_info & (1u << 10);
5867 int seg_reg = (vmx_instruction_info >> 15) & 7;
5868 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5869 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5870 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5871 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5872
5873 if (is_reg) {
5874 kvm_queue_exception(vcpu, UD_VECTOR);
5875 return 1;
5876 }
5877
5878 /* Addr = segment_base + offset */
5879 /* offset = base + [index * scale] + displacement */
5880 *ret = vmx_get_segment_base(vcpu, seg_reg);
5881 if (base_is_valid)
5882 *ret += kvm_register_read(vcpu, base_reg);
5883 if (index_is_valid)
5884 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5885 *ret += exit_qualification; /* holds the displacement */
5886
5887 if (addr_size == 1) /* 32 bit */
5888 *ret &= 0xffffffff;
5889
5890 /*
5891 * TODO: throw #GP (and return 1) in various cases that the VM*
5892 * instructions require it - e.g., offset beyond segment limit,
5893 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5894 * address, and so on. Currently these are not checked.
5895 */
5896 return 0;
5897}
5898
27d6c865
NHE		 5899/* Emulate the VMCLEAR instruction */
5900static int handle_vmclear(struct kvm_vcpu *vcpu)
5901{
5902 struct vcpu_vmx *vmx = to_vmx(vcpu);
5903 gva_t gva;
5904 gpa_t vmptr;
5905 struct vmcs12 *vmcs12;
5906 struct page *page;
5907 struct x86_exception e;
5908
5909 if (!nested_vmx_check_permission(vcpu))
5910 return 1;
5911
5912 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5913 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5914 return 1;
5915
5916 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5917 sizeof(vmptr), &e)) {
5918 kvm_inject_page_fault(vcpu, &e);
5919 return 1;
5920 }
5921
5922 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5923 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5924 skip_emulated_instruction(vcpu);
5925 return 1;
5926 }
5927
5928 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5929 nested_release_vmcs12(vmx);
27d6c865
NHE		 5930 vmx->nested.current_vmptr = -1ull;
5931 vmx->nested.current_vmcs12 = NULL;
5932 }
5933
5934 page = nested_get_page(vcpu, vmptr);
5935 if (page == NULL) {
5936 /*
5937 * For accurate processor emulation, VMCLEAR beyond available
5938 * physical memory should do nothing at all. However, it is
5939 * possible that a nested vmx bug, not a guest hypervisor bug,
5940 * resulted in this case, so let's shut down before doing any
5941 * more damage:
5942 */
5943 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5944 return 1;
5945 }
5946 vmcs12 = kmap(page);
5947 vmcs12->launch_state = 0;
5948 kunmap(page);
5949 nested_release_page(page);
5950
5951 nested_free_vmcs02(vmx, vmptr);
5952
5953 skip_emulated_instruction(vcpu);
5954 nested_vmx_succeed(vcpu);
5955 return 1;
5956}
5957
cd232ad0
NHE		 5958static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5959
5960/* Emulate the VMLAUNCH instruction */
5961static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5962{
5963 return nested_vmx_run(vcpu, true);
5964}
5965
5966/* Emulate the VMRESUME instruction */
5967static int handle_vmresume(struct kvm_vcpu *vcpu)
5968{
5969
5970 return nested_vmx_run(vcpu, false);
5971}
5972
49f705c5
NHE		 5973enum vmcs_field_type {
5974 VMCS_FIELD_TYPE_U16 = 0,
5975 VMCS_FIELD_TYPE_U64 = 1,
5976 VMCS_FIELD_TYPE_U32 = 2,
5977 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5978};
5979
5980static inline int vmcs_field_type(unsigned long field)
5981{
5982 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5983 return VMCS_FIELD_TYPE_U32;
5984 return (field >> 13) & 0x3 ;
5985}
5986
5987static inline int vmcs_field_readonly(unsigned long field)
5988{
5989 return (((field >> 10) & 0x3) == 1);
5990}
5991
5992/*
5993 * Read a vmcs12 field. Since these can have varying lengths and we return
5994 * one type, we chose the biggest type (u64) and zero-extend the return value
5995 * to that size. Note that the caller, handle_vmread, might need to use only
5996 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5997 * 64-bit fields are to be returned).
5998 */
5999static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6000 unsigned long field, u64 *ret)
6001{
6002 short offset = vmcs_field_to_offset(field);
6003 char *p;
6004
6005 if (offset < 0)
6006 return 0;
6007
6008 p = ((char *)(get_vmcs12(vcpu))) + offset;
6009
6010 switch (vmcs_field_type(field)) {
6011 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6012 *ret = *((natural_width *)p);
6013 return 1;
6014 case VMCS_FIELD_TYPE_U16:
6015 *ret = *((u16 *)p);
6016 return 1;
6017 case VMCS_FIELD_TYPE_U32:
6018 *ret = *((u32 *)p);
6019 return 1;
6020 case VMCS_FIELD_TYPE_U64:
6021 *ret = *((u64 *)p);
6022 return 1;
6023 default:
6024 return 0; /* can never happen. */
6025 }
6026}
6027
20b97fea
AG		 6028
6029static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6030 unsigned long field, u64 field_value){
6031 short offset = vmcs_field_to_offset(field);
6032 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6033 if (offset < 0)
6034 return false;
6035
6036 switch (vmcs_field_type(field)) {
6037 case VMCS_FIELD_TYPE_U16:
6038 *(u16 *)p = field_value;
6039 return true;
6040 case VMCS_FIELD_TYPE_U32:
6041 *(u32 *)p = field_value;
6042 return true;
6043 case VMCS_FIELD_TYPE_U64:
6044 *(u64 *)p = field_value;
6045 return true;
6046 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6047 *(natural_width *)p = field_value;
6048 return true;
6049 default:
6050 return false; /* can never happen. */
6051 }
6052
6053}
6054
16f5b903
AG		 6055static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6056{
6057 int i;
6058 unsigned long field;
6059 u64 field_value;
6060 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6061 const unsigned long *fields = shadow_read_write_fields;
6062 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6063
6064 vmcs_load(shadow_vmcs);
6065
6066 for (i = 0; i < num_fields; i++) {
6067 field = fields[i];
6068 switch (vmcs_field_type(field)) {
6069 case VMCS_FIELD_TYPE_U16:
6070 field_value = vmcs_read16(field);
6071 break;
6072 case VMCS_FIELD_TYPE_U32:
6073 field_value = vmcs_read32(field);
6074 break;
6075 case VMCS_FIELD_TYPE_U64:
6076 field_value = vmcs_read64(field);
6077 break;
6078 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6079 field_value = vmcs_readl(field);
6080 break;
6081 }
6082 vmcs12_write_any(&vmx->vcpu, field, field_value);
6083 }
6084
6085 vmcs_clear(shadow_vmcs);
6086 vmcs_load(vmx->loaded_vmcs->vmcs);
6087}
6088
c3114420
AG		 6089static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6090{
c2bae893
MK		 6091 const unsigned long *fields[] = {
6092 shadow_read_write_fields,
6093 shadow_read_only_fields
c3114420 6094 };
c2bae893 6095 const int max_fields[] = {
c3114420
AG		 6096 max_shadow_read_write_fields,
6097 max_shadow_read_only_fields
6098 };
6099 int i, q;
6100 unsigned long field;
6101 u64 field_value = 0;
6102 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6103
6104 vmcs_load(shadow_vmcs);
6105
c2bae893 6106 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6107 for (i = 0; i < max_fields[q]; i++) {
6108 field = fields[q][i];
6109 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6110
6111 switch (vmcs_field_type(field)) {
6112 case VMCS_FIELD_TYPE_U16:
6113 vmcs_write16(field, (u16)field_value);
6114 break;
6115 case VMCS_FIELD_TYPE_U32:
6116 vmcs_write32(field, (u32)field_value);
6117 break;
6118 case VMCS_FIELD_TYPE_U64:
6119 vmcs_write64(field, (u64)field_value);
6120 break;
6121 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6122 vmcs_writel(field, (long)field_value);
6123 break;
6124 }
6125 }
6126 }
6127
6128 vmcs_clear(shadow_vmcs);
6129 vmcs_load(vmx->loaded_vmcs->vmcs);
6130}
6131
49f705c5
NHE		 6132/*
6133 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6134 * used before) all generate the same failure when it is missing.
6135 */
6136static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6137{
6138 struct vcpu_vmx *vmx = to_vmx(vcpu);
6139 if (vmx->nested.current_vmptr == -1ull) {
6140 nested_vmx_failInvalid(vcpu);
6141 skip_emulated_instruction(vcpu);
6142 return 0;
6143 }
6144 return 1;
6145}
6146
6147static int handle_vmread(struct kvm_vcpu *vcpu)
6148{
6149 unsigned long field;
6150 u64 field_value;
6151 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6152 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6153 gva_t gva = 0;
6154
6155 if (!nested_vmx_check_permission(vcpu) ||
6156 !nested_vmx_check_vmcs12(vcpu))
6157 return 1;
6158
6159 /* Decode instruction info and find the field to read */
6160 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6161 /* Read the field, zero-extended to a u64 field_value */
6162 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6163 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6164 skip_emulated_instruction(vcpu);
6165 return 1;
6166 }
6167 /*
6168 * Now copy part of this value to register or memory, as requested.
6169 * Note that the number of bits actually copied is 32 or 64 depending
6170 * on the guest's mode (32 or 64 bit), not on the given field's length.
6171 */
6172 if (vmx_instruction_info & (1u << 10)) {
6173 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6174 field_value);
6175 } else {
6176 if (get_vmx_mem_address(vcpu, exit_qualification,
6177 vmx_instruction_info, &gva))
6178 return 1;
6179 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6180 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6181 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6182 }
6183
6184 nested_vmx_succeed(vcpu);
6185 skip_emulated_instruction(vcpu);
6186 return 1;
6187}
6188
6189
6190static int handle_vmwrite(struct kvm_vcpu *vcpu)
6191{
6192 unsigned long field;
6193 gva_t gva;
6194 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6195 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6196 /* The value to write might be 32 or 64 bits, depending on L1's long
6197 * mode, and eventually we need to write that into a field of several
6198 * possible lengths. The code below first zero-extends the value to 64
6199 * bit (field_value), and then copies only the approriate number of
6200 * bits into the vmcs12 field.
6201 */
6202 u64 field_value = 0;
6203 struct x86_exception e;
6204
6205 if (!nested_vmx_check_permission(vcpu) ||
6206 !nested_vmx_check_vmcs12(vcpu))
6207 return 1;
6208
6209 if (vmx_instruction_info & (1u << 10))
6210 field_value = kvm_register_read(vcpu,
6211 (((vmx_instruction_info) >> 3) & 0xf));
6212 else {
6213 if (get_vmx_mem_address(vcpu, exit_qualification,
6214 vmx_instruction_info, &gva))
6215 return 1;
6216 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6217 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6218 kvm_inject_page_fault(vcpu, &e);
6219 return 1;
6220 }
6221 }
6222
6223
6224 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6225 if (vmcs_field_readonly(field)) {
6226 nested_vmx_failValid(vcpu,
6227 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6228 skip_emulated_instruction(vcpu);
6229 return 1;
6230 }
6231
20b97fea 6232 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6233 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6234 skip_emulated_instruction(vcpu);
6235 return 1;
6236 }
6237
6238 nested_vmx_succeed(vcpu);
6239 skip_emulated_instruction(vcpu);
6240 return 1;
6241}
6242
63846663
NHE		 6243/* Emulate the VMPTRLD instruction */
6244static int handle_vmptrld(struct kvm_vcpu *vcpu)
6245{
6246 struct vcpu_vmx *vmx = to_vmx(vcpu);
6247 gva_t gva;
6248 gpa_t vmptr;
6249 struct x86_exception e;
8a1b9dd0 6250 u32 exec_control;
63846663
NHE		 6251
6252 if (!nested_vmx_check_permission(vcpu))
6253 return 1;
6254
6255 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6256 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6257 return 1;
6258
6259 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6260 sizeof(vmptr), &e)) {
6261 kvm_inject_page_fault(vcpu, &e);
6262 return 1;
6263 }
6264
6265 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6266 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6267 skip_emulated_instruction(vcpu);
6268 return 1;
6269 }
6270
6271 if (vmx->nested.current_vmptr != vmptr) {
6272 struct vmcs12 *new_vmcs12;
6273 struct page *page;
6274 page = nested_get_page(vcpu, vmptr);
6275 if (page == NULL) {
6276 nested_vmx_failInvalid(vcpu);
6277 skip_emulated_instruction(vcpu);
6278 return 1;
6279 }
6280 new_vmcs12 = kmap(page);
6281 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6282 kunmap(page);
6283 nested_release_page_clean(page);
6284 nested_vmx_failValid(vcpu,
6285 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6286 skip_emulated_instruction(vcpu);
6287 return 1;
6288 }
e7953d7f
AG		 6289 if (vmx->nested.current_vmptr != -1ull)
6290 nested_release_vmcs12(vmx);
63846663
NHE		 6291
6292 vmx->nested.current_vmptr = vmptr;
6293 vmx->nested.current_vmcs12 = new_vmcs12;
6294 vmx->nested.current_vmcs12_page = page;
012f83cb 6295 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6296 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6297 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6298 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6299 vmcs_write64(VMCS_LINK_POINTER,
6300 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6301 vmx->nested.sync_shadow_vmcs = true;
6302 }
63846663
NHE		 6303 }
6304
6305 nested_vmx_succeed(vcpu);
6306 skip_emulated_instruction(vcpu);
6307 return 1;
6308}
6309
6a4d7550
NHE		 6310/* Emulate the VMPTRST instruction */
6311static int handle_vmptrst(struct kvm_vcpu *vcpu)
6312{
6313 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6314 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6315 gva_t vmcs_gva;
6316 struct x86_exception e;
6317
6318 if (!nested_vmx_check_permission(vcpu))
6319 return 1;
6320
6321 if (get_vmx_mem_address(vcpu, exit_qualification,
6322 vmx_instruction_info, &vmcs_gva))
6323 return 1;
6324 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6325 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6326 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6327 sizeof(u64), &e)) {
6328 kvm_inject_page_fault(vcpu, &e);
6329 return 1;
6330 }
6331 nested_vmx_succeed(vcpu);
6332 skip_emulated_instruction(vcpu);
6333 return 1;
6334}
6335
bfd0a56b
NHE		 6336/* Emulate the INVEPT instruction */
6337static int handle_invept(struct kvm_vcpu *vcpu)
6338{
6339 u32 vmx_instruction_info, types;
6340 unsigned long type;
6341 gva_t gva;
6342 struct x86_exception e;
6343 struct {
6344 u64 eptp, gpa;
6345 } operand;
6346 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6347
6348 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6349 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6350 kvm_queue_exception(vcpu, UD_VECTOR);
6351 return 1;
6352 }
6353
6354 if (!nested_vmx_check_permission(vcpu))
6355 return 1;
6356
6357 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6358 kvm_queue_exception(vcpu, UD_VECTOR);
6359 return 1;
6360 }
6361
6362 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6363 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6364
6365 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6366
6367 if (!(types & (1UL << type))) {
6368 nested_vmx_failValid(vcpu,
6369 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6370 return 1;
6371 }
6372
6373 /* According to the Intel VMX instruction reference, the memory
6374 * operand is read even if it isn't needed (e.g., for type==global)
6375 */
6376 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6377 vmx_instruction_info, &gva))
6378 return 1;
6379 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6380 sizeof(operand), &e)) {
6381 kvm_inject_page_fault(vcpu, &e);
6382 return 1;
6383 }
6384
6385 switch (type) {
6386 case VMX_EPT_EXTENT_CONTEXT:
6387 if ((operand.eptp & eptp_mask) !=
6388 (nested_ept_get_cr3(vcpu) & eptp_mask))
6389 break;
6390 case VMX_EPT_EXTENT_GLOBAL:
6391 kvm_mmu_sync_roots(vcpu);
6392 kvm_mmu_flush_tlb(vcpu);
6393 nested_vmx_succeed(vcpu);
6394 break;
6395 default:
6396 BUG_ON(1);
6397 break;
6398 }
6399
6400 skip_emulated_instruction(vcpu);
6401 return 1;
6402}
6403
6aa8b732
AK		 6404/*
6405 * The exit handlers return 1 if the exit was handled fully and guest execution
6406 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6407 * to be done to userspace and return 0.
6408 */
772e0318 6409static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6410 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6411 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6412 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6413 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6414 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6415 [EXIT_REASON_CR_ACCESS] = handle_cr,
6416 [EXIT_REASON_DR_ACCESS] = handle_dr,
6417 [EXIT_REASON_CPUID] = handle_cpuid,
6418 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6419 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6420 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6421 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6422 [EXIT_REASON_INVD] = handle_invd,
a7052897 6423 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6424 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6425 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6426 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6427 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6428 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6429 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6430 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6431 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6432 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6433 [EXIT_REASON_VMOFF] = handle_vmoff,
6434 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6435 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6436 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6437 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6438 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6439 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6440 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6441 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6442 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6443 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6444 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6445 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6446 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6447 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6448 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6449};
6450
6451static const int kvm_vmx_max_exit_handlers =
50a3485c 6452 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6453
908a7bdd
JK		 6454static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6455 struct vmcs12 *vmcs12)
6456{
6457 unsigned long exit_qualification;
6458 gpa_t bitmap, last_bitmap;
6459 unsigned int port;
6460 int size;
6461 u8 b;
6462
6463 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6464 return 1;
6465
6466 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6467 return 0;
6468
6469 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6470
6471 port = exit_qualification >> 16;
6472 size = (exit_qualification & 7) + 1;
6473
6474 last_bitmap = (gpa_t)-1;
6475 b = -1;
6476
6477 while (size > 0) {
6478 if (port < 0x8000)
6479 bitmap = vmcs12->io_bitmap_a;
6480 else if (port < 0x10000)
6481 bitmap = vmcs12->io_bitmap_b;
6482 else
6483 return 1;
6484 bitmap += (port & 0x7fff) / 8;
6485
6486 if (last_bitmap != bitmap)
6487 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6488 return 1;
6489 if (b & (1 << (port & 7)))
6490 return 1;
6491
6492 port++;
6493 size--;
6494 last_bitmap = bitmap;
6495 }
6496
6497 return 0;
6498}
6499
644d711a
NHE		 6500/*
6501 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6502 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6503 * disinterest in the current event (read or write a specific MSR) by using an
6504 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6505 */
6506static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6507 struct vmcs12 *vmcs12, u32 exit_reason)
6508{
6509 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6510 gpa_t bitmap;
6511
cbd29cb6 6512 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6513 return 1;
6514
6515 /*
6516 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6517 * for the four combinations of read/write and low/high MSR numbers.
6518 * First we need to figure out which of the four to use:
6519 */
6520 bitmap = vmcs12->msr_bitmap;
6521 if (exit_reason == EXIT_REASON_MSR_WRITE)
6522 bitmap += 2048;
6523 if (msr_index >= 0xc0000000) {
6524 msr_index -= 0xc0000000;
6525 bitmap += 1024;
6526 }
6527
6528 /* Then read the msr_index'th bit from this bitmap: */
6529 if (msr_index < 1024*8) {
6530 unsigned char b;
bd31a7f5
JK		 6531 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6532 return 1;
644d711a
NHE		 6533 return 1 & (b >> (msr_index & 7));
6534 } else
6535 return 1; /* let L1 handle the wrong parameter */
6536}
6537
6538/*
6539 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6540 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6541 * intercept (via guest_host_mask etc.) the current event.
6542 */
6543static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6544 struct vmcs12 *vmcs12)
6545{
6546 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6547 int cr = exit_qualification & 15;
6548 int reg = (exit_qualification >> 8) & 15;
6549 unsigned long val = kvm_register_read(vcpu, reg);
6550
6551 switch ((exit_qualification >> 4) & 3) {
6552 case 0: /* mov to cr */
6553 switch (cr) {
6554 case 0:
6555 if (vmcs12->cr0_guest_host_mask &
6556 (val ^ vmcs12->cr0_read_shadow))
6557 return 1;
6558 break;
6559 case 3:
6560 if ((vmcs12->cr3_target_count >= 1 &&
6561 vmcs12->cr3_target_value0 == val) ||
6562 (vmcs12->cr3_target_count >= 2 &&
6563 vmcs12->cr3_target_value1 == val) ||
6564 (vmcs12->cr3_target_count >= 3 &&
6565 vmcs12->cr3_target_value2 == val) ||
6566 (vmcs12->cr3_target_count >= 4 &&
6567 vmcs12->cr3_target_value3 == val))
6568 return 0;
6569 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6570 return 1;
6571 break;
6572 case 4:
6573 if (vmcs12->cr4_guest_host_mask &
6574 (vmcs12->cr4_read_shadow ^ val))
6575 return 1;
6576 break;
6577 case 8:
6578 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6579 return 1;
6580 break;
6581 }
6582 break;
6583 case 2: /* clts */
6584 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6585 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6586 return 1;
6587 break;
6588 case 1: /* mov from cr */
6589 switch (cr) {
6590 case 3:
6591 if (vmcs12->cpu_based_vm_exec_control &
6592 CPU_BASED_CR3_STORE_EXITING)
6593 return 1;
6594 break;
6595 case 8:
6596 if (vmcs12->cpu_based_vm_exec_control &
6597 CPU_BASED_CR8_STORE_EXITING)
6598 return 1;
6599 break;
6600 }
6601 break;
6602 case 3: /* lmsw */
6603 /*
6604 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6605 * cr0. Other attempted changes are ignored, with no exit.
6606 */
6607 if (vmcs12->cr0_guest_host_mask & 0xe &
6608 (val ^ vmcs12->cr0_read_shadow))
6609 return 1;
6610 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6611 !(vmcs12->cr0_read_shadow & 0x1) &&
6612 (val & 0x1))
6613 return 1;
6614 break;
6615 }
6616 return 0;
6617}
6618
6619/*
6620 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6621 * should handle it ourselves in L0 (and then continue L2). Only call this
6622 * when in is_guest_mode (L2).
6623 */
6624static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6625{
644d711a
NHE		 6626 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6627 struct vcpu_vmx *vmx = to_vmx(vcpu);
6628 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6629 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6630
6631 if (vmx->nested.nested_run_pending)
6632 return 0;
6633
6634 if (unlikely(vmx->fail)) {
bd80158a
JK		 6635 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6636 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6637 return 1;
6638 }
6639
6640 switch (exit_reason) {
6641 case EXIT_REASON_EXCEPTION_NMI:
6642 if (!is_exception(intr_info))
6643 return 0;
6644 else if (is_page_fault(intr_info))
6645 return enable_ept;
e504c909
AB		 6646 else if (is_no_device(intr_info) &&
6647 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6648 return 0;
644d711a
NHE		 6649 return vmcs12->exception_bitmap &
6650 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6651 case EXIT_REASON_EXTERNAL_INTERRUPT:
6652 return 0;
6653 case EXIT_REASON_TRIPLE_FAULT:
6654 return 1;
6655 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6656 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6657 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6658 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6659 case EXIT_REASON_TASK_SWITCH:
6660 return 1;
6661 case EXIT_REASON_CPUID:
6662 return 1;
6663 case EXIT_REASON_HLT:
6664 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6665 case EXIT_REASON_INVD:
6666 return 1;
6667 case EXIT_REASON_INVLPG:
6668 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6669 case EXIT_REASON_RDPMC:
6670 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6671 case EXIT_REASON_RDTSC:
6672 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6673 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6674 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6675 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6676 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6677 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6678 case EXIT_REASON_INVEPT:
644d711a
NHE		 6679 /*
6680 * VMX instructions trap unconditionally. This allows L1 to
6681 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6682 */
6683 return 1;
6684 case EXIT_REASON_CR_ACCESS:
6685 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6686 case EXIT_REASON_DR_ACCESS:
6687 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6688 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6689 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6690 case EXIT_REASON_MSR_READ:
6691 case EXIT_REASON_MSR_WRITE:
6692 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6693 case EXIT_REASON_INVALID_STATE:
6694 return 1;
6695 case EXIT_REASON_MWAIT_INSTRUCTION:
6696 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6697 case EXIT_REASON_MONITOR_INSTRUCTION:
6698 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6699 case EXIT_REASON_PAUSE_INSTRUCTION:
6700 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6701 nested_cpu_has2(vmcs12,
6702 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6703 case EXIT_REASON_MCE_DURING_VMENTRY:
6704 return 0;
6705 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6706 return 1;
6707 case EXIT_REASON_APIC_ACCESS:
6708 return nested_cpu_has2(vmcs12,
6709 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6710 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6711 /*
6712 * L0 always deals with the EPT violation. If nested EPT is
6713 * used, and the nested mmu code discovers that the address is
6714 * missing in the guest EPT table (EPT12), the EPT violation
6715 * will be injected with nested_ept_inject_page_fault()
6716 */
6717 return 0;
644d711a 6718 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6719 /*
6720 * L2 never uses directly L1's EPT, but rather L0's own EPT
6721 * table (shadow on EPT) or a merged EPT table that L0 built
6722 * (EPT on EPT). So any problems with the structure of the
6723 * table is L0's fault.
6724 */
644d711a 6725 return 0;
0238ea91
JK		 6726 case EXIT_REASON_PREEMPTION_TIMER:
6727 return vmcs12->pin_based_vm_exec_control &
6728 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6729 case EXIT_REASON_WBINVD:
6730 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6731 case EXIT_REASON_XSETBV:
6732 return 1;
6733 default:
6734 return 1;
6735 }
6736}
6737
586f9607
AK		 6738static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6739{
6740 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6741 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6742}
6743
7854cbca
ACL		 6744static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6745{
6746 u64 delta_tsc_l1;
6747 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6748
6749 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6750 PIN_BASED_VMX_PREEMPTION_TIMER))
6751 return;
6752 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6753 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6754 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6755 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6756 - vcpu->arch.last_guest_tsc;
6757 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6758 if (preempt_val_l2 <= preempt_val_l1)
6759 preempt_val_l2 = 0;
6760 else
6761 preempt_val_l2 -= preempt_val_l1;
6762 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6763}
6764
6aa8b732
AK		 6765/*
6766 * The guest has exited. See if we can fix it or if we need userspace
6767 * assistance.
6768 */
851ba692 6769static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6770{
29bd8a78 6771 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6772 u32 exit_reason = vmx->exit_reason;
1155f76a 6773 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6774
80ced186 6775 /* If guest state is invalid, start emulating */
14168786 6776 if (vmx->emulation_required)
80ced186 6777 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6778
644d711a
NHE		 6779 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6780 nested_vmx_vmexit(vcpu);
6781 return 1;
6782 }
6783
5120702e
MG		 6784 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6785 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6786 vcpu->run->fail_entry.hardware_entry_failure_reason
6787 = exit_reason;
6788 return 0;
6789 }
6790
29bd8a78 6791 if (unlikely(vmx->fail)) {
851ba692
AK		 6792 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6793 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6794 = vmcs_read32(VM_INSTRUCTION_ERROR);
6795 return 0;
6796 }
6aa8b732 6797
b9bf6882
XG		 6798 /*
6799 * Note:
6800 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6801 * delivery event since it indicates guest is accessing MMIO.
6802 * The vm-exit can be triggered again after return to guest that
6803 * will cause infinite loop.
6804 */
d77c26fc 6805 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6806 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6807 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6808 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6809 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6810 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6811 vcpu->run->internal.ndata = 2;
6812 vcpu->run->internal.data[0] = vectoring_info;
6813 vcpu->run->internal.data[1] = exit_reason;
6814 return 0;
6815 }
3b86cd99 6816
644d711a
NHE		 6817 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6818 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6819 get_vmcs12(vcpu))))) {
c4282df9 6820 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6821 vmx->soft_vnmi_blocked = 0;
3b86cd99 6822 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6823 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6824 /*
6825 * This CPU don't support us in finding the end of an
6826 * NMI-blocked window if the guest runs with IRQs
6827 * disabled. So we pull the trigger after 1 s of
6828 * futile waiting, but inform the user about this.
6829 */
6830 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6831 "state on VCPU %d after 1 s timeout\n",
6832 __func__, vcpu->vcpu_id);
6833 vmx->soft_vnmi_blocked = 0;
3b86cd99 6834 }
3b86cd99
JK		 6835 }
6836
6aa8b732
AK		 6837 if (exit_reason < kvm_vmx_max_exit_handlers
6838 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6839 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6840 else {
851ba692
AK		 6841 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6842 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6843 }
6844 return 0;
6845}
6846
95ba8273 6847static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6848{
95ba8273 6849 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6850 vmcs_write32(TPR_THRESHOLD, 0);
6851 return;
6852 }
6853
95ba8273 6854 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6855}
6856
8d14695f
YZ		 6857static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6858{
6859 u32 sec_exec_control;
6860
6861 /*
6862 * There is not point to enable virtualize x2apic without enable
6863 * apicv
6864 */
c7c9c56c
YZ		 6865 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6866 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6867 return;
6868
6869 if (!vm_need_tpr_shadow(vcpu->kvm))
6870 return;
6871
6872 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6873
6874 if (set) {
6875 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6876 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6877 } else {
6878 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6879 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6880 }
6881 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6882
6883 vmx_set_msr_bitmap(vcpu);
6884}
6885
c7c9c56c
YZ		 6886static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6887{
6888 u16 status;
6889 u8 old;
6890
6891 if (!vmx_vm_has_apicv(kvm))
6892 return;
6893
6894 if (isr == -1)
6895 isr = 0;
6896
6897 status = vmcs_read16(GUEST_INTR_STATUS);
6898 old = status >> 8;
6899 if (isr != old) {
6900 status &= 0xff;
6901 status |= isr << 8;
6902 vmcs_write16(GUEST_INTR_STATUS, status);
6903 }
6904}
6905
6906static void vmx_set_rvi(int vector)
6907{
6908 u16 status;
6909 u8 old;
6910
6911 status = vmcs_read16(GUEST_INTR_STATUS);
6912 old = (u8)status & 0xff;
6913 if ((u8)vector != old) {
6914 status &= ~0xff;
6915 status |= (u8)vector;
6916 vmcs_write16(GUEST_INTR_STATUS, status);
6917 }
6918}
6919
6920static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6921{
6922 if (max_irr == -1)
6923 return;
6924
6925 vmx_set_rvi(max_irr);
6926}
6927
6928static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6929{
3d81bc7e
YZ		 6930 if (!vmx_vm_has_apicv(vcpu->kvm))
6931 return;
6932
c7c9c56c
YZ		 6933 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6934 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6935 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6936 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6937}
6938
51aa01d1 6939static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6940{
00eba012
AK		 6941 u32 exit_intr_info;
6942
6943 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6944 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6945 return;
6946
c5ca8e57 6947 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6948 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6949
6950 /* Handle machine checks before interrupts are enabled */
00eba012 6951 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6952 kvm_machine_check();
6953
20f65983 6954 /* We need to handle NMIs before interrupts are enabled */
00eba012 6955 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6956 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6957 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6958 asm("int $2");
ff9d07a0
ZY		 6959 kvm_after_handle_nmi(&vmx->vcpu);
6960 }
51aa01d1 6961}
20f65983 6962
a547c6db
YZ		 6963static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6964{
6965 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6966
6967 /*
6968 * If external interrupt exists, IF bit is set in rflags/eflags on the
6969 * interrupt stack frame, and interrupt will be enabled on a return
6970 * from interrupt handler.
6971 */
6972 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6973 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6974 unsigned int vector;
6975 unsigned long entry;
6976 gate_desc *desc;
6977 struct vcpu_vmx *vmx = to_vmx(vcpu);
6978#ifdef CONFIG_X86_64
6979 unsigned long tmp;
6980#endif
6981
6982 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6983 desc = (gate_desc *)vmx->host_idt_base + vector;
6984 entry = gate_offset(*desc);
6985 asm volatile(
6986#ifdef CONFIG_X86_64
6987 "mov %%" _ASM_SP ", %[sp]\n\t"
6988 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6989 "push $%c[ss]\n\t"
6990 "push %[sp]\n\t"
6991#endif
6992 "pushf\n\t"
6993 "orl $0x200, (%%" _ASM_SP ")\n\t"
6994 __ASM_SIZE(push) " $%c[cs]\n\t"
6995 "call *%[entry]\n\t"
6996 :
6997#ifdef CONFIG_X86_64
6998 [sp]"=&r"(tmp)
6999#endif
7000 :
7001 [entry]"r"(entry),
7002 [ss]"i"(__KERNEL_DS),
7003 [cs]"i"(__KERNEL_CS)
7004 );
7005 } else
7006 local_irq_enable();
7007}
7008
51aa01d1
AK		 7009static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7010{
c5ca8e57 7011 u32 exit_intr_info;
51aa01d1
AK		 7012 bool unblock_nmi;
7013 u8 vector;
7014 bool idtv_info_valid;
7015
7016 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7017
cf393f75 7018 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7019 if (vmx->nmi_known_unmasked)
7020 return;
c5ca8e57
AK		 7021 /*
7022 * Can't use vmx->exit_intr_info since we're not sure what
7023 * the exit reason is.
7024 */
7025 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7026 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7027 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7028 /*
7b4a25cb 7029 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7030 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7031 * a guest IRET fault.
7b4a25cb
GN		 7032 * SDM 3: 23.2.2 (September 2008)
7033 * Bit 12 is undefined in any of the following cases:
7034 * If the VM exit sets the valid bit in the IDT-vectoring
7035 * information field.
7036 * If the VM exit is due to a double fault.
cf393f75 7037 */
7b4a25cb
GN		 7038 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7039 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7040 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7041 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7042 else
7043 vmx->nmi_known_unmasked =
7044 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7045 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7046 } else if (unlikely(vmx->soft_vnmi_blocked))
7047 vmx->vnmi_blocked_time +=
7048 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7049}
7050
3ab66e8a 7051static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7052 u32 idt_vectoring_info,
7053 int instr_len_field,
7054 int error_code_field)
51aa01d1 7055{
51aa01d1
AK		 7056 u8 vector;
7057 int type;
7058 bool idtv_info_valid;
7059
7060 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7061
3ab66e8a
JK		 7062 vcpu->arch.nmi_injected = false;
7063 kvm_clear_exception_queue(vcpu);
7064 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7065
7066 if (!idtv_info_valid)
7067 return;
7068
3ab66e8a 7069 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7070
668f612f
AK		 7071 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7072 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7073
64a7ec06 7074 switch (type) {
37b96e98 7075 case INTR_TYPE_NMI_INTR:
3ab66e8a 7076 vcpu->arch.nmi_injected = true;
668f612f 7077 /*
7b4a25cb 7078 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7079 * Clear bit "block by NMI" before VM entry if a NMI
7080 * delivery faulted.
668f612f 7081 */
3ab66e8a 7082 vmx_set_nmi_mask(vcpu, false);
37b96e98 7083 break;
37b96e98 7084 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7085 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7086 /* fall through */
7087 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7088 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7089 u32 err = vmcs_read32(error_code_field);
851eb667 7090 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7091 } else
851eb667 7092 kvm_requeue_exception(vcpu, vector);
37b96e98 7093 break;
66fd3f7f 7094 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7095 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7096 /* fall through */
37b96e98 7097 case INTR_TYPE_EXT_INTR:
3ab66e8a 7098 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7099 break;
7100 default:
7101 break;
f7d9238f 7102 }
cf393f75
AK		 7103}
7104
83422e17
AK		 7105static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7106{
3ab66e8a 7107 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7108 VM_EXIT_INSTRUCTION_LEN,
7109 IDT_VECTORING_ERROR_CODE);
7110}
7111
b463a6f7
AK		 7112static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7113{
3ab66e8a 7114 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7115 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7116 VM_ENTRY_INSTRUCTION_LEN,
7117 VM_ENTRY_EXCEPTION_ERROR_CODE);
7118
7119 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7120}
7121
d7cd9796
GN		 7122static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7123{
7124 int i, nr_msrs;
7125 struct perf_guest_switch_msr *msrs;
7126
7127 msrs = perf_guest_get_msrs(&nr_msrs);
7128
7129 if (!msrs)
7130 return;
7131
7132 for (i = 0; i < nr_msrs; i++)
7133 if (msrs[i].host == msrs[i].guest)
7134 clear_atomic_switch_msr(vmx, msrs[i].msr);
7135 else
7136 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7137 msrs[i].host);
7138}
7139
a3b5ba49 7140static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7141{
a2fa3e9f 7142 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7143 unsigned long debugctlmsr;
104f226b
AK		 7144
7145 /* Record the guest's net vcpu time for enforced NMI injections. */
7146 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7147 vmx->entry_time = ktime_get();
7148
7149 /* Don't enter VMX if guest state is invalid, let the exit handler
7150 start emulation until we arrive back to a valid state */
14168786 7151 if (vmx->emulation_required)
104f226b
AK		 7152 return;
7153
012f83cb
AG		 7154 if (vmx->nested.sync_shadow_vmcs) {
7155 copy_vmcs12_to_shadow(vmx);
7156 vmx->nested.sync_shadow_vmcs = false;
7157 }
7158
104f226b
AK		 7159 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7160 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7161 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7162 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7163
7164 /* When single-stepping over STI and MOV SS, we must clear the
7165 * corresponding interruptibility bits in the guest state. Otherwise
7166 * vmentry fails as it then expects bit 14 (BS) in pending debug
7167 * exceptions being set, but that's not correct for the guest debugging
7168 * case. */
7169 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7170 vmx_set_interrupt_shadow(vcpu, 0);
7171
d7cd9796 7172 atomic_switch_perf_msrs(vmx);
2a7921b7 7173 debugctlmsr = get_debugctlmsr();
d7cd9796 7174
7854cbca
ACL		 7175 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7176 nested_adjust_preemption_timer(vcpu);
d462b819 7177 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7178 asm(
6aa8b732 7179 /* Store host registers */
b188c81f
AK		 7180 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7181 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7182 "push %%" _ASM_CX " \n\t"
7183 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7184 "je 1f \n\t"
b188c81f 7185 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7186 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7187 "1: \n\t"
d3edefc0 7188 /* Reload cr2 if changed */
b188c81f
AK		 7189 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7190 "mov %%cr2, %%" _ASM_DX " \n\t"
7191 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7192 "je 2f \n\t"
b188c81f 7193 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7194 "2: \n\t"
6aa8b732 7195 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7196 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7197 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7198 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7199 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7200 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7201 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7202 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7203 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7204#ifdef CONFIG_X86_64
e08aa78a
AK		 7205 "mov %c[r8](%0), %%r8 \n\t"
7206 "mov %c[r9](%0), %%r9 \n\t"
7207 "mov %c[r10](%0), %%r10 \n\t"
7208 "mov %c[r11](%0), %%r11 \n\t"
7209 "mov %c[r12](%0), %%r12 \n\t"
7210 "mov %c[r13](%0), %%r13 \n\t"
7211 "mov %c[r14](%0), %%r14 \n\t"
7212 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7213#endif
b188c81f 7214 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7215
6aa8b732 7216 /* Enter guest mode */
83287ea4 7217 "jne 1f \n\t"
4ecac3fd 7218 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7219 "jmp 2f \n\t"
7220 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7221 "2: "
6aa8b732 7222 /* Save guest registers, load host registers, keep flags */
b188c81f 7223 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7224 "pop %0 \n\t"
b188c81f
AK		 7225 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7226 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7227 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7228 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7229 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7230 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7231 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7232#ifdef CONFIG_X86_64
e08aa78a
AK		 7233 "mov %%r8, %c[r8](%0) \n\t"
7234 "mov %%r9, %c[r9](%0) \n\t"
7235 "mov %%r10, %c[r10](%0) \n\t"
7236 "mov %%r11, %c[r11](%0) \n\t"
7237 "mov %%r12, %c[r12](%0) \n\t"
7238 "mov %%r13, %c[r13](%0) \n\t"
7239 "mov %%r14, %c[r14](%0) \n\t"
7240 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7241#endif
b188c81f
AK		 7242 "mov %%cr2, %%" _ASM_AX " \n\t"
7243 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7244
b188c81f 7245 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7246 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7247 ".pushsection .rodata \n\t"
7248 ".global vmx_return \n\t"
7249 "vmx_return: " _ASM_PTR " 2b \n\t"
7250 ".popsection"
e08aa78a 7251 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7252 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7253 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7254 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7255 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7256 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7257 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7258 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7259 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7260 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7261 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7262#ifdef CONFIG_X86_64
ad312c7c
ZX		 7263 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7264 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7265 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7266 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7267 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7268 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7269 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7270 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7271#endif
40712fae
AK		 7272 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7273 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7274 : "cc", "memory"
7275#ifdef CONFIG_X86_64
b188c81f 7276 , "rax", "rbx", "rdi", "rsi"
c2036300 7277 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7278#else
7279 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7280#endif
7281 );
6aa8b732 7282
2a7921b7
GN		 7283 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7284 if (debugctlmsr)
7285 update_debugctlmsr(debugctlmsr);
7286
aa67f609
AK		 7287#ifndef CONFIG_X86_64
7288 /*
7289 * The sysexit path does not restore ds/es, so we must set them to
7290 * a reasonable value ourselves.
7291 *
7292 * We can't defer this to vmx_load_host_state() since that function
7293 * may be executed in interrupt context, which saves and restore segments
7294 * around it, nullifying its effect.
7295 */
7296 loadsegment(ds, __USER_DS);
7297 loadsegment(es, __USER_DS);
7298#endif
7299
6de4f3ad 7300 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7301 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7302 | (1 << VCPU_EXREG_CPL)
aff48baa 7303 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7304 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7305 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7306 vcpu->arch.regs_dirty = 0;
7307
1155f76a
AK		 7308 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7309
d462b819 7310 vmx->loaded_vmcs->launched = 1;
1b6269db 7311
51aa01d1 7312 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7313 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7314
e0b890d3
GN		 7315 /*
7316 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7317 * we did not inject a still-pending event to L1 now because of
7318 * nested_run_pending, we need to re-enable this bit.
7319 */
7320 if (vmx->nested.nested_run_pending)
7321 kvm_make_request(KVM_REQ_EVENT, vcpu);
7322
7323 vmx->nested.nested_run_pending = 0;
7324
51aa01d1
AK		 7325 vmx_complete_atomic_exit(vmx);
7326 vmx_recover_nmi_blocking(vmx);
cf393f75 7327 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7328}
7329
6aa8b732
AK		 7330static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7331{
fb3f0f51
RR		 7332 struct vcpu_vmx *vmx = to_vmx(vcpu);
7333
cdbecfc3 7334 free_vpid(vmx);
ec378aee 7335 free_nested(vmx);
d462b819 7336 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7337 kfree(vmx->guest_msrs);
7338 kvm_vcpu_uninit(vcpu);
a4770347 7339 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7340}
7341
fb3f0f51 7342static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7343{
fb3f0f51 7344 int err;
c16f862d 7345 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7346 int cpu;
6aa8b732 7347
a2fa3e9f 7348 if (!vmx)
fb3f0f51
RR		 7349 return ERR_PTR(-ENOMEM);
7350
2384d2b3
SY		 7351 allocate_vpid(vmx);
7352
fb3f0f51
RR		 7353 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7354 if (err)
7355 goto free_vcpu;
965b58a5 7356
a2fa3e9f 7357 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7358 err = -ENOMEM;
fb3f0f51 7359 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7360 goto uninit_vcpu;
7361 }
965b58a5 7362
d462b819
NHE		 7363 vmx->loaded_vmcs = &vmx->vmcs01;
7364 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7365 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7366 goto free_msrs;
d462b819
NHE		 7367 if (!vmm_exclusive)
7368 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7369 loaded_vmcs_init(vmx->loaded_vmcs);
7370 if (!vmm_exclusive)
7371 kvm_cpu_vmxoff();
a2fa3e9f 7372
15ad7146
AK		 7373 cpu = get_cpu();
7374 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7375 vmx->vcpu.cpu = cpu;
8b9cf98c 7376 err = vmx_vcpu_setup(vmx);
fb3f0f51 7377 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7378 put_cpu();
fb3f0f51
RR		 7379 if (err)
7380 goto free_vmcs;
a63cb560 7381 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7382 err = alloc_apic_access_page(kvm);
7383 if (err)
5e4a0b3c 7384 goto free_vmcs;
a63cb560 7385 }
fb3f0f51 7386
b927a3ce
SY		 7387 if (enable_ept) {
7388 if (!kvm->arch.ept_identity_map_addr)
7389 kvm->arch.ept_identity_map_addr =
7390 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7391 err = -ENOMEM;
b7ebfb05
SY		 7392 if (alloc_identity_pagetable(kvm) != 0)
7393 goto free_vmcs;
93ea5388
GN		 7394 if (!init_rmode_identity_map(kvm))
7395 goto free_vmcs;
b927a3ce 7396 }
b7ebfb05 7397
a9d30f33
NHE		 7398 vmx->nested.current_vmptr = -1ull;
7399 vmx->nested.current_vmcs12 = NULL;
7400
fb3f0f51
RR		 7401 return &vmx->vcpu;
7402
7403free_vmcs:
5f3fbc34 7404 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7405free_msrs:
fb3f0f51
RR		 7406 kfree(vmx->guest_msrs);
7407uninit_vcpu:
7408 kvm_vcpu_uninit(&vmx->vcpu);
7409free_vcpu:
cdbecfc3 7410 free_vpid(vmx);
a4770347 7411 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7412 return ERR_PTR(err);
6aa8b732
AK		 7413}
7414
002c7f7c
YS		 7415static void __init vmx_check_processor_compat(void *rtn)
7416{
7417 struct vmcs_config vmcs_conf;
7418
7419 *(int *)rtn = 0;
7420 if (setup_vmcs_config(&vmcs_conf) < 0)
7421 *(int *)rtn = -EIO;
7422 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7423 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7424 smp_processor_id());
7425 *(int *)rtn = -EIO;
7426 }
7427}
7428
67253af5
SY		 7429static int get_ept_level(void)
7430{
7431 return VMX_EPT_DEFAULT_GAW + 1;
7432}
7433
4b12f0de 7434static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7435{
4b12f0de
SY		 7436 u64 ret;
7437
522c68c4
SY		 7438 /* For VT-d and EPT combination
7439 * 1. MMIO: always map as UC
7440 * 2. EPT with VT-d:
7441 * a. VT-d without snooping control feature: can't guarantee the
7442 * result, try to trust guest.
7443 * b. VT-d with snooping control feature: snooping control feature of
7444 * VT-d engine can guarantee the cache correctness. Just set it
7445 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7446 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7447 * consistent with host MTRR
7448 */
4b12f0de
SY		 7449 if (is_mmio)
7450 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7451 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7452 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7453 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7454 else
522c68c4 7455 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7456 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7457
7458 return ret;
64d4d521
SY		 7459}
7460
17cc3935 7461static int vmx_get_lpage_level(void)
344f414f 7462{
878403b7
SY		 7463 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7464 return PT_DIRECTORY_LEVEL;
7465 else
7466 /* For shadow and EPT supported 1GB page */
7467 return PT_PDPE_LEVEL;
344f414f
JR		 7468}
7469
0e851880
SY		 7470static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7471{
4e47c7a6
SY		 7472 struct kvm_cpuid_entry2 *best;
7473 struct vcpu_vmx *vmx = to_vmx(vcpu);
7474 u32 exec_control;
7475
7476 vmx->rdtscp_enabled = false;
7477 if (vmx_rdtscp_supported()) {
7478 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7479 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7480 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7481 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7482 vmx->rdtscp_enabled = true;
7483 else {
7484 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7485 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7486 exec_control);
7487 }
7488 }
7489 }
ad756a16 7490
ad756a16
MJ		 7491 /* Exposing INVPCID only when PCID is exposed */
7492 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7493 if (vmx_invpcid_supported() &&
4f977045 7494 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7495 guest_cpuid_has_pcid(vcpu)) {
29282fde 7496 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7497 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7498 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7499 exec_control);
7500 } else {
29282fde
TI		 7501 if (cpu_has_secondary_exec_ctrls()) {
7502 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7503 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7504 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7505 exec_control);
7506 }
ad756a16 7507 if (best)
4f977045 7508 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7509 }
0e851880
SY		 7510}
7511
d4330ef2
JR		 7512static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7513{
7b8050f5
NHE		 7514 if (func == 1 && nested)
7515 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7516}
7517
25d92081
YZ		 7518static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7519 struct x86_exception *fault)
7520{
7521 struct vmcs12 *vmcs12;
7522 nested_vmx_vmexit(vcpu);
7523 vmcs12 = get_vmcs12(vcpu);
7524
7525 if (fault->error_code & PFERR_RSVD_MASK)
7526 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7527 else
7528 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7529 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7530 vmcs12->guest_physical_address = fault->address;
7531}
7532
155a97a3
NHE		 7533/* Callbacks for nested_ept_init_mmu_context: */
7534
7535static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7536{
7537 /* return the page table to be shadowed - in our case, EPT12 */
7538 return get_vmcs12(vcpu)->ept_pointer;
7539}
7540
8a3c1a33 7541static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7542{
8a3c1a33 7543 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7544 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7545
7546 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7547 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7548 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7549
7550 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7551}
7552
7553static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7554{
7555 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7556}
7557
feaf0c7d
GN		 7558static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7559 struct x86_exception *fault)
7560{
7561 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7562
7563 WARN_ON(!is_guest_mode(vcpu));
7564
7565 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7566 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7567 nested_vmx_vmexit(vcpu);
7568 else
7569 kvm_inject_page_fault(vcpu, fault);
7570}
7571
fe3ef05c
NHE		 7572/*
7573 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7574 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7575 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7576 * guest in a way that will both be appropriate to L1's requests, and our
7577 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7578 * function also has additional necessary side-effects, like setting various
7579 * vcpu->arch fields.
7580 */
7581static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7582{
7583 struct vcpu_vmx *vmx = to_vmx(vcpu);
7584 u32 exec_control;
7854cbca 7585 u32 exit_control;
fe3ef05c
NHE		 7586
7587 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7588 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7589 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7590 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7591 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7592 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7593 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7594 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7595 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7596 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7597 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7598 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7599 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7600 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7601 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7602 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7603 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7604 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7605 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7606 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7607 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7608 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7609 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7610 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7611 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7612 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7613 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7614 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7615 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7616 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7617 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7618 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7619 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7620 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7621 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7622 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7623
7624 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7625 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7626 vmcs12->vm_entry_intr_info_field);
7627 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7628 vmcs12->vm_entry_exception_error_code);
7629 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7630 vmcs12->vm_entry_instruction_len);
7631 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7632 vmcs12->guest_interruptibility_info);
fe3ef05c 7633 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7634 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7635 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7636 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7637 vmcs12->guest_pending_dbg_exceptions);
7638 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7639 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7640
7641 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7642
7643 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7644 (vmcs_config.pin_based_exec_ctrl |
7645 vmcs12->pin_based_vm_exec_control));
7646
0238ea91
JK		 7647 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7648 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7649 vmcs12->vmx_preemption_timer_value);
7650
fe3ef05c
NHE		 7651 /*
7652 * Whether page-faults are trapped is determined by a combination of
7653 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7654 * If enable_ept, L0 doesn't care about page faults and we should
7655 * set all of these to L1's desires. However, if !enable_ept, L0 does
7656 * care about (at least some) page faults, and because it is not easy
7657 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7658 * to exit on each and every L2 page fault. This is done by setting
7659 * MASK=MATCH=0 and (see below) EB.PF=1.
7660 * Note that below we don't need special code to set EB.PF beyond the
7661 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7662 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7663 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7664 *
7665 * A problem with this approach (when !enable_ept) is that L1 may be
7666 * injected with more page faults than it asked for. This could have
7667 * caused problems, but in practice existing hypervisors don't care.
7668 * To fix this, we will need to emulate the PFEC checking (on the L1
7669 * page tables), using walk_addr(), when injecting PFs to L1.
7670 */
7671 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7672 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7673 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7674 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7675
7676 if (cpu_has_secondary_exec_ctrls()) {
7677 u32 exec_control = vmx_secondary_exec_control(vmx);
7678 if (!vmx->rdtscp_enabled)
7679 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7680 /* Take the following fields only from vmcs12 */
7681 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7682 if (nested_cpu_has(vmcs12,
7683 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7684 exec_control |= vmcs12->secondary_vm_exec_control;
7685
7686 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7687 /*
7688 * Translate L1 physical address to host physical
7689 * address for vmcs02. Keep the page pinned, so this
7690 * physical address remains valid. We keep a reference
7691 * to it so we can release it later.
7692 */
7693 if (vmx->nested.apic_access_page) /* shouldn't happen */
7694 nested_release_page(vmx->nested.apic_access_page);
7695 vmx->nested.apic_access_page =
7696 nested_get_page(vcpu, vmcs12->apic_access_addr);
7697 /*
7698 * If translation failed, no matter: This feature asks
7699 * to exit when accessing the given address, and if it
7700 * can never be accessed, this feature won't do
7701 * anything anyway.
7702 */
7703 if (!vmx->nested.apic_access_page)
7704 exec_control &=
7705 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7706 else
7707 vmcs_write64(APIC_ACCESS_ADDR,
7708 page_to_phys(vmx->nested.apic_access_page));
7709 }
7710
7711 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7712 }
7713
7714
7715 /*
7716 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7717 * Some constant fields are set here by vmx_set_constant_host_state().
7718 * Other fields are different per CPU, and will be set later when
7719 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7720 */
a547c6db 7721 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7722
7723 /*
7724 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7725 * entry, but only if the current (host) sp changed from the value
7726 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7727 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7728 * here we just force the write to happen on entry.
7729 */
7730 vmx->host_rsp = 0;
7731
7732 exec_control = vmx_exec_control(vmx); /* L0's desires */
7733 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7734 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7735 exec_control &= ~CPU_BASED_TPR_SHADOW;
7736 exec_control |= vmcs12->cpu_based_vm_exec_control;
7737 /*
7738 * Merging of IO and MSR bitmaps not currently supported.
7739 * Rather, exit every time.
7740 */
7741 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7742 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7743 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7744
7745 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7746
7747 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7748 * bitwise-or of what L1 wants to trap for L2, and what we want to
7749 * trap. Note that CR0.TS also needs updating - we do this later.
7750 */
7751 update_exception_bitmap(vcpu);
7752 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7753 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7754
8049d651
NHE		 7755 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7756 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7757 * bits are further modified by vmx_set_efer() below.
7758 */
7854cbca
ACL		 7759 exit_control = vmcs_config.vmexit_ctrl;
7760 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7761 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
7762 vmcs_write32(VM_EXIT_CONTROLS, exit_control);
8049d651
NHE		 7763
7764 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7765 * emulated by vmx_set_efer(), below.
7766 */
7767 vmcs_write32(VM_ENTRY_CONTROLS,
7768 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7769 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7770 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7771
44811c02 7772 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7773 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7774 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7775 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7776 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7777
7778
7779 set_cr4_guest_host_mask(vmx);
7780
27fc51b2
NHE		 7781 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7782 vmcs_write64(TSC_OFFSET,
7783 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7784 else
7785 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7786
7787 if (enable_vpid) {
7788 /*
7789 * Trivially support vpid by letting L2s share their parent
7790 * L1's vpid. TODO: move to a more elaborate solution, giving
7791 * each L2 its own vpid and exposing the vpid feature to L1.
7792 */
7793 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7794 vmx_flush_tlb(vcpu);
7795 }
7796
155a97a3
NHE		 7797 if (nested_cpu_has_ept(vmcs12)) {
7798 kvm_mmu_unload(vcpu);
7799 nested_ept_init_mmu_context(vcpu);
7800 }
7801
fe3ef05c
NHE		 7802 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7803 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7804 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7805 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7806 else
7807 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7808 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7809 vmx_set_efer(vcpu, vcpu->arch.efer);
7810
7811 /*
7812 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7813 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7814 * The CR0_READ_SHADOW is what L2 should have expected to read given
7815 * the specifications by L1; It's not enough to take
7816 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7817 * have more bits than L1 expected.
7818 */
7819 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7820 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7821
7822 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7823 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7824
7825 /* shadow page tables on either EPT or shadow page tables */
7826 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7827 kvm_mmu_reset_context(vcpu);
7828
feaf0c7d
GN		 7829 if (!enable_ept)
7830 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7831
3633cfc3
NHE		 7832 /*
7833 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7834 */
7835 if (enable_ept) {
7836 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7837 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7838 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7839 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7840 }
7841
fe3ef05c
NHE		 7842 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7843 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7844}
7845
cd232ad0
NHE		 7846/*
7847 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7848 * for running an L2 nested guest.
7849 */
7850static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7851{
7852 struct vmcs12 *vmcs12;
7853 struct vcpu_vmx *vmx = to_vmx(vcpu);
7854 int cpu;
7855 struct loaded_vmcs *vmcs02;
384bb783 7856 bool ia32e;
cd232ad0
NHE		 7857
7858 if (!nested_vmx_check_permission(vcpu) ||
7859 !nested_vmx_check_vmcs12(vcpu))
7860 return 1;
7861
7862 skip_emulated_instruction(vcpu);
7863 vmcs12 = get_vmcs12(vcpu);
7864
012f83cb
AG		 7865 if (enable_shadow_vmcs)
7866 copy_shadow_to_vmcs12(vmx);
7867
7c177938
NHE		 7868 /*
7869 * The nested entry process starts with enforcing various prerequisites
7870 * on vmcs12 as required by the Intel SDM, and act appropriately when
7871 * they fail: As the SDM explains, some conditions should cause the
7872 * instruction to fail, while others will cause the instruction to seem
7873 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7874 * To speed up the normal (success) code path, we should avoid checking
7875 * for misconfigurations which will anyway be caught by the processor
7876 * when using the merged vmcs02.
7877 */
7878 if (vmcs12->launch_state == launch) {
7879 nested_vmx_failValid(vcpu,
7880 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7881 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7882 return 1;
7883 }
7884
26539bd0
PB		 7885 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7886 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7887 return 1;
7888 }
7889
7c177938
NHE		 7890 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7891 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7892 /*TODO: Also verify bits beyond physical address width are 0*/
7893 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7894 return 1;
7895 }
7896
7897 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7898 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7899 /*TODO: Also verify bits beyond physical address width are 0*/
7900 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7901 return 1;
7902 }
7903
7904 if (vmcs12->vm_entry_msr_load_count > 0 ||
7905 vmcs12->vm_exit_msr_load_count > 0 ||
7906 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7907 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7908 __func__);
7c177938
NHE		 7909 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7910 return 1;
7911 }
7912
7913 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7914 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7915 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7916 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7917 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7918 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7919 !vmx_control_verify(vmcs12->vm_exit_controls,
7920 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7921 !vmx_control_verify(vmcs12->vm_entry_controls,
7922 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7923 {
7924 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7925 return 1;
7926 }
7927
7928 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7929 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7930 nested_vmx_failValid(vcpu,
7931 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7932 return 1;
7933 }
7934
92fbc7b1 7935 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7936 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7937 nested_vmx_entry_failure(vcpu, vmcs12,
7938 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7939 return 1;
7940 }
7941 if (vmcs12->vmcs_link_pointer != -1ull) {
7942 nested_vmx_entry_failure(vcpu, vmcs12,
7943 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7944 return 1;
7945 }
7946
384bb783 7947 /*
cb0c8cda 7948 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7949 * are performed on the field for the IA32_EFER MSR:
7950 * - Bits reserved in the IA32_EFER MSR must be 0.
7951 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7952 * the IA-32e mode guest VM-exit control. It must also be identical
7953 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7954 * CR0.PG) is 1.
7955 */
7956 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7957 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7958 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7959 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7960 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7961 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7962 nested_vmx_entry_failure(vcpu, vmcs12,
7963 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7964 return 1;
7965 }
7966 }
7967
7968 /*
7969 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7970 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7971 * the values of the LMA and LME bits in the field must each be that of
7972 * the host address-space size VM-exit control.
7973 */
7974 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7975 ia32e = (vmcs12->vm_exit_controls &
7976 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7977 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7978 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7979 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7980 nested_vmx_entry_failure(vcpu, vmcs12,
7981 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7982 return 1;
7983 }
7984 }
7985
7c177938
NHE		 7986 /*
7987 * We're finally done with prerequisite checking, and can start with
7988 * the nested entry.
7989 */
7990
cd232ad0
NHE		 7991 vmcs02 = nested_get_current_vmcs02(vmx);
7992 if (!vmcs02)
7993 return -ENOMEM;
7994
7995 enter_guest_mode(vcpu);
7996
e0b890d3
GN		 7997 vmx->nested.nested_run_pending = 1;
7998
cd232ad0
NHE		 7999 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8000
8001 cpu = get_cpu();
8002 vmx->loaded_vmcs = vmcs02;
8003 vmx_vcpu_put(vcpu);
8004 vmx_vcpu_load(vcpu, cpu);
8005 vcpu->cpu = cpu;
8006 put_cpu();
8007
36c3cc42
JK		 8008 vmx_segment_cache_clear(vmx);
8009
cd232ad0
NHE		 8010 vmcs12->launch_state = 1;
8011
8012 prepare_vmcs02(vcpu, vmcs12);
8013
8014 /*
8015 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8016 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8017 * returned as far as L1 is concerned. It will only return (and set
8018 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8019 */
8020 return 1;
8021}
8022
4704d0be
NHE		 8023/*
8024 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8025 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8026 * This function returns the new value we should put in vmcs12.guest_cr0.
8027 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8028 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8029 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8030 * didn't trap the bit, because if L1 did, so would L0).
8031 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8032 * been modified by L2, and L1 knows it. So just leave the old value of
8033 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8034 * isn't relevant, because if L0 traps this bit it can set it to anything.
8035 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8036 * changed these bits, and therefore they need to be updated, but L0
8037 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8038 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8039 */
8040static inline unsigned long
8041vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8042{
8043 return
8044 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8045 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8046 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8047 vcpu->arch.cr0_guest_owned_bits));
8048}
8049
8050static inline unsigned long
8051vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8052{
8053 return
8054 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8055 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8056 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8057 vcpu->arch.cr4_guest_owned_bits));
8058}
8059
5f3d5799
JK		 8060static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8061 struct vmcs12 *vmcs12)
8062{
8063 u32 idt_vectoring;
8064 unsigned int nr;
8065
851eb667 8066 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8067 nr = vcpu->arch.exception.nr;
8068 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8069
8070 if (kvm_exception_is_soft(nr)) {
8071 vmcs12->vm_exit_instruction_len =
8072 vcpu->arch.event_exit_inst_len;
8073 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8074 } else
8075 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8076
8077 if (vcpu->arch.exception.has_error_code) {
8078 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8079 vmcs12->idt_vectoring_error_code =
8080 vcpu->arch.exception.error_code;
8081 }
8082
8083 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8084 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8085 vmcs12->idt_vectoring_info_field =
8086 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8087 } else if (vcpu->arch.interrupt.pending) {
8088 nr = vcpu->arch.interrupt.nr;
8089 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8090
8091 if (vcpu->arch.interrupt.soft) {
8092 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8093 vmcs12->vm_entry_instruction_len =
8094 vcpu->arch.event_exit_inst_len;
8095 } else
8096 idt_vectoring |= INTR_TYPE_EXT_INTR;
8097
8098 vmcs12->idt_vectoring_info_field = idt_vectoring;
8099 }
8100}
8101
4704d0be
NHE		 8102/*
8103 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8104 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8105 * and this function updates it to reflect the changes to the guest state while
8106 * L2 was running (and perhaps made some exits which were handled directly by L0
8107 * without going back to L1), and to reflect the exit reason.
8108 * Note that we do not have to copy here all VMCS fields, just those that
8109 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8110 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8111 * which already writes to vmcs12 directly.
8112 */
733568f9 8113static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8114{
8115 /* update guest state fields: */
8116 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8117 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8118
8119 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8120 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8121 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8122 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8123
8124 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8125 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8126 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8127 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8128 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8129 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8130 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8131 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8132 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8133 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8134 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8135 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8136 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8137 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8138 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8139 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8140 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8141 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8142 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8143 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8144 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8145 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8146 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8147 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8148 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8149 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8150 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8151 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8152 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8153 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8154 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8155 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8156 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8157 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8158 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8159 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8160
4704d0be
NHE		 8161 vmcs12->guest_interruptibility_info =
8162 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8163 vmcs12->guest_pending_dbg_exceptions =
8164 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8165
7854cbca
ACL		 8166 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8167 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8168 vmcs12->vmx_preemption_timer_value =
8169 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8170
3633cfc3
NHE		 8171 /*
8172 * In some cases (usually, nested EPT), L2 is allowed to change its
8173 * own CR3 without exiting. If it has changed it, we must keep it.
8174 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8175 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8176 *
8177 * Additionally, restore L2's PDPTR to vmcs12.
8178 */
8179 if (enable_ept) {
8180 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8181 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8182 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8183 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8184 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8185 }
8186
c18911a2
JK		 8187 vmcs12->vm_entry_controls =
8188 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8189 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8190
4704d0be
NHE		 8191 /* TODO: These cannot have changed unless we have MSR bitmaps and
8192 * the relevant bit asks not to trap the change */
8193 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8194 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8195 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8196 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8197 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8198 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8199 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8200 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8201
8202 /* update exit information fields: */
8203
957c897e 8204 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8205 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8206
8207 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8208 if ((vmcs12->vm_exit_intr_info &
8209 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8210 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8211 vmcs12->vm_exit_intr_error_code =
8212 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8213 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8214 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8215 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8216
5f3d5799
JK		 8217 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8218 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8219 * instead of reading the real value. */
4704d0be 8220 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8221
8222 /*
8223 * Transfer the event that L0 or L1 may wanted to inject into
8224 * L2 to IDT_VECTORING_INFO_FIELD.
8225 */
8226 vmcs12_save_pending_event(vcpu, vmcs12);
8227 }
8228
8229 /*
8230 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8231 * preserved above and would only end up incorrectly in L1.
8232 */
8233 vcpu->arch.nmi_injected = false;
8234 kvm_clear_exception_queue(vcpu);
8235 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8236}
8237
8238/*
8239 * A part of what we need to when the nested L2 guest exits and we want to
8240 * run its L1 parent, is to reset L1's guest state to the host state specified
8241 * in vmcs12.
8242 * This function is to be called not only on normal nested exit, but also on
8243 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8244 * Failures During or After Loading Guest State").
8245 * This function should be called when the active VMCS is L1's (vmcs01).
8246 */
733568f9
JK		 8247static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8248 struct vmcs12 *vmcs12)
4704d0be 8249{
21feb4eb
ACL		 8250 struct kvm_segment seg;
8251
4704d0be
NHE		 8252 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8253 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8254 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8255 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8256 else
8257 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8258 vmx_set_efer(vcpu, vcpu->arch.efer);
8259
8260 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8261 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8262 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8263 /*
8264 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8265 * actually changed, because it depends on the current state of
8266 * fpu_active (which may have changed).
8267 * Note that vmx_set_cr0 refers to efer set above.
8268 */
9e3e4dbf 8269 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8270 /*
8271 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8272 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8273 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8274 */
8275 update_exception_bitmap(vcpu);
8276 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8277 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8278
8279 /*
8280 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8281 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8282 */
8283 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8284 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8285
155a97a3
NHE		 8286 if (nested_cpu_has_ept(vmcs12))
8287 nested_ept_uninit_mmu_context(vcpu);
8288
4704d0be
NHE		 8289 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8290 kvm_mmu_reset_context(vcpu);
8291
feaf0c7d
GN		 8292 if (!enable_ept)
8293 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8294
4704d0be
NHE		 8295 if (enable_vpid) {
8296 /*
8297 * Trivially support vpid by letting L2s share their parent
8298 * L1's vpid. TODO: move to a more elaborate solution, giving
8299 * each L2 its own vpid and exposing the vpid feature to L1.
8300 */
8301 vmx_flush_tlb(vcpu);
8302 }
8303
8304
8305 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8306 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8307 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8308 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8309 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8310
44811c02 8311 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8312 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8313 vcpu->arch.pat = vmcs12->host_ia32_pat;
8314 }
4704d0be
NHE		 8315 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8316 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8317 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8318
21feb4eb
ACL		 8319 /* Set L1 segment info according to Intel SDM
8320 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8321 seg = (struct kvm_segment) {
8322 .base = 0,
8323 .limit = 0xFFFFFFFF,
8324 .selector = vmcs12->host_cs_selector,
8325 .type = 11,
8326 .present = 1,
8327 .s = 1,
8328 .g = 1
8329 };
8330 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8331 seg.l = 1;
8332 else
8333 seg.db = 1;
8334 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8335 seg = (struct kvm_segment) {
8336 .base = 0,
8337 .limit = 0xFFFFFFFF,
8338 .type = 3,
8339 .present = 1,
8340 .s = 1,
8341 .db = 1,
8342 .g = 1
8343 };
8344 seg.selector = vmcs12->host_ds_selector;
8345 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8346 seg.selector = vmcs12->host_es_selector;
8347 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8348 seg.selector = vmcs12->host_ss_selector;
8349 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8350 seg.selector = vmcs12->host_fs_selector;
8351 seg.base = vmcs12->host_fs_base;
8352 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8353 seg.selector = vmcs12->host_gs_selector;
8354 seg.base = vmcs12->host_gs_base;
8355 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8356 seg = (struct kvm_segment) {
205befd9 8357 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8358 .limit = 0x67,
8359 .selector = vmcs12->host_tr_selector,
8360 .type = 11,
8361 .present = 1
8362 };
8363 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8364
503cd0c5
JK		 8365 kvm_set_dr(vcpu, 7, 0x400);
8366 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8367}
8368
8369/*
8370 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8371 * and modify vmcs12 to make it see what it would expect to see there if
8372 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8373 */
8374static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8375{
8376 struct vcpu_vmx *vmx = to_vmx(vcpu);
8377 int cpu;
8378 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8379
5f3d5799
JK		 8380 /* trying to cancel vmlaunch/vmresume is a bug */
8381 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8382
4704d0be
NHE		 8383 leave_guest_mode(vcpu);
8384 prepare_vmcs12(vcpu, vmcs12);
8385
8386 cpu = get_cpu();
8387 vmx->loaded_vmcs = &vmx->vmcs01;
8388 vmx_vcpu_put(vcpu);
8389 vmx_vcpu_load(vcpu, cpu);
8390 vcpu->cpu = cpu;
8391 put_cpu();
8392
36c3cc42
JK		 8393 vmx_segment_cache_clear(vmx);
8394
4704d0be
NHE		 8395 /* if no vmcs02 cache requested, remove the one we used */
8396 if (VMCS02_POOL_SIZE == 0)
8397 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8398
8399 load_vmcs12_host_state(vcpu, vmcs12);
8400
27fc51b2 8401 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8402 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8403
8404 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8405 vmx->host_rsp = 0;
8406
8407 /* Unpin physical memory we referred to in vmcs02 */
8408 if (vmx->nested.apic_access_page) {
8409 nested_release_page(vmx->nested.apic_access_page);
8410 vmx->nested.apic_access_page = 0;
8411 }
8412
8413 /*
8414 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8415 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8416 * success or failure flag accordingly.
8417 */
8418 if (unlikely(vmx->fail)) {
8419 vmx->fail = 0;
8420 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8421 } else
8422 nested_vmx_succeed(vcpu);
012f83cb
AG		 8423 if (enable_shadow_vmcs)
8424 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8425}
8426
7c177938
NHE		 8427/*
8428 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8429 * 23.7 "VM-entry failures during or after loading guest state" (this also
8430 * lists the acceptable exit-reason and exit-qualification parameters).
8431 * It should only be called before L2 actually succeeded to run, and when
8432 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8433 */
8434static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8435 struct vmcs12 *vmcs12,
8436 u32 reason, unsigned long qualification)
8437{
8438 load_vmcs12_host_state(vcpu, vmcs12);
8439 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8440 vmcs12->exit_qualification = qualification;
8441 nested_vmx_succeed(vcpu);
012f83cb
AG		 8442 if (enable_shadow_vmcs)
8443 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8444}
8445
8a76d7f2
JR		 8446static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8447 struct x86_instruction_info *info,
8448 enum x86_intercept_stage stage)
8449{
8450 return X86EMUL_CONTINUE;
8451}
8452
cbdd1bea 8453static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8454 .cpu_has_kvm_support = cpu_has_kvm_support,
8455 .disabled_by_bios = vmx_disabled_by_bios,
8456 .hardware_setup = hardware_setup,
8457 .hardware_unsetup = hardware_unsetup,
002c7f7c 8458 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8459 .hardware_enable = hardware_enable,
8460 .hardware_disable = hardware_disable,
04547156 8461 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8462
8463 .vcpu_create = vmx_create_vcpu,
8464 .vcpu_free = vmx_free_vcpu,
04d2cc77 8465 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8466
04d2cc77 8467 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8468 .vcpu_load = vmx_vcpu_load,
8469 .vcpu_put = vmx_vcpu_put,
8470
c8639010 8471 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8472 .get_msr = vmx_get_msr,
8473 .set_msr = vmx_set_msr,
8474 .get_segment_base = vmx_get_segment_base,
8475 .get_segment = vmx_get_segment,
8476 .set_segment = vmx_set_segment,
2e4d2653 8477 .get_cpl = vmx_get_cpl,
6aa8b732 8478 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8479 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8480 .decache_cr3 = vmx_decache_cr3,
25c4c276 8481 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8482 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8483 .set_cr3 = vmx_set_cr3,
8484 .set_cr4 = vmx_set_cr4,
6aa8b732 8485 .set_efer = vmx_set_efer,
6aa8b732
AK		 8486 .get_idt = vmx_get_idt,
8487 .set_idt = vmx_set_idt,
8488 .get_gdt = vmx_get_gdt,
8489 .set_gdt = vmx_set_gdt,
020df079 8490 .set_dr7 = vmx_set_dr7,
5fdbf976 8491 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8492 .get_rflags = vmx_get_rflags,
8493 .set_rflags = vmx_set_rflags,
ebcbab4c 8494 .fpu_activate = vmx_fpu_activate,
02daab21 8495 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8496
8497 .tlb_flush = vmx_flush_tlb,
6aa8b732 8498
6aa8b732 8499 .run = vmx_vcpu_run,
6062d012 8500 .handle_exit = vmx_handle_exit,
6aa8b732 8501 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8502 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8503 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8504 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8505 .set_irq = vmx_inject_irq,
95ba8273 8506 .set_nmi = vmx_inject_nmi,
298101da 8507 .queue_exception = vmx_queue_exception,
b463a6f7 8508 .cancel_injection = vmx_cancel_injection,
78646121 8509 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8510 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8511 .get_nmi_mask = vmx_get_nmi_mask,
8512 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8513 .enable_nmi_window = enable_nmi_window,
8514 .enable_irq_window = enable_irq_window,
8515 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8516 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8517 .vm_has_apicv = vmx_vm_has_apicv,
8518 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8519 .hwapic_irr_update = vmx_hwapic_irr_update,
8520 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8521 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8522 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8523
cbc94022 8524 .set_tss_addr = vmx_set_tss_addr,
67253af5 8525 .get_tdp_level = get_ept_level,
4b12f0de 8526 .get_mt_mask = vmx_get_mt_mask,
229456fc 8527
586f9607 8528 .get_exit_info = vmx_get_exit_info,
586f9607 8529
17cc3935 8530 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8531
8532 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8533
8534 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8535 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8536
8537 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8538
8539 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8540
4051b188 8541 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8542 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8543 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8544 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8545 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8546 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8547
8548 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8549
8550 .check_intercept = vmx_check_intercept,
a547c6db 8551 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8552};
8553
8554static int __init vmx_init(void)
8555{
8d14695f 8556 int r, i, msr;
26bb0981
AK		 8557
8558 rdmsrl_safe(MSR_EFER, &host_efer);
8559
8560 for (i = 0; i < NR_VMX_MSR; ++i)
8561 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8562
3e7c73e9 8563 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8564 if (!vmx_io_bitmap_a)
8565 return -ENOMEM;
8566
2106a548
GC		 8567 r = -ENOMEM;
8568
3e7c73e9 8569 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8570 if (!vmx_io_bitmap_b)
fdef3ad1 8571 goto out;
fdef3ad1 8572
5897297b 8573 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8574 if (!vmx_msr_bitmap_legacy)
25c5f225 8575 goto out1;
2106a548 8576
8d14695f
YZ		 8577 vmx_msr_bitmap_legacy_x2apic =
8578 (unsigned long *)__get_free_page(GFP_KERNEL);
8579 if (!vmx_msr_bitmap_legacy_x2apic)
8580 goto out2;
25c5f225 8581
5897297b 8582 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8583 if (!vmx_msr_bitmap_longmode)
8d14695f 8584 goto out3;
2106a548 8585
8d14695f
YZ		 8586 vmx_msr_bitmap_longmode_x2apic =
8587 (unsigned long *)__get_free_page(GFP_KERNEL);
8588 if (!vmx_msr_bitmap_longmode_x2apic)
8589 goto out4;
4607c2d7
AG		 8590 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8591 if (!vmx_vmread_bitmap)
8592 goto out5;
8593
8594 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8595 if (!vmx_vmwrite_bitmap)
8596 goto out6;
8597
8598 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8599 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8600 /* shadowed read/write fields */
8601 for (i = 0; i < max_shadow_read_write_fields; i++) {
8602 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8603 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8604 }
8605 /* shadowed read only fields */
8606 for (i = 0; i < max_shadow_read_only_fields; i++)
8607 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8608
fdef3ad1
HQ		 8609 /*
8610 * Allow direct access to the PC debug port (it is often used for I/O
8611 * delays, but the vmexits simply slow things down).
8612 */
3e7c73e9
AK		 8613 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8614 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8615
3e7c73e9 8616 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8617
5897297b
AK		 8618 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8619 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8620
2384d2b3
SY		 8621 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8622
0ee75bea
AK		 8623 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8624 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8625 if (r)
4607c2d7 8626 goto out7;
25c5f225 8627
8f536b76
ZY		 8628#ifdef CONFIG_KEXEC
8629 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8630 crash_vmclear_local_loaded_vmcss);
8631#endif
8632
5897297b
AK		 8633 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8634 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8635 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8636 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8637 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8638 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8639 memcpy(vmx_msr_bitmap_legacy_x2apic,
8640 vmx_msr_bitmap_legacy, PAGE_SIZE);
8641 memcpy(vmx_msr_bitmap_longmode_x2apic,
8642 vmx_msr_bitmap_longmode, PAGE_SIZE);
8643
01e439be 8644 if (enable_apicv) {
8d14695f
YZ		 8645 for (msr = 0x800; msr <= 0x8ff; msr++)
8646 vmx_disable_intercept_msr_read_x2apic(msr);
8647
8648 /* According SDM, in x2apic mode, the whole id reg is used.
8649 * But in KVM, it only use the highest eight bits. Need to
8650 * intercept it */
8651 vmx_enable_intercept_msr_read_x2apic(0x802);
8652 /* TMCCT */
8653 vmx_enable_intercept_msr_read_x2apic(0x839);
8654 /* TPR */
8655 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8656 /* EOI */
8657 vmx_disable_intercept_msr_write_x2apic(0x80b);
8658 /* SELF-IPI */
8659 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8660 }
fdef3ad1 8661
089d034e 8662 if (enable_ept) {
3f6d8c8a
XH		 8663 kvm_mmu_set_mask_ptes(0ull,
8664 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8665 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8666 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8667 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8668 kvm_enable_tdp();
8669 } else
8670 kvm_disable_tdp();
1439442c 8671
fdef3ad1
HQ		 8672 return 0;
8673
4607c2d7
AG		 8674out7:
8675 free_page((unsigned long)vmx_vmwrite_bitmap);
8676out6:
8677 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8678out5:
8679 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8680out4:
5897297b 8681 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8682out3:
8683 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8684out2:
5897297b 8685 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8686out1:
3e7c73e9 8687 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8688out:
3e7c73e9 8689 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8690 return r;
6aa8b732
AK		 8691}
8692
8693static void __exit vmx_exit(void)
8694{
8d14695f
YZ		 8695 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8696 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8697 free_page((unsigned long)vmx_msr_bitmap_legacy);
8698 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8699 free_page((unsigned long)vmx_io_bitmap_b);
8700 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8701 free_page((unsigned long)vmx_vmwrite_bitmap);
8702 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8703
8f536b76
ZY		 8704#ifdef CONFIG_KEXEC
8705 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8706 synchronize_rcu();
8707#endif
8708
cb498ea2 8709 kvm_exit();
6aa8b732
AK		 8710}
8711
8712module_init(vmx_init)
8713module_exit(vmx_exit)
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