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KVM: nVMX: Fix returned value of MSR_IA32_VMX_PROCBASED_CTLS
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
3573e22c 357 gpa_t vmxon_ptr;
a9d30f33
NHE		 358
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 gpa_t current_vmptr;
361 /* The host-usable pointer to the above */
362 struct page *current_vmcs12_page;
363 struct vmcs12 *current_vmcs12;
8de48833 364 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 365 /*
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
368 */
369 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 370
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool;
373 int vmcs02_num;
fe3ef05c 374 u64 vmcs01_tsc_offset;
644d711a
NHE		 375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending;
fe3ef05c
NHE		 377 /*
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
380 */
381 struct page *apic_access_page;
b3897a49 382 u64 msr_ia32_feature_control;
f4124500
JK		 383
384 struct hrtimer preemption_timer;
385 bool preemption_timer_expired;
ec378aee
NHE		 386};
387
01e439be
YZ		 388#define POSTED_INTR_ON 0
389/* Posted-Interrupt Descriptor */
390struct pi_desc {
391 u32 pir[8]; /* Posted interrupt requested */
392 u32 control; /* bit 0 of control is outstanding notification bit */
393 u32 rsvd[7];
394} __aligned(64);
395
a20ed54d
YZ		 396static bool pi_test_and_set_on(struct pi_desc *pi_desc)
397{
398 return test_and_set_bit(POSTED_INTR_ON,
399 (unsigned long *)&pi_desc->control);
400}
401
402static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
403{
404 return test_and_clear_bit(POSTED_INTR_ON,
405 (unsigned long *)&pi_desc->control);
406}
407
408static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
409{
410 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
411}
412
a2fa3e9f 413struct vcpu_vmx {
fb3f0f51 414 struct kvm_vcpu vcpu;
313dbd49 415 unsigned long host_rsp;
29bd8a78 416 u8 fail;
9d58b931 417 bool nmi_known_unmasked;
51aa01d1 418 u32 exit_intr_info;
1155f76a 419 u32 idt_vectoring_info;
6de12732 420 ulong rflags;
26bb0981 421 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 422 int nmsrs;
423 int save_nmsrs;
a547c6db 424 unsigned long host_idt_base;
a2fa3e9f 425#ifdef CONFIG_X86_64
44ea2b17
AK		 426 u64 msr_host_kernel_gs_base;
427 u64 msr_guest_kernel_gs_base;
a2fa3e9f 428#endif
2961e876
GN		 429 u32 vm_entry_controls_shadow;
430 u32 vm_exit_controls_shadow;
d462b819
NHE		 431 /*
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
435 */
436 struct loaded_vmcs vmcs01;
437 struct loaded_vmcs *loaded_vmcs;
438 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 439 struct msr_autoload {
440 unsigned nr;
441 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
442 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
443 } msr_autoload;
a2fa3e9f
GH		 444 struct {
445 int loaded;
446 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 447#ifdef CONFIG_X86_64
448 u16 ds_sel, es_sel;
449#endif
152d3f2f
LV		 450 int gs_ldt_reload_needed;
451 int fs_reload_needed;
da8999d3 452 u64 msr_host_bndcfgs;
d77c26fc 453 } host_state;
9c8cba37 454 struct {
7ffd92c5 455 int vm86_active;
78ac8b47 456 ulong save_rflags;
f5f7b2fe
AK		 457 struct kvm_segment segs[8];
458 } rmode;
459 struct {
460 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 461 struct kvm_save_segment {
462 u16 selector;
463 unsigned long base;
464 u32 limit;
465 u32 ar;
f5f7b2fe 466 } seg[8];
2fb92db1 467 } segment_cache;
2384d2b3 468 int vpid;
04fa4d32 469 bool emulation_required;
3b86cd99
JK		 470
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked;
473 ktime_t entry_time;
474 s64 vnmi_blocked_time;
a0861c02 475 u32 exit_reason;
4e47c7a6
SY		 476
477 bool rdtscp_enabled;
ec378aee 478
01e439be
YZ		 479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc;
481
ec378aee
NHE		 482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested;
a2fa3e9f
GH		 484};
485
2fb92db1
AK		 486enum segment_cache_field {
487 SEG_FIELD_SEL = 0,
488 SEG_FIELD_BASE = 1,
489 SEG_FIELD_LIMIT = 2,
490 SEG_FIELD_AR = 3,
491
492 SEG_FIELD_NR = 4
493};
494
a2fa3e9f
GH		 495static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
496{
fb3f0f51 497 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 498}
499
22bd0358
NHE		 500#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
504
4607c2d7 505
fe2b201b 506static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 507 /*
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
518 */
519 VM_EXIT_REASON,
520 VM_EXIT_INTR_INFO,
521 VM_EXIT_INSTRUCTION_LEN,
522 IDT_VECTORING_INFO_FIELD,
523 IDT_VECTORING_ERROR_CODE,
524 VM_EXIT_INTR_ERROR_CODE,
525 EXIT_QUALIFICATION,
526 GUEST_LINEAR_ADDRESS,
527 GUEST_PHYSICAL_ADDRESS
528};
fe2b201b 529static int max_shadow_read_only_fields =
4607c2d7
AG		 530 ARRAY_SIZE(shadow_read_only_fields);
531
fe2b201b 532static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 533 GUEST_RIP,
534 GUEST_RSP,
535 GUEST_CR0,
536 GUEST_CR3,
537 GUEST_CR4,
538 GUEST_INTERRUPTIBILITY_INFO,
539 GUEST_RFLAGS,
540 GUEST_CS_SELECTOR,
541 GUEST_CS_AR_BYTES,
542 GUEST_CS_LIMIT,
543 GUEST_CS_BASE,
544 GUEST_ES_BASE,
36be0b9d 545 GUEST_BNDCFGS,
4607c2d7
AG		 546 CR0_GUEST_HOST_MASK,
547 CR0_READ_SHADOW,
548 CR4_READ_SHADOW,
549 TSC_OFFSET,
550 EXCEPTION_BITMAP,
551 CPU_BASED_VM_EXEC_CONTROL,
552 VM_ENTRY_EXCEPTION_ERROR_CODE,
553 VM_ENTRY_INTR_INFO_FIELD,
554 VM_ENTRY_INSTRUCTION_LEN,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 HOST_FS_BASE,
557 HOST_GS_BASE,
558 HOST_FS_SELECTOR,
559 HOST_GS_SELECTOR
560};
fe2b201b 561static int max_shadow_read_write_fields =
4607c2d7
AG		 562 ARRAY_SIZE(shadow_read_write_fields);
563
772e0318 564static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 565 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
566 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
567 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
568 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
569 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
570 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
571 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
572 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
573 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
574 FIELD(HOST_ES_SELECTOR, host_es_selector),
575 FIELD(HOST_CS_SELECTOR, host_cs_selector),
576 FIELD(HOST_SS_SELECTOR, host_ss_selector),
577 FIELD(HOST_DS_SELECTOR, host_ds_selector),
578 FIELD(HOST_FS_SELECTOR, host_fs_selector),
579 FIELD(HOST_GS_SELECTOR, host_gs_selector),
580 FIELD(HOST_TR_SELECTOR, host_tr_selector),
581 FIELD64(IO_BITMAP_A, io_bitmap_a),
582 FIELD64(IO_BITMAP_B, io_bitmap_b),
583 FIELD64(MSR_BITMAP, msr_bitmap),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
587 FIELD64(TSC_OFFSET, tsc_offset),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
589 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
590 FIELD64(EPT_POINTER, ept_pointer),
591 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
592 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
593 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
594 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
595 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
597 FIELD64(GUEST_PDPTR0, guest_pdptr0),
598 FIELD64(GUEST_PDPTR1, guest_pdptr1),
599 FIELD64(GUEST_PDPTR2, guest_pdptr2),
600 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 601 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 602 FIELD64(HOST_IA32_PAT, host_ia32_pat),
603 FIELD64(HOST_IA32_EFER, host_ia32_efer),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
607 FIELD(EXCEPTION_BITMAP, exception_bitmap),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
610 FIELD(CR3_TARGET_COUNT, cr3_target_count),
611 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
612 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
614 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
619 FIELD(TPR_THRESHOLD, tpr_threshold),
620 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
621 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
622 FIELD(VM_EXIT_REASON, vm_exit_reason),
623 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
624 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
625 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
626 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
627 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
628 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
629 FIELD(GUEST_ES_LIMIT, guest_es_limit),
630 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
631 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
632 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
633 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
634 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
635 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
636 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
637 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
638 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
639 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
640 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
641 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
642 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
643 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
644 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
645 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
646 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
648 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
649 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
650 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 651 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 652 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
653 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
654 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
655 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
656 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
657 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
658 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
659 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
660 FIELD(EXIT_QUALIFICATION, exit_qualification),
661 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
662 FIELD(GUEST_CR0, guest_cr0),
663 FIELD(GUEST_CR3, guest_cr3),
664 FIELD(GUEST_CR4, guest_cr4),
665 FIELD(GUEST_ES_BASE, guest_es_base),
666 FIELD(GUEST_CS_BASE, guest_cs_base),
667 FIELD(GUEST_SS_BASE, guest_ss_base),
668 FIELD(GUEST_DS_BASE, guest_ds_base),
669 FIELD(GUEST_FS_BASE, guest_fs_base),
670 FIELD(GUEST_GS_BASE, guest_gs_base),
671 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
672 FIELD(GUEST_TR_BASE, guest_tr_base),
673 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
674 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
675 FIELD(GUEST_DR7, guest_dr7),
676 FIELD(GUEST_RSP, guest_rsp),
677 FIELD(GUEST_RIP, guest_rip),
678 FIELD(GUEST_RFLAGS, guest_rflags),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
680 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
681 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
682 FIELD(HOST_CR0, host_cr0),
683 FIELD(HOST_CR3, host_cr3),
684 FIELD(HOST_CR4, host_cr4),
685 FIELD(HOST_FS_BASE, host_fs_base),
686 FIELD(HOST_GS_BASE, host_gs_base),
687 FIELD(HOST_TR_BASE, host_tr_base),
688 FIELD(HOST_GDTR_BASE, host_gdtr_base),
689 FIELD(HOST_IDTR_BASE, host_idtr_base),
690 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
691 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
692 FIELD(HOST_RSP, host_rsp),
693 FIELD(HOST_RIP, host_rip),
694};
695static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
696
697static inline short vmcs_field_to_offset(unsigned long field)
698{
699 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
700 return -1;
701 return vmcs_field_to_offset_table[field];
702}
703
a9d30f33
NHE		 704static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
705{
706 return to_vmx(vcpu)->nested.current_vmcs12;
707}
708
709static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
710{
711 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 712 if (is_error_page(page))
a9d30f33 713 return NULL;
32cad84f 714
a9d30f33
NHE		 715 return page;
716}
717
718static void nested_release_page(struct page *page)
719{
720 kvm_release_page_dirty(page);
721}
722
723static void nested_release_page_clean(struct page *page)
724{
725 kvm_release_page_clean(page);
726}
727
bfd0a56b 728static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 729static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 730static void kvm_cpu_vmxon(u64 addr);
731static void kvm_cpu_vmxoff(void);
93c4adc7 732static bool vmx_mpx_supported(void);
776e58ea 733static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 734static void vmx_set_segment(struct kvm_vcpu *vcpu,
735 struct kvm_segment *var, int seg);
736static void vmx_get_segment(struct kvm_vcpu *vcpu,
737 struct kvm_segment *var, int seg);
d99e4152
GN		 738static bool guest_state_valid(struct kvm_vcpu *vcpu);
739static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 740static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 741static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 742static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 743static bool vmx_mpx_supported(void);
75880a01 744
6aa8b732
AK		 745static DEFINE_PER_CPU(struct vmcs *, vmxarea);
746static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 747/*
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
750 */
751static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 752static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 753
3e7c73e9
AK		 754static unsigned long *vmx_io_bitmap_a;
755static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 756static unsigned long *vmx_msr_bitmap_legacy;
757static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 758static unsigned long *vmx_msr_bitmap_legacy_x2apic;
759static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 760static unsigned long *vmx_vmread_bitmap;
761static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 762
110312c8 763static bool cpu_has_load_ia32_efer;
8bf00a52 764static bool cpu_has_load_perf_global_ctrl;
110312c8 765
2384d2b3
SY		 766static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
767static DEFINE_SPINLOCK(vmx_vpid_lock);
768
1c3d14fe 769static struct vmcs_config {
6aa8b732
AK		 770 int size;
771 int order;
772 u32 revision_id;
1c3d14fe
YS		 773 u32 pin_based_exec_ctrl;
774 u32 cpu_based_exec_ctrl;
f78e0e2e 775 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 776 u32 vmexit_ctrl;
777 u32 vmentry_ctrl;
778} vmcs_config;
6aa8b732 779
efff9e53 780static struct vmx_capability {
d56f546d
SY		 781 u32 ept;
782 u32 vpid;
783} vmx_capability;
784
6aa8b732
AK		 785#define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
791 }
792
772e0318 793static const struct kvm_vmx_segment_field {
6aa8b732
AK		 794 unsigned selector;
795 unsigned base;
796 unsigned limit;
797 unsigned ar_bytes;
798} kvm_vmx_segment_fields[] = {
799 VMX_SEGMENT_FIELD(CS),
800 VMX_SEGMENT_FIELD(DS),
801 VMX_SEGMENT_FIELD(ES),
802 VMX_SEGMENT_FIELD(FS),
803 VMX_SEGMENT_FIELD(GS),
804 VMX_SEGMENT_FIELD(SS),
805 VMX_SEGMENT_FIELD(TR),
806 VMX_SEGMENT_FIELD(LDTR),
807};
808
26bb0981
AK		 809static u64 host_efer;
810
6de4f3ad
AK		 811static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
812
4d56c8a7 813/*
8c06585d 814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 815 * away by decrementing the array size.
816 */
6aa8b732 817static const u32 vmx_msr_index[] = {
05b3e0c2 818#ifdef CONFIG_X86_64
44ea2b17 819 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 820#endif
8c06585d 821 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 822};
9d8f549d 823#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 824
31299944 825static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 826{
827 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
828 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 829 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 830}
831
31299944 832static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 833{
834 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
835 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 836 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 837}
838
31299944 839static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 843 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 844}
845
31299944 846static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 847{
848 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
849 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
850}
851
31299944 852static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 853{
854 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
855 INTR_INFO_VALID_MASK)) ==
856 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
857}
858
31299944 859static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 860{
04547156 861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 862}
863
31299944 864static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 865{
04547156 866 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 867}
868
31299944 869static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 870{
04547156 871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 872}
873
31299944 874static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 875{
04547156
SY		 876 return vmcs_config.cpu_based_exec_ctrl &
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 878}
879
774ead3a 880static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 881{
04547156
SY		 882 return vmcs_config.cpu_based_2nd_exec_ctrl &
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
884}
885
8d14695f
YZ		 886static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
887{
888 return vmcs_config.cpu_based_2nd_exec_ctrl &
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
890}
891
83d4c286
YZ		 892static inline bool cpu_has_vmx_apic_register_virt(void)
893{
894 return vmcs_config.cpu_based_2nd_exec_ctrl &
895 SECONDARY_EXEC_APIC_REGISTER_VIRT;
896}
897
c7c9c56c
YZ		 898static inline bool cpu_has_vmx_virtual_intr_delivery(void)
899{
900 return vmcs_config.cpu_based_2nd_exec_ctrl &
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
902}
903
01e439be
YZ		 904static inline bool cpu_has_vmx_posted_intr(void)
905{
906 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
907}
908
909static inline bool cpu_has_vmx_apicv(void)
910{
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
914}
915
04547156
SY		 916static inline bool cpu_has_vmx_flexpriority(void)
917{
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 920}
921
e799794e
MT		 922static inline bool cpu_has_vmx_ept_execute_only(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 925}
926
927static inline bool cpu_has_vmx_eptp_uncacheable(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_eptp_writeback(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 935}
936
937static inline bool cpu_has_vmx_ept_2m_page(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 940}
941
878403b7
SY		 942static inline bool cpu_has_vmx_ept_1g_page(void)
943{
31299944 944 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 945}
946
4bc9b982
SY		 947static inline bool cpu_has_vmx_ept_4levels(void)
948{
949 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
950}
951
83c3a331
XH		 952static inline bool cpu_has_vmx_ept_ad_bits(void)
953{
954 return vmx_capability.ept & VMX_EPT_AD_BIT;
955}
956
31299944 957static inline bool cpu_has_vmx_invept_context(void)
d56f546d 958{
31299944 959 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 960}
961
31299944 962static inline bool cpu_has_vmx_invept_global(void)
d56f546d 963{
31299944 964 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 965}
966
518c8aee
GJ		 967static inline bool cpu_has_vmx_invvpid_single(void)
968{
969 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
970}
971
b9d762fa
GJ		 972static inline bool cpu_has_vmx_invvpid_global(void)
973{
974 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
975}
976
31299944 977static inline bool cpu_has_vmx_ept(void)
d56f546d 978{
04547156
SY		 979 return vmcs_config.cpu_based_2nd_exec_ctrl &
980 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 981}
982
31299944 983static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 984{
985 return vmcs_config.cpu_based_2nd_exec_ctrl &
986 SECONDARY_EXEC_UNRESTRICTED_GUEST;
987}
988
31299944 989static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 990{
991 return vmcs_config.cpu_based_2nd_exec_ctrl &
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
993}
994
31299944 995static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 996{
6d3e435e 997 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 998}
999
31299944 1000static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1001{
04547156
SY		 1002 return vmcs_config.cpu_based_2nd_exec_ctrl &
1003 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1004}
1005
31299944 1006static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1007{
1008 return vmcs_config.cpu_based_2nd_exec_ctrl &
1009 SECONDARY_EXEC_RDTSCP;
1010}
1011
ad756a16
MJ		 1012static inline bool cpu_has_vmx_invpcid(void)
1013{
1014 return vmcs_config.cpu_based_2nd_exec_ctrl &
1015 SECONDARY_EXEC_ENABLE_INVPCID;
1016}
1017
31299944 1018static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1019{
1020 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1021}
1022
f5f48ee1
SY		 1023static inline bool cpu_has_vmx_wbinvd_exit(void)
1024{
1025 return vmcs_config.cpu_based_2nd_exec_ctrl &
1026 SECONDARY_EXEC_WBINVD_EXITING;
1027}
1028
abc4fc58
AG		 1029static inline bool cpu_has_vmx_shadow_vmcs(void)
1030{
1031 u64 vmx_msr;
1032 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1035 return false;
1036
1037 return vmcs_config.cpu_based_2nd_exec_ctrl &
1038 SECONDARY_EXEC_SHADOW_VMCS;
1039}
1040
04547156
SY		 1041static inline bool report_flexpriority(void)
1042{
1043 return flexpriority_enabled;
1044}
1045
fe3ef05c
NHE		 1046static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1047{
1048 return vmcs12->cpu_based_vm_exec_control & bit;
1049}
1050
1051static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1052{
1053 return (vmcs12->cpu_based_vm_exec_control &
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1055 (vmcs12->secondary_vm_exec_control & bit);
1056}
1057
f5c4368f 1058static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1059{
1060 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1061}
1062
f4124500
JK		 1063static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1064{
1065 return vmcs12->pin_based_vm_exec_control &
1066 PIN_BASED_VMX_PREEMPTION_TIMER;
1067}
1068
155a97a3
NHE		 1069static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1070{
1071 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1072}
1073
644d711a
NHE		 1074static inline bool is_exception(u32 intr_info)
1075{
1076 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1077 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1078}
1079
533558bc
JK		 1080static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1081 u32 exit_intr_info,
1082 unsigned long exit_qualification);
7c177938
NHE		 1083static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1084 struct vmcs12 *vmcs12,
1085 u32 reason, unsigned long qualification);
1086
8b9cf98c 1087static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1088{
1089 int i;
1090
a2fa3e9f 1091 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1092 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1093 return i;
1094 return -1;
1095}
1096
2384d2b3
SY		 1097static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1098{
1099 struct {
1100 u64 vpid : 16;
1101 u64 rsvd : 48;
1102 u64 gva;
1103 } operand = { vpid, 0, gva };
1104
4ecac3fd 1105 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand), "c"(ext) : "cc", "memory");
1109}
1110
1439442c
SY		 1111static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1112{
1113 struct {
1114 u64 eptp, gpa;
1115 } operand = {eptp, gpa};
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand), "c" (ext) : "cc", "memory");
1121}
1122
26bb0981 1123static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1124{
1125 int i;
1126
8b9cf98c 1127 i = __find_msr_index(vmx, msr);
a75beee6 1128 if (i >= 0)
a2fa3e9f 1129 return &vmx->guest_msrs[i];
8b6d44c7 1130 return NULL;
7725f0ba
AK		 1131}
1132
6aa8b732
AK		 1133static void vmcs_clear(struct vmcs *vmcs)
1134{
1135 u64 phys_addr = __pa(vmcs);
1136 u8 error;
1137
4ecac3fd 1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1139 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1140 : "cc", "memory");
1141 if (error)
1142 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1143 vmcs, phys_addr);
1144}
1145
d462b819
NHE		 1146static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1147{
1148 vmcs_clear(loaded_vmcs->vmcs);
1149 loaded_vmcs->cpu = -1;
1150 loaded_vmcs->launched = 0;
1151}
1152
7725b894
DX		 1153static void vmcs_load(struct vmcs *vmcs)
1154{
1155 u64 phys_addr = __pa(vmcs);
1156 u8 error;
1157
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1159 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1160 : "cc", "memory");
1161 if (error)
2844d849 1162 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1163 vmcs, phys_addr);
1164}
1165
8f536b76
ZY		 1166#ifdef CONFIG_KEXEC
1167/*
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1170 * default.
1171 */
1172static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1173
1174static inline void crash_enable_local_vmclear(int cpu)
1175{
1176 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177}
1178
1179static inline void crash_disable_local_vmclear(int cpu)
1180{
1181 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static inline int crash_local_vmclear_enabled(int cpu)
1185{
1186 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1187}
1188
1189static void crash_vmclear_local_loaded_vmcss(void)
1190{
1191 int cpu = raw_smp_processor_id();
1192 struct loaded_vmcs *v;
1193
1194 if (!crash_local_vmclear_enabled(cpu))
1195 return;
1196
1197 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1198 loaded_vmcss_on_cpu_link)
1199 vmcs_clear(v->vmcs);
1200}
1201#else
1202static inline void crash_enable_local_vmclear(int cpu) { }
1203static inline void crash_disable_local_vmclear(int cpu) { }
1204#endif /* CONFIG_KEXEC */
1205
d462b819 1206static void __loaded_vmcs_clear(void *arg)
6aa8b732 1207{
d462b819 1208 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1209 int cpu = raw_smp_processor_id();
6aa8b732 1210
d462b819
NHE		 1211 if (loaded_vmcs->cpu != cpu)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1214 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1215 crash_disable_local_vmclear(cpu);
d462b819 1216 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1217
1218 /*
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1223 */
1224 smp_wmb();
1225
d462b819 1226 loaded_vmcs_init(loaded_vmcs);
8f536b76 1227 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1228}
1229
d462b819 1230static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1231{
e6c7d321
XG		 1232 int cpu = loaded_vmcs->cpu;
1233
1234 if (cpu != -1)
1235 smp_call_function_single(cpu,
1236 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1237}
1238
1760dd49 1239static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1240{
1241 if (vmx->vpid == 0)
1242 return;
1243
518c8aee
GJ		 1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1246}
1247
b9d762fa
GJ		 1248static inline void vpid_sync_vcpu_global(void)
1249{
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1252}
1253
1254static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1255{
1256 if (cpu_has_vmx_invvpid_single())
1760dd49 1257 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1258 else
1259 vpid_sync_vcpu_global();
1260}
1261
1439442c
SY		 1262static inline void ept_sync_global(void)
1263{
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1266}
1267
1268static inline void ept_sync_context(u64 eptp)
1269{
089d034e 1270 if (enable_ept) {
1439442c
SY		 1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1273 else
1274 ept_sync_global();
1275 }
1276}
1277
96304217 1278static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1279{
5e520e62 1280 unsigned long value;
6aa8b732 1281
5e520e62
AK		 1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1283 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1284 return value;
1285}
1286
96304217 1287static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1288{
1289 return vmcs_readl(field);
1290}
1291
96304217 1292static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1293{
1294 return vmcs_readl(field);
1295}
1296
96304217 1297static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1298{
05b3e0c2 1299#ifdef CONFIG_X86_64
6aa8b732
AK		 1300 return vmcs_readl(field);
1301#else
1302 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1303#endif
1304}
1305
e52de1b8
AK		 1306static noinline void vmwrite_error(unsigned long field, unsigned long value)
1307{
1308 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1309 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1310 dump_stack();
1311}
1312
6aa8b732
AK		 1313static void vmcs_writel(unsigned long field, unsigned long value)
1314{
1315 u8 error;
1316
4ecac3fd 1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1318 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1319 if (unlikely(error))
1320 vmwrite_error(field, value);
6aa8b732
AK		 1321}
1322
1323static void vmcs_write16(unsigned long field, u16 value)
1324{
1325 vmcs_writel(field, value);
1326}
1327
1328static void vmcs_write32(unsigned long field, u32 value)
1329{
1330 vmcs_writel(field, value);
1331}
1332
1333static void vmcs_write64(unsigned long field, u64 value)
1334{
6aa8b732 1335 vmcs_writel(field, value);
7682f2d0 1336#ifndef CONFIG_X86_64
6aa8b732
AK		 1337 asm volatile ("");
1338 vmcs_writel(field+1, value >> 32);
1339#endif
1340}
1341
2ab455cc
AL		 1342static void vmcs_clear_bits(unsigned long field, u32 mask)
1343{
1344 vmcs_writel(field, vmcs_readl(field) & ~mask);
1345}
1346
1347static void vmcs_set_bits(unsigned long field, u32 mask)
1348{
1349 vmcs_writel(field, vmcs_readl(field) | mask);
1350}
1351
2961e876
GN		 1352static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1353{
1354 vmcs_write32(VM_ENTRY_CONTROLS, val);
1355 vmx->vm_entry_controls_shadow = val;
1356}
1357
1358static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1359{
1360 if (vmx->vm_entry_controls_shadow != val)
1361 vm_entry_controls_init(vmx, val);
1362}
1363
1364static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1365{
1366 return vmx->vm_entry_controls_shadow;
1367}
1368
1369
1370static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1371{
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1373}
1374
1375static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1378}
1379
1380static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1381{
1382 vmcs_write32(VM_EXIT_CONTROLS, val);
1383 vmx->vm_exit_controls_shadow = val;
1384}
1385
1386static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1387{
1388 if (vmx->vm_exit_controls_shadow != val)
1389 vm_exit_controls_init(vmx, val);
1390}
1391
1392static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1393{
1394 return vmx->vm_exit_controls_shadow;
1395}
1396
1397
1398static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1401}
1402
1403static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1404{
1405 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1406}
1407
2fb92db1
AK		 1408static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1409{
1410 vmx->segment_cache.bitmask = 0;
1411}
1412
1413static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1414 unsigned field)
1415{
1416 bool ret;
1417 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1418
1419 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1420 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1421 vmx->segment_cache.bitmask = 0;
1422 }
1423 ret = vmx->segment_cache.bitmask & mask;
1424 vmx->segment_cache.bitmask |= mask;
1425 return ret;
1426}
1427
1428static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1429{
1430 u16 *p = &vmx->segment_cache.seg[seg].selector;
1431
1432 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1433 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1434 return *p;
1435}
1436
1437static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1438{
1439 ulong *p = &vmx->segment_cache.seg[seg].base;
1440
1441 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1442 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1443 return *p;
1444}
1445
1446static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1447{
1448 u32 *p = &vmx->segment_cache.seg[seg].limit;
1449
1450 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1451 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1452 return *p;
1453}
1454
1455static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1456{
1457 u32 *p = &vmx->segment_cache.seg[seg].ar;
1458
1459 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1460 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1461 return *p;
1462}
1463
abd3f2d6
AK		 1464static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1465{
1466 u32 eb;
1467
fd7373cc
JK		 1468 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1469 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1470 if ((vcpu->guest_debug &
1471 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1472 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1473 eb |= 1u << BP_VECTOR;
7ffd92c5 1474 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1475 eb = ~0;
089d034e 1476 if (enable_ept)
1439442c 1477 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1478 if (vcpu->fpu_active)
1479 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1480
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1485 */
1486 if (is_guest_mode(vcpu))
1487 eb |= get_vmcs12(vcpu)->exception_bitmap;
1488
abd3f2d6
AK		 1489 vmcs_write32(EXCEPTION_BITMAP, eb);
1490}
1491
2961e876
GN		 1492static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1493 unsigned long entry, unsigned long exit)
8bf00a52 1494{
2961e876
GN		 1495 vm_entry_controls_clearbit(vmx, entry);
1496 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1497}
1498
61d2ef2c
AK		 1499static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1500{
1501 unsigned i;
1502 struct msr_autoload *m = &vmx->msr_autoload;
1503
8bf00a52
GN		 1504 switch (msr) {
1505 case MSR_EFER:
1506 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1507 clear_atomic_switch_msr_special(vmx,
1508 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1509 VM_EXIT_LOAD_IA32_EFER);
1510 return;
1511 }
1512 break;
1513 case MSR_CORE_PERF_GLOBAL_CTRL:
1514 if (cpu_has_load_perf_global_ctrl) {
2961e876 1515 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1518 return;
1519 }
1520 break;
110312c8
AK		 1521 }
1522
61d2ef2c
AK		 1523 for (i = 0; i < m->nr; ++i)
1524 if (m->guest[i].index == msr)
1525 break;
1526
1527 if (i == m->nr)
1528 return;
1529 --m->nr;
1530 m->guest[i] = m->guest[m->nr];
1531 m->host[i] = m->host[m->nr];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1534}
1535
2961e876
GN		 1536static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1537 unsigned long entry, unsigned long exit,
1538 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1539 u64 guest_val, u64 host_val)
8bf00a52
GN		 1540{
1541 vmcs_write64(guest_val_vmcs, guest_val);
1542 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1543 vm_entry_controls_setbit(vmx, entry);
1544 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1545}
1546
61d2ef2c
AK		 1547static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1548 u64 guest_val, u64 host_val)
1549{
1550 unsigned i;
1551 struct msr_autoload *m = &vmx->msr_autoload;
1552
8bf00a52
GN		 1553 switch (msr) {
1554 case MSR_EFER:
1555 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1556 add_atomic_switch_msr_special(vmx,
1557 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1558 VM_EXIT_LOAD_IA32_EFER,
1559 GUEST_IA32_EFER,
1560 HOST_IA32_EFER,
1561 guest_val, host_val);
1562 return;
1563 }
1564 break;
1565 case MSR_CORE_PERF_GLOBAL_CTRL:
1566 if (cpu_has_load_perf_global_ctrl) {
2961e876 1567 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1570 GUEST_IA32_PERF_GLOBAL_CTRL,
1571 HOST_IA32_PERF_GLOBAL_CTRL,
1572 guest_val, host_val);
1573 return;
1574 }
1575 break;
110312c8
AK		 1576 }
1577
61d2ef2c
AK		 1578 for (i = 0; i < m->nr; ++i)
1579 if (m->guest[i].index == msr)
1580 break;
1581
e7fc6f93 1582 if (i == NR_AUTOLOAD_MSRS) {
60266204 1583 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1584 "Can't add msr %x\n", msr);
1585 return;
1586 } else if (i == m->nr) {
61d2ef2c
AK		 1587 ++m->nr;
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1590 }
1591
1592 m->guest[i].index = msr;
1593 m->guest[i].value = guest_val;
1594 m->host[i].index = msr;
1595 m->host[i].value = host_val;
1596}
1597
33ed6329
AK		 1598static void reload_tss(void)
1599{
33ed6329
AK		 1600 /*
1601 * VT restores TR but not its size. Useless.
1602 */
d359192f 1603 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1604 struct desc_struct *descs;
33ed6329 1605
d359192f 1606 descs = (void *)gdt->address;
33ed6329
AK		 1607 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1608 load_TR_desc();
33ed6329
AK		 1609}
1610
92c0d900 1611static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1612{
3a34a881 1613 u64 guest_efer;
51c6cf66
AK		 1614 u64 ignore_bits;
1615
f6801dff 1616 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1617
51c6cf66 1618 /*
0fa06071 1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1620 * outside long mode
1621 */
1622 ignore_bits = EFER_NX | EFER_SCE;
1623#ifdef CONFIG_X86_64
1624 ignore_bits |= EFER_LMA | EFER_LME;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer & EFER_LMA)
1627 ignore_bits &= ~(u64)EFER_SCE;
1628#endif
51c6cf66
AK		 1629 guest_efer &= ~ignore_bits;
1630 guest_efer |= host_efer & ignore_bits;
26bb0981 1631 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1632 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1633
1634 clear_atomic_switch_msr(vmx, MSR_EFER);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1637 guest_efer = vmx->vcpu.arch.efer;
1638 if (!(guest_efer & EFER_LMA))
1639 guest_efer &= ~EFER_LME;
1640 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1641 return false;
1642 }
1643
26bb0981 1644 return true;
51c6cf66
AK		 1645}
1646
2d49ec72
GN		 1647static unsigned long segment_base(u16 selector)
1648{
d359192f 1649 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1650 struct desc_struct *d;
1651 unsigned long table_base;
1652 unsigned long v;
1653
1654 if (!(selector & ~3))
1655 return 0;
1656
d359192f 1657 table_base = gdt->address;
2d49ec72
GN		 1658
1659 if (selector & 4) { /* from ldt */
1660 u16 ldt_selector = kvm_read_ldt();
1661
1662 if (!(ldt_selector & ~3))
1663 return 0;
1664
1665 table_base = segment_base(ldt_selector);
1666 }
1667 d = (struct desc_struct *)(table_base + (selector & ~7));
1668 v = get_desc_base(d);
1669#ifdef CONFIG_X86_64
1670 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1671 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1672#endif
1673 return v;
1674}
1675
1676static inline unsigned long kvm_read_tr_base(void)
1677{
1678 u16 tr;
1679 asm("str %0" : "=g"(tr));
1680 return segment_base(tr);
1681}
1682
04d2cc77 1683static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1684{
04d2cc77 1685 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1686 int i;
04d2cc77 1687
a2fa3e9f 1688 if (vmx->host_state.loaded)
33ed6329
AK		 1689 return;
1690
a2fa3e9f 1691 vmx->host_state.loaded = 1;
33ed6329
AK		 1692 /*
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1695 */
d6e88aec 1696 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1697 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1698 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1699 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1700 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1701 vmx->host_state.fs_reload_needed = 0;
1702 } else {
33ed6329 1703 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1704 vmx->host_state.fs_reload_needed = 1;
33ed6329 1705 }
9581d442 1706 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1707 if (!(vmx->host_state.gs_sel & 7))
1708 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1709 else {
1710 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1711 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1712 }
1713
b2da15ac
AK		 1714#ifdef CONFIG_X86_64
1715 savesegment(ds, vmx->host_state.ds_sel);
1716 savesegment(es, vmx->host_state.es_sel);
1717#endif
1718
33ed6329
AK		 1719#ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1721 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1722#else
a2fa3e9f
GH		 1723 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1724 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1725#endif
707c0874
AK		 1726
1727#ifdef CONFIG_X86_64
c8770e7b
AK		 1728 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1729 if (is_long_mode(&vmx->vcpu))
44ea2b17 1730 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1731#endif
da8999d3
LJ		 1732 if (boot_cpu_has(X86_FEATURE_MPX))
1733 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1734 for (i = 0; i < vmx->save_nmsrs; ++i)
1735 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1736 vmx->guest_msrs[i].data,
1737 vmx->guest_msrs[i].mask);
33ed6329
AK		 1738}
1739
a9b21b62 1740static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1741{
a2fa3e9f 1742 if (!vmx->host_state.loaded)
33ed6329
AK		 1743 return;
1744
e1beb1d3 1745 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1746 vmx->host_state.loaded = 0;
c8770e7b
AK		 1747#ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx->vcpu))
1749 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1750#endif
152d3f2f 1751 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1752 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1753#ifdef CONFIG_X86_64
9581d442 1754 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1755#else
1756 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1757#endif
33ed6329 1758 }
0a77fe4c
AK		 1759 if (vmx->host_state.fs_reload_needed)
1760 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1761#ifdef CONFIG_X86_64
1762 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1763 loadsegment(ds, vmx->host_state.ds_sel);
1764 loadsegment(es, vmx->host_state.es_sel);
1765 }
b2da15ac 1766#endif
152d3f2f 1767 reload_tss();
44ea2b17 1768#ifdef CONFIG_X86_64
c8770e7b 1769 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1770#endif
da8999d3
LJ		 1771 if (vmx->host_state.msr_host_bndcfgs)
1772 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1773 /*
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1776 */
1777 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1778 stts();
3444d7da 1779 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1780}
1781
a9b21b62
AK		 1782static void vmx_load_host_state(struct vcpu_vmx *vmx)
1783{
1784 preempt_disable();
1785 __vmx_load_host_state(vmx);
1786 preempt_enable();
1787}
1788
6aa8b732
AK		 1789/*
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1792 */
15ad7146 1793static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1794{
a2fa3e9f 1795 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1796 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1797
4610c9cc
DX		 1798 if (!vmm_exclusive)
1799 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1800 else if (vmx->loaded_vmcs->cpu != cpu)
1801 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1802
d462b819
NHE		 1803 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1804 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1805 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1806 }
1807
d462b819 1808 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1809 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1810 unsigned long sysenter_esp;
1811
a8eeb04a 1812 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1813 local_irq_disable();
8f536b76 1814 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1815
1816 /*
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1820 */
1821 smp_rmb();
1822
d462b819
NHE		 1823 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1824 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1825 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1826 local_irq_enable();
1827
6aa8b732
AK		 1828 /*
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1830 * processors.
1831 */
d6e88aec 1832 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1833 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1834
1835 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1837 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1838 }
6aa8b732
AK		 1839}
1840
1841static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1842{
a9b21b62 1843 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1844 if (!vmm_exclusive) {
d462b819
NHE		 1845 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1846 vcpu->cpu = -1;
4610c9cc
DX		 1847 kvm_cpu_vmxoff();
1848 }
6aa8b732
AK		 1849}
1850
5fd86fcf
AK		 1851static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1852{
81231c69
AK		 1853 ulong cr0;
1854
5fd86fcf
AK		 1855 if (vcpu->fpu_active)
1856 return;
1857 vcpu->fpu_active = 1;
81231c69
AK		 1858 cr0 = vmcs_readl(GUEST_CR0);
1859 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1860 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1861 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1862 update_exception_bitmap(vcpu);
edcafe3c 1863 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1864 if (is_guest_mode(vcpu))
1865 vcpu->arch.cr0_guest_owned_bits &=
1866 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1867 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1868}
1869
edcafe3c
AK		 1870static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1871
fe3ef05c
NHE		 1872/*
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1876 */
1877static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1878{
1879 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1880 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1881}
1882static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1883{
1884 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1885 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1886}
1887
5fd86fcf
AK		 1888static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1889{
36cf24e0
NHE		 1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1892 */
edcafe3c 1893 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1894 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1895 update_exception_bitmap(vcpu);
edcafe3c
AK		 1896 vcpu->arch.cr0_guest_owned_bits = 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1898 if (is_guest_mode(vcpu)) {
1899 /*
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1906 */
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1909 (vcpu->arch.cr0 & X86_CR0_TS);
1910 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1911 } else
1912 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1913}
1914
6aa8b732
AK		 1915static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1916{
78ac8b47 1917 unsigned long rflags, save_rflags;
345dcaa8 1918
6de12732
AK		 1919 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1920 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1921 rflags = vmcs_readl(GUEST_RFLAGS);
1922 if (to_vmx(vcpu)->rmode.vm86_active) {
1923 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1924 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1925 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1926 }
1927 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1928 }
6de12732 1929 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1930}
1931
1932static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1933{
6de12732
AK		 1934 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1935 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1936 if (to_vmx(vcpu)->rmode.vm86_active) {
1937 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1938 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1939 }
6aa8b732
AK		 1940 vmcs_writel(GUEST_RFLAGS, rflags);
1941}
1942
2809f5d2
GC		 1943static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1944{
1945 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1946 int ret = 0;
1947
1948 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1949 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1950 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1951 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1952
1953 return ret & mask;
1954}
1955
1956static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1957{
1958 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1959 u32 interruptibility = interruptibility_old;
1960
1961 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1962
48005f64 1963 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1964 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1965 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1966 interruptibility |= GUEST_INTR_STATE_STI;
1967
1968 if ((interruptibility != interruptibility_old))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1970}
1971
6aa8b732
AK		 1972static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1973{
1974 unsigned long rip;
6aa8b732 1975
5fdbf976 1976 rip = kvm_rip_read(vcpu);
6aa8b732 1977 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1978 kvm_rip_write(vcpu, rip);
6aa8b732 1979
2809f5d2
GC		 1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1982}
1983
0b6ac343
NHE		 1984/*
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1987 */
e011c663 1988static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1989{
1990 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1991
e011c663 1992 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1993 return 0;
1994
533558bc
JK		 1995 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1996 vmcs_read32(VM_EXIT_INTR_INFO),
1997 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1998 return 1;
1999}
2000
298101da 2001static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2002 bool has_error_code, u32 error_code,
2003 bool reinject)
298101da 2004{
77ab6db0 2005 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2006 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2007
e011c663
GN		 2008 if (!reinject && is_guest_mode(vcpu) &&
2009 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2010 return;
2011
8ab2d2e2 2012 if (has_error_code) {
77ab6db0 2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2014 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2015 }
77ab6db0 2016
7ffd92c5 2017 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2018 int inc_eip = 0;
2019 if (kvm_exception_is_soft(nr))
2020 inc_eip = vcpu->arch.event_exit_inst_len;
2021 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2023 return;
2024 }
2025
66fd3f7f
GN		 2026 if (kvm_exception_is_soft(nr)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2028 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2029 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2030 } else
2031 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2032
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2034}
2035
4e47c7a6
SY		 2036static bool vmx_rdtscp_supported(void)
2037{
2038 return cpu_has_vmx_rdtscp();
2039}
2040
ad756a16
MJ		 2041static bool vmx_invpcid_supported(void)
2042{
2043 return cpu_has_vmx_invpcid() && enable_ept;
2044}
2045
a75beee6
ED		 2046/*
2047 * Swap MSR entry in host/guest MSR entry array.
2048 */
8b9cf98c 2049static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2050{
26bb0981 2051 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2052
2053 tmp = vmx->guest_msrs[to];
2054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2055 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2056}
2057
8d14695f
YZ		 2058static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2059{
2060 unsigned long *msr_bitmap;
2061
2062 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2065 else
2066 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2067 } else {
2068 if (is_long_mode(vcpu))
2069 msr_bitmap = vmx_msr_bitmap_longmode;
2070 else
2071 msr_bitmap = vmx_msr_bitmap_legacy;
2072 }
2073
2074 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2075}
2076
e38aea3e
AK		 2077/*
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2081 */
8b9cf98c 2082static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2083{
26bb0981 2084 int save_nmsrs, index;
e38aea3e 2085
a75beee6
ED		 2086 save_nmsrs = 0;
2087#ifdef CONFIG_X86_64
8b9cf98c 2088 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2089 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2090 if (index >= 0)
8b9cf98c
RR		 2091 move_msr_up(vmx, index, save_nmsrs++);
2092 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2093 if (index >= 0)
8b9cf98c
RR		 2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2096 if (index >= 0)
8b9cf98c 2097 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2098 index = __find_msr_index(vmx, MSR_TSC_AUX);
2099 if (index >= 0 && vmx->rdtscp_enabled)
2100 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2101 /*
8c06585d 2102 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2103 * if efer.sce is enabled.
2104 */
8c06585d 2105 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2106 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2107 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2108 }
2109#endif
92c0d900
AK		 2110 index = __find_msr_index(vmx, MSR_EFER);
2111 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2112 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2113
26bb0981 2114 vmx->save_nmsrs = save_nmsrs;
5897297b 2115
8d14695f
YZ		 2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2118}
2119
6aa8b732
AK		 2120/*
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2123 */
2124static u64 guest_read_tsc(void)
2125{
2126 u64 host_tsc, tsc_offset;
2127
2128 rdtscll(host_tsc);
2129 tsc_offset = vmcs_read64(TSC_OFFSET);
2130 return host_tsc + tsc_offset;
2131}
2132
d5c1785d
NHE		 2133/*
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2136 */
886b470c 2137u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2138{
886b470c 2139 u64 tsc_offset;
d5c1785d 2140
d5c1785d
NHE		 2141 tsc_offset = is_guest_mode(vcpu) ?
2142 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2143 vmcs_read64(TSC_OFFSET);
2144 return host_tsc + tsc_offset;
2145}
2146
4051b188 2147/*
cc578287
ZA		 2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
4051b188 2150 */
cc578287 2151static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2152{
cc578287
ZA		 2153 if (!scale)
2154 return;
2155
2156 if (user_tsc_khz > tsc_khz) {
2157 vcpu->arch.tsc_catchup = 1;
2158 vcpu->arch.tsc_always_catchup = 1;
2159 } else
2160 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2161}
2162
ba904635
WA		 2163static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2164{
2165 return vmcs_read64(TSC_OFFSET);
2166}
2167
6aa8b732 2168/*
99e3e30a 2169 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2170 */
99e3e30a 2171static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2172{
27fc51b2 2173 if (is_guest_mode(vcpu)) {
7991825b 2174 /*
27fc51b2
NHE		 2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
7991825b 2179 */
27fc51b2
NHE		 2180 struct vmcs12 *vmcs12;
2181 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12 = get_vmcs12(vcpu);
2184 vmcs_write64(TSC_OFFSET, offset +
2185 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2186 vmcs12->tsc_offset : 0));
2187 } else {
489223ed
YY		 2188 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2189 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2190 vmcs_write64(TSC_OFFSET, offset);
2191 }
6aa8b732
AK		 2192}
2193
f1e2b260 2194static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2195{
2196 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2197
e48672fa 2198 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2199 if (is_guest_mode(vcpu)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2202 } else
2203 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2204 offset + adjustment);
e48672fa
ZA		 2205}
2206
857e4099
JR		 2207static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2208{
2209 return target_tsc - native_read_tsc();
2210}
2211
801d3424
NHE		 2212static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2213{
2214 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2215 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2216}
2217
2218/*
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2223 */
2224static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2225{
2226 return nested && guest_cpuid_has_vmx(vcpu);
2227}
2228
b87a51ae
NHE		 2229/*
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2239 * or other means.
2240 */
2241static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2242static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2243static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2244static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2245static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2246static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2247static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2248static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2249static __init void nested_vmx_setup_ctls_msrs(void)
2250{
2251 /*
2252 * Note that as a general rule, the high half of the MSRs (bits in
2253 * the control fields which may be 1) should be initialized by the
2254 * intersection of the underlying hardware's MSR (i.e., features which
2255 * can be supported) and the list of features we want to expose -
2256 * because they are known to be properly supported in our code.
2257 * Also, usually, the low half of the MSRs (bits which must be 1) can
2258 * be set to 0, meaning that L1 may turn off any of these bits. The
2259 * reason is that if one of these bits is necessary, it will appear
2260 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2261 * fields of vmcs01 and vmcs02, will turn these bits off - and
2262 * nested_vmx_exit_handled() will not pass related exits to L1.
2263 * These rules have exceptions below.
2264 */
2265
2266 /* pin-based controls */
eabeaacc
JK		 2267 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2268 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2269 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2270 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2271 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2272 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2273 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2274
3dbcd8da 2275 /* exit controls */
c0dfee58
ACL		 2276 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2277 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2278 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2279
c0dfee58 2280 nested_vmx_exit_ctls_high &=
b87a51ae 2281#ifdef CONFIG_X86_64
c0dfee58 2282 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2283#endif
f4124500
JK		 2284 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2285 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2286 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2287 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2288
36be0b9d
PB		 2289 if (vmx_mpx_supported())
2290 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae
NHE		 2291
2292 /* entry controls */
2293 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2294 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2295 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2296 nested_vmx_entry_ctls_high &=
57435349
JK		 2297#ifdef CONFIG_X86_64
2298 VM_ENTRY_IA32E_MODE |
2299#endif
2300 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2301 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2302 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2303 if (vmx_mpx_supported())
2304 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2305
b87a51ae
NHE		 2306 /* cpu-based controls */
2307 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2308 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2309 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2310 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2311 CPU_BASED_VIRTUAL_INTR_PENDING |
2312 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2313 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2314 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2315 CPU_BASED_CR3_STORE_EXITING |
2316#ifdef CONFIG_X86_64
2317 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2318#endif
2319 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2320 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2321 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2322 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2323 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2324 /*
2325 * We can allow some features even when not supported by the
2326 * hardware. For example, L1 can specify an MSR bitmap - and we
2327 * can use it to avoid exits to L1 - even when L0 runs L2
2328 * without MSR bitmaps.
2329 */
560b7ee1
JK		 2330 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2331 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2332
3dcdf3ec
JK		 2333 /* We support free control of CR3 access interception. */
2334 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2335 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2336
b87a51ae
NHE		 2337 /* secondary cpu-based controls */
2338 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2339 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2340 nested_vmx_secondary_ctls_low = 0;
2341 nested_vmx_secondary_ctls_high &=
d6851fbe 2342 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2343 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2344 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2345
afa61f75
NHE		 2346 if (enable_ept) {
2347 /* nested EPT: emulate EPT also to L1 */
2348 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2349 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2350 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2351 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2352 nested_vmx_ept_caps &= vmx_capability.ept;
2353 /*
4b855078
BD		 2354 * For nested guests, we don't do anything specific
2355 * for single context invalidation. Hence, only advertise
2356 * support for global context invalidation.
afa61f75 2357 */
4b855078 2358 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2359 } else
2360 nested_vmx_ept_caps = 0;
2361
c18911a2
JK		 2362 /* miscellaneous data */
2363 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2364 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2365 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2366 VMX_MISC_ACTIVITY_HLT;
c18911a2 2367 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2368}
2369
2370static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2371{
2372 /*
2373 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2374 */
2375 return ((control & high) | low) == control;
2376}
2377
2378static inline u64 vmx_control_msr(u32 low, u32 high)
2379{
2380 return low | ((u64)high << 32);
2381}
2382
cae50139 2383/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2384static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2385{
b87a51ae 2386 switch (msr_index) {
b87a51ae
NHE		 2387 case MSR_IA32_VMX_BASIC:
2388 /*
2389 * This MSR reports some information about VMX support. We
2390 * should return information about the VMX we emulate for the
2391 * guest, and the VMCS structure we give it - not about the
2392 * VMX support of the underlying hardware.
2393 */
3dbcd8da 2394 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2395 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2396 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2397 break;
2398 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2399 case MSR_IA32_VMX_PINBASED_CTLS:
2400 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2401 nested_vmx_pinbased_ctls_high);
2402 break;
2403 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2404 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2405 nested_vmx_procbased_ctls_high);
2406 break;
b87a51ae
NHE		 2407 case MSR_IA32_VMX_PROCBASED_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2409 nested_vmx_procbased_ctls_high);
2410 break;
2411 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2412 case MSR_IA32_VMX_EXIT_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2414 nested_vmx_exit_ctls_high);
2415 break;
2416 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2417 case MSR_IA32_VMX_ENTRY_CTLS:
2418 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2419 nested_vmx_entry_ctls_high);
2420 break;
2421 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2422 *pdata = vmx_control_msr(nested_vmx_misc_low,
2423 nested_vmx_misc_high);
b87a51ae
NHE		 2424 break;
2425 /*
2426 * These MSRs specify bits which the guest must keep fixed (on or off)
2427 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428 * We picked the standard core2 setting.
2429 */
2430#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2432 case MSR_IA32_VMX_CR0_FIXED0:
2433 *pdata = VMXON_CR0_ALWAYSON;
2434 break;
2435 case MSR_IA32_VMX_CR0_FIXED1:
2436 *pdata = -1ULL;
2437 break;
2438 case MSR_IA32_VMX_CR4_FIXED0:
2439 *pdata = VMXON_CR4_ALWAYSON;
2440 break;
2441 case MSR_IA32_VMX_CR4_FIXED1:
2442 *pdata = -1ULL;
2443 break;
2444 case MSR_IA32_VMX_VMCS_ENUM:
2445 *pdata = 0x1f;
2446 break;
2447 case MSR_IA32_VMX_PROCBASED_CTLS2:
2448 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2449 nested_vmx_secondary_ctls_high);
2450 break;
2451 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2452 /* Currently, no nested vpid support */
2453 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2454 break;
2455 default:
b87a51ae 2456 return 1;
b3897a49
NHE		 2457 }
2458
b87a51ae
NHE		 2459 return 0;
2460}
2461
6aa8b732
AK		 2462/*
2463 * Reads an msr value (of 'msr_index') into 'pdata'.
2464 * Returns 0 on success, non-0 otherwise.
2465 * Assumes vcpu_load() was already called.
2466 */
2467static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2468{
2469 u64 data;
26bb0981 2470 struct shared_msr_entry *msr;
6aa8b732
AK		 2471
2472 if (!pdata) {
2473 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2474 return -EINVAL;
2475 }
2476
2477 switch (msr_index) {
05b3e0c2 2478#ifdef CONFIG_X86_64
6aa8b732
AK		 2479 case MSR_FS_BASE:
2480 data = vmcs_readl(GUEST_FS_BASE);
2481 break;
2482 case MSR_GS_BASE:
2483 data = vmcs_readl(GUEST_GS_BASE);
2484 break;
44ea2b17
AK		 2485 case MSR_KERNEL_GS_BASE:
2486 vmx_load_host_state(to_vmx(vcpu));
2487 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2488 break;
26bb0981 2489#endif
6aa8b732 2490 case MSR_EFER:
3bab1f5d 2491 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2492 case MSR_IA32_TSC:
6aa8b732
AK		 2493 data = guest_read_tsc();
2494 break;
2495 case MSR_IA32_SYSENTER_CS:
2496 data = vmcs_read32(GUEST_SYSENTER_CS);
2497 break;
2498 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2499 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2500 break;
2501 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2502 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2503 break;
0dd376e7 2504 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2505 if (!vmx_mpx_supported())
2506 return 1;
0dd376e7
LJ		 2507 data = vmcs_read64(GUEST_BNDCFGS);
2508 break;
cae50139
JK		 2509 case MSR_IA32_FEATURE_CONTROL:
2510 if (!nested_vmx_allowed(vcpu))
2511 return 1;
2512 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2513 break;
2514 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2515 if (!nested_vmx_allowed(vcpu))
2516 return 1;
2517 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2518 case MSR_TSC_AUX:
2519 if (!to_vmx(vcpu)->rdtscp_enabled)
2520 return 1;
2521 /* Otherwise falls through */
6aa8b732 2522 default:
8b9cf98c 2523 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2524 if (msr) {
2525 data = msr->data;
2526 break;
6aa8b732 2527 }
3bab1f5d 2528 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2529 }
2530
2531 *pdata = data;
2532 return 0;
2533}
2534
cae50139
JK		 2535static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2536
6aa8b732
AK		 2537/*
2538 * Writes msr value into into the appropriate "register".
2539 * Returns 0 on success, non-0 otherwise.
2540 * Assumes vcpu_load() was already called.
2541 */
8fe8ab46 2542static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2543{
a2fa3e9f 2544 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2545 struct shared_msr_entry *msr;
2cc51560 2546 int ret = 0;
8fe8ab46
WA		 2547 u32 msr_index = msr_info->index;
2548 u64 data = msr_info->data;
2cc51560 2549
6aa8b732 2550 switch (msr_index) {
3bab1f5d 2551 case MSR_EFER:
8fe8ab46 2552 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2553 break;
16175a79 2554#ifdef CONFIG_X86_64
6aa8b732 2555 case MSR_FS_BASE:
2fb92db1 2556 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2557 vmcs_writel(GUEST_FS_BASE, data);
2558 break;
2559 case MSR_GS_BASE:
2fb92db1 2560 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2561 vmcs_writel(GUEST_GS_BASE, data);
2562 break;
44ea2b17
AK		 2563 case MSR_KERNEL_GS_BASE:
2564 vmx_load_host_state(vmx);
2565 vmx->msr_guest_kernel_gs_base = data;
2566 break;
6aa8b732
AK		 2567#endif
2568 case MSR_IA32_SYSENTER_CS:
2569 vmcs_write32(GUEST_SYSENTER_CS, data);
2570 break;
2571 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2572 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2573 break;
2574 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2575 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2576 break;
0dd376e7 2577 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2578 if (!vmx_mpx_supported())
2579 return 1;
0dd376e7
LJ		 2580 vmcs_write64(GUEST_BNDCFGS, data);
2581 break;
af24a4e4 2582 case MSR_IA32_TSC:
8fe8ab46 2583 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2584 break;
468d472f
SY		 2585 case MSR_IA32_CR_PAT:
2586 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2587 vmcs_write64(GUEST_IA32_PAT, data);
2588 vcpu->arch.pat = data;
2589 break;
2590 }
8fe8ab46 2591 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2592 break;
ba904635
WA		 2593 case MSR_IA32_TSC_ADJUST:
2594 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2595 break;
cae50139
JK		 2596 case MSR_IA32_FEATURE_CONTROL:
2597 if (!nested_vmx_allowed(vcpu) ||
2598 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2599 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2600 return 1;
2601 vmx->nested.msr_ia32_feature_control = data;
2602 if (msr_info->host_initiated && data == 0)
2603 vmx_leave_nested(vcpu);
2604 break;
2605 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2606 return 1; /* they are read-only */
4e47c7a6
SY		 2607 case MSR_TSC_AUX:
2608 if (!vmx->rdtscp_enabled)
2609 return 1;
2610 /* Check reserved bit, higher 32 bits should be zero */
2611 if ((data >> 32) != 0)
2612 return 1;
2613 /* Otherwise falls through */
6aa8b732 2614 default:
8b9cf98c 2615 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2616 if (msr) {
2617 msr->data = data;
2225fd56
AK		 2618 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2619 preempt_disable();
9ee73970
AK		 2620 kvm_set_shared_msr(msr->index, msr->data,
2621 msr->mask);
2225fd56
AK		 2622 preempt_enable();
2623 }
3bab1f5d 2624 break;
6aa8b732 2625 }
8fe8ab46 2626 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2627 }
2628
2cc51560 2629 return ret;
6aa8b732
AK		 2630}
2631
5fdbf976 2632static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2633{
5fdbf976
MT		 2634 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2635 switch (reg) {
2636 case VCPU_REGS_RSP:
2637 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2638 break;
2639 case VCPU_REGS_RIP:
2640 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2641 break;
6de4f3ad
AK		 2642 case VCPU_EXREG_PDPTR:
2643 if (enable_ept)
2644 ept_save_pdptrs(vcpu);
2645 break;
5fdbf976
MT		 2646 default:
2647 break;
2648 }
6aa8b732
AK		 2649}
2650
6aa8b732
AK		 2651static __init int cpu_has_kvm_support(void)
2652{
6210e37b 2653 return cpu_has_vmx();
6aa8b732
AK		 2654}
2655
2656static __init int vmx_disabled_by_bios(void)
2657{
2658 u64 msr;
2659
2660 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2661 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2662 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2663 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2664 && tboot_enabled())
2665 return 1;
23f3e991 2666 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2667 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2668 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2669 && !tboot_enabled()) {
2670 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2671 "activate TXT before enabling KVM\n");
cafd6659 2672 return 1;
f9335afe 2673 }
23f3e991
JC		 2674 /* launched w/o TXT and VMX disabled */
2675 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2676 && !tboot_enabled())
2677 return 1;
cafd6659
SW		 2678 }
2679
2680 return 0;
6aa8b732
AK		 2681}
2682
7725b894
DX		 2683static void kvm_cpu_vmxon(u64 addr)
2684{
2685 asm volatile (ASM_VMX_VMXON_RAX
2686 : : "a"(&addr), "m"(addr)
2687 : "memory", "cc");
2688}
2689
10474ae8 2690static int hardware_enable(void *garbage)
6aa8b732
AK		 2691{
2692 int cpu = raw_smp_processor_id();
2693 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2694 u64 old, test_bits;
6aa8b732 2695
10474ae8
AG		 2696 if (read_cr4() & X86_CR4_VMXE)
2697 return -EBUSY;
2698
d462b819 2699 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2700
2701 /*
2702 * Now we can enable the vmclear operation in kdump
2703 * since the loaded_vmcss_on_cpu list on this cpu
2704 * has been initialized.
2705 *
2706 * Though the cpu is not in VMX operation now, there
2707 * is no problem to enable the vmclear operation
2708 * for the loaded_vmcss_on_cpu list is empty!
2709 */
2710 crash_enable_local_vmclear(cpu);
2711
6aa8b732 2712 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2713
2714 test_bits = FEATURE_CONTROL_LOCKED;
2715 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2716 if (tboot_enabled())
2717 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2718
2719 if ((old & test_bits) != test_bits) {
6aa8b732 2720 /* enable and lock */
cafd6659
SW		 2721 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2722 }
66aee91a 2723 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2724
4610c9cc
DX		 2725 if (vmm_exclusive) {
2726 kvm_cpu_vmxon(phys_addr);
2727 ept_sync_global();
2728 }
10474ae8 2729
357d1226 2730 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2731
10474ae8 2732 return 0;
6aa8b732
AK		 2733}
2734
d462b819 2735static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2736{
2737 int cpu = raw_smp_processor_id();
d462b819 2738 struct loaded_vmcs *v, *n;
543e4243 2739
d462b819
NHE		 2740 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2741 loaded_vmcss_on_cpu_link)
2742 __loaded_vmcs_clear(v);
543e4243
AK		 2743}
2744
710ff4a8
EH		 2745
2746/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2747 * tricks.
2748 */
2749static void kvm_cpu_vmxoff(void)
6aa8b732 2750{
4ecac3fd 2751 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2752}
2753
710ff4a8
EH		 2754static void hardware_disable(void *garbage)
2755{
4610c9cc 2756 if (vmm_exclusive) {
d462b819 2757 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2758 kvm_cpu_vmxoff();
2759 }
7725b894 2760 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2761}
2762
1c3d14fe 2763static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2764 u32 msr, u32 *result)
1c3d14fe
YS		 2765{
2766 u32 vmx_msr_low, vmx_msr_high;
2767 u32 ctl = ctl_min | ctl_opt;
2768
2769 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2770
2771 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2772 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2773
2774 /* Ensure minimum (required) set of control bits are supported. */
2775 if (ctl_min & ~ctl)
002c7f7c 2776 return -EIO;
1c3d14fe
YS		 2777
2778 *result = ctl;
2779 return 0;
2780}
2781
110312c8
AK		 2782static __init bool allow_1_setting(u32 msr, u32 ctl)
2783{
2784 u32 vmx_msr_low, vmx_msr_high;
2785
2786 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2787 return vmx_msr_high & ctl;
2788}
2789
002c7f7c 2790static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2791{
2792 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2793 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2794 u32 _pin_based_exec_control = 0;
2795 u32 _cpu_based_exec_control = 0;
f78e0e2e 2796 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2797 u32 _vmexit_control = 0;
2798 u32 _vmentry_control = 0;
2799
10166744 2800 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2801#ifdef CONFIG_X86_64
2802 CPU_BASED_CR8_LOAD_EXITING |
2803 CPU_BASED_CR8_STORE_EXITING |
2804#endif
d56f546d
SY		 2805 CPU_BASED_CR3_LOAD_EXITING |
2806 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2807 CPU_BASED_USE_IO_BITMAPS |
2808 CPU_BASED_MOV_DR_EXITING |
a7052897 2809 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2810 CPU_BASED_MWAIT_EXITING |
2811 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2812 CPU_BASED_INVLPG_EXITING |
2813 CPU_BASED_RDPMC_EXITING;
443381a8 2814
f78e0e2e 2815 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2816 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2817 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2818 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2819 &_cpu_based_exec_control) < 0)
002c7f7c 2820 return -EIO;
6e5d865c
YS		 2821#ifdef CONFIG_X86_64
2822 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2823 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2824 ~CPU_BASED_CR8_STORE_EXITING;
2825#endif
f78e0e2e 2826 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2827 min2 = 0;
2828 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2829 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2830 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2831 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2832 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2833 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2834 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2835 SECONDARY_EXEC_RDTSCP |
83d4c286 2836 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2837 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2838 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2839 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2840 if (adjust_vmx_controls(min2, opt2,
2841 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2842 &_cpu_based_2nd_exec_control) < 0)
2843 return -EIO;
2844 }
2845#ifndef CONFIG_X86_64
2846 if (!(_cpu_based_2nd_exec_control &
2847 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2848 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2849#endif
83d4c286
YZ		 2850
2851 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2852 _cpu_based_2nd_exec_control &= ~(
8d14695f 2853 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2854 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2855 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2856
d56f546d 2857 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2858 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2859 enabled */
5fff7d27
GN		 2860 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2861 CPU_BASED_CR3_STORE_EXITING |
2862 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2863 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2864 vmx_capability.ept, vmx_capability.vpid);
2865 }
1c3d14fe 2866
81908bf4 2867 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2868#ifdef CONFIG_X86_64
2869 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2870#endif
a547c6db 2871 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2872 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2873 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2874 &_vmexit_control) < 0)
002c7f7c 2875 return -EIO;
1c3d14fe 2876
01e439be
YZ		 2877 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2878 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2879 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2880 &_pin_based_exec_control) < 0)
2881 return -EIO;
2882
2883 if (!(_cpu_based_2nd_exec_control &
2884 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2885 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2886 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2887
c845f9c6 2888 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2889 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2890 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2891 &_vmentry_control) < 0)
002c7f7c 2892 return -EIO;
6aa8b732 2893
c68876fd 2894 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2895
2896 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2898 return -EIO;
1c3d14fe
YS		 2899
2900#ifdef CONFIG_X86_64
2901 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902 if (vmx_msr_high & (1u<<16))
002c7f7c 2903 return -EIO;
1c3d14fe
YS		 2904#endif
2905
2906 /* Require Write-Back (WB) memory type for VMCS accesses. */
2907 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2908 return -EIO;
1c3d14fe 2909
002c7f7c
YS		 2910 vmcs_conf->size = vmx_msr_high & 0x1fff;
2911 vmcs_conf->order = get_order(vmcs_config.size);
2912 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2913
002c7f7c
YS		 2914 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2915 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2916 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2917 vmcs_conf->vmexit_ctrl = _vmexit_control;
2918 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2919
110312c8
AK		 2920 cpu_has_load_ia32_efer =
2921 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2922 VM_ENTRY_LOAD_IA32_EFER)
2923 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2924 VM_EXIT_LOAD_IA32_EFER);
2925
8bf00a52
GN		 2926 cpu_has_load_perf_global_ctrl =
2927 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2928 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2929 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2931
2932 /*
2933 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934 * but due to arrata below it can't be used. Workaround is to use
2935 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2936 *
2937 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2938 *
2939 * AAK155 (model 26)
2940 * AAP115 (model 30)
2941 * AAT100 (model 37)
2942 * BC86,AAY89,BD102 (model 44)
2943 * BA97 (model 46)
2944 *
2945 */
2946 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2947 switch (boot_cpu_data.x86_model) {
2948 case 26:
2949 case 30:
2950 case 37:
2951 case 44:
2952 case 46:
2953 cpu_has_load_perf_global_ctrl = false;
2954 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955 "does not work properly. Using workaround\n");
2956 break;
2957 default:
2958 break;
2959 }
2960 }
2961
1c3d14fe 2962 return 0;
c68876fd 2963}
6aa8b732
AK		 2964
2965static struct vmcs *alloc_vmcs_cpu(int cpu)
2966{
2967 int node = cpu_to_node(cpu);
2968 struct page *pages;
2969 struct vmcs *vmcs;
2970
6484eb3e 2971 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2972 if (!pages)
2973 return NULL;
2974 vmcs = page_address(pages);
1c3d14fe
YS		 2975 memset(vmcs, 0, vmcs_config.size);
2976 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2977 return vmcs;
2978}
2979
2980static struct vmcs *alloc_vmcs(void)
2981{
d3b2c338 2982 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2983}
2984
2985static void free_vmcs(struct vmcs *vmcs)
2986{
1c3d14fe 2987 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2988}
2989
d462b819
NHE		 2990/*
2991 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2992 */
2993static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2994{
2995 if (!loaded_vmcs->vmcs)
2996 return;
2997 loaded_vmcs_clear(loaded_vmcs);
2998 free_vmcs(loaded_vmcs->vmcs);
2999 loaded_vmcs->vmcs = NULL;
3000}
3001
39959588 3002static void free_kvm_area(void)
6aa8b732
AK		 3003{
3004 int cpu;
3005
3230bb47 3006 for_each_possible_cpu(cpu) {
6aa8b732 3007 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3008 per_cpu(vmxarea, cpu) = NULL;
3009 }
6aa8b732
AK		 3010}
3011
fe2b201b
BD		 3012static void init_vmcs_shadow_fields(void)
3013{
3014 int i, j;
3015
3016 /* No checks for read only fields yet */
3017
3018 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3019 switch (shadow_read_write_fields[i]) {
3020 case GUEST_BNDCFGS:
3021 if (!vmx_mpx_supported())
3022 continue;
3023 break;
3024 default:
3025 break;
3026 }
3027
3028 if (j < i)
3029 shadow_read_write_fields[j] =
3030 shadow_read_write_fields[i];
3031 j++;
3032 }
3033 max_shadow_read_write_fields = j;
3034
3035 /* shadowed fields guest access without vmexit */
3036 for (i = 0; i < max_shadow_read_write_fields; i++) {
3037 clear_bit(shadow_read_write_fields[i],
3038 vmx_vmwrite_bitmap);
3039 clear_bit(shadow_read_write_fields[i],
3040 vmx_vmread_bitmap);
3041 }
3042 for (i = 0; i < max_shadow_read_only_fields; i++)
3043 clear_bit(shadow_read_only_fields[i],
3044 vmx_vmread_bitmap);
3045}
3046
6aa8b732
AK		 3047static __init int alloc_kvm_area(void)
3048{
3049 int cpu;
3050
3230bb47 3051 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3052 struct vmcs *vmcs;
3053
3054 vmcs = alloc_vmcs_cpu(cpu);
3055 if (!vmcs) {
3056 free_kvm_area();
3057 return -ENOMEM;
3058 }
3059
3060 per_cpu(vmxarea, cpu) = vmcs;
3061 }
3062 return 0;
3063}
3064
3065static __init int hardware_setup(void)
3066{
002c7f7c
YS		 3067 if (setup_vmcs_config(&vmcs_config) < 0)
3068 return -EIO;
50a37eb4
JR		 3069
3070 if (boot_cpu_has(X86_FEATURE_NX))
3071 kvm_enable_efer_bits(EFER_NX);
3072
93ba03c2
SY		 3073 if (!cpu_has_vmx_vpid())
3074 enable_vpid = 0;
abc4fc58
AG		 3075 if (!cpu_has_vmx_shadow_vmcs())
3076 enable_shadow_vmcs = 0;
fe2b201b
BD		 3077 if (enable_shadow_vmcs)
3078 init_vmcs_shadow_fields();
93ba03c2 3079
4bc9b982
SY		 3080 if (!cpu_has_vmx_ept() ||
3081 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3082 enable_ept = 0;
3a624e29 3083 enable_unrestricted_guest = 0;
83c3a331 3084 enable_ept_ad_bits = 0;
3a624e29
NK		 3085 }
3086
83c3a331
XH		 3087 if (!cpu_has_vmx_ept_ad_bits())
3088 enable_ept_ad_bits = 0;
3089
3a624e29
NK		 3090 if (!cpu_has_vmx_unrestricted_guest())
3091 enable_unrestricted_guest = 0;
93ba03c2
SY		 3092
3093 if (!cpu_has_vmx_flexpriority())
3094 flexpriority_enabled = 0;
3095
95ba8273
GN		 3096 if (!cpu_has_vmx_tpr_shadow())
3097 kvm_x86_ops->update_cr8_intercept = NULL;
3098
54dee993
MT		 3099 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3100 kvm_disable_largepages();
3101
4b8d54f9
ZE		 3102 if (!cpu_has_vmx_ple())
3103 ple_gap = 0;
3104
01e439be
YZ		 3105 if (!cpu_has_vmx_apicv())
3106 enable_apicv = 0;
c7c9c56c 3107
01e439be 3108 if (enable_apicv)
c7c9c56c 3109 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3110 else {
c7c9c56c 3111 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3112 kvm_x86_ops->deliver_posted_interrupt = NULL;
3113 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3114 }
83d4c286 3115
b87a51ae
NHE		 3116 if (nested)
3117 nested_vmx_setup_ctls_msrs();
3118
6aa8b732
AK		 3119 return alloc_kvm_area();
3120}
3121
3122static __exit void hardware_unsetup(void)
3123{
3124 free_kvm_area();
3125}
3126
14168786
GN		 3127static bool emulation_required(struct kvm_vcpu *vcpu)
3128{
3129 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3130}
3131
91b0aa2c 3132static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3133 struct kvm_segment *save)
6aa8b732 3134{
d99e4152
GN		 3135 if (!emulate_invalid_guest_state) {
3136 /*
3137 * CS and SS RPL should be equal during guest entry according
3138 * to VMX spec, but in reality it is not always so. Since vcpu
3139 * is in the middle of the transition from real mode to
3140 * protected mode it is safe to assume that RPL 0 is a good
3141 * default value.
3142 */
3143 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3144 save->selector &= ~SELECTOR_RPL_MASK;
3145 save->dpl = save->selector & SELECTOR_RPL_MASK;
3146 save->s = 1;
6aa8b732 3147 }
d99e4152 3148 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3149}
3150
3151static void enter_pmode(struct kvm_vcpu *vcpu)
3152{
3153 unsigned long flags;
a89a8fb9 3154 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3155
d99e4152
GN		 3156 /*
3157 * Update real mode segment cache. It may be not up-to-date if sement
3158 * register was written while vcpu was in a guest mode.
3159 */
3160 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3161 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3162 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3163 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3164 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3165 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3166
7ffd92c5 3167 vmx->rmode.vm86_active = 0;
6aa8b732 3168
2fb92db1
AK		 3169 vmx_segment_cache_clear(vmx);
3170
f5f7b2fe 3171 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3172
3173 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3174 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3175 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3176 vmcs_writel(GUEST_RFLAGS, flags);
3177
66aee91a
RR		 3178 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3179 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3180
3181 update_exception_bitmap(vcpu);
3182
91b0aa2c
GN		 3183 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3184 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3185 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3186 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3187 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3188 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3189}
3190
f5f7b2fe 3191static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3192{
772e0318 3193 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3194 struct kvm_segment var = *save;
3195
3196 var.dpl = 0x3;
3197 if (seg == VCPU_SREG_CS)
3198 var.type = 0x3;
3199
3200 if (!emulate_invalid_guest_state) {
3201 var.selector = var.base >> 4;
3202 var.base = var.base & 0xffff0;
3203 var.limit = 0xffff;
3204 var.g = 0;
3205 var.db = 0;
3206 var.present = 1;
3207 var.s = 1;
3208 var.l = 0;
3209 var.unusable = 0;
3210 var.type = 0x3;
3211 var.avl = 0;
3212 if (save->base & 0xf)
3213 printk_once(KERN_WARNING "kvm: segment base is not "
3214 "paragraph aligned when entering "
3215 "protected mode (seg=%d)", seg);
3216 }
6aa8b732 3217
d99e4152
GN		 3218 vmcs_write16(sf->selector, var.selector);
3219 vmcs_write32(sf->base, var.base);
3220 vmcs_write32(sf->limit, var.limit);
3221 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3222}
3223
3224static void enter_rmode(struct kvm_vcpu *vcpu)
3225{
3226 unsigned long flags;
a89a8fb9 3227 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3228
f5f7b2fe
AK		 3229 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3230 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3231 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3232 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3233 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3234 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3235 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3236
7ffd92c5 3237 vmx->rmode.vm86_active = 1;
6aa8b732 3238
776e58ea
GN		 3239 /*
3240 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3241 * vcpu. Warn the user that an update is overdue.
776e58ea 3242 */
4918c6ca 3243 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3244 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3245 "called before entering vcpu\n");
776e58ea 3246
2fb92db1
AK		 3247 vmx_segment_cache_clear(vmx);
3248
4918c6ca 3249 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3250 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3251 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3252
3253 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3254 vmx->rmode.save_rflags = flags;
6aa8b732 3255
053de044 3256 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3257
3258 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3259 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3260 update_exception_bitmap(vcpu);
3261
d99e4152
GN		 3262 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3263 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3264 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3265 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3266 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3267 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3268
8668a3c4 3269 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3270}
3271
401d10de
AS		 3272static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3273{
3274 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3275 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3276
3277 if (!msr)
3278 return;
401d10de 3279
44ea2b17
AK		 3280 /*
3281 * Force kernel_gs_base reloading before EFER changes, as control
3282 * of this msr depends on is_long_mode().
3283 */
3284 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3285 vcpu->arch.efer = efer;
401d10de 3286 if (efer & EFER_LMA) {
2961e876 3287 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3288 msr->data = efer;
3289 } else {
2961e876 3290 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3291
3292 msr->data = efer & ~EFER_LME;
3293 }
3294 setup_msrs(vmx);
3295}
3296
05b3e0c2 3297#ifdef CONFIG_X86_64
6aa8b732
AK		 3298
3299static void enter_lmode(struct kvm_vcpu *vcpu)
3300{
3301 u32 guest_tr_ar;
3302
2fb92db1
AK		 3303 vmx_segment_cache_clear(to_vmx(vcpu));
3304
6aa8b732
AK		 3305 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3306 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3307 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3308 __func__);
6aa8b732
AK		 3309 vmcs_write32(GUEST_TR_AR_BYTES,
3310 (guest_tr_ar & ~AR_TYPE_MASK)
3311 | AR_TYPE_BUSY_64_TSS);
3312 }
da38f438 3313 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3314}
3315
3316static void exit_lmode(struct kvm_vcpu *vcpu)
3317{
2961e876 3318 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3319 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3320}
3321
3322#endif
3323
2384d2b3
SY		 3324static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3325{
b9d762fa 3326 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3327 if (enable_ept) {
3328 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3329 return;
4e1096d2 3330 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3331 }
2384d2b3
SY		 3332}
3333
e8467fda
AK		 3334static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3335{
3336 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3337
3338 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3339 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3340}
3341
aff48baa
AK		 3342static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3343{
3344 if (enable_ept && is_paging(vcpu))
3345 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3346 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3347}
3348
25c4c276 3349static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3350{
fc78f519
AK		 3351 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3352
3353 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3354 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3355}
3356
1439442c
SY		 3357static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3358{
d0d538b9
GN		 3359 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3360
6de4f3ad
AK		 3361 if (!test_bit(VCPU_EXREG_PDPTR,
3362 (unsigned long *)&vcpu->arch.regs_dirty))
3363 return;
3364
1439442c 3365 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3366 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3367 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3368 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3369 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3370 }
3371}
3372
8f5d549f
AK		 3373static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3374{
d0d538b9
GN		 3375 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3376
8f5d549f 3377 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3378 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3379 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3380 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3381 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3382 }
6de4f3ad
AK		 3383
3384 __set_bit(VCPU_EXREG_PDPTR,
3385 (unsigned long *)&vcpu->arch.regs_avail);
3386 __set_bit(VCPU_EXREG_PDPTR,
3387 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3388}
3389
5e1746d6 3390static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3391
3392static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3393 unsigned long cr0,
3394 struct kvm_vcpu *vcpu)
3395{
5233dd51
MT		 3396 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3397 vmx_decache_cr3(vcpu);
1439442c
SY		 3398 if (!(cr0 & X86_CR0_PG)) {
3399 /* From paging/starting to nonpaging */
3400 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3401 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3402 (CPU_BASED_CR3_LOAD_EXITING |
3403 CPU_BASED_CR3_STORE_EXITING));
3404 vcpu->arch.cr0 = cr0;
fc78f519 3405 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3406 } else if (!is_paging(vcpu)) {
3407 /* From nonpaging to paging */
3408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3409 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3410 ~(CPU_BASED_CR3_LOAD_EXITING |
3411 CPU_BASED_CR3_STORE_EXITING));
3412 vcpu->arch.cr0 = cr0;
fc78f519 3413 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3414 }
95eb84a7
SY		 3415
3416 if (!(cr0 & X86_CR0_WP))
3417 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3418}
3419
6aa8b732
AK		 3420static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3421{
7ffd92c5 3422 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3423 unsigned long hw_cr0;
3424
5037878e 3425 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3426 if (enable_unrestricted_guest)
5037878e 3427 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3428 else {
5037878e 3429 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3430
218e763f
GN		 3431 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3432 enter_pmode(vcpu);
6aa8b732 3433
218e763f
GN		 3434 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3435 enter_rmode(vcpu);
3436 }
6aa8b732 3437
05b3e0c2 3438#ifdef CONFIG_X86_64
f6801dff 3439 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3441 enter_lmode(vcpu);
707d92fa 3442 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3443 exit_lmode(vcpu);
3444 }
3445#endif
3446
089d034e 3447 if (enable_ept)
1439442c
SY		 3448 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3449
02daab21 3450 if (!vcpu->fpu_active)
81231c69 3451 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3452
6aa8b732 3453 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3454 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3455 vcpu->arch.cr0 = cr0;
14168786
GN		 3456
3457 /* depends on vcpu->arch.cr0 to be set to a new value */
3458 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3459}
3460
1439442c
SY		 3461static u64 construct_eptp(unsigned long root_hpa)
3462{
3463 u64 eptp;
3464
3465 /* TODO write the value reading from MSR */
3466 eptp = VMX_EPT_DEFAULT_MT |
3467 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3468 if (enable_ept_ad_bits)
3469 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3470 eptp |= (root_hpa & PAGE_MASK);
3471
3472 return eptp;
3473}
3474
6aa8b732
AK		 3475static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3476{
1439442c
SY		 3477 unsigned long guest_cr3;
3478 u64 eptp;
3479
3480 guest_cr3 = cr3;
089d034e 3481 if (enable_ept) {
1439442c
SY		 3482 eptp = construct_eptp(cr3);
3483 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3484 if (is_paging(vcpu) || is_guest_mode(vcpu))
3485 guest_cr3 = kvm_read_cr3(vcpu);
3486 else
3487 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3488 ept_load_pdptrs(vcpu);
1439442c
SY		 3489 }
3490
2384d2b3 3491 vmx_flush_tlb(vcpu);
1439442c 3492 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3493}
3494
5e1746d6 3495static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3496{
7ffd92c5 3497 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3498 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3499
5e1746d6
NHE		 3500 if (cr4 & X86_CR4_VMXE) {
3501 /*
3502 * To use VMXON (and later other VMX instructions), a guest
3503 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3504 * So basically the check on whether to allow nested VMX
3505 * is here.
3506 */
3507 if (!nested_vmx_allowed(vcpu))
3508 return 1;
1a0d74e6
JK		 3509 }
3510 if (to_vmx(vcpu)->nested.vmxon &&
3511 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3512 return 1;
3513
ad312c7c 3514 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3515 if (enable_ept) {
3516 if (!is_paging(vcpu)) {
3517 hw_cr4 &= ~X86_CR4_PAE;
3518 hw_cr4 |= X86_CR4_PSE;
c08800a5 3519 /*
e1e746b3
FW		 3520 * SMEP/SMAP is disabled if CPU is in non-paging mode
3521 * in hardware. However KVM always uses paging mode to
c08800a5 3522 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3523 * To emulate this behavior, SMEP/SMAP needs to be
3524 * manually disabled when guest switches to non-paging
3525 * mode.
c08800a5 3526 */
e1e746b3 3527 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3528 } else if (!(cr4 & X86_CR4_PAE)) {
3529 hw_cr4 &= ~X86_CR4_PAE;
3530 }
3531 }
1439442c
SY		 3532
3533 vmcs_writel(CR4_READ_SHADOW, cr4);
3534 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3535 return 0;
6aa8b732
AK		 3536}
3537
6aa8b732
AK		 3538static void vmx_get_segment(struct kvm_vcpu *vcpu,
3539 struct kvm_segment *var, int seg)
3540{
a9179499 3541 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3542 u32 ar;
3543
c6ad1153 3544 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3545 *var = vmx->rmode.segs[seg];
a9179499 3546 if (seg == VCPU_SREG_TR
2fb92db1 3547 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3548 return;
1390a28b
AK		 3549 var->base = vmx_read_guest_seg_base(vmx, seg);
3550 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3551 return;
a9179499 3552 }
2fb92db1
AK		 3553 var->base = vmx_read_guest_seg_base(vmx, seg);
3554 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3555 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3556 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3557 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3558 var->type = ar & 15;
3559 var->s = (ar >> 4) & 1;
3560 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3561 /*
3562 * Some userspaces do not preserve unusable property. Since usable
3563 * segment has to be present according to VMX spec we can use present
3564 * property to amend userspace bug by making unusable segment always
3565 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3566 * segment as unusable.
3567 */
3568 var->present = !var->unusable;
6aa8b732
AK		 3569 var->avl = (ar >> 12) & 1;
3570 var->l = (ar >> 13) & 1;
3571 var->db = (ar >> 14) & 1;
3572 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3573}
3574
a9179499
AK		 3575static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3576{
a9179499
AK		 3577 struct kvm_segment s;
3578
3579 if (to_vmx(vcpu)->rmode.vm86_active) {
3580 vmx_get_segment(vcpu, &s, seg);
3581 return s.base;
3582 }
2fb92db1 3583 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3584}
3585
b09408d0 3586static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3587{
b09408d0
MT		 3588 struct vcpu_vmx *vmx = to_vmx(vcpu);
3589
ae9fedc7 3590 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3591 return 0;
ae9fedc7
PB		 3592 else {
3593 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3594 return AR_DPL(ar);
69c73028 3595 }
69c73028
AK		 3596}
3597
653e3108 3598static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3599{
6aa8b732
AK		 3600 u32 ar;
3601
f0495f9b 3602 if (var->unusable || !var->present)
6aa8b732
AK		 3603 ar = 1 << 16;
3604 else {
3605 ar = var->type & 15;
3606 ar |= (var->s & 1) << 4;
3607 ar |= (var->dpl & 3) << 5;
3608 ar |= (var->present & 1) << 7;
3609 ar |= (var->avl & 1) << 12;
3610 ar |= (var->l & 1) << 13;
3611 ar |= (var->db & 1) << 14;
3612 ar |= (var->g & 1) << 15;
3613 }
653e3108
AK		 3614
3615 return ar;
3616}
3617
3618static void vmx_set_segment(struct kvm_vcpu *vcpu,
3619 struct kvm_segment *var, int seg)
3620{
7ffd92c5 3621 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3622 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3623
2fb92db1
AK		 3624 vmx_segment_cache_clear(vmx);
3625
1ecd50a9
GN		 3626 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3627 vmx->rmode.segs[seg] = *var;
3628 if (seg == VCPU_SREG_TR)
3629 vmcs_write16(sf->selector, var->selector);
3630 else if (var->s)
3631 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3632 goto out;
653e3108 3633 }
1ecd50a9 3634
653e3108
AK		 3635 vmcs_writel(sf->base, var->base);
3636 vmcs_write32(sf->limit, var->limit);
3637 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3638
3639 /*
3640 * Fix the "Accessed" bit in AR field of segment registers for older
3641 * qemu binaries.
3642 * IA32 arch specifies that at the time of processor reset the
3643 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3644 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3645 * state vmexit when "unrestricted guest" mode is turned on.
3646 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3647 * tree. Newer qemu binaries with that qemu fix would not need this
3648 * kvm hack.
3649 */
3650 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3651 var->type |= 0x1; /* Accessed */
3a624e29 3652
f924d66d 3653 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3654
3655out:
14168786 3656 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3657}
3658
6aa8b732
AK		 3659static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3660{
2fb92db1 3661 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3662
3663 *db = (ar >> 14) & 1;
3664 *l = (ar >> 13) & 1;
3665}
3666
89a27f4d 3667static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3668{
89a27f4d
GN		 3669 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3670 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3671}
3672
89a27f4d 3673static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3674{
89a27f4d
GN		 3675 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3676 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3677}
3678
89a27f4d 3679static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3680{
89a27f4d
GN		 3681 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3682 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3683}
3684
89a27f4d 3685static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3686{
89a27f4d
GN		 3687 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3688 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3689}
3690
648dfaa7
MG		 3691static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3692{
3693 struct kvm_segment var;
3694 u32 ar;
3695
3696 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3697 var.dpl = 0x3;
0647f4aa
GN		 3698 if (seg == VCPU_SREG_CS)
3699 var.type = 0x3;
648dfaa7
MG		 3700 ar = vmx_segment_access_rights(&var);
3701
3702 if (var.base != (var.selector << 4))
3703 return false;
89efbed0 3704 if (var.limit != 0xffff)
648dfaa7 3705 return false;
07f42f5f 3706 if (ar != 0xf3)
648dfaa7
MG		 3707 return false;
3708
3709 return true;
3710}
3711
3712static bool code_segment_valid(struct kvm_vcpu *vcpu)
3713{
3714 struct kvm_segment cs;
3715 unsigned int cs_rpl;
3716
3717 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3718 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3719
1872a3f4
AK		 3720 if (cs.unusable)
3721 return false;
648dfaa7
MG		 3722 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3723 return false;
3724 if (!cs.s)
3725 return false;
1872a3f4 3726 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3727 if (cs.dpl > cs_rpl)
3728 return false;
1872a3f4 3729 } else {
648dfaa7
MG		 3730 if (cs.dpl != cs_rpl)
3731 return false;
3732 }
3733 if (!cs.present)
3734 return false;
3735
3736 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3737 return true;
3738}
3739
3740static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3741{
3742 struct kvm_segment ss;
3743 unsigned int ss_rpl;
3744
3745 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3746 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3747
1872a3f4
AK		 3748 if (ss.unusable)
3749 return true;
3750 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3751 return false;
3752 if (!ss.s)
3753 return false;
3754 if (ss.dpl != ss_rpl) /* DPL != RPL */
3755 return false;
3756 if (!ss.present)
3757 return false;
3758
3759 return true;
3760}
3761
3762static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3763{
3764 struct kvm_segment var;
3765 unsigned int rpl;
3766
3767 vmx_get_segment(vcpu, &var, seg);
3768 rpl = var.selector & SELECTOR_RPL_MASK;
3769
1872a3f4
AK		 3770 if (var.unusable)
3771 return true;
648dfaa7
MG		 3772 if (!var.s)
3773 return false;
3774 if (!var.present)
3775 return false;
3776 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3777 if (var.dpl < rpl) /* DPL < RPL */
3778 return false;
3779 }
3780
3781 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3782 * rights flags
3783 */
3784 return true;
3785}
3786
3787static bool tr_valid(struct kvm_vcpu *vcpu)
3788{
3789 struct kvm_segment tr;
3790
3791 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3792
1872a3f4
AK		 3793 if (tr.unusable)
3794 return false;
648dfaa7
MG		 3795 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3796 return false;
1872a3f4 3797 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3798 return false;
3799 if (!tr.present)
3800 return false;
3801
3802 return true;
3803}
3804
3805static bool ldtr_valid(struct kvm_vcpu *vcpu)
3806{
3807 struct kvm_segment ldtr;
3808
3809 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3810
1872a3f4
AK		 3811 if (ldtr.unusable)
3812 return true;
648dfaa7
MG		 3813 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3814 return false;
3815 if (ldtr.type != 2)
3816 return false;
3817 if (!ldtr.present)
3818 return false;
3819
3820 return true;
3821}
3822
3823static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3824{
3825 struct kvm_segment cs, ss;
3826
3827 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3828 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3829
3830 return ((cs.selector & SELECTOR_RPL_MASK) ==
3831 (ss.selector & SELECTOR_RPL_MASK));
3832}
3833
3834/*
3835 * Check if guest state is valid. Returns true if valid, false if
3836 * not.
3837 * We assume that registers are always usable
3838 */
3839static bool guest_state_valid(struct kvm_vcpu *vcpu)
3840{
c5e97c80
GN		 3841 if (enable_unrestricted_guest)
3842 return true;
3843
648dfaa7 3844 /* real mode guest state checks */
f13882d8 3845 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3846 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3847 return false;
3848 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3849 return false;
3850 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3851 return false;
3852 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3853 return false;
3854 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3855 return false;
3856 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3857 return false;
3858 } else {
3859 /* protected mode guest state checks */
3860 if (!cs_ss_rpl_check(vcpu))
3861 return false;
3862 if (!code_segment_valid(vcpu))
3863 return false;
3864 if (!stack_segment_valid(vcpu))
3865 return false;
3866 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3867 return false;
3868 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3869 return false;
3870 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3871 return false;
3872 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3873 return false;
3874 if (!tr_valid(vcpu))
3875 return false;
3876 if (!ldtr_valid(vcpu))
3877 return false;
3878 }
3879 /* TODO:
3880 * - Add checks on RIP
3881 * - Add checks on RFLAGS
3882 */
3883
3884 return true;
3885}
3886
d77c26fc 3887static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3888{
40dcaa9f 3889 gfn_t fn;
195aefde 3890 u16 data = 0;
40dcaa9f 3891 int r, idx, ret = 0;
6aa8b732 3892
40dcaa9f 3893 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3894 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3895 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3896 if (r < 0)
10589a46 3897 goto out;
195aefde 3898 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3899 r = kvm_write_guest_page(kvm, fn++, &data,
3900 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3901 if (r < 0)
10589a46 3902 goto out;
195aefde
IE		 3903 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3904 if (r < 0)
10589a46 3905 goto out;
195aefde
IE		 3906 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3907 if (r < 0)
10589a46 3908 goto out;
195aefde 3909 data = ~0;
10589a46
MT		 3910 r = kvm_write_guest_page(kvm, fn, &data,
3911 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3912 sizeof(u8));
195aefde 3913 if (r < 0)
10589a46
MT		 3914 goto out;
3915
3916 ret = 1;
3917out:
40dcaa9f 3918 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3919 return ret;
6aa8b732
AK		 3920}
3921
b7ebfb05
SY		 3922static int init_rmode_identity_map(struct kvm *kvm)
3923{
40dcaa9f 3924 int i, idx, r, ret;
b7ebfb05
SY		 3925 pfn_t identity_map_pfn;
3926 u32 tmp;
3927
089d034e 3928 if (!enable_ept)
b7ebfb05
SY		 3929 return 1;
3930 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3931 printk(KERN_ERR "EPT: identity-mapping pagetable "
3932 "haven't been allocated!\n");
3933 return 0;
3934 }
3935 if (likely(kvm->arch.ept_identity_pagetable_done))
3936 return 1;
3937 ret = 0;
b927a3ce 3938 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3939 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3940 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3941 if (r < 0)
3942 goto out;
3943 /* Set up identity-mapping pagetable for EPT in real mode */
3944 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3945 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3946 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3947 r = kvm_write_guest_page(kvm, identity_map_pfn,
3948 &tmp, i * sizeof(tmp), sizeof(tmp));
3949 if (r < 0)
3950 goto out;
3951 }
3952 kvm->arch.ept_identity_pagetable_done = true;
3953 ret = 1;
3954out:
40dcaa9f 3955 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3956 return ret;
3957}
3958
6aa8b732
AK		 3959static void seg_setup(int seg)
3960{
772e0318 3961 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3962 unsigned int ar;
6aa8b732
AK		 3963
3964 vmcs_write16(sf->selector, 0);
3965 vmcs_writel(sf->base, 0);
3966 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3967 ar = 0x93;
3968 if (seg == VCPU_SREG_CS)
3969 ar |= 0x08; /* code segment */
3a624e29
NK		 3970
3971 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3972}
3973
f78e0e2e
SY		 3974static int alloc_apic_access_page(struct kvm *kvm)
3975{
4484141a 3976 struct page *page;
f78e0e2e
SY		 3977 struct kvm_userspace_memory_region kvm_userspace_mem;
3978 int r = 0;
3979
79fac95e 3980 mutex_lock(&kvm->slots_lock);
bfc6d222 3981 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3982 goto out;
3983 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3984 kvm_userspace_mem.flags = 0;
3985 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3986 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3987 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3988 if (r)
3989 goto out;
72dc67a6 3990
4484141a
XG		 3991 page = gfn_to_page(kvm, 0xfee00);
3992 if (is_error_page(page)) {
3993 r = -EFAULT;
3994 goto out;
3995 }
3996
3997 kvm->arch.apic_access_page = page;
f78e0e2e 3998out:
79fac95e 3999 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4000 return r;
4001}
4002
b7ebfb05
SY		 4003static int alloc_identity_pagetable(struct kvm *kvm)
4004{
4484141a 4005 struct page *page;
b7ebfb05
SY		 4006 struct kvm_userspace_memory_region kvm_userspace_mem;
4007 int r = 0;
4008
79fac95e 4009 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4010 if (kvm->arch.ept_identity_pagetable)
4011 goto out;
4012 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4013 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4014 kvm_userspace_mem.guest_phys_addr =
4015 kvm->arch.ept_identity_map_addr;
b7ebfb05 4016 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4017 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4018 if (r)
4019 goto out;
4020
4484141a
XG		 4021 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4022 if (is_error_page(page)) {
4023 r = -EFAULT;
4024 goto out;
4025 }
4026
4027 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4028out:
79fac95e 4029 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4030 return r;
4031}
4032
2384d2b3
SY		 4033static void allocate_vpid(struct vcpu_vmx *vmx)
4034{
4035 int vpid;
4036
4037 vmx->vpid = 0;
919818ab 4038 if (!enable_vpid)
2384d2b3
SY		 4039 return;
4040 spin_lock(&vmx_vpid_lock);
4041 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4042 if (vpid < VMX_NR_VPIDS) {
4043 vmx->vpid = vpid;
4044 __set_bit(vpid, vmx_vpid_bitmap);
4045 }
4046 spin_unlock(&vmx_vpid_lock);
4047}
4048
cdbecfc3
LJ		 4049static void free_vpid(struct vcpu_vmx *vmx)
4050{
4051 if (!enable_vpid)
4052 return;
4053 spin_lock(&vmx_vpid_lock);
4054 if (vmx->vpid != 0)
4055 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4056 spin_unlock(&vmx_vpid_lock);
4057}
4058
8d14695f
YZ		 4059#define MSR_TYPE_R 1
4060#define MSR_TYPE_W 2
4061static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4062 u32 msr, int type)
25c5f225 4063{
3e7c73e9 4064 int f = sizeof(unsigned long);
25c5f225
SY		 4065
4066 if (!cpu_has_vmx_msr_bitmap())
4067 return;
4068
4069 /*
4070 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4071 * have the write-low and read-high bitmap offsets the wrong way round.
4072 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4073 */
25c5f225 4074 if (msr <= 0x1fff) {
8d14695f
YZ		 4075 if (type & MSR_TYPE_R)
4076 /* read-low */
4077 __clear_bit(msr, msr_bitmap + 0x000 / f);
4078
4079 if (type & MSR_TYPE_W)
4080 /* write-low */
4081 __clear_bit(msr, msr_bitmap + 0x800 / f);
4082
25c5f225
SY		 4083 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4084 msr &= 0x1fff;
8d14695f
YZ		 4085 if (type & MSR_TYPE_R)
4086 /* read-high */
4087 __clear_bit(msr, msr_bitmap + 0x400 / f);
4088
4089 if (type & MSR_TYPE_W)
4090 /* write-high */
4091 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4092
4093 }
4094}
4095
4096static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4097 u32 msr, int type)
4098{
4099 int f = sizeof(unsigned long);
4100
4101 if (!cpu_has_vmx_msr_bitmap())
4102 return;
4103
4104 /*
4105 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4106 * have the write-low and read-high bitmap offsets the wrong way round.
4107 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4108 */
4109 if (msr <= 0x1fff) {
4110 if (type & MSR_TYPE_R)
4111 /* read-low */
4112 __set_bit(msr, msr_bitmap + 0x000 / f);
4113
4114 if (type & MSR_TYPE_W)
4115 /* write-low */
4116 __set_bit(msr, msr_bitmap + 0x800 / f);
4117
4118 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4119 msr &= 0x1fff;
4120 if (type & MSR_TYPE_R)
4121 /* read-high */
4122 __set_bit(msr, msr_bitmap + 0x400 / f);
4123
4124 if (type & MSR_TYPE_W)
4125 /* write-high */
4126 __set_bit(msr, msr_bitmap + 0xc00 / f);
4127
25c5f225 4128 }
25c5f225
SY		 4129}
4130
5897297b
AK		 4131static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4132{
4133 if (!longmode_only)
8d14695f
YZ		 4134 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4135 msr, MSR_TYPE_R | MSR_TYPE_W);
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4137 msr, MSR_TYPE_R | MSR_TYPE_W);
4138}
4139
4140static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4141{
4142 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4143 msr, MSR_TYPE_R);
4144 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4145 msr, MSR_TYPE_R);
4146}
4147
4148static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4149{
4150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4151 msr, MSR_TYPE_R);
4152 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4153 msr, MSR_TYPE_R);
4154}
4155
4156static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4157{
4158 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4159 msr, MSR_TYPE_W);
4160 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4161 msr, MSR_TYPE_W);
5897297b
AK		 4162}
4163
01e439be
YZ		 4164static int vmx_vm_has_apicv(struct kvm *kvm)
4165{
4166 return enable_apicv && irqchip_in_kernel(kvm);
4167}
4168
a20ed54d
YZ		 4169/*
4170 * Send interrupt to vcpu via posted interrupt way.
4171 * 1. If target vcpu is running(non-root mode), send posted interrupt
4172 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4173 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4174 * interrupt from PIR in next vmentry.
4175 */
4176static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4177{
4178 struct vcpu_vmx *vmx = to_vmx(vcpu);
4179 int r;
4180
4181 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4182 return;
4183
4184 r = pi_test_and_set_on(&vmx->pi_desc);
4185 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4186#ifdef CONFIG_SMP
a20ed54d
YZ		 4187 if (!r && (vcpu->mode == IN_GUEST_MODE))
4188 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4189 POSTED_INTR_VECTOR);
4190 else
6ffbbbba 4191#endif
a20ed54d
YZ		 4192 kvm_vcpu_kick(vcpu);
4193}
4194
4195static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4196{
4197 struct vcpu_vmx *vmx = to_vmx(vcpu);
4198
4199 if (!pi_test_and_clear_on(&vmx->pi_desc))
4200 return;
4201
4202 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4203}
4204
4205static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4206{
4207 return;
4208}
4209
a3a8ff8e
NHE		 4210/*
4211 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4212 * will not change in the lifetime of the guest.
4213 * Note that host-state that does change is set elsewhere. E.g., host-state
4214 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4215 */
a547c6db 4216static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4217{
4218 u32 low32, high32;
4219 unsigned long tmpl;
4220 struct desc_ptr dt;
4221
b1a74bf8 4222 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4223 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4224 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4225
4226 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4227#ifdef CONFIG_X86_64
4228 /*
4229 * Load null selectors, so we can avoid reloading them in
4230 * __vmx_load_host_state(), in case userspace uses the null selectors
4231 * too (the expected case).
4232 */
4233 vmcs_write16(HOST_DS_SELECTOR, 0);
4234 vmcs_write16(HOST_ES_SELECTOR, 0);
4235#else
a3a8ff8e
NHE		 4236 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4237 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4238#endif
a3a8ff8e
NHE		 4239 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4240 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4241
4242 native_store_idt(&dt);
4243 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4244 vmx->host_idt_base = dt.address;
a3a8ff8e 4245
83287ea4 4246 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4247
4248 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4249 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4250 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4251 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4252
4253 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4254 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4255 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4256 }
4257}
4258
bf8179a0
NHE		 4259static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4260{
4261 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4262 if (enable_ept)
4263 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4264 if (is_guest_mode(&vmx->vcpu))
4265 vmx->vcpu.arch.cr4_guest_owned_bits &=
4266 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4267 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4268}
4269
01e439be
YZ		 4270static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4271{
4272 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4273
4274 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4275 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4276 return pin_based_exec_ctrl;
4277}
4278
bf8179a0
NHE		 4279static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4280{
4281 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4282
4283 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4284 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4285
bf8179a0
NHE		 4286 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4287 exec_control &= ~CPU_BASED_TPR_SHADOW;
4288#ifdef CONFIG_X86_64
4289 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4290 CPU_BASED_CR8_LOAD_EXITING;
4291#endif
4292 }
4293 if (!enable_ept)
4294 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4295 CPU_BASED_CR3_LOAD_EXITING |
4296 CPU_BASED_INVLPG_EXITING;
4297 return exec_control;
4298}
4299
4300static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4301{
4302 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4303 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4304 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4305 if (vmx->vpid == 0)
4306 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4307 if (!enable_ept) {
4308 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4309 enable_unrestricted_guest = 0;
ad756a16
MJ		 4310 /* Enable INVPCID for non-ept guests may cause performance regression. */
4311 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4312 }
4313 if (!enable_unrestricted_guest)
4314 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4315 if (!ple_gap)
4316 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4317 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4318 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4319 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4320 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4321 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4322 (handle_vmptrld).
4323 We can NOT enable shadow_vmcs here because we don't have yet
4324 a current VMCS12
4325 */
4326 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4327 return exec_control;
4328}
4329
ce88decf
XG		 4330static void ept_set_mmio_spte_mask(void)
4331{
4332 /*
4333 * EPT Misconfigurations can be generated if the value of bits 2:0
4334 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4335 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4336 * spte.
4337 */
885032b9 4338 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4339}
4340
6aa8b732
AK		 4341/*
4342 * Sets up the vmcs for emulated real mode.
4343 */
8b9cf98c 4344static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4345{
2e4ce7f5 4346#ifdef CONFIG_X86_64
6aa8b732 4347 unsigned long a;
2e4ce7f5 4348#endif
6aa8b732 4349 int i;
6aa8b732 4350
6aa8b732 4351 /* I/O */
3e7c73e9
AK		 4352 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4353 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4354
4607c2d7
AG		 4355 if (enable_shadow_vmcs) {
4356 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4357 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4358 }
25c5f225 4359 if (cpu_has_vmx_msr_bitmap())
5897297b 4360 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4361
6aa8b732
AK		 4362 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4363
6aa8b732 4364 /* Control */
01e439be 4365 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4366
bf8179a0 4367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4368
83ff3b9d 4369 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4370 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4371 vmx_secondary_exec_control(vmx));
83ff3b9d 4372 }
f78e0e2e 4373
01e439be 4374 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4375 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4376 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4377 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4378 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4379
4380 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4381
4382 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4383 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4384 }
4385
4b8d54f9
ZE		 4386 if (ple_gap) {
4387 vmcs_write32(PLE_GAP, ple_gap);
4388 vmcs_write32(PLE_WINDOW, ple_window);
4389 }
4390
c3707958
XG		 4391 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4392 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4393 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4394
9581d442
AK		 4395 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4396 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4397 vmx_set_constant_host_state(vmx);
05b3e0c2 4398#ifdef CONFIG_X86_64
6aa8b732
AK		 4399 rdmsrl(MSR_FS_BASE, a);
4400 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4401 rdmsrl(MSR_GS_BASE, a);
4402 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4403#else
4404 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4405 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4406#endif
4407
2cc51560
ED		 4408 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4409 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4410 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4411 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4412 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4413
468d472f 4414 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4415 u32 msr_low, msr_high;
4416 u64 host_pat;
468d472f
SY		 4417 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4418 host_pat = msr_low | ((u64) msr_high << 32);
4419 /* Write the default value follow host pat */
4420 vmcs_write64(GUEST_IA32_PAT, host_pat);
4421 /* Keep arch.pat sync with GUEST_IA32_PAT */
4422 vmx->vcpu.arch.pat = host_pat;
4423 }
4424
6aa8b732
AK		 4425 for (i = 0; i < NR_VMX_MSR; ++i) {
4426 u32 index = vmx_msr_index[i];
4427 u32 data_low, data_high;
a2fa3e9f 4428 int j = vmx->nmsrs;
6aa8b732
AK		 4429
4430 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4431 continue;
432bd6cb
AK		 4432 if (wrmsr_safe(index, data_low, data_high) < 0)
4433 continue;
26bb0981
AK		 4434 vmx->guest_msrs[j].index = i;
4435 vmx->guest_msrs[j].data = 0;
d5696725 4436 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4437 ++vmx->nmsrs;
6aa8b732 4438 }
6aa8b732 4439
2961e876
GN		 4440
4441 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4442
4443 /* 22.2.1, 20.8.1 */
2961e876 4444 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4445
e00c8cf2 4446 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4447 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4448
4449 return 0;
4450}
4451
57f252f2 4452static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4453{
4454 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4455 struct msr_data apic_base_msr;
e00c8cf2 4456
7ffd92c5 4457 vmx->rmode.vm86_active = 0;
e00c8cf2 4458
3b86cd99
JK		 4459 vmx->soft_vnmi_blocked = 0;
4460
ad312c7c 4461 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4462 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4463 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4464 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4465 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4466 apic_base_msr.host_initiated = true;
4467 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4468
2fb92db1
AK		 4469 vmx_segment_cache_clear(vmx);
4470
5706be0d 4471 seg_setup(VCPU_SREG_CS);
66450a21 4472 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4473 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4474
4475 seg_setup(VCPU_SREG_DS);
4476 seg_setup(VCPU_SREG_ES);
4477 seg_setup(VCPU_SREG_FS);
4478 seg_setup(VCPU_SREG_GS);
4479 seg_setup(VCPU_SREG_SS);
4480
4481 vmcs_write16(GUEST_TR_SELECTOR, 0);
4482 vmcs_writel(GUEST_TR_BASE, 0);
4483 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4484 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4485
4486 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4487 vmcs_writel(GUEST_LDTR_BASE, 0);
4488 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4489 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4490
4491 vmcs_write32(GUEST_SYSENTER_CS, 0);
4492 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4493 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4494
4495 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4496 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4497
e00c8cf2
AK		 4498 vmcs_writel(GUEST_GDTR_BASE, 0);
4499 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4500
4501 vmcs_writel(GUEST_IDTR_BASE, 0);
4502 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4503
443381a8 4504 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4506 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4507
e00c8cf2
AK		 4508 /* Special registers */
4509 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4510
4511 setup_msrs(vmx);
4512
6aa8b732
AK		 4513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4514
f78e0e2e
SY		 4515 if (cpu_has_vmx_tpr_shadow()) {
4516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4517 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4518 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4519 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4520 vmcs_write32(TPR_THRESHOLD, 0);
4521 }
4522
4523 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4524 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4525 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4526
01e439be
YZ		 4527 if (vmx_vm_has_apicv(vcpu->kvm))
4528 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4529
2384d2b3
SY		 4530 if (vmx->vpid != 0)
4531 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4532
fa40052c 4533 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4534 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4535 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4536 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4537 vmx_fpu_activate(&vmx->vcpu);
4538 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4539
b9d762fa 4540 vpid_sync_context(vmx);
6aa8b732
AK		 4541}
4542
b6f1250e
NHE		 4543/*
4544 * In nested virtualization, check if L1 asked to exit on external interrupts.
4545 * For most existing hypervisors, this will always return true.
4546 */
4547static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4548{
4549 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4550 PIN_BASED_EXT_INTR_MASK;
4551}
4552
77b0f5d6
BD		 4553/*
4554 * In nested virtualization, check if L1 has set
4555 * VM_EXIT_ACK_INTR_ON_EXIT
4556 */
4557static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4558{
4559 return get_vmcs12(vcpu)->vm_exit_controls &
4560 VM_EXIT_ACK_INTR_ON_EXIT;
4561}
4562
ea8ceb83
JK		 4563static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4564{
4565 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4566 PIN_BASED_NMI_EXITING;
4567}
4568
c9a7953f 4569static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4570{
4571 u32 cpu_based_vm_exec_control;
730dca42 4572
3b86cd99
JK		 4573 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4574 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4575 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4576}
4577
c9a7953f 4578static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4579{
4580 u32 cpu_based_vm_exec_control;
4581
c9a7953f
JK		 4582 if (!cpu_has_virtual_nmis() ||
4583 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4584 enable_irq_window(vcpu);
4585 return;
4586 }
3b86cd99
JK		 4587
4588 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4589 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4590 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4591}
4592
66fd3f7f 4593static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4594{
9c8cba37 4595 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4596 uint32_t intr;
4597 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4598
229456fc 4599 trace_kvm_inj_virq(irq);
2714d1d3 4600
fa89a817 4601 ++vcpu->stat.irq_injections;
7ffd92c5 4602 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4603 int inc_eip = 0;
4604 if (vcpu->arch.interrupt.soft)
4605 inc_eip = vcpu->arch.event_exit_inst_len;
4606 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4607 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4608 return;
4609 }
66fd3f7f
GN		 4610 intr = irq | INTR_INFO_VALID_MASK;
4611 if (vcpu->arch.interrupt.soft) {
4612 intr |= INTR_TYPE_SOFT_INTR;
4613 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4614 vmx->vcpu.arch.event_exit_inst_len);
4615 } else
4616 intr |= INTR_TYPE_EXT_INTR;
4617 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4618}
4619
f08864b4
SY		 4620static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4621{
66a5a347
JK		 4622 struct vcpu_vmx *vmx = to_vmx(vcpu);
4623
0b6ac343
NHE		 4624 if (is_guest_mode(vcpu))
4625 return;
4626
3b86cd99
JK		 4627 if (!cpu_has_virtual_nmis()) {
4628 /*
4629 * Tracking the NMI-blocked state in software is built upon
4630 * finding the next open IRQ window. This, in turn, depends on
4631 * well-behaving guests: They have to keep IRQs disabled at
4632 * least as long as the NMI handler runs. Otherwise we may
4633 * cause NMI nesting, maybe breaking the guest. But as this is
4634 * highly unlikely, we can live with the residual risk.
4635 */
4636 vmx->soft_vnmi_blocked = 1;
4637 vmx->vnmi_blocked_time = 0;
4638 }
4639
487b391d 4640 ++vcpu->stat.nmi_injections;
9d58b931 4641 vmx->nmi_known_unmasked = false;
7ffd92c5 4642 if (vmx->rmode.vm86_active) {
71f9833b 4643 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4644 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4645 return;
4646 }
f08864b4
SY		 4647 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4648 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4649}
4650
3cfc3092
JK		 4651static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4652{
4653 if (!cpu_has_virtual_nmis())
4654 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4655 if (to_vmx(vcpu)->nmi_known_unmasked)
4656 return false;
c332c83a 4657 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4658}
4659
4660static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4661{
4662 struct vcpu_vmx *vmx = to_vmx(vcpu);
4663
4664 if (!cpu_has_virtual_nmis()) {
4665 if (vmx->soft_vnmi_blocked != masked) {
4666 vmx->soft_vnmi_blocked = masked;
4667 vmx->vnmi_blocked_time = 0;
4668 }
4669 } else {
9d58b931 4670 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4671 if (masked)
4672 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4673 GUEST_INTR_STATE_NMI);
4674 else
4675 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4676 GUEST_INTR_STATE_NMI);
4677 }
4678}
4679
2505dc9f
JK		 4680static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4681{
b6b8a145
JK		 4682 if (to_vmx(vcpu)->nested.nested_run_pending)
4683 return 0;
ea8ceb83 4684
2505dc9f
JK		 4685 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4686 return 0;
4687
4688 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4689 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4690 | GUEST_INTR_STATE_NMI));
4691}
4692
78646121
GN		 4693static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4694{
b6b8a145
JK		 4695 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4696 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4697 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4698 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4699}
4700
cbc94022
IE		 4701static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4702{
4703 int ret;
4704 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4705 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4706 .guest_phys_addr = addr,
4707 .memory_size = PAGE_SIZE * 3,
4708 .flags = 0,
4709 };
4710
47ae31e2 4711 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4712 if (ret)
4713 return ret;
bfc6d222 4714 kvm->arch.tss_addr = addr;
93ea5388
GN		 4715 if (!init_rmode_tss(kvm))
4716 return -ENOMEM;
4717
cbc94022
IE		 4718 return 0;
4719}
4720
0ca1b4f4 4721static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4722{
77ab6db0 4723 switch (vec) {
77ab6db0 4724 case BP_VECTOR:
c573cd22
JK		 4725 /*
4726 * Update instruction length as we may reinject the exception
4727 * from user space while in guest debugging mode.
4728 */
4729 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4730 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4731 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4732 return false;
4733 /* fall through */
4734 case DB_VECTOR:
4735 if (vcpu->guest_debug &
4736 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4737 return false;
d0bfb940
JK		 4738 /* fall through */
4739 case DE_VECTOR:
77ab6db0
JK		 4740 case OF_VECTOR:
4741 case BR_VECTOR:
4742 case UD_VECTOR:
4743 case DF_VECTOR:
4744 case SS_VECTOR:
4745 case GP_VECTOR:
4746 case MF_VECTOR:
0ca1b4f4
GN		 4747 return true;
4748 break;
77ab6db0 4749 }
0ca1b4f4
GN		 4750 return false;
4751}
4752
4753static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4754 int vec, u32 err_code)
4755{
4756 /*
4757 * Instruction with address size override prefix opcode 0x67
4758 * Cause the #SS fault with 0 error code in VM86 mode.
4759 */
4760 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4761 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4762 if (vcpu->arch.halt_request) {
4763 vcpu->arch.halt_request = 0;
4764 return kvm_emulate_halt(vcpu);
4765 }
4766 return 1;
4767 }
4768 return 0;
4769 }
4770
4771 /*
4772 * Forward all other exceptions that are valid in real mode.
4773 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4774 * the required debugging infrastructure rework.
4775 */
4776 kvm_queue_exception(vcpu, vec);
4777 return 1;
6aa8b732
AK		 4778}
4779
a0861c02
AK		 4780/*
4781 * Trigger machine check on the host. We assume all the MSRs are already set up
4782 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4783 * We pass a fake environment to the machine check handler because we want
4784 * the guest to be always treated like user space, no matter what context
4785 * it used internally.
4786 */
4787static void kvm_machine_check(void)
4788{
4789#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4790 struct pt_regs regs = {
4791 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4792 .flags = X86_EFLAGS_IF,
4793 };
4794
4795 do_machine_check(&regs, 0);
4796#endif
4797}
4798
851ba692 4799static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4800{
4801 /* already handled by vcpu_run */
4802 return 1;
4803}
4804
851ba692 4805static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4806{
1155f76a 4807 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4808 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4809 u32 intr_info, ex_no, error_code;
42dbaa5a 4810 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4811 u32 vect_info;
4812 enum emulation_result er;
4813
1155f76a 4814 vect_info = vmx->idt_vectoring_info;
88786475 4815 intr_info = vmx->exit_intr_info;
6aa8b732 4816
a0861c02 4817 if (is_machine_check(intr_info))
851ba692 4818 return handle_machine_check(vcpu);
a0861c02 4819
e4a41889 4820 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4821 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4822
4823 if (is_no_device(intr_info)) {
5fd86fcf 4824 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4825 return 1;
4826 }
4827
7aa81cc0 4828 if (is_invalid_opcode(intr_info)) {
51d8b661 4829 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4830 if (er != EMULATE_DONE)
7ee5d940 4831 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4832 return 1;
4833 }
4834
6aa8b732 4835 error_code = 0;
2e11384c 4836 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4837 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4838
4839 /*
4840 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4841 * MMIO, it is better to report an internal error.
4842 * See the comments in vmx_handle_exit.
4843 */
4844 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4845 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4846 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4847 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4848 vcpu->run->internal.ndata = 2;
4849 vcpu->run->internal.data[0] = vect_info;
4850 vcpu->run->internal.data[1] = intr_info;
4851 return 0;
4852 }
4853
6aa8b732 4854 if (is_page_fault(intr_info)) {
1439442c 4855 /* EPT won't cause page fault directly */
cf3ace79 4856 BUG_ON(enable_ept);
6aa8b732 4857 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4858 trace_kvm_page_fault(cr2, error_code);
4859
3298b75c 4860 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4861 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4862 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4863 }
4864
d0bfb940 4865 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4866
4867 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4868 return handle_rmode_exception(vcpu, ex_no, error_code);
4869
42dbaa5a
JK		 4870 switch (ex_no) {
4871 case DB_VECTOR:
4872 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4873 if (!(vcpu->guest_debug &
4874 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4875 vcpu->arch.dr6 &= ~15;
4876 vcpu->arch.dr6 |= dr6;
fd2a445a
HD		 4877 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4878 skip_emulated_instruction(vcpu);
4879
42dbaa5a
JK		 4880 kvm_queue_exception(vcpu, DB_VECTOR);
4881 return 1;
4882 }
4883 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4884 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4885 /* fall through */
4886 case BP_VECTOR:
c573cd22
JK		 4887 /*
4888 * Update instruction length as we may reinject #BP from
4889 * user space while in guest debugging mode. Reading it for
4890 * #DB as well causes no harm, it is not used in that case.
4891 */
4892 vmx->vcpu.arch.event_exit_inst_len =
4893 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4894 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4895 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4896 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4897 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4898 break;
4899 default:
d0bfb940
JK		 4900 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4901 kvm_run->ex.exception = ex_no;
4902 kvm_run->ex.error_code = error_code;
42dbaa5a 4903 break;
6aa8b732 4904 }
6aa8b732
AK		 4905 return 0;
4906}
4907
851ba692 4908static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4909{
1165f5fe 4910 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4911 return 1;
4912}
4913
851ba692 4914static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4915{
851ba692 4916 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4917 return 0;
4918}
6aa8b732 4919
851ba692 4920static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4921{
bfdaab09 4922 unsigned long exit_qualification;
34c33d16 4923 int size, in, string;
039576c0 4924 unsigned port;
6aa8b732 4925
bfdaab09 4926 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4927 string = (exit_qualification & 16) != 0;
cf8f70bf 4928 in = (exit_qualification & 8) != 0;
e70669ab 4929
cf8f70bf 4930 ++vcpu->stat.io_exits;
e70669ab 4931
cf8f70bf 4932 if (string || in)
51d8b661 4933 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4934
cf8f70bf
GN		 4935 port = exit_qualification >> 16;
4936 size = (exit_qualification & 7) + 1;
e93f36bc 4937 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4938
4939 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4940}
4941
102d8325
IM		 4942static void
4943vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4944{
4945 /*
4946 * Patch in the VMCALL instruction:
4947 */
4948 hypercall[0] = 0x0f;
4949 hypercall[1] = 0x01;
4950 hypercall[2] = 0xc1;
102d8325
IM		 4951}
4952
92fbc7b1
JK		 4953static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4954{
4955 unsigned long always_on = VMXON_CR0_ALWAYSON;
4956
4957 if (nested_vmx_secondary_ctls_high &
4958 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4959 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4960 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4961 return (val & always_on) == always_on;
4962}
4963
0fa06071 4964/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4965static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4966{
eeadf9e7 4967 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4968 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4969 unsigned long orig_val = val;
4970
eeadf9e7
NHE		 4971 /*
4972 * We get here when L2 changed cr0 in a way that did not change
4973 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4974 * but did change L0 shadowed bits. So we first calculate the
4975 * effective cr0 value that L1 would like to write into the
4976 * hardware. It consists of the L2-owned bits from the new
4977 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4978 */
1a0d74e6
JK		 4979 val = (val & ~vmcs12->cr0_guest_host_mask) |
4980 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4981
92fbc7b1 4982 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4983 return 1;
1a0d74e6
JK		 4984
4985 if (kvm_set_cr0(vcpu, val))
4986 return 1;
4987 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4988 return 0;
1a0d74e6
JK		 4989 } else {
4990 if (to_vmx(vcpu)->nested.vmxon &&
4991 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4992 return 1;
eeadf9e7 4993 return kvm_set_cr0(vcpu, val);
1a0d74e6 4994 }
eeadf9e7
NHE		 4995}
4996
4997static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4998{
4999 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5000 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5001 unsigned long orig_val = val;
5002
5003 /* analogously to handle_set_cr0 */
5004 val = (val & ~vmcs12->cr4_guest_host_mask) |
5005 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5006 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5007 return 1;
1a0d74e6 5008 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5009 return 0;
5010 } else
5011 return kvm_set_cr4(vcpu, val);
5012}
5013
5014/* called to set cr0 as approriate for clts instruction exit. */
5015static void handle_clts(struct kvm_vcpu *vcpu)
5016{
5017 if (is_guest_mode(vcpu)) {
5018 /*
5019 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5020 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5021 * just pretend it's off (also in arch.cr0 for fpu_activate).
5022 */
5023 vmcs_writel(CR0_READ_SHADOW,
5024 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5025 vcpu->arch.cr0 &= ~X86_CR0_TS;
5026 } else
5027 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5028}
5029
851ba692 5030static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5031{
229456fc 5032 unsigned long exit_qualification, val;
6aa8b732
AK		 5033 int cr;
5034 int reg;
49a9b07e 5035 int err;
6aa8b732 5036
bfdaab09 5037 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5038 cr = exit_qualification & 15;
5039 reg = (exit_qualification >> 8) & 15;
5040 switch ((exit_qualification >> 4) & 3) {
5041 case 0: /* mov to cr */
229456fc
MT		 5042 val = kvm_register_read(vcpu, reg);
5043 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5044 switch (cr) {
5045 case 0:
eeadf9e7 5046 err = handle_set_cr0(vcpu, val);
db8fcefa 5047 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5048 return 1;
5049 case 3:
2390218b 5050 err = kvm_set_cr3(vcpu, val);
db8fcefa 5051 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5052 return 1;
5053 case 4:
eeadf9e7 5054 err = handle_set_cr4(vcpu, val);
db8fcefa 5055 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5056 return 1;
0a5fff19
GN		 5057 case 8: {
5058 u8 cr8_prev = kvm_get_cr8(vcpu);
5059 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5060 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5061 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5062 if (irqchip_in_kernel(vcpu->kvm))
5063 return 1;
5064 if (cr8_prev <= cr8)
5065 return 1;
851ba692 5066 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5067 return 0;
5068 }
4b8073e4 5069 }
6aa8b732 5070 break;
25c4c276 5071 case 2: /* clts */
eeadf9e7 5072 handle_clts(vcpu);
4d4ec087 5073 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5074 skip_emulated_instruction(vcpu);
6b52d186 5075 vmx_fpu_activate(vcpu);
25c4c276 5076 return 1;
6aa8b732
AK		 5077 case 1: /*mov from cr*/
5078 switch (cr) {
5079 case 3:
9f8fe504
AK		 5080 val = kvm_read_cr3(vcpu);
5081 kvm_register_write(vcpu, reg, val);
5082 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5083 skip_emulated_instruction(vcpu);
5084 return 1;
5085 case 8:
229456fc
MT		 5086 val = kvm_get_cr8(vcpu);
5087 kvm_register_write(vcpu, reg, val);
5088 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5089 skip_emulated_instruction(vcpu);
5090 return 1;
5091 }
5092 break;
5093 case 3: /* lmsw */
a1f83a74 5094 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5095 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5096 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5097
5098 skip_emulated_instruction(vcpu);
5099 return 1;
5100 default:
5101 break;
5102 }
851ba692 5103 vcpu->run->exit_reason = 0;
a737f256 5104 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5105 (int)(exit_qualification >> 4) & 3, cr);
5106 return 0;
5107}
5108
851ba692 5109static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5110{
bfdaab09 5111 unsigned long exit_qualification;
6aa8b732
AK		 5112 int dr, reg;
5113
f2483415 5114 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5115 if (!kvm_require_cpl(vcpu, 0))
5116 return 1;
42dbaa5a
JK		 5117 dr = vmcs_readl(GUEST_DR7);
5118 if (dr & DR7_GD) {
5119 /*
5120 * As the vm-exit takes precedence over the debug trap, we
5121 * need to emulate the latter, either for the host or the
5122 * guest debugging itself.
5123 */
5124 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5125 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5126 vcpu->run->debug.arch.dr7 = dr;
5127 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5128 vmcs_readl(GUEST_CS_BASE) +
5129 vmcs_readl(GUEST_RIP);
851ba692
AK		 5130 vcpu->run->debug.arch.exception = DB_VECTOR;
5131 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5132 return 0;
5133 } else {
5134 vcpu->arch.dr7 &= ~DR7_GD;
5135 vcpu->arch.dr6 |= DR6_BD;
5136 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5137 kvm_queue_exception(vcpu, DB_VECTOR);
5138 return 1;
5139 }
5140 }
5141
81908bf4
PB		 5142 if (vcpu->guest_debug == 0) {
5143 u32 cpu_based_vm_exec_control;
5144
5145 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5146 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5147 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5148
5149 /*
5150 * No more DR vmexits; force a reload of the debug registers
5151 * and reenter on this instruction. The next vmexit will
5152 * retrieve the full state of the debug registers.
5153 */
5154 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5155 return 1;
5156 }
5157
bfdaab09 5158 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5159 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5160 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5161 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5162 unsigned long val;
4c4d563b
JK		 5163
5164 if (kvm_get_dr(vcpu, dr, &val))
5165 return 1;
5166 kvm_register_write(vcpu, reg, val);
020df079 5167 } else
a4ab9d0c 5168 if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)))
4c4d563b
JK		 5169 return 1;
5170
6aa8b732
AK		 5171 skip_emulated_instruction(vcpu);
5172 return 1;
5173}
5174
73aaf249
JK		 5175static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5176{
5177 return vcpu->arch.dr6;
5178}
5179
5180static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5181{
5182}
5183
81908bf4
PB		 5184static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5185{
5186 u32 cpu_based_vm_exec_control;
5187
5188 get_debugreg(vcpu->arch.db[0], 0);
5189 get_debugreg(vcpu->arch.db[1], 1);
5190 get_debugreg(vcpu->arch.db[2], 2);
5191 get_debugreg(vcpu->arch.db[3], 3);
5192 get_debugreg(vcpu->arch.dr6, 6);
5193 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5194
5195 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5196
5197 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5198 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5199 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5200}
5201
020df079
GN		 5202static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5203{
5204 vmcs_writel(GUEST_DR7, val);
5205}
5206
851ba692 5207static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5208{
06465c5a
AK		 5209 kvm_emulate_cpuid(vcpu);
5210 return 1;
6aa8b732
AK		 5211}
5212
851ba692 5213static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5214{
ad312c7c 5215 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5216 u64 data;
5217
5218 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5219 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5220 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5221 return 1;
5222 }
5223
229456fc 5224 trace_kvm_msr_read(ecx, data);
2714d1d3 5225
6aa8b732 5226 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5227 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5228 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5229 skip_emulated_instruction(vcpu);
5230 return 1;
5231}
5232
851ba692 5233static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5234{
8fe8ab46 5235 struct msr_data msr;
ad312c7c
ZX		 5236 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5237 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5238 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5239
8fe8ab46
WA		 5240 msr.data = data;
5241 msr.index = ecx;
5242 msr.host_initiated = false;
5243 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5244 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5245 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5246 return 1;
5247 }
5248
59200273 5249 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5250 skip_emulated_instruction(vcpu);
5251 return 1;
5252}
5253
851ba692 5254static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5255{
3842d135 5256 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5257 return 1;
5258}
5259
851ba692 5260static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5261{
85f455f7
ED		 5262 u32 cpu_based_vm_exec_control;
5263
5264 /* clear pending irq */
5265 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5266 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5268
3842d135
AK		 5269 kvm_make_request(KVM_REQ_EVENT, vcpu);
5270
a26bf12a 5271 ++vcpu->stat.irq_window_exits;
2714d1d3 5272
c1150d8c
DL		 5273 /*
5274 * If the user space waits to inject interrupts, exit as soon as
5275 * possible
5276 */
8061823a 5277 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5278 vcpu->run->request_interrupt_window &&
8061823a 5279 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5280 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5281 return 0;
5282 }
6aa8b732
AK		 5283 return 1;
5284}
5285
851ba692 5286static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5287{
5288 skip_emulated_instruction(vcpu);
d3bef15f 5289 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5290}
5291
851ba692 5292static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5293{
510043da 5294 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5295 kvm_emulate_hypercall(vcpu);
5296 return 1;
c21415e8
IM		 5297}
5298
ec25d5e6
GN		 5299static int handle_invd(struct kvm_vcpu *vcpu)
5300{
51d8b661 5301 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5302}
5303
851ba692 5304static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5305{
f9c617f6 5306 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5307
5308 kvm_mmu_invlpg(vcpu, exit_qualification);
5309 skip_emulated_instruction(vcpu);
5310 return 1;
5311}
5312
fee84b07
AK		 5313static int handle_rdpmc(struct kvm_vcpu *vcpu)
5314{
5315 int err;
5316
5317 err = kvm_rdpmc(vcpu);
5318 kvm_complete_insn_gp(vcpu, err);
5319
5320 return 1;
5321}
5322
851ba692 5323static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5324{
5325 skip_emulated_instruction(vcpu);
f5f48ee1 5326 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5327 return 1;
5328}
5329
2acf923e
DC		 5330static int handle_xsetbv(struct kvm_vcpu *vcpu)
5331{
5332 u64 new_bv = kvm_read_edx_eax(vcpu);
5333 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5334
5335 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5336 skip_emulated_instruction(vcpu);
5337 return 1;
5338}
5339
851ba692 5340static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5341{
58fbbf26
KT		 5342 if (likely(fasteoi)) {
5343 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5344 int access_type, offset;
5345
5346 access_type = exit_qualification & APIC_ACCESS_TYPE;
5347 offset = exit_qualification & APIC_ACCESS_OFFSET;
5348 /*
5349 * Sane guest uses MOV to write EOI, with written value
5350 * not cared. So make a short-circuit here by avoiding
5351 * heavy instruction emulation.
5352 */
5353 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5354 (offset == APIC_EOI)) {
5355 kvm_lapic_set_eoi(vcpu);
5356 skip_emulated_instruction(vcpu);
5357 return 1;
5358 }
5359 }
51d8b661 5360 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5361}
5362
c7c9c56c
YZ		 5363static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5364{
5365 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5366 int vector = exit_qualification & 0xff;
5367
5368 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5369 kvm_apic_set_eoi_accelerated(vcpu, vector);
5370 return 1;
5371}
5372
83d4c286
YZ		 5373static int handle_apic_write(struct kvm_vcpu *vcpu)
5374{
5375 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5376 u32 offset = exit_qualification & 0xfff;
5377
5378 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5379 kvm_apic_write_nodecode(vcpu, offset);
5380 return 1;
5381}
5382
851ba692 5383static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5384{
60637aac 5385 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5386 unsigned long exit_qualification;
e269fb21
JK		 5387 bool has_error_code = false;
5388 u32 error_code = 0;
37817f29 5389 u16 tss_selector;
7f3d35fd 5390 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5391
5392 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5393 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5394 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5395
5396 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5397
5398 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5399 if (reason == TASK_SWITCH_GATE && idt_v) {
5400 switch (type) {
5401 case INTR_TYPE_NMI_INTR:
5402 vcpu->arch.nmi_injected = false;
654f06fc 5403 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5404 break;
5405 case INTR_TYPE_EXT_INTR:
66fd3f7f 5406 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5407 kvm_clear_interrupt_queue(vcpu);
5408 break;
5409 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5410 if (vmx->idt_vectoring_info &
5411 VECTORING_INFO_DELIVER_CODE_MASK) {
5412 has_error_code = true;
5413 error_code =
5414 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5415 }
5416 /* fall through */
64a7ec06
GN		 5417 case INTR_TYPE_SOFT_EXCEPTION:
5418 kvm_clear_exception_queue(vcpu);
5419 break;
5420 default:
5421 break;
5422 }
60637aac 5423 }
37817f29
IE		 5424 tss_selector = exit_qualification;
5425
64a7ec06
GN		 5426 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5427 type != INTR_TYPE_EXT_INTR &&
5428 type != INTR_TYPE_NMI_INTR))
5429 skip_emulated_instruction(vcpu);
5430
7f3d35fd
KW		 5431 if (kvm_task_switch(vcpu, tss_selector,
5432 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5433 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5434 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5435 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5436 vcpu->run->internal.ndata = 0;
42dbaa5a 5437 return 0;
acb54517 5438 }
42dbaa5a
JK		 5439
5440 /* clear all local breakpoint enable flags */
1f854112 5441 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5442
5443 /*
5444 * TODO: What about debug traps on tss switch?
5445 * Are we supposed to inject them and update dr6?
5446 */
5447
5448 return 1;
37817f29
IE		 5449}
5450
851ba692 5451static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5452{
f9c617f6 5453 unsigned long exit_qualification;
1439442c 5454 gpa_t gpa;
4f5982a5 5455 u32 error_code;
1439442c 5456 int gla_validity;
1439442c 5457
f9c617f6 5458 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5459
1439442c
SY		 5460 gla_validity = (exit_qualification >> 7) & 0x3;
5461 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5462 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5463 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5464 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5465 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5466 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5467 (long unsigned int)exit_qualification);
851ba692
AK		 5468 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5469 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5470 return 0;
1439442c
SY		 5471 }
5472
0be9c7a8
GN		 5473 /*
5474 * EPT violation happened while executing iret from NMI,
5475 * "blocked by NMI" bit has to be set before next VM entry.
5476 * There are errata that may cause this bit to not be set:
5477 * AAK134, BY25.
5478 */
bcd1c294
GN		 5479 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5480 cpu_has_virtual_nmis() &&
5481 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5482 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5483
1439442c 5484 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5485 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5486
5487 /* It is a write fault? */
5488 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5489 /* It is a fetch fault? */
5490 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5491 /* ept page table is present? */
5492 error_code |= (exit_qualification >> 3) & 0x1;
5493
25d92081
YZ		 5494 vcpu->arch.exit_qualification = exit_qualification;
5495
4f5982a5 5496 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5497}
5498
68f89400
MT		 5499static u64 ept_rsvd_mask(u64 spte, int level)
5500{
5501 int i;
5502 u64 mask = 0;
5503
5504 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5505 mask |= (1ULL << i);
5506
5507 if (level > 2)
5508 /* bits 7:3 reserved */
5509 mask |= 0xf8;
5510 else if (level == 2) {
5511 if (spte & (1ULL << 7))
5512 /* 2MB ref, bits 20:12 reserved */
5513 mask |= 0x1ff000;
5514 else
5515 /* bits 6:3 reserved */
5516 mask |= 0x78;
5517 }
5518
5519 return mask;
5520}
5521
5522static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5523 int level)
5524{
5525 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5526
5527 /* 010b (write-only) */
5528 WARN_ON((spte & 0x7) == 0x2);
5529
5530 /* 110b (write/execute) */
5531 WARN_ON((spte & 0x7) == 0x6);
5532
5533 /* 100b (execute-only) and value not supported by logical processor */
5534 if (!cpu_has_vmx_ept_execute_only())
5535 WARN_ON((spte & 0x7) == 0x4);
5536
5537 /* not 000b */
5538 if ((spte & 0x7)) {
5539 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5540
5541 if (rsvd_bits != 0) {
5542 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5543 __func__, rsvd_bits);
5544 WARN_ON(1);
5545 }
5546
5547 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5548 u64 ept_mem_type = (spte & 0x38) >> 3;
5549
5550 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5551 ept_mem_type == 7) {
5552 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5553 __func__, ept_mem_type);
5554 WARN_ON(1);
5555 }
5556 }
5557 }
5558}
5559
851ba692 5560static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5561{
5562 u64 sptes[4];
ce88decf 5563 int nr_sptes, i, ret;
68f89400
MT		 5564 gpa_t gpa;
5565
5566 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5567 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5568 skip_emulated_instruction(vcpu);
5569 return 1;
5570 }
68f89400 5571
ce88decf 5572 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5573 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5574 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5575 EMULATE_DONE;
f8f55942
XG		 5576
5577 if (unlikely(ret == RET_MMIO_PF_INVALID))
5578 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5579
b37fbea6 5580 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5581 return 1;
5582
5583 /* It is the real ept misconfig */
68f89400
MT		 5584 printk(KERN_ERR "EPT: Misconfiguration.\n");
5585 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5586
5587 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5588
5589 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5590 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5591
851ba692
AK		 5592 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5593 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5594
5595 return 0;
5596}
5597
851ba692 5598static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5599{
5600 u32 cpu_based_vm_exec_control;
5601
5602 /* clear pending NMI */
5603 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5604 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5605 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5606 ++vcpu->stat.nmi_window_exits;
3842d135 5607 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5608
5609 return 1;
5610}
5611
80ced186 5612static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5613{
8b3079a5
AK		 5614 struct vcpu_vmx *vmx = to_vmx(vcpu);
5615 enum emulation_result err = EMULATE_DONE;
80ced186 5616 int ret = 1;
49e9d557
AK		 5617 u32 cpu_exec_ctrl;
5618 bool intr_window_requested;
b8405c18 5619 unsigned count = 130;
49e9d557
AK		 5620
5621 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5622 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5623
b8405c18 5624 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5625 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5626 return handle_interrupt_window(&vmx->vcpu);
5627
de87dcdd
AK		 5628 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5629 return 1;
5630
991eebf9 5631 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5632
ac0a48c3 5633 if (err == EMULATE_USER_EXIT) {
94452b9e 5634 ++vcpu->stat.mmio_exits;
80ced186
MG		 5635 ret = 0;
5636 goto out;
5637 }
1d5a4d9b 5638
de5f70e0
AK		 5639 if (err != EMULATE_DONE) {
5640 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5641 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5642 vcpu->run->internal.ndata = 0;
6d77dbfc 5643 return 0;
de5f70e0 5644 }
ea953ef0 5645
8d76c49e
GN		 5646 if (vcpu->arch.halt_request) {
5647 vcpu->arch.halt_request = 0;
5648 ret = kvm_emulate_halt(vcpu);
5649 goto out;
5650 }
5651
ea953ef0 5652 if (signal_pending(current))
80ced186 5653 goto out;
ea953ef0
MG		 5654 if (need_resched())
5655 schedule();
5656 }
5657
14168786 5658 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5659out:
5660 return ret;
ea953ef0
MG		 5661}
5662
4b8d54f9
ZE		 5663/*
5664 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5665 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5666 */
9fb41ba8 5667static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5668{
5669 skip_emulated_instruction(vcpu);
5670 kvm_vcpu_on_spin(vcpu);
5671
5672 return 1;
5673}
5674
87c00572 5675static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5676{
87c00572 5677 skip_emulated_instruction(vcpu);
59708670
SY		 5678 return 1;
5679}
5680
87c00572
GS		 5681static int handle_mwait(struct kvm_vcpu *vcpu)
5682{
5683 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5684 return handle_nop(vcpu);
5685}
5686
5687static int handle_monitor(struct kvm_vcpu *vcpu)
5688{
5689 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5690 return handle_nop(vcpu);
5691}
5692
ff2f6fe9
NHE		 5693/*
5694 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5695 * We could reuse a single VMCS for all the L2 guests, but we also want the
5696 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5697 * allows keeping them loaded on the processor, and in the future will allow
5698 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5699 * every entry if they never change.
5700 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5701 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5702 *
5703 * The following functions allocate and free a vmcs02 in this pool.
5704 */
5705
5706/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5707static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5708{
5709 struct vmcs02_list *item;
5710 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5711 if (item->vmptr == vmx->nested.current_vmptr) {
5712 list_move(&item->list, &vmx->nested.vmcs02_pool);
5713 return &item->vmcs02;
5714 }
5715
5716 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5717 /* Recycle the least recently used VMCS. */
5718 item = list_entry(vmx->nested.vmcs02_pool.prev,
5719 struct vmcs02_list, list);
5720 item->vmptr = vmx->nested.current_vmptr;
5721 list_move(&item->list, &vmx->nested.vmcs02_pool);
5722 return &item->vmcs02;
5723 }
5724
5725 /* Create a new VMCS */
0fa24ce3 5726 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5727 if (!item)
5728 return NULL;
5729 item->vmcs02.vmcs = alloc_vmcs();
5730 if (!item->vmcs02.vmcs) {
5731 kfree(item);
5732 return NULL;
5733 }
5734 loaded_vmcs_init(&item->vmcs02);
5735 item->vmptr = vmx->nested.current_vmptr;
5736 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5737 vmx->nested.vmcs02_num++;
5738 return &item->vmcs02;
5739}
5740
5741/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5742static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5743{
5744 struct vmcs02_list *item;
5745 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5746 if (item->vmptr == vmptr) {
5747 free_loaded_vmcs(&item->vmcs02);
5748 list_del(&item->list);
5749 kfree(item);
5750 vmx->nested.vmcs02_num--;
5751 return;
5752 }
5753}
5754
5755/*
5756 * Free all VMCSs saved for this vcpu, except the one pointed by
5757 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5758 * currently used, if running L2), and vmcs01 when running L2.
5759 */
5760static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5761{
5762 struct vmcs02_list *item, *n;
5763 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5764 if (vmx->loaded_vmcs != &item->vmcs02)
5765 free_loaded_vmcs(&item->vmcs02);
5766 list_del(&item->list);
5767 kfree(item);
5768 }
5769 vmx->nested.vmcs02_num = 0;
5770
5771 if (vmx->loaded_vmcs != &vmx->vmcs01)
5772 free_loaded_vmcs(&vmx->vmcs01);
5773}
5774
0658fbaa
ACL		 5775/*
5776 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5777 * set the success or error code of an emulated VMX instruction, as specified
5778 * by Vol 2B, VMX Instruction Reference, "Conventions".
5779 */
5780static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5781{
5782 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5783 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5784 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5785}
5786
5787static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5788{
5789 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5790 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5791 X86_EFLAGS_SF | X86_EFLAGS_OF))
5792 | X86_EFLAGS_CF);
5793}
5794
145c28dd 5795static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5796 u32 vm_instruction_error)
5797{
5798 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5799 /*
5800 * failValid writes the error number to the current VMCS, which
5801 * can't be done there isn't a current VMCS.
5802 */
5803 nested_vmx_failInvalid(vcpu);
5804 return;
5805 }
5806 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5807 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5808 X86_EFLAGS_SF | X86_EFLAGS_OF))
5809 | X86_EFLAGS_ZF);
5810 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5811 /*
5812 * We don't need to force a shadow sync because
5813 * VM_INSTRUCTION_ERROR is not shadowed
5814 */
5815}
145c28dd 5816
f4124500
JK		 5817static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5818{
5819 struct vcpu_vmx *vmx =
5820 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5821
5822 vmx->nested.preemption_timer_expired = true;
5823 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5824 kvm_vcpu_kick(&vmx->vcpu);
5825
5826 return HRTIMER_NORESTART;
5827}
5828
19677e32
BD		 5829/*
5830 * Decode the memory-address operand of a vmx instruction, as recorded on an
5831 * exit caused by such an instruction (run by a guest hypervisor).
5832 * On success, returns 0. When the operand is invalid, returns 1 and throws
5833 * #UD or #GP.
5834 */
5835static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5836 unsigned long exit_qualification,
5837 u32 vmx_instruction_info, gva_t *ret)
5838{
5839 /*
5840 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5841 * Execution", on an exit, vmx_instruction_info holds most of the
5842 * addressing components of the operand. Only the displacement part
5843 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5844 * For how an actual address is calculated from all these components,
5845 * refer to Vol. 1, "Operand Addressing".
5846 */
5847 int scaling = vmx_instruction_info & 3;
5848 int addr_size = (vmx_instruction_info >> 7) & 7;
5849 bool is_reg = vmx_instruction_info & (1u << 10);
5850 int seg_reg = (vmx_instruction_info >> 15) & 7;
5851 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5852 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5853 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5854 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5855
5856 if (is_reg) {
5857 kvm_queue_exception(vcpu, UD_VECTOR);
5858 return 1;
5859 }
5860
5861 /* Addr = segment_base + offset */
5862 /* offset = base + [index * scale] + displacement */
5863 *ret = vmx_get_segment_base(vcpu, seg_reg);
5864 if (base_is_valid)
5865 *ret += kvm_register_read(vcpu, base_reg);
5866 if (index_is_valid)
5867 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5868 *ret += exit_qualification; /* holds the displacement */
5869
5870 if (addr_size == 1) /* 32 bit */
5871 *ret &= 0xffffffff;
5872
5873 /*
5874 * TODO: throw #GP (and return 1) in various cases that the VM*
5875 * instructions require it - e.g., offset beyond segment limit,
5876 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5877 * address, and so on. Currently these are not checked.
5878 */
5879 return 0;
5880}
5881
3573e22c
BD		 5882/*
5883 * This function performs the various checks including
5884 * - if it's 4KB aligned
5885 * - No bits beyond the physical address width are set
5886 * - Returns 0 on success or else 1
4291b588 5887 * (Intel SDM Section 30.3)
3573e22c 5888 */
4291b588
BD		 5889static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5890 gpa_t *vmpointer)
3573e22c
BD		 5891{
5892 gva_t gva;
5893 gpa_t vmptr;
5894 struct x86_exception e;
5895 struct page *page;
5896 struct vcpu_vmx *vmx = to_vmx(vcpu);
5897 int maxphyaddr = cpuid_maxphyaddr(vcpu);
5898
5899 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5900 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5901 return 1;
5902
5903 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5904 sizeof(vmptr), &e)) {
5905 kvm_inject_page_fault(vcpu, &e);
5906 return 1;
5907 }
5908
5909 switch (exit_reason) {
5910 case EXIT_REASON_VMON:
5911 /*
5912 * SDM 3: 24.11.5
5913 * The first 4 bytes of VMXON region contain the supported
5914 * VMCS revision identifier
5915 *
5916 * Note - IA32_VMX_BASIC[48] will never be 1
5917 * for the nested case;
5918 * which replaces physical address width with 32
5919 *
5920 */
bc39c4db 5921 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 5922 nested_vmx_failInvalid(vcpu);
5923 skip_emulated_instruction(vcpu);
5924 return 1;
5925 }
5926
5927 page = nested_get_page(vcpu, vmptr);
5928 if (page == NULL ||
5929 *(u32 *)kmap(page) != VMCS12_REVISION) {
5930 nested_vmx_failInvalid(vcpu);
5931 kunmap(page);
5932 skip_emulated_instruction(vcpu);
5933 return 1;
5934 }
5935 kunmap(page);
5936 vmx->nested.vmxon_ptr = vmptr;
5937 break;
4291b588 5938 case EXIT_REASON_VMCLEAR:
bc39c4db 5939 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5940 nested_vmx_failValid(vcpu,
5941 VMXERR_VMCLEAR_INVALID_ADDRESS);
5942 skip_emulated_instruction(vcpu);
5943 return 1;
5944 }
5945
5946 if (vmptr == vmx->nested.vmxon_ptr) {
5947 nested_vmx_failValid(vcpu,
5948 VMXERR_VMCLEAR_VMXON_POINTER);
5949 skip_emulated_instruction(vcpu);
5950 return 1;
5951 }
5952 break;
5953 case EXIT_REASON_VMPTRLD:
bc39c4db 5954 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5955 nested_vmx_failValid(vcpu,
5956 VMXERR_VMPTRLD_INVALID_ADDRESS);
5957 skip_emulated_instruction(vcpu);
5958 return 1;
5959 }
3573e22c 5960
4291b588
BD		 5961 if (vmptr == vmx->nested.vmxon_ptr) {
5962 nested_vmx_failValid(vcpu,
5963 VMXERR_VMCLEAR_VMXON_POINTER);
5964 skip_emulated_instruction(vcpu);
5965 return 1;
5966 }
5967 break;
3573e22c
BD		 5968 default:
5969 return 1; /* shouldn't happen */
5970 }
5971
4291b588
BD		 5972 if (vmpointer)
5973 *vmpointer = vmptr;
3573e22c
BD		 5974 return 0;
5975}
5976
ec378aee
NHE		 5977/*
5978 * Emulate the VMXON instruction.
5979 * Currently, we just remember that VMX is active, and do not save or even
5980 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5981 * do not currently need to store anything in that guest-allocated memory
5982 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5983 * argument is different from the VMXON pointer (which the spec says they do).
5984 */
5985static int handle_vmon(struct kvm_vcpu *vcpu)
5986{
5987 struct kvm_segment cs;
5988 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5989 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5990 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5991 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5992
5993 /* The Intel VMX Instruction Reference lists a bunch of bits that
5994 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5995 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5996 * Otherwise, we should fail with #UD. We test these now:
5997 */
5998 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5999 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6000 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6001 kvm_queue_exception(vcpu, UD_VECTOR);
6002 return 1;
6003 }
6004
6005 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6006 if (is_long_mode(vcpu) && !cs.l) {
6007 kvm_queue_exception(vcpu, UD_VECTOR);
6008 return 1;
6009 }
6010
6011 if (vmx_get_cpl(vcpu)) {
6012 kvm_inject_gp(vcpu, 0);
6013 return 1;
6014 }
3573e22c 6015
4291b588 6016 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6017 return 1;
6018
145c28dd
AG		 6019 if (vmx->nested.vmxon) {
6020 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6021 skip_emulated_instruction(vcpu);
6022 return 1;
6023 }
b3897a49
NHE		 6024
6025 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6026 != VMXON_NEEDED_FEATURES) {
6027 kvm_inject_gp(vcpu, 0);
6028 return 1;
6029 }
6030
8de48833
AG		 6031 if (enable_shadow_vmcs) {
6032 shadow_vmcs = alloc_vmcs();
6033 if (!shadow_vmcs)
6034 return -ENOMEM;
6035 /* mark vmcs as shadow */
6036 shadow_vmcs->revision_id |= (1u << 31);
6037 /* init shadow vmcs */
6038 vmcs_clear(shadow_vmcs);
6039 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6040 }
ec378aee 6041
ff2f6fe9
NHE		 6042 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6043 vmx->nested.vmcs02_num = 0;
6044
f4124500
JK		 6045 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6046 HRTIMER_MODE_REL);
6047 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6048
ec378aee
NHE		 6049 vmx->nested.vmxon = true;
6050
6051 skip_emulated_instruction(vcpu);
a25eb114 6052 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6053 return 1;
6054}
6055
6056/*
6057 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6058 * for running VMX instructions (except VMXON, whose prerequisites are
6059 * slightly different). It also specifies what exception to inject otherwise.
6060 */
6061static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6062{
6063 struct kvm_segment cs;
6064 struct vcpu_vmx *vmx = to_vmx(vcpu);
6065
6066 if (!vmx->nested.vmxon) {
6067 kvm_queue_exception(vcpu, UD_VECTOR);
6068 return 0;
6069 }
6070
6071 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6072 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6073 (is_long_mode(vcpu) && !cs.l)) {
6074 kvm_queue_exception(vcpu, UD_VECTOR);
6075 return 0;
6076 }
6077
6078 if (vmx_get_cpl(vcpu)) {
6079 kvm_inject_gp(vcpu, 0);
6080 return 0;
6081 }
6082
6083 return 1;
6084}
6085
e7953d7f
AG		 6086static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6087{
8a1b9dd0 6088 u32 exec_control;
012f83cb
AG		 6089 if (enable_shadow_vmcs) {
6090 if (vmx->nested.current_vmcs12 != NULL) {
6091 /* copy to memory all shadowed fields in case
6092 they were modified */
6093 copy_shadow_to_vmcs12(vmx);
6094 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 6095 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6096 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6097 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6098 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 6099 }
6100 }
e7953d7f
AG		 6101 kunmap(vmx->nested.current_vmcs12_page);
6102 nested_release_page(vmx->nested.current_vmcs12_page);
6103}
6104
ec378aee
NHE		 6105/*
6106 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6107 * just stops using VMX.
6108 */
6109static void free_nested(struct vcpu_vmx *vmx)
6110{
6111 if (!vmx->nested.vmxon)
6112 return;
6113 vmx->nested.vmxon = false;
a9d30f33 6114 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 6115 nested_release_vmcs12(vmx);
a9d30f33
NHE		 6116 vmx->nested.current_vmptr = -1ull;
6117 vmx->nested.current_vmcs12 = NULL;
6118 }
e7953d7f
AG		 6119 if (enable_shadow_vmcs)
6120 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6121 /* Unpin physical memory we referred to in current vmcs02 */
6122 if (vmx->nested.apic_access_page) {
6123 nested_release_page(vmx->nested.apic_access_page);
6124 vmx->nested.apic_access_page = 0;
6125 }
ff2f6fe9
NHE		 6126
6127 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6128}
6129
6130/* Emulate the VMXOFF instruction */
6131static int handle_vmoff(struct kvm_vcpu *vcpu)
6132{
6133 if (!nested_vmx_check_permission(vcpu))
6134 return 1;
6135 free_nested(to_vmx(vcpu));
6136 skip_emulated_instruction(vcpu);
a25eb114 6137 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6138 return 1;
6139}
6140
27d6c865
NHE		 6141/* Emulate the VMCLEAR instruction */
6142static int handle_vmclear(struct kvm_vcpu *vcpu)
6143{
6144 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6145 gpa_t vmptr;
6146 struct vmcs12 *vmcs12;
6147 struct page *page;
27d6c865
NHE		 6148
6149 if (!nested_vmx_check_permission(vcpu))
6150 return 1;
6151
4291b588 6152 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6153 return 1;
27d6c865
NHE		 6154
6155 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6156 nested_release_vmcs12(vmx);
27d6c865
NHE		 6157 vmx->nested.current_vmptr = -1ull;
6158 vmx->nested.current_vmcs12 = NULL;
6159 }
6160
6161 page = nested_get_page(vcpu, vmptr);
6162 if (page == NULL) {
6163 /*
6164 * For accurate processor emulation, VMCLEAR beyond available
6165 * physical memory should do nothing at all. However, it is
6166 * possible that a nested vmx bug, not a guest hypervisor bug,
6167 * resulted in this case, so let's shut down before doing any
6168 * more damage:
6169 */
6170 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6171 return 1;
6172 }
6173 vmcs12 = kmap(page);
6174 vmcs12->launch_state = 0;
6175 kunmap(page);
6176 nested_release_page(page);
6177
6178 nested_free_vmcs02(vmx, vmptr);
6179
6180 skip_emulated_instruction(vcpu);
6181 nested_vmx_succeed(vcpu);
6182 return 1;
6183}
6184
cd232ad0
NHE		 6185static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6186
6187/* Emulate the VMLAUNCH instruction */
6188static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6189{
6190 return nested_vmx_run(vcpu, true);
6191}
6192
6193/* Emulate the VMRESUME instruction */
6194static int handle_vmresume(struct kvm_vcpu *vcpu)
6195{
6196
6197 return nested_vmx_run(vcpu, false);
6198}
6199
49f705c5
NHE		 6200enum vmcs_field_type {
6201 VMCS_FIELD_TYPE_U16 = 0,
6202 VMCS_FIELD_TYPE_U64 = 1,
6203 VMCS_FIELD_TYPE_U32 = 2,
6204 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6205};
6206
6207static inline int vmcs_field_type(unsigned long field)
6208{
6209 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6210 return VMCS_FIELD_TYPE_U32;
6211 return (field >> 13) & 0x3 ;
6212}
6213
6214static inline int vmcs_field_readonly(unsigned long field)
6215{
6216 return (((field >> 10) & 0x3) == 1);
6217}
6218
6219/*
6220 * Read a vmcs12 field. Since these can have varying lengths and we return
6221 * one type, we chose the biggest type (u64) and zero-extend the return value
6222 * to that size. Note that the caller, handle_vmread, might need to use only
6223 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6224 * 64-bit fields are to be returned).
6225 */
6226static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6227 unsigned long field, u64 *ret)
6228{
6229 short offset = vmcs_field_to_offset(field);
6230 char *p;
6231
6232 if (offset < 0)
6233 return 0;
6234
6235 p = ((char *)(get_vmcs12(vcpu))) + offset;
6236
6237 switch (vmcs_field_type(field)) {
6238 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6239 *ret = *((natural_width *)p);
6240 return 1;
6241 case VMCS_FIELD_TYPE_U16:
6242 *ret = *((u16 *)p);
6243 return 1;
6244 case VMCS_FIELD_TYPE_U32:
6245 *ret = *((u32 *)p);
6246 return 1;
6247 case VMCS_FIELD_TYPE_U64:
6248 *ret = *((u64 *)p);
6249 return 1;
6250 default:
6251 return 0; /* can never happen. */
6252 }
6253}
6254
20b97fea
AG		 6255
6256static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6257 unsigned long field, u64 field_value){
6258 short offset = vmcs_field_to_offset(field);
6259 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6260 if (offset < 0)
6261 return false;
6262
6263 switch (vmcs_field_type(field)) {
6264 case VMCS_FIELD_TYPE_U16:
6265 *(u16 *)p = field_value;
6266 return true;
6267 case VMCS_FIELD_TYPE_U32:
6268 *(u32 *)p = field_value;
6269 return true;
6270 case VMCS_FIELD_TYPE_U64:
6271 *(u64 *)p = field_value;
6272 return true;
6273 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6274 *(natural_width *)p = field_value;
6275 return true;
6276 default:
6277 return false; /* can never happen. */
6278 }
6279
6280}
6281
16f5b903
AG		 6282static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6283{
6284 int i;
6285 unsigned long field;
6286 u64 field_value;
6287 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6288 const unsigned long *fields = shadow_read_write_fields;
6289 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6290
6291 vmcs_load(shadow_vmcs);
6292
6293 for (i = 0; i < num_fields; i++) {
6294 field = fields[i];
6295 switch (vmcs_field_type(field)) {
6296 case VMCS_FIELD_TYPE_U16:
6297 field_value = vmcs_read16(field);
6298 break;
6299 case VMCS_FIELD_TYPE_U32:
6300 field_value = vmcs_read32(field);
6301 break;
6302 case VMCS_FIELD_TYPE_U64:
6303 field_value = vmcs_read64(field);
6304 break;
6305 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6306 field_value = vmcs_readl(field);
6307 break;
6308 }
6309 vmcs12_write_any(&vmx->vcpu, field, field_value);
6310 }
6311
6312 vmcs_clear(shadow_vmcs);
6313 vmcs_load(vmx->loaded_vmcs->vmcs);
6314}
6315
c3114420
AG		 6316static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6317{
c2bae893
MK		 6318 const unsigned long *fields[] = {
6319 shadow_read_write_fields,
6320 shadow_read_only_fields
c3114420 6321 };
c2bae893 6322 const int max_fields[] = {
c3114420
AG		 6323 max_shadow_read_write_fields,
6324 max_shadow_read_only_fields
6325 };
6326 int i, q;
6327 unsigned long field;
6328 u64 field_value = 0;
6329 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6330
6331 vmcs_load(shadow_vmcs);
6332
c2bae893 6333 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6334 for (i = 0; i < max_fields[q]; i++) {
6335 field = fields[q][i];
6336 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6337
6338 switch (vmcs_field_type(field)) {
6339 case VMCS_FIELD_TYPE_U16:
6340 vmcs_write16(field, (u16)field_value);
6341 break;
6342 case VMCS_FIELD_TYPE_U32:
6343 vmcs_write32(field, (u32)field_value);
6344 break;
6345 case VMCS_FIELD_TYPE_U64:
6346 vmcs_write64(field, (u64)field_value);
6347 break;
6348 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6349 vmcs_writel(field, (long)field_value);
6350 break;
6351 }
6352 }
6353 }
6354
6355 vmcs_clear(shadow_vmcs);
6356 vmcs_load(vmx->loaded_vmcs->vmcs);
6357}
6358
49f705c5
NHE		 6359/*
6360 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6361 * used before) all generate the same failure when it is missing.
6362 */
6363static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6364{
6365 struct vcpu_vmx *vmx = to_vmx(vcpu);
6366 if (vmx->nested.current_vmptr == -1ull) {
6367 nested_vmx_failInvalid(vcpu);
6368 skip_emulated_instruction(vcpu);
6369 return 0;
6370 }
6371 return 1;
6372}
6373
6374static int handle_vmread(struct kvm_vcpu *vcpu)
6375{
6376 unsigned long field;
6377 u64 field_value;
6378 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6379 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6380 gva_t gva = 0;
6381
6382 if (!nested_vmx_check_permission(vcpu) ||
6383 !nested_vmx_check_vmcs12(vcpu))
6384 return 1;
6385
6386 /* Decode instruction info and find the field to read */
6387 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6388 /* Read the field, zero-extended to a u64 field_value */
6389 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6390 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6391 skip_emulated_instruction(vcpu);
6392 return 1;
6393 }
6394 /*
6395 * Now copy part of this value to register or memory, as requested.
6396 * Note that the number of bits actually copied is 32 or 64 depending
6397 * on the guest's mode (32 or 64 bit), not on the given field's length.
6398 */
6399 if (vmx_instruction_info & (1u << 10)) {
6400 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6401 field_value);
6402 } else {
6403 if (get_vmx_mem_address(vcpu, exit_qualification,
6404 vmx_instruction_info, &gva))
6405 return 1;
6406 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6407 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6408 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6409 }
6410
6411 nested_vmx_succeed(vcpu);
6412 skip_emulated_instruction(vcpu);
6413 return 1;
6414}
6415
6416
6417static int handle_vmwrite(struct kvm_vcpu *vcpu)
6418{
6419 unsigned long field;
6420 gva_t gva;
6421 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6422 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6423 /* The value to write might be 32 or 64 bits, depending on L1's long
6424 * mode, and eventually we need to write that into a field of several
6425 * possible lengths. The code below first zero-extends the value to 64
6426 * bit (field_value), and then copies only the approriate number of
6427 * bits into the vmcs12 field.
6428 */
6429 u64 field_value = 0;
6430 struct x86_exception e;
6431
6432 if (!nested_vmx_check_permission(vcpu) ||
6433 !nested_vmx_check_vmcs12(vcpu))
6434 return 1;
6435
6436 if (vmx_instruction_info & (1u << 10))
6437 field_value = kvm_register_read(vcpu,
6438 (((vmx_instruction_info) >> 3) & 0xf));
6439 else {
6440 if (get_vmx_mem_address(vcpu, exit_qualification,
6441 vmx_instruction_info, &gva))
6442 return 1;
6443 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6444 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6445 kvm_inject_page_fault(vcpu, &e);
6446 return 1;
6447 }
6448 }
6449
6450
6451 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6452 if (vmcs_field_readonly(field)) {
6453 nested_vmx_failValid(vcpu,
6454 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6455 skip_emulated_instruction(vcpu);
6456 return 1;
6457 }
6458
20b97fea 6459 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6460 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6461 skip_emulated_instruction(vcpu);
6462 return 1;
6463 }
6464
6465 nested_vmx_succeed(vcpu);
6466 skip_emulated_instruction(vcpu);
6467 return 1;
6468}
6469
63846663
NHE		 6470/* Emulate the VMPTRLD instruction */
6471static int handle_vmptrld(struct kvm_vcpu *vcpu)
6472{
6473 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6474 gpa_t vmptr;
8a1b9dd0 6475 u32 exec_control;
63846663
NHE		 6476
6477 if (!nested_vmx_check_permission(vcpu))
6478 return 1;
6479
4291b588 6480 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6481 return 1;
63846663
NHE		 6482
6483 if (vmx->nested.current_vmptr != vmptr) {
6484 struct vmcs12 *new_vmcs12;
6485 struct page *page;
6486 page = nested_get_page(vcpu, vmptr);
6487 if (page == NULL) {
6488 nested_vmx_failInvalid(vcpu);
6489 skip_emulated_instruction(vcpu);
6490 return 1;
6491 }
6492 new_vmcs12 = kmap(page);
6493 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6494 kunmap(page);
6495 nested_release_page_clean(page);
6496 nested_vmx_failValid(vcpu,
6497 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6498 skip_emulated_instruction(vcpu);
6499 return 1;
6500 }
e7953d7f
AG		 6501 if (vmx->nested.current_vmptr != -1ull)
6502 nested_release_vmcs12(vmx);
63846663
NHE		 6503
6504 vmx->nested.current_vmptr = vmptr;
6505 vmx->nested.current_vmcs12 = new_vmcs12;
6506 vmx->nested.current_vmcs12_page = page;
012f83cb 6507 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6508 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6509 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6510 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6511 vmcs_write64(VMCS_LINK_POINTER,
6512 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6513 vmx->nested.sync_shadow_vmcs = true;
6514 }
63846663
NHE		 6515 }
6516
6517 nested_vmx_succeed(vcpu);
6518 skip_emulated_instruction(vcpu);
6519 return 1;
6520}
6521
6a4d7550
NHE		 6522/* Emulate the VMPTRST instruction */
6523static int handle_vmptrst(struct kvm_vcpu *vcpu)
6524{
6525 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6526 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6527 gva_t vmcs_gva;
6528 struct x86_exception e;
6529
6530 if (!nested_vmx_check_permission(vcpu))
6531 return 1;
6532
6533 if (get_vmx_mem_address(vcpu, exit_qualification,
6534 vmx_instruction_info, &vmcs_gva))
6535 return 1;
6536 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6537 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6538 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6539 sizeof(u64), &e)) {
6540 kvm_inject_page_fault(vcpu, &e);
6541 return 1;
6542 }
6543 nested_vmx_succeed(vcpu);
6544 skip_emulated_instruction(vcpu);
6545 return 1;
6546}
6547
bfd0a56b
NHE		 6548/* Emulate the INVEPT instruction */
6549static int handle_invept(struct kvm_vcpu *vcpu)
6550{
6551 u32 vmx_instruction_info, types;
6552 unsigned long type;
6553 gva_t gva;
6554 struct x86_exception e;
6555 struct {
6556 u64 eptp, gpa;
6557 } operand;
bfd0a56b
NHE		 6558
6559 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6560 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6561 kvm_queue_exception(vcpu, UD_VECTOR);
6562 return 1;
6563 }
6564
6565 if (!nested_vmx_check_permission(vcpu))
6566 return 1;
6567
6568 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6569 kvm_queue_exception(vcpu, UD_VECTOR);
6570 return 1;
6571 }
6572
6573 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6574 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6575
6576 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6577
6578 if (!(types & (1UL << type))) {
6579 nested_vmx_failValid(vcpu,
6580 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6581 return 1;
6582 }
6583
6584 /* According to the Intel VMX instruction reference, the memory
6585 * operand is read even if it isn't needed (e.g., for type==global)
6586 */
6587 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6588 vmx_instruction_info, &gva))
6589 return 1;
6590 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6591 sizeof(operand), &e)) {
6592 kvm_inject_page_fault(vcpu, &e);
6593 return 1;
6594 }
6595
6596 switch (type) {
bfd0a56b
NHE		 6597 case VMX_EPT_EXTENT_GLOBAL:
6598 kvm_mmu_sync_roots(vcpu);
6599 kvm_mmu_flush_tlb(vcpu);
6600 nested_vmx_succeed(vcpu);
6601 break;
6602 default:
4b855078 6603 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6604 BUG_ON(1);
6605 break;
6606 }
6607
6608 skip_emulated_instruction(vcpu);
6609 return 1;
6610}
6611
6aa8b732
AK		 6612/*
6613 * The exit handlers return 1 if the exit was handled fully and guest execution
6614 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6615 * to be done to userspace and return 0.
6616 */
772e0318 6617static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6618 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6619 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6620 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6621 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6622 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6623 [EXIT_REASON_CR_ACCESS] = handle_cr,
6624 [EXIT_REASON_DR_ACCESS] = handle_dr,
6625 [EXIT_REASON_CPUID] = handle_cpuid,
6626 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6627 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6628 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6629 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6630 [EXIT_REASON_INVD] = handle_invd,
a7052897 6631 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6632 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6633 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6634 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6635 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6636 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6637 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6638 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6639 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6640 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6641 [EXIT_REASON_VMOFF] = handle_vmoff,
6642 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6643 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6644 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6645 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6646 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6647 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6648 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6649 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6650 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6651 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6652 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6653 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6654 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6655 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6656 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6657};
6658
6659static const int kvm_vmx_max_exit_handlers =
50a3485c 6660 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6661
908a7bdd
JK		 6662static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6663 struct vmcs12 *vmcs12)
6664{
6665 unsigned long exit_qualification;
6666 gpa_t bitmap, last_bitmap;
6667 unsigned int port;
6668 int size;
6669 u8 b;
6670
908a7bdd 6671 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6672 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6673
6674 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6675
6676 port = exit_qualification >> 16;
6677 size = (exit_qualification & 7) + 1;
6678
6679 last_bitmap = (gpa_t)-1;
6680 b = -1;
6681
6682 while (size > 0) {
6683 if (port < 0x8000)
6684 bitmap = vmcs12->io_bitmap_a;
6685 else if (port < 0x10000)
6686 bitmap = vmcs12->io_bitmap_b;
6687 else
6688 return 1;
6689 bitmap += (port & 0x7fff) / 8;
6690
6691 if (last_bitmap != bitmap)
6692 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6693 return 1;
6694 if (b & (1 << (port & 7)))
6695 return 1;
6696
6697 port++;
6698 size--;
6699 last_bitmap = bitmap;
6700 }
6701
6702 return 0;
6703}
6704
644d711a
NHE		 6705/*
6706 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6707 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6708 * disinterest in the current event (read or write a specific MSR) by using an
6709 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6710 */
6711static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6712 struct vmcs12 *vmcs12, u32 exit_reason)
6713{
6714 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6715 gpa_t bitmap;
6716
cbd29cb6 6717 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6718 return 1;
6719
6720 /*
6721 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6722 * for the four combinations of read/write and low/high MSR numbers.
6723 * First we need to figure out which of the four to use:
6724 */
6725 bitmap = vmcs12->msr_bitmap;
6726 if (exit_reason == EXIT_REASON_MSR_WRITE)
6727 bitmap += 2048;
6728 if (msr_index >= 0xc0000000) {
6729 msr_index -= 0xc0000000;
6730 bitmap += 1024;
6731 }
6732
6733 /* Then read the msr_index'th bit from this bitmap: */
6734 if (msr_index < 1024*8) {
6735 unsigned char b;
bd31a7f5
JK		 6736 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6737 return 1;
644d711a
NHE		 6738 return 1 & (b >> (msr_index & 7));
6739 } else
6740 return 1; /* let L1 handle the wrong parameter */
6741}
6742
6743/*
6744 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6745 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6746 * intercept (via guest_host_mask etc.) the current event.
6747 */
6748static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6749 struct vmcs12 *vmcs12)
6750{
6751 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6752 int cr = exit_qualification & 15;
6753 int reg = (exit_qualification >> 8) & 15;
6754 unsigned long val = kvm_register_read(vcpu, reg);
6755
6756 switch ((exit_qualification >> 4) & 3) {
6757 case 0: /* mov to cr */
6758 switch (cr) {
6759 case 0:
6760 if (vmcs12->cr0_guest_host_mask &
6761 (val ^ vmcs12->cr0_read_shadow))
6762 return 1;
6763 break;
6764 case 3:
6765 if ((vmcs12->cr3_target_count >= 1 &&
6766 vmcs12->cr3_target_value0 == val) ||
6767 (vmcs12->cr3_target_count >= 2 &&
6768 vmcs12->cr3_target_value1 == val) ||
6769 (vmcs12->cr3_target_count >= 3 &&
6770 vmcs12->cr3_target_value2 == val) ||
6771 (vmcs12->cr3_target_count >= 4 &&
6772 vmcs12->cr3_target_value3 == val))
6773 return 0;
6774 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6775 return 1;
6776 break;
6777 case 4:
6778 if (vmcs12->cr4_guest_host_mask &
6779 (vmcs12->cr4_read_shadow ^ val))
6780 return 1;
6781 break;
6782 case 8:
6783 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6784 return 1;
6785 break;
6786 }
6787 break;
6788 case 2: /* clts */
6789 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6790 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6791 return 1;
6792 break;
6793 case 1: /* mov from cr */
6794 switch (cr) {
6795 case 3:
6796 if (vmcs12->cpu_based_vm_exec_control &
6797 CPU_BASED_CR3_STORE_EXITING)
6798 return 1;
6799 break;
6800 case 8:
6801 if (vmcs12->cpu_based_vm_exec_control &
6802 CPU_BASED_CR8_STORE_EXITING)
6803 return 1;
6804 break;
6805 }
6806 break;
6807 case 3: /* lmsw */
6808 /*
6809 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6810 * cr0. Other attempted changes are ignored, with no exit.
6811 */
6812 if (vmcs12->cr0_guest_host_mask & 0xe &
6813 (val ^ vmcs12->cr0_read_shadow))
6814 return 1;
6815 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6816 !(vmcs12->cr0_read_shadow & 0x1) &&
6817 (val & 0x1))
6818 return 1;
6819 break;
6820 }
6821 return 0;
6822}
6823
6824/*
6825 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6826 * should handle it ourselves in L0 (and then continue L2). Only call this
6827 * when in is_guest_mode (L2).
6828 */
6829static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6830{
644d711a
NHE		 6831 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6832 struct vcpu_vmx *vmx = to_vmx(vcpu);
6833 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6834 u32 exit_reason = vmx->exit_reason;
644d711a 6835
542060ea
JK		 6836 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6837 vmcs_readl(EXIT_QUALIFICATION),
6838 vmx->idt_vectoring_info,
6839 intr_info,
6840 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6841 KVM_ISA_VMX);
6842
644d711a
NHE		 6843 if (vmx->nested.nested_run_pending)
6844 return 0;
6845
6846 if (unlikely(vmx->fail)) {
bd80158a
JK		 6847 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6848 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6849 return 1;
6850 }
6851
6852 switch (exit_reason) {
6853 case EXIT_REASON_EXCEPTION_NMI:
6854 if (!is_exception(intr_info))
6855 return 0;
6856 else if (is_page_fault(intr_info))
6857 return enable_ept;
e504c909 6858 else if (is_no_device(intr_info) &&
ccf9844e 6859 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6860 return 0;
644d711a
NHE		 6861 return vmcs12->exception_bitmap &
6862 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6863 case EXIT_REASON_EXTERNAL_INTERRUPT:
6864 return 0;
6865 case EXIT_REASON_TRIPLE_FAULT:
6866 return 1;
6867 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6868 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6869 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6870 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6871 case EXIT_REASON_TASK_SWITCH:
6872 return 1;
6873 case EXIT_REASON_CPUID:
6874 return 1;
6875 case EXIT_REASON_HLT:
6876 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6877 case EXIT_REASON_INVD:
6878 return 1;
6879 case EXIT_REASON_INVLPG:
6880 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6881 case EXIT_REASON_RDPMC:
6882 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6883 case EXIT_REASON_RDTSC:
6884 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6885 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6886 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6887 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6888 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6889 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6890 case EXIT_REASON_INVEPT:
644d711a
NHE		 6891 /*
6892 * VMX instructions trap unconditionally. This allows L1 to
6893 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6894 */
6895 return 1;
6896 case EXIT_REASON_CR_ACCESS:
6897 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6898 case EXIT_REASON_DR_ACCESS:
6899 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6900 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6901 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6902 case EXIT_REASON_MSR_READ:
6903 case EXIT_REASON_MSR_WRITE:
6904 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6905 case EXIT_REASON_INVALID_STATE:
6906 return 1;
6907 case EXIT_REASON_MWAIT_INSTRUCTION:
6908 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6909 case EXIT_REASON_MONITOR_INSTRUCTION:
6910 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6911 case EXIT_REASON_PAUSE_INSTRUCTION:
6912 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6913 nested_cpu_has2(vmcs12,
6914 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6915 case EXIT_REASON_MCE_DURING_VMENTRY:
6916 return 0;
6917 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6918 return 1;
6919 case EXIT_REASON_APIC_ACCESS:
6920 return nested_cpu_has2(vmcs12,
6921 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6922 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6923 /*
6924 * L0 always deals with the EPT violation. If nested EPT is
6925 * used, and the nested mmu code discovers that the address is
6926 * missing in the guest EPT table (EPT12), the EPT violation
6927 * will be injected with nested_ept_inject_page_fault()
6928 */
6929 return 0;
644d711a 6930 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6931 /*
6932 * L2 never uses directly L1's EPT, but rather L0's own EPT
6933 * table (shadow on EPT) or a merged EPT table that L0 built
6934 * (EPT on EPT). So any problems with the structure of the
6935 * table is L0's fault.
6936 */
644d711a
NHE		 6937 return 0;
6938 case EXIT_REASON_WBINVD:
6939 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6940 case EXIT_REASON_XSETBV:
6941 return 1;
6942 default:
6943 return 1;
6944 }
6945}
6946
586f9607
AK		 6947static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6948{
6949 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6950 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6951}
6952
6aa8b732
AK		 6953/*
6954 * The guest has exited. See if we can fix it or if we need userspace
6955 * assistance.
6956 */
851ba692 6957static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6958{
29bd8a78 6959 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6960 u32 exit_reason = vmx->exit_reason;
1155f76a 6961 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6962
80ced186 6963 /* If guest state is invalid, start emulating */
14168786 6964 if (vmx->emulation_required)
80ced186 6965 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6966
644d711a 6967 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6968 nested_vmx_vmexit(vcpu, exit_reason,
6969 vmcs_read32(VM_EXIT_INTR_INFO),
6970 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6971 return 1;
6972 }
6973
5120702e
MG		 6974 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6975 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6976 vcpu->run->fail_entry.hardware_entry_failure_reason
6977 = exit_reason;
6978 return 0;
6979 }
6980
29bd8a78 6981 if (unlikely(vmx->fail)) {
851ba692
AK		 6982 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6983 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6984 = vmcs_read32(VM_INSTRUCTION_ERROR);
6985 return 0;
6986 }
6aa8b732 6987
b9bf6882
XG		 6988 /*
6989 * Note:
6990 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6991 * delivery event since it indicates guest is accessing MMIO.
6992 * The vm-exit can be triggered again after return to guest that
6993 * will cause infinite loop.
6994 */
d77c26fc 6995 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6996 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6997 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6998 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6999 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7000 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7001 vcpu->run->internal.ndata = 2;
7002 vcpu->run->internal.data[0] = vectoring_info;
7003 vcpu->run->internal.data[1] = exit_reason;
7004 return 0;
7005 }
3b86cd99 7006
644d711a
NHE		 7007 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7008 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7009 get_vmcs12(vcpu))))) {
c4282df9 7010 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7011 vmx->soft_vnmi_blocked = 0;
3b86cd99 7012 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7013 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7014 /*
7015 * This CPU don't support us in finding the end of an
7016 * NMI-blocked window if the guest runs with IRQs
7017 * disabled. So we pull the trigger after 1 s of
7018 * futile waiting, but inform the user about this.
7019 */
7020 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7021 "state on VCPU %d after 1 s timeout\n",
7022 __func__, vcpu->vcpu_id);
7023 vmx->soft_vnmi_blocked = 0;
3b86cd99 7024 }
3b86cd99
JK		 7025 }
7026
6aa8b732
AK		 7027 if (exit_reason < kvm_vmx_max_exit_handlers
7028 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7029 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7030 else {
851ba692
AK		 7031 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7032 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7033 }
7034 return 0;
7035}
7036
95ba8273 7037static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7038{
95ba8273 7039 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7040 vmcs_write32(TPR_THRESHOLD, 0);
7041 return;
7042 }
7043
95ba8273 7044 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7045}
7046
8d14695f
YZ		 7047static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7048{
7049 u32 sec_exec_control;
7050
7051 /*
7052 * There is not point to enable virtualize x2apic without enable
7053 * apicv
7054 */
c7c9c56c
YZ		 7055 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7056 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7057 return;
7058
7059 if (!vm_need_tpr_shadow(vcpu->kvm))
7060 return;
7061
7062 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7063
7064 if (set) {
7065 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7066 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7067 } else {
7068 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7069 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7070 }
7071 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7072
7073 vmx_set_msr_bitmap(vcpu);
7074}
7075
c7c9c56c
YZ		 7076static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7077{
7078 u16 status;
7079 u8 old;
7080
7081 if (!vmx_vm_has_apicv(kvm))
7082 return;
7083
7084 if (isr == -1)
7085 isr = 0;
7086
7087 status = vmcs_read16(GUEST_INTR_STATUS);
7088 old = status >> 8;
7089 if (isr != old) {
7090 status &= 0xff;
7091 status |= isr << 8;
7092 vmcs_write16(GUEST_INTR_STATUS, status);
7093 }
7094}
7095
7096static void vmx_set_rvi(int vector)
7097{
7098 u16 status;
7099 u8 old;
7100
7101 status = vmcs_read16(GUEST_INTR_STATUS);
7102 old = (u8)status & 0xff;
7103 if ((u8)vector != old) {
7104 status &= ~0xff;
7105 status |= (u8)vector;
7106 vmcs_write16(GUEST_INTR_STATUS, status);
7107 }
7108}
7109
7110static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7111{
7112 if (max_irr == -1)
7113 return;
7114
7115 vmx_set_rvi(max_irr);
7116}
7117
7118static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7119{
3d81bc7e
YZ		 7120 if (!vmx_vm_has_apicv(vcpu->kvm))
7121 return;
7122
c7c9c56c
YZ		 7123 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7124 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7125 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7126 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7127}
7128
51aa01d1 7129static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7130{
00eba012
AK		 7131 u32 exit_intr_info;
7132
7133 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7134 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7135 return;
7136
c5ca8e57 7137 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7138 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7139
7140 /* Handle machine checks before interrupts are enabled */
00eba012 7141 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7142 kvm_machine_check();
7143
20f65983 7144 /* We need to handle NMIs before interrupts are enabled */
00eba012 7145 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7146 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7147 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7148 asm("int $2");
ff9d07a0
ZY		 7149 kvm_after_handle_nmi(&vmx->vcpu);
7150 }
51aa01d1 7151}
20f65983 7152
a547c6db
YZ		 7153static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7154{
7155 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7156
7157 /*
7158 * If external interrupt exists, IF bit is set in rflags/eflags on the
7159 * interrupt stack frame, and interrupt will be enabled on a return
7160 * from interrupt handler.
7161 */
7162 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7163 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7164 unsigned int vector;
7165 unsigned long entry;
7166 gate_desc *desc;
7167 struct vcpu_vmx *vmx = to_vmx(vcpu);
7168#ifdef CONFIG_X86_64
7169 unsigned long tmp;
7170#endif
7171
7172 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7173 desc = (gate_desc *)vmx->host_idt_base + vector;
7174 entry = gate_offset(*desc);
7175 asm volatile(
7176#ifdef CONFIG_X86_64
7177 "mov %%" _ASM_SP ", %[sp]\n\t"
7178 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7179 "push $%c[ss]\n\t"
7180 "push %[sp]\n\t"
7181#endif
7182 "pushf\n\t"
7183 "orl $0x200, (%%" _ASM_SP ")\n\t"
7184 __ASM_SIZE(push) " $%c[cs]\n\t"
7185 "call *%[entry]\n\t"
7186 :
7187#ifdef CONFIG_X86_64
7188 [sp]"=&r"(tmp)
7189#endif
7190 :
7191 [entry]"r"(entry),
7192 [ss]"i"(__KERNEL_DS),
7193 [cs]"i"(__KERNEL_CS)
7194 );
7195 } else
7196 local_irq_enable();
7197}
7198
da8999d3
LJ		 7199static bool vmx_mpx_supported(void)
7200{
7201 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7202 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7203}
7204
51aa01d1
AK		 7205static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7206{
c5ca8e57 7207 u32 exit_intr_info;
51aa01d1
AK		 7208 bool unblock_nmi;
7209 u8 vector;
7210 bool idtv_info_valid;
7211
7212 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7213
cf393f75 7214 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7215 if (vmx->nmi_known_unmasked)
7216 return;
c5ca8e57
AK		 7217 /*
7218 * Can't use vmx->exit_intr_info since we're not sure what
7219 * the exit reason is.
7220 */
7221 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7222 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7223 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7224 /*
7b4a25cb 7225 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7226 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7227 * a guest IRET fault.
7b4a25cb
GN		 7228 * SDM 3: 23.2.2 (September 2008)
7229 * Bit 12 is undefined in any of the following cases:
7230 * If the VM exit sets the valid bit in the IDT-vectoring
7231 * information field.
7232 * If the VM exit is due to a double fault.
cf393f75 7233 */
7b4a25cb
GN		 7234 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7235 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7236 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7237 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7238 else
7239 vmx->nmi_known_unmasked =
7240 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7241 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7242 } else if (unlikely(vmx->soft_vnmi_blocked))
7243 vmx->vnmi_blocked_time +=
7244 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7245}
7246
3ab66e8a 7247static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7248 u32 idt_vectoring_info,
7249 int instr_len_field,
7250 int error_code_field)
51aa01d1 7251{
51aa01d1
AK		 7252 u8 vector;
7253 int type;
7254 bool idtv_info_valid;
7255
7256 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7257
3ab66e8a
JK		 7258 vcpu->arch.nmi_injected = false;
7259 kvm_clear_exception_queue(vcpu);
7260 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7261
7262 if (!idtv_info_valid)
7263 return;
7264
3ab66e8a 7265 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7266
668f612f
AK		 7267 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7268 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7269
64a7ec06 7270 switch (type) {
37b96e98 7271 case INTR_TYPE_NMI_INTR:
3ab66e8a 7272 vcpu->arch.nmi_injected = true;
668f612f 7273 /*
7b4a25cb 7274 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7275 * Clear bit "block by NMI" before VM entry if a NMI
7276 * delivery faulted.
668f612f 7277 */
3ab66e8a 7278 vmx_set_nmi_mask(vcpu, false);
37b96e98 7279 break;
37b96e98 7280 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7281 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7282 /* fall through */
7283 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7284 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7285 u32 err = vmcs_read32(error_code_field);
851eb667 7286 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7287 } else
851eb667 7288 kvm_requeue_exception(vcpu, vector);
37b96e98 7289 break;
66fd3f7f 7290 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7291 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7292 /* fall through */
37b96e98 7293 case INTR_TYPE_EXT_INTR:
3ab66e8a 7294 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7295 break;
7296 default:
7297 break;
f7d9238f 7298 }
cf393f75
AK		 7299}
7300
83422e17
AK		 7301static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7302{
3ab66e8a 7303 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7304 VM_EXIT_INSTRUCTION_LEN,
7305 IDT_VECTORING_ERROR_CODE);
7306}
7307
b463a6f7
AK		 7308static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7309{
3ab66e8a 7310 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7311 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7312 VM_ENTRY_INSTRUCTION_LEN,
7313 VM_ENTRY_EXCEPTION_ERROR_CODE);
7314
7315 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7316}
7317
d7cd9796
GN		 7318static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7319{
7320 int i, nr_msrs;
7321 struct perf_guest_switch_msr *msrs;
7322
7323 msrs = perf_guest_get_msrs(&nr_msrs);
7324
7325 if (!msrs)
7326 return;
7327
7328 for (i = 0; i < nr_msrs; i++)
7329 if (msrs[i].host == msrs[i].guest)
7330 clear_atomic_switch_msr(vmx, msrs[i].msr);
7331 else
7332 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7333 msrs[i].host);
7334}
7335
a3b5ba49 7336static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7337{
a2fa3e9f 7338 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7339 unsigned long debugctlmsr;
104f226b
AK		 7340
7341 /* Record the guest's net vcpu time for enforced NMI injections. */
7342 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7343 vmx->entry_time = ktime_get();
7344
7345 /* Don't enter VMX if guest state is invalid, let the exit handler
7346 start emulation until we arrive back to a valid state */
14168786 7347 if (vmx->emulation_required)
104f226b
AK		 7348 return;
7349
012f83cb
AG		 7350 if (vmx->nested.sync_shadow_vmcs) {
7351 copy_vmcs12_to_shadow(vmx);
7352 vmx->nested.sync_shadow_vmcs = false;
7353 }
7354
104f226b
AK		 7355 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7356 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7357 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7358 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7359
7360 /* When single-stepping over STI and MOV SS, we must clear the
7361 * corresponding interruptibility bits in the guest state. Otherwise
7362 * vmentry fails as it then expects bit 14 (BS) in pending debug
7363 * exceptions being set, but that's not correct for the guest debugging
7364 * case. */
7365 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7366 vmx_set_interrupt_shadow(vcpu, 0);
7367
d7cd9796 7368 atomic_switch_perf_msrs(vmx);
2a7921b7 7369 debugctlmsr = get_debugctlmsr();
d7cd9796 7370
d462b819 7371 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7372 asm(
6aa8b732 7373 /* Store host registers */
b188c81f
AK		 7374 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7375 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7376 "push %%" _ASM_CX " \n\t"
7377 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7378 "je 1f \n\t"
b188c81f 7379 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7380 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7381 "1: \n\t"
d3edefc0 7382 /* Reload cr2 if changed */
b188c81f
AK		 7383 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7384 "mov %%cr2, %%" _ASM_DX " \n\t"
7385 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7386 "je 2f \n\t"
b188c81f 7387 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7388 "2: \n\t"
6aa8b732 7389 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7390 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7391 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7392 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7393 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7394 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7395 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7396 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7397 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7398#ifdef CONFIG_X86_64
e08aa78a
AK		 7399 "mov %c[r8](%0), %%r8 \n\t"
7400 "mov %c[r9](%0), %%r9 \n\t"
7401 "mov %c[r10](%0), %%r10 \n\t"
7402 "mov %c[r11](%0), %%r11 \n\t"
7403 "mov %c[r12](%0), %%r12 \n\t"
7404 "mov %c[r13](%0), %%r13 \n\t"
7405 "mov %c[r14](%0), %%r14 \n\t"
7406 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7407#endif
b188c81f 7408 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7409
6aa8b732 7410 /* Enter guest mode */
83287ea4 7411 "jne 1f \n\t"
4ecac3fd 7412 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7413 "jmp 2f \n\t"
7414 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7415 "2: "
6aa8b732 7416 /* Save guest registers, load host registers, keep flags */
b188c81f 7417 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7418 "pop %0 \n\t"
b188c81f
AK		 7419 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7420 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7421 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7422 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7423 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7424 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7425 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7426#ifdef CONFIG_X86_64
e08aa78a
AK		 7427 "mov %%r8, %c[r8](%0) \n\t"
7428 "mov %%r9, %c[r9](%0) \n\t"
7429 "mov %%r10, %c[r10](%0) \n\t"
7430 "mov %%r11, %c[r11](%0) \n\t"
7431 "mov %%r12, %c[r12](%0) \n\t"
7432 "mov %%r13, %c[r13](%0) \n\t"
7433 "mov %%r14, %c[r14](%0) \n\t"
7434 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7435#endif
b188c81f
AK		 7436 "mov %%cr2, %%" _ASM_AX " \n\t"
7437 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7438
b188c81f 7439 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7440 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7441 ".pushsection .rodata \n\t"
7442 ".global vmx_return \n\t"
7443 "vmx_return: " _ASM_PTR " 2b \n\t"
7444 ".popsection"
e08aa78a 7445 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7446 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7447 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7448 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7449 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7450 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7451 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7452 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7453 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7454 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7455 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7456#ifdef CONFIG_X86_64
ad312c7c
ZX		 7457 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7458 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7459 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7460 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7461 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7462 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7463 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7464 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7465#endif
40712fae
AK		 7466 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7467 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7468 : "cc", "memory"
7469#ifdef CONFIG_X86_64
b188c81f 7470 , "rax", "rbx", "rdi", "rsi"
c2036300 7471 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7472#else
7473 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7474#endif
7475 );
6aa8b732 7476
2a7921b7
GN		 7477 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7478 if (debugctlmsr)
7479 update_debugctlmsr(debugctlmsr);
7480
aa67f609
AK		 7481#ifndef CONFIG_X86_64
7482 /*
7483 * The sysexit path does not restore ds/es, so we must set them to
7484 * a reasonable value ourselves.
7485 *
7486 * We can't defer this to vmx_load_host_state() since that function
7487 * may be executed in interrupt context, which saves and restore segments
7488 * around it, nullifying its effect.
7489 */
7490 loadsegment(ds, __USER_DS);
7491 loadsegment(es, __USER_DS);
7492#endif
7493
6de4f3ad 7494 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7495 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7496 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7497 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7498 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7499 vcpu->arch.regs_dirty = 0;
7500
1155f76a
AK		 7501 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7502
d462b819 7503 vmx->loaded_vmcs->launched = 1;
1b6269db 7504
51aa01d1 7505 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7506 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7507
e0b890d3
GN		 7508 /*
7509 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7510 * we did not inject a still-pending event to L1 now because of
7511 * nested_run_pending, we need to re-enable this bit.
7512 */
7513 if (vmx->nested.nested_run_pending)
7514 kvm_make_request(KVM_REQ_EVENT, vcpu);
7515
7516 vmx->nested.nested_run_pending = 0;
7517
51aa01d1
AK		 7518 vmx_complete_atomic_exit(vmx);
7519 vmx_recover_nmi_blocking(vmx);
cf393f75 7520 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7521}
7522
6aa8b732
AK		 7523static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7524{
fb3f0f51
RR		 7525 struct vcpu_vmx *vmx = to_vmx(vcpu);
7526
cdbecfc3 7527 free_vpid(vmx);
d462b819 7528 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7529 free_nested(vmx);
fb3f0f51
RR		 7530 kfree(vmx->guest_msrs);
7531 kvm_vcpu_uninit(vcpu);
a4770347 7532 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7533}
7534
fb3f0f51 7535static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7536{
fb3f0f51 7537 int err;
c16f862d 7538 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7539 int cpu;
6aa8b732 7540
a2fa3e9f 7541 if (!vmx)
fb3f0f51
RR		 7542 return ERR_PTR(-ENOMEM);
7543
2384d2b3
SY		 7544 allocate_vpid(vmx);
7545
fb3f0f51
RR		 7546 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7547 if (err)
7548 goto free_vcpu;
965b58a5 7549
a2fa3e9f 7550 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7551 err = -ENOMEM;
fb3f0f51 7552 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7553 goto uninit_vcpu;
7554 }
965b58a5 7555
d462b819
NHE		 7556 vmx->loaded_vmcs = &vmx->vmcs01;
7557 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7558 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7559 goto free_msrs;
d462b819
NHE		 7560 if (!vmm_exclusive)
7561 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7562 loaded_vmcs_init(vmx->loaded_vmcs);
7563 if (!vmm_exclusive)
7564 kvm_cpu_vmxoff();
a2fa3e9f 7565
15ad7146
AK		 7566 cpu = get_cpu();
7567 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7568 vmx->vcpu.cpu = cpu;
8b9cf98c 7569 err = vmx_vcpu_setup(vmx);
fb3f0f51 7570 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7571 put_cpu();
fb3f0f51
RR		 7572 if (err)
7573 goto free_vmcs;
a63cb560 7574 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7575 err = alloc_apic_access_page(kvm);
7576 if (err)
5e4a0b3c 7577 goto free_vmcs;
a63cb560 7578 }
fb3f0f51 7579
b927a3ce
SY		 7580 if (enable_ept) {
7581 if (!kvm->arch.ept_identity_map_addr)
7582 kvm->arch.ept_identity_map_addr =
7583 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7584 err = -ENOMEM;
b7ebfb05
SY		 7585 if (alloc_identity_pagetable(kvm) != 0)
7586 goto free_vmcs;
93ea5388
GN		 7587 if (!init_rmode_identity_map(kvm))
7588 goto free_vmcs;
b927a3ce 7589 }
b7ebfb05 7590
a9d30f33
NHE		 7591 vmx->nested.current_vmptr = -1ull;
7592 vmx->nested.current_vmcs12 = NULL;
7593
fb3f0f51
RR		 7594 return &vmx->vcpu;
7595
7596free_vmcs:
5f3fbc34 7597 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7598free_msrs:
fb3f0f51
RR		 7599 kfree(vmx->guest_msrs);
7600uninit_vcpu:
7601 kvm_vcpu_uninit(&vmx->vcpu);
7602free_vcpu:
cdbecfc3 7603 free_vpid(vmx);
a4770347 7604 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7605 return ERR_PTR(err);
6aa8b732
AK		 7606}
7607
002c7f7c
YS		 7608static void __init vmx_check_processor_compat(void *rtn)
7609{
7610 struct vmcs_config vmcs_conf;
7611
7612 *(int *)rtn = 0;
7613 if (setup_vmcs_config(&vmcs_conf) < 0)
7614 *(int *)rtn = -EIO;
7615 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7616 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7617 smp_processor_id());
7618 *(int *)rtn = -EIO;
7619 }
7620}
7621
67253af5
SY		 7622static int get_ept_level(void)
7623{
7624 return VMX_EPT_DEFAULT_GAW + 1;
7625}
7626
4b12f0de 7627static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7628{
4b12f0de
SY		 7629 u64 ret;
7630
522c68c4
SY		 7631 /* For VT-d and EPT combination
7632 * 1. MMIO: always map as UC
7633 * 2. EPT with VT-d:
7634 * a. VT-d without snooping control feature: can't guarantee the
7635 * result, try to trust guest.
7636 * b. VT-d with snooping control feature: snooping control feature of
7637 * VT-d engine can guarantee the cache correctness. Just set it
7638 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7639 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7640 * consistent with host MTRR
7641 */
4b12f0de
SY		 7642 if (is_mmio)
7643 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7644 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7645 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7646 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7647 else
522c68c4 7648 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7649 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7650
7651 return ret;
64d4d521
SY		 7652}
7653
17cc3935 7654static int vmx_get_lpage_level(void)
344f414f 7655{
878403b7
SY		 7656 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7657 return PT_DIRECTORY_LEVEL;
7658 else
7659 /* For shadow and EPT supported 1GB page */
7660 return PT_PDPE_LEVEL;
344f414f
JR		 7661}
7662
0e851880
SY		 7663static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7664{
4e47c7a6
SY		 7665 struct kvm_cpuid_entry2 *best;
7666 struct vcpu_vmx *vmx = to_vmx(vcpu);
7667 u32 exec_control;
7668
7669 vmx->rdtscp_enabled = false;
7670 if (vmx_rdtscp_supported()) {
7671 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7672 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7673 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7674 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7675 vmx->rdtscp_enabled = true;
7676 else {
7677 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7678 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7679 exec_control);
7680 }
7681 }
7682 }
ad756a16 7683
ad756a16
MJ		 7684 /* Exposing INVPCID only when PCID is exposed */
7685 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7686 if (vmx_invpcid_supported() &&
4f977045 7687 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7688 guest_cpuid_has_pcid(vcpu)) {
29282fde 7689 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7690 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7691 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7692 exec_control);
7693 } else {
29282fde
TI		 7694 if (cpu_has_secondary_exec_ctrls()) {
7695 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7696 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7697 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7698 exec_control);
7699 }
ad756a16 7700 if (best)
4f977045 7701 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7702 }
0e851880
SY		 7703}
7704
d4330ef2
JR		 7705static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7706{
7b8050f5
NHE		 7707 if (func == 1 && nested)
7708 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7709}
7710
25d92081
YZ		 7711static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7712 struct x86_exception *fault)
7713{
533558bc
JK		 7714 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7715 u32 exit_reason;
25d92081
YZ		 7716
7717 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7718 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7719 else
533558bc
JK		 7720 exit_reason = EXIT_REASON_EPT_VIOLATION;
7721 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7722 vmcs12->guest_physical_address = fault->address;
7723}
7724
155a97a3
NHE		 7725/* Callbacks for nested_ept_init_mmu_context: */
7726
7727static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7728{
7729 /* return the page table to be shadowed - in our case, EPT12 */
7730 return get_vmcs12(vcpu)->ept_pointer;
7731}
7732
8a3c1a33 7733static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7734{
8a3c1a33 7735 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7736 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7737
7738 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7739 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7740 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7741
7742 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7743}
7744
7745static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7746{
7747 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7748}
7749
feaf0c7d
GN		 7750static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7751 struct x86_exception *fault)
7752{
7753 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7754
7755 WARN_ON(!is_guest_mode(vcpu));
7756
7757 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7758 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7759 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7760 vmcs_read32(VM_EXIT_INTR_INFO),
7761 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7762 else
7763 kvm_inject_page_fault(vcpu, fault);
7764}
7765
f4124500
JK		 7766static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7767{
7768 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7769 struct vcpu_vmx *vmx = to_vmx(vcpu);
7770
7771 if (vcpu->arch.virtual_tsc_khz == 0)
7772 return;
7773
7774 /* Make sure short timeouts reliably trigger an immediate vmexit.
7775 * hrtimer_start does not guarantee this. */
7776 if (preemption_timeout <= 1) {
7777 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7778 return;
7779 }
7780
7781 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7782 preemption_timeout *= 1000000;
7783 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7784 hrtimer_start(&vmx->nested.preemption_timer,
7785 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7786}
7787
fe3ef05c
NHE		 7788/*
7789 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7790 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7791 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7792 * guest in a way that will both be appropriate to L1's requests, and our
7793 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7794 * function also has additional necessary side-effects, like setting various
7795 * vcpu->arch fields.
7796 */
7797static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7798{
7799 struct vcpu_vmx *vmx = to_vmx(vcpu);
7800 u32 exec_control;
7801
7802 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7803 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7804 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7805 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7806 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7807 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7808 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7809 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7810 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7811 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7812 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7813 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7814 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7815 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7816 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7817 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7818 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7819 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7820 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7821 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7822 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7823 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7824 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7825 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7826 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7827 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7828 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7829 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7830 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7831 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7832 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7833 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7834 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7835 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7836 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7837 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7838
7839 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7840 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7841 vmcs12->vm_entry_intr_info_field);
7842 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7843 vmcs12->vm_entry_exception_error_code);
7844 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7845 vmcs12->vm_entry_instruction_len);
7846 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7847 vmcs12->guest_interruptibility_info);
fe3ef05c 7848 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7849 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7850 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7851 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7852 vmcs12->guest_pending_dbg_exceptions);
7853 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7854 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7855
7856 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7857
f4124500
JK		 7858 exec_control = vmcs12->pin_based_vm_exec_control;
7859 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 7860 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
7861 PIN_BASED_POSTED_INTR);
f4124500 7862 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7863
f4124500
JK		 7864 vmx->nested.preemption_timer_expired = false;
7865 if (nested_cpu_has_preemption_timer(vmcs12))
7866 vmx_start_preemption_timer(vcpu);
0238ea91 7867
fe3ef05c
NHE		 7868 /*
7869 * Whether page-faults are trapped is determined by a combination of
7870 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7871 * If enable_ept, L0 doesn't care about page faults and we should
7872 * set all of these to L1's desires. However, if !enable_ept, L0 does
7873 * care about (at least some) page faults, and because it is not easy
7874 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7875 * to exit on each and every L2 page fault. This is done by setting
7876 * MASK=MATCH=0 and (see below) EB.PF=1.
7877 * Note that below we don't need special code to set EB.PF beyond the
7878 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7879 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7880 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7881 *
7882 * A problem with this approach (when !enable_ept) is that L1 may be
7883 * injected with more page faults than it asked for. This could have
7884 * caused problems, but in practice existing hypervisors don't care.
7885 * To fix this, we will need to emulate the PFEC checking (on the L1
7886 * page tables), using walk_addr(), when injecting PFs to L1.
7887 */
7888 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7889 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7890 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7891 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7892
7893 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7894 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7895 if (!vmx->rdtscp_enabled)
7896 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7897 /* Take the following fields only from vmcs12 */
696dfd95
PB		 7898 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7899 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
7900 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 7901 if (nested_cpu_has(vmcs12,
7902 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7903 exec_control |= vmcs12->secondary_vm_exec_control;
7904
7905 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7906 /*
7907 * Translate L1 physical address to host physical
7908 * address for vmcs02. Keep the page pinned, so this
7909 * physical address remains valid. We keep a reference
7910 * to it so we can release it later.
7911 */
7912 if (vmx->nested.apic_access_page) /* shouldn't happen */
7913 nested_release_page(vmx->nested.apic_access_page);
7914 vmx->nested.apic_access_page =
7915 nested_get_page(vcpu, vmcs12->apic_access_addr);
7916 /*
7917 * If translation failed, no matter: This feature asks
7918 * to exit when accessing the given address, and if it
7919 * can never be accessed, this feature won't do
7920 * anything anyway.
7921 */
7922 if (!vmx->nested.apic_access_page)
7923 exec_control &=
7924 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7925 else
7926 vmcs_write64(APIC_ACCESS_ADDR,
7927 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7928 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7929 exec_control |=
7930 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7931 vmcs_write64(APIC_ACCESS_ADDR,
7932 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7933 }
7934
7935 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7936 }
7937
7938
7939 /*
7940 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7941 * Some constant fields are set here by vmx_set_constant_host_state().
7942 * Other fields are different per CPU, and will be set later when
7943 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7944 */
a547c6db 7945 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7946
7947 /*
7948 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7949 * entry, but only if the current (host) sp changed from the value
7950 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7951 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7952 * here we just force the write to happen on entry.
7953 */
7954 vmx->host_rsp = 0;
7955
7956 exec_control = vmx_exec_control(vmx); /* L0's desires */
7957 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7958 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7959 exec_control &= ~CPU_BASED_TPR_SHADOW;
7960 exec_control |= vmcs12->cpu_based_vm_exec_control;
7961 /*
7962 * Merging of IO and MSR bitmaps not currently supported.
7963 * Rather, exit every time.
7964 */
7965 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7966 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7967 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7968
7969 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7970
7971 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7972 * bitwise-or of what L1 wants to trap for L2, and what we want to
7973 * trap. Note that CR0.TS also needs updating - we do this later.
7974 */
7975 update_exception_bitmap(vcpu);
7976 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7977 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7978
8049d651
NHE		 7979 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7980 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7981 * bits are further modified by vmx_set_efer() below.
7982 */
f4124500 7983 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7984
7985 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7986 * emulated by vmx_set_efer(), below.
7987 */
2961e876 7988 vm_entry_controls_init(vmx,
8049d651
NHE		 7989 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7990 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7991 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7992
44811c02 7993 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7994 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7995 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7996 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7997 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7998
7999
8000 set_cr4_guest_host_mask(vmx);
8001
36be0b9d
PB		 8002 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8003 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8004
27fc51b2
NHE		 8005 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8006 vmcs_write64(TSC_OFFSET,
8007 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8008 else
8009 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8010
8011 if (enable_vpid) {
8012 /*
8013 * Trivially support vpid by letting L2s share their parent
8014 * L1's vpid. TODO: move to a more elaborate solution, giving
8015 * each L2 its own vpid and exposing the vpid feature to L1.
8016 */
8017 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8018 vmx_flush_tlb(vcpu);
8019 }
8020
155a97a3
NHE		 8021 if (nested_cpu_has_ept(vmcs12)) {
8022 kvm_mmu_unload(vcpu);
8023 nested_ept_init_mmu_context(vcpu);
8024 }
8025
fe3ef05c
NHE		 8026 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8027 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8028 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8029 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8030 else
8031 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8032 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8033 vmx_set_efer(vcpu, vcpu->arch.efer);
8034
8035 /*
8036 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8037 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8038 * The CR0_READ_SHADOW is what L2 should have expected to read given
8039 * the specifications by L1; It's not enough to take
8040 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8041 * have more bits than L1 expected.
8042 */
8043 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8044 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8045
8046 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8047 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8048
8049 /* shadow page tables on either EPT or shadow page tables */
8050 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8051 kvm_mmu_reset_context(vcpu);
8052
feaf0c7d
GN		 8053 if (!enable_ept)
8054 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8055
3633cfc3
NHE		 8056 /*
8057 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8058 */
8059 if (enable_ept) {
8060 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8061 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8062 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8063 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8064 }
8065
fe3ef05c
NHE		 8066 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8067 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8068}
8069
cd232ad0
NHE		 8070/*
8071 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8072 * for running an L2 nested guest.
8073 */
8074static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8075{
8076 struct vmcs12 *vmcs12;
8077 struct vcpu_vmx *vmx = to_vmx(vcpu);
8078 int cpu;
8079 struct loaded_vmcs *vmcs02;
384bb783 8080 bool ia32e;
cd232ad0
NHE		 8081
8082 if (!nested_vmx_check_permission(vcpu) ||
8083 !nested_vmx_check_vmcs12(vcpu))
8084 return 1;
8085
8086 skip_emulated_instruction(vcpu);
8087 vmcs12 = get_vmcs12(vcpu);
8088
012f83cb
AG		 8089 if (enable_shadow_vmcs)
8090 copy_shadow_to_vmcs12(vmx);
8091
7c177938
NHE		 8092 /*
8093 * The nested entry process starts with enforcing various prerequisites
8094 * on vmcs12 as required by the Intel SDM, and act appropriately when
8095 * they fail: As the SDM explains, some conditions should cause the
8096 * instruction to fail, while others will cause the instruction to seem
8097 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8098 * To speed up the normal (success) code path, we should avoid checking
8099 * for misconfigurations which will anyway be caught by the processor
8100 * when using the merged vmcs02.
8101 */
8102 if (vmcs12->launch_state == launch) {
8103 nested_vmx_failValid(vcpu,
8104 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8105 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8106 return 1;
8107 }
8108
6dfacadd
JK		 8109 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8110 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8111 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8112 return 1;
8113 }
8114
7c177938 8115 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8116 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8117 /*TODO: Also verify bits beyond physical address width are 0*/
8118 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8119 return 1;
8120 }
8121
8122 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
bc39c4db 8123 !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
7c177938
NHE		 8124 /*TODO: Also verify bits beyond physical address width are 0*/
8125 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8126 return 1;
8127 }
8128
8129 if (vmcs12->vm_entry_msr_load_count > 0 ||
8130 vmcs12->vm_exit_msr_load_count > 0 ||
8131 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8132 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8133 __func__);
7c177938
NHE		 8134 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8135 return 1;
8136 }
8137
8138 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8139 nested_vmx_true_procbased_ctls_low,
8140 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8141 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8142 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8143 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8144 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8145 !vmx_control_verify(vmcs12->vm_exit_controls,
8146 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8147 !vmx_control_verify(vmcs12->vm_entry_controls,
8148 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8149 {
8150 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8151 return 1;
8152 }
8153
8154 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8155 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8156 nested_vmx_failValid(vcpu,
8157 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8158 return 1;
8159 }
8160
92fbc7b1 8161 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8162 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8163 nested_vmx_entry_failure(vcpu, vmcs12,
8164 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8165 return 1;
8166 }
8167 if (vmcs12->vmcs_link_pointer != -1ull) {
8168 nested_vmx_entry_failure(vcpu, vmcs12,
8169 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8170 return 1;
8171 }
8172
384bb783 8173 /*
cb0c8cda 8174 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8175 * are performed on the field for the IA32_EFER MSR:
8176 * - Bits reserved in the IA32_EFER MSR must be 0.
8177 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8178 * the IA-32e mode guest VM-exit control. It must also be identical
8179 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8180 * CR0.PG) is 1.
8181 */
8182 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8183 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8184 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8185 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8186 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8187 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8188 nested_vmx_entry_failure(vcpu, vmcs12,
8189 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8190 return 1;
8191 }
8192 }
8193
8194 /*
8195 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8196 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8197 * the values of the LMA and LME bits in the field must each be that of
8198 * the host address-space size VM-exit control.
8199 */
8200 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8201 ia32e = (vmcs12->vm_exit_controls &
8202 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8203 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8204 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8205 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8206 nested_vmx_entry_failure(vcpu, vmcs12,
8207 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8208 return 1;
8209 }
8210 }
8211
7c177938
NHE		 8212 /*
8213 * We're finally done with prerequisite checking, and can start with
8214 * the nested entry.
8215 */
8216
cd232ad0
NHE		 8217 vmcs02 = nested_get_current_vmcs02(vmx);
8218 if (!vmcs02)
8219 return -ENOMEM;
8220
8221 enter_guest_mode(vcpu);
8222
8223 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8224
8225 cpu = get_cpu();
8226 vmx->loaded_vmcs = vmcs02;
8227 vmx_vcpu_put(vcpu);
8228 vmx_vcpu_load(vcpu, cpu);
8229 vcpu->cpu = cpu;
8230 put_cpu();
8231
36c3cc42
JK		 8232 vmx_segment_cache_clear(vmx);
8233
cd232ad0
NHE		 8234 vmcs12->launch_state = 1;
8235
8236 prepare_vmcs02(vcpu, vmcs12);
8237
6dfacadd
JK		 8238 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8239 return kvm_emulate_halt(vcpu);
8240
7af40ad3
JK		 8241 vmx->nested.nested_run_pending = 1;
8242
cd232ad0
NHE		 8243 /*
8244 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8245 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8246 * returned as far as L1 is concerned. It will only return (and set
8247 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8248 */
8249 return 1;
8250}
8251
4704d0be
NHE		 8252/*
8253 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8254 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8255 * This function returns the new value we should put in vmcs12.guest_cr0.
8256 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8257 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8258 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8259 * didn't trap the bit, because if L1 did, so would L0).
8260 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8261 * been modified by L2, and L1 knows it. So just leave the old value of
8262 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8263 * isn't relevant, because if L0 traps this bit it can set it to anything.
8264 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8265 * changed these bits, and therefore they need to be updated, but L0
8266 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8267 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8268 */
8269static inline unsigned long
8270vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8271{
8272 return
8273 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8274 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8275 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8276 vcpu->arch.cr0_guest_owned_bits));
8277}
8278
8279static inline unsigned long
8280vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8281{
8282 return
8283 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8284 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8285 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8286 vcpu->arch.cr4_guest_owned_bits));
8287}
8288
5f3d5799
JK		 8289static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8290 struct vmcs12 *vmcs12)
8291{
8292 u32 idt_vectoring;
8293 unsigned int nr;
8294
851eb667 8295 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8296 nr = vcpu->arch.exception.nr;
8297 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8298
8299 if (kvm_exception_is_soft(nr)) {
8300 vmcs12->vm_exit_instruction_len =
8301 vcpu->arch.event_exit_inst_len;
8302 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8303 } else
8304 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8305
8306 if (vcpu->arch.exception.has_error_code) {
8307 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8308 vmcs12->idt_vectoring_error_code =
8309 vcpu->arch.exception.error_code;
8310 }
8311
8312 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8313 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8314 vmcs12->idt_vectoring_info_field =
8315 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8316 } else if (vcpu->arch.interrupt.pending) {
8317 nr = vcpu->arch.interrupt.nr;
8318 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8319
8320 if (vcpu->arch.interrupt.soft) {
8321 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8322 vmcs12->vm_entry_instruction_len =
8323 vcpu->arch.event_exit_inst_len;
8324 } else
8325 idt_vectoring |= INTR_TYPE_EXT_INTR;
8326
8327 vmcs12->idt_vectoring_info_field = idt_vectoring;
8328 }
8329}
8330
b6b8a145
JK		 8331static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8332{
8333 struct vcpu_vmx *vmx = to_vmx(vcpu);
8334
f4124500
JK		 8335 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8336 vmx->nested.preemption_timer_expired) {
8337 if (vmx->nested.nested_run_pending)
8338 return -EBUSY;
8339 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8340 return 0;
8341 }
8342
b6b8a145 8343 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8344 if (vmx->nested.nested_run_pending ||
8345 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8346 return -EBUSY;
8347 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8348 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8349 INTR_INFO_VALID_MASK, 0);
8350 /*
8351 * The NMI-triggered VM exit counts as injection:
8352 * clear this one and block further NMIs.
8353 */
8354 vcpu->arch.nmi_pending = 0;
8355 vmx_set_nmi_mask(vcpu, true);
8356 return 0;
8357 }
8358
8359 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8360 nested_exit_on_intr(vcpu)) {
8361 if (vmx->nested.nested_run_pending)
8362 return -EBUSY;
8363 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8364 }
8365
8366 return 0;
8367}
8368
f4124500
JK		 8369static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8370{
8371 ktime_t remaining =
8372 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8373 u64 value;
8374
8375 if (ktime_to_ns(remaining) <= 0)
8376 return 0;
8377
8378 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8379 do_div(value, 1000000);
8380 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8381}
8382
4704d0be
NHE		 8383/*
8384 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8385 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8386 * and this function updates it to reflect the changes to the guest state while
8387 * L2 was running (and perhaps made some exits which were handled directly by L0
8388 * without going back to L1), and to reflect the exit reason.
8389 * Note that we do not have to copy here all VMCS fields, just those that
8390 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8391 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8392 * which already writes to vmcs12 directly.
8393 */
533558bc
JK		 8394static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8395 u32 exit_reason, u32 exit_intr_info,
8396 unsigned long exit_qualification)
4704d0be
NHE		 8397{
8398 /* update guest state fields: */
8399 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8400 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8401
8402 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8403 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8404 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8405 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8406
8407 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8408 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8409 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8410 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8411 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8412 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8413 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8414 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8415 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8416 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8417 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8418 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8419 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8420 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8421 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8422 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8423 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8424 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8425 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8426 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8427 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8428 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8429 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8430 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8431 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8432 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8433 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8434 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8435 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8436 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8437 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8438 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8439 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8440 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8441 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8442 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8443
4704d0be
NHE		 8444 vmcs12->guest_interruptibility_info =
8445 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8446 vmcs12->guest_pending_dbg_exceptions =
8447 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8448 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8449 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8450 else
8451 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8452
f4124500
JK		 8453 if (nested_cpu_has_preemption_timer(vmcs12)) {
8454 if (vmcs12->vm_exit_controls &
8455 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8456 vmcs12->vmx_preemption_timer_value =
8457 vmx_get_preemption_timer_value(vcpu);
8458 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8459 }
7854cbca 8460
3633cfc3
NHE		 8461 /*
8462 * In some cases (usually, nested EPT), L2 is allowed to change its
8463 * own CR3 without exiting. If it has changed it, we must keep it.
8464 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8465 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8466 *
8467 * Additionally, restore L2's PDPTR to vmcs12.
8468 */
8469 if (enable_ept) {
8470 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8471 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8472 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8473 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8474 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8475 }
8476
c18911a2
JK		 8477 vmcs12->vm_entry_controls =
8478 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8479 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8480
4704d0be
NHE		 8481 /* TODO: These cannot have changed unless we have MSR bitmaps and
8482 * the relevant bit asks not to trap the change */
8483 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8484 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8485 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8486 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8487 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8488 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8489 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8490 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8491 if (vmx_mpx_supported())
8492 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8493
8494 /* update exit information fields: */
8495
533558bc
JK		 8496 vmcs12->vm_exit_reason = exit_reason;
8497 vmcs12->exit_qualification = exit_qualification;
4704d0be 8498
533558bc 8499 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8500 if ((vmcs12->vm_exit_intr_info &
8501 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8502 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8503 vmcs12->vm_exit_intr_error_code =
8504 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8505 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8506 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8507 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8508
5f3d5799
JK		 8509 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8510 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8511 * instead of reading the real value. */
4704d0be 8512 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8513
8514 /*
8515 * Transfer the event that L0 or L1 may wanted to inject into
8516 * L2 to IDT_VECTORING_INFO_FIELD.
8517 */
8518 vmcs12_save_pending_event(vcpu, vmcs12);
8519 }
8520
8521 /*
8522 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8523 * preserved above and would only end up incorrectly in L1.
8524 */
8525 vcpu->arch.nmi_injected = false;
8526 kvm_clear_exception_queue(vcpu);
8527 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8528}
8529
8530/*
8531 * A part of what we need to when the nested L2 guest exits and we want to
8532 * run its L1 parent, is to reset L1's guest state to the host state specified
8533 * in vmcs12.
8534 * This function is to be called not only on normal nested exit, but also on
8535 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8536 * Failures During or After Loading Guest State").
8537 * This function should be called when the active VMCS is L1's (vmcs01).
8538 */
733568f9
JK		 8539static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8540 struct vmcs12 *vmcs12)
4704d0be 8541{
21feb4eb
ACL		 8542 struct kvm_segment seg;
8543
4704d0be
NHE		 8544 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8545 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8546 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8547 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8548 else
8549 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8550 vmx_set_efer(vcpu, vcpu->arch.efer);
8551
8552 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8553 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8554 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8555 /*
8556 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8557 * actually changed, because it depends on the current state of
8558 * fpu_active (which may have changed).
8559 * Note that vmx_set_cr0 refers to efer set above.
8560 */
9e3e4dbf 8561 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8562 /*
8563 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8564 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8565 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8566 */
8567 update_exception_bitmap(vcpu);
8568 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8569 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8570
8571 /*
8572 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8573 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8574 */
8575 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8576 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8577
29bf08f1 8578 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8579
4704d0be
NHE		 8580 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8581 kvm_mmu_reset_context(vcpu);
8582
feaf0c7d
GN		 8583 if (!enable_ept)
8584 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8585
4704d0be
NHE		 8586 if (enable_vpid) {
8587 /*
8588 * Trivially support vpid by letting L2s share their parent
8589 * L1's vpid. TODO: move to a more elaborate solution, giving
8590 * each L2 its own vpid and exposing the vpid feature to L1.
8591 */
8592 vmx_flush_tlb(vcpu);
8593 }
8594
8595
8596 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8597 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8598 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8599 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8600 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8601
36be0b9d
PB		 8602 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8603 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8604 vmcs_write64(GUEST_BNDCFGS, 0);
8605
44811c02 8606 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8607 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8608 vcpu->arch.pat = vmcs12->host_ia32_pat;
8609 }
4704d0be
NHE		 8610 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8611 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8612 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8613
21feb4eb
ACL		 8614 /* Set L1 segment info according to Intel SDM
8615 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8616 seg = (struct kvm_segment) {
8617 .base = 0,
8618 .limit = 0xFFFFFFFF,
8619 .selector = vmcs12->host_cs_selector,
8620 .type = 11,
8621 .present = 1,
8622 .s = 1,
8623 .g = 1
8624 };
8625 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8626 seg.l = 1;
8627 else
8628 seg.db = 1;
8629 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8630 seg = (struct kvm_segment) {
8631 .base = 0,
8632 .limit = 0xFFFFFFFF,
8633 .type = 3,
8634 .present = 1,
8635 .s = 1,
8636 .db = 1,
8637 .g = 1
8638 };
8639 seg.selector = vmcs12->host_ds_selector;
8640 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8641 seg.selector = vmcs12->host_es_selector;
8642 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8643 seg.selector = vmcs12->host_ss_selector;
8644 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8645 seg.selector = vmcs12->host_fs_selector;
8646 seg.base = vmcs12->host_fs_base;
8647 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8648 seg.selector = vmcs12->host_gs_selector;
8649 seg.base = vmcs12->host_gs_base;
8650 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8651 seg = (struct kvm_segment) {
205befd9 8652 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8653 .limit = 0x67,
8654 .selector = vmcs12->host_tr_selector,
8655 .type = 11,
8656 .present = 1
8657 };
8658 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8659
503cd0c5
JK		 8660 kvm_set_dr(vcpu, 7, 0x400);
8661 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8662}
8663
8664/*
8665 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8666 * and modify vmcs12 to make it see what it would expect to see there if
8667 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8668 */
533558bc
JK		 8669static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8670 u32 exit_intr_info,
8671 unsigned long exit_qualification)
4704d0be
NHE		 8672{
8673 struct vcpu_vmx *vmx = to_vmx(vcpu);
8674 int cpu;
8675 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8676
5f3d5799
JK		 8677 /* trying to cancel vmlaunch/vmresume is a bug */
8678 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8679
4704d0be 8680 leave_guest_mode(vcpu);
533558bc
JK		 8681 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8682 exit_qualification);
4704d0be 8683
77b0f5d6
BD		 8684 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8685 && nested_exit_intr_ack_set(vcpu)) {
8686 int irq = kvm_cpu_get_interrupt(vcpu);
8687 WARN_ON(irq < 0);
8688 vmcs12->vm_exit_intr_info = irq |
8689 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8690 }
8691
542060ea
JK		 8692 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8693 vmcs12->exit_qualification,
8694 vmcs12->idt_vectoring_info_field,
8695 vmcs12->vm_exit_intr_info,
8696 vmcs12->vm_exit_intr_error_code,
8697 KVM_ISA_VMX);
4704d0be
NHE		 8698
8699 cpu = get_cpu();
8700 vmx->loaded_vmcs = &vmx->vmcs01;
8701 vmx_vcpu_put(vcpu);
8702 vmx_vcpu_load(vcpu, cpu);
8703 vcpu->cpu = cpu;
8704 put_cpu();
8705
2961e876
GN		 8706 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8707 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8708 vmx_segment_cache_clear(vmx);
8709
4704d0be
NHE		 8710 /* if no vmcs02 cache requested, remove the one we used */
8711 if (VMCS02_POOL_SIZE == 0)
8712 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8713
8714 load_vmcs12_host_state(vcpu, vmcs12);
8715
27fc51b2 8716 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8717 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8718
8719 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8720 vmx->host_rsp = 0;
8721
8722 /* Unpin physical memory we referred to in vmcs02 */
8723 if (vmx->nested.apic_access_page) {
8724 nested_release_page(vmx->nested.apic_access_page);
8725 vmx->nested.apic_access_page = 0;
8726 }
8727
8728 /*
8729 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8730 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8731 * success or failure flag accordingly.
8732 */
8733 if (unlikely(vmx->fail)) {
8734 vmx->fail = 0;
8735 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8736 } else
8737 nested_vmx_succeed(vcpu);
012f83cb
AG		 8738 if (enable_shadow_vmcs)
8739 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8740
8741 /* in case we halted in L2 */
8742 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8743}
8744
42124925
JK		 8745/*
8746 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8747 */
8748static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8749{
8750 if (is_guest_mode(vcpu))
533558bc 8751 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8752 free_nested(to_vmx(vcpu));
8753}
8754
7c177938
NHE		 8755/*
8756 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8757 * 23.7 "VM-entry failures during or after loading guest state" (this also
8758 * lists the acceptable exit-reason and exit-qualification parameters).
8759 * It should only be called before L2 actually succeeded to run, and when
8760 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8761 */
8762static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8763 struct vmcs12 *vmcs12,
8764 u32 reason, unsigned long qualification)
8765{
8766 load_vmcs12_host_state(vcpu, vmcs12);
8767 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8768 vmcs12->exit_qualification = qualification;
8769 nested_vmx_succeed(vcpu);
012f83cb
AG		 8770 if (enable_shadow_vmcs)
8771 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8772}
8773
8a76d7f2
JR		 8774static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8775 struct x86_instruction_info *info,
8776 enum x86_intercept_stage stage)
8777{
8778 return X86EMUL_CONTINUE;
8779}
8780
cbdd1bea 8781static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8782 .cpu_has_kvm_support = cpu_has_kvm_support,
8783 .disabled_by_bios = vmx_disabled_by_bios,
8784 .hardware_setup = hardware_setup,
8785 .hardware_unsetup = hardware_unsetup,
002c7f7c 8786 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8787 .hardware_enable = hardware_enable,
8788 .hardware_disable = hardware_disable,
04547156 8789 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8790
8791 .vcpu_create = vmx_create_vcpu,
8792 .vcpu_free = vmx_free_vcpu,
04d2cc77 8793 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8794
04d2cc77 8795 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8796 .vcpu_load = vmx_vcpu_load,
8797 .vcpu_put = vmx_vcpu_put,
8798
c8639010 8799 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8800 .get_msr = vmx_get_msr,
8801 .set_msr = vmx_set_msr,
8802 .get_segment_base = vmx_get_segment_base,
8803 .get_segment = vmx_get_segment,
8804 .set_segment = vmx_set_segment,
2e4d2653 8805 .get_cpl = vmx_get_cpl,
6aa8b732 8806 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8807 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8808 .decache_cr3 = vmx_decache_cr3,
25c4c276 8809 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8810 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8811 .set_cr3 = vmx_set_cr3,
8812 .set_cr4 = vmx_set_cr4,
6aa8b732 8813 .set_efer = vmx_set_efer,
6aa8b732
AK		 8814 .get_idt = vmx_get_idt,
8815 .set_idt = vmx_set_idt,
8816 .get_gdt = vmx_get_gdt,
8817 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8818 .get_dr6 = vmx_get_dr6,
8819 .set_dr6 = vmx_set_dr6,
020df079 8820 .set_dr7 = vmx_set_dr7,
81908bf4 8821 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8822 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8823 .get_rflags = vmx_get_rflags,
8824 .set_rflags = vmx_set_rflags,
ebcbab4c 8825 .fpu_activate = vmx_fpu_activate,
02daab21 8826 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8827
8828 .tlb_flush = vmx_flush_tlb,
6aa8b732 8829
6aa8b732 8830 .run = vmx_vcpu_run,
6062d012 8831 .handle_exit = vmx_handle_exit,
6aa8b732 8832 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8833 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8834 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8835 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8836 .set_irq = vmx_inject_irq,
95ba8273 8837 .set_nmi = vmx_inject_nmi,
298101da 8838 .queue_exception = vmx_queue_exception,
b463a6f7 8839 .cancel_injection = vmx_cancel_injection,
78646121 8840 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8841 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8842 .get_nmi_mask = vmx_get_nmi_mask,
8843 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8844 .enable_nmi_window = enable_nmi_window,
8845 .enable_irq_window = enable_irq_window,
8846 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8847 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8848 .vm_has_apicv = vmx_vm_has_apicv,
8849 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8850 .hwapic_irr_update = vmx_hwapic_irr_update,
8851 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8852 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8853 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8854
cbc94022 8855 .set_tss_addr = vmx_set_tss_addr,
67253af5 8856 .get_tdp_level = get_ept_level,
4b12f0de 8857 .get_mt_mask = vmx_get_mt_mask,
229456fc 8858
586f9607 8859 .get_exit_info = vmx_get_exit_info,
586f9607 8860
17cc3935 8861 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8862
8863 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8864
8865 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8866 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8867
8868 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8869
8870 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8871
4051b188 8872 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8873 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8874 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8875 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8876 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8877 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8878
8879 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8880
8881 .check_intercept = vmx_check_intercept,
a547c6db 8882 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8883 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8884
8885 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8886};
8887
8888static int __init vmx_init(void)
8889{
8d14695f 8890 int r, i, msr;
26bb0981
AK		 8891
8892 rdmsrl_safe(MSR_EFER, &host_efer);
8893
8894 for (i = 0; i < NR_VMX_MSR; ++i)
8895 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8896
3e7c73e9 8897 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8898 if (!vmx_io_bitmap_a)
8899 return -ENOMEM;
8900
2106a548
GC		 8901 r = -ENOMEM;
8902
3e7c73e9 8903 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8904 if (!vmx_io_bitmap_b)
fdef3ad1 8905 goto out;
fdef3ad1 8906
5897297b 8907 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8908 if (!vmx_msr_bitmap_legacy)
25c5f225 8909 goto out1;
2106a548 8910
8d14695f
YZ		 8911 vmx_msr_bitmap_legacy_x2apic =
8912 (unsigned long *)__get_free_page(GFP_KERNEL);
8913 if (!vmx_msr_bitmap_legacy_x2apic)
8914 goto out2;
25c5f225 8915
5897297b 8916 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8917 if (!vmx_msr_bitmap_longmode)
8d14695f 8918 goto out3;
2106a548 8919
8d14695f
YZ		 8920 vmx_msr_bitmap_longmode_x2apic =
8921 (unsigned long *)__get_free_page(GFP_KERNEL);
8922 if (!vmx_msr_bitmap_longmode_x2apic)
8923 goto out4;
4607c2d7
AG		 8924 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8925 if (!vmx_vmread_bitmap)
8926 goto out5;
8927
8928 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8929 if (!vmx_vmwrite_bitmap)
8930 goto out6;
8931
8932 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8933 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 8934
fdef3ad1
HQ		 8935 /*
8936 * Allow direct access to the PC debug port (it is often used for I/O
8937 * delays, but the vmexits simply slow things down).
8938 */
3e7c73e9
AK		 8939 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8940 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8941
3e7c73e9 8942 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8943
5897297b
AK		 8944 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8945 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8946
2384d2b3
SY		 8947 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8948
0ee75bea
AK		 8949 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8950 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8951 if (r)
4607c2d7 8952 goto out7;
25c5f225 8953
8f536b76
ZY		 8954#ifdef CONFIG_KEXEC
8955 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8956 crash_vmclear_local_loaded_vmcss);
8957#endif
8958
5897297b
AK		 8959 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8960 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8961 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8962 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8963 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8964 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8965 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8966
8d14695f
YZ		 8967 memcpy(vmx_msr_bitmap_legacy_x2apic,
8968 vmx_msr_bitmap_legacy, PAGE_SIZE);
8969 memcpy(vmx_msr_bitmap_longmode_x2apic,
8970 vmx_msr_bitmap_longmode, PAGE_SIZE);
8971
01e439be 8972 if (enable_apicv) {
8d14695f
YZ		 8973 for (msr = 0x800; msr <= 0x8ff; msr++)
8974 vmx_disable_intercept_msr_read_x2apic(msr);
8975
8976 /* According SDM, in x2apic mode, the whole id reg is used.
8977 * But in KVM, it only use the highest eight bits. Need to
8978 * intercept it */
8979 vmx_enable_intercept_msr_read_x2apic(0x802);
8980 /* TMCCT */
8981 vmx_enable_intercept_msr_read_x2apic(0x839);
8982 /* TPR */
8983 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8984 /* EOI */
8985 vmx_disable_intercept_msr_write_x2apic(0x80b);
8986 /* SELF-IPI */
8987 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8988 }
fdef3ad1 8989
089d034e 8990 if (enable_ept) {
3f6d8c8a
XH		 8991 kvm_mmu_set_mask_ptes(0ull,
8992 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8993 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8994 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8995 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8996 kvm_enable_tdp();
8997 } else
8998 kvm_disable_tdp();
1439442c 8999
fdef3ad1
HQ		 9000 return 0;
9001
4607c2d7
AG		 9002out7:
9003 free_page((unsigned long)vmx_vmwrite_bitmap);
9004out6:
9005 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9006out5:
9007 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9008out4:
5897297b 9009 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9010out3:
9011 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9012out2:
5897297b 9013 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9014out1:
3e7c73e9 9015 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9016out:
3e7c73e9 9017 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9018 return r;
6aa8b732
AK		 9019}
9020
9021static void __exit vmx_exit(void)
9022{
8d14695f
YZ		 9023 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9024 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9025 free_page((unsigned long)vmx_msr_bitmap_legacy);
9026 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9027 free_page((unsigned long)vmx_io_bitmap_b);
9028 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9029 free_page((unsigned long)vmx_vmwrite_bitmap);
9030 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9031
8f536b76
ZY		 9032#ifdef CONFIG_KEXEC
9033 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
9034 synchronize_rcu();
9035#endif
9036
cb498ea2 9037 kvm_exit();
6aa8b732
AK		 9038}
9039
9040module_init(vmx_init)
9041module_exit(vmx_exit)
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