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KVM: x86: introduce kvm_supported_xcr0()
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
209 u64 host_ia32_pat;
210 u64 host_ia32_efer;
211 u64 host_ia32_perf_global_ctrl;
212 u64 padding64[8]; /* room for future expansion */
213 /*
214 * To allow migration of L1 (complete with its L2 guests) between
215 * machines of different natural widths (32 or 64 bit), we cannot have
216 * unsigned long fields with no explict size. We use u64 (aliased
217 * natural_width) instead. Luckily, x86 is little-endian.
218 */
219 natural_width cr0_guest_host_mask;
220 natural_width cr4_guest_host_mask;
221 natural_width cr0_read_shadow;
222 natural_width cr4_read_shadow;
223 natural_width cr3_target_value0;
224 natural_width cr3_target_value1;
225 natural_width cr3_target_value2;
226 natural_width cr3_target_value3;
227 natural_width exit_qualification;
228 natural_width guest_linear_address;
229 natural_width guest_cr0;
230 natural_width guest_cr3;
231 natural_width guest_cr4;
232 natural_width guest_es_base;
233 natural_width guest_cs_base;
234 natural_width guest_ss_base;
235 natural_width guest_ds_base;
236 natural_width guest_fs_base;
237 natural_width guest_gs_base;
238 natural_width guest_ldtr_base;
239 natural_width guest_tr_base;
240 natural_width guest_gdtr_base;
241 natural_width guest_idtr_base;
242 natural_width guest_dr7;
243 natural_width guest_rsp;
244 natural_width guest_rip;
245 natural_width guest_rflags;
246 natural_width guest_pending_dbg_exceptions;
247 natural_width guest_sysenter_esp;
248 natural_width guest_sysenter_eip;
249 natural_width host_cr0;
250 natural_width host_cr3;
251 natural_width host_cr4;
252 natural_width host_fs_base;
253 natural_width host_gs_base;
254 natural_width host_tr_base;
255 natural_width host_gdtr_base;
256 natural_width host_idtr_base;
257 natural_width host_ia32_sysenter_esp;
258 natural_width host_ia32_sysenter_eip;
259 natural_width host_rsp;
260 natural_width host_rip;
261 natural_width paddingl[8]; /* room for future expansion */
262 u32 pin_based_vm_exec_control;
263 u32 cpu_based_vm_exec_control;
264 u32 exception_bitmap;
265 u32 page_fault_error_code_mask;
266 u32 page_fault_error_code_match;
267 u32 cr3_target_count;
268 u32 vm_exit_controls;
269 u32 vm_exit_msr_store_count;
270 u32 vm_exit_msr_load_count;
271 u32 vm_entry_controls;
272 u32 vm_entry_msr_load_count;
273 u32 vm_entry_intr_info_field;
274 u32 vm_entry_exception_error_code;
275 u32 vm_entry_instruction_len;
276 u32 tpr_threshold;
277 u32 secondary_vm_exec_control;
278 u32 vm_instruction_error;
279 u32 vm_exit_reason;
280 u32 vm_exit_intr_info;
281 u32 vm_exit_intr_error_code;
282 u32 idt_vectoring_info_field;
283 u32 idt_vectoring_error_code;
284 u32 vm_exit_instruction_len;
285 u32 vmx_instruction_info;
286 u32 guest_es_limit;
287 u32 guest_cs_limit;
288 u32 guest_ss_limit;
289 u32 guest_ds_limit;
290 u32 guest_fs_limit;
291 u32 guest_gs_limit;
292 u32 guest_ldtr_limit;
293 u32 guest_tr_limit;
294 u32 guest_gdtr_limit;
295 u32 guest_idtr_limit;
296 u32 guest_es_ar_bytes;
297 u32 guest_cs_ar_bytes;
298 u32 guest_ss_ar_bytes;
299 u32 guest_ds_ar_bytes;
300 u32 guest_fs_ar_bytes;
301 u32 guest_gs_ar_bytes;
302 u32 guest_ldtr_ar_bytes;
303 u32 guest_tr_ar_bytes;
304 u32 guest_interruptibility_info;
305 u32 guest_activity_state;
306 u32 guest_sysenter_cs;
307 u32 host_ia32_sysenter_cs;
0238ea91
JK		 308 u32 vmx_preemption_timer_value;
309 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 310 u16 virtual_processor_id;
311 u16 guest_es_selector;
312 u16 guest_cs_selector;
313 u16 guest_ss_selector;
314 u16 guest_ds_selector;
315 u16 guest_fs_selector;
316 u16 guest_gs_selector;
317 u16 guest_ldtr_selector;
318 u16 guest_tr_selector;
319 u16 host_es_selector;
320 u16 host_cs_selector;
321 u16 host_ss_selector;
322 u16 host_ds_selector;
323 u16 host_fs_selector;
324 u16 host_gs_selector;
325 u16 host_tr_selector;
a9d30f33
NHE		 326};
327
328/*
329 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
330 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
331 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
332 */
333#define VMCS12_REVISION 0x11e57ed0
334
335/*
336 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
337 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
338 * current implementation, 4K are reserved to avoid future complications.
339 */
340#define VMCS12_SIZE 0x1000
341
ff2f6fe9
NHE		 342/* Used to remember the last vmcs02 used for some recently used vmcs12s */
343struct vmcs02_list {
344 struct list_head list;
345 gpa_t vmptr;
346 struct loaded_vmcs vmcs02;
347};
348
ec378aee
NHE		 349/*
350 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
351 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
352 */
353struct nested_vmx {
354 /* Has the level1 guest done vmxon? */
355 bool vmxon;
a9d30f33
NHE		 356
357 /* The guest-physical address of the current VMCS L1 keeps for L2 */
358 gpa_t current_vmptr;
359 /* The host-usable pointer to the above */
360 struct page *current_vmcs12_page;
361 struct vmcs12 *current_vmcs12;
8de48833 362 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 363 /*
364 * Indicates if the shadow vmcs must be updated with the
365 * data hold by vmcs12
366 */
367 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 368
369 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
370 struct list_head vmcs02_pool;
371 int vmcs02_num;
fe3ef05c 372 u64 vmcs01_tsc_offset;
644d711a
NHE		 373 /* L2 must run next, and mustn't decide to exit to L1. */
374 bool nested_run_pending;
fe3ef05c
NHE		 375 /*
376 * Guest pages referred to in vmcs02 with host-physical pointers, so
377 * we must keep them pinned while L2 runs.
378 */
379 struct page *apic_access_page;
b3897a49 380 u64 msr_ia32_feature_control;
f4124500
JK		 381
382 struct hrtimer preemption_timer;
383 bool preemption_timer_expired;
ec378aee
NHE		 384};
385
01e439be
YZ		 386#define POSTED_INTR_ON 0
387/* Posted-Interrupt Descriptor */
388struct pi_desc {
389 u32 pir[8]; /* Posted interrupt requested */
390 u32 control; /* bit 0 of control is outstanding notification bit */
391 u32 rsvd[7];
392} __aligned(64);
393
a20ed54d
YZ		 394static bool pi_test_and_set_on(struct pi_desc *pi_desc)
395{
396 return test_and_set_bit(POSTED_INTR_ON,
397 (unsigned long *)&pi_desc->control);
398}
399
400static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
401{
402 return test_and_clear_bit(POSTED_INTR_ON,
403 (unsigned long *)&pi_desc->control);
404}
405
406static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
407{
408 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
409}
410
a2fa3e9f 411struct vcpu_vmx {
fb3f0f51 412 struct kvm_vcpu vcpu;
313dbd49 413 unsigned long host_rsp;
29bd8a78 414 u8 fail;
69c73028 415 u8 cpl;
9d58b931 416 bool nmi_known_unmasked;
51aa01d1 417 u32 exit_intr_info;
1155f76a 418 u32 idt_vectoring_info;
6de12732 419 ulong rflags;
26bb0981 420 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 421 int nmsrs;
422 int save_nmsrs;
a547c6db 423 unsigned long host_idt_base;
a2fa3e9f 424#ifdef CONFIG_X86_64
44ea2b17
AK		 425 u64 msr_host_kernel_gs_base;
426 u64 msr_guest_kernel_gs_base;
a2fa3e9f 427#endif
2961e876
GN		 428 u32 vm_entry_controls_shadow;
429 u32 vm_exit_controls_shadow;
d462b819
NHE		 430 /*
431 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
432 * non-nested (L1) guest, it always points to vmcs01. For a nested
433 * guest (L2), it points to a different VMCS.
434 */
435 struct loaded_vmcs vmcs01;
436 struct loaded_vmcs *loaded_vmcs;
437 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 438 struct msr_autoload {
439 unsigned nr;
440 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
441 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
442 } msr_autoload;
a2fa3e9f
GH		 443 struct {
444 int loaded;
445 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 446#ifdef CONFIG_X86_64
447 u16 ds_sel, es_sel;
448#endif
152d3f2f
LV		 449 int gs_ldt_reload_needed;
450 int fs_reload_needed;
da8999d3 451 u64 msr_host_bndcfgs;
d77c26fc 452 } host_state;
9c8cba37 453 struct {
7ffd92c5 454 int vm86_active;
78ac8b47 455 ulong save_rflags;
f5f7b2fe
AK		 456 struct kvm_segment segs[8];
457 } rmode;
458 struct {
459 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 460 struct kvm_save_segment {
461 u16 selector;
462 unsigned long base;
463 u32 limit;
464 u32 ar;
f5f7b2fe 465 } seg[8];
2fb92db1 466 } segment_cache;
2384d2b3 467 int vpid;
04fa4d32 468 bool emulation_required;
3b86cd99
JK		 469
470 /* Support for vnmi-less CPUs */
471 int soft_vnmi_blocked;
472 ktime_t entry_time;
473 s64 vnmi_blocked_time;
a0861c02 474 u32 exit_reason;
4e47c7a6
SY		 475
476 bool rdtscp_enabled;
ec378aee 477
01e439be
YZ		 478 /* Posted interrupt descriptor */
479 struct pi_desc pi_desc;
480
ec378aee
NHE		 481 /* Support for a guest hypervisor (nested VMX) */
482 struct nested_vmx nested;
a2fa3e9f
GH		 483};
484
2fb92db1
AK		 485enum segment_cache_field {
486 SEG_FIELD_SEL = 0,
487 SEG_FIELD_BASE = 1,
488 SEG_FIELD_LIMIT = 2,
489 SEG_FIELD_AR = 3,
490
491 SEG_FIELD_NR = 4
492};
493
a2fa3e9f
GH		 494static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
495{
fb3f0f51 496 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 497}
498
22bd0358
NHE		 499#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
500#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
501#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
502 [number##_HIGH] = VMCS12_OFFSET(name)+4
503
4607c2d7
AG		 504
505static const unsigned long shadow_read_only_fields[] = {
506 /*
507 * We do NOT shadow fields that are modified when L0
508 * traps and emulates any vmx instruction (e.g. VMPTRLD,
509 * VMXON...) executed by L1.
510 * For example, VM_INSTRUCTION_ERROR is read
511 * by L1 if a vmx instruction fails (part of the error path).
512 * Note the code assumes this logic. If for some reason
513 * we start shadowing these fields then we need to
514 * force a shadow sync when L0 emulates vmx instructions
515 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
516 * by nested_vmx_failValid)
517 */
518 VM_EXIT_REASON,
519 VM_EXIT_INTR_INFO,
520 VM_EXIT_INSTRUCTION_LEN,
521 IDT_VECTORING_INFO_FIELD,
522 IDT_VECTORING_ERROR_CODE,
523 VM_EXIT_INTR_ERROR_CODE,
524 EXIT_QUALIFICATION,
525 GUEST_LINEAR_ADDRESS,
526 GUEST_PHYSICAL_ADDRESS
527};
528static const int max_shadow_read_only_fields =
529 ARRAY_SIZE(shadow_read_only_fields);
530
531static const unsigned long shadow_read_write_fields[] = {
532 GUEST_RIP,
533 GUEST_RSP,
534 GUEST_CR0,
535 GUEST_CR3,
536 GUEST_CR4,
537 GUEST_INTERRUPTIBILITY_INFO,
538 GUEST_RFLAGS,
539 GUEST_CS_SELECTOR,
540 GUEST_CS_AR_BYTES,
541 GUEST_CS_LIMIT,
542 GUEST_CS_BASE,
543 GUEST_ES_BASE,
544 CR0_GUEST_HOST_MASK,
545 CR0_READ_SHADOW,
546 CR4_READ_SHADOW,
547 TSC_OFFSET,
548 EXCEPTION_BITMAP,
549 CPU_BASED_VM_EXEC_CONTROL,
550 VM_ENTRY_EXCEPTION_ERROR_CODE,
551 VM_ENTRY_INTR_INFO_FIELD,
552 VM_ENTRY_INSTRUCTION_LEN,
553 VM_ENTRY_EXCEPTION_ERROR_CODE,
554 HOST_FS_BASE,
555 HOST_GS_BASE,
556 HOST_FS_SELECTOR,
557 HOST_GS_SELECTOR
558};
559static const int max_shadow_read_write_fields =
560 ARRAY_SIZE(shadow_read_write_fields);
561
772e0318 562static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 563 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
564 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
565 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
566 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
567 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
568 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
569 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
570 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
571 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
572 FIELD(HOST_ES_SELECTOR, host_es_selector),
573 FIELD(HOST_CS_SELECTOR, host_cs_selector),
574 FIELD(HOST_SS_SELECTOR, host_ss_selector),
575 FIELD(HOST_DS_SELECTOR, host_ds_selector),
576 FIELD(HOST_FS_SELECTOR, host_fs_selector),
577 FIELD(HOST_GS_SELECTOR, host_gs_selector),
578 FIELD(HOST_TR_SELECTOR, host_tr_selector),
579 FIELD64(IO_BITMAP_A, io_bitmap_a),
580 FIELD64(IO_BITMAP_B, io_bitmap_b),
581 FIELD64(MSR_BITMAP, msr_bitmap),
582 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
583 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
584 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
585 FIELD64(TSC_OFFSET, tsc_offset),
586 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
587 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
588 FIELD64(EPT_POINTER, ept_pointer),
589 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
590 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
591 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
592 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
593 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
594 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
595 FIELD64(GUEST_PDPTR0, guest_pdptr0),
596 FIELD64(GUEST_PDPTR1, guest_pdptr1),
597 FIELD64(GUEST_PDPTR2, guest_pdptr2),
598 FIELD64(GUEST_PDPTR3, guest_pdptr3),
599 FIELD64(HOST_IA32_PAT, host_ia32_pat),
600 FIELD64(HOST_IA32_EFER, host_ia32_efer),
601 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
602 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
603 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
604 FIELD(EXCEPTION_BITMAP, exception_bitmap),
605 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
606 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
607 FIELD(CR3_TARGET_COUNT, cr3_target_count),
608 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
609 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
610 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
611 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
612 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
613 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
614 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
615 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
616 FIELD(TPR_THRESHOLD, tpr_threshold),
617 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
618 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
619 FIELD(VM_EXIT_REASON, vm_exit_reason),
620 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
621 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
622 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
623 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
624 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
625 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
626 FIELD(GUEST_ES_LIMIT, guest_es_limit),
627 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
628 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
629 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
630 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
631 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
632 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
633 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
634 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
635 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
636 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
637 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
638 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
639 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
640 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
641 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
642 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
643 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
644 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
645 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
646 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
647 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 648 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 649 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
650 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
651 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
652 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
653 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
654 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
655 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
656 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
657 FIELD(EXIT_QUALIFICATION, exit_qualification),
658 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
659 FIELD(GUEST_CR0, guest_cr0),
660 FIELD(GUEST_CR3, guest_cr3),
661 FIELD(GUEST_CR4, guest_cr4),
662 FIELD(GUEST_ES_BASE, guest_es_base),
663 FIELD(GUEST_CS_BASE, guest_cs_base),
664 FIELD(GUEST_SS_BASE, guest_ss_base),
665 FIELD(GUEST_DS_BASE, guest_ds_base),
666 FIELD(GUEST_FS_BASE, guest_fs_base),
667 FIELD(GUEST_GS_BASE, guest_gs_base),
668 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
669 FIELD(GUEST_TR_BASE, guest_tr_base),
670 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
671 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
672 FIELD(GUEST_DR7, guest_dr7),
673 FIELD(GUEST_RSP, guest_rsp),
674 FIELD(GUEST_RIP, guest_rip),
675 FIELD(GUEST_RFLAGS, guest_rflags),
676 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
677 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
678 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
679 FIELD(HOST_CR0, host_cr0),
680 FIELD(HOST_CR3, host_cr3),
681 FIELD(HOST_CR4, host_cr4),
682 FIELD(HOST_FS_BASE, host_fs_base),
683 FIELD(HOST_GS_BASE, host_gs_base),
684 FIELD(HOST_TR_BASE, host_tr_base),
685 FIELD(HOST_GDTR_BASE, host_gdtr_base),
686 FIELD(HOST_IDTR_BASE, host_idtr_base),
687 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
688 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
689 FIELD(HOST_RSP, host_rsp),
690 FIELD(HOST_RIP, host_rip),
691};
692static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
693
694static inline short vmcs_field_to_offset(unsigned long field)
695{
696 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
697 return -1;
698 return vmcs_field_to_offset_table[field];
699}
700
a9d30f33
NHE		 701static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
702{
703 return to_vmx(vcpu)->nested.current_vmcs12;
704}
705
706static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
707{
708 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 709 if (is_error_page(page))
a9d30f33 710 return NULL;
32cad84f 711
a9d30f33
NHE		 712 return page;
713}
714
715static void nested_release_page(struct page *page)
716{
717 kvm_release_page_dirty(page);
718}
719
720static void nested_release_page_clean(struct page *page)
721{
722 kvm_release_page_clean(page);
723}
724
bfd0a56b 725static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 726static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 727static void kvm_cpu_vmxon(u64 addr);
728static void kvm_cpu_vmxoff(void);
776e58ea 729static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 730static void vmx_set_segment(struct kvm_vcpu *vcpu,
731 struct kvm_segment *var, int seg);
732static void vmx_get_segment(struct kvm_vcpu *vcpu,
733 struct kvm_segment *var, int seg);
d99e4152
GN		 734static bool guest_state_valid(struct kvm_vcpu *vcpu);
735static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 736static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 737static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 738static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 739
6aa8b732
AK		 740static DEFINE_PER_CPU(struct vmcs *, vmxarea);
741static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 742/*
743 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
744 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
745 */
746static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 747static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 748
3e7c73e9
AK		 749static unsigned long *vmx_io_bitmap_a;
750static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 751static unsigned long *vmx_msr_bitmap_legacy;
752static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 753static unsigned long *vmx_msr_bitmap_legacy_x2apic;
754static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 755static unsigned long *vmx_vmread_bitmap;
756static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 757
110312c8 758static bool cpu_has_load_ia32_efer;
8bf00a52 759static bool cpu_has_load_perf_global_ctrl;
110312c8 760
2384d2b3
SY		 761static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
762static DEFINE_SPINLOCK(vmx_vpid_lock);
763
1c3d14fe 764static struct vmcs_config {
6aa8b732
AK		 765 int size;
766 int order;
767 u32 revision_id;
1c3d14fe
YS		 768 u32 pin_based_exec_ctrl;
769 u32 cpu_based_exec_ctrl;
f78e0e2e 770 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 771 u32 vmexit_ctrl;
772 u32 vmentry_ctrl;
773} vmcs_config;
6aa8b732 774
efff9e53 775static struct vmx_capability {
d56f546d
SY		 776 u32 ept;
777 u32 vpid;
778} vmx_capability;
779
6aa8b732
AK		 780#define VMX_SEGMENT_FIELD(seg) \
781 [VCPU_SREG_##seg] = { \
782 .selector = GUEST_##seg##_SELECTOR, \
783 .base = GUEST_##seg##_BASE, \
784 .limit = GUEST_##seg##_LIMIT, \
785 .ar_bytes = GUEST_##seg##_AR_BYTES, \
786 }
787
772e0318 788static const struct kvm_vmx_segment_field {
6aa8b732
AK		 789 unsigned selector;
790 unsigned base;
791 unsigned limit;
792 unsigned ar_bytes;
793} kvm_vmx_segment_fields[] = {
794 VMX_SEGMENT_FIELD(CS),
795 VMX_SEGMENT_FIELD(DS),
796 VMX_SEGMENT_FIELD(ES),
797 VMX_SEGMENT_FIELD(FS),
798 VMX_SEGMENT_FIELD(GS),
799 VMX_SEGMENT_FIELD(SS),
800 VMX_SEGMENT_FIELD(TR),
801 VMX_SEGMENT_FIELD(LDTR),
802};
803
26bb0981
AK		 804static u64 host_efer;
805
6de4f3ad
AK		 806static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
807
4d56c8a7 808/*
8c06585d 809 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 810 * away by decrementing the array size.
811 */
6aa8b732 812static const u32 vmx_msr_index[] = {
05b3e0c2 813#ifdef CONFIG_X86_64
44ea2b17 814 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 815#endif
8c06585d 816 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 817};
9d8f549d 818#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 819
31299944 820static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 821{
822 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
823 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 824 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 825}
826
31299944 827static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 828{
829 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
830 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 831 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 832}
833
31299944 834static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 835{
836 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
837 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 838 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 839}
840
31299944 841static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 842{
843 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
844 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
845}
846
31299944 847static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 848{
849 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
850 INTR_INFO_VALID_MASK)) ==
851 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
852}
853
31299944 854static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 855{
04547156 856 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 857}
858
31299944 859static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 860{
04547156 861 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 862}
863
31299944 864static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 865{
04547156 866 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 867}
868
31299944 869static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 870{
04547156
SY		 871 return vmcs_config.cpu_based_exec_ctrl &
872 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 873}
874
774ead3a 875static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 876{
04547156
SY		 877 return vmcs_config.cpu_based_2nd_exec_ctrl &
878 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
879}
880
8d14695f
YZ		 881static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
882{
883 return vmcs_config.cpu_based_2nd_exec_ctrl &
884 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
885}
886
83d4c286
YZ		 887static inline bool cpu_has_vmx_apic_register_virt(void)
888{
889 return vmcs_config.cpu_based_2nd_exec_ctrl &
890 SECONDARY_EXEC_APIC_REGISTER_VIRT;
891}
892
c7c9c56c
YZ		 893static inline bool cpu_has_vmx_virtual_intr_delivery(void)
894{
895 return vmcs_config.cpu_based_2nd_exec_ctrl &
896 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
897}
898
01e439be
YZ		 899static inline bool cpu_has_vmx_posted_intr(void)
900{
901 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
902}
903
904static inline bool cpu_has_vmx_apicv(void)
905{
906 return cpu_has_vmx_apic_register_virt() &&
907 cpu_has_vmx_virtual_intr_delivery() &&
908 cpu_has_vmx_posted_intr();
909}
910
04547156
SY		 911static inline bool cpu_has_vmx_flexpriority(void)
912{
913 return cpu_has_vmx_tpr_shadow() &&
914 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 915}
916
e799794e
MT		 917static inline bool cpu_has_vmx_ept_execute_only(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_eptp_uncacheable(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 925}
926
927static inline bool cpu_has_vmx_eptp_writeback(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 930}
931
932static inline bool cpu_has_vmx_ept_2m_page(void)
933{
31299944 934 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 935}
936
878403b7
SY		 937static inline bool cpu_has_vmx_ept_1g_page(void)
938{
31299944 939 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 940}
941
4bc9b982
SY		 942static inline bool cpu_has_vmx_ept_4levels(void)
943{
944 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
945}
946
83c3a331
XH		 947static inline bool cpu_has_vmx_ept_ad_bits(void)
948{
949 return vmx_capability.ept & VMX_EPT_AD_BIT;
950}
951
31299944 952static inline bool cpu_has_vmx_invept_context(void)
d56f546d 953{
31299944 954 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 955}
956
31299944 957static inline bool cpu_has_vmx_invept_global(void)
d56f546d 958{
31299944 959 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 960}
961
518c8aee
GJ		 962static inline bool cpu_has_vmx_invvpid_single(void)
963{
964 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
965}
966
b9d762fa
GJ		 967static inline bool cpu_has_vmx_invvpid_global(void)
968{
969 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
970}
971
31299944 972static inline bool cpu_has_vmx_ept(void)
d56f546d 973{
04547156
SY		 974 return vmcs_config.cpu_based_2nd_exec_ctrl &
975 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 976}
977
31299944 978static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 979{
980 return vmcs_config.cpu_based_2nd_exec_ctrl &
981 SECONDARY_EXEC_UNRESTRICTED_GUEST;
982}
983
31299944 984static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 985{
986 return vmcs_config.cpu_based_2nd_exec_ctrl &
987 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
988}
989
31299944 990static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 991{
6d3e435e 992 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 993}
994
31299944 995static inline bool cpu_has_vmx_vpid(void)
2384d2b3 996{
04547156
SY		 997 return vmcs_config.cpu_based_2nd_exec_ctrl &
998 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 999}
1000
31299944 1001static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1002{
1003 return vmcs_config.cpu_based_2nd_exec_ctrl &
1004 SECONDARY_EXEC_RDTSCP;
1005}
1006
ad756a16
MJ		 1007static inline bool cpu_has_vmx_invpcid(void)
1008{
1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_ENABLE_INVPCID;
1011}
1012
31299944 1013static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1014{
1015 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1016}
1017
f5f48ee1
SY		 1018static inline bool cpu_has_vmx_wbinvd_exit(void)
1019{
1020 return vmcs_config.cpu_based_2nd_exec_ctrl &
1021 SECONDARY_EXEC_WBINVD_EXITING;
1022}
1023
abc4fc58
AG		 1024static inline bool cpu_has_vmx_shadow_vmcs(void)
1025{
1026 u64 vmx_msr;
1027 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1028 /* check if the cpu supports writing r/o exit information fields */
1029 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1030 return false;
1031
1032 return vmcs_config.cpu_based_2nd_exec_ctrl &
1033 SECONDARY_EXEC_SHADOW_VMCS;
1034}
1035
04547156
SY		 1036static inline bool report_flexpriority(void)
1037{
1038 return flexpriority_enabled;
1039}
1040
fe3ef05c
NHE		 1041static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1042{
1043 return vmcs12->cpu_based_vm_exec_control & bit;
1044}
1045
1046static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1047{
1048 return (vmcs12->cpu_based_vm_exec_control &
1049 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1050 (vmcs12->secondary_vm_exec_control & bit);
1051}
1052
f5c4368f 1053static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1054{
1055 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1056}
1057
f4124500
JK		 1058static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1059{
1060 return vmcs12->pin_based_vm_exec_control &
1061 PIN_BASED_VMX_PREEMPTION_TIMER;
1062}
1063
155a97a3
NHE		 1064static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1065{
1066 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1067}
1068
644d711a
NHE		 1069static inline bool is_exception(u32 intr_info)
1070{
1071 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1072 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1073}
1074
533558bc
JK		 1075static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1076 u32 exit_intr_info,
1077 unsigned long exit_qualification);
7c177938
NHE		 1078static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1079 struct vmcs12 *vmcs12,
1080 u32 reason, unsigned long qualification);
1081
8b9cf98c 1082static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1083{
1084 int i;
1085
a2fa3e9f 1086 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1087 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1088 return i;
1089 return -1;
1090}
1091
2384d2b3
SY		 1092static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1093{
1094 struct {
1095 u64 vpid : 16;
1096 u64 rsvd : 48;
1097 u64 gva;
1098 } operand = { vpid, 0, gva };
1099
4ecac3fd 1100 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1101 /* CF==1 or ZF==1 --> rc = -1 */
1102 "; ja 1f ; ud2 ; 1:"
1103 : : "a"(&operand), "c"(ext) : "cc", "memory");
1104}
1105
1439442c
SY		 1106static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1107{
1108 struct {
1109 u64 eptp, gpa;
1110 } operand = {eptp, gpa};
1111
4ecac3fd 1112 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1113 /* CF==1 or ZF==1 --> rc = -1 */
1114 "; ja 1f ; ud2 ; 1:\n"
1115 : : "a" (&operand), "c" (ext) : "cc", "memory");
1116}
1117
26bb0981 1118static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1119{
1120 int i;
1121
8b9cf98c 1122 i = __find_msr_index(vmx, msr);
a75beee6 1123 if (i >= 0)
a2fa3e9f 1124 return &vmx->guest_msrs[i];
8b6d44c7 1125 return NULL;
7725f0ba
AK		 1126}
1127
6aa8b732
AK		 1128static void vmcs_clear(struct vmcs *vmcs)
1129{
1130 u64 phys_addr = __pa(vmcs);
1131 u8 error;
1132
4ecac3fd 1133 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1134 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1135 : "cc", "memory");
1136 if (error)
1137 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1138 vmcs, phys_addr);
1139}
1140
d462b819
NHE		 1141static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1142{
1143 vmcs_clear(loaded_vmcs->vmcs);
1144 loaded_vmcs->cpu = -1;
1145 loaded_vmcs->launched = 0;
1146}
1147
7725b894
DX		 1148static void vmcs_load(struct vmcs *vmcs)
1149{
1150 u64 phys_addr = __pa(vmcs);
1151 u8 error;
1152
1153 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1154 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1155 : "cc", "memory");
1156 if (error)
2844d849 1157 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1158 vmcs, phys_addr);
1159}
1160
8f536b76
ZY		 1161#ifdef CONFIG_KEXEC
1162/*
1163 * This bitmap is used to indicate whether the vmclear
1164 * operation is enabled on all cpus. All disabled by
1165 * default.
1166 */
1167static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1168
1169static inline void crash_enable_local_vmclear(int cpu)
1170{
1171 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1172}
1173
1174static inline void crash_disable_local_vmclear(int cpu)
1175{
1176 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1177}
1178
1179static inline int crash_local_vmclear_enabled(int cpu)
1180{
1181 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1182}
1183
1184static void crash_vmclear_local_loaded_vmcss(void)
1185{
1186 int cpu = raw_smp_processor_id();
1187 struct loaded_vmcs *v;
1188
1189 if (!crash_local_vmclear_enabled(cpu))
1190 return;
1191
1192 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1193 loaded_vmcss_on_cpu_link)
1194 vmcs_clear(v->vmcs);
1195}
1196#else
1197static inline void crash_enable_local_vmclear(int cpu) { }
1198static inline void crash_disable_local_vmclear(int cpu) { }
1199#endif /* CONFIG_KEXEC */
1200
d462b819 1201static void __loaded_vmcs_clear(void *arg)
6aa8b732 1202{
d462b819 1203 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1204 int cpu = raw_smp_processor_id();
6aa8b732 1205
d462b819
NHE		 1206 if (loaded_vmcs->cpu != cpu)
1207 return; /* vcpu migration can race with cpu offline */
1208 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1209 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1210 crash_disable_local_vmclear(cpu);
d462b819 1211 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1212
1213 /*
1214 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1215 * is before setting loaded_vmcs->vcpu to -1 which is done in
1216 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1217 * then adds the vmcs into percpu list before it is deleted.
1218 */
1219 smp_wmb();
1220
d462b819 1221 loaded_vmcs_init(loaded_vmcs);
8f536b76 1222 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1223}
1224
d462b819 1225static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1226{
e6c7d321
XG		 1227 int cpu = loaded_vmcs->cpu;
1228
1229 if (cpu != -1)
1230 smp_call_function_single(cpu,
1231 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1232}
1233
1760dd49 1234static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1235{
1236 if (vmx->vpid == 0)
1237 return;
1238
518c8aee
GJ		 1239 if (cpu_has_vmx_invvpid_single())
1240 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1241}
1242
b9d762fa
GJ		 1243static inline void vpid_sync_vcpu_global(void)
1244{
1245 if (cpu_has_vmx_invvpid_global())
1246 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1247}
1248
1249static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1250{
1251 if (cpu_has_vmx_invvpid_single())
1760dd49 1252 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1253 else
1254 vpid_sync_vcpu_global();
1255}
1256
1439442c
SY		 1257static inline void ept_sync_global(void)
1258{
1259 if (cpu_has_vmx_invept_global())
1260 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1261}
1262
1263static inline void ept_sync_context(u64 eptp)
1264{
089d034e 1265 if (enable_ept) {
1439442c
SY		 1266 if (cpu_has_vmx_invept_context())
1267 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1268 else
1269 ept_sync_global();
1270 }
1271}
1272
96304217 1273static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1274{
5e520e62 1275 unsigned long value;
6aa8b732 1276
5e520e62
AK		 1277 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1278 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1279 return value;
1280}
1281
96304217 1282static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1283{
1284 return vmcs_readl(field);
1285}
1286
96304217 1287static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1288{
1289 return vmcs_readl(field);
1290}
1291
96304217 1292static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1293{
05b3e0c2 1294#ifdef CONFIG_X86_64
6aa8b732
AK		 1295 return vmcs_readl(field);
1296#else
1297 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1298#endif
1299}
1300
e52de1b8
AK		 1301static noinline void vmwrite_error(unsigned long field, unsigned long value)
1302{
1303 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1304 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1305 dump_stack();
1306}
1307
6aa8b732
AK		 1308static void vmcs_writel(unsigned long field, unsigned long value)
1309{
1310 u8 error;
1311
4ecac3fd 1312 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1313 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1314 if (unlikely(error))
1315 vmwrite_error(field, value);
6aa8b732
AK		 1316}
1317
1318static void vmcs_write16(unsigned long field, u16 value)
1319{
1320 vmcs_writel(field, value);
1321}
1322
1323static void vmcs_write32(unsigned long field, u32 value)
1324{
1325 vmcs_writel(field, value);
1326}
1327
1328static void vmcs_write64(unsigned long field, u64 value)
1329{
6aa8b732 1330 vmcs_writel(field, value);
7682f2d0 1331#ifndef CONFIG_X86_64
6aa8b732
AK		 1332 asm volatile ("");
1333 vmcs_writel(field+1, value >> 32);
1334#endif
1335}
1336
2ab455cc
AL		 1337static void vmcs_clear_bits(unsigned long field, u32 mask)
1338{
1339 vmcs_writel(field, vmcs_readl(field) & ~mask);
1340}
1341
1342static void vmcs_set_bits(unsigned long field, u32 mask)
1343{
1344 vmcs_writel(field, vmcs_readl(field) | mask);
1345}
1346
2961e876
GN		 1347static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1348{
1349 vmcs_write32(VM_ENTRY_CONTROLS, val);
1350 vmx->vm_entry_controls_shadow = val;
1351}
1352
1353static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1354{
1355 if (vmx->vm_entry_controls_shadow != val)
1356 vm_entry_controls_init(vmx, val);
1357}
1358
1359static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1360{
1361 return vmx->vm_entry_controls_shadow;
1362}
1363
1364
1365static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1366{
1367 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1368}
1369
1370static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1371{
1372 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1373}
1374
1375static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1376{
1377 vmcs_write32(VM_EXIT_CONTROLS, val);
1378 vmx->vm_exit_controls_shadow = val;
1379}
1380
1381static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1382{
1383 if (vmx->vm_exit_controls_shadow != val)
1384 vm_exit_controls_init(vmx, val);
1385}
1386
1387static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1388{
1389 return vmx->vm_exit_controls_shadow;
1390}
1391
1392
1393static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1394{
1395 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1396}
1397
1398static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1399{
1400 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1401}
1402
2fb92db1
AK		 1403static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1404{
1405 vmx->segment_cache.bitmask = 0;
1406}
1407
1408static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1409 unsigned field)
1410{
1411 bool ret;
1412 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1413
1414 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1415 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1416 vmx->segment_cache.bitmask = 0;
1417 }
1418 ret = vmx->segment_cache.bitmask & mask;
1419 vmx->segment_cache.bitmask |= mask;
1420 return ret;
1421}
1422
1423static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1424{
1425 u16 *p = &vmx->segment_cache.seg[seg].selector;
1426
1427 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1428 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1429 return *p;
1430}
1431
1432static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1433{
1434 ulong *p = &vmx->segment_cache.seg[seg].base;
1435
1436 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1437 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1438 return *p;
1439}
1440
1441static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1442{
1443 u32 *p = &vmx->segment_cache.seg[seg].limit;
1444
1445 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1446 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1447 return *p;
1448}
1449
1450static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1451{
1452 u32 *p = &vmx->segment_cache.seg[seg].ar;
1453
1454 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1455 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1456 return *p;
1457}
1458
abd3f2d6
AK		 1459static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1460{
1461 u32 eb;
1462
fd7373cc
JK		 1463 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1464 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1465 if ((vcpu->guest_debug &
1466 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1467 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1468 eb |= 1u << BP_VECTOR;
7ffd92c5 1469 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1470 eb = ~0;
089d034e 1471 if (enable_ept)
1439442c 1472 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1473 if (vcpu->fpu_active)
1474 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1475
1476 /* When we are running a nested L2 guest and L1 specified for it a
1477 * certain exception bitmap, we must trap the same exceptions and pass
1478 * them to L1. When running L2, we will only handle the exceptions
1479 * specified above if L1 did not want them.
1480 */
1481 if (is_guest_mode(vcpu))
1482 eb |= get_vmcs12(vcpu)->exception_bitmap;
1483
abd3f2d6
AK		 1484 vmcs_write32(EXCEPTION_BITMAP, eb);
1485}
1486
2961e876
GN		 1487static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1488 unsigned long entry, unsigned long exit)
8bf00a52 1489{
2961e876
GN		 1490 vm_entry_controls_clearbit(vmx, entry);
1491 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1492}
1493
61d2ef2c
AK		 1494static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1495{
1496 unsigned i;
1497 struct msr_autoload *m = &vmx->msr_autoload;
1498
8bf00a52
GN		 1499 switch (msr) {
1500 case MSR_EFER:
1501 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1502 clear_atomic_switch_msr_special(vmx,
1503 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1504 VM_EXIT_LOAD_IA32_EFER);
1505 return;
1506 }
1507 break;
1508 case MSR_CORE_PERF_GLOBAL_CTRL:
1509 if (cpu_has_load_perf_global_ctrl) {
2961e876 1510 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1511 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1512 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1513 return;
1514 }
1515 break;
110312c8
AK		 1516 }
1517
61d2ef2c
AK		 1518 for (i = 0; i < m->nr; ++i)
1519 if (m->guest[i].index == msr)
1520 break;
1521
1522 if (i == m->nr)
1523 return;
1524 --m->nr;
1525 m->guest[i] = m->guest[m->nr];
1526 m->host[i] = m->host[m->nr];
1527 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1528 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1529}
1530
2961e876
GN		 1531static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1532 unsigned long entry, unsigned long exit,
1533 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1534 u64 guest_val, u64 host_val)
8bf00a52
GN		 1535{
1536 vmcs_write64(guest_val_vmcs, guest_val);
1537 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1538 vm_entry_controls_setbit(vmx, entry);
1539 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1540}
1541
61d2ef2c
AK		 1542static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1543 u64 guest_val, u64 host_val)
1544{
1545 unsigned i;
1546 struct msr_autoload *m = &vmx->msr_autoload;
1547
8bf00a52
GN		 1548 switch (msr) {
1549 case MSR_EFER:
1550 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1551 add_atomic_switch_msr_special(vmx,
1552 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1553 VM_EXIT_LOAD_IA32_EFER,
1554 GUEST_IA32_EFER,
1555 HOST_IA32_EFER,
1556 guest_val, host_val);
1557 return;
1558 }
1559 break;
1560 case MSR_CORE_PERF_GLOBAL_CTRL:
1561 if (cpu_has_load_perf_global_ctrl) {
2961e876 1562 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1563 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1564 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1565 GUEST_IA32_PERF_GLOBAL_CTRL,
1566 HOST_IA32_PERF_GLOBAL_CTRL,
1567 guest_val, host_val);
1568 return;
1569 }
1570 break;
110312c8
AK		 1571 }
1572
61d2ef2c
AK		 1573 for (i = 0; i < m->nr; ++i)
1574 if (m->guest[i].index == msr)
1575 break;
1576
e7fc6f93 1577 if (i == NR_AUTOLOAD_MSRS) {
60266204 1578 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1579 "Can't add msr %x\n", msr);
1580 return;
1581 } else if (i == m->nr) {
61d2ef2c
AK		 1582 ++m->nr;
1583 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1584 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1585 }
1586
1587 m->guest[i].index = msr;
1588 m->guest[i].value = guest_val;
1589 m->host[i].index = msr;
1590 m->host[i].value = host_val;
1591}
1592
33ed6329
AK		 1593static void reload_tss(void)
1594{
33ed6329
AK		 1595 /*
1596 * VT restores TR but not its size. Useless.
1597 */
d359192f 1598 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1599 struct desc_struct *descs;
33ed6329 1600
d359192f 1601 descs = (void *)gdt->address;
33ed6329
AK		 1602 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1603 load_TR_desc();
33ed6329
AK		 1604}
1605
92c0d900 1606static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1607{
3a34a881 1608 u64 guest_efer;
51c6cf66
AK		 1609 u64 ignore_bits;
1610
f6801dff 1611 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1612
51c6cf66 1613 /*
0fa06071 1614 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1615 * outside long mode
1616 */
1617 ignore_bits = EFER_NX | EFER_SCE;
1618#ifdef CONFIG_X86_64
1619 ignore_bits |= EFER_LMA | EFER_LME;
1620 /* SCE is meaningful only in long mode on Intel */
1621 if (guest_efer & EFER_LMA)
1622 ignore_bits &= ~(u64)EFER_SCE;
1623#endif
51c6cf66
AK		 1624 guest_efer &= ~ignore_bits;
1625 guest_efer |= host_efer & ignore_bits;
26bb0981 1626 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1627 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1628
1629 clear_atomic_switch_msr(vmx, MSR_EFER);
1630 /* On ept, can't emulate nx, and must switch nx atomically */
1631 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1632 guest_efer = vmx->vcpu.arch.efer;
1633 if (!(guest_efer & EFER_LMA))
1634 guest_efer &= ~EFER_LME;
1635 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1636 return false;
1637 }
1638
26bb0981 1639 return true;
51c6cf66
AK		 1640}
1641
2d49ec72
GN		 1642static unsigned long segment_base(u16 selector)
1643{
d359192f 1644 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1645 struct desc_struct *d;
1646 unsigned long table_base;
1647 unsigned long v;
1648
1649 if (!(selector & ~3))
1650 return 0;
1651
d359192f 1652 table_base = gdt->address;
2d49ec72
GN		 1653
1654 if (selector & 4) { /* from ldt */
1655 u16 ldt_selector = kvm_read_ldt();
1656
1657 if (!(ldt_selector & ~3))
1658 return 0;
1659
1660 table_base = segment_base(ldt_selector);
1661 }
1662 d = (struct desc_struct *)(table_base + (selector & ~7));
1663 v = get_desc_base(d);
1664#ifdef CONFIG_X86_64
1665 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1666 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1667#endif
1668 return v;
1669}
1670
1671static inline unsigned long kvm_read_tr_base(void)
1672{
1673 u16 tr;
1674 asm("str %0" : "=g"(tr));
1675 return segment_base(tr);
1676}
1677
04d2cc77 1678static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1679{
04d2cc77 1680 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1681 int i;
04d2cc77 1682
a2fa3e9f 1683 if (vmx->host_state.loaded)
33ed6329
AK		 1684 return;
1685
a2fa3e9f 1686 vmx->host_state.loaded = 1;
33ed6329
AK		 1687 /*
1688 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1689 * allow segment selectors with cpl > 0 or ti == 1.
1690 */
d6e88aec 1691 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1692 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1693 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1694 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1695 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1696 vmx->host_state.fs_reload_needed = 0;
1697 } else {
33ed6329 1698 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1699 vmx->host_state.fs_reload_needed = 1;
33ed6329 1700 }
9581d442 1701 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1702 if (!(vmx->host_state.gs_sel & 7))
1703 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1704 else {
1705 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1706 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1707 }
1708
b2da15ac
AK		 1709#ifdef CONFIG_X86_64
1710 savesegment(ds, vmx->host_state.ds_sel);
1711 savesegment(es, vmx->host_state.es_sel);
1712#endif
1713
33ed6329
AK		 1714#ifdef CONFIG_X86_64
1715 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1716 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1717#else
a2fa3e9f
GH		 1718 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1719 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1720#endif
707c0874
AK		 1721
1722#ifdef CONFIG_X86_64
c8770e7b
AK		 1723 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1724 if (is_long_mode(&vmx->vcpu))
44ea2b17 1725 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1726#endif
da8999d3
LJ		 1727 if (boot_cpu_has(X86_FEATURE_MPX))
1728 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1729 for (i = 0; i < vmx->save_nmsrs; ++i)
1730 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1731 vmx->guest_msrs[i].data,
1732 vmx->guest_msrs[i].mask);
33ed6329
AK		 1733}
1734
a9b21b62 1735static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1736{
a2fa3e9f 1737 if (!vmx->host_state.loaded)
33ed6329
AK		 1738 return;
1739
e1beb1d3 1740 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1741 vmx->host_state.loaded = 0;
c8770e7b
AK		 1742#ifdef CONFIG_X86_64
1743 if (is_long_mode(&vmx->vcpu))
1744 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1745#endif
152d3f2f 1746 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1747 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1748#ifdef CONFIG_X86_64
9581d442 1749 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1750#else
1751 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1752#endif
33ed6329 1753 }
0a77fe4c
AK		 1754 if (vmx->host_state.fs_reload_needed)
1755 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1756#ifdef CONFIG_X86_64
1757 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1758 loadsegment(ds, vmx->host_state.ds_sel);
1759 loadsegment(es, vmx->host_state.es_sel);
1760 }
b2da15ac 1761#endif
152d3f2f 1762 reload_tss();
44ea2b17 1763#ifdef CONFIG_X86_64
c8770e7b 1764 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1765#endif
da8999d3
LJ		 1766 if (vmx->host_state.msr_host_bndcfgs)
1767 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1768 /*
1769 * If the FPU is not active (through the host task or
1770 * the guest vcpu), then restore the cr0.TS bit.
1771 */
1772 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1773 stts();
3444d7da 1774 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1775}
1776
a9b21b62
AK		 1777static void vmx_load_host_state(struct vcpu_vmx *vmx)
1778{
1779 preempt_disable();
1780 __vmx_load_host_state(vmx);
1781 preempt_enable();
1782}
1783
6aa8b732
AK		 1784/*
1785 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1786 * vcpu mutex is already taken.
1787 */
15ad7146 1788static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1789{
a2fa3e9f 1790 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1791 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1792
4610c9cc
DX		 1793 if (!vmm_exclusive)
1794 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1795 else if (vmx->loaded_vmcs->cpu != cpu)
1796 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1797
d462b819
NHE		 1798 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1799 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1800 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1801 }
1802
d462b819 1803 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1804 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1805 unsigned long sysenter_esp;
1806
a8eeb04a 1807 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1808 local_irq_disable();
8f536b76 1809 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1810
1811 /*
1812 * Read loaded_vmcs->cpu should be before fetching
1813 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1814 * See the comments in __loaded_vmcs_clear().
1815 */
1816 smp_rmb();
1817
d462b819
NHE		 1818 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1819 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1820 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1821 local_irq_enable();
1822
6aa8b732
AK		 1823 /*
1824 * Linux uses per-cpu TSS and GDT, so set these when switching
1825 * processors.
1826 */
d6e88aec 1827 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1828 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1829
1830 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1831 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1832 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1833 }
6aa8b732
AK		 1834}
1835
1836static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1837{
a9b21b62 1838 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1839 if (!vmm_exclusive) {
d462b819
NHE		 1840 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1841 vcpu->cpu = -1;
4610c9cc
DX		 1842 kvm_cpu_vmxoff();
1843 }
6aa8b732
AK		 1844}
1845
5fd86fcf
AK		 1846static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1847{
81231c69
AK		 1848 ulong cr0;
1849
5fd86fcf
AK		 1850 if (vcpu->fpu_active)
1851 return;
1852 vcpu->fpu_active = 1;
81231c69
AK		 1853 cr0 = vmcs_readl(GUEST_CR0);
1854 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1855 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1856 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1857 update_exception_bitmap(vcpu);
edcafe3c 1858 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1859 if (is_guest_mode(vcpu))
1860 vcpu->arch.cr0_guest_owned_bits &=
1861 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1862 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1863}
1864
edcafe3c
AK		 1865static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1866
fe3ef05c
NHE		 1867/*
1868 * Return the cr0 value that a nested guest would read. This is a combination
1869 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1870 * its hypervisor (cr0_read_shadow).
1871 */
1872static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1873{
1874 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1875 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1876}
1877static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1878{
1879 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1880 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1881}
1882
5fd86fcf
AK		 1883static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1884{
36cf24e0
NHE		 1885 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1886 * set this *before* calling this function.
1887 */
edcafe3c 1888 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1889 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1890 update_exception_bitmap(vcpu);
edcafe3c
AK		 1891 vcpu->arch.cr0_guest_owned_bits = 0;
1892 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1893 if (is_guest_mode(vcpu)) {
1894 /*
1895 * L1's specified read shadow might not contain the TS bit,
1896 * so now that we turned on shadowing of this bit, we need to
1897 * set this bit of the shadow. Like in nested_vmx_run we need
1898 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1899 * up-to-date here because we just decached cr0.TS (and we'll
1900 * only update vmcs12->guest_cr0 on nested exit).
1901 */
1902 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1904 (vcpu->arch.cr0 & X86_CR0_TS);
1905 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1906 } else
1907 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1908}
1909
6aa8b732
AK		 1910static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1911{
78ac8b47 1912 unsigned long rflags, save_rflags;
345dcaa8 1913
6de12732
AK		 1914 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1915 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1916 rflags = vmcs_readl(GUEST_RFLAGS);
1917 if (to_vmx(vcpu)->rmode.vm86_active) {
1918 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1919 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1920 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1921 }
1922 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1923 }
6de12732 1924 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1925}
1926
1927static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1928{
6de12732
AK		 1929 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1930 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1931 if (to_vmx(vcpu)->rmode.vm86_active) {
1932 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1933 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1934 }
6aa8b732
AK		 1935 vmcs_writel(GUEST_RFLAGS, rflags);
1936}
1937
2809f5d2
GC		 1938static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1939{
1940 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1941 int ret = 0;
1942
1943 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1944 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1945 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1946 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1947
1948 return ret & mask;
1949}
1950
1951static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1952{
1953 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1954 u32 interruptibility = interruptibility_old;
1955
1956 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1957
48005f64 1958 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1959 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1960 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1961 interruptibility |= GUEST_INTR_STATE_STI;
1962
1963 if ((interruptibility != interruptibility_old))
1964 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1965}
1966
6aa8b732
AK		 1967static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1968{
1969 unsigned long rip;
6aa8b732 1970
5fdbf976 1971 rip = kvm_rip_read(vcpu);
6aa8b732 1972 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1973 kvm_rip_write(vcpu, rip);
6aa8b732 1974
2809f5d2
GC		 1975 /* skipping an emulated instruction also counts */
1976 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1977}
1978
0b6ac343
NHE		 1979/*
1980 * KVM wants to inject page-faults which it got to the guest. This function
1981 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1982 */
e011c663 1983static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1984{
1985 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1986
e011c663 1987 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1988 return 0;
1989
533558bc
JK		 1990 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1991 vmcs_read32(VM_EXIT_INTR_INFO),
1992 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 1993 return 1;
1994}
1995
298101da 1996static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1997 bool has_error_code, u32 error_code,
1998 bool reinject)
298101da 1999{
77ab6db0 2000 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2001 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2002
e011c663
GN		 2003 if (!reinject && is_guest_mode(vcpu) &&
2004 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2005 return;
2006
8ab2d2e2 2007 if (has_error_code) {
77ab6db0 2008 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2009 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2010 }
77ab6db0 2011
7ffd92c5 2012 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2013 int inc_eip = 0;
2014 if (kvm_exception_is_soft(nr))
2015 inc_eip = vcpu->arch.event_exit_inst_len;
2016 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2017 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2018 return;
2019 }
2020
66fd3f7f
GN		 2021 if (kvm_exception_is_soft(nr)) {
2022 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2023 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2024 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2025 } else
2026 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2027
2028 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2029}
2030
4e47c7a6
SY		 2031static bool vmx_rdtscp_supported(void)
2032{
2033 return cpu_has_vmx_rdtscp();
2034}
2035
ad756a16
MJ		 2036static bool vmx_invpcid_supported(void)
2037{
2038 return cpu_has_vmx_invpcid() && enable_ept;
2039}
2040
a75beee6
ED		 2041/*
2042 * Swap MSR entry in host/guest MSR entry array.
2043 */
8b9cf98c 2044static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2045{
26bb0981 2046 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2047
2048 tmp = vmx->guest_msrs[to];
2049 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2050 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2051}
2052
8d14695f
YZ		 2053static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2054{
2055 unsigned long *msr_bitmap;
2056
2057 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2058 if (is_long_mode(vcpu))
2059 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2060 else
2061 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2062 } else {
2063 if (is_long_mode(vcpu))
2064 msr_bitmap = vmx_msr_bitmap_longmode;
2065 else
2066 msr_bitmap = vmx_msr_bitmap_legacy;
2067 }
2068
2069 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2070}
2071
e38aea3e
AK		 2072/*
2073 * Set up the vmcs to automatically save and restore system
2074 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2075 * mode, as fiddling with msrs is very expensive.
2076 */
8b9cf98c 2077static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2078{
26bb0981 2079 int save_nmsrs, index;
e38aea3e 2080
a75beee6
ED		 2081 save_nmsrs = 0;
2082#ifdef CONFIG_X86_64
8b9cf98c 2083 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2084 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2085 if (index >= 0)
8b9cf98c
RR		 2086 move_msr_up(vmx, index, save_nmsrs++);
2087 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2088 if (index >= 0)
8b9cf98c
RR		 2089 move_msr_up(vmx, index, save_nmsrs++);
2090 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2091 if (index >= 0)
8b9cf98c 2092 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2093 index = __find_msr_index(vmx, MSR_TSC_AUX);
2094 if (index >= 0 && vmx->rdtscp_enabled)
2095 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2096 /*
8c06585d 2097 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2098 * if efer.sce is enabled.
2099 */
8c06585d 2100 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2101 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2102 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2103 }
2104#endif
92c0d900
AK		 2105 index = __find_msr_index(vmx, MSR_EFER);
2106 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2107 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2108
26bb0981 2109 vmx->save_nmsrs = save_nmsrs;
5897297b 2110
8d14695f
YZ		 2111 if (cpu_has_vmx_msr_bitmap())
2112 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2113}
2114
6aa8b732
AK		 2115/*
2116 * reads and returns guest's timestamp counter "register"
2117 * guest_tsc = host_tsc + tsc_offset -- 21.3
2118 */
2119static u64 guest_read_tsc(void)
2120{
2121 u64 host_tsc, tsc_offset;
2122
2123 rdtscll(host_tsc);
2124 tsc_offset = vmcs_read64(TSC_OFFSET);
2125 return host_tsc + tsc_offset;
2126}
2127
d5c1785d
NHE		 2128/*
2129 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2130 * counter, even if a nested guest (L2) is currently running.
2131 */
886b470c 2132u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2133{
886b470c 2134 u64 tsc_offset;
d5c1785d 2135
d5c1785d
NHE		 2136 tsc_offset = is_guest_mode(vcpu) ?
2137 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2138 vmcs_read64(TSC_OFFSET);
2139 return host_tsc + tsc_offset;
2140}
2141
4051b188 2142/*
cc578287
ZA		 2143 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2144 * software catchup for faster rates on slower CPUs.
4051b188 2145 */
cc578287 2146static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2147{
cc578287
ZA		 2148 if (!scale)
2149 return;
2150
2151 if (user_tsc_khz > tsc_khz) {
2152 vcpu->arch.tsc_catchup = 1;
2153 vcpu->arch.tsc_always_catchup = 1;
2154 } else
2155 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2156}
2157
ba904635
WA		 2158static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2159{
2160 return vmcs_read64(TSC_OFFSET);
2161}
2162
6aa8b732 2163/*
99e3e30a 2164 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2165 */
99e3e30a 2166static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2167{
27fc51b2 2168 if (is_guest_mode(vcpu)) {
7991825b 2169 /*
27fc51b2
NHE		 2170 * We're here if L1 chose not to trap WRMSR to TSC. According
2171 * to the spec, this should set L1's TSC; The offset that L1
2172 * set for L2 remains unchanged, and still needs to be added
2173 * to the newly set TSC to get L2's TSC.
7991825b 2174 */
27fc51b2
NHE		 2175 struct vmcs12 *vmcs12;
2176 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2177 /* recalculate vmcs02.TSC_OFFSET: */
2178 vmcs12 = get_vmcs12(vcpu);
2179 vmcs_write64(TSC_OFFSET, offset +
2180 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2181 vmcs12->tsc_offset : 0));
2182 } else {
489223ed
YY		 2183 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2184 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2185 vmcs_write64(TSC_OFFSET, offset);
2186 }
6aa8b732
AK		 2187}
2188
f1e2b260 2189static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2190{
2191 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2192
e48672fa 2193 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2194 if (is_guest_mode(vcpu)) {
2195 /* Even when running L2, the adjustment needs to apply to L1 */
2196 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2197 } else
2198 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2199 offset + adjustment);
e48672fa
ZA		 2200}
2201
857e4099
JR		 2202static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2203{
2204 return target_tsc - native_read_tsc();
2205}
2206
801d3424
NHE		 2207static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2208{
2209 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2210 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2211}
2212
2213/*
2214 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2215 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2216 * all guests if the "nested" module option is off, and can also be disabled
2217 * for a single guest by disabling its VMX cpuid bit.
2218 */
2219static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2220{
2221 return nested && guest_cpuid_has_vmx(vcpu);
2222}
2223
b87a51ae
NHE		 2224/*
2225 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2226 * returned for the various VMX controls MSRs when nested VMX is enabled.
2227 * The same values should also be used to verify that vmcs12 control fields are
2228 * valid during nested entry from L1 to L2.
2229 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2230 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2231 * bit in the high half is on if the corresponding bit in the control field
2232 * may be on. See also vmx_control_verify().
2233 * TODO: allow these variables to be modified (downgraded) by module options
2234 * or other means.
2235 */
2236static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2237static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2238static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2239static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2240static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2241static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2242static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2243static __init void nested_vmx_setup_ctls_msrs(void)
2244{
2245 /*
2246 * Note that as a general rule, the high half of the MSRs (bits in
2247 * the control fields which may be 1) should be initialized by the
2248 * intersection of the underlying hardware's MSR (i.e., features which
2249 * can be supported) and the list of features we want to expose -
2250 * because they are known to be properly supported in our code.
2251 * Also, usually, the low half of the MSRs (bits which must be 1) can
2252 * be set to 0, meaning that L1 may turn off any of these bits. The
2253 * reason is that if one of these bits is necessary, it will appear
2254 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2255 * fields of vmcs01 and vmcs02, will turn these bits off - and
2256 * nested_vmx_exit_handled() will not pass related exits to L1.
2257 * These rules have exceptions below.
2258 */
2259
2260 /* pin-based controls */
eabeaacc
JK		 2261 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2262 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2263 /*
2264 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2265 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2266 */
eabeaacc
JK		 2267 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2268 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2269 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2270 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2271 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2272
33fb20c3
JK		 2273 /*
2274 * Exit controls
2275 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2276 * 17 must be 1.
2277 */
c0dfee58
ACL		 2278 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2279 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2280 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2281 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2282 nested_vmx_exit_ctls_high &=
b87a51ae 2283#ifdef CONFIG_X86_64
c0dfee58 2284 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2285#endif
f4124500
JK		 2286 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2287 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2288 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
7854cbca 2289 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
b87a51ae
NHE		 2290
2291 /* entry controls */
2292 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2293 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2294 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2295 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2296 nested_vmx_entry_ctls_high &=
57435349
JK		 2297#ifdef CONFIG_X86_64
2298 VM_ENTRY_IA32E_MODE |
2299#endif
2300 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2301 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2302 VM_ENTRY_LOAD_IA32_EFER);
57435349 2303
b87a51ae
NHE		 2304 /* cpu-based controls */
2305 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2306 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2307 nested_vmx_procbased_ctls_low = 0;
2308 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2309 CPU_BASED_VIRTUAL_INTR_PENDING |
2310 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2311 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2312 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2313 CPU_BASED_CR3_STORE_EXITING |
2314#ifdef CONFIG_X86_64
2315 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2316#endif
2317 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2318 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2319 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2320 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2321 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2322 /*
2323 * We can allow some features even when not supported by the
2324 * hardware. For example, L1 can specify an MSR bitmap - and we
2325 * can use it to avoid exits to L1 - even when L0 runs L2
2326 * without MSR bitmaps.
2327 */
2328 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2329
2330 /* secondary cpu-based controls */
2331 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2332 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2333 nested_vmx_secondary_ctls_low = 0;
2334 nested_vmx_secondary_ctls_high &=
d6851fbe 2335 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2336 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2337 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2338
afa61f75
NHE		 2339 if (enable_ept) {
2340 /* nested EPT: emulate EPT also to L1 */
2341 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2342 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2343 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2344 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2345 nested_vmx_ept_caps &= vmx_capability.ept;
2346 /*
2347 * Since invept is completely emulated we support both global
2348 * and context invalidation independent of what host cpu
2349 * supports
2350 */
2351 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2352 VMX_EPT_EXTENT_CONTEXT_BIT;
2353 } else
2354 nested_vmx_ept_caps = 0;
2355
c18911a2
JK		 2356 /* miscellaneous data */
2357 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2358 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2359 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2360 VMX_MISC_ACTIVITY_HLT;
c18911a2 2361 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2362}
2363
2364static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2365{
2366 /*
2367 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2368 */
2369 return ((control & high) | low) == control;
2370}
2371
2372static inline u64 vmx_control_msr(u32 low, u32 high)
2373{
2374 return low | ((u64)high << 32);
2375}
2376
cae50139 2377/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2378static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2379{
b87a51ae 2380 switch (msr_index) {
b87a51ae
NHE		 2381 case MSR_IA32_VMX_BASIC:
2382 /*
2383 * This MSR reports some information about VMX support. We
2384 * should return information about the VMX we emulate for the
2385 * guest, and the VMCS structure we give it - not about the
2386 * VMX support of the underlying hardware.
2387 */
2388 *pdata = VMCS12_REVISION |
2389 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2390 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2391 break;
2392 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2393 case MSR_IA32_VMX_PINBASED_CTLS:
2394 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2395 nested_vmx_pinbased_ctls_high);
2396 break;
2397 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2398 case MSR_IA32_VMX_PROCBASED_CTLS:
2399 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2400 nested_vmx_procbased_ctls_high);
2401 break;
2402 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2403 case MSR_IA32_VMX_EXIT_CTLS:
2404 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2405 nested_vmx_exit_ctls_high);
2406 break;
2407 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2408 case MSR_IA32_VMX_ENTRY_CTLS:
2409 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2410 nested_vmx_entry_ctls_high);
2411 break;
2412 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2413 *pdata = vmx_control_msr(nested_vmx_misc_low,
2414 nested_vmx_misc_high);
b87a51ae
NHE		 2415 break;
2416 /*
2417 * These MSRs specify bits which the guest must keep fixed (on or off)
2418 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2419 * We picked the standard core2 setting.
2420 */
2421#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2422#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2423 case MSR_IA32_VMX_CR0_FIXED0:
2424 *pdata = VMXON_CR0_ALWAYSON;
2425 break;
2426 case MSR_IA32_VMX_CR0_FIXED1:
2427 *pdata = -1ULL;
2428 break;
2429 case MSR_IA32_VMX_CR4_FIXED0:
2430 *pdata = VMXON_CR4_ALWAYSON;
2431 break;
2432 case MSR_IA32_VMX_CR4_FIXED1:
2433 *pdata = -1ULL;
2434 break;
2435 case MSR_IA32_VMX_VMCS_ENUM:
2436 *pdata = 0x1f;
2437 break;
2438 case MSR_IA32_VMX_PROCBASED_CTLS2:
2439 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2440 nested_vmx_secondary_ctls_high);
2441 break;
2442 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2443 /* Currently, no nested vpid support */
2444 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2445 break;
2446 default:
b87a51ae 2447 return 1;
b3897a49
NHE		 2448 }
2449
b87a51ae
NHE		 2450 return 0;
2451}
2452
6aa8b732
AK		 2453/*
2454 * Reads an msr value (of 'msr_index') into 'pdata'.
2455 * Returns 0 on success, non-0 otherwise.
2456 * Assumes vcpu_load() was already called.
2457 */
2458static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2459{
2460 u64 data;
26bb0981 2461 struct shared_msr_entry *msr;
6aa8b732
AK		 2462
2463 if (!pdata) {
2464 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2465 return -EINVAL;
2466 }
2467
2468 switch (msr_index) {
05b3e0c2 2469#ifdef CONFIG_X86_64
6aa8b732
AK		 2470 case MSR_FS_BASE:
2471 data = vmcs_readl(GUEST_FS_BASE);
2472 break;
2473 case MSR_GS_BASE:
2474 data = vmcs_readl(GUEST_GS_BASE);
2475 break;
44ea2b17
AK		 2476 case MSR_KERNEL_GS_BASE:
2477 vmx_load_host_state(to_vmx(vcpu));
2478 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2479 break;
26bb0981 2480#endif
6aa8b732 2481 case MSR_EFER:
3bab1f5d 2482 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2483 case MSR_IA32_TSC:
6aa8b732
AK		 2484 data = guest_read_tsc();
2485 break;
2486 case MSR_IA32_SYSENTER_CS:
2487 data = vmcs_read32(GUEST_SYSENTER_CS);
2488 break;
2489 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2490 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2491 break;
2492 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2493 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2494 break;
0dd376e7
LJ		 2495 case MSR_IA32_BNDCFGS:
2496 data = vmcs_read64(GUEST_BNDCFGS);
2497 break;
cae50139
JK		 2498 case MSR_IA32_FEATURE_CONTROL:
2499 if (!nested_vmx_allowed(vcpu))
2500 return 1;
2501 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2502 break;
2503 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2504 if (!nested_vmx_allowed(vcpu))
2505 return 1;
2506 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2507 case MSR_TSC_AUX:
2508 if (!to_vmx(vcpu)->rdtscp_enabled)
2509 return 1;
2510 /* Otherwise falls through */
6aa8b732 2511 default:
8b9cf98c 2512 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2513 if (msr) {
2514 data = msr->data;
2515 break;
6aa8b732 2516 }
3bab1f5d 2517 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2518 }
2519
2520 *pdata = data;
2521 return 0;
2522}
2523
cae50139
JK		 2524static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2525
6aa8b732
AK		 2526/*
2527 * Writes msr value into into the appropriate "register".
2528 * Returns 0 on success, non-0 otherwise.
2529 * Assumes vcpu_load() was already called.
2530 */
8fe8ab46 2531static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2532{
a2fa3e9f 2533 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2534 struct shared_msr_entry *msr;
2cc51560 2535 int ret = 0;
8fe8ab46
WA		 2536 u32 msr_index = msr_info->index;
2537 u64 data = msr_info->data;
2cc51560 2538
6aa8b732 2539 switch (msr_index) {
3bab1f5d 2540 case MSR_EFER:
8fe8ab46 2541 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2542 break;
16175a79 2543#ifdef CONFIG_X86_64
6aa8b732 2544 case MSR_FS_BASE:
2fb92db1 2545 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2546 vmcs_writel(GUEST_FS_BASE, data);
2547 break;
2548 case MSR_GS_BASE:
2fb92db1 2549 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2550 vmcs_writel(GUEST_GS_BASE, data);
2551 break;
44ea2b17
AK		 2552 case MSR_KERNEL_GS_BASE:
2553 vmx_load_host_state(vmx);
2554 vmx->msr_guest_kernel_gs_base = data;
2555 break;
6aa8b732
AK		 2556#endif
2557 case MSR_IA32_SYSENTER_CS:
2558 vmcs_write32(GUEST_SYSENTER_CS, data);
2559 break;
2560 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2561 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2562 break;
2563 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2564 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2565 break;
0dd376e7
LJ		 2566 case MSR_IA32_BNDCFGS:
2567 vmcs_write64(GUEST_BNDCFGS, data);
2568 break;
af24a4e4 2569 case MSR_IA32_TSC:
8fe8ab46 2570 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2571 break;
468d472f
SY		 2572 case MSR_IA32_CR_PAT:
2573 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2574 vmcs_write64(GUEST_IA32_PAT, data);
2575 vcpu->arch.pat = data;
2576 break;
2577 }
8fe8ab46 2578 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2579 break;
ba904635
WA		 2580 case MSR_IA32_TSC_ADJUST:
2581 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2582 break;
cae50139
JK		 2583 case MSR_IA32_FEATURE_CONTROL:
2584 if (!nested_vmx_allowed(vcpu) ||
2585 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2586 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2587 return 1;
2588 vmx->nested.msr_ia32_feature_control = data;
2589 if (msr_info->host_initiated && data == 0)
2590 vmx_leave_nested(vcpu);
2591 break;
2592 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2593 return 1; /* they are read-only */
4e47c7a6
SY		 2594 case MSR_TSC_AUX:
2595 if (!vmx->rdtscp_enabled)
2596 return 1;
2597 /* Check reserved bit, higher 32 bits should be zero */
2598 if ((data >> 32) != 0)
2599 return 1;
2600 /* Otherwise falls through */
6aa8b732 2601 default:
8b9cf98c 2602 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2603 if (msr) {
2604 msr->data = data;
2225fd56
AK		 2605 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2606 preempt_disable();
9ee73970
AK		 2607 kvm_set_shared_msr(msr->index, msr->data,
2608 msr->mask);
2225fd56
AK		 2609 preempt_enable();
2610 }
3bab1f5d 2611 break;
6aa8b732 2612 }
8fe8ab46 2613 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2614 }
2615
2cc51560 2616 return ret;
6aa8b732
AK		 2617}
2618
5fdbf976 2619static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2620{
5fdbf976
MT		 2621 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2622 switch (reg) {
2623 case VCPU_REGS_RSP:
2624 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2625 break;
2626 case VCPU_REGS_RIP:
2627 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2628 break;
6de4f3ad
AK		 2629 case VCPU_EXREG_PDPTR:
2630 if (enable_ept)
2631 ept_save_pdptrs(vcpu);
2632 break;
5fdbf976
MT		 2633 default:
2634 break;
2635 }
6aa8b732
AK		 2636}
2637
6aa8b732
AK		 2638static __init int cpu_has_kvm_support(void)
2639{
6210e37b 2640 return cpu_has_vmx();
6aa8b732
AK		 2641}
2642
2643static __init int vmx_disabled_by_bios(void)
2644{
2645 u64 msr;
2646
2647 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2648 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2649 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2650 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2651 && tboot_enabled())
2652 return 1;
23f3e991 2653 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2654 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2655 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2656 && !tboot_enabled()) {
2657 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2658 "activate TXT before enabling KVM\n");
cafd6659 2659 return 1;
f9335afe 2660 }
23f3e991
JC		 2661 /* launched w/o TXT and VMX disabled */
2662 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2663 && !tboot_enabled())
2664 return 1;
cafd6659
SW		 2665 }
2666
2667 return 0;
6aa8b732
AK		 2668}
2669
7725b894
DX		 2670static void kvm_cpu_vmxon(u64 addr)
2671{
2672 asm volatile (ASM_VMX_VMXON_RAX
2673 : : "a"(&addr), "m"(addr)
2674 : "memory", "cc");
2675}
2676
10474ae8 2677static int hardware_enable(void *garbage)
6aa8b732
AK		 2678{
2679 int cpu = raw_smp_processor_id();
2680 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2681 u64 old, test_bits;
6aa8b732 2682
10474ae8
AG		 2683 if (read_cr4() & X86_CR4_VMXE)
2684 return -EBUSY;
2685
d462b819 2686 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2687
2688 /*
2689 * Now we can enable the vmclear operation in kdump
2690 * since the loaded_vmcss_on_cpu list on this cpu
2691 * has been initialized.
2692 *
2693 * Though the cpu is not in VMX operation now, there
2694 * is no problem to enable the vmclear operation
2695 * for the loaded_vmcss_on_cpu list is empty!
2696 */
2697 crash_enable_local_vmclear(cpu);
2698
6aa8b732 2699 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2700
2701 test_bits = FEATURE_CONTROL_LOCKED;
2702 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2703 if (tboot_enabled())
2704 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2705
2706 if ((old & test_bits) != test_bits) {
6aa8b732 2707 /* enable and lock */
cafd6659
SW		 2708 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2709 }
66aee91a 2710 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2711
4610c9cc
DX		 2712 if (vmm_exclusive) {
2713 kvm_cpu_vmxon(phys_addr);
2714 ept_sync_global();
2715 }
10474ae8 2716
357d1226 2717 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2718
10474ae8 2719 return 0;
6aa8b732
AK		 2720}
2721
d462b819 2722static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2723{
2724 int cpu = raw_smp_processor_id();
d462b819 2725 struct loaded_vmcs *v, *n;
543e4243 2726
d462b819
NHE		 2727 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2728 loaded_vmcss_on_cpu_link)
2729 __loaded_vmcs_clear(v);
543e4243
AK		 2730}
2731
710ff4a8
EH		 2732
2733/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2734 * tricks.
2735 */
2736static void kvm_cpu_vmxoff(void)
6aa8b732 2737{
4ecac3fd 2738 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2739}
2740
710ff4a8
EH		 2741static void hardware_disable(void *garbage)
2742{
4610c9cc 2743 if (vmm_exclusive) {
d462b819 2744 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2745 kvm_cpu_vmxoff();
2746 }
7725b894 2747 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2748}
2749
1c3d14fe 2750static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2751 u32 msr, u32 *result)
1c3d14fe
YS		 2752{
2753 u32 vmx_msr_low, vmx_msr_high;
2754 u32 ctl = ctl_min | ctl_opt;
2755
2756 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2757
2758 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2759 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2760
2761 /* Ensure minimum (required) set of control bits are supported. */
2762 if (ctl_min & ~ctl)
002c7f7c 2763 return -EIO;
1c3d14fe
YS		 2764
2765 *result = ctl;
2766 return 0;
2767}
2768
110312c8
AK		 2769static __init bool allow_1_setting(u32 msr, u32 ctl)
2770{
2771 u32 vmx_msr_low, vmx_msr_high;
2772
2773 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2774 return vmx_msr_high & ctl;
2775}
2776
002c7f7c 2777static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2778{
2779 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2780 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2781 u32 _pin_based_exec_control = 0;
2782 u32 _cpu_based_exec_control = 0;
f78e0e2e 2783 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2784 u32 _vmexit_control = 0;
2785 u32 _vmentry_control = 0;
2786
10166744 2787 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2788#ifdef CONFIG_X86_64
2789 CPU_BASED_CR8_LOAD_EXITING |
2790 CPU_BASED_CR8_STORE_EXITING |
2791#endif
d56f546d
SY		 2792 CPU_BASED_CR3_LOAD_EXITING |
2793 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2794 CPU_BASED_USE_IO_BITMAPS |
2795 CPU_BASED_MOV_DR_EXITING |
a7052897 2796 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2797 CPU_BASED_MWAIT_EXITING |
2798 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2799 CPU_BASED_INVLPG_EXITING |
2800 CPU_BASED_RDPMC_EXITING;
443381a8 2801
f78e0e2e 2802 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2803 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2804 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2805 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2806 &_cpu_based_exec_control) < 0)
002c7f7c 2807 return -EIO;
6e5d865c
YS		 2808#ifdef CONFIG_X86_64
2809 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2810 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2811 ~CPU_BASED_CR8_STORE_EXITING;
2812#endif
f78e0e2e 2813 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2814 min2 = 0;
2815 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2816 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2817 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2818 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2819 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2820 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2821 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2822 SECONDARY_EXEC_RDTSCP |
83d4c286 2823 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2824 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2825 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2826 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2827 if (adjust_vmx_controls(min2, opt2,
2828 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2829 &_cpu_based_2nd_exec_control) < 0)
2830 return -EIO;
2831 }
2832#ifndef CONFIG_X86_64
2833 if (!(_cpu_based_2nd_exec_control &
2834 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2835 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2836#endif
83d4c286
YZ		 2837
2838 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2839 _cpu_based_2nd_exec_control &= ~(
8d14695f 2840 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2841 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2842 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2843
d56f546d 2844 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2845 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2846 enabled */
5fff7d27
GN		 2847 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2848 CPU_BASED_CR3_STORE_EXITING |
2849 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2850 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2851 vmx_capability.ept, vmx_capability.vpid);
2852 }
1c3d14fe 2853
81908bf4 2854 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2855#ifdef CONFIG_X86_64
2856 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2857#endif
a547c6db 2858 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2859 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2860 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2861 &_vmexit_control) < 0)
002c7f7c 2862 return -EIO;
1c3d14fe 2863
01e439be
YZ		 2864 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2865 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2866 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2867 &_pin_based_exec_control) < 0)
2868 return -EIO;
2869
2870 if (!(_cpu_based_2nd_exec_control &
2871 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2872 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2873 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2874
c845f9c6 2875 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2876 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2877 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2878 &_vmentry_control) < 0)
002c7f7c 2879 return -EIO;
6aa8b732 2880
c68876fd 2881 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2882
2883 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2884 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2885 return -EIO;
1c3d14fe
YS		 2886
2887#ifdef CONFIG_X86_64
2888 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2889 if (vmx_msr_high & (1u<<16))
002c7f7c 2890 return -EIO;
1c3d14fe
YS		 2891#endif
2892
2893 /* Require Write-Back (WB) memory type for VMCS accesses. */
2894 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2895 return -EIO;
1c3d14fe 2896
002c7f7c
YS		 2897 vmcs_conf->size = vmx_msr_high & 0x1fff;
2898 vmcs_conf->order = get_order(vmcs_config.size);
2899 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2900
002c7f7c
YS		 2901 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2902 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2903 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2904 vmcs_conf->vmexit_ctrl = _vmexit_control;
2905 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2906
110312c8
AK		 2907 cpu_has_load_ia32_efer =
2908 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2909 VM_ENTRY_LOAD_IA32_EFER)
2910 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2911 VM_EXIT_LOAD_IA32_EFER);
2912
8bf00a52
GN		 2913 cpu_has_load_perf_global_ctrl =
2914 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2915 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2916 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2917 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2918
2919 /*
2920 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2921 * but due to arrata below it can't be used. Workaround is to use
2922 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2923 *
2924 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2925 *
2926 * AAK155 (model 26)
2927 * AAP115 (model 30)
2928 * AAT100 (model 37)
2929 * BC86,AAY89,BD102 (model 44)
2930 * BA97 (model 46)
2931 *
2932 */
2933 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2934 switch (boot_cpu_data.x86_model) {
2935 case 26:
2936 case 30:
2937 case 37:
2938 case 44:
2939 case 46:
2940 cpu_has_load_perf_global_ctrl = false;
2941 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2942 "does not work properly. Using workaround\n");
2943 break;
2944 default:
2945 break;
2946 }
2947 }
2948
1c3d14fe 2949 return 0;
c68876fd 2950}
6aa8b732
AK		 2951
2952static struct vmcs *alloc_vmcs_cpu(int cpu)
2953{
2954 int node = cpu_to_node(cpu);
2955 struct page *pages;
2956 struct vmcs *vmcs;
2957
6484eb3e 2958 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2959 if (!pages)
2960 return NULL;
2961 vmcs = page_address(pages);
1c3d14fe
YS		 2962 memset(vmcs, 0, vmcs_config.size);
2963 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2964 return vmcs;
2965}
2966
2967static struct vmcs *alloc_vmcs(void)
2968{
d3b2c338 2969 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2970}
2971
2972static void free_vmcs(struct vmcs *vmcs)
2973{
1c3d14fe 2974 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2975}
2976
d462b819
NHE		 2977/*
2978 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2979 */
2980static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2981{
2982 if (!loaded_vmcs->vmcs)
2983 return;
2984 loaded_vmcs_clear(loaded_vmcs);
2985 free_vmcs(loaded_vmcs->vmcs);
2986 loaded_vmcs->vmcs = NULL;
2987}
2988
39959588 2989static void free_kvm_area(void)
6aa8b732
AK		 2990{
2991 int cpu;
2992
3230bb47 2993 for_each_possible_cpu(cpu) {
6aa8b732 2994 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2995 per_cpu(vmxarea, cpu) = NULL;
2996 }
6aa8b732
AK		 2997}
2998
6aa8b732
AK		 2999static __init int alloc_kvm_area(void)
3000{
3001 int cpu;
3002
3230bb47 3003 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3004 struct vmcs *vmcs;
3005
3006 vmcs = alloc_vmcs_cpu(cpu);
3007 if (!vmcs) {
3008 free_kvm_area();
3009 return -ENOMEM;
3010 }
3011
3012 per_cpu(vmxarea, cpu) = vmcs;
3013 }
3014 return 0;
3015}
3016
3017static __init int hardware_setup(void)
3018{
002c7f7c
YS		 3019 if (setup_vmcs_config(&vmcs_config) < 0)
3020 return -EIO;
50a37eb4
JR		 3021
3022 if (boot_cpu_has(X86_FEATURE_NX))
3023 kvm_enable_efer_bits(EFER_NX);
3024
93ba03c2
SY		 3025 if (!cpu_has_vmx_vpid())
3026 enable_vpid = 0;
abc4fc58
AG		 3027 if (!cpu_has_vmx_shadow_vmcs())
3028 enable_shadow_vmcs = 0;
93ba03c2 3029
4bc9b982
SY		 3030 if (!cpu_has_vmx_ept() ||
3031 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3032 enable_ept = 0;
3a624e29 3033 enable_unrestricted_guest = 0;
83c3a331 3034 enable_ept_ad_bits = 0;
3a624e29
NK		 3035 }
3036
83c3a331
XH		 3037 if (!cpu_has_vmx_ept_ad_bits())
3038 enable_ept_ad_bits = 0;
3039
3a624e29
NK		 3040 if (!cpu_has_vmx_unrestricted_guest())
3041 enable_unrestricted_guest = 0;
93ba03c2
SY		 3042
3043 if (!cpu_has_vmx_flexpriority())
3044 flexpriority_enabled = 0;
3045
95ba8273
GN		 3046 if (!cpu_has_vmx_tpr_shadow())
3047 kvm_x86_ops->update_cr8_intercept = NULL;
3048
54dee993
MT		 3049 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3050 kvm_disable_largepages();
3051
4b8d54f9
ZE		 3052 if (!cpu_has_vmx_ple())
3053 ple_gap = 0;
3054
01e439be
YZ		 3055 if (!cpu_has_vmx_apicv())
3056 enable_apicv = 0;
c7c9c56c 3057
01e439be 3058 if (enable_apicv)
c7c9c56c 3059 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3060 else {
c7c9c56c 3061 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3062 kvm_x86_ops->deliver_posted_interrupt = NULL;
3063 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3064 }
83d4c286 3065
b87a51ae
NHE		 3066 if (nested)
3067 nested_vmx_setup_ctls_msrs();
3068
6aa8b732
AK		 3069 return alloc_kvm_area();
3070}
3071
3072static __exit void hardware_unsetup(void)
3073{
3074 free_kvm_area();
3075}
3076
14168786
GN		 3077static bool emulation_required(struct kvm_vcpu *vcpu)
3078{
3079 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3080}
3081
91b0aa2c 3082static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3083 struct kvm_segment *save)
6aa8b732 3084{
d99e4152
GN		 3085 if (!emulate_invalid_guest_state) {
3086 /*
3087 * CS and SS RPL should be equal during guest entry according
3088 * to VMX spec, but in reality it is not always so. Since vcpu
3089 * is in the middle of the transition from real mode to
3090 * protected mode it is safe to assume that RPL 0 is a good
3091 * default value.
3092 */
3093 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3094 save->selector &= ~SELECTOR_RPL_MASK;
3095 save->dpl = save->selector & SELECTOR_RPL_MASK;
3096 save->s = 1;
6aa8b732 3097 }
d99e4152 3098 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3099}
3100
3101static void enter_pmode(struct kvm_vcpu *vcpu)
3102{
3103 unsigned long flags;
a89a8fb9 3104 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3105
d99e4152
GN		 3106 /*
3107 * Update real mode segment cache. It may be not up-to-date if sement
3108 * register was written while vcpu was in a guest mode.
3109 */
3110 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3111 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3112 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3113 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3114 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3115 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3116
7ffd92c5 3117 vmx->rmode.vm86_active = 0;
6aa8b732 3118
2fb92db1
AK		 3119 vmx_segment_cache_clear(vmx);
3120
f5f7b2fe 3121 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3122
3123 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3124 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3125 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3126 vmcs_writel(GUEST_RFLAGS, flags);
3127
66aee91a
RR		 3128 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3129 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3130
3131 update_exception_bitmap(vcpu);
3132
91b0aa2c
GN		 3133 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3134 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3135 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3136 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3137 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3138 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3139
3140 /* CPL is always 0 when CPU enters protected mode */
3141 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3142 vmx->cpl = 0;
6aa8b732
AK		 3143}
3144
f5f7b2fe 3145static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3146{
772e0318 3147 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3148 struct kvm_segment var = *save;
3149
3150 var.dpl = 0x3;
3151 if (seg == VCPU_SREG_CS)
3152 var.type = 0x3;
3153
3154 if (!emulate_invalid_guest_state) {
3155 var.selector = var.base >> 4;
3156 var.base = var.base & 0xffff0;
3157 var.limit = 0xffff;
3158 var.g = 0;
3159 var.db = 0;
3160 var.present = 1;
3161 var.s = 1;
3162 var.l = 0;
3163 var.unusable = 0;
3164 var.type = 0x3;
3165 var.avl = 0;
3166 if (save->base & 0xf)
3167 printk_once(KERN_WARNING "kvm: segment base is not "
3168 "paragraph aligned when entering "
3169 "protected mode (seg=%d)", seg);
3170 }
6aa8b732 3171
d99e4152
GN		 3172 vmcs_write16(sf->selector, var.selector);
3173 vmcs_write32(sf->base, var.base);
3174 vmcs_write32(sf->limit, var.limit);
3175 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3176}
3177
3178static void enter_rmode(struct kvm_vcpu *vcpu)
3179{
3180 unsigned long flags;
a89a8fb9 3181 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3182
f5f7b2fe
AK		 3183 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3184 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3185 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3186 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3187 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3188 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3189 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3190
7ffd92c5 3191 vmx->rmode.vm86_active = 1;
6aa8b732 3192
776e58ea
GN		 3193 /*
3194 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3195 * vcpu. Warn the user that an update is overdue.
776e58ea 3196 */
4918c6ca 3197 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3198 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3199 "called before entering vcpu\n");
776e58ea 3200
2fb92db1
AK		 3201 vmx_segment_cache_clear(vmx);
3202
4918c6ca 3203 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3204 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3205 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3206
3207 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3208 vmx->rmode.save_rflags = flags;
6aa8b732 3209
053de044 3210 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3211
3212 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3213 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3214 update_exception_bitmap(vcpu);
3215
d99e4152
GN		 3216 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3217 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3218 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3219 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3220 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3221 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3222
8668a3c4 3223 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3224}
3225
401d10de
AS		 3226static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3227{
3228 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3229 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3230
3231 if (!msr)
3232 return;
401d10de 3233
44ea2b17
AK		 3234 /*
3235 * Force kernel_gs_base reloading before EFER changes, as control
3236 * of this msr depends on is_long_mode().
3237 */
3238 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3239 vcpu->arch.efer = efer;
401d10de 3240 if (efer & EFER_LMA) {
2961e876 3241 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3242 msr->data = efer;
3243 } else {
2961e876 3244 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3245
3246 msr->data = efer & ~EFER_LME;
3247 }
3248 setup_msrs(vmx);
3249}
3250
05b3e0c2 3251#ifdef CONFIG_X86_64
6aa8b732
AK		 3252
3253static void enter_lmode(struct kvm_vcpu *vcpu)
3254{
3255 u32 guest_tr_ar;
3256
2fb92db1
AK		 3257 vmx_segment_cache_clear(to_vmx(vcpu));
3258
6aa8b732
AK		 3259 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3260 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3261 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3262 __func__);
6aa8b732
AK		 3263 vmcs_write32(GUEST_TR_AR_BYTES,
3264 (guest_tr_ar & ~AR_TYPE_MASK)
3265 | AR_TYPE_BUSY_64_TSS);
3266 }
da38f438 3267 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3268}
3269
3270static void exit_lmode(struct kvm_vcpu *vcpu)
3271{
2961e876 3272 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3273 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3274}
3275
3276#endif
3277
2384d2b3
SY		 3278static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3279{
b9d762fa 3280 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3281 if (enable_ept) {
3282 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3283 return;
4e1096d2 3284 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3285 }
2384d2b3
SY		 3286}
3287
e8467fda
AK		 3288static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3289{
3290 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3291
3292 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3293 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3294}
3295
aff48baa
AK		 3296static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3297{
3298 if (enable_ept && is_paging(vcpu))
3299 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3300 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3301}
3302
25c4c276 3303static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3304{
fc78f519
AK		 3305 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3306
3307 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3308 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3309}
3310
1439442c
SY		 3311static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3312{
d0d538b9
GN		 3313 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3314
6de4f3ad
AK		 3315 if (!test_bit(VCPU_EXREG_PDPTR,
3316 (unsigned long *)&vcpu->arch.regs_dirty))
3317 return;
3318
1439442c 3319 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3320 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3321 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3322 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3323 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3324 }
3325}
3326
8f5d549f
AK		 3327static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3328{
d0d538b9
GN		 3329 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3330
8f5d549f 3331 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3332 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3333 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3334 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3335 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3336 }
6de4f3ad
AK		 3337
3338 __set_bit(VCPU_EXREG_PDPTR,
3339 (unsigned long *)&vcpu->arch.regs_avail);
3340 __set_bit(VCPU_EXREG_PDPTR,
3341 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3342}
3343
5e1746d6 3344static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3345
3346static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3347 unsigned long cr0,
3348 struct kvm_vcpu *vcpu)
3349{
5233dd51
MT		 3350 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3351 vmx_decache_cr3(vcpu);
1439442c
SY		 3352 if (!(cr0 & X86_CR0_PG)) {
3353 /* From paging/starting to nonpaging */
3354 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3355 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3356 (CPU_BASED_CR3_LOAD_EXITING |
3357 CPU_BASED_CR3_STORE_EXITING));
3358 vcpu->arch.cr0 = cr0;
fc78f519 3359 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3360 } else if (!is_paging(vcpu)) {
3361 /* From nonpaging to paging */
3362 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3363 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3364 ~(CPU_BASED_CR3_LOAD_EXITING |
3365 CPU_BASED_CR3_STORE_EXITING));
3366 vcpu->arch.cr0 = cr0;
fc78f519 3367 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3368 }
95eb84a7
SY		 3369
3370 if (!(cr0 & X86_CR0_WP))
3371 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3372}
3373
6aa8b732
AK		 3374static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3375{
7ffd92c5 3376 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3377 unsigned long hw_cr0;
3378
5037878e 3379 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3380 if (enable_unrestricted_guest)
5037878e 3381 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3382 else {
5037878e 3383 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3384
218e763f
GN		 3385 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3386 enter_pmode(vcpu);
6aa8b732 3387
218e763f
GN		 3388 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3389 enter_rmode(vcpu);
3390 }
6aa8b732 3391
05b3e0c2 3392#ifdef CONFIG_X86_64
f6801dff 3393 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3394 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3395 enter_lmode(vcpu);
707d92fa 3396 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3397 exit_lmode(vcpu);
3398 }
3399#endif
3400
089d034e 3401 if (enable_ept)
1439442c
SY		 3402 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3403
02daab21 3404 if (!vcpu->fpu_active)
81231c69 3405 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3406
6aa8b732 3407 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3408 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3409 vcpu->arch.cr0 = cr0;
14168786
GN		 3410
3411 /* depends on vcpu->arch.cr0 to be set to a new value */
3412 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3413}
3414
1439442c
SY		 3415static u64 construct_eptp(unsigned long root_hpa)
3416{
3417 u64 eptp;
3418
3419 /* TODO write the value reading from MSR */
3420 eptp = VMX_EPT_DEFAULT_MT |
3421 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3422 if (enable_ept_ad_bits)
3423 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3424 eptp |= (root_hpa & PAGE_MASK);
3425
3426 return eptp;
3427}
3428
6aa8b732
AK		 3429static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3430{
1439442c
SY		 3431 unsigned long guest_cr3;
3432 u64 eptp;
3433
3434 guest_cr3 = cr3;
089d034e 3435 if (enable_ept) {
1439442c
SY		 3436 eptp = construct_eptp(cr3);
3437 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3438 if (is_paging(vcpu) || is_guest_mode(vcpu))
3439 guest_cr3 = kvm_read_cr3(vcpu);
3440 else
3441 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3442 ept_load_pdptrs(vcpu);
1439442c
SY		 3443 }
3444
2384d2b3 3445 vmx_flush_tlb(vcpu);
1439442c 3446 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3447}
3448
5e1746d6 3449static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3450{
7ffd92c5 3451 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3452 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3453
5e1746d6
NHE		 3454 if (cr4 & X86_CR4_VMXE) {
3455 /*
3456 * To use VMXON (and later other VMX instructions), a guest
3457 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3458 * So basically the check on whether to allow nested VMX
3459 * is here.
3460 */
3461 if (!nested_vmx_allowed(vcpu))
3462 return 1;
1a0d74e6
JK		 3463 }
3464 if (to_vmx(vcpu)->nested.vmxon &&
3465 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3466 return 1;
3467
ad312c7c 3468 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3469 if (enable_ept) {
3470 if (!is_paging(vcpu)) {
3471 hw_cr4 &= ~X86_CR4_PAE;
3472 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3473 /*
3474 * SMEP is disabled if CPU is in non-paging mode in
3475 * hardware. However KVM always uses paging mode to
3476 * emulate guest non-paging mode with TDP.
3477 * To emulate this behavior, SMEP needs to be manually
3478 * disabled when guest switches to non-paging mode.
3479 */
3480 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3481 } else if (!(cr4 & X86_CR4_PAE)) {
3482 hw_cr4 &= ~X86_CR4_PAE;
3483 }
3484 }
1439442c
SY		 3485
3486 vmcs_writel(CR4_READ_SHADOW, cr4);
3487 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3488 return 0;
6aa8b732
AK		 3489}
3490
6aa8b732
AK		 3491static void vmx_get_segment(struct kvm_vcpu *vcpu,
3492 struct kvm_segment *var, int seg)
3493{
a9179499 3494 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3495 u32 ar;
3496
c6ad1153 3497 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3498 *var = vmx->rmode.segs[seg];
a9179499 3499 if (seg == VCPU_SREG_TR
2fb92db1 3500 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3501 return;
1390a28b
AK		 3502 var->base = vmx_read_guest_seg_base(vmx, seg);
3503 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3504 return;
a9179499 3505 }
2fb92db1
AK		 3506 var->base = vmx_read_guest_seg_base(vmx, seg);
3507 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3508 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3509 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3510 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3511 var->type = ar & 15;
3512 var->s = (ar >> 4) & 1;
3513 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3514 /*
3515 * Some userspaces do not preserve unusable property. Since usable
3516 * segment has to be present according to VMX spec we can use present
3517 * property to amend userspace bug by making unusable segment always
3518 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3519 * segment as unusable.
3520 */
3521 var->present = !var->unusable;
6aa8b732
AK		 3522 var->avl = (ar >> 12) & 1;
3523 var->l = (ar >> 13) & 1;
3524 var->db = (ar >> 14) & 1;
3525 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3526}
3527
a9179499
AK		 3528static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3529{
a9179499
AK		 3530 struct kvm_segment s;
3531
3532 if (to_vmx(vcpu)->rmode.vm86_active) {
3533 vmx_get_segment(vcpu, &s, seg);
3534 return s.base;
3535 }
2fb92db1 3536 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3537}
3538
b09408d0 3539static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3540{
b09408d0
MT		 3541 struct vcpu_vmx *vmx = to_vmx(vcpu);
3542
3eeb3288 3543 if (!is_protmode(vcpu))
2e4d2653
IE		 3544 return 0;
3545
f4c63e5d
AK		 3546 if (!is_long_mode(vcpu)
3547 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3548 return 3;
3549
69c73028
AK		 3550 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3551 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3552 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3553 }
d881e6f6
AK		 3554
3555 return vmx->cpl;
69c73028
AK		 3556}
3557
3558
653e3108 3559static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3560{
6aa8b732
AK		 3561 u32 ar;
3562
f0495f9b 3563 if (var->unusable || !var->present)
6aa8b732
AK		 3564 ar = 1 << 16;
3565 else {
3566 ar = var->type & 15;
3567 ar |= (var->s & 1) << 4;
3568 ar |= (var->dpl & 3) << 5;
3569 ar |= (var->present & 1) << 7;
3570 ar |= (var->avl & 1) << 12;
3571 ar |= (var->l & 1) << 13;
3572 ar |= (var->db & 1) << 14;
3573 ar |= (var->g & 1) << 15;
3574 }
653e3108
AK		 3575
3576 return ar;
3577}
3578
3579static void vmx_set_segment(struct kvm_vcpu *vcpu,
3580 struct kvm_segment *var, int seg)
3581{
7ffd92c5 3582 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3583 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3584
2fb92db1 3585 vmx_segment_cache_clear(vmx);
2f143240
GN		 3586 if (seg == VCPU_SREG_CS)
3587 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3588
1ecd50a9
GN		 3589 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3590 vmx->rmode.segs[seg] = *var;
3591 if (seg == VCPU_SREG_TR)
3592 vmcs_write16(sf->selector, var->selector);
3593 else if (var->s)
3594 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3595 goto out;
653e3108 3596 }
1ecd50a9 3597
653e3108
AK		 3598 vmcs_writel(sf->base, var->base);
3599 vmcs_write32(sf->limit, var->limit);
3600 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3601
3602 /*
3603 * Fix the "Accessed" bit in AR field of segment registers for older
3604 * qemu binaries.
3605 * IA32 arch specifies that at the time of processor reset the
3606 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3607 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3608 * state vmexit when "unrestricted guest" mode is turned on.
3609 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3610 * tree. Newer qemu binaries with that qemu fix would not need this
3611 * kvm hack.
3612 */
3613 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3614 var->type |= 0x1; /* Accessed */
3a624e29 3615
f924d66d 3616 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3617
3618out:
14168786 3619 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3620}
3621
6aa8b732
AK		 3622static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3623{
2fb92db1 3624 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3625
3626 *db = (ar >> 14) & 1;
3627 *l = (ar >> 13) & 1;
3628}
3629
89a27f4d 3630static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3631{
89a27f4d
GN		 3632 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3633 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3634}
3635
89a27f4d 3636static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3637{
89a27f4d
GN		 3638 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3639 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3640}
3641
89a27f4d 3642static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3643{
89a27f4d
GN		 3644 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3645 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3646}
3647
89a27f4d 3648static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3649{
89a27f4d
GN		 3650 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3651 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3652}
3653
648dfaa7
MG		 3654static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3655{
3656 struct kvm_segment var;
3657 u32 ar;
3658
3659 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3660 var.dpl = 0x3;
0647f4aa
GN		 3661 if (seg == VCPU_SREG_CS)
3662 var.type = 0x3;
648dfaa7
MG		 3663 ar = vmx_segment_access_rights(&var);
3664
3665 if (var.base != (var.selector << 4))
3666 return false;
89efbed0 3667 if (var.limit != 0xffff)
648dfaa7 3668 return false;
07f42f5f 3669 if (ar != 0xf3)
648dfaa7
MG		 3670 return false;
3671
3672 return true;
3673}
3674
3675static bool code_segment_valid(struct kvm_vcpu *vcpu)
3676{
3677 struct kvm_segment cs;
3678 unsigned int cs_rpl;
3679
3680 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3681 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3682
1872a3f4
AK		 3683 if (cs.unusable)
3684 return false;
648dfaa7
MG		 3685 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3686 return false;
3687 if (!cs.s)
3688 return false;
1872a3f4 3689 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3690 if (cs.dpl > cs_rpl)
3691 return false;
1872a3f4 3692 } else {
648dfaa7
MG		 3693 if (cs.dpl != cs_rpl)
3694 return false;
3695 }
3696 if (!cs.present)
3697 return false;
3698
3699 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3700 return true;
3701}
3702
3703static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3704{
3705 struct kvm_segment ss;
3706 unsigned int ss_rpl;
3707
3708 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3709 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3710
1872a3f4
AK		 3711 if (ss.unusable)
3712 return true;
3713 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3714 return false;
3715 if (!ss.s)
3716 return false;
3717 if (ss.dpl != ss_rpl) /* DPL != RPL */
3718 return false;
3719 if (!ss.present)
3720 return false;
3721
3722 return true;
3723}
3724
3725static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3726{
3727 struct kvm_segment var;
3728 unsigned int rpl;
3729
3730 vmx_get_segment(vcpu, &var, seg);
3731 rpl = var.selector & SELECTOR_RPL_MASK;
3732
1872a3f4
AK		 3733 if (var.unusable)
3734 return true;
648dfaa7
MG		 3735 if (!var.s)
3736 return false;
3737 if (!var.present)
3738 return false;
3739 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3740 if (var.dpl < rpl) /* DPL < RPL */
3741 return false;
3742 }
3743
3744 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3745 * rights flags
3746 */
3747 return true;
3748}
3749
3750static bool tr_valid(struct kvm_vcpu *vcpu)
3751{
3752 struct kvm_segment tr;
3753
3754 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3755
1872a3f4
AK		 3756 if (tr.unusable)
3757 return false;
648dfaa7
MG		 3758 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3759 return false;
1872a3f4 3760 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3761 return false;
3762 if (!tr.present)
3763 return false;
3764
3765 return true;
3766}
3767
3768static bool ldtr_valid(struct kvm_vcpu *vcpu)
3769{
3770 struct kvm_segment ldtr;
3771
3772 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3773
1872a3f4
AK		 3774 if (ldtr.unusable)
3775 return true;
648dfaa7
MG		 3776 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3777 return false;
3778 if (ldtr.type != 2)
3779 return false;
3780 if (!ldtr.present)
3781 return false;
3782
3783 return true;
3784}
3785
3786static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3787{
3788 struct kvm_segment cs, ss;
3789
3790 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3791 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3792
3793 return ((cs.selector & SELECTOR_RPL_MASK) ==
3794 (ss.selector & SELECTOR_RPL_MASK));
3795}
3796
3797/*
3798 * Check if guest state is valid. Returns true if valid, false if
3799 * not.
3800 * We assume that registers are always usable
3801 */
3802static bool guest_state_valid(struct kvm_vcpu *vcpu)
3803{
c5e97c80
GN		 3804 if (enable_unrestricted_guest)
3805 return true;
3806
648dfaa7 3807 /* real mode guest state checks */
f13882d8 3808 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3809 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3810 return false;
3811 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3812 return false;
3813 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3814 return false;
3815 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3816 return false;
3817 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3818 return false;
3819 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3820 return false;
3821 } else {
3822 /* protected mode guest state checks */
3823 if (!cs_ss_rpl_check(vcpu))
3824 return false;
3825 if (!code_segment_valid(vcpu))
3826 return false;
3827 if (!stack_segment_valid(vcpu))
3828 return false;
3829 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3830 return false;
3831 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3832 return false;
3833 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3834 return false;
3835 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3836 return false;
3837 if (!tr_valid(vcpu))
3838 return false;
3839 if (!ldtr_valid(vcpu))
3840 return false;
3841 }
3842 /* TODO:
3843 * - Add checks on RIP
3844 * - Add checks on RFLAGS
3845 */
3846
3847 return true;
3848}
3849
d77c26fc 3850static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3851{
40dcaa9f 3852 gfn_t fn;
195aefde 3853 u16 data = 0;
40dcaa9f 3854 int r, idx, ret = 0;
6aa8b732 3855
40dcaa9f 3856 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3857 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3858 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3859 if (r < 0)
10589a46 3860 goto out;
195aefde 3861 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3862 r = kvm_write_guest_page(kvm, fn++, &data,
3863 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3864 if (r < 0)
10589a46 3865 goto out;
195aefde
IE		 3866 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3867 if (r < 0)
10589a46 3868 goto out;
195aefde
IE		 3869 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3870 if (r < 0)
10589a46 3871 goto out;
195aefde 3872 data = ~0;
10589a46
MT		 3873 r = kvm_write_guest_page(kvm, fn, &data,
3874 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3875 sizeof(u8));
195aefde 3876 if (r < 0)
10589a46
MT		 3877 goto out;
3878
3879 ret = 1;
3880out:
40dcaa9f 3881 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3882 return ret;
6aa8b732
AK		 3883}
3884
b7ebfb05
SY		 3885static int init_rmode_identity_map(struct kvm *kvm)
3886{
40dcaa9f 3887 int i, idx, r, ret;
b7ebfb05
SY		 3888 pfn_t identity_map_pfn;
3889 u32 tmp;
3890
089d034e 3891 if (!enable_ept)
b7ebfb05
SY		 3892 return 1;
3893 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3894 printk(KERN_ERR "EPT: identity-mapping pagetable "
3895 "haven't been allocated!\n");
3896 return 0;
3897 }
3898 if (likely(kvm->arch.ept_identity_pagetable_done))
3899 return 1;
3900 ret = 0;
b927a3ce 3901 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3902 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3903 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3904 if (r < 0)
3905 goto out;
3906 /* Set up identity-mapping pagetable for EPT in real mode */
3907 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3908 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3909 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3910 r = kvm_write_guest_page(kvm, identity_map_pfn,
3911 &tmp, i * sizeof(tmp), sizeof(tmp));
3912 if (r < 0)
3913 goto out;
3914 }
3915 kvm->arch.ept_identity_pagetable_done = true;
3916 ret = 1;
3917out:
40dcaa9f 3918 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3919 return ret;
3920}
3921
6aa8b732
AK		 3922static void seg_setup(int seg)
3923{
772e0318 3924 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3925 unsigned int ar;
6aa8b732
AK		 3926
3927 vmcs_write16(sf->selector, 0);
3928 vmcs_writel(sf->base, 0);
3929 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3930 ar = 0x93;
3931 if (seg == VCPU_SREG_CS)
3932 ar |= 0x08; /* code segment */
3a624e29
NK		 3933
3934 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3935}
3936
f78e0e2e
SY		 3937static int alloc_apic_access_page(struct kvm *kvm)
3938{
4484141a 3939 struct page *page;
f78e0e2e
SY		 3940 struct kvm_userspace_memory_region kvm_userspace_mem;
3941 int r = 0;
3942
79fac95e 3943 mutex_lock(&kvm->slots_lock);
bfc6d222 3944 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3945 goto out;
3946 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3947 kvm_userspace_mem.flags = 0;
3948 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3949 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3950 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3951 if (r)
3952 goto out;
72dc67a6 3953
4484141a
XG		 3954 page = gfn_to_page(kvm, 0xfee00);
3955 if (is_error_page(page)) {
3956 r = -EFAULT;
3957 goto out;
3958 }
3959
3960 kvm->arch.apic_access_page = page;
f78e0e2e 3961out:
79fac95e 3962 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3963 return r;
3964}
3965
b7ebfb05
SY		 3966static int alloc_identity_pagetable(struct kvm *kvm)
3967{
4484141a 3968 struct page *page;
b7ebfb05
SY		 3969 struct kvm_userspace_memory_region kvm_userspace_mem;
3970 int r = 0;
3971
79fac95e 3972 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3973 if (kvm->arch.ept_identity_pagetable)
3974 goto out;
3975 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3976 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3977 kvm_userspace_mem.guest_phys_addr =
3978 kvm->arch.ept_identity_map_addr;
b7ebfb05 3979 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3980 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3981 if (r)
3982 goto out;
3983
4484141a
XG		 3984 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3985 if (is_error_page(page)) {
3986 r = -EFAULT;
3987 goto out;
3988 }
3989
3990 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3991out:
79fac95e 3992 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3993 return r;
3994}
3995
2384d2b3
SY		 3996static void allocate_vpid(struct vcpu_vmx *vmx)
3997{
3998 int vpid;
3999
4000 vmx->vpid = 0;
919818ab 4001 if (!enable_vpid)
2384d2b3
SY		 4002 return;
4003 spin_lock(&vmx_vpid_lock);
4004 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4005 if (vpid < VMX_NR_VPIDS) {
4006 vmx->vpid = vpid;
4007 __set_bit(vpid, vmx_vpid_bitmap);
4008 }
4009 spin_unlock(&vmx_vpid_lock);
4010}
4011
cdbecfc3
LJ		 4012static void free_vpid(struct vcpu_vmx *vmx)
4013{
4014 if (!enable_vpid)
4015 return;
4016 spin_lock(&vmx_vpid_lock);
4017 if (vmx->vpid != 0)
4018 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4019 spin_unlock(&vmx_vpid_lock);
4020}
4021
8d14695f
YZ		 4022#define MSR_TYPE_R 1
4023#define MSR_TYPE_W 2
4024static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4025 u32 msr, int type)
25c5f225 4026{
3e7c73e9 4027 int f = sizeof(unsigned long);
25c5f225
SY		 4028
4029 if (!cpu_has_vmx_msr_bitmap())
4030 return;
4031
4032 /*
4033 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4034 * have the write-low and read-high bitmap offsets the wrong way round.
4035 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4036 */
25c5f225 4037 if (msr <= 0x1fff) {
8d14695f
YZ		 4038 if (type & MSR_TYPE_R)
4039 /* read-low */
4040 __clear_bit(msr, msr_bitmap + 0x000 / f);
4041
4042 if (type & MSR_TYPE_W)
4043 /* write-low */
4044 __clear_bit(msr, msr_bitmap + 0x800 / f);
4045
25c5f225
SY		 4046 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4047 msr &= 0x1fff;
8d14695f
YZ		 4048 if (type & MSR_TYPE_R)
4049 /* read-high */
4050 __clear_bit(msr, msr_bitmap + 0x400 / f);
4051
4052 if (type & MSR_TYPE_W)
4053 /* write-high */
4054 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4055
4056 }
4057}
4058
4059static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4060 u32 msr, int type)
4061{
4062 int f = sizeof(unsigned long);
4063
4064 if (!cpu_has_vmx_msr_bitmap())
4065 return;
4066
4067 /*
4068 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4069 * have the write-low and read-high bitmap offsets the wrong way round.
4070 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4071 */
4072 if (msr <= 0x1fff) {
4073 if (type & MSR_TYPE_R)
4074 /* read-low */
4075 __set_bit(msr, msr_bitmap + 0x000 / f);
4076
4077 if (type & MSR_TYPE_W)
4078 /* write-low */
4079 __set_bit(msr, msr_bitmap + 0x800 / f);
4080
4081 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4082 msr &= 0x1fff;
4083 if (type & MSR_TYPE_R)
4084 /* read-high */
4085 __set_bit(msr, msr_bitmap + 0x400 / f);
4086
4087 if (type & MSR_TYPE_W)
4088 /* write-high */
4089 __set_bit(msr, msr_bitmap + 0xc00 / f);
4090
25c5f225 4091 }
25c5f225
SY		 4092}
4093
5897297b
AK		 4094static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4095{
4096 if (!longmode_only)
8d14695f
YZ		 4097 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4098 msr, MSR_TYPE_R | MSR_TYPE_W);
4099 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4100 msr, MSR_TYPE_R | MSR_TYPE_W);
4101}
4102
4103static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4104{
4105 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4106 msr, MSR_TYPE_R);
4107 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4108 msr, MSR_TYPE_R);
4109}
4110
4111static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4112{
4113 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4114 msr, MSR_TYPE_R);
4115 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4116 msr, MSR_TYPE_R);
4117}
4118
4119static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4120{
4121 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4122 msr, MSR_TYPE_W);
4123 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4124 msr, MSR_TYPE_W);
5897297b
AK		 4125}
4126
01e439be
YZ		 4127static int vmx_vm_has_apicv(struct kvm *kvm)
4128{
4129 return enable_apicv && irqchip_in_kernel(kvm);
4130}
4131
a20ed54d
YZ		 4132/*
4133 * Send interrupt to vcpu via posted interrupt way.
4134 * 1. If target vcpu is running(non-root mode), send posted interrupt
4135 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4136 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4137 * interrupt from PIR in next vmentry.
4138 */
4139static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4140{
4141 struct vcpu_vmx *vmx = to_vmx(vcpu);
4142 int r;
4143
4144 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4145 return;
4146
4147 r = pi_test_and_set_on(&vmx->pi_desc);
4148 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4149#ifdef CONFIG_SMP
a20ed54d
YZ		 4150 if (!r && (vcpu->mode == IN_GUEST_MODE))
4151 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4152 POSTED_INTR_VECTOR);
4153 else
6ffbbbba 4154#endif
a20ed54d
YZ		 4155 kvm_vcpu_kick(vcpu);
4156}
4157
4158static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4159{
4160 struct vcpu_vmx *vmx = to_vmx(vcpu);
4161
4162 if (!pi_test_and_clear_on(&vmx->pi_desc))
4163 return;
4164
4165 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4166}
4167
4168static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4169{
4170 return;
4171}
4172
a3a8ff8e
NHE		 4173/*
4174 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4175 * will not change in the lifetime of the guest.
4176 * Note that host-state that does change is set elsewhere. E.g., host-state
4177 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4178 */
a547c6db 4179static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4180{
4181 u32 low32, high32;
4182 unsigned long tmpl;
4183 struct desc_ptr dt;
4184
b1a74bf8 4185 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4186 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4187 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4188
4189 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4190#ifdef CONFIG_X86_64
4191 /*
4192 * Load null selectors, so we can avoid reloading them in
4193 * __vmx_load_host_state(), in case userspace uses the null selectors
4194 * too (the expected case).
4195 */
4196 vmcs_write16(HOST_DS_SELECTOR, 0);
4197 vmcs_write16(HOST_ES_SELECTOR, 0);
4198#else
a3a8ff8e
NHE		 4199 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4200 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4201#endif
a3a8ff8e
NHE		 4202 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4203 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4204
4205 native_store_idt(&dt);
4206 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4207 vmx->host_idt_base = dt.address;
a3a8ff8e 4208
83287ea4 4209 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4210
4211 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4212 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4213 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4214 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4215
4216 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4217 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4218 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4219 }
4220}
4221
bf8179a0
NHE		 4222static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4223{
4224 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4225 if (enable_ept)
4226 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4227 if (is_guest_mode(&vmx->vcpu))
4228 vmx->vcpu.arch.cr4_guest_owned_bits &=
4229 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4230 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4231}
4232
01e439be
YZ		 4233static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4234{
4235 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4236
4237 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4238 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4239 return pin_based_exec_ctrl;
4240}
4241
bf8179a0
NHE		 4242static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4243{
4244 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4245
4246 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4247 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4248
bf8179a0
NHE		 4249 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4250 exec_control &= ~CPU_BASED_TPR_SHADOW;
4251#ifdef CONFIG_X86_64
4252 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4253 CPU_BASED_CR8_LOAD_EXITING;
4254#endif
4255 }
4256 if (!enable_ept)
4257 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4258 CPU_BASED_CR3_LOAD_EXITING |
4259 CPU_BASED_INVLPG_EXITING;
4260 return exec_control;
4261}
4262
4263static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4264{
4265 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4266 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4267 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4268 if (vmx->vpid == 0)
4269 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4270 if (!enable_ept) {
4271 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4272 enable_unrestricted_guest = 0;
ad756a16
MJ		 4273 /* Enable INVPCID for non-ept guests may cause performance regression. */
4274 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4275 }
4276 if (!enable_unrestricted_guest)
4277 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4278 if (!ple_gap)
4279 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4280 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4281 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4282 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4283 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4284 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4285 (handle_vmptrld).
4286 We can NOT enable shadow_vmcs here because we don't have yet
4287 a current VMCS12
4288 */
4289 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4290 return exec_control;
4291}
4292
ce88decf
XG		 4293static void ept_set_mmio_spte_mask(void)
4294{
4295 /*
4296 * EPT Misconfigurations can be generated if the value of bits 2:0
4297 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4298 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4299 * spte.
4300 */
885032b9 4301 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4302}
4303
6aa8b732
AK		 4304/*
4305 * Sets up the vmcs for emulated real mode.
4306 */
8b9cf98c 4307static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4308{
2e4ce7f5 4309#ifdef CONFIG_X86_64
6aa8b732 4310 unsigned long a;
2e4ce7f5 4311#endif
6aa8b732 4312 int i;
6aa8b732 4313
6aa8b732 4314 /* I/O */
3e7c73e9
AK		 4315 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4316 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4317
4607c2d7
AG		 4318 if (enable_shadow_vmcs) {
4319 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4320 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4321 }
25c5f225 4322 if (cpu_has_vmx_msr_bitmap())
5897297b 4323 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4324
6aa8b732
AK		 4325 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4326
6aa8b732 4327 /* Control */
01e439be 4328 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4329
bf8179a0 4330 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4331
83ff3b9d 4332 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4333 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4334 vmx_secondary_exec_control(vmx));
83ff3b9d 4335 }
f78e0e2e 4336
01e439be 4337 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4338 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4339 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4340 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4341 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4342
4343 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4344
4345 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4346 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4347 }
4348
4b8d54f9
ZE		 4349 if (ple_gap) {
4350 vmcs_write32(PLE_GAP, ple_gap);
4351 vmcs_write32(PLE_WINDOW, ple_window);
4352 }
4353
c3707958
XG		 4354 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4355 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4356 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4357
9581d442
AK		 4358 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4359 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4360 vmx_set_constant_host_state(vmx);
05b3e0c2 4361#ifdef CONFIG_X86_64
6aa8b732
AK		 4362 rdmsrl(MSR_FS_BASE, a);
4363 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4364 rdmsrl(MSR_GS_BASE, a);
4365 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4366#else
4367 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4368 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4369#endif
4370
2cc51560
ED		 4371 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4372 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4373 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4375 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4376
468d472f 4377 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4378 u32 msr_low, msr_high;
4379 u64 host_pat;
468d472f
SY		 4380 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4381 host_pat = msr_low | ((u64) msr_high << 32);
4382 /* Write the default value follow host pat */
4383 vmcs_write64(GUEST_IA32_PAT, host_pat);
4384 /* Keep arch.pat sync with GUEST_IA32_PAT */
4385 vmx->vcpu.arch.pat = host_pat;
4386 }
4387
6aa8b732
AK		 4388 for (i = 0; i < NR_VMX_MSR; ++i) {
4389 u32 index = vmx_msr_index[i];
4390 u32 data_low, data_high;
a2fa3e9f 4391 int j = vmx->nmsrs;
6aa8b732
AK		 4392
4393 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4394 continue;
432bd6cb
AK		 4395 if (wrmsr_safe(index, data_low, data_high) < 0)
4396 continue;
26bb0981
AK		 4397 vmx->guest_msrs[j].index = i;
4398 vmx->guest_msrs[j].data = 0;
d5696725 4399 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4400 ++vmx->nmsrs;
6aa8b732 4401 }
6aa8b732 4402
2961e876
GN		 4403
4404 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4405
4406 /* 22.2.1, 20.8.1 */
2961e876 4407 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4408
e00c8cf2 4409 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4410 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4411
4412 return 0;
4413}
4414
57f252f2 4415static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4416{
4417 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4418 struct msr_data apic_base_msr;
e00c8cf2 4419
7ffd92c5 4420 vmx->rmode.vm86_active = 0;
e00c8cf2 4421
3b86cd99
JK		 4422 vmx->soft_vnmi_blocked = 0;
4423
ad312c7c 4424 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4425 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4426 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4427 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4428 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4429 apic_base_msr.host_initiated = true;
4430 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4431
2fb92db1
AK		 4432 vmx_segment_cache_clear(vmx);
4433
5706be0d 4434 seg_setup(VCPU_SREG_CS);
66450a21 4435 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4436 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4437
4438 seg_setup(VCPU_SREG_DS);
4439 seg_setup(VCPU_SREG_ES);
4440 seg_setup(VCPU_SREG_FS);
4441 seg_setup(VCPU_SREG_GS);
4442 seg_setup(VCPU_SREG_SS);
4443
4444 vmcs_write16(GUEST_TR_SELECTOR, 0);
4445 vmcs_writel(GUEST_TR_BASE, 0);
4446 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4447 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4448
4449 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4450 vmcs_writel(GUEST_LDTR_BASE, 0);
4451 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4452 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4453
4454 vmcs_write32(GUEST_SYSENTER_CS, 0);
4455 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4456 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4457
4458 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4459 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4460
e00c8cf2
AK		 4461 vmcs_writel(GUEST_GDTR_BASE, 0);
4462 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4463
4464 vmcs_writel(GUEST_IDTR_BASE, 0);
4465 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4466
443381a8 4467 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4468 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4469 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4470
e00c8cf2
AK		 4471 /* Special registers */
4472 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4473
4474 setup_msrs(vmx);
4475
6aa8b732
AK		 4476 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4477
f78e0e2e
SY		 4478 if (cpu_has_vmx_tpr_shadow()) {
4479 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4480 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4481 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4482 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4483 vmcs_write32(TPR_THRESHOLD, 0);
4484 }
4485
4486 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4487 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4488 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4489
01e439be
YZ		 4490 if (vmx_vm_has_apicv(vcpu->kvm))
4491 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4492
2384d2b3
SY		 4493 if (vmx->vpid != 0)
4494 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4495
fa40052c 4496 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4497 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4498 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4499 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4500 vmx_fpu_activate(&vmx->vcpu);
4501 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4502
b9d762fa 4503 vpid_sync_context(vmx);
6aa8b732
AK		 4504}
4505
b6f1250e
NHE		 4506/*
4507 * In nested virtualization, check if L1 asked to exit on external interrupts.
4508 * For most existing hypervisors, this will always return true.
4509 */
4510static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4511{
4512 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4513 PIN_BASED_EXT_INTR_MASK;
4514}
4515
ea8ceb83
JK		 4516static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4517{
4518 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4519 PIN_BASED_NMI_EXITING;
4520}
4521
c9a7953f 4522static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4523{
4524 u32 cpu_based_vm_exec_control;
730dca42 4525
3b86cd99
JK		 4526 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4527 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4529}
4530
c9a7953f 4531static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4532{
4533 u32 cpu_based_vm_exec_control;
4534
c9a7953f
JK		 4535 if (!cpu_has_virtual_nmis() ||
4536 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4537 enable_irq_window(vcpu);
4538 return;
4539 }
3b86cd99
JK		 4540
4541 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4542 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4543 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4544}
4545
66fd3f7f 4546static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4547{
9c8cba37 4548 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4549 uint32_t intr;
4550 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4551
229456fc 4552 trace_kvm_inj_virq(irq);
2714d1d3 4553
fa89a817 4554 ++vcpu->stat.irq_injections;
7ffd92c5 4555 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4556 int inc_eip = 0;
4557 if (vcpu->arch.interrupt.soft)
4558 inc_eip = vcpu->arch.event_exit_inst_len;
4559 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4560 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4561 return;
4562 }
66fd3f7f
GN		 4563 intr = irq | INTR_INFO_VALID_MASK;
4564 if (vcpu->arch.interrupt.soft) {
4565 intr |= INTR_TYPE_SOFT_INTR;
4566 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4567 vmx->vcpu.arch.event_exit_inst_len);
4568 } else
4569 intr |= INTR_TYPE_EXT_INTR;
4570 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4571}
4572
f08864b4
SY		 4573static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4574{
66a5a347
JK		 4575 struct vcpu_vmx *vmx = to_vmx(vcpu);
4576
0b6ac343
NHE		 4577 if (is_guest_mode(vcpu))
4578 return;
4579
3b86cd99
JK		 4580 if (!cpu_has_virtual_nmis()) {
4581 /*
4582 * Tracking the NMI-blocked state in software is built upon
4583 * finding the next open IRQ window. This, in turn, depends on
4584 * well-behaving guests: They have to keep IRQs disabled at
4585 * least as long as the NMI handler runs. Otherwise we may
4586 * cause NMI nesting, maybe breaking the guest. But as this is
4587 * highly unlikely, we can live with the residual risk.
4588 */
4589 vmx->soft_vnmi_blocked = 1;
4590 vmx->vnmi_blocked_time = 0;
4591 }
4592
487b391d 4593 ++vcpu->stat.nmi_injections;
9d58b931 4594 vmx->nmi_known_unmasked = false;
7ffd92c5 4595 if (vmx->rmode.vm86_active) {
71f9833b 4596 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4597 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4598 return;
4599 }
f08864b4
SY		 4600 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4601 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4602}
4603
3cfc3092
JK		 4604static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4605{
4606 if (!cpu_has_virtual_nmis())
4607 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4608 if (to_vmx(vcpu)->nmi_known_unmasked)
4609 return false;
c332c83a 4610 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4611}
4612
4613static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4614{
4615 struct vcpu_vmx *vmx = to_vmx(vcpu);
4616
4617 if (!cpu_has_virtual_nmis()) {
4618 if (vmx->soft_vnmi_blocked != masked) {
4619 vmx->soft_vnmi_blocked = masked;
4620 vmx->vnmi_blocked_time = 0;
4621 }
4622 } else {
9d58b931 4623 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4624 if (masked)
4625 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4626 GUEST_INTR_STATE_NMI);
4627 else
4628 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4629 GUEST_INTR_STATE_NMI);
4630 }
4631}
4632
2505dc9f
JK		 4633static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4634{
b6b8a145
JK		 4635 if (to_vmx(vcpu)->nested.nested_run_pending)
4636 return 0;
ea8ceb83 4637
2505dc9f
JK		 4638 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4639 return 0;
4640
4641 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4642 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4643 | GUEST_INTR_STATE_NMI));
4644}
4645
78646121
GN		 4646static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4647{
b6b8a145
JK		 4648 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4649 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4650 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4651 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4652}
4653
cbc94022
IE		 4654static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4655{
4656 int ret;
4657 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4658 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4659 .guest_phys_addr = addr,
4660 .memory_size = PAGE_SIZE * 3,
4661 .flags = 0,
4662 };
4663
47ae31e2 4664 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4665 if (ret)
4666 return ret;
bfc6d222 4667 kvm->arch.tss_addr = addr;
93ea5388
GN		 4668 if (!init_rmode_tss(kvm))
4669 return -ENOMEM;
4670
cbc94022
IE		 4671 return 0;
4672}
4673
0ca1b4f4 4674static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4675{
77ab6db0 4676 switch (vec) {
77ab6db0 4677 case BP_VECTOR:
c573cd22
JK		 4678 /*
4679 * Update instruction length as we may reinject the exception
4680 * from user space while in guest debugging mode.
4681 */
4682 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4683 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4684 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4685 return false;
4686 /* fall through */
4687 case DB_VECTOR:
4688 if (vcpu->guest_debug &
4689 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4690 return false;
d0bfb940
JK		 4691 /* fall through */
4692 case DE_VECTOR:
77ab6db0
JK		 4693 case OF_VECTOR:
4694 case BR_VECTOR:
4695 case UD_VECTOR:
4696 case DF_VECTOR:
4697 case SS_VECTOR:
4698 case GP_VECTOR:
4699 case MF_VECTOR:
0ca1b4f4
GN		 4700 return true;
4701 break;
77ab6db0 4702 }
0ca1b4f4
GN		 4703 return false;
4704}
4705
4706static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4707 int vec, u32 err_code)
4708{
4709 /*
4710 * Instruction with address size override prefix opcode 0x67
4711 * Cause the #SS fault with 0 error code in VM86 mode.
4712 */
4713 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4714 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4715 if (vcpu->arch.halt_request) {
4716 vcpu->arch.halt_request = 0;
4717 return kvm_emulate_halt(vcpu);
4718 }
4719 return 1;
4720 }
4721 return 0;
4722 }
4723
4724 /*
4725 * Forward all other exceptions that are valid in real mode.
4726 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4727 * the required debugging infrastructure rework.
4728 */
4729 kvm_queue_exception(vcpu, vec);
4730 return 1;
6aa8b732
AK		 4731}
4732
a0861c02
AK		 4733/*
4734 * Trigger machine check on the host. We assume all the MSRs are already set up
4735 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4736 * We pass a fake environment to the machine check handler because we want
4737 * the guest to be always treated like user space, no matter what context
4738 * it used internally.
4739 */
4740static void kvm_machine_check(void)
4741{
4742#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4743 struct pt_regs regs = {
4744 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4745 .flags = X86_EFLAGS_IF,
4746 };
4747
4748 do_machine_check(&regs, 0);
4749#endif
4750}
4751
851ba692 4752static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4753{
4754 /* already handled by vcpu_run */
4755 return 1;
4756}
4757
851ba692 4758static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4759{
1155f76a 4760 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4761 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4762 u32 intr_info, ex_no, error_code;
42dbaa5a 4763 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4764 u32 vect_info;
4765 enum emulation_result er;
4766
1155f76a 4767 vect_info = vmx->idt_vectoring_info;
88786475 4768 intr_info = vmx->exit_intr_info;
6aa8b732 4769
a0861c02 4770 if (is_machine_check(intr_info))
851ba692 4771 return handle_machine_check(vcpu);
a0861c02 4772
e4a41889 4773 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4774 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4775
4776 if (is_no_device(intr_info)) {
5fd86fcf 4777 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4778 return 1;
4779 }
4780
7aa81cc0 4781 if (is_invalid_opcode(intr_info)) {
51d8b661 4782 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4783 if (er != EMULATE_DONE)
7ee5d940 4784 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4785 return 1;
4786 }
4787
6aa8b732 4788 error_code = 0;
2e11384c 4789 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4790 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4791
4792 /*
4793 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4794 * MMIO, it is better to report an internal error.
4795 * See the comments in vmx_handle_exit.
4796 */
4797 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4798 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4799 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4800 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4801 vcpu->run->internal.ndata = 2;
4802 vcpu->run->internal.data[0] = vect_info;
4803 vcpu->run->internal.data[1] = intr_info;
4804 return 0;
4805 }
4806
6aa8b732 4807 if (is_page_fault(intr_info)) {
1439442c 4808 /* EPT won't cause page fault directly */
cf3ace79 4809 BUG_ON(enable_ept);
6aa8b732 4810 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4811 trace_kvm_page_fault(cr2, error_code);
4812
3298b75c 4813 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4814 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4815 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4816 }
4817
d0bfb940 4818 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4819
4820 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4821 return handle_rmode_exception(vcpu, ex_no, error_code);
4822
42dbaa5a
JK		 4823 switch (ex_no) {
4824 case DB_VECTOR:
4825 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4826 if (!(vcpu->guest_debug &
4827 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4828 vcpu->arch.dr6 &= ~15;
4829 vcpu->arch.dr6 |= dr6;
42dbaa5a
JK		 4830 kvm_queue_exception(vcpu, DB_VECTOR);
4831 return 1;
4832 }
4833 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4834 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4835 /* fall through */
4836 case BP_VECTOR:
c573cd22
JK		 4837 /*
4838 * Update instruction length as we may reinject #BP from
4839 * user space while in guest debugging mode. Reading it for
4840 * #DB as well causes no harm, it is not used in that case.
4841 */
4842 vmx->vcpu.arch.event_exit_inst_len =
4843 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4844 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4845 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4846 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4847 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4848 break;
4849 default:
d0bfb940
JK		 4850 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4851 kvm_run->ex.exception = ex_no;
4852 kvm_run->ex.error_code = error_code;
42dbaa5a 4853 break;
6aa8b732 4854 }
6aa8b732
AK		 4855 return 0;
4856}
4857
851ba692 4858static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4859{
1165f5fe 4860 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4861 return 1;
4862}
4863
851ba692 4864static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4865{
851ba692 4866 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4867 return 0;
4868}
6aa8b732 4869
851ba692 4870static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4871{
bfdaab09 4872 unsigned long exit_qualification;
34c33d16 4873 int size, in, string;
039576c0 4874 unsigned port;
6aa8b732 4875
bfdaab09 4876 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4877 string = (exit_qualification & 16) != 0;
cf8f70bf 4878 in = (exit_qualification & 8) != 0;
e70669ab 4879
cf8f70bf 4880 ++vcpu->stat.io_exits;
e70669ab 4881
cf8f70bf 4882 if (string || in)
51d8b661 4883 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4884
cf8f70bf
GN		 4885 port = exit_qualification >> 16;
4886 size = (exit_qualification & 7) + 1;
e93f36bc 4887 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4888
4889 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4890}
4891
102d8325
IM		 4892static void
4893vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4894{
4895 /*
4896 * Patch in the VMCALL instruction:
4897 */
4898 hypercall[0] = 0x0f;
4899 hypercall[1] = 0x01;
4900 hypercall[2] = 0xc1;
102d8325
IM		 4901}
4902
92fbc7b1
JK		 4903static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4904{
4905 unsigned long always_on = VMXON_CR0_ALWAYSON;
4906
4907 if (nested_vmx_secondary_ctls_high &
4908 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4909 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4910 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4911 return (val & always_on) == always_on;
4912}
4913
0fa06071 4914/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4915static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4916{
eeadf9e7 4917 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4918 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4919 unsigned long orig_val = val;
4920
eeadf9e7
NHE		 4921 /*
4922 * We get here when L2 changed cr0 in a way that did not change
4923 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4924 * but did change L0 shadowed bits. So we first calculate the
4925 * effective cr0 value that L1 would like to write into the
4926 * hardware. It consists of the L2-owned bits from the new
4927 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4928 */
1a0d74e6
JK		 4929 val = (val & ~vmcs12->cr0_guest_host_mask) |
4930 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4931
92fbc7b1 4932 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4933 return 1;
1a0d74e6
JK		 4934
4935 if (kvm_set_cr0(vcpu, val))
4936 return 1;
4937 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4938 return 0;
1a0d74e6
JK		 4939 } else {
4940 if (to_vmx(vcpu)->nested.vmxon &&
4941 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4942 return 1;
eeadf9e7 4943 return kvm_set_cr0(vcpu, val);
1a0d74e6 4944 }
eeadf9e7
NHE		 4945}
4946
4947static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4948{
4949 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4950 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4951 unsigned long orig_val = val;
4952
4953 /* analogously to handle_set_cr0 */
4954 val = (val & ~vmcs12->cr4_guest_host_mask) |
4955 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4956 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4957 return 1;
1a0d74e6 4958 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4959 return 0;
4960 } else
4961 return kvm_set_cr4(vcpu, val);
4962}
4963
4964/* called to set cr0 as approriate for clts instruction exit. */
4965static void handle_clts(struct kvm_vcpu *vcpu)
4966{
4967 if (is_guest_mode(vcpu)) {
4968 /*
4969 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4970 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4971 * just pretend it's off (also in arch.cr0 for fpu_activate).
4972 */
4973 vmcs_writel(CR0_READ_SHADOW,
4974 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4975 vcpu->arch.cr0 &= ~X86_CR0_TS;
4976 } else
4977 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4978}
4979
851ba692 4980static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4981{
229456fc 4982 unsigned long exit_qualification, val;
6aa8b732
AK		 4983 int cr;
4984 int reg;
49a9b07e 4985 int err;
6aa8b732 4986
bfdaab09 4987 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4988 cr = exit_qualification & 15;
4989 reg = (exit_qualification >> 8) & 15;
4990 switch ((exit_qualification >> 4) & 3) {
4991 case 0: /* mov to cr */
229456fc
MT		 4992 val = kvm_register_read(vcpu, reg);
4993 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4994 switch (cr) {
4995 case 0:
eeadf9e7 4996 err = handle_set_cr0(vcpu, val);
db8fcefa 4997 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4998 return 1;
4999 case 3:
2390218b 5000 err = kvm_set_cr3(vcpu, val);
db8fcefa 5001 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5002 return 1;
5003 case 4:
eeadf9e7 5004 err = handle_set_cr4(vcpu, val);
db8fcefa 5005 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5006 return 1;
0a5fff19
GN		 5007 case 8: {
5008 u8 cr8_prev = kvm_get_cr8(vcpu);
5009 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5010 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5011 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5012 if (irqchip_in_kernel(vcpu->kvm))
5013 return 1;
5014 if (cr8_prev <= cr8)
5015 return 1;
851ba692 5016 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5017 return 0;
5018 }
4b8073e4 5019 }
6aa8b732 5020 break;
25c4c276 5021 case 2: /* clts */
eeadf9e7 5022 handle_clts(vcpu);
4d4ec087 5023 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5024 skip_emulated_instruction(vcpu);
6b52d186 5025 vmx_fpu_activate(vcpu);
25c4c276 5026 return 1;
6aa8b732
AK		 5027 case 1: /*mov from cr*/
5028 switch (cr) {
5029 case 3:
9f8fe504
AK		 5030 val = kvm_read_cr3(vcpu);
5031 kvm_register_write(vcpu, reg, val);
5032 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5033 skip_emulated_instruction(vcpu);
5034 return 1;
5035 case 8:
229456fc
MT		 5036 val = kvm_get_cr8(vcpu);
5037 kvm_register_write(vcpu, reg, val);
5038 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5039 skip_emulated_instruction(vcpu);
5040 return 1;
5041 }
5042 break;
5043 case 3: /* lmsw */
a1f83a74 5044 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5045 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5046 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5047
5048 skip_emulated_instruction(vcpu);
5049 return 1;
5050 default:
5051 break;
5052 }
851ba692 5053 vcpu->run->exit_reason = 0;
a737f256 5054 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5055 (int)(exit_qualification >> 4) & 3, cr);
5056 return 0;
5057}
5058
851ba692 5059static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5060{
bfdaab09 5061 unsigned long exit_qualification;
6aa8b732
AK		 5062 int dr, reg;
5063
f2483415 5064 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5065 if (!kvm_require_cpl(vcpu, 0))
5066 return 1;
42dbaa5a
JK		 5067 dr = vmcs_readl(GUEST_DR7);
5068 if (dr & DR7_GD) {
5069 /*
5070 * As the vm-exit takes precedence over the debug trap, we
5071 * need to emulate the latter, either for the host or the
5072 * guest debugging itself.
5073 */
5074 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5075 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5076 vcpu->run->debug.arch.dr7 = dr;
5077 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5078 vmcs_readl(GUEST_CS_BASE) +
5079 vmcs_readl(GUEST_RIP);
851ba692
AK		 5080 vcpu->run->debug.arch.exception = DB_VECTOR;
5081 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5082 return 0;
5083 } else {
5084 vcpu->arch.dr7 &= ~DR7_GD;
5085 vcpu->arch.dr6 |= DR6_BD;
5086 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5087 kvm_queue_exception(vcpu, DB_VECTOR);
5088 return 1;
5089 }
5090 }
5091
81908bf4
PB		 5092 if (vcpu->guest_debug == 0) {
5093 u32 cpu_based_vm_exec_control;
5094
5095 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5096 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5097 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5098
5099 /*
5100 * No more DR vmexits; force a reload of the debug registers
5101 * and reenter on this instruction. The next vmexit will
5102 * retrieve the full state of the debug registers.
5103 */
5104 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5105 return 1;
5106 }
5107
bfdaab09 5108 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5109 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5110 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5111 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5112 unsigned long val;
4c4d563b
JK		 5113
5114 if (kvm_get_dr(vcpu, dr, &val))
5115 return 1;
5116 kvm_register_write(vcpu, reg, val);
020df079 5117 } else
4c4d563b
JK		 5118 if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]))
5119 return 1;
5120
6aa8b732
AK		 5121 skip_emulated_instruction(vcpu);
5122 return 1;
5123}
5124
73aaf249
JK		 5125static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5126{
5127 return vcpu->arch.dr6;
5128}
5129
5130static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5131{
5132}
5133
81908bf4
PB		 5134static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5135{
5136 u32 cpu_based_vm_exec_control;
5137
5138 get_debugreg(vcpu->arch.db[0], 0);
5139 get_debugreg(vcpu->arch.db[1], 1);
5140 get_debugreg(vcpu->arch.db[2], 2);
5141 get_debugreg(vcpu->arch.db[3], 3);
5142 get_debugreg(vcpu->arch.dr6, 6);
5143 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5144
5145 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5146
5147 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5148 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5149 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5150}
5151
020df079
GN		 5152static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5153{
5154 vmcs_writel(GUEST_DR7, val);
5155}
5156
851ba692 5157static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5158{
06465c5a
AK		 5159 kvm_emulate_cpuid(vcpu);
5160 return 1;
6aa8b732
AK		 5161}
5162
851ba692 5163static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5164{
ad312c7c 5165 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5166 u64 data;
5167
5168 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5169 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5170 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5171 return 1;
5172 }
5173
229456fc 5174 trace_kvm_msr_read(ecx, data);
2714d1d3 5175
6aa8b732 5176 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5177 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5178 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5179 skip_emulated_instruction(vcpu);
5180 return 1;
5181}
5182
851ba692 5183static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5184{
8fe8ab46 5185 struct msr_data msr;
ad312c7c
ZX		 5186 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5187 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5188 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5189
8fe8ab46
WA		 5190 msr.data = data;
5191 msr.index = ecx;
5192 msr.host_initiated = false;
5193 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5194 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5195 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5196 return 1;
5197 }
5198
59200273 5199 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5200 skip_emulated_instruction(vcpu);
5201 return 1;
5202}
5203
851ba692 5204static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5205{
3842d135 5206 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5207 return 1;
5208}
5209
851ba692 5210static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5211{
85f455f7
ED		 5212 u32 cpu_based_vm_exec_control;
5213
5214 /* clear pending irq */
5215 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5216 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5217 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5218
3842d135
AK		 5219 kvm_make_request(KVM_REQ_EVENT, vcpu);
5220
a26bf12a 5221 ++vcpu->stat.irq_window_exits;
2714d1d3 5222
c1150d8c
DL		 5223 /*
5224 * If the user space waits to inject interrupts, exit as soon as
5225 * possible
5226 */
8061823a 5227 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5228 vcpu->run->request_interrupt_window &&
8061823a 5229 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5230 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5231 return 0;
5232 }
6aa8b732
AK		 5233 return 1;
5234}
5235
851ba692 5236static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5237{
5238 skip_emulated_instruction(vcpu);
d3bef15f 5239 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5240}
5241
851ba692 5242static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5243{
510043da 5244 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5245 kvm_emulate_hypercall(vcpu);
5246 return 1;
c21415e8
IM		 5247}
5248
ec25d5e6
GN		 5249static int handle_invd(struct kvm_vcpu *vcpu)
5250{
51d8b661 5251 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5252}
5253
851ba692 5254static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5255{
f9c617f6 5256 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5257
5258 kvm_mmu_invlpg(vcpu, exit_qualification);
5259 skip_emulated_instruction(vcpu);
5260 return 1;
5261}
5262
fee84b07
AK		 5263static int handle_rdpmc(struct kvm_vcpu *vcpu)
5264{
5265 int err;
5266
5267 err = kvm_rdpmc(vcpu);
5268 kvm_complete_insn_gp(vcpu, err);
5269
5270 return 1;
5271}
5272
851ba692 5273static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5274{
5275 skip_emulated_instruction(vcpu);
f5f48ee1 5276 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5277 return 1;
5278}
5279
2acf923e
DC		 5280static int handle_xsetbv(struct kvm_vcpu *vcpu)
5281{
5282 u64 new_bv = kvm_read_edx_eax(vcpu);
5283 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5284
5285 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5286 skip_emulated_instruction(vcpu);
5287 return 1;
5288}
5289
851ba692 5290static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5291{
58fbbf26
KT		 5292 if (likely(fasteoi)) {
5293 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5294 int access_type, offset;
5295
5296 access_type = exit_qualification & APIC_ACCESS_TYPE;
5297 offset = exit_qualification & APIC_ACCESS_OFFSET;
5298 /*
5299 * Sane guest uses MOV to write EOI, with written value
5300 * not cared. So make a short-circuit here by avoiding
5301 * heavy instruction emulation.
5302 */
5303 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5304 (offset == APIC_EOI)) {
5305 kvm_lapic_set_eoi(vcpu);
5306 skip_emulated_instruction(vcpu);
5307 return 1;
5308 }
5309 }
51d8b661 5310 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5311}
5312
c7c9c56c
YZ		 5313static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5314{
5315 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5316 int vector = exit_qualification & 0xff;
5317
5318 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5319 kvm_apic_set_eoi_accelerated(vcpu, vector);
5320 return 1;
5321}
5322
83d4c286
YZ		 5323static int handle_apic_write(struct kvm_vcpu *vcpu)
5324{
5325 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5326 u32 offset = exit_qualification & 0xfff;
5327
5328 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5329 kvm_apic_write_nodecode(vcpu, offset);
5330 return 1;
5331}
5332
851ba692 5333static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5334{
60637aac 5335 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5336 unsigned long exit_qualification;
e269fb21
JK		 5337 bool has_error_code = false;
5338 u32 error_code = 0;
37817f29 5339 u16 tss_selector;
7f3d35fd 5340 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5341
5342 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5343 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5344 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5345
5346 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5347
5348 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5349 if (reason == TASK_SWITCH_GATE && idt_v) {
5350 switch (type) {
5351 case INTR_TYPE_NMI_INTR:
5352 vcpu->arch.nmi_injected = false;
654f06fc 5353 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5354 break;
5355 case INTR_TYPE_EXT_INTR:
66fd3f7f 5356 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5357 kvm_clear_interrupt_queue(vcpu);
5358 break;
5359 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5360 if (vmx->idt_vectoring_info &
5361 VECTORING_INFO_DELIVER_CODE_MASK) {
5362 has_error_code = true;
5363 error_code =
5364 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5365 }
5366 /* fall through */
64a7ec06
GN		 5367 case INTR_TYPE_SOFT_EXCEPTION:
5368 kvm_clear_exception_queue(vcpu);
5369 break;
5370 default:
5371 break;
5372 }
60637aac 5373 }
37817f29
IE		 5374 tss_selector = exit_qualification;
5375
64a7ec06
GN		 5376 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5377 type != INTR_TYPE_EXT_INTR &&
5378 type != INTR_TYPE_NMI_INTR))
5379 skip_emulated_instruction(vcpu);
5380
7f3d35fd
KW		 5381 if (kvm_task_switch(vcpu, tss_selector,
5382 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5383 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5384 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5385 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5386 vcpu->run->internal.ndata = 0;
42dbaa5a 5387 return 0;
acb54517 5388 }
42dbaa5a
JK		 5389
5390 /* clear all local breakpoint enable flags */
5391 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5392
5393 /*
5394 * TODO: What about debug traps on tss switch?
5395 * Are we supposed to inject them and update dr6?
5396 */
5397
5398 return 1;
37817f29
IE		 5399}
5400
851ba692 5401static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5402{
f9c617f6 5403 unsigned long exit_qualification;
1439442c 5404 gpa_t gpa;
4f5982a5 5405 u32 error_code;
1439442c 5406 int gla_validity;
1439442c 5407
f9c617f6 5408 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5409
1439442c
SY		 5410 gla_validity = (exit_qualification >> 7) & 0x3;
5411 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5412 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5413 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5414 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5415 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5416 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5417 (long unsigned int)exit_qualification);
851ba692
AK		 5418 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5419 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5420 return 0;
1439442c
SY		 5421 }
5422
0be9c7a8
GN		 5423 /*
5424 * EPT violation happened while executing iret from NMI,
5425 * "blocked by NMI" bit has to be set before next VM entry.
5426 * There are errata that may cause this bit to not be set:
5427 * AAK134, BY25.
5428 */
bcd1c294
GN		 5429 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5430 cpu_has_virtual_nmis() &&
5431 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5432 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5433
1439442c 5434 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5435 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5436
5437 /* It is a write fault? */
5438 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5439 /* It is a fetch fault? */
5440 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5441 /* ept page table is present? */
5442 error_code |= (exit_qualification >> 3) & 0x1;
5443
25d92081
YZ		 5444 vcpu->arch.exit_qualification = exit_qualification;
5445
4f5982a5 5446 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5447}
5448
68f89400
MT		 5449static u64 ept_rsvd_mask(u64 spte, int level)
5450{
5451 int i;
5452 u64 mask = 0;
5453
5454 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5455 mask |= (1ULL << i);
5456
5457 if (level > 2)
5458 /* bits 7:3 reserved */
5459 mask |= 0xf8;
5460 else if (level == 2) {
5461 if (spte & (1ULL << 7))
5462 /* 2MB ref, bits 20:12 reserved */
5463 mask |= 0x1ff000;
5464 else
5465 /* bits 6:3 reserved */
5466 mask |= 0x78;
5467 }
5468
5469 return mask;
5470}
5471
5472static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5473 int level)
5474{
5475 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5476
5477 /* 010b (write-only) */
5478 WARN_ON((spte & 0x7) == 0x2);
5479
5480 /* 110b (write/execute) */
5481 WARN_ON((spte & 0x7) == 0x6);
5482
5483 /* 100b (execute-only) and value not supported by logical processor */
5484 if (!cpu_has_vmx_ept_execute_only())
5485 WARN_ON((spte & 0x7) == 0x4);
5486
5487 /* not 000b */
5488 if ((spte & 0x7)) {
5489 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5490
5491 if (rsvd_bits != 0) {
5492 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5493 __func__, rsvd_bits);
5494 WARN_ON(1);
5495 }
5496
5497 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5498 u64 ept_mem_type = (spte & 0x38) >> 3;
5499
5500 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5501 ept_mem_type == 7) {
5502 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5503 __func__, ept_mem_type);
5504 WARN_ON(1);
5505 }
5506 }
5507 }
5508}
5509
851ba692 5510static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5511{
5512 u64 sptes[4];
ce88decf 5513 int nr_sptes, i, ret;
68f89400
MT		 5514 gpa_t gpa;
5515
5516 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5517
ce88decf 5518 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5519 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5520 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5521 EMULATE_DONE;
f8f55942
XG		 5522
5523 if (unlikely(ret == RET_MMIO_PF_INVALID))
5524 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5525
b37fbea6 5526 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5527 return 1;
5528
5529 /* It is the real ept misconfig */
68f89400
MT		 5530 printk(KERN_ERR "EPT: Misconfiguration.\n");
5531 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5532
5533 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5534
5535 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5536 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5537
851ba692
AK		 5538 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5539 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5540
5541 return 0;
5542}
5543
851ba692 5544static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5545{
5546 u32 cpu_based_vm_exec_control;
5547
5548 /* clear pending NMI */
5549 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5550 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5551 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5552 ++vcpu->stat.nmi_window_exits;
3842d135 5553 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5554
5555 return 1;
5556}
5557
80ced186 5558static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5559{
8b3079a5
AK		 5560 struct vcpu_vmx *vmx = to_vmx(vcpu);
5561 enum emulation_result err = EMULATE_DONE;
80ced186 5562 int ret = 1;
49e9d557
AK		 5563 u32 cpu_exec_ctrl;
5564 bool intr_window_requested;
b8405c18 5565 unsigned count = 130;
49e9d557
AK		 5566
5567 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5568 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5569
b8405c18 5570 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5571 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5572 return handle_interrupt_window(&vmx->vcpu);
5573
de87dcdd
AK		 5574 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5575 return 1;
5576
991eebf9 5577 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5578
ac0a48c3 5579 if (err == EMULATE_USER_EXIT) {
94452b9e 5580 ++vcpu->stat.mmio_exits;
80ced186
MG		 5581 ret = 0;
5582 goto out;
5583 }
1d5a4d9b 5584
de5f70e0
AK		 5585 if (err != EMULATE_DONE) {
5586 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5587 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5588 vcpu->run->internal.ndata = 0;
6d77dbfc 5589 return 0;
de5f70e0 5590 }
ea953ef0 5591
8d76c49e
GN		 5592 if (vcpu->arch.halt_request) {
5593 vcpu->arch.halt_request = 0;
5594 ret = kvm_emulate_halt(vcpu);
5595 goto out;
5596 }
5597
ea953ef0 5598 if (signal_pending(current))
80ced186 5599 goto out;
ea953ef0
MG		 5600 if (need_resched())
5601 schedule();
5602 }
5603
14168786 5604 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5605out:
5606 return ret;
ea953ef0
MG		 5607}
5608
4b8d54f9
ZE		 5609/*
5610 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5611 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5612 */
9fb41ba8 5613static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5614{
5615 skip_emulated_instruction(vcpu);
5616 kvm_vcpu_on_spin(vcpu);
5617
5618 return 1;
5619}
5620
59708670
SY		 5621static int handle_invalid_op(struct kvm_vcpu *vcpu)
5622{
5623 kvm_queue_exception(vcpu, UD_VECTOR);
5624 return 1;
5625}
5626
ff2f6fe9
NHE		 5627/*
5628 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5629 * We could reuse a single VMCS for all the L2 guests, but we also want the
5630 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5631 * allows keeping them loaded on the processor, and in the future will allow
5632 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5633 * every entry if they never change.
5634 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5635 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5636 *
5637 * The following functions allocate and free a vmcs02 in this pool.
5638 */
5639
5640/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5641static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5642{
5643 struct vmcs02_list *item;
5644 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5645 if (item->vmptr == vmx->nested.current_vmptr) {
5646 list_move(&item->list, &vmx->nested.vmcs02_pool);
5647 return &item->vmcs02;
5648 }
5649
5650 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5651 /* Recycle the least recently used VMCS. */
5652 item = list_entry(vmx->nested.vmcs02_pool.prev,
5653 struct vmcs02_list, list);
5654 item->vmptr = vmx->nested.current_vmptr;
5655 list_move(&item->list, &vmx->nested.vmcs02_pool);
5656 return &item->vmcs02;
5657 }
5658
5659 /* Create a new VMCS */
0fa24ce3 5660 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5661 if (!item)
5662 return NULL;
5663 item->vmcs02.vmcs = alloc_vmcs();
5664 if (!item->vmcs02.vmcs) {
5665 kfree(item);
5666 return NULL;
5667 }
5668 loaded_vmcs_init(&item->vmcs02);
5669 item->vmptr = vmx->nested.current_vmptr;
5670 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5671 vmx->nested.vmcs02_num++;
5672 return &item->vmcs02;
5673}
5674
5675/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5676static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5677{
5678 struct vmcs02_list *item;
5679 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5680 if (item->vmptr == vmptr) {
5681 free_loaded_vmcs(&item->vmcs02);
5682 list_del(&item->list);
5683 kfree(item);
5684 vmx->nested.vmcs02_num--;
5685 return;
5686 }
5687}
5688
5689/*
5690 * Free all VMCSs saved for this vcpu, except the one pointed by
5691 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5692 * currently used, if running L2), and vmcs01 when running L2.
5693 */
5694static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5695{
5696 struct vmcs02_list *item, *n;
5697 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5698 if (vmx->loaded_vmcs != &item->vmcs02)
5699 free_loaded_vmcs(&item->vmcs02);
5700 list_del(&item->list);
5701 kfree(item);
5702 }
5703 vmx->nested.vmcs02_num = 0;
5704
5705 if (vmx->loaded_vmcs != &vmx->vmcs01)
5706 free_loaded_vmcs(&vmx->vmcs01);
5707}
5708
0658fbaa
ACL		 5709/*
5710 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5711 * set the success or error code of an emulated VMX instruction, as specified
5712 * by Vol 2B, VMX Instruction Reference, "Conventions".
5713 */
5714static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5715{
5716 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5717 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5718 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5719}
5720
5721static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5722{
5723 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5724 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5725 X86_EFLAGS_SF | X86_EFLAGS_OF))
5726 | X86_EFLAGS_CF);
5727}
5728
145c28dd 5729static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5730 u32 vm_instruction_error)
5731{
5732 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5733 /*
5734 * failValid writes the error number to the current VMCS, which
5735 * can't be done there isn't a current VMCS.
5736 */
5737 nested_vmx_failInvalid(vcpu);
5738 return;
5739 }
5740 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5741 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5742 X86_EFLAGS_SF | X86_EFLAGS_OF))
5743 | X86_EFLAGS_ZF);
5744 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5745 /*
5746 * We don't need to force a shadow sync because
5747 * VM_INSTRUCTION_ERROR is not shadowed
5748 */
5749}
145c28dd 5750
f4124500
JK		 5751static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5752{
5753 struct vcpu_vmx *vmx =
5754 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5755
5756 vmx->nested.preemption_timer_expired = true;
5757 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5758 kvm_vcpu_kick(&vmx->vcpu);
5759
5760 return HRTIMER_NORESTART;
5761}
5762
ec378aee
NHE		 5763/*
5764 * Emulate the VMXON instruction.
5765 * Currently, we just remember that VMX is active, and do not save or even
5766 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5767 * do not currently need to store anything in that guest-allocated memory
5768 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5769 * argument is different from the VMXON pointer (which the spec says they do).
5770 */
5771static int handle_vmon(struct kvm_vcpu *vcpu)
5772{
5773 struct kvm_segment cs;
5774 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5775 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5776 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5777 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5778
5779 /* The Intel VMX Instruction Reference lists a bunch of bits that
5780 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5781 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5782 * Otherwise, we should fail with #UD. We test these now:
5783 */
5784 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5785 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5786 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5787 kvm_queue_exception(vcpu, UD_VECTOR);
5788 return 1;
5789 }
5790
5791 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5792 if (is_long_mode(vcpu) && !cs.l) {
5793 kvm_queue_exception(vcpu, UD_VECTOR);
5794 return 1;
5795 }
5796
5797 if (vmx_get_cpl(vcpu)) {
5798 kvm_inject_gp(vcpu, 0);
5799 return 1;
5800 }
145c28dd
AG		 5801 if (vmx->nested.vmxon) {
5802 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5803 skip_emulated_instruction(vcpu);
5804 return 1;
5805 }
b3897a49
NHE		 5806
5807 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5808 != VMXON_NEEDED_FEATURES) {
5809 kvm_inject_gp(vcpu, 0);
5810 return 1;
5811 }
5812
8de48833
AG		 5813 if (enable_shadow_vmcs) {
5814 shadow_vmcs = alloc_vmcs();
5815 if (!shadow_vmcs)
5816 return -ENOMEM;
5817 /* mark vmcs as shadow */
5818 shadow_vmcs->revision_id |= (1u << 31);
5819 /* init shadow vmcs */
5820 vmcs_clear(shadow_vmcs);
5821 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5822 }
ec378aee 5823
ff2f6fe9
NHE		 5824 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5825 vmx->nested.vmcs02_num = 0;
5826
f4124500
JK		 5827 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
5828 HRTIMER_MODE_REL);
5829 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
5830
ec378aee
NHE		 5831 vmx->nested.vmxon = true;
5832
5833 skip_emulated_instruction(vcpu);
a25eb114 5834 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5835 return 1;
5836}
5837
5838/*
5839 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5840 * for running VMX instructions (except VMXON, whose prerequisites are
5841 * slightly different). It also specifies what exception to inject otherwise.
5842 */
5843static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5844{
5845 struct kvm_segment cs;
5846 struct vcpu_vmx *vmx = to_vmx(vcpu);
5847
5848 if (!vmx->nested.vmxon) {
5849 kvm_queue_exception(vcpu, UD_VECTOR);
5850 return 0;
5851 }
5852
5853 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5854 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5855 (is_long_mode(vcpu) && !cs.l)) {
5856 kvm_queue_exception(vcpu, UD_VECTOR);
5857 return 0;
5858 }
5859
5860 if (vmx_get_cpl(vcpu)) {
5861 kvm_inject_gp(vcpu, 0);
5862 return 0;
5863 }
5864
5865 return 1;
5866}
5867
e7953d7f
AG		 5868static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5869{
8a1b9dd0 5870 u32 exec_control;
012f83cb
AG		 5871 if (enable_shadow_vmcs) {
5872 if (vmx->nested.current_vmcs12 != NULL) {
5873 /* copy to memory all shadowed fields in case
5874 they were modified */
5875 copy_shadow_to_vmcs12(vmx);
5876 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5877 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5878 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5879 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5880 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5881 }
5882 }
e7953d7f
AG		 5883 kunmap(vmx->nested.current_vmcs12_page);
5884 nested_release_page(vmx->nested.current_vmcs12_page);
5885}
5886
ec378aee
NHE		 5887/*
5888 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5889 * just stops using VMX.
5890 */
5891static void free_nested(struct vcpu_vmx *vmx)
5892{
5893 if (!vmx->nested.vmxon)
5894 return;
5895 vmx->nested.vmxon = false;
a9d30f33 5896 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5897 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5898 vmx->nested.current_vmptr = -1ull;
5899 vmx->nested.current_vmcs12 = NULL;
5900 }
e7953d7f
AG		 5901 if (enable_shadow_vmcs)
5902 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5903 /* Unpin physical memory we referred to in current vmcs02 */
5904 if (vmx->nested.apic_access_page) {
5905 nested_release_page(vmx->nested.apic_access_page);
5906 vmx->nested.apic_access_page = 0;
5907 }
ff2f6fe9
NHE		 5908
5909 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5910}
5911
5912/* Emulate the VMXOFF instruction */
5913static int handle_vmoff(struct kvm_vcpu *vcpu)
5914{
5915 if (!nested_vmx_check_permission(vcpu))
5916 return 1;
5917 free_nested(to_vmx(vcpu));
5918 skip_emulated_instruction(vcpu);
a25eb114 5919 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5920 return 1;
5921}
5922
064aea77
NHE		 5923/*
5924 * Decode the memory-address operand of a vmx instruction, as recorded on an
5925 * exit caused by such an instruction (run by a guest hypervisor).
5926 * On success, returns 0. When the operand is invalid, returns 1 and throws
5927 * #UD or #GP.
5928 */
5929static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5930 unsigned long exit_qualification,
5931 u32 vmx_instruction_info, gva_t *ret)
5932{
5933 /*
5934 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5935 * Execution", on an exit, vmx_instruction_info holds most of the
5936 * addressing components of the operand. Only the displacement part
5937 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5938 * For how an actual address is calculated from all these components,
5939 * refer to Vol. 1, "Operand Addressing".
5940 */
5941 int scaling = vmx_instruction_info & 3;
5942 int addr_size = (vmx_instruction_info >> 7) & 7;
5943 bool is_reg = vmx_instruction_info & (1u << 10);
5944 int seg_reg = (vmx_instruction_info >> 15) & 7;
5945 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5946 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5947 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5948 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5949
5950 if (is_reg) {
5951 kvm_queue_exception(vcpu, UD_VECTOR);
5952 return 1;
5953 }
5954
5955 /* Addr = segment_base + offset */
5956 /* offset = base + [index * scale] + displacement */
5957 *ret = vmx_get_segment_base(vcpu, seg_reg);
5958 if (base_is_valid)
5959 *ret += kvm_register_read(vcpu, base_reg);
5960 if (index_is_valid)
5961 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5962 *ret += exit_qualification; /* holds the displacement */
5963
5964 if (addr_size == 1) /* 32 bit */
5965 *ret &= 0xffffffff;
5966
5967 /*
5968 * TODO: throw #GP (and return 1) in various cases that the VM*
5969 * instructions require it - e.g., offset beyond segment limit,
5970 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5971 * address, and so on. Currently these are not checked.
5972 */
5973 return 0;
5974}
5975
27d6c865
NHE		 5976/* Emulate the VMCLEAR instruction */
5977static int handle_vmclear(struct kvm_vcpu *vcpu)
5978{
5979 struct vcpu_vmx *vmx = to_vmx(vcpu);
5980 gva_t gva;
5981 gpa_t vmptr;
5982 struct vmcs12 *vmcs12;
5983 struct page *page;
5984 struct x86_exception e;
5985
5986 if (!nested_vmx_check_permission(vcpu))
5987 return 1;
5988
5989 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5990 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5991 return 1;
5992
5993 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5994 sizeof(vmptr), &e)) {
5995 kvm_inject_page_fault(vcpu, &e);
5996 return 1;
5997 }
5998
5999 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6000 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
6001 skip_emulated_instruction(vcpu);
6002 return 1;
6003 }
6004
6005 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6006 nested_release_vmcs12(vmx);
27d6c865
NHE		 6007 vmx->nested.current_vmptr = -1ull;
6008 vmx->nested.current_vmcs12 = NULL;
6009 }
6010
6011 page = nested_get_page(vcpu, vmptr);
6012 if (page == NULL) {
6013 /*
6014 * For accurate processor emulation, VMCLEAR beyond available
6015 * physical memory should do nothing at all. However, it is
6016 * possible that a nested vmx bug, not a guest hypervisor bug,
6017 * resulted in this case, so let's shut down before doing any
6018 * more damage:
6019 */
6020 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6021 return 1;
6022 }
6023 vmcs12 = kmap(page);
6024 vmcs12->launch_state = 0;
6025 kunmap(page);
6026 nested_release_page(page);
6027
6028 nested_free_vmcs02(vmx, vmptr);
6029
6030 skip_emulated_instruction(vcpu);
6031 nested_vmx_succeed(vcpu);
6032 return 1;
6033}
6034
cd232ad0
NHE		 6035static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6036
6037/* Emulate the VMLAUNCH instruction */
6038static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6039{
6040 return nested_vmx_run(vcpu, true);
6041}
6042
6043/* Emulate the VMRESUME instruction */
6044static int handle_vmresume(struct kvm_vcpu *vcpu)
6045{
6046
6047 return nested_vmx_run(vcpu, false);
6048}
6049
49f705c5
NHE		 6050enum vmcs_field_type {
6051 VMCS_FIELD_TYPE_U16 = 0,
6052 VMCS_FIELD_TYPE_U64 = 1,
6053 VMCS_FIELD_TYPE_U32 = 2,
6054 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6055};
6056
6057static inline int vmcs_field_type(unsigned long field)
6058{
6059 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6060 return VMCS_FIELD_TYPE_U32;
6061 return (field >> 13) & 0x3 ;
6062}
6063
6064static inline int vmcs_field_readonly(unsigned long field)
6065{
6066 return (((field >> 10) & 0x3) == 1);
6067}
6068
6069/*
6070 * Read a vmcs12 field. Since these can have varying lengths and we return
6071 * one type, we chose the biggest type (u64) and zero-extend the return value
6072 * to that size. Note that the caller, handle_vmread, might need to use only
6073 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6074 * 64-bit fields are to be returned).
6075 */
6076static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6077 unsigned long field, u64 *ret)
6078{
6079 short offset = vmcs_field_to_offset(field);
6080 char *p;
6081
6082 if (offset < 0)
6083 return 0;
6084
6085 p = ((char *)(get_vmcs12(vcpu))) + offset;
6086
6087 switch (vmcs_field_type(field)) {
6088 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6089 *ret = *((natural_width *)p);
6090 return 1;
6091 case VMCS_FIELD_TYPE_U16:
6092 *ret = *((u16 *)p);
6093 return 1;
6094 case VMCS_FIELD_TYPE_U32:
6095 *ret = *((u32 *)p);
6096 return 1;
6097 case VMCS_FIELD_TYPE_U64:
6098 *ret = *((u64 *)p);
6099 return 1;
6100 default:
6101 return 0; /* can never happen. */
6102 }
6103}
6104
20b97fea
AG		 6105
6106static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6107 unsigned long field, u64 field_value){
6108 short offset = vmcs_field_to_offset(field);
6109 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6110 if (offset < 0)
6111 return false;
6112
6113 switch (vmcs_field_type(field)) {
6114 case VMCS_FIELD_TYPE_U16:
6115 *(u16 *)p = field_value;
6116 return true;
6117 case VMCS_FIELD_TYPE_U32:
6118 *(u32 *)p = field_value;
6119 return true;
6120 case VMCS_FIELD_TYPE_U64:
6121 *(u64 *)p = field_value;
6122 return true;
6123 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6124 *(natural_width *)p = field_value;
6125 return true;
6126 default:
6127 return false; /* can never happen. */
6128 }
6129
6130}
6131
16f5b903
AG		 6132static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6133{
6134 int i;
6135 unsigned long field;
6136 u64 field_value;
6137 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6138 const unsigned long *fields = shadow_read_write_fields;
6139 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6140
6141 vmcs_load(shadow_vmcs);
6142
6143 for (i = 0; i < num_fields; i++) {
6144 field = fields[i];
6145 switch (vmcs_field_type(field)) {
6146 case VMCS_FIELD_TYPE_U16:
6147 field_value = vmcs_read16(field);
6148 break;
6149 case VMCS_FIELD_TYPE_U32:
6150 field_value = vmcs_read32(field);
6151 break;
6152 case VMCS_FIELD_TYPE_U64:
6153 field_value = vmcs_read64(field);
6154 break;
6155 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6156 field_value = vmcs_readl(field);
6157 break;
6158 }
6159 vmcs12_write_any(&vmx->vcpu, field, field_value);
6160 }
6161
6162 vmcs_clear(shadow_vmcs);
6163 vmcs_load(vmx->loaded_vmcs->vmcs);
6164}
6165
c3114420
AG		 6166static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6167{
c2bae893
MK		 6168 const unsigned long *fields[] = {
6169 shadow_read_write_fields,
6170 shadow_read_only_fields
c3114420 6171 };
c2bae893 6172 const int max_fields[] = {
c3114420
AG		 6173 max_shadow_read_write_fields,
6174 max_shadow_read_only_fields
6175 };
6176 int i, q;
6177 unsigned long field;
6178 u64 field_value = 0;
6179 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6180
6181 vmcs_load(shadow_vmcs);
6182
c2bae893 6183 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6184 for (i = 0; i < max_fields[q]; i++) {
6185 field = fields[q][i];
6186 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6187
6188 switch (vmcs_field_type(field)) {
6189 case VMCS_FIELD_TYPE_U16:
6190 vmcs_write16(field, (u16)field_value);
6191 break;
6192 case VMCS_FIELD_TYPE_U32:
6193 vmcs_write32(field, (u32)field_value);
6194 break;
6195 case VMCS_FIELD_TYPE_U64:
6196 vmcs_write64(field, (u64)field_value);
6197 break;
6198 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6199 vmcs_writel(field, (long)field_value);
6200 break;
6201 }
6202 }
6203 }
6204
6205 vmcs_clear(shadow_vmcs);
6206 vmcs_load(vmx->loaded_vmcs->vmcs);
6207}
6208
49f705c5
NHE		 6209/*
6210 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6211 * used before) all generate the same failure when it is missing.
6212 */
6213static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6214{
6215 struct vcpu_vmx *vmx = to_vmx(vcpu);
6216 if (vmx->nested.current_vmptr == -1ull) {
6217 nested_vmx_failInvalid(vcpu);
6218 skip_emulated_instruction(vcpu);
6219 return 0;
6220 }
6221 return 1;
6222}
6223
6224static int handle_vmread(struct kvm_vcpu *vcpu)
6225{
6226 unsigned long field;
6227 u64 field_value;
6228 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6229 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6230 gva_t gva = 0;
6231
6232 if (!nested_vmx_check_permission(vcpu) ||
6233 !nested_vmx_check_vmcs12(vcpu))
6234 return 1;
6235
6236 /* Decode instruction info and find the field to read */
6237 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6238 /* Read the field, zero-extended to a u64 field_value */
6239 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6240 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6241 skip_emulated_instruction(vcpu);
6242 return 1;
6243 }
6244 /*
6245 * Now copy part of this value to register or memory, as requested.
6246 * Note that the number of bits actually copied is 32 or 64 depending
6247 * on the guest's mode (32 or 64 bit), not on the given field's length.
6248 */
6249 if (vmx_instruction_info & (1u << 10)) {
6250 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6251 field_value);
6252 } else {
6253 if (get_vmx_mem_address(vcpu, exit_qualification,
6254 vmx_instruction_info, &gva))
6255 return 1;
6256 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6257 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6258 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6259 }
6260
6261 nested_vmx_succeed(vcpu);
6262 skip_emulated_instruction(vcpu);
6263 return 1;
6264}
6265
6266
6267static int handle_vmwrite(struct kvm_vcpu *vcpu)
6268{
6269 unsigned long field;
6270 gva_t gva;
6271 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6272 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6273 /* The value to write might be 32 or 64 bits, depending on L1's long
6274 * mode, and eventually we need to write that into a field of several
6275 * possible lengths. The code below first zero-extends the value to 64
6276 * bit (field_value), and then copies only the approriate number of
6277 * bits into the vmcs12 field.
6278 */
6279 u64 field_value = 0;
6280 struct x86_exception e;
6281
6282 if (!nested_vmx_check_permission(vcpu) ||
6283 !nested_vmx_check_vmcs12(vcpu))
6284 return 1;
6285
6286 if (vmx_instruction_info & (1u << 10))
6287 field_value = kvm_register_read(vcpu,
6288 (((vmx_instruction_info) >> 3) & 0xf));
6289 else {
6290 if (get_vmx_mem_address(vcpu, exit_qualification,
6291 vmx_instruction_info, &gva))
6292 return 1;
6293 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6294 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6295 kvm_inject_page_fault(vcpu, &e);
6296 return 1;
6297 }
6298 }
6299
6300
6301 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6302 if (vmcs_field_readonly(field)) {
6303 nested_vmx_failValid(vcpu,
6304 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6305 skip_emulated_instruction(vcpu);
6306 return 1;
6307 }
6308
20b97fea 6309 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6310 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6311 skip_emulated_instruction(vcpu);
6312 return 1;
6313 }
6314
6315 nested_vmx_succeed(vcpu);
6316 skip_emulated_instruction(vcpu);
6317 return 1;
6318}
6319
63846663
NHE		 6320/* Emulate the VMPTRLD instruction */
6321static int handle_vmptrld(struct kvm_vcpu *vcpu)
6322{
6323 struct vcpu_vmx *vmx = to_vmx(vcpu);
6324 gva_t gva;
6325 gpa_t vmptr;
6326 struct x86_exception e;
8a1b9dd0 6327 u32 exec_control;
63846663
NHE		 6328
6329 if (!nested_vmx_check_permission(vcpu))
6330 return 1;
6331
6332 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6333 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6334 return 1;
6335
6336 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6337 sizeof(vmptr), &e)) {
6338 kvm_inject_page_fault(vcpu, &e);
6339 return 1;
6340 }
6341
6342 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6343 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6344 skip_emulated_instruction(vcpu);
6345 return 1;
6346 }
6347
6348 if (vmx->nested.current_vmptr != vmptr) {
6349 struct vmcs12 *new_vmcs12;
6350 struct page *page;
6351 page = nested_get_page(vcpu, vmptr);
6352 if (page == NULL) {
6353 nested_vmx_failInvalid(vcpu);
6354 skip_emulated_instruction(vcpu);
6355 return 1;
6356 }
6357 new_vmcs12 = kmap(page);
6358 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6359 kunmap(page);
6360 nested_release_page_clean(page);
6361 nested_vmx_failValid(vcpu,
6362 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6363 skip_emulated_instruction(vcpu);
6364 return 1;
6365 }
e7953d7f
AG		 6366 if (vmx->nested.current_vmptr != -1ull)
6367 nested_release_vmcs12(vmx);
63846663
NHE		 6368
6369 vmx->nested.current_vmptr = vmptr;
6370 vmx->nested.current_vmcs12 = new_vmcs12;
6371 vmx->nested.current_vmcs12_page = page;
012f83cb 6372 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6373 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6374 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6375 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6376 vmcs_write64(VMCS_LINK_POINTER,
6377 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6378 vmx->nested.sync_shadow_vmcs = true;
6379 }
63846663
NHE		 6380 }
6381
6382 nested_vmx_succeed(vcpu);
6383 skip_emulated_instruction(vcpu);
6384 return 1;
6385}
6386
6a4d7550
NHE		 6387/* Emulate the VMPTRST instruction */
6388static int handle_vmptrst(struct kvm_vcpu *vcpu)
6389{
6390 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6391 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6392 gva_t vmcs_gva;
6393 struct x86_exception e;
6394
6395 if (!nested_vmx_check_permission(vcpu))
6396 return 1;
6397
6398 if (get_vmx_mem_address(vcpu, exit_qualification,
6399 vmx_instruction_info, &vmcs_gva))
6400 return 1;
6401 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6402 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6403 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6404 sizeof(u64), &e)) {
6405 kvm_inject_page_fault(vcpu, &e);
6406 return 1;
6407 }
6408 nested_vmx_succeed(vcpu);
6409 skip_emulated_instruction(vcpu);
6410 return 1;
6411}
6412
bfd0a56b
NHE		 6413/* Emulate the INVEPT instruction */
6414static int handle_invept(struct kvm_vcpu *vcpu)
6415{
6416 u32 vmx_instruction_info, types;
6417 unsigned long type;
6418 gva_t gva;
6419 struct x86_exception e;
6420 struct {
6421 u64 eptp, gpa;
6422 } operand;
6423 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6424
6425 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6426 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6427 kvm_queue_exception(vcpu, UD_VECTOR);
6428 return 1;
6429 }
6430
6431 if (!nested_vmx_check_permission(vcpu))
6432 return 1;
6433
6434 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6435 kvm_queue_exception(vcpu, UD_VECTOR);
6436 return 1;
6437 }
6438
6439 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6440 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6441
6442 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6443
6444 if (!(types & (1UL << type))) {
6445 nested_vmx_failValid(vcpu,
6446 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6447 return 1;
6448 }
6449
6450 /* According to the Intel VMX instruction reference, the memory
6451 * operand is read even if it isn't needed (e.g., for type==global)
6452 */
6453 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6454 vmx_instruction_info, &gva))
6455 return 1;
6456 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6457 sizeof(operand), &e)) {
6458 kvm_inject_page_fault(vcpu, &e);
6459 return 1;
6460 }
6461
6462 switch (type) {
6463 case VMX_EPT_EXTENT_CONTEXT:
6464 if ((operand.eptp & eptp_mask) !=
6465 (nested_ept_get_cr3(vcpu) & eptp_mask))
6466 break;
6467 case VMX_EPT_EXTENT_GLOBAL:
6468 kvm_mmu_sync_roots(vcpu);
6469 kvm_mmu_flush_tlb(vcpu);
6470 nested_vmx_succeed(vcpu);
6471 break;
6472 default:
6473 BUG_ON(1);
6474 break;
6475 }
6476
6477 skip_emulated_instruction(vcpu);
6478 return 1;
6479}
6480
6aa8b732
AK		 6481/*
6482 * The exit handlers return 1 if the exit was handled fully and guest execution
6483 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6484 * to be done to userspace and return 0.
6485 */
772e0318 6486static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6487 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6488 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6489 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6490 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6491 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6492 [EXIT_REASON_CR_ACCESS] = handle_cr,
6493 [EXIT_REASON_DR_ACCESS] = handle_dr,
6494 [EXIT_REASON_CPUID] = handle_cpuid,
6495 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6496 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6497 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6498 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6499 [EXIT_REASON_INVD] = handle_invd,
a7052897 6500 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6501 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6502 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6503 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6504 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6505 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6506 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6507 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6508 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6509 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6510 [EXIT_REASON_VMOFF] = handle_vmoff,
6511 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6512 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6513 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6514 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6515 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6516 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6517 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6518 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6519 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6520 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6521 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6522 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6523 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6524 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6525 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6526};
6527
6528static const int kvm_vmx_max_exit_handlers =
50a3485c 6529 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6530
908a7bdd
JK		 6531static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6532 struct vmcs12 *vmcs12)
6533{
6534 unsigned long exit_qualification;
6535 gpa_t bitmap, last_bitmap;
6536 unsigned int port;
6537 int size;
6538 u8 b;
6539
908a7bdd 6540 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6541 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6542
6543 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6544
6545 port = exit_qualification >> 16;
6546 size = (exit_qualification & 7) + 1;
6547
6548 last_bitmap = (gpa_t)-1;
6549 b = -1;
6550
6551 while (size > 0) {
6552 if (port < 0x8000)
6553 bitmap = vmcs12->io_bitmap_a;
6554 else if (port < 0x10000)
6555 bitmap = vmcs12->io_bitmap_b;
6556 else
6557 return 1;
6558 bitmap += (port & 0x7fff) / 8;
6559
6560 if (last_bitmap != bitmap)
6561 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6562 return 1;
6563 if (b & (1 << (port & 7)))
6564 return 1;
6565
6566 port++;
6567 size--;
6568 last_bitmap = bitmap;
6569 }
6570
6571 return 0;
6572}
6573
644d711a
NHE		 6574/*
6575 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6576 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6577 * disinterest in the current event (read or write a specific MSR) by using an
6578 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6579 */
6580static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6581 struct vmcs12 *vmcs12, u32 exit_reason)
6582{
6583 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6584 gpa_t bitmap;
6585
cbd29cb6 6586 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6587 return 1;
6588
6589 /*
6590 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6591 * for the four combinations of read/write and low/high MSR numbers.
6592 * First we need to figure out which of the four to use:
6593 */
6594 bitmap = vmcs12->msr_bitmap;
6595 if (exit_reason == EXIT_REASON_MSR_WRITE)
6596 bitmap += 2048;
6597 if (msr_index >= 0xc0000000) {
6598 msr_index -= 0xc0000000;
6599 bitmap += 1024;
6600 }
6601
6602 /* Then read the msr_index'th bit from this bitmap: */
6603 if (msr_index < 1024*8) {
6604 unsigned char b;
bd31a7f5
JK		 6605 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6606 return 1;
644d711a
NHE		 6607 return 1 & (b >> (msr_index & 7));
6608 } else
6609 return 1; /* let L1 handle the wrong parameter */
6610}
6611
6612/*
6613 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6614 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6615 * intercept (via guest_host_mask etc.) the current event.
6616 */
6617static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6618 struct vmcs12 *vmcs12)
6619{
6620 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6621 int cr = exit_qualification & 15;
6622 int reg = (exit_qualification >> 8) & 15;
6623 unsigned long val = kvm_register_read(vcpu, reg);
6624
6625 switch ((exit_qualification >> 4) & 3) {
6626 case 0: /* mov to cr */
6627 switch (cr) {
6628 case 0:
6629 if (vmcs12->cr0_guest_host_mask &
6630 (val ^ vmcs12->cr0_read_shadow))
6631 return 1;
6632 break;
6633 case 3:
6634 if ((vmcs12->cr3_target_count >= 1 &&
6635 vmcs12->cr3_target_value0 == val) ||
6636 (vmcs12->cr3_target_count >= 2 &&
6637 vmcs12->cr3_target_value1 == val) ||
6638 (vmcs12->cr3_target_count >= 3 &&
6639 vmcs12->cr3_target_value2 == val) ||
6640 (vmcs12->cr3_target_count >= 4 &&
6641 vmcs12->cr3_target_value3 == val))
6642 return 0;
6643 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6644 return 1;
6645 break;
6646 case 4:
6647 if (vmcs12->cr4_guest_host_mask &
6648 (vmcs12->cr4_read_shadow ^ val))
6649 return 1;
6650 break;
6651 case 8:
6652 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6653 return 1;
6654 break;
6655 }
6656 break;
6657 case 2: /* clts */
6658 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6659 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6660 return 1;
6661 break;
6662 case 1: /* mov from cr */
6663 switch (cr) {
6664 case 3:
6665 if (vmcs12->cpu_based_vm_exec_control &
6666 CPU_BASED_CR3_STORE_EXITING)
6667 return 1;
6668 break;
6669 case 8:
6670 if (vmcs12->cpu_based_vm_exec_control &
6671 CPU_BASED_CR8_STORE_EXITING)
6672 return 1;
6673 break;
6674 }
6675 break;
6676 case 3: /* lmsw */
6677 /*
6678 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6679 * cr0. Other attempted changes are ignored, with no exit.
6680 */
6681 if (vmcs12->cr0_guest_host_mask & 0xe &
6682 (val ^ vmcs12->cr0_read_shadow))
6683 return 1;
6684 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6685 !(vmcs12->cr0_read_shadow & 0x1) &&
6686 (val & 0x1))
6687 return 1;
6688 break;
6689 }
6690 return 0;
6691}
6692
6693/*
6694 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6695 * should handle it ourselves in L0 (and then continue L2). Only call this
6696 * when in is_guest_mode (L2).
6697 */
6698static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6699{
644d711a
NHE		 6700 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6701 struct vcpu_vmx *vmx = to_vmx(vcpu);
6702 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6703 u32 exit_reason = vmx->exit_reason;
644d711a 6704
542060ea
JK		 6705 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6706 vmcs_readl(EXIT_QUALIFICATION),
6707 vmx->idt_vectoring_info,
6708 intr_info,
6709 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6710 KVM_ISA_VMX);
6711
644d711a
NHE		 6712 if (vmx->nested.nested_run_pending)
6713 return 0;
6714
6715 if (unlikely(vmx->fail)) {
bd80158a
JK		 6716 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6717 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6718 return 1;
6719 }
6720
6721 switch (exit_reason) {
6722 case EXIT_REASON_EXCEPTION_NMI:
6723 if (!is_exception(intr_info))
6724 return 0;
6725 else if (is_page_fault(intr_info))
6726 return enable_ept;
e504c909 6727 else if (is_no_device(intr_info) &&
ccf9844e 6728 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6729 return 0;
644d711a
NHE		 6730 return vmcs12->exception_bitmap &
6731 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6732 case EXIT_REASON_EXTERNAL_INTERRUPT:
6733 return 0;
6734 case EXIT_REASON_TRIPLE_FAULT:
6735 return 1;
6736 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6737 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6738 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6739 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6740 case EXIT_REASON_TASK_SWITCH:
6741 return 1;
6742 case EXIT_REASON_CPUID:
6743 return 1;
6744 case EXIT_REASON_HLT:
6745 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6746 case EXIT_REASON_INVD:
6747 return 1;
6748 case EXIT_REASON_INVLPG:
6749 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6750 case EXIT_REASON_RDPMC:
6751 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6752 case EXIT_REASON_RDTSC:
6753 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6754 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6755 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6756 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6757 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6758 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6759 case EXIT_REASON_INVEPT:
644d711a
NHE		 6760 /*
6761 * VMX instructions trap unconditionally. This allows L1 to
6762 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6763 */
6764 return 1;
6765 case EXIT_REASON_CR_ACCESS:
6766 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6767 case EXIT_REASON_DR_ACCESS:
6768 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6769 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6770 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6771 case EXIT_REASON_MSR_READ:
6772 case EXIT_REASON_MSR_WRITE:
6773 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6774 case EXIT_REASON_INVALID_STATE:
6775 return 1;
6776 case EXIT_REASON_MWAIT_INSTRUCTION:
6777 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6778 case EXIT_REASON_MONITOR_INSTRUCTION:
6779 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6780 case EXIT_REASON_PAUSE_INSTRUCTION:
6781 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6782 nested_cpu_has2(vmcs12,
6783 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6784 case EXIT_REASON_MCE_DURING_VMENTRY:
6785 return 0;
6786 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6787 return 1;
6788 case EXIT_REASON_APIC_ACCESS:
6789 return nested_cpu_has2(vmcs12,
6790 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6791 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6792 /*
6793 * L0 always deals with the EPT violation. If nested EPT is
6794 * used, and the nested mmu code discovers that the address is
6795 * missing in the guest EPT table (EPT12), the EPT violation
6796 * will be injected with nested_ept_inject_page_fault()
6797 */
6798 return 0;
644d711a 6799 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6800 /*
6801 * L2 never uses directly L1's EPT, but rather L0's own EPT
6802 * table (shadow on EPT) or a merged EPT table that L0 built
6803 * (EPT on EPT). So any problems with the structure of the
6804 * table is L0's fault.
6805 */
644d711a
NHE		 6806 return 0;
6807 case EXIT_REASON_WBINVD:
6808 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6809 case EXIT_REASON_XSETBV:
6810 return 1;
6811 default:
6812 return 1;
6813 }
6814}
6815
586f9607
AK		 6816static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6817{
6818 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6819 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6820}
6821
6aa8b732
AK		 6822/*
6823 * The guest has exited. See if we can fix it or if we need userspace
6824 * assistance.
6825 */
851ba692 6826static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6827{
29bd8a78 6828 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6829 u32 exit_reason = vmx->exit_reason;
1155f76a 6830 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6831
80ced186 6832 /* If guest state is invalid, start emulating */
14168786 6833 if (vmx->emulation_required)
80ced186 6834 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6835
644d711a 6836 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6837 nested_vmx_vmexit(vcpu, exit_reason,
6838 vmcs_read32(VM_EXIT_INTR_INFO),
6839 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6840 return 1;
6841 }
6842
5120702e
MG		 6843 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6844 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6845 vcpu->run->fail_entry.hardware_entry_failure_reason
6846 = exit_reason;
6847 return 0;
6848 }
6849
29bd8a78 6850 if (unlikely(vmx->fail)) {
851ba692
AK		 6851 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6852 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6853 = vmcs_read32(VM_INSTRUCTION_ERROR);
6854 return 0;
6855 }
6aa8b732 6856
b9bf6882
XG		 6857 /*
6858 * Note:
6859 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6860 * delivery event since it indicates guest is accessing MMIO.
6861 * The vm-exit can be triggered again after return to guest that
6862 * will cause infinite loop.
6863 */
d77c26fc 6864 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6865 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6866 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6867 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6868 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6869 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6870 vcpu->run->internal.ndata = 2;
6871 vcpu->run->internal.data[0] = vectoring_info;
6872 vcpu->run->internal.data[1] = exit_reason;
6873 return 0;
6874 }
3b86cd99 6875
644d711a
NHE		 6876 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6877 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6878 get_vmcs12(vcpu))))) {
c4282df9 6879 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6880 vmx->soft_vnmi_blocked = 0;
3b86cd99 6881 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6882 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6883 /*
6884 * This CPU don't support us in finding the end of an
6885 * NMI-blocked window if the guest runs with IRQs
6886 * disabled. So we pull the trigger after 1 s of
6887 * futile waiting, but inform the user about this.
6888 */
6889 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6890 "state on VCPU %d after 1 s timeout\n",
6891 __func__, vcpu->vcpu_id);
6892 vmx->soft_vnmi_blocked = 0;
3b86cd99 6893 }
3b86cd99
JK		 6894 }
6895
6aa8b732
AK		 6896 if (exit_reason < kvm_vmx_max_exit_handlers
6897 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6898 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6899 else {
851ba692
AK		 6900 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6901 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6902 }
6903 return 0;
6904}
6905
95ba8273 6906static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6907{
95ba8273 6908 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6909 vmcs_write32(TPR_THRESHOLD, 0);
6910 return;
6911 }
6912
95ba8273 6913 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6914}
6915
8d14695f
YZ		 6916static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6917{
6918 u32 sec_exec_control;
6919
6920 /*
6921 * There is not point to enable virtualize x2apic without enable
6922 * apicv
6923 */
c7c9c56c
YZ		 6924 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6925 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6926 return;
6927
6928 if (!vm_need_tpr_shadow(vcpu->kvm))
6929 return;
6930
6931 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6932
6933 if (set) {
6934 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6935 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6936 } else {
6937 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6938 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6939 }
6940 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6941
6942 vmx_set_msr_bitmap(vcpu);
6943}
6944
c7c9c56c
YZ		 6945static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6946{
6947 u16 status;
6948 u8 old;
6949
6950 if (!vmx_vm_has_apicv(kvm))
6951 return;
6952
6953 if (isr == -1)
6954 isr = 0;
6955
6956 status = vmcs_read16(GUEST_INTR_STATUS);
6957 old = status >> 8;
6958 if (isr != old) {
6959 status &= 0xff;
6960 status |= isr << 8;
6961 vmcs_write16(GUEST_INTR_STATUS, status);
6962 }
6963}
6964
6965static void vmx_set_rvi(int vector)
6966{
6967 u16 status;
6968 u8 old;
6969
6970 status = vmcs_read16(GUEST_INTR_STATUS);
6971 old = (u8)status & 0xff;
6972 if ((u8)vector != old) {
6973 status &= ~0xff;
6974 status |= (u8)vector;
6975 vmcs_write16(GUEST_INTR_STATUS, status);
6976 }
6977}
6978
6979static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6980{
6981 if (max_irr == -1)
6982 return;
6983
6984 vmx_set_rvi(max_irr);
6985}
6986
6987static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6988{
3d81bc7e
YZ		 6989 if (!vmx_vm_has_apicv(vcpu->kvm))
6990 return;
6991
c7c9c56c
YZ		 6992 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6993 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6994 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6995 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6996}
6997
51aa01d1 6998static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6999{
00eba012
AK		 7000 u32 exit_intr_info;
7001
7002 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7003 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7004 return;
7005
c5ca8e57 7006 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7007 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7008
7009 /* Handle machine checks before interrupts are enabled */
00eba012 7010 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7011 kvm_machine_check();
7012
20f65983 7013 /* We need to handle NMIs before interrupts are enabled */
00eba012 7014 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7015 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7016 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7017 asm("int $2");
ff9d07a0
ZY		 7018 kvm_after_handle_nmi(&vmx->vcpu);
7019 }
51aa01d1 7020}
20f65983 7021
a547c6db
YZ		 7022static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7023{
7024 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7025
7026 /*
7027 * If external interrupt exists, IF bit is set in rflags/eflags on the
7028 * interrupt stack frame, and interrupt will be enabled on a return
7029 * from interrupt handler.
7030 */
7031 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7032 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7033 unsigned int vector;
7034 unsigned long entry;
7035 gate_desc *desc;
7036 struct vcpu_vmx *vmx = to_vmx(vcpu);
7037#ifdef CONFIG_X86_64
7038 unsigned long tmp;
7039#endif
7040
7041 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7042 desc = (gate_desc *)vmx->host_idt_base + vector;
7043 entry = gate_offset(*desc);
7044 asm volatile(
7045#ifdef CONFIG_X86_64
7046 "mov %%" _ASM_SP ", %[sp]\n\t"
7047 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7048 "push $%c[ss]\n\t"
7049 "push %[sp]\n\t"
7050#endif
7051 "pushf\n\t"
7052 "orl $0x200, (%%" _ASM_SP ")\n\t"
7053 __ASM_SIZE(push) " $%c[cs]\n\t"
7054 "call *%[entry]\n\t"
7055 :
7056#ifdef CONFIG_X86_64
7057 [sp]"=&r"(tmp)
7058#endif
7059 :
7060 [entry]"r"(entry),
7061 [ss]"i"(__KERNEL_DS),
7062 [cs]"i"(__KERNEL_CS)
7063 );
7064 } else
7065 local_irq_enable();
7066}
7067
da8999d3
LJ		 7068static bool vmx_mpx_supported(void)
7069{
7070 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7071 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7072}
7073
51aa01d1
AK		 7074static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7075{
c5ca8e57 7076 u32 exit_intr_info;
51aa01d1
AK		 7077 bool unblock_nmi;
7078 u8 vector;
7079 bool idtv_info_valid;
7080
7081 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7082
cf393f75 7083 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7084 if (vmx->nmi_known_unmasked)
7085 return;
c5ca8e57
AK		 7086 /*
7087 * Can't use vmx->exit_intr_info since we're not sure what
7088 * the exit reason is.
7089 */
7090 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7091 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7092 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7093 /*
7b4a25cb 7094 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7095 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7096 * a guest IRET fault.
7b4a25cb
GN		 7097 * SDM 3: 23.2.2 (September 2008)
7098 * Bit 12 is undefined in any of the following cases:
7099 * If the VM exit sets the valid bit in the IDT-vectoring
7100 * information field.
7101 * If the VM exit is due to a double fault.
cf393f75 7102 */
7b4a25cb
GN		 7103 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7104 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7105 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7106 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7107 else
7108 vmx->nmi_known_unmasked =
7109 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7110 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7111 } else if (unlikely(vmx->soft_vnmi_blocked))
7112 vmx->vnmi_blocked_time +=
7113 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7114}
7115
3ab66e8a 7116static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7117 u32 idt_vectoring_info,
7118 int instr_len_field,
7119 int error_code_field)
51aa01d1 7120{
51aa01d1
AK		 7121 u8 vector;
7122 int type;
7123 bool idtv_info_valid;
7124
7125 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7126
3ab66e8a
JK		 7127 vcpu->arch.nmi_injected = false;
7128 kvm_clear_exception_queue(vcpu);
7129 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7130
7131 if (!idtv_info_valid)
7132 return;
7133
3ab66e8a 7134 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7135
668f612f
AK		 7136 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7137 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7138
64a7ec06 7139 switch (type) {
37b96e98 7140 case INTR_TYPE_NMI_INTR:
3ab66e8a 7141 vcpu->arch.nmi_injected = true;
668f612f 7142 /*
7b4a25cb 7143 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7144 * Clear bit "block by NMI" before VM entry if a NMI
7145 * delivery faulted.
668f612f 7146 */
3ab66e8a 7147 vmx_set_nmi_mask(vcpu, false);
37b96e98 7148 break;
37b96e98 7149 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7150 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7151 /* fall through */
7152 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7153 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7154 u32 err = vmcs_read32(error_code_field);
851eb667 7155 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7156 } else
851eb667 7157 kvm_requeue_exception(vcpu, vector);
37b96e98 7158 break;
66fd3f7f 7159 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7160 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7161 /* fall through */
37b96e98 7162 case INTR_TYPE_EXT_INTR:
3ab66e8a 7163 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7164 break;
7165 default:
7166 break;
f7d9238f 7167 }
cf393f75
AK		 7168}
7169
83422e17
AK		 7170static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7171{
3ab66e8a 7172 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7173 VM_EXIT_INSTRUCTION_LEN,
7174 IDT_VECTORING_ERROR_CODE);
7175}
7176
b463a6f7
AK		 7177static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7178{
3ab66e8a 7179 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7180 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7181 VM_ENTRY_INSTRUCTION_LEN,
7182 VM_ENTRY_EXCEPTION_ERROR_CODE);
7183
7184 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7185}
7186
d7cd9796
GN		 7187static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7188{
7189 int i, nr_msrs;
7190 struct perf_guest_switch_msr *msrs;
7191
7192 msrs = perf_guest_get_msrs(&nr_msrs);
7193
7194 if (!msrs)
7195 return;
7196
7197 for (i = 0; i < nr_msrs; i++)
7198 if (msrs[i].host == msrs[i].guest)
7199 clear_atomic_switch_msr(vmx, msrs[i].msr);
7200 else
7201 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7202 msrs[i].host);
7203}
7204
a3b5ba49 7205static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7206{
a2fa3e9f 7207 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7208 unsigned long debugctlmsr;
104f226b
AK		 7209
7210 /* Record the guest's net vcpu time for enforced NMI injections. */
7211 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7212 vmx->entry_time = ktime_get();
7213
7214 /* Don't enter VMX if guest state is invalid, let the exit handler
7215 start emulation until we arrive back to a valid state */
14168786 7216 if (vmx->emulation_required)
104f226b
AK		 7217 return;
7218
012f83cb
AG		 7219 if (vmx->nested.sync_shadow_vmcs) {
7220 copy_vmcs12_to_shadow(vmx);
7221 vmx->nested.sync_shadow_vmcs = false;
7222 }
7223
104f226b
AK		 7224 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7225 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7226 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7227 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7228
7229 /* When single-stepping over STI and MOV SS, we must clear the
7230 * corresponding interruptibility bits in the guest state. Otherwise
7231 * vmentry fails as it then expects bit 14 (BS) in pending debug
7232 * exceptions being set, but that's not correct for the guest debugging
7233 * case. */
7234 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7235 vmx_set_interrupt_shadow(vcpu, 0);
7236
d7cd9796 7237 atomic_switch_perf_msrs(vmx);
2a7921b7 7238 debugctlmsr = get_debugctlmsr();
d7cd9796 7239
d462b819 7240 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7241 asm(
6aa8b732 7242 /* Store host registers */
b188c81f
AK		 7243 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7244 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7245 "push %%" _ASM_CX " \n\t"
7246 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7247 "je 1f \n\t"
b188c81f 7248 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7249 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7250 "1: \n\t"
d3edefc0 7251 /* Reload cr2 if changed */
b188c81f
AK		 7252 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7253 "mov %%cr2, %%" _ASM_DX " \n\t"
7254 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7255 "je 2f \n\t"
b188c81f 7256 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7257 "2: \n\t"
6aa8b732 7258 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7259 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7260 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7261 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7262 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7263 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7264 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7265 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7266 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7267#ifdef CONFIG_X86_64
e08aa78a
AK		 7268 "mov %c[r8](%0), %%r8 \n\t"
7269 "mov %c[r9](%0), %%r9 \n\t"
7270 "mov %c[r10](%0), %%r10 \n\t"
7271 "mov %c[r11](%0), %%r11 \n\t"
7272 "mov %c[r12](%0), %%r12 \n\t"
7273 "mov %c[r13](%0), %%r13 \n\t"
7274 "mov %c[r14](%0), %%r14 \n\t"
7275 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7276#endif
b188c81f 7277 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7278
6aa8b732 7279 /* Enter guest mode */
83287ea4 7280 "jne 1f \n\t"
4ecac3fd 7281 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7282 "jmp 2f \n\t"
7283 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7284 "2: "
6aa8b732 7285 /* Save guest registers, load host registers, keep flags */
b188c81f 7286 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7287 "pop %0 \n\t"
b188c81f
AK		 7288 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7289 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7290 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7291 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7292 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7293 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7294 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7295#ifdef CONFIG_X86_64
e08aa78a
AK		 7296 "mov %%r8, %c[r8](%0) \n\t"
7297 "mov %%r9, %c[r9](%0) \n\t"
7298 "mov %%r10, %c[r10](%0) \n\t"
7299 "mov %%r11, %c[r11](%0) \n\t"
7300 "mov %%r12, %c[r12](%0) \n\t"
7301 "mov %%r13, %c[r13](%0) \n\t"
7302 "mov %%r14, %c[r14](%0) \n\t"
7303 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7304#endif
b188c81f
AK		 7305 "mov %%cr2, %%" _ASM_AX " \n\t"
7306 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7307
b188c81f 7308 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7309 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7310 ".pushsection .rodata \n\t"
7311 ".global vmx_return \n\t"
7312 "vmx_return: " _ASM_PTR " 2b \n\t"
7313 ".popsection"
e08aa78a 7314 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7315 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7316 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7317 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7318 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7319 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7320 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7321 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7322 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7323 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7324 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7325#ifdef CONFIG_X86_64
ad312c7c
ZX		 7326 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7327 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7328 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7329 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7330 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7331 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7332 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7333 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7334#endif
40712fae
AK		 7335 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7336 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7337 : "cc", "memory"
7338#ifdef CONFIG_X86_64
b188c81f 7339 , "rax", "rbx", "rdi", "rsi"
c2036300 7340 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7341#else
7342 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7343#endif
7344 );
6aa8b732 7345
2a7921b7
GN		 7346 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7347 if (debugctlmsr)
7348 update_debugctlmsr(debugctlmsr);
7349
aa67f609
AK		 7350#ifndef CONFIG_X86_64
7351 /*
7352 * The sysexit path does not restore ds/es, so we must set them to
7353 * a reasonable value ourselves.
7354 *
7355 * We can't defer this to vmx_load_host_state() since that function
7356 * may be executed in interrupt context, which saves and restore segments
7357 * around it, nullifying its effect.
7358 */
7359 loadsegment(ds, __USER_DS);
7360 loadsegment(es, __USER_DS);
7361#endif
7362
6de4f3ad 7363 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7364 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7365 | (1 << VCPU_EXREG_CPL)
aff48baa 7366 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7367 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7368 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7369 vcpu->arch.regs_dirty = 0;
7370
1155f76a
AK		 7371 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7372
d462b819 7373 vmx->loaded_vmcs->launched = 1;
1b6269db 7374
51aa01d1 7375 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7376 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7377
e0b890d3
GN		 7378 /*
7379 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7380 * we did not inject a still-pending event to L1 now because of
7381 * nested_run_pending, we need to re-enable this bit.
7382 */
7383 if (vmx->nested.nested_run_pending)
7384 kvm_make_request(KVM_REQ_EVENT, vcpu);
7385
7386 vmx->nested.nested_run_pending = 0;
7387
51aa01d1
AK		 7388 vmx_complete_atomic_exit(vmx);
7389 vmx_recover_nmi_blocking(vmx);
cf393f75 7390 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7391}
7392
6aa8b732
AK		 7393static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7394{
fb3f0f51
RR		 7395 struct vcpu_vmx *vmx = to_vmx(vcpu);
7396
cdbecfc3 7397 free_vpid(vmx);
d462b819 7398 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7399 free_nested(vmx);
fb3f0f51
RR		 7400 kfree(vmx->guest_msrs);
7401 kvm_vcpu_uninit(vcpu);
a4770347 7402 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7403}
7404
fb3f0f51 7405static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7406{
fb3f0f51 7407 int err;
c16f862d 7408 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7409 int cpu;
6aa8b732 7410
a2fa3e9f 7411 if (!vmx)
fb3f0f51
RR		 7412 return ERR_PTR(-ENOMEM);
7413
2384d2b3
SY		 7414 allocate_vpid(vmx);
7415
fb3f0f51
RR		 7416 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7417 if (err)
7418 goto free_vcpu;
965b58a5 7419
a2fa3e9f 7420 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7421 err = -ENOMEM;
fb3f0f51 7422 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7423 goto uninit_vcpu;
7424 }
965b58a5 7425
d462b819
NHE		 7426 vmx->loaded_vmcs = &vmx->vmcs01;
7427 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7428 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7429 goto free_msrs;
d462b819
NHE		 7430 if (!vmm_exclusive)
7431 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7432 loaded_vmcs_init(vmx->loaded_vmcs);
7433 if (!vmm_exclusive)
7434 kvm_cpu_vmxoff();
a2fa3e9f 7435
15ad7146
AK		 7436 cpu = get_cpu();
7437 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7438 vmx->vcpu.cpu = cpu;
8b9cf98c 7439 err = vmx_vcpu_setup(vmx);
fb3f0f51 7440 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7441 put_cpu();
fb3f0f51
RR		 7442 if (err)
7443 goto free_vmcs;
a63cb560 7444 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7445 err = alloc_apic_access_page(kvm);
7446 if (err)
5e4a0b3c 7447 goto free_vmcs;
a63cb560 7448 }
fb3f0f51 7449
b927a3ce
SY		 7450 if (enable_ept) {
7451 if (!kvm->arch.ept_identity_map_addr)
7452 kvm->arch.ept_identity_map_addr =
7453 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7454 err = -ENOMEM;
b7ebfb05
SY		 7455 if (alloc_identity_pagetable(kvm) != 0)
7456 goto free_vmcs;
93ea5388
GN		 7457 if (!init_rmode_identity_map(kvm))
7458 goto free_vmcs;
b927a3ce 7459 }
b7ebfb05 7460
a9d30f33
NHE		 7461 vmx->nested.current_vmptr = -1ull;
7462 vmx->nested.current_vmcs12 = NULL;
7463
fb3f0f51
RR		 7464 return &vmx->vcpu;
7465
7466free_vmcs:
5f3fbc34 7467 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7468free_msrs:
fb3f0f51
RR		 7469 kfree(vmx->guest_msrs);
7470uninit_vcpu:
7471 kvm_vcpu_uninit(&vmx->vcpu);
7472free_vcpu:
cdbecfc3 7473 free_vpid(vmx);
a4770347 7474 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7475 return ERR_PTR(err);
6aa8b732
AK		 7476}
7477
002c7f7c
YS		 7478static void __init vmx_check_processor_compat(void *rtn)
7479{
7480 struct vmcs_config vmcs_conf;
7481
7482 *(int *)rtn = 0;
7483 if (setup_vmcs_config(&vmcs_conf) < 0)
7484 *(int *)rtn = -EIO;
7485 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7486 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7487 smp_processor_id());
7488 *(int *)rtn = -EIO;
7489 }
7490}
7491
67253af5
SY		 7492static int get_ept_level(void)
7493{
7494 return VMX_EPT_DEFAULT_GAW + 1;
7495}
7496
4b12f0de 7497static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7498{
4b12f0de
SY		 7499 u64 ret;
7500
522c68c4
SY		 7501 /* For VT-d and EPT combination
7502 * 1. MMIO: always map as UC
7503 * 2. EPT with VT-d:
7504 * a. VT-d without snooping control feature: can't guarantee the
7505 * result, try to trust guest.
7506 * b. VT-d with snooping control feature: snooping control feature of
7507 * VT-d engine can guarantee the cache correctness. Just set it
7508 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7509 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7510 * consistent with host MTRR
7511 */
4b12f0de
SY		 7512 if (is_mmio)
7513 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7514 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7515 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7516 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7517 else
522c68c4 7518 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7519 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7520
7521 return ret;
64d4d521
SY		 7522}
7523
17cc3935 7524static int vmx_get_lpage_level(void)
344f414f 7525{
878403b7
SY		 7526 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7527 return PT_DIRECTORY_LEVEL;
7528 else
7529 /* For shadow and EPT supported 1GB page */
7530 return PT_PDPE_LEVEL;
344f414f
JR		 7531}
7532
0e851880
SY		 7533static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7534{
4e47c7a6
SY		 7535 struct kvm_cpuid_entry2 *best;
7536 struct vcpu_vmx *vmx = to_vmx(vcpu);
7537 u32 exec_control;
7538
7539 vmx->rdtscp_enabled = false;
7540 if (vmx_rdtscp_supported()) {
7541 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7542 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7543 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7544 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7545 vmx->rdtscp_enabled = true;
7546 else {
7547 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7548 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7549 exec_control);
7550 }
7551 }
7552 }
ad756a16 7553
ad756a16
MJ		 7554 /* Exposing INVPCID only when PCID is exposed */
7555 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7556 if (vmx_invpcid_supported() &&
4f977045 7557 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7558 guest_cpuid_has_pcid(vcpu)) {
29282fde 7559 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7560 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7561 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7562 exec_control);
7563 } else {
29282fde
TI		 7564 if (cpu_has_secondary_exec_ctrls()) {
7565 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7566 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7568 exec_control);
7569 }
ad756a16 7570 if (best)
4f977045 7571 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7572 }
0e851880
SY		 7573}
7574
d4330ef2
JR		 7575static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7576{
7b8050f5
NHE		 7577 if (func == 1 && nested)
7578 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7579}
7580
25d92081
YZ		 7581static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7582 struct x86_exception *fault)
7583{
533558bc
JK		 7584 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7585 u32 exit_reason;
25d92081
YZ		 7586
7587 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7588 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7589 else
533558bc
JK		 7590 exit_reason = EXIT_REASON_EPT_VIOLATION;
7591 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7592 vmcs12->guest_physical_address = fault->address;
7593}
7594
155a97a3
NHE		 7595/* Callbacks for nested_ept_init_mmu_context: */
7596
7597static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7598{
7599 /* return the page table to be shadowed - in our case, EPT12 */
7600 return get_vmcs12(vcpu)->ept_pointer;
7601}
7602
8a3c1a33 7603static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7604{
8a3c1a33 7605 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7606 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7607
7608 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7609 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7610 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7611
7612 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7613}
7614
7615static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7616{
7617 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7618}
7619
feaf0c7d
GN		 7620static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7621 struct x86_exception *fault)
7622{
7623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7624
7625 WARN_ON(!is_guest_mode(vcpu));
7626
7627 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7628 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7629 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7630 vmcs_read32(VM_EXIT_INTR_INFO),
7631 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7632 else
7633 kvm_inject_page_fault(vcpu, fault);
7634}
7635
f4124500
JK		 7636static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7637{
7638 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7639 struct vcpu_vmx *vmx = to_vmx(vcpu);
7640
7641 if (vcpu->arch.virtual_tsc_khz == 0)
7642 return;
7643
7644 /* Make sure short timeouts reliably trigger an immediate vmexit.
7645 * hrtimer_start does not guarantee this. */
7646 if (preemption_timeout <= 1) {
7647 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7648 return;
7649 }
7650
7651 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7652 preemption_timeout *= 1000000;
7653 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7654 hrtimer_start(&vmx->nested.preemption_timer,
7655 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7656}
7657
fe3ef05c
NHE		 7658/*
7659 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7660 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7661 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7662 * guest in a way that will both be appropriate to L1's requests, and our
7663 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7664 * function also has additional necessary side-effects, like setting various
7665 * vcpu->arch fields.
7666 */
7667static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7668{
7669 struct vcpu_vmx *vmx = to_vmx(vcpu);
7670 u32 exec_control;
7671
7672 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7673 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7674 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7675 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7676 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7677 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7678 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7679 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7680 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7681 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7682 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7683 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7684 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7685 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7686 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7687 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7688 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7689 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7690 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7691 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7692 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7693 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7694 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7695 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7696 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7697 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7698 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7699 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7700 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7701 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7702 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7703 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7704 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7705 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7706 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7707 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7708
7709 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7710 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7711 vmcs12->vm_entry_intr_info_field);
7712 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7713 vmcs12->vm_entry_exception_error_code);
7714 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7715 vmcs12->vm_entry_instruction_len);
7716 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7717 vmcs12->guest_interruptibility_info);
fe3ef05c 7718 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7719 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7720 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7721 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7722 vmcs12->guest_pending_dbg_exceptions);
7723 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7724 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7725
7726 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7727
f4124500
JK		 7728 exec_control = vmcs12->pin_based_vm_exec_control;
7729 exec_control |= vmcs_config.pin_based_exec_ctrl;
7730 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
7731 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7732
f4124500
JK		 7733 vmx->nested.preemption_timer_expired = false;
7734 if (nested_cpu_has_preemption_timer(vmcs12))
7735 vmx_start_preemption_timer(vcpu);
0238ea91 7736
fe3ef05c
NHE		 7737 /*
7738 * Whether page-faults are trapped is determined by a combination of
7739 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7740 * If enable_ept, L0 doesn't care about page faults and we should
7741 * set all of these to L1's desires. However, if !enable_ept, L0 does
7742 * care about (at least some) page faults, and because it is not easy
7743 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7744 * to exit on each and every L2 page fault. This is done by setting
7745 * MASK=MATCH=0 and (see below) EB.PF=1.
7746 * Note that below we don't need special code to set EB.PF beyond the
7747 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7748 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7749 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7750 *
7751 * A problem with this approach (when !enable_ept) is that L1 may be
7752 * injected with more page faults than it asked for. This could have
7753 * caused problems, but in practice existing hypervisors don't care.
7754 * To fix this, we will need to emulate the PFEC checking (on the L1
7755 * page tables), using walk_addr(), when injecting PFs to L1.
7756 */
7757 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7758 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7759 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7760 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7761
7762 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7763 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7764 if (!vmx->rdtscp_enabled)
7765 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7766 /* Take the following fields only from vmcs12 */
7767 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7768 if (nested_cpu_has(vmcs12,
7769 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7770 exec_control |= vmcs12->secondary_vm_exec_control;
7771
7772 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7773 /*
7774 * Translate L1 physical address to host physical
7775 * address for vmcs02. Keep the page pinned, so this
7776 * physical address remains valid. We keep a reference
7777 * to it so we can release it later.
7778 */
7779 if (vmx->nested.apic_access_page) /* shouldn't happen */
7780 nested_release_page(vmx->nested.apic_access_page);
7781 vmx->nested.apic_access_page =
7782 nested_get_page(vcpu, vmcs12->apic_access_addr);
7783 /*
7784 * If translation failed, no matter: This feature asks
7785 * to exit when accessing the given address, and if it
7786 * can never be accessed, this feature won't do
7787 * anything anyway.
7788 */
7789 if (!vmx->nested.apic_access_page)
7790 exec_control &=
7791 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7792 else
7793 vmcs_write64(APIC_ACCESS_ADDR,
7794 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7795 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7796 exec_control |=
7797 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7798 vmcs_write64(APIC_ACCESS_ADDR,
7799 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7800 }
7801
7802 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7803 }
7804
7805
7806 /*
7807 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7808 * Some constant fields are set here by vmx_set_constant_host_state().
7809 * Other fields are different per CPU, and will be set later when
7810 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7811 */
a547c6db 7812 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7813
7814 /*
7815 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7816 * entry, but only if the current (host) sp changed from the value
7817 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7818 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7819 * here we just force the write to happen on entry.
7820 */
7821 vmx->host_rsp = 0;
7822
7823 exec_control = vmx_exec_control(vmx); /* L0's desires */
7824 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7825 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7826 exec_control &= ~CPU_BASED_TPR_SHADOW;
7827 exec_control |= vmcs12->cpu_based_vm_exec_control;
7828 /*
7829 * Merging of IO and MSR bitmaps not currently supported.
7830 * Rather, exit every time.
7831 */
7832 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7833 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7834 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7835
7836 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7837
7838 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7839 * bitwise-or of what L1 wants to trap for L2, and what we want to
7840 * trap. Note that CR0.TS also needs updating - we do this later.
7841 */
7842 update_exception_bitmap(vcpu);
7843 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7844 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7845
8049d651
NHE		 7846 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7847 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7848 * bits are further modified by vmx_set_efer() below.
7849 */
f4124500 7850 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 7851
7852 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7853 * emulated by vmx_set_efer(), below.
7854 */
2961e876 7855 vm_entry_controls_init(vmx,
8049d651
NHE		 7856 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7857 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7858 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7859
44811c02 7860 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7861 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7862 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7863 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7864 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7865
7866
7867 set_cr4_guest_host_mask(vmx);
7868
27fc51b2
NHE		 7869 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7870 vmcs_write64(TSC_OFFSET,
7871 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7872 else
7873 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7874
7875 if (enable_vpid) {
7876 /*
7877 * Trivially support vpid by letting L2s share their parent
7878 * L1's vpid. TODO: move to a more elaborate solution, giving
7879 * each L2 its own vpid and exposing the vpid feature to L1.
7880 */
7881 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7882 vmx_flush_tlb(vcpu);
7883 }
7884
155a97a3
NHE		 7885 if (nested_cpu_has_ept(vmcs12)) {
7886 kvm_mmu_unload(vcpu);
7887 nested_ept_init_mmu_context(vcpu);
7888 }
7889
fe3ef05c
NHE		 7890 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7891 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7892 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7893 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7894 else
7895 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7896 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7897 vmx_set_efer(vcpu, vcpu->arch.efer);
7898
7899 /*
7900 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7901 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7902 * The CR0_READ_SHADOW is what L2 should have expected to read given
7903 * the specifications by L1; It's not enough to take
7904 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7905 * have more bits than L1 expected.
7906 */
7907 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7908 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7909
7910 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7911 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7912
7913 /* shadow page tables on either EPT or shadow page tables */
7914 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7915 kvm_mmu_reset_context(vcpu);
7916
feaf0c7d
GN		 7917 if (!enable_ept)
7918 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7919
3633cfc3
NHE		 7920 /*
7921 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7922 */
7923 if (enable_ept) {
7924 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7925 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7926 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7927 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7928 }
7929
fe3ef05c
NHE		 7930 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7931 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7932}
7933
cd232ad0
NHE		 7934/*
7935 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7936 * for running an L2 nested guest.
7937 */
7938static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7939{
7940 struct vmcs12 *vmcs12;
7941 struct vcpu_vmx *vmx = to_vmx(vcpu);
7942 int cpu;
7943 struct loaded_vmcs *vmcs02;
384bb783 7944 bool ia32e;
cd232ad0
NHE		 7945
7946 if (!nested_vmx_check_permission(vcpu) ||
7947 !nested_vmx_check_vmcs12(vcpu))
7948 return 1;
7949
7950 skip_emulated_instruction(vcpu);
7951 vmcs12 = get_vmcs12(vcpu);
7952
012f83cb
AG		 7953 if (enable_shadow_vmcs)
7954 copy_shadow_to_vmcs12(vmx);
7955
7c177938
NHE		 7956 /*
7957 * The nested entry process starts with enforcing various prerequisites
7958 * on vmcs12 as required by the Intel SDM, and act appropriately when
7959 * they fail: As the SDM explains, some conditions should cause the
7960 * instruction to fail, while others will cause the instruction to seem
7961 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7962 * To speed up the normal (success) code path, we should avoid checking
7963 * for misconfigurations which will anyway be caught by the processor
7964 * when using the merged vmcs02.
7965 */
7966 if (vmcs12->launch_state == launch) {
7967 nested_vmx_failValid(vcpu,
7968 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7969 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7970 return 1;
7971 }
7972
6dfacadd
JK		 7973 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
7974 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 7975 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7976 return 1;
7977 }
7978
7c177938
NHE		 7979 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7980 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7981 /*TODO: Also verify bits beyond physical address width are 0*/
7982 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7983 return 1;
7984 }
7985
7986 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7987 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7988 /*TODO: Also verify bits beyond physical address width are 0*/
7989 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7990 return 1;
7991 }
7992
7993 if (vmcs12->vm_entry_msr_load_count > 0 ||
7994 vmcs12->vm_exit_msr_load_count > 0 ||
7995 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7996 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7997 __func__);
7c177938
NHE		 7998 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7999 return 1;
8000 }
8001
8002 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
8003 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
8004 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8005 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8006 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8007 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8008 !vmx_control_verify(vmcs12->vm_exit_controls,
8009 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
8010 !vmx_control_verify(vmcs12->vm_entry_controls,
8011 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
8012 {
8013 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8014 return 1;
8015 }
8016
8017 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8018 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8019 nested_vmx_failValid(vcpu,
8020 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8021 return 1;
8022 }
8023
92fbc7b1 8024 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8025 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8026 nested_vmx_entry_failure(vcpu, vmcs12,
8027 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8028 return 1;
8029 }
8030 if (vmcs12->vmcs_link_pointer != -1ull) {
8031 nested_vmx_entry_failure(vcpu, vmcs12,
8032 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8033 return 1;
8034 }
8035
384bb783 8036 /*
cb0c8cda 8037 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8038 * are performed on the field for the IA32_EFER MSR:
8039 * - Bits reserved in the IA32_EFER MSR must be 0.
8040 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8041 * the IA-32e mode guest VM-exit control. It must also be identical
8042 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8043 * CR0.PG) is 1.
8044 */
8045 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8046 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8047 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8048 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8049 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8050 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8051 nested_vmx_entry_failure(vcpu, vmcs12,
8052 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8053 return 1;
8054 }
8055 }
8056
8057 /*
8058 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8059 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8060 * the values of the LMA and LME bits in the field must each be that of
8061 * the host address-space size VM-exit control.
8062 */
8063 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8064 ia32e = (vmcs12->vm_exit_controls &
8065 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8066 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8067 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8068 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8069 nested_vmx_entry_failure(vcpu, vmcs12,
8070 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8071 return 1;
8072 }
8073 }
8074
7c177938
NHE		 8075 /*
8076 * We're finally done with prerequisite checking, and can start with
8077 * the nested entry.
8078 */
8079
cd232ad0
NHE		 8080 vmcs02 = nested_get_current_vmcs02(vmx);
8081 if (!vmcs02)
8082 return -ENOMEM;
8083
8084 enter_guest_mode(vcpu);
8085
8086 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8087
8088 cpu = get_cpu();
8089 vmx->loaded_vmcs = vmcs02;
8090 vmx_vcpu_put(vcpu);
8091 vmx_vcpu_load(vcpu, cpu);
8092 vcpu->cpu = cpu;
8093 put_cpu();
8094
36c3cc42
JK		 8095 vmx_segment_cache_clear(vmx);
8096
cd232ad0
NHE		 8097 vmcs12->launch_state = 1;
8098
8099 prepare_vmcs02(vcpu, vmcs12);
8100
6dfacadd
JK		 8101 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8102 return kvm_emulate_halt(vcpu);
8103
7af40ad3
JK		 8104 vmx->nested.nested_run_pending = 1;
8105
cd232ad0
NHE		 8106 /*
8107 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8108 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8109 * returned as far as L1 is concerned. It will only return (and set
8110 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8111 */
8112 return 1;
8113}
8114
4704d0be
NHE		 8115/*
8116 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8117 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8118 * This function returns the new value we should put in vmcs12.guest_cr0.
8119 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8120 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8121 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8122 * didn't trap the bit, because if L1 did, so would L0).
8123 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8124 * been modified by L2, and L1 knows it. So just leave the old value of
8125 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8126 * isn't relevant, because if L0 traps this bit it can set it to anything.
8127 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8128 * changed these bits, and therefore they need to be updated, but L0
8129 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8130 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8131 */
8132static inline unsigned long
8133vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8134{
8135 return
8136 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8137 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8138 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8139 vcpu->arch.cr0_guest_owned_bits));
8140}
8141
8142static inline unsigned long
8143vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8144{
8145 return
8146 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8147 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8148 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8149 vcpu->arch.cr4_guest_owned_bits));
8150}
8151
5f3d5799
JK		 8152static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8153 struct vmcs12 *vmcs12)
8154{
8155 u32 idt_vectoring;
8156 unsigned int nr;
8157
851eb667 8158 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8159 nr = vcpu->arch.exception.nr;
8160 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8161
8162 if (kvm_exception_is_soft(nr)) {
8163 vmcs12->vm_exit_instruction_len =
8164 vcpu->arch.event_exit_inst_len;
8165 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8166 } else
8167 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8168
8169 if (vcpu->arch.exception.has_error_code) {
8170 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8171 vmcs12->idt_vectoring_error_code =
8172 vcpu->arch.exception.error_code;
8173 }
8174
8175 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8176 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8177 vmcs12->idt_vectoring_info_field =
8178 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8179 } else if (vcpu->arch.interrupt.pending) {
8180 nr = vcpu->arch.interrupt.nr;
8181 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8182
8183 if (vcpu->arch.interrupt.soft) {
8184 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8185 vmcs12->vm_entry_instruction_len =
8186 vcpu->arch.event_exit_inst_len;
8187 } else
8188 idt_vectoring |= INTR_TYPE_EXT_INTR;
8189
8190 vmcs12->idt_vectoring_info_field = idt_vectoring;
8191 }
8192}
8193
b6b8a145
JK		 8194static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8195{
8196 struct vcpu_vmx *vmx = to_vmx(vcpu);
8197
f4124500
JK		 8198 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8199 vmx->nested.preemption_timer_expired) {
8200 if (vmx->nested.nested_run_pending)
8201 return -EBUSY;
8202 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8203 return 0;
8204 }
8205
b6b8a145 8206 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8207 if (vmx->nested.nested_run_pending ||
8208 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8209 return -EBUSY;
8210 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8211 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8212 INTR_INFO_VALID_MASK, 0);
8213 /*
8214 * The NMI-triggered VM exit counts as injection:
8215 * clear this one and block further NMIs.
8216 */
8217 vcpu->arch.nmi_pending = 0;
8218 vmx_set_nmi_mask(vcpu, true);
8219 return 0;
8220 }
8221
8222 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8223 nested_exit_on_intr(vcpu)) {
8224 if (vmx->nested.nested_run_pending)
8225 return -EBUSY;
8226 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8227 }
8228
8229 return 0;
8230}
8231
f4124500
JK		 8232static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8233{
8234 ktime_t remaining =
8235 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8236 u64 value;
8237
8238 if (ktime_to_ns(remaining) <= 0)
8239 return 0;
8240
8241 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8242 do_div(value, 1000000);
8243 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8244}
8245
4704d0be
NHE		 8246/*
8247 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8248 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8249 * and this function updates it to reflect the changes to the guest state while
8250 * L2 was running (and perhaps made some exits which were handled directly by L0
8251 * without going back to L1), and to reflect the exit reason.
8252 * Note that we do not have to copy here all VMCS fields, just those that
8253 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8254 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8255 * which already writes to vmcs12 directly.
8256 */
533558bc
JK		 8257static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8258 u32 exit_reason, u32 exit_intr_info,
8259 unsigned long exit_qualification)
4704d0be
NHE		 8260{
8261 /* update guest state fields: */
8262 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8263 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8264
8265 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8266 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8267 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8268 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8269
8270 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8271 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8272 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8273 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8274 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8275 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8276 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8277 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8278 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8279 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8280 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8281 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8282 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8283 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8284 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8285 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8286 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8287 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8288 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8289 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8290 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8291 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8292 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8293 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8294 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8295 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8296 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8297 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8298 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8299 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8300 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8301 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8302 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8303 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8304 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8305 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8306
4704d0be
NHE		 8307 vmcs12->guest_interruptibility_info =
8308 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8309 vmcs12->guest_pending_dbg_exceptions =
8310 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8311 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8312 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8313 else
8314 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8315
f4124500
JK		 8316 if (nested_cpu_has_preemption_timer(vmcs12)) {
8317 if (vmcs12->vm_exit_controls &
8318 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8319 vmcs12->vmx_preemption_timer_value =
8320 vmx_get_preemption_timer_value(vcpu);
8321 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8322 }
7854cbca 8323
3633cfc3
NHE		 8324 /*
8325 * In some cases (usually, nested EPT), L2 is allowed to change its
8326 * own CR3 without exiting. If it has changed it, we must keep it.
8327 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8328 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8329 *
8330 * Additionally, restore L2's PDPTR to vmcs12.
8331 */
8332 if (enable_ept) {
8333 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8334 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8335 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8336 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8337 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8338 }
8339
c18911a2
JK		 8340 vmcs12->vm_entry_controls =
8341 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8342 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8343
4704d0be
NHE		 8344 /* TODO: These cannot have changed unless we have MSR bitmaps and
8345 * the relevant bit asks not to trap the change */
8346 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8347 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8348 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8349 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8350 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8351 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8352 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8353 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8354
8355 /* update exit information fields: */
8356
533558bc
JK		 8357 vmcs12->vm_exit_reason = exit_reason;
8358 vmcs12->exit_qualification = exit_qualification;
4704d0be 8359
533558bc 8360 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8361 if ((vmcs12->vm_exit_intr_info &
8362 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8363 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8364 vmcs12->vm_exit_intr_error_code =
8365 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8366 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8367 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8368 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8369
5f3d5799
JK		 8370 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8371 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8372 * instead of reading the real value. */
4704d0be 8373 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8374
8375 /*
8376 * Transfer the event that L0 or L1 may wanted to inject into
8377 * L2 to IDT_VECTORING_INFO_FIELD.
8378 */
8379 vmcs12_save_pending_event(vcpu, vmcs12);
8380 }
8381
8382 /*
8383 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8384 * preserved above and would only end up incorrectly in L1.
8385 */
8386 vcpu->arch.nmi_injected = false;
8387 kvm_clear_exception_queue(vcpu);
8388 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8389}
8390
8391/*
8392 * A part of what we need to when the nested L2 guest exits and we want to
8393 * run its L1 parent, is to reset L1's guest state to the host state specified
8394 * in vmcs12.
8395 * This function is to be called not only on normal nested exit, but also on
8396 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8397 * Failures During or After Loading Guest State").
8398 * This function should be called when the active VMCS is L1's (vmcs01).
8399 */
733568f9
JK		 8400static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8401 struct vmcs12 *vmcs12)
4704d0be 8402{
21feb4eb
ACL		 8403 struct kvm_segment seg;
8404
4704d0be
NHE		 8405 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8406 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8407 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8408 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8409 else
8410 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8411 vmx_set_efer(vcpu, vcpu->arch.efer);
8412
8413 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8414 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8415 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8416 /*
8417 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8418 * actually changed, because it depends on the current state of
8419 * fpu_active (which may have changed).
8420 * Note that vmx_set_cr0 refers to efer set above.
8421 */
9e3e4dbf 8422 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8423 /*
8424 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8425 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8426 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8427 */
8428 update_exception_bitmap(vcpu);
8429 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8430 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8431
8432 /*
8433 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8434 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8435 */
8436 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8437 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8438
29bf08f1 8439 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8440
4704d0be
NHE		 8441 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8442 kvm_mmu_reset_context(vcpu);
8443
feaf0c7d
GN		 8444 if (!enable_ept)
8445 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8446
4704d0be
NHE		 8447 if (enable_vpid) {
8448 /*
8449 * Trivially support vpid by letting L2s share their parent
8450 * L1's vpid. TODO: move to a more elaborate solution, giving
8451 * each L2 its own vpid and exposing the vpid feature to L1.
8452 */
8453 vmx_flush_tlb(vcpu);
8454 }
8455
8456
8457 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8458 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8459 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8460 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8461 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8462
44811c02 8463 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8464 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8465 vcpu->arch.pat = vmcs12->host_ia32_pat;
8466 }
4704d0be
NHE		 8467 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8468 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8469 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8470
21feb4eb
ACL		 8471 /* Set L1 segment info according to Intel SDM
8472 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8473 seg = (struct kvm_segment) {
8474 .base = 0,
8475 .limit = 0xFFFFFFFF,
8476 .selector = vmcs12->host_cs_selector,
8477 .type = 11,
8478 .present = 1,
8479 .s = 1,
8480 .g = 1
8481 };
8482 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8483 seg.l = 1;
8484 else
8485 seg.db = 1;
8486 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8487 seg = (struct kvm_segment) {
8488 .base = 0,
8489 .limit = 0xFFFFFFFF,
8490 .type = 3,
8491 .present = 1,
8492 .s = 1,
8493 .db = 1,
8494 .g = 1
8495 };
8496 seg.selector = vmcs12->host_ds_selector;
8497 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8498 seg.selector = vmcs12->host_es_selector;
8499 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8500 seg.selector = vmcs12->host_ss_selector;
8501 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8502 seg.selector = vmcs12->host_fs_selector;
8503 seg.base = vmcs12->host_fs_base;
8504 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8505 seg.selector = vmcs12->host_gs_selector;
8506 seg.base = vmcs12->host_gs_base;
8507 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8508 seg = (struct kvm_segment) {
205befd9 8509 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8510 .limit = 0x67,
8511 .selector = vmcs12->host_tr_selector,
8512 .type = 11,
8513 .present = 1
8514 };
8515 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8516
503cd0c5
JK		 8517 kvm_set_dr(vcpu, 7, 0x400);
8518 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8519}
8520
8521/*
8522 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8523 * and modify vmcs12 to make it see what it would expect to see there if
8524 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8525 */
533558bc
JK		 8526static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8527 u32 exit_intr_info,
8528 unsigned long exit_qualification)
4704d0be
NHE		 8529{
8530 struct vcpu_vmx *vmx = to_vmx(vcpu);
8531 int cpu;
8532 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8533
5f3d5799
JK		 8534 /* trying to cancel vmlaunch/vmresume is a bug */
8535 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8536
4704d0be 8537 leave_guest_mode(vcpu);
533558bc
JK		 8538 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8539 exit_qualification);
4704d0be 8540
542060ea
JK		 8541 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8542 vmcs12->exit_qualification,
8543 vmcs12->idt_vectoring_info_field,
8544 vmcs12->vm_exit_intr_info,
8545 vmcs12->vm_exit_intr_error_code,
8546 KVM_ISA_VMX);
4704d0be
NHE		 8547
8548 cpu = get_cpu();
8549 vmx->loaded_vmcs = &vmx->vmcs01;
8550 vmx_vcpu_put(vcpu);
8551 vmx_vcpu_load(vcpu, cpu);
8552 vcpu->cpu = cpu;
8553 put_cpu();
8554
2961e876
GN		 8555 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8556 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8557 vmx_segment_cache_clear(vmx);
8558
4704d0be
NHE		 8559 /* if no vmcs02 cache requested, remove the one we used */
8560 if (VMCS02_POOL_SIZE == 0)
8561 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8562
8563 load_vmcs12_host_state(vcpu, vmcs12);
8564
27fc51b2 8565 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8566 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8567
8568 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8569 vmx->host_rsp = 0;
8570
8571 /* Unpin physical memory we referred to in vmcs02 */
8572 if (vmx->nested.apic_access_page) {
8573 nested_release_page(vmx->nested.apic_access_page);
8574 vmx->nested.apic_access_page = 0;
8575 }
8576
8577 /*
8578 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8579 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8580 * success or failure flag accordingly.
8581 */
8582 if (unlikely(vmx->fail)) {
8583 vmx->fail = 0;
8584 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8585 } else
8586 nested_vmx_succeed(vcpu);
012f83cb
AG		 8587 if (enable_shadow_vmcs)
8588 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8589
8590 /* in case we halted in L2 */
8591 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8592}
8593
42124925
JK		 8594/*
8595 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8596 */
8597static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8598{
8599 if (is_guest_mode(vcpu))
533558bc 8600 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8601 free_nested(to_vmx(vcpu));
8602}
8603
7c177938
NHE		 8604/*
8605 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8606 * 23.7 "VM-entry failures during or after loading guest state" (this also
8607 * lists the acceptable exit-reason and exit-qualification parameters).
8608 * It should only be called before L2 actually succeeded to run, and when
8609 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8610 */
8611static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8612 struct vmcs12 *vmcs12,
8613 u32 reason, unsigned long qualification)
8614{
8615 load_vmcs12_host_state(vcpu, vmcs12);
8616 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8617 vmcs12->exit_qualification = qualification;
8618 nested_vmx_succeed(vcpu);
012f83cb
AG		 8619 if (enable_shadow_vmcs)
8620 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8621}
8622
8a76d7f2
JR		 8623static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8624 struct x86_instruction_info *info,
8625 enum x86_intercept_stage stage)
8626{
8627 return X86EMUL_CONTINUE;
8628}
8629
cbdd1bea 8630static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8631 .cpu_has_kvm_support = cpu_has_kvm_support,
8632 .disabled_by_bios = vmx_disabled_by_bios,
8633 .hardware_setup = hardware_setup,
8634 .hardware_unsetup = hardware_unsetup,
002c7f7c 8635 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8636 .hardware_enable = hardware_enable,
8637 .hardware_disable = hardware_disable,
04547156 8638 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8639
8640 .vcpu_create = vmx_create_vcpu,
8641 .vcpu_free = vmx_free_vcpu,
04d2cc77 8642 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8643
04d2cc77 8644 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8645 .vcpu_load = vmx_vcpu_load,
8646 .vcpu_put = vmx_vcpu_put,
8647
c8639010 8648 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8649 .get_msr = vmx_get_msr,
8650 .set_msr = vmx_set_msr,
8651 .get_segment_base = vmx_get_segment_base,
8652 .get_segment = vmx_get_segment,
8653 .set_segment = vmx_set_segment,
2e4d2653 8654 .get_cpl = vmx_get_cpl,
6aa8b732 8655 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8656 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8657 .decache_cr3 = vmx_decache_cr3,
25c4c276 8658 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8659 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8660 .set_cr3 = vmx_set_cr3,
8661 .set_cr4 = vmx_set_cr4,
6aa8b732 8662 .set_efer = vmx_set_efer,
6aa8b732
AK		 8663 .get_idt = vmx_get_idt,
8664 .set_idt = vmx_set_idt,
8665 .get_gdt = vmx_get_gdt,
8666 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8667 .get_dr6 = vmx_get_dr6,
8668 .set_dr6 = vmx_set_dr6,
020df079 8669 .set_dr7 = vmx_set_dr7,
81908bf4 8670 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8671 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8672 .get_rflags = vmx_get_rflags,
8673 .set_rflags = vmx_set_rflags,
ebcbab4c 8674 .fpu_activate = vmx_fpu_activate,
02daab21 8675 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8676
8677 .tlb_flush = vmx_flush_tlb,
6aa8b732 8678
6aa8b732 8679 .run = vmx_vcpu_run,
6062d012 8680 .handle_exit = vmx_handle_exit,
6aa8b732 8681 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8682 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8683 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8684 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8685 .set_irq = vmx_inject_irq,
95ba8273 8686 .set_nmi = vmx_inject_nmi,
298101da 8687 .queue_exception = vmx_queue_exception,
b463a6f7 8688 .cancel_injection = vmx_cancel_injection,
78646121 8689 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8690 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8691 .get_nmi_mask = vmx_get_nmi_mask,
8692 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8693 .enable_nmi_window = enable_nmi_window,
8694 .enable_irq_window = enable_irq_window,
8695 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8696 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8697 .vm_has_apicv = vmx_vm_has_apicv,
8698 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8699 .hwapic_irr_update = vmx_hwapic_irr_update,
8700 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8701 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8702 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8703
cbc94022 8704 .set_tss_addr = vmx_set_tss_addr,
67253af5 8705 .get_tdp_level = get_ept_level,
4b12f0de 8706 .get_mt_mask = vmx_get_mt_mask,
229456fc 8707
586f9607 8708 .get_exit_info = vmx_get_exit_info,
586f9607 8709
17cc3935 8710 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8711
8712 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8713
8714 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8715 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8716
8717 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8718
8719 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8720
4051b188 8721 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8722 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8723 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8724 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8725 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8726 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8727
8728 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8729
8730 .check_intercept = vmx_check_intercept,
a547c6db 8731 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8732 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8733
8734 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8735};
8736
8737static int __init vmx_init(void)
8738{
8d14695f 8739 int r, i, msr;
26bb0981
AK		 8740
8741 rdmsrl_safe(MSR_EFER, &host_efer);
8742
8743 for (i = 0; i < NR_VMX_MSR; ++i)
8744 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8745
3e7c73e9 8746 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8747 if (!vmx_io_bitmap_a)
8748 return -ENOMEM;
8749
2106a548
GC		 8750 r = -ENOMEM;
8751
3e7c73e9 8752 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8753 if (!vmx_io_bitmap_b)
fdef3ad1 8754 goto out;
fdef3ad1 8755
5897297b 8756 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8757 if (!vmx_msr_bitmap_legacy)
25c5f225 8758 goto out1;
2106a548 8759
8d14695f
YZ		 8760 vmx_msr_bitmap_legacy_x2apic =
8761 (unsigned long *)__get_free_page(GFP_KERNEL);
8762 if (!vmx_msr_bitmap_legacy_x2apic)
8763 goto out2;
25c5f225 8764
5897297b 8765 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8766 if (!vmx_msr_bitmap_longmode)
8d14695f 8767 goto out3;
2106a548 8768
8d14695f
YZ		 8769 vmx_msr_bitmap_longmode_x2apic =
8770 (unsigned long *)__get_free_page(GFP_KERNEL);
8771 if (!vmx_msr_bitmap_longmode_x2apic)
8772 goto out4;
4607c2d7
AG		 8773 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8774 if (!vmx_vmread_bitmap)
8775 goto out5;
8776
8777 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8778 if (!vmx_vmwrite_bitmap)
8779 goto out6;
8780
8781 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8782 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8783 /* shadowed read/write fields */
8784 for (i = 0; i < max_shadow_read_write_fields; i++) {
8785 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8786 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8787 }
8788 /* shadowed read only fields */
8789 for (i = 0; i < max_shadow_read_only_fields; i++)
8790 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8791
fdef3ad1
HQ		 8792 /*
8793 * Allow direct access to the PC debug port (it is often used for I/O
8794 * delays, but the vmexits simply slow things down).
8795 */
3e7c73e9
AK		 8796 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8797 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8798
3e7c73e9 8799 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8800
5897297b
AK		 8801 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8802 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8803
2384d2b3
SY		 8804 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8805
0ee75bea
AK		 8806 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8807 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8808 if (r)
4607c2d7 8809 goto out7;
25c5f225 8810
8f536b76
ZY		 8811#ifdef CONFIG_KEXEC
8812 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8813 crash_vmclear_local_loaded_vmcss);
8814#endif
8815
5897297b
AK		 8816 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8817 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8818 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8819 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8820 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8821 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8822 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8823
8d14695f
YZ		 8824 memcpy(vmx_msr_bitmap_legacy_x2apic,
8825 vmx_msr_bitmap_legacy, PAGE_SIZE);
8826 memcpy(vmx_msr_bitmap_longmode_x2apic,
8827 vmx_msr_bitmap_longmode, PAGE_SIZE);
8828
01e439be 8829 if (enable_apicv) {
8d14695f
YZ		 8830 for (msr = 0x800; msr <= 0x8ff; msr++)
8831 vmx_disable_intercept_msr_read_x2apic(msr);
8832
8833 /* According SDM, in x2apic mode, the whole id reg is used.
8834 * But in KVM, it only use the highest eight bits. Need to
8835 * intercept it */
8836 vmx_enable_intercept_msr_read_x2apic(0x802);
8837 /* TMCCT */
8838 vmx_enable_intercept_msr_read_x2apic(0x839);
8839 /* TPR */
8840 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8841 /* EOI */
8842 vmx_disable_intercept_msr_write_x2apic(0x80b);
8843 /* SELF-IPI */
8844 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8845 }
fdef3ad1 8846
089d034e 8847 if (enable_ept) {
3f6d8c8a
XH		 8848 kvm_mmu_set_mask_ptes(0ull,
8849 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8850 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8851 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8852 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8853 kvm_enable_tdp();
8854 } else
8855 kvm_disable_tdp();
1439442c 8856
fdef3ad1
HQ		 8857 return 0;
8858
4607c2d7
AG		 8859out7:
8860 free_page((unsigned long)vmx_vmwrite_bitmap);
8861out6:
8862 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8863out5:
8864 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8865out4:
5897297b 8866 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8867out3:
8868 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8869out2:
5897297b 8870 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8871out1:
3e7c73e9 8872 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8873out:
3e7c73e9 8874 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8875 return r;
6aa8b732
AK		 8876}
8877
8878static void __exit vmx_exit(void)
8879{
8d14695f
YZ		 8880 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8881 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8882 free_page((unsigned long)vmx_msr_bitmap_legacy);
8883 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8884 free_page((unsigned long)vmx_io_bitmap_b);
8885 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8886 free_page((unsigned long)vmx_vmwrite_bitmap);
8887 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8888
8f536b76
ZY		 8889#ifdef CONFIG_KEXEC
8890 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8891 synchronize_rcu();
8892#endif
8893
cb498ea2 8894 kvm_exit();
6aa8b732
AK		 8895}
8896
8897module_init(vmx_init)
8898module_exit(vmx_exit)
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