2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
43 #include <asm/fpu/internal.h>
44 #include <asm/perf_event.h>
45 #include <asm/debugreg.h>
46 #include <asm/kexec.h>
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 #define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id vmx_cpu_id
[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
63 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
65 static bool __read_mostly enable_vpid
= 1;
66 module_param_named(vpid
, enable_vpid
, bool, 0444);
68 static bool __read_mostly flexpriority_enabled
= 1;
69 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
71 static bool __read_mostly enable_ept
= 1;
72 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
74 static bool __read_mostly enable_unrestricted_guest
= 1;
75 module_param_named(unrestricted_guest
,
76 enable_unrestricted_guest
, bool, S_IRUGO
);
78 static bool __read_mostly enable_ept_ad_bits
= 1;
79 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
81 static bool __read_mostly emulate_invalid_guest_state
= true;
82 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
84 static bool __read_mostly vmm_exclusive
= 1;
85 module_param(vmm_exclusive
, bool, S_IRUGO
);
87 static bool __read_mostly fasteoi
= 1;
88 module_param(fasteoi
, bool, S_IRUGO
);
90 static bool __read_mostly enable_apicv
= 1;
91 module_param(enable_apicv
, bool, S_IRUGO
);
93 static bool __read_mostly enable_shadow_vmcs
= 1;
94 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested
= 0;
101 module_param(nested
, bool, S_IRUGO
);
103 static u64 __read_mostly host_xss
;
105 static bool __read_mostly enable_pml
= 1;
106 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
127 * According to test, this time is usually smaller than 128 cycles.
128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
134 #define KVM_VMX_DEFAULT_PLE_GAP 128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
141 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
142 module_param(ple_gap
, int, S_IRUGO
);
144 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
145 module_param(ple_window
, int, S_IRUGO
);
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
149 module_param(ple_window_grow
, int, S_IRUGO
);
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
153 module_param(ple_window_shrink
, int, S_IRUGO
);
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
157 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
158 module_param(ple_window_max
, int, S_IRUGO
);
160 extern const ulong vmx_return
;
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
180 struct list_head loaded_vmcss_on_cpu_link
;
183 struct shared_msr_entry
{
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
202 typedef u64 natural_width
;
203 struct __packed vmcs12
{
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
210 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding
[7]; /* room for future expansion */
216 u64 vm_exit_msr_store_addr
;
217 u64 vm_exit_msr_load_addr
;
218 u64 vm_entry_msr_load_addr
;
220 u64 virtual_apic_page_addr
;
221 u64 apic_access_addr
;
222 u64 posted_intr_desc_addr
;
224 u64 eoi_exit_bitmap0
;
225 u64 eoi_exit_bitmap1
;
226 u64 eoi_exit_bitmap2
;
227 u64 eoi_exit_bitmap3
;
229 u64 guest_physical_address
;
230 u64 vmcs_link_pointer
;
231 u64 guest_ia32_debugctl
;
234 u64 guest_ia32_perf_global_ctrl
;
242 u64 host_ia32_perf_global_ctrl
;
243 u64 padding64
[8]; /* room for future expansion */
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
250 natural_width cr0_guest_host_mask
;
251 natural_width cr4_guest_host_mask
;
252 natural_width cr0_read_shadow
;
253 natural_width cr4_read_shadow
;
254 natural_width cr3_target_value0
;
255 natural_width cr3_target_value1
;
256 natural_width cr3_target_value2
;
257 natural_width cr3_target_value3
;
258 natural_width exit_qualification
;
259 natural_width guest_linear_address
;
260 natural_width guest_cr0
;
261 natural_width guest_cr3
;
262 natural_width guest_cr4
;
263 natural_width guest_es_base
;
264 natural_width guest_cs_base
;
265 natural_width guest_ss_base
;
266 natural_width guest_ds_base
;
267 natural_width guest_fs_base
;
268 natural_width guest_gs_base
;
269 natural_width guest_ldtr_base
;
270 natural_width guest_tr_base
;
271 natural_width guest_gdtr_base
;
272 natural_width guest_idtr_base
;
273 natural_width guest_dr7
;
274 natural_width guest_rsp
;
275 natural_width guest_rip
;
276 natural_width guest_rflags
;
277 natural_width guest_pending_dbg_exceptions
;
278 natural_width guest_sysenter_esp
;
279 natural_width guest_sysenter_eip
;
280 natural_width host_cr0
;
281 natural_width host_cr3
;
282 natural_width host_cr4
;
283 natural_width host_fs_base
;
284 natural_width host_gs_base
;
285 natural_width host_tr_base
;
286 natural_width host_gdtr_base
;
287 natural_width host_idtr_base
;
288 natural_width host_ia32_sysenter_esp
;
289 natural_width host_ia32_sysenter_eip
;
290 natural_width host_rsp
;
291 natural_width host_rip
;
292 natural_width paddingl
[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control
;
294 u32 cpu_based_vm_exec_control
;
295 u32 exception_bitmap
;
296 u32 page_fault_error_code_mask
;
297 u32 page_fault_error_code_match
;
298 u32 cr3_target_count
;
299 u32 vm_exit_controls
;
300 u32 vm_exit_msr_store_count
;
301 u32 vm_exit_msr_load_count
;
302 u32 vm_entry_controls
;
303 u32 vm_entry_msr_load_count
;
304 u32 vm_entry_intr_info_field
;
305 u32 vm_entry_exception_error_code
;
306 u32 vm_entry_instruction_len
;
308 u32 secondary_vm_exec_control
;
309 u32 vm_instruction_error
;
311 u32 vm_exit_intr_info
;
312 u32 vm_exit_intr_error_code
;
313 u32 idt_vectoring_info_field
;
314 u32 idt_vectoring_error_code
;
315 u32 vm_exit_instruction_len
;
316 u32 vmx_instruction_info
;
323 u32 guest_ldtr_limit
;
325 u32 guest_gdtr_limit
;
326 u32 guest_idtr_limit
;
327 u32 guest_es_ar_bytes
;
328 u32 guest_cs_ar_bytes
;
329 u32 guest_ss_ar_bytes
;
330 u32 guest_ds_ar_bytes
;
331 u32 guest_fs_ar_bytes
;
332 u32 guest_gs_ar_bytes
;
333 u32 guest_ldtr_ar_bytes
;
334 u32 guest_tr_ar_bytes
;
335 u32 guest_interruptibility_info
;
336 u32 guest_activity_state
;
337 u32 guest_sysenter_cs
;
338 u32 host_ia32_sysenter_cs
;
339 u32 vmx_preemption_timer_value
;
340 u32 padding32
[7]; /* room for future expansion */
341 u16 virtual_processor_id
;
343 u16 guest_es_selector
;
344 u16 guest_cs_selector
;
345 u16 guest_ss_selector
;
346 u16 guest_ds_selector
;
347 u16 guest_fs_selector
;
348 u16 guest_gs_selector
;
349 u16 guest_ldtr_selector
;
350 u16 guest_tr_selector
;
351 u16 guest_intr_status
;
352 u16 host_es_selector
;
353 u16 host_cs_selector
;
354 u16 host_ss_selector
;
355 u16 host_ds_selector
;
356 u16 host_fs_selector
;
357 u16 host_gs_selector
;
358 u16 host_tr_selector
;
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
366 #define VMCS12_REVISION 0x11e57ed0
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
373 #define VMCS12_SIZE 0x1000
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
377 struct list_head list
;
379 struct loaded_vmcs vmcs02
;
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 /* Has the level1 guest done vmxon? */
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
393 /* The host-usable pointer to the above */
394 struct page
*current_vmcs12_page
;
395 struct vmcs12
*current_vmcs12
;
396 struct vmcs
*current_shadow_vmcs
;
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
401 bool sync_shadow_vmcs
;
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool
;
406 u64 vmcs01_tsc_offset
;
407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending
;
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
413 struct page
*apic_access_page
;
414 struct page
*virtual_apic_page
;
415 struct page
*pi_desc_page
;
416 struct pi_desc
*pi_desc
;
419 u64 msr_ia32_feature_control
;
421 struct hrtimer preemption_timer
;
422 bool preemption_timer_expired
;
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u32 nested_vmx_procbased_ctls_low
;
428 u32 nested_vmx_procbased_ctls_high
;
429 u32 nested_vmx_true_procbased_ctls_low
;
430 u32 nested_vmx_secondary_ctls_low
;
431 u32 nested_vmx_secondary_ctls_high
;
432 u32 nested_vmx_pinbased_ctls_low
;
433 u32 nested_vmx_pinbased_ctls_high
;
434 u32 nested_vmx_exit_ctls_low
;
435 u32 nested_vmx_exit_ctls_high
;
436 u32 nested_vmx_true_exit_ctls_low
;
437 u32 nested_vmx_entry_ctls_low
;
438 u32 nested_vmx_entry_ctls_high
;
439 u32 nested_vmx_true_entry_ctls_low
;
440 u32 nested_vmx_misc_low
;
441 u32 nested_vmx_misc_high
;
442 u32 nested_vmx_ept_caps
;
445 #define POSTED_INTR_ON 0
446 /* Posted-Interrupt Descriptor */
448 u32 pir
[8]; /* Posted interrupt requested */
449 u32 control
; /* bit 0 of control is outstanding notification bit */
453 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
455 return test_and_set_bit(POSTED_INTR_ON
,
456 (unsigned long *)&pi_desc
->control
);
459 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
461 return test_and_clear_bit(POSTED_INTR_ON
,
462 (unsigned long *)&pi_desc
->control
);
465 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
467 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
471 struct kvm_vcpu vcpu
;
472 unsigned long host_rsp
;
474 bool nmi_known_unmasked
;
476 u32 idt_vectoring_info
;
478 struct shared_msr_entry
*guest_msrs
;
481 unsigned long host_idt_base
;
483 u64 msr_host_kernel_gs_base
;
484 u64 msr_guest_kernel_gs_base
;
486 u32 vm_entry_controls_shadow
;
487 u32 vm_exit_controls_shadow
;
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
493 struct loaded_vmcs vmcs01
;
494 struct loaded_vmcs
*loaded_vmcs
;
495 bool __launched
; /* temporary, used in vmx_vcpu_run */
496 struct msr_autoload
{
498 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
499 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
503 u16 fs_sel
, gs_sel
, ldt_sel
;
507 int gs_ldt_reload_needed
;
508 int fs_reload_needed
;
509 u64 msr_host_bndcfgs
;
510 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
515 struct kvm_segment segs
[8];
518 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
519 struct kvm_save_segment
{
527 bool emulation_required
;
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked
;
532 s64 vnmi_blocked_time
;
537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc
;
540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested
;
543 /* Dynamic PLE window. */
545 bool ple_window_dirty
;
547 /* Support for PML */
548 #define PML_ENTITY_NUM 512
552 enum segment_cache_field
{
561 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
563 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
572 static unsigned long shadow_read_only_fields
[] = {
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
587 VM_EXIT_INSTRUCTION_LEN
,
588 IDT_VECTORING_INFO_FIELD
,
589 IDT_VECTORING_ERROR_CODE
,
590 VM_EXIT_INTR_ERROR_CODE
,
592 GUEST_LINEAR_ADDRESS
,
593 GUEST_PHYSICAL_ADDRESS
595 static int max_shadow_read_only_fields
=
596 ARRAY_SIZE(shadow_read_only_fields
);
598 static unsigned long shadow_read_write_fields
[] = {
605 GUEST_INTERRUPTIBILITY_INFO
,
618 CPU_BASED_VM_EXEC_CONTROL
,
619 VM_ENTRY_EXCEPTION_ERROR_CODE
,
620 VM_ENTRY_INTR_INFO_FIELD
,
621 VM_ENTRY_INSTRUCTION_LEN
,
622 VM_ENTRY_EXCEPTION_ERROR_CODE
,
628 static int max_shadow_read_write_fields
=
629 ARRAY_SIZE(shadow_read_write_fields
);
631 static const unsigned short vmcs_field_to_offset_table
[] = {
632 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
633 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
634 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
635 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
636 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
637 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
638 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
639 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
640 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
641 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
642 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
643 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
644 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
645 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
646 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
647 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
648 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
649 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
650 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
651 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
652 FIELD64(MSR_BITMAP
, msr_bitmap
),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
656 FIELD64(TSC_OFFSET
, tsc_offset
),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
658 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
659 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
660 FIELD64(EPT_POINTER
, ept_pointer
),
661 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
662 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
663 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
664 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
665 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
666 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
667 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
668 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
669 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
670 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
672 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
673 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
674 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
675 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
676 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
677 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
678 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
682 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
685 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
686 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
687 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
689 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
694 FIELD(TPR_THRESHOLD
, tpr_threshold
),
695 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
696 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
697 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
698 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
699 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
700 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
701 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
702 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
703 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
704 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
705 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
706 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
707 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
708 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
709 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
710 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
711 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
712 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
713 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
714 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
715 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
716 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
717 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
718 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
719 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
720 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
721 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
723 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
724 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
725 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
726 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
727 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
728 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
729 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
730 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
731 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
732 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
733 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
734 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
735 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
736 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
737 FIELD(GUEST_CR0
, guest_cr0
),
738 FIELD(GUEST_CR3
, guest_cr3
),
739 FIELD(GUEST_CR4
, guest_cr4
),
740 FIELD(GUEST_ES_BASE
, guest_es_base
),
741 FIELD(GUEST_CS_BASE
, guest_cs_base
),
742 FIELD(GUEST_SS_BASE
, guest_ss_base
),
743 FIELD(GUEST_DS_BASE
, guest_ds_base
),
744 FIELD(GUEST_FS_BASE
, guest_fs_base
),
745 FIELD(GUEST_GS_BASE
, guest_gs_base
),
746 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
747 FIELD(GUEST_TR_BASE
, guest_tr_base
),
748 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
749 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
750 FIELD(GUEST_DR7
, guest_dr7
),
751 FIELD(GUEST_RSP
, guest_rsp
),
752 FIELD(GUEST_RIP
, guest_rip
),
753 FIELD(GUEST_RFLAGS
, guest_rflags
),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
755 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
756 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
757 FIELD(HOST_CR0
, host_cr0
),
758 FIELD(HOST_CR3
, host_cr3
),
759 FIELD(HOST_CR4
, host_cr4
),
760 FIELD(HOST_FS_BASE
, host_fs_base
),
761 FIELD(HOST_GS_BASE
, host_gs_base
),
762 FIELD(HOST_TR_BASE
, host_tr_base
),
763 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
764 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
765 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
766 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
767 FIELD(HOST_RSP
, host_rsp
),
768 FIELD(HOST_RIP
, host_rip
),
771 static inline short vmcs_field_to_offset(unsigned long field
)
773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
775 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
776 vmcs_field_to_offset_table
[field
] == 0)
779 return vmcs_field_to_offset_table
[field
];
782 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
784 return to_vmx(vcpu
)->nested
.current_vmcs12
;
787 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
789 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
790 if (is_error_page(page
))
796 static void nested_release_page(struct page
*page
)
798 kvm_release_page_dirty(page
);
801 static void nested_release_page_clean(struct page
*page
)
803 kvm_release_page_clean(page
);
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
807 static u64
construct_eptp(unsigned long root_hpa
);
808 static void kvm_cpu_vmxon(u64 addr
);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm
*kvm
);
813 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
);
814 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
815 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
816 struct kvm_segment
*var
, int seg
);
817 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
818 struct kvm_segment
*var
, int seg
);
819 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
820 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
821 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
822 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
823 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
824 static int alloc_identity_pagetable(struct kvm
*kvm
);
826 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
827 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
829 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
830 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
832 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
833 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
835 static unsigned long *vmx_io_bitmap_a
;
836 static unsigned long *vmx_io_bitmap_b
;
837 static unsigned long *vmx_msr_bitmap_legacy
;
838 static unsigned long *vmx_msr_bitmap_longmode
;
839 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
840 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
841 static unsigned long *vmx_msr_bitmap_nested
;
842 static unsigned long *vmx_vmread_bitmap
;
843 static unsigned long *vmx_vmwrite_bitmap
;
845 static bool cpu_has_load_ia32_efer
;
846 static bool cpu_has_load_perf_global_ctrl
;
848 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
849 static DEFINE_SPINLOCK(vmx_vpid_lock
);
851 static struct vmcs_config
{
855 u32 pin_based_exec_ctrl
;
856 u32 cpu_based_exec_ctrl
;
857 u32 cpu_based_2nd_exec_ctrl
;
862 static struct vmx_capability
{
867 #define VMX_SEGMENT_FIELD(seg) \
868 [VCPU_SREG_##seg] = { \
869 .selector = GUEST_##seg##_SELECTOR, \
870 .base = GUEST_##seg##_BASE, \
871 .limit = GUEST_##seg##_LIMIT, \
872 .ar_bytes = GUEST_##seg##_AR_BYTES, \
875 static const struct kvm_vmx_segment_field
{
880 } kvm_vmx_segment_fields
[] = {
881 VMX_SEGMENT_FIELD(CS
),
882 VMX_SEGMENT_FIELD(DS
),
883 VMX_SEGMENT_FIELD(ES
),
884 VMX_SEGMENT_FIELD(FS
),
885 VMX_SEGMENT_FIELD(GS
),
886 VMX_SEGMENT_FIELD(SS
),
887 VMX_SEGMENT_FIELD(TR
),
888 VMX_SEGMENT_FIELD(LDTR
),
891 static u64 host_efer
;
893 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
896 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
897 * away by decrementing the array size.
899 static const u32 vmx_msr_index
[] = {
901 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
903 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
906 static inline bool is_page_fault(u32 intr_info
)
908 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
909 INTR_INFO_VALID_MASK
)) ==
910 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
913 static inline bool is_no_device(u32 intr_info
)
915 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
916 INTR_INFO_VALID_MASK
)) ==
917 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
920 static inline bool is_invalid_opcode(u32 intr_info
)
922 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
923 INTR_INFO_VALID_MASK
)) ==
924 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
927 static inline bool is_external_interrupt(u32 intr_info
)
929 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
930 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
933 static inline bool is_machine_check(u32 intr_info
)
935 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
936 INTR_INFO_VALID_MASK
)) ==
937 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
940 static inline bool cpu_has_vmx_msr_bitmap(void)
942 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
945 static inline bool cpu_has_vmx_tpr_shadow(void)
947 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
950 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
952 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
955 static inline bool cpu_has_secondary_exec_ctrls(void)
957 return vmcs_config
.cpu_based_exec_ctrl
&
958 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
961 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
963 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
964 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
967 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
969 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
970 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
973 static inline bool cpu_has_vmx_apic_register_virt(void)
975 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
976 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
979 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
981 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
982 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
985 static inline bool cpu_has_vmx_posted_intr(void)
987 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
990 static inline bool cpu_has_vmx_apicv(void)
992 return cpu_has_vmx_apic_register_virt() &&
993 cpu_has_vmx_virtual_intr_delivery() &&
994 cpu_has_vmx_posted_intr();
997 static inline bool cpu_has_vmx_flexpriority(void)
999 return cpu_has_vmx_tpr_shadow() &&
1000 cpu_has_vmx_virtualize_apic_accesses();
1003 static inline bool cpu_has_vmx_ept_execute_only(void)
1005 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1008 static inline bool cpu_has_vmx_ept_2m_page(void)
1010 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1013 static inline bool cpu_has_vmx_ept_1g_page(void)
1015 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1018 static inline bool cpu_has_vmx_ept_4levels(void)
1020 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1023 static inline bool cpu_has_vmx_ept_ad_bits(void)
1025 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1028 static inline bool cpu_has_vmx_invept_context(void)
1030 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1033 static inline bool cpu_has_vmx_invept_global(void)
1035 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1038 static inline bool cpu_has_vmx_invvpid_single(void)
1040 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1043 static inline bool cpu_has_vmx_invvpid_global(void)
1045 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1048 static inline bool cpu_has_vmx_ept(void)
1050 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1051 SECONDARY_EXEC_ENABLE_EPT
;
1054 static inline bool cpu_has_vmx_unrestricted_guest(void)
1056 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1057 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1060 static inline bool cpu_has_vmx_ple(void)
1062 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1063 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1066 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1068 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1071 static inline bool cpu_has_vmx_vpid(void)
1073 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1074 SECONDARY_EXEC_ENABLE_VPID
;
1077 static inline bool cpu_has_vmx_rdtscp(void)
1079 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1080 SECONDARY_EXEC_RDTSCP
;
1083 static inline bool cpu_has_vmx_invpcid(void)
1085 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1086 SECONDARY_EXEC_ENABLE_INVPCID
;
1089 static inline bool cpu_has_virtual_nmis(void)
1091 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1094 static inline bool cpu_has_vmx_wbinvd_exit(void)
1096 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1097 SECONDARY_EXEC_WBINVD_EXITING
;
1100 static inline bool cpu_has_vmx_shadow_vmcs(void)
1103 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1104 /* check if the cpu supports writing r/o exit information fields */
1105 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_SHADOW_VMCS
;
1112 static inline bool cpu_has_vmx_pml(void)
1114 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1117 static inline bool report_flexpriority(void)
1119 return flexpriority_enabled
;
1122 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1124 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1127 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1129 return (vmcs12
->cpu_based_vm_exec_control
&
1130 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1131 (vmcs12
->secondary_vm_exec_control
& bit
);
1134 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1136 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1139 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1141 return vmcs12
->pin_based_vm_exec_control
&
1142 PIN_BASED_VMX_PREEMPTION_TIMER
;
1145 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1147 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1150 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1152 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1153 vmx_xsaves_supported();
1156 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1158 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1161 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1163 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1166 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1168 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1171 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1173 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1176 static inline bool is_exception(u32 intr_info
)
1178 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1179 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1182 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1184 unsigned long exit_qualification
);
1185 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1186 struct vmcs12
*vmcs12
,
1187 u32 reason
, unsigned long qualification
);
1189 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1193 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1194 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1199 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1205 } operand
= { vpid
, 0, gva
};
1207 asm volatile (__ex(ASM_VMX_INVVPID
)
1208 /* CF==1 or ZF==1 --> rc = -1 */
1209 "; ja 1f ; ud2 ; 1:"
1210 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1213 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1217 } operand
= {eptp
, gpa
};
1219 asm volatile (__ex(ASM_VMX_INVEPT
)
1220 /* CF==1 or ZF==1 --> rc = -1 */
1221 "; ja 1f ; ud2 ; 1:\n"
1222 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1225 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1229 i
= __find_msr_index(vmx
, msr
);
1231 return &vmx
->guest_msrs
[i
];
1235 static void vmcs_clear(struct vmcs
*vmcs
)
1237 u64 phys_addr
= __pa(vmcs
);
1240 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1241 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1244 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1248 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1250 vmcs_clear(loaded_vmcs
->vmcs
);
1251 loaded_vmcs
->cpu
= -1;
1252 loaded_vmcs
->launched
= 0;
1255 static void vmcs_load(struct vmcs
*vmcs
)
1257 u64 phys_addr
= __pa(vmcs
);
1260 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1261 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1264 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1268 #ifdef CONFIG_KEXEC_CORE
1270 * This bitmap is used to indicate whether the vmclear
1271 * operation is enabled on all cpus. All disabled by
1274 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1276 static inline void crash_enable_local_vmclear(int cpu
)
1278 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1281 static inline void crash_disable_local_vmclear(int cpu
)
1283 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1286 static inline int crash_local_vmclear_enabled(int cpu
)
1288 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1291 static void crash_vmclear_local_loaded_vmcss(void)
1293 int cpu
= raw_smp_processor_id();
1294 struct loaded_vmcs
*v
;
1296 if (!crash_local_vmclear_enabled(cpu
))
1299 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1300 loaded_vmcss_on_cpu_link
)
1301 vmcs_clear(v
->vmcs
);
1304 static inline void crash_enable_local_vmclear(int cpu
) { }
1305 static inline void crash_disable_local_vmclear(int cpu
) { }
1306 #endif /* CONFIG_KEXEC_CORE */
1308 static void __loaded_vmcs_clear(void *arg
)
1310 struct loaded_vmcs
*loaded_vmcs
= arg
;
1311 int cpu
= raw_smp_processor_id();
1313 if (loaded_vmcs
->cpu
!= cpu
)
1314 return; /* vcpu migration can race with cpu offline */
1315 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1316 per_cpu(current_vmcs
, cpu
) = NULL
;
1317 crash_disable_local_vmclear(cpu
);
1318 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1321 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1322 * is before setting loaded_vmcs->vcpu to -1 which is done in
1323 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1324 * then adds the vmcs into percpu list before it is deleted.
1328 loaded_vmcs_init(loaded_vmcs
);
1329 crash_enable_local_vmclear(cpu
);
1332 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1334 int cpu
= loaded_vmcs
->cpu
;
1337 smp_call_function_single(cpu
,
1338 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1341 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1346 if (cpu_has_vmx_invvpid_single())
1347 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1350 static inline void vpid_sync_vcpu_global(void)
1352 if (cpu_has_vmx_invvpid_global())
1353 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1356 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1358 if (cpu_has_vmx_invvpid_single())
1359 vpid_sync_vcpu_single(vmx
);
1361 vpid_sync_vcpu_global();
1364 static inline void ept_sync_global(void)
1366 if (cpu_has_vmx_invept_global())
1367 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1370 static inline void ept_sync_context(u64 eptp
)
1373 if (cpu_has_vmx_invept_context())
1374 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1380 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1382 unsigned long value
;
1384 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1385 : "=a"(value
) : "d"(field
) : "cc");
1389 static __always_inline u16
vmcs_read16(unsigned long field
)
1391 return vmcs_readl(field
);
1394 static __always_inline u32
vmcs_read32(unsigned long field
)
1396 return vmcs_readl(field
);
1399 static __always_inline u64
vmcs_read64(unsigned long field
)
1401 #ifdef CONFIG_X86_64
1402 return vmcs_readl(field
);
1404 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1408 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1410 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1411 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1415 static void vmcs_writel(unsigned long field
, unsigned long value
)
1419 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1420 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1421 if (unlikely(error
))
1422 vmwrite_error(field
, value
);
1425 static void vmcs_write16(unsigned long field
, u16 value
)
1427 vmcs_writel(field
, value
);
1430 static void vmcs_write32(unsigned long field
, u32 value
)
1432 vmcs_writel(field
, value
);
1435 static void vmcs_write64(unsigned long field
, u64 value
)
1437 vmcs_writel(field
, value
);
1438 #ifndef CONFIG_X86_64
1440 vmcs_writel(field
+1, value
>> 32);
1444 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1446 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1449 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1451 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1454 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1456 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1457 vmx
->vm_entry_controls_shadow
= val
;
1460 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1462 if (vmx
->vm_entry_controls_shadow
!= val
)
1463 vm_entry_controls_init(vmx
, val
);
1466 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1468 return vmx
->vm_entry_controls_shadow
;
1472 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1474 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1477 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1479 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1482 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1484 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1485 vmx
->vm_exit_controls_shadow
= val
;
1488 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1490 if (vmx
->vm_exit_controls_shadow
!= val
)
1491 vm_exit_controls_init(vmx
, val
);
1494 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1496 return vmx
->vm_exit_controls_shadow
;
1500 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1502 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1505 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1507 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1510 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1512 vmx
->segment_cache
.bitmask
= 0;
1515 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1519 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1521 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1522 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1523 vmx
->segment_cache
.bitmask
= 0;
1525 ret
= vmx
->segment_cache
.bitmask
& mask
;
1526 vmx
->segment_cache
.bitmask
|= mask
;
1530 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1532 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1534 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1535 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1539 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1541 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1543 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1544 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1548 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1550 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1552 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1553 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1557 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1559 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1561 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1562 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1566 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1570 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1571 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1572 if ((vcpu
->guest_debug
&
1573 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1574 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1575 eb
|= 1u << BP_VECTOR
;
1576 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1579 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1580 if (vcpu
->fpu_active
)
1581 eb
&= ~(1u << NM_VECTOR
);
1583 /* When we are running a nested L2 guest and L1 specified for it a
1584 * certain exception bitmap, we must trap the same exceptions and pass
1585 * them to L1. When running L2, we will only handle the exceptions
1586 * specified above if L1 did not want them.
1588 if (is_guest_mode(vcpu
))
1589 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1591 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1594 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1595 unsigned long entry
, unsigned long exit
)
1597 vm_entry_controls_clearbit(vmx
, entry
);
1598 vm_exit_controls_clearbit(vmx
, exit
);
1601 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1604 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1608 if (cpu_has_load_ia32_efer
) {
1609 clear_atomic_switch_msr_special(vmx
,
1610 VM_ENTRY_LOAD_IA32_EFER
,
1611 VM_EXIT_LOAD_IA32_EFER
);
1615 case MSR_CORE_PERF_GLOBAL_CTRL
:
1616 if (cpu_has_load_perf_global_ctrl
) {
1617 clear_atomic_switch_msr_special(vmx
,
1618 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1619 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1625 for (i
= 0; i
< m
->nr
; ++i
)
1626 if (m
->guest
[i
].index
== msr
)
1632 m
->guest
[i
] = m
->guest
[m
->nr
];
1633 m
->host
[i
] = m
->host
[m
->nr
];
1634 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1635 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1638 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1639 unsigned long entry
, unsigned long exit
,
1640 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1641 u64 guest_val
, u64 host_val
)
1643 vmcs_write64(guest_val_vmcs
, guest_val
);
1644 vmcs_write64(host_val_vmcs
, host_val
);
1645 vm_entry_controls_setbit(vmx
, entry
);
1646 vm_exit_controls_setbit(vmx
, exit
);
1649 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1650 u64 guest_val
, u64 host_val
)
1653 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1657 if (cpu_has_load_ia32_efer
) {
1658 add_atomic_switch_msr_special(vmx
,
1659 VM_ENTRY_LOAD_IA32_EFER
,
1660 VM_EXIT_LOAD_IA32_EFER
,
1663 guest_val
, host_val
);
1667 case MSR_CORE_PERF_GLOBAL_CTRL
:
1668 if (cpu_has_load_perf_global_ctrl
) {
1669 add_atomic_switch_msr_special(vmx
,
1670 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1671 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1672 GUEST_IA32_PERF_GLOBAL_CTRL
,
1673 HOST_IA32_PERF_GLOBAL_CTRL
,
1674 guest_val
, host_val
);
1680 for (i
= 0; i
< m
->nr
; ++i
)
1681 if (m
->guest
[i
].index
== msr
)
1684 if (i
== NR_AUTOLOAD_MSRS
) {
1685 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1686 "Can't add msr %x\n", msr
);
1688 } else if (i
== m
->nr
) {
1690 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1691 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1694 m
->guest
[i
].index
= msr
;
1695 m
->guest
[i
].value
= guest_val
;
1696 m
->host
[i
].index
= msr
;
1697 m
->host
[i
].value
= host_val
;
1700 static void reload_tss(void)
1703 * VT restores TR but not its size. Useless.
1705 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1706 struct desc_struct
*descs
;
1708 descs
= (void *)gdt
->address
;
1709 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1713 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1718 guest_efer
= vmx
->vcpu
.arch
.efer
;
1721 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1724 ignore_bits
= EFER_NX
| EFER_SCE
;
1725 #ifdef CONFIG_X86_64
1726 ignore_bits
|= EFER_LMA
| EFER_LME
;
1727 /* SCE is meaningful only in long mode on Intel */
1728 if (guest_efer
& EFER_LMA
)
1729 ignore_bits
&= ~(u64
)EFER_SCE
;
1731 guest_efer
&= ~ignore_bits
;
1732 guest_efer
|= host_efer
& ignore_bits
;
1733 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1734 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1736 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1739 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1740 * On CPUs that support "load IA32_EFER", always switch EFER
1741 * atomically, since it's faster than switching it manually.
1743 if (cpu_has_load_ia32_efer
||
1744 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1745 guest_efer
= vmx
->vcpu
.arch
.efer
;
1746 if (!(guest_efer
& EFER_LMA
))
1747 guest_efer
&= ~EFER_LME
;
1748 if (guest_efer
!= host_efer
)
1749 add_atomic_switch_msr(vmx
, MSR_EFER
,
1750 guest_efer
, host_efer
);
1757 static unsigned long segment_base(u16 selector
)
1759 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1760 struct desc_struct
*d
;
1761 unsigned long table_base
;
1764 if (!(selector
& ~3))
1767 table_base
= gdt
->address
;
1769 if (selector
& 4) { /* from ldt */
1770 u16 ldt_selector
= kvm_read_ldt();
1772 if (!(ldt_selector
& ~3))
1775 table_base
= segment_base(ldt_selector
);
1777 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1778 v
= get_desc_base(d
);
1779 #ifdef CONFIG_X86_64
1780 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1781 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1786 static inline unsigned long kvm_read_tr_base(void)
1789 asm("str %0" : "=g"(tr
));
1790 return segment_base(tr
);
1793 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1795 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1798 if (vmx
->host_state
.loaded
)
1801 vmx
->host_state
.loaded
= 1;
1803 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1804 * allow segment selectors with cpl > 0 or ti == 1.
1806 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1807 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1808 savesegment(fs
, vmx
->host_state
.fs_sel
);
1809 if (!(vmx
->host_state
.fs_sel
& 7)) {
1810 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1811 vmx
->host_state
.fs_reload_needed
= 0;
1813 vmcs_write16(HOST_FS_SELECTOR
, 0);
1814 vmx
->host_state
.fs_reload_needed
= 1;
1816 savesegment(gs
, vmx
->host_state
.gs_sel
);
1817 if (!(vmx
->host_state
.gs_sel
& 7))
1818 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1820 vmcs_write16(HOST_GS_SELECTOR
, 0);
1821 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1824 #ifdef CONFIG_X86_64
1825 savesegment(ds
, vmx
->host_state
.ds_sel
);
1826 savesegment(es
, vmx
->host_state
.es_sel
);
1829 #ifdef CONFIG_X86_64
1830 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1831 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1833 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1834 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1837 #ifdef CONFIG_X86_64
1838 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1839 if (is_long_mode(&vmx
->vcpu
))
1840 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1842 if (boot_cpu_has(X86_FEATURE_MPX
))
1843 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1844 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1845 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1846 vmx
->guest_msrs
[i
].data
,
1847 vmx
->guest_msrs
[i
].mask
);
1850 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1852 if (!vmx
->host_state
.loaded
)
1855 ++vmx
->vcpu
.stat
.host_state_reload
;
1856 vmx
->host_state
.loaded
= 0;
1857 #ifdef CONFIG_X86_64
1858 if (is_long_mode(&vmx
->vcpu
))
1859 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1861 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1862 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1863 #ifdef CONFIG_X86_64
1864 load_gs_index(vmx
->host_state
.gs_sel
);
1866 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1869 if (vmx
->host_state
.fs_reload_needed
)
1870 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1871 #ifdef CONFIG_X86_64
1872 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1873 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1874 loadsegment(es
, vmx
->host_state
.es_sel
);
1878 #ifdef CONFIG_X86_64
1879 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1881 if (vmx
->host_state
.msr_host_bndcfgs
)
1882 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1884 * If the FPU is not active (through the host task or
1885 * the guest vcpu), then restore the cr0.TS bit.
1887 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
1889 load_gdt(this_cpu_ptr(&host_gdt
));
1892 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1895 __vmx_load_host_state(vmx
);
1900 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1901 * vcpu mutex is already taken.
1903 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1905 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1906 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1909 kvm_cpu_vmxon(phys_addr
);
1910 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1911 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1913 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1914 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1915 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1918 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1919 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1920 unsigned long sysenter_esp
;
1922 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1923 local_irq_disable();
1924 crash_disable_local_vmclear(cpu
);
1927 * Read loaded_vmcs->cpu should be before fetching
1928 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1929 * See the comments in __loaded_vmcs_clear().
1933 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1934 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1935 crash_enable_local_vmclear(cpu
);
1939 * Linux uses per-cpu TSS and GDT, so set these when switching
1942 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1943 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1945 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1946 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1947 vmx
->loaded_vmcs
->cpu
= cpu
;
1951 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1953 __vmx_load_host_state(to_vmx(vcpu
));
1954 if (!vmm_exclusive
) {
1955 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1961 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1965 if (vcpu
->fpu_active
)
1967 vcpu
->fpu_active
= 1;
1968 cr0
= vmcs_readl(GUEST_CR0
);
1969 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1970 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1971 vmcs_writel(GUEST_CR0
, cr0
);
1972 update_exception_bitmap(vcpu
);
1973 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1974 if (is_guest_mode(vcpu
))
1975 vcpu
->arch
.cr0_guest_owned_bits
&=
1976 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1977 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1980 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1983 * Return the cr0 value that a nested guest would read. This is a combination
1984 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1985 * its hypervisor (cr0_read_shadow).
1987 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1989 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1990 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1992 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1994 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1995 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1998 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2000 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2001 * set this *before* calling this function.
2003 vmx_decache_cr0_guest_bits(vcpu
);
2004 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2005 update_exception_bitmap(vcpu
);
2006 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2007 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2008 if (is_guest_mode(vcpu
)) {
2010 * L1's specified read shadow might not contain the TS bit,
2011 * so now that we turned on shadowing of this bit, we need to
2012 * set this bit of the shadow. Like in nested_vmx_run we need
2013 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2014 * up-to-date here because we just decached cr0.TS (and we'll
2015 * only update vmcs12->guest_cr0 on nested exit).
2017 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2018 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2019 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2020 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2022 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2025 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2027 unsigned long rflags
, save_rflags
;
2029 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2030 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2031 rflags
= vmcs_readl(GUEST_RFLAGS
);
2032 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2033 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2034 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2035 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2037 to_vmx(vcpu
)->rflags
= rflags
;
2039 return to_vmx(vcpu
)->rflags
;
2042 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2044 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2045 to_vmx(vcpu
)->rflags
= rflags
;
2046 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2047 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2048 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2050 vmcs_writel(GUEST_RFLAGS
, rflags
);
2053 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2055 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2058 if (interruptibility
& GUEST_INTR_STATE_STI
)
2059 ret
|= KVM_X86_SHADOW_INT_STI
;
2060 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2061 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2066 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2068 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2069 u32 interruptibility
= interruptibility_old
;
2071 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2073 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2074 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2075 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2076 interruptibility
|= GUEST_INTR_STATE_STI
;
2078 if ((interruptibility
!= interruptibility_old
))
2079 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2082 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2086 rip
= kvm_rip_read(vcpu
);
2087 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2088 kvm_rip_write(vcpu
, rip
);
2090 /* skipping an emulated instruction also counts */
2091 vmx_set_interrupt_shadow(vcpu
, 0);
2095 * KVM wants to inject page-faults which it got to the guest. This function
2096 * checks whether in a nested guest, we need to inject them to L1 or L2.
2098 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2100 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2102 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2105 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2106 vmcs_read32(VM_EXIT_INTR_INFO
),
2107 vmcs_readl(EXIT_QUALIFICATION
));
2111 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2112 bool has_error_code
, u32 error_code
,
2115 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2116 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2118 if (!reinject
&& is_guest_mode(vcpu
) &&
2119 nested_vmx_check_exception(vcpu
, nr
))
2122 if (has_error_code
) {
2123 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2124 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2127 if (vmx
->rmode
.vm86_active
) {
2129 if (kvm_exception_is_soft(nr
))
2130 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2131 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2132 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2136 if (kvm_exception_is_soft(nr
)) {
2137 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2138 vmx
->vcpu
.arch
.event_exit_inst_len
);
2139 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2141 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2143 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2146 static bool vmx_rdtscp_supported(void)
2148 return cpu_has_vmx_rdtscp();
2151 static bool vmx_invpcid_supported(void)
2153 return cpu_has_vmx_invpcid() && enable_ept
;
2157 * Swap MSR entry in host/guest MSR entry array.
2159 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2161 struct shared_msr_entry tmp
;
2163 tmp
= vmx
->guest_msrs
[to
];
2164 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2165 vmx
->guest_msrs
[from
] = tmp
;
2168 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2170 unsigned long *msr_bitmap
;
2172 if (is_guest_mode(vcpu
))
2173 msr_bitmap
= vmx_msr_bitmap_nested
;
2174 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2175 if (is_long_mode(vcpu
))
2176 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2178 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2180 if (is_long_mode(vcpu
))
2181 msr_bitmap
= vmx_msr_bitmap_longmode
;
2183 msr_bitmap
= vmx_msr_bitmap_legacy
;
2186 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2194 static void setup_msrs(struct vcpu_vmx
*vmx
)
2196 int save_nmsrs
, index
;
2199 #ifdef CONFIG_X86_64
2200 if (is_long_mode(&vmx
->vcpu
)) {
2201 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2203 move_msr_up(vmx
, index
, save_nmsrs
++);
2204 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2206 move_msr_up(vmx
, index
, save_nmsrs
++);
2207 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2209 move_msr_up(vmx
, index
, save_nmsrs
++);
2210 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2211 if (index
>= 0 && vmx
->rdtscp_enabled
)
2212 move_msr_up(vmx
, index
, save_nmsrs
++);
2214 * MSR_STAR is only needed on long mode guests, and only
2215 * if efer.sce is enabled.
2217 index
= __find_msr_index(vmx
, MSR_STAR
);
2218 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2219 move_msr_up(vmx
, index
, save_nmsrs
++);
2222 index
= __find_msr_index(vmx
, MSR_EFER
);
2223 if (index
>= 0 && update_transition_efer(vmx
, index
))
2224 move_msr_up(vmx
, index
, save_nmsrs
++);
2226 vmx
->save_nmsrs
= save_nmsrs
;
2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx
->vcpu
);
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2236 static u64
guest_read_tsc(void)
2238 u64 host_tsc
, tsc_offset
;
2241 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2242 return host_tsc
+ tsc_offset
;
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2249 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2253 tsc_offset
= is_guest_mode(vcpu
) ?
2254 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2255 vmcs_read64(TSC_OFFSET
);
2256 return host_tsc
+ tsc_offset
;
2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
2263 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2268 if (user_tsc_khz
> tsc_khz
) {
2269 vcpu
->arch
.tsc_catchup
= 1;
2270 vcpu
->arch
.tsc_always_catchup
= 1;
2272 WARN(1, "user requested TSC rate below hardware speed\n");
2275 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2277 return vmcs_read64(TSC_OFFSET
);
2281 * writes 'offset' into guest's timestamp counter offset register
2283 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2285 if (is_guest_mode(vcpu
)) {
2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
2292 struct vmcs12
*vmcs12
;
2293 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12
= get_vmcs12(vcpu
);
2296 vmcs_write64(TSC_OFFSET
, offset
+
2297 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2298 vmcs12
->tsc_offset
: 0));
2300 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2301 vmcs_read64(TSC_OFFSET
), offset
);
2302 vmcs_write64(TSC_OFFSET
, offset
);
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2308 u64 offset
= vmcs_read64(TSC_OFFSET
);
2310 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2311 if (is_guest_mode(vcpu
)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2315 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2316 offset
+ adjustment
);
2319 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2321 return target_tsc
- rdtsc();
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2326 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2327 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2338 return nested
&& guest_cpuid_has_vmx(vcpu
);
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2368 /* pin-based controls */
2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2370 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2371 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2372 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2374 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2375 PIN_BASED_EXT_INTR_MASK
|
2376 PIN_BASED_NMI_EXITING
|
2377 PIN_BASED_VIRTUAL_NMIS
;
2378 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2380 PIN_BASED_VMX_PREEMPTION_TIMER
;
2381 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
2382 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2383 PIN_BASED_POSTED_INTR
;
2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2387 vmx
->nested
.nested_vmx_exit_ctls_low
,
2388 vmx
->nested
.nested_vmx_exit_ctls_high
);
2389 vmx
->nested
.nested_vmx_exit_ctls_low
=
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2392 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2393 #ifdef CONFIG_X86_64
2394 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2396 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2397 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2399 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2402 if (vmx_mpx_supported())
2403 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2405 /* We support free control of debug control saving. */
2406 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2407 vmx
->nested
.nested_vmx_exit_ctls_low
&
2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2412 vmx
->nested
.nested_vmx_entry_ctls_low
,
2413 vmx
->nested
.nested_vmx_entry_ctls_high
);
2414 vmx
->nested
.nested_vmx_entry_ctls_low
=
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2416 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2417 #ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE
|
2420 VM_ENTRY_LOAD_IA32_PAT
;
2421 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2423 if (vmx_mpx_supported())
2424 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2426 /* We support free control of debug control loading. */
2427 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2428 vmx
->nested
.nested_vmx_entry_ctls_low
&
2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2433 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2434 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2435 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2437 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2438 CPU_BASED_VIRTUAL_INTR_PENDING
|
2439 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2440 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2441 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2442 CPU_BASED_CR3_STORE_EXITING
|
2443 #ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2446 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2447 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2448 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2449 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2450 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2457 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2459 CPU_BASED_USE_MSR_BITMAPS
;
2461 /* We support free control of CR3 access interception. */
2462 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2463 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2464 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2468 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2469 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2470 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2471 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2473 SECONDARY_EXEC_RDTSCP
|
2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2475 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2477 SECONDARY_EXEC_WBINVD_EXITING
|
2478 SECONDARY_EXEC_XSAVES
;
2481 /* nested EPT: emulate EPT also to L1 */
2482 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2483 SECONDARY_EXEC_ENABLE_EPT
;
2484 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2485 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2487 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
2493 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2495 vmx
->nested
.nested_vmx_ept_caps
= 0;
2497 if (enable_unrestricted_guest
)
2498 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2501 /* miscellaneous data */
2502 rdmsr(MSR_IA32_VMX_MISC
,
2503 vmx
->nested
.nested_vmx_misc_low
,
2504 vmx
->nested
.nested_vmx_misc_high
);
2505 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2506 vmx
->nested
.nested_vmx_misc_low
|=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2508 VMX_MISC_ACTIVITY_HLT
;
2509 vmx
->nested
.nested_vmx_misc_high
= 0;
2512 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2517 return ((control
& high
) | low
) == control
;
2520 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2522 return low
| ((u64
)high
<< 32);
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2528 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2530 switch (msr_index
) {
2531 case MSR_IA32_VMX_BASIC
:
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2538 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2539 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2540 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2543 case MSR_IA32_VMX_PINBASED_CTLS
:
2544 *pdata
= vmx_control_msr(
2545 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2546 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2549 *pdata
= vmx_control_msr(
2550 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2551 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2553 case MSR_IA32_VMX_PROCBASED_CTLS
:
2554 *pdata
= vmx_control_msr(
2555 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2556 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2559 *pdata
= vmx_control_msr(
2560 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2561 vmx
->nested
.nested_vmx_exit_ctls_high
);
2563 case MSR_IA32_VMX_EXIT_CTLS
:
2564 *pdata
= vmx_control_msr(
2565 vmx
->nested
.nested_vmx_exit_ctls_low
,
2566 vmx
->nested
.nested_vmx_exit_ctls_high
);
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2569 *pdata
= vmx_control_msr(
2570 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2571 vmx
->nested
.nested_vmx_entry_ctls_high
);
2573 case MSR_IA32_VMX_ENTRY_CTLS
:
2574 *pdata
= vmx_control_msr(
2575 vmx
->nested
.nested_vmx_entry_ctls_low
,
2576 vmx
->nested
.nested_vmx_entry_ctls_high
);
2578 case MSR_IA32_VMX_MISC
:
2579 *pdata
= vmx_control_msr(
2580 vmx
->nested
.nested_vmx_misc_low
,
2581 vmx
->nested
.nested_vmx_misc_high
);
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2588 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0
:
2591 *pdata
= VMXON_CR0_ALWAYSON
;
2593 case MSR_IA32_VMX_CR0_FIXED1
:
2596 case MSR_IA32_VMX_CR4_FIXED0
:
2597 *pdata
= VMXON_CR4_ALWAYSON
;
2599 case MSR_IA32_VMX_CR4_FIXED1
:
2602 case MSR_IA32_VMX_VMCS_ENUM
:
2603 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2605 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2606 *pdata
= vmx_control_msr(
2607 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2608 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2610 case MSR_IA32_VMX_EPT_VPID_CAP
:
2611 /* Currently, no nested vpid support */
2612 *pdata
= vmx
->nested
.nested_vmx_ept_caps
;
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2626 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2628 struct shared_msr_entry
*msr
;
2630 switch (msr_info
->index
) {
2631 #ifdef CONFIG_X86_64
2633 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2636 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2638 case MSR_KERNEL_GS_BASE
:
2639 vmx_load_host_state(to_vmx(vcpu
));
2640 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2644 return kvm_get_msr_common(vcpu
, msr_info
);
2646 msr_info
->data
= guest_read_tsc();
2648 case MSR_IA32_SYSENTER_CS
:
2649 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2651 case MSR_IA32_SYSENTER_EIP
:
2652 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2654 case MSR_IA32_SYSENTER_ESP
:
2655 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2657 case MSR_IA32_BNDCFGS
:
2658 if (!vmx_mpx_supported())
2660 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2662 case MSR_IA32_FEATURE_CONTROL
:
2663 if (!nested_vmx_allowed(vcpu
))
2665 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2667 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2668 if (!nested_vmx_allowed(vcpu
))
2670 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2672 if (!vmx_xsaves_supported())
2674 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2677 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2679 /* Otherwise falls through */
2681 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2683 msr_info
->data
= msr
->data
;
2686 return kvm_get_msr_common(vcpu
, msr_info
);
2692 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2695 * Writes msr value into into the appropriate "register".
2696 * Returns 0 on success, non-0 otherwise.
2697 * Assumes vcpu_load() was already called.
2699 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2701 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2702 struct shared_msr_entry
*msr
;
2704 u32 msr_index
= msr_info
->index
;
2705 u64 data
= msr_info
->data
;
2707 switch (msr_index
) {
2709 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2711 #ifdef CONFIG_X86_64
2713 vmx_segment_cache_clear(vmx
);
2714 vmcs_writel(GUEST_FS_BASE
, data
);
2717 vmx_segment_cache_clear(vmx
);
2718 vmcs_writel(GUEST_GS_BASE
, data
);
2720 case MSR_KERNEL_GS_BASE
:
2721 vmx_load_host_state(vmx
);
2722 vmx
->msr_guest_kernel_gs_base
= data
;
2725 case MSR_IA32_SYSENTER_CS
:
2726 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2728 case MSR_IA32_SYSENTER_EIP
:
2729 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2731 case MSR_IA32_SYSENTER_ESP
:
2732 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2734 case MSR_IA32_BNDCFGS
:
2735 if (!vmx_mpx_supported())
2737 vmcs_write64(GUEST_BNDCFGS
, data
);
2740 kvm_write_tsc(vcpu
, msr_info
);
2742 case MSR_IA32_CR_PAT
:
2743 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2744 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2746 vmcs_write64(GUEST_IA32_PAT
, data
);
2747 vcpu
->arch
.pat
= data
;
2750 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2752 case MSR_IA32_TSC_ADJUST
:
2753 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2755 case MSR_IA32_FEATURE_CONTROL
:
2756 if (!nested_vmx_allowed(vcpu
) ||
2757 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2758 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2760 vmx
->nested
.msr_ia32_feature_control
= data
;
2761 if (msr_info
->host_initiated
&& data
== 0)
2762 vmx_leave_nested(vcpu
);
2764 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2765 return 1; /* they are read-only */
2767 if (!vmx_xsaves_supported())
2770 * The only supported bit as of Skylake is bit 8, but
2771 * it is not supported on KVM.
2775 vcpu
->arch
.ia32_xss
= data
;
2776 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2777 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2778 vcpu
->arch
.ia32_xss
, host_xss
);
2780 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2783 if (!vmx
->rdtscp_enabled
)
2785 /* Check reserved bit, higher 32 bits should be zero */
2786 if ((data
>> 32) != 0)
2788 /* Otherwise falls through */
2790 msr
= find_msr_entry(vmx
, msr_index
);
2792 u64 old_msr_data
= msr
->data
;
2794 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2796 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2800 msr
->data
= old_msr_data
;
2804 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2810 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2812 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2815 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2818 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2820 case VCPU_EXREG_PDPTR
:
2822 ept_save_pdptrs(vcpu
);
2829 static __init
int cpu_has_kvm_support(void)
2831 return cpu_has_vmx();
2834 static __init
int vmx_disabled_by_bios(void)
2838 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2839 if (msr
& FEATURE_CONTROL_LOCKED
) {
2840 /* launched w/ TXT and VMX disabled */
2841 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2844 /* launched w/o TXT and VMX only enabled w/ TXT */
2845 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2846 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2847 && !tboot_enabled()) {
2848 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2849 "activate TXT before enabling KVM\n");
2852 /* launched w/o TXT and VMX disabled */
2853 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2854 && !tboot_enabled())
2861 static void kvm_cpu_vmxon(u64 addr
)
2863 asm volatile (ASM_VMX_VMXON_RAX
2864 : : "a"(&addr
), "m"(addr
)
2868 static int hardware_enable(void)
2870 int cpu
= raw_smp_processor_id();
2871 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2874 if (cr4_read_shadow() & X86_CR4_VMXE
)
2877 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2880 * Now we can enable the vmclear operation in kdump
2881 * since the loaded_vmcss_on_cpu list on this cpu
2882 * has been initialized.
2884 * Though the cpu is not in VMX operation now, there
2885 * is no problem to enable the vmclear operation
2886 * for the loaded_vmcss_on_cpu list is empty!
2888 crash_enable_local_vmclear(cpu
);
2890 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2892 test_bits
= FEATURE_CONTROL_LOCKED
;
2893 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2894 if (tboot_enabled())
2895 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2897 if ((old
& test_bits
) != test_bits
) {
2898 /* enable and lock */
2899 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2901 cr4_set_bits(X86_CR4_VMXE
);
2903 if (vmm_exclusive
) {
2904 kvm_cpu_vmxon(phys_addr
);
2908 native_store_gdt(this_cpu_ptr(&host_gdt
));
2913 static void vmclear_local_loaded_vmcss(void)
2915 int cpu
= raw_smp_processor_id();
2916 struct loaded_vmcs
*v
, *n
;
2918 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2919 loaded_vmcss_on_cpu_link
)
2920 __loaded_vmcs_clear(v
);
2924 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2927 static void kvm_cpu_vmxoff(void)
2929 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2932 static void hardware_disable(void)
2934 if (vmm_exclusive
) {
2935 vmclear_local_loaded_vmcss();
2938 cr4_clear_bits(X86_CR4_VMXE
);
2941 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2942 u32 msr
, u32
*result
)
2944 u32 vmx_msr_low
, vmx_msr_high
;
2945 u32 ctl
= ctl_min
| ctl_opt
;
2947 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2949 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2950 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2952 /* Ensure minimum (required) set of control bits are supported. */
2960 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2962 u32 vmx_msr_low
, vmx_msr_high
;
2964 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2965 return vmx_msr_high
& ctl
;
2968 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2970 u32 vmx_msr_low
, vmx_msr_high
;
2971 u32 min
, opt
, min2
, opt2
;
2972 u32 _pin_based_exec_control
= 0;
2973 u32 _cpu_based_exec_control
= 0;
2974 u32 _cpu_based_2nd_exec_control
= 0;
2975 u32 _vmexit_control
= 0;
2976 u32 _vmentry_control
= 0;
2978 min
= CPU_BASED_HLT_EXITING
|
2979 #ifdef CONFIG_X86_64
2980 CPU_BASED_CR8_LOAD_EXITING
|
2981 CPU_BASED_CR8_STORE_EXITING
|
2983 CPU_BASED_CR3_LOAD_EXITING
|
2984 CPU_BASED_CR3_STORE_EXITING
|
2985 CPU_BASED_USE_IO_BITMAPS
|
2986 CPU_BASED_MOV_DR_EXITING
|
2987 CPU_BASED_USE_TSC_OFFSETING
|
2988 CPU_BASED_MWAIT_EXITING
|
2989 CPU_BASED_MONITOR_EXITING
|
2990 CPU_BASED_INVLPG_EXITING
|
2991 CPU_BASED_RDPMC_EXITING
;
2993 opt
= CPU_BASED_TPR_SHADOW
|
2994 CPU_BASED_USE_MSR_BITMAPS
|
2995 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2996 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2997 &_cpu_based_exec_control
) < 0)
2999 #ifdef CONFIG_X86_64
3000 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3001 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3002 ~CPU_BASED_CR8_STORE_EXITING
;
3004 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3006 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3007 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3008 SECONDARY_EXEC_WBINVD_EXITING
|
3009 SECONDARY_EXEC_ENABLE_VPID
|
3010 SECONDARY_EXEC_ENABLE_EPT
|
3011 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3012 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3013 SECONDARY_EXEC_RDTSCP
|
3014 SECONDARY_EXEC_ENABLE_INVPCID
|
3015 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3016 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3017 SECONDARY_EXEC_SHADOW_VMCS
|
3018 SECONDARY_EXEC_XSAVES
|
3019 SECONDARY_EXEC_ENABLE_PML
;
3020 if (adjust_vmx_controls(min2
, opt2
,
3021 MSR_IA32_VMX_PROCBASED_CTLS2
,
3022 &_cpu_based_2nd_exec_control
) < 0)
3025 #ifndef CONFIG_X86_64
3026 if (!(_cpu_based_2nd_exec_control
&
3027 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3028 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3031 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3032 _cpu_based_2nd_exec_control
&= ~(
3033 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3034 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3035 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3037 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3038 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3040 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3041 CPU_BASED_CR3_STORE_EXITING
|
3042 CPU_BASED_INVLPG_EXITING
);
3043 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3044 vmx_capability
.ept
, vmx_capability
.vpid
);
3047 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3048 #ifdef CONFIG_X86_64
3049 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3051 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3052 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3053 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3054 &_vmexit_control
) < 0)
3057 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3058 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3059 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3060 &_pin_based_exec_control
) < 0)
3063 if (!(_cpu_based_2nd_exec_control
&
3064 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3065 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3066 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3068 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3069 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3070 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3071 &_vmentry_control
) < 0)
3074 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3076 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3077 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3080 #ifdef CONFIG_X86_64
3081 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3082 if (vmx_msr_high
& (1u<<16))
3086 /* Require Write-Back (WB) memory type for VMCS accesses. */
3087 if (((vmx_msr_high
>> 18) & 15) != 6)
3090 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3091 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3092 vmcs_conf
->revision_id
= vmx_msr_low
;
3094 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3095 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3096 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3097 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3098 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3100 cpu_has_load_ia32_efer
=
3101 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3102 VM_ENTRY_LOAD_IA32_EFER
)
3103 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3104 VM_EXIT_LOAD_IA32_EFER
);
3106 cpu_has_load_perf_global_ctrl
=
3107 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3108 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3109 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3110 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3113 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3114 * but due to arrata below it can't be used. Workaround is to use
3115 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3117 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3122 * BC86,AAY89,BD102 (model 44)
3126 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3127 switch (boot_cpu_data
.x86_model
) {
3133 cpu_has_load_perf_global_ctrl
= false;
3134 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3135 "does not work properly. Using workaround\n");
3143 rdmsrl(MSR_IA32_XSS
, host_xss
);
3148 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3150 int node
= cpu_to_node(cpu
);
3154 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3157 vmcs
= page_address(pages
);
3158 memset(vmcs
, 0, vmcs_config
.size
);
3159 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3163 static struct vmcs
*alloc_vmcs(void)
3165 return alloc_vmcs_cpu(raw_smp_processor_id());
3168 static void free_vmcs(struct vmcs
*vmcs
)
3170 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3174 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3176 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3178 if (!loaded_vmcs
->vmcs
)
3180 loaded_vmcs_clear(loaded_vmcs
);
3181 free_vmcs(loaded_vmcs
->vmcs
);
3182 loaded_vmcs
->vmcs
= NULL
;
3185 static void free_kvm_area(void)
3189 for_each_possible_cpu(cpu
) {
3190 free_vmcs(per_cpu(vmxarea
, cpu
));
3191 per_cpu(vmxarea
, cpu
) = NULL
;
3195 static void init_vmcs_shadow_fields(void)
3199 /* No checks for read only fields yet */
3201 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3202 switch (shadow_read_write_fields
[i
]) {
3204 if (!vmx_mpx_supported())
3212 shadow_read_write_fields
[j
] =
3213 shadow_read_write_fields
[i
];
3216 max_shadow_read_write_fields
= j
;
3218 /* shadowed fields guest access without vmexit */
3219 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3220 clear_bit(shadow_read_write_fields
[i
],
3221 vmx_vmwrite_bitmap
);
3222 clear_bit(shadow_read_write_fields
[i
],
3225 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3226 clear_bit(shadow_read_only_fields
[i
],
3230 static __init
int alloc_kvm_area(void)
3234 for_each_possible_cpu(cpu
) {
3237 vmcs
= alloc_vmcs_cpu(cpu
);
3243 per_cpu(vmxarea
, cpu
) = vmcs
;
3248 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3250 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3253 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3254 struct kvm_segment
*save
)
3256 if (!emulate_invalid_guest_state
) {
3258 * CS and SS RPL should be equal during guest entry according
3259 * to VMX spec, but in reality it is not always so. Since vcpu
3260 * is in the middle of the transition from real mode to
3261 * protected mode it is safe to assume that RPL 0 is a good
3264 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3265 save
->selector
&= ~SEGMENT_RPL_MASK
;
3266 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3269 vmx_set_segment(vcpu
, save
, seg
);
3272 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3274 unsigned long flags
;
3275 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3278 * Update real mode segment cache. It may be not up-to-date if sement
3279 * register was written while vcpu was in a guest mode.
3281 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3282 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3283 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3284 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3285 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3286 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3288 vmx
->rmode
.vm86_active
= 0;
3290 vmx_segment_cache_clear(vmx
);
3292 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3294 flags
= vmcs_readl(GUEST_RFLAGS
);
3295 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3296 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3297 vmcs_writel(GUEST_RFLAGS
, flags
);
3299 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3300 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3302 update_exception_bitmap(vcpu
);
3304 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3305 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3306 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3307 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3308 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3309 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3312 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3314 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3315 struct kvm_segment var
= *save
;
3318 if (seg
== VCPU_SREG_CS
)
3321 if (!emulate_invalid_guest_state
) {
3322 var
.selector
= var
.base
>> 4;
3323 var
.base
= var
.base
& 0xffff0;
3333 if (save
->base
& 0xf)
3334 printk_once(KERN_WARNING
"kvm: segment base is not "
3335 "paragraph aligned when entering "
3336 "protected mode (seg=%d)", seg
);
3339 vmcs_write16(sf
->selector
, var
.selector
);
3340 vmcs_write32(sf
->base
, var
.base
);
3341 vmcs_write32(sf
->limit
, var
.limit
);
3342 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3345 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3347 unsigned long flags
;
3348 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3350 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3351 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3352 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3353 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3354 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3355 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3356 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3358 vmx
->rmode
.vm86_active
= 1;
3361 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3362 * vcpu. Warn the user that an update is overdue.
3364 if (!vcpu
->kvm
->arch
.tss_addr
)
3365 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3366 "called before entering vcpu\n");
3368 vmx_segment_cache_clear(vmx
);
3370 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3371 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3372 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3374 flags
= vmcs_readl(GUEST_RFLAGS
);
3375 vmx
->rmode
.save_rflags
= flags
;
3377 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3379 vmcs_writel(GUEST_RFLAGS
, flags
);
3380 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3381 update_exception_bitmap(vcpu
);
3383 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3384 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3385 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3386 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3387 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3388 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3390 kvm_mmu_reset_context(vcpu
);
3393 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3395 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3396 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3402 * Force kernel_gs_base reloading before EFER changes, as control
3403 * of this msr depends on is_long_mode().
3405 vmx_load_host_state(to_vmx(vcpu
));
3406 vcpu
->arch
.efer
= efer
;
3407 if (efer
& EFER_LMA
) {
3408 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3411 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3413 msr
->data
= efer
& ~EFER_LME
;
3418 #ifdef CONFIG_X86_64
3420 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3424 vmx_segment_cache_clear(to_vmx(vcpu
));
3426 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3427 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3428 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3430 vmcs_write32(GUEST_TR_AR_BYTES
,
3431 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3432 | VMX_AR_TYPE_BUSY_64_TSS
);
3434 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3437 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3439 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3440 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3445 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3447 vpid_sync_context(to_vmx(vcpu
));
3449 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3451 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3455 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3457 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3459 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3460 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3463 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3465 if (enable_ept
&& is_paging(vcpu
))
3466 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3467 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3470 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3472 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3474 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3475 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3478 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3480 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3482 if (!test_bit(VCPU_EXREG_PDPTR
,
3483 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3486 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3487 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3488 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3489 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3490 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3494 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3496 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3498 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3499 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3500 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3501 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3502 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3505 __set_bit(VCPU_EXREG_PDPTR
,
3506 (unsigned long *)&vcpu
->arch
.regs_avail
);
3507 __set_bit(VCPU_EXREG_PDPTR
,
3508 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3511 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3513 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3515 struct kvm_vcpu
*vcpu
)
3517 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3518 vmx_decache_cr3(vcpu
);
3519 if (!(cr0
& X86_CR0_PG
)) {
3520 /* From paging/starting to nonpaging */
3521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3522 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3523 (CPU_BASED_CR3_LOAD_EXITING
|
3524 CPU_BASED_CR3_STORE_EXITING
));
3525 vcpu
->arch
.cr0
= cr0
;
3526 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3527 } else if (!is_paging(vcpu
)) {
3528 /* From nonpaging to paging */
3529 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3530 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3531 ~(CPU_BASED_CR3_LOAD_EXITING
|
3532 CPU_BASED_CR3_STORE_EXITING
));
3533 vcpu
->arch
.cr0
= cr0
;
3534 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3537 if (!(cr0
& X86_CR0_WP
))
3538 *hw_cr0
&= ~X86_CR0_WP
;
3541 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3543 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3544 unsigned long hw_cr0
;
3546 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3547 if (enable_unrestricted_guest
)
3548 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3550 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3552 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3555 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3559 #ifdef CONFIG_X86_64
3560 if (vcpu
->arch
.efer
& EFER_LME
) {
3561 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3563 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3569 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3571 if (!vcpu
->fpu_active
)
3572 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3574 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3575 vmcs_writel(GUEST_CR0
, hw_cr0
);
3576 vcpu
->arch
.cr0
= cr0
;
3578 /* depends on vcpu->arch.cr0 to be set to a new value */
3579 vmx
->emulation_required
= emulation_required(vcpu
);
3582 static u64
construct_eptp(unsigned long root_hpa
)
3586 /* TODO write the value reading from MSR */
3587 eptp
= VMX_EPT_DEFAULT_MT
|
3588 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3589 if (enable_ept_ad_bits
)
3590 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3591 eptp
|= (root_hpa
& PAGE_MASK
);
3596 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3598 unsigned long guest_cr3
;
3603 eptp
= construct_eptp(cr3
);
3604 vmcs_write64(EPT_POINTER
, eptp
);
3605 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3606 guest_cr3
= kvm_read_cr3(vcpu
);
3608 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3609 ept_load_pdptrs(vcpu
);
3612 vmx_flush_tlb(vcpu
);
3613 vmcs_writel(GUEST_CR3
, guest_cr3
);
3616 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3619 * Pass through host's Machine Check Enable value to hw_cr4, which
3620 * is in force while we are in guest mode. Do not let guests control
3621 * this bit, even if host CR4.MCE == 0.
3623 unsigned long hw_cr4
=
3624 (cr4_read_shadow() & X86_CR4_MCE
) |
3625 (cr4
& ~X86_CR4_MCE
) |
3626 (to_vmx(vcpu
)->rmode
.vm86_active
?
3627 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3629 if (cr4
& X86_CR4_VMXE
) {
3631 * To use VMXON (and later other VMX instructions), a guest
3632 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3633 * So basically the check on whether to allow nested VMX
3636 if (!nested_vmx_allowed(vcpu
))
3639 if (to_vmx(vcpu
)->nested
.vmxon
&&
3640 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3643 vcpu
->arch
.cr4
= cr4
;
3645 if (!is_paging(vcpu
)) {
3646 hw_cr4
&= ~X86_CR4_PAE
;
3647 hw_cr4
|= X86_CR4_PSE
;
3649 * SMEP/SMAP is disabled if CPU is in non-paging mode
3650 * in hardware. However KVM always uses paging mode to
3651 * emulate guest non-paging mode with TDP.
3652 * To emulate this behavior, SMEP/SMAP needs to be
3653 * manually disabled when guest switches to non-paging
3656 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3657 } else if (!(cr4
& X86_CR4_PAE
)) {
3658 hw_cr4
&= ~X86_CR4_PAE
;
3662 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3663 vmcs_writel(GUEST_CR4
, hw_cr4
);
3667 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3668 struct kvm_segment
*var
, int seg
)
3670 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3673 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3674 *var
= vmx
->rmode
.segs
[seg
];
3675 if (seg
== VCPU_SREG_TR
3676 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3678 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3679 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3682 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3683 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3684 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3685 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3686 var
->unusable
= (ar
>> 16) & 1;
3687 var
->type
= ar
& 15;
3688 var
->s
= (ar
>> 4) & 1;
3689 var
->dpl
= (ar
>> 5) & 3;
3691 * Some userspaces do not preserve unusable property. Since usable
3692 * segment has to be present according to VMX spec we can use present
3693 * property to amend userspace bug by making unusable segment always
3694 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3695 * segment as unusable.
3697 var
->present
= !var
->unusable
;
3698 var
->avl
= (ar
>> 12) & 1;
3699 var
->l
= (ar
>> 13) & 1;
3700 var
->db
= (ar
>> 14) & 1;
3701 var
->g
= (ar
>> 15) & 1;
3704 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3706 struct kvm_segment s
;
3708 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3709 vmx_get_segment(vcpu
, &s
, seg
);
3712 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3715 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3719 if (unlikely(vmx
->rmode
.vm86_active
))
3722 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3723 return VMX_AR_DPL(ar
);
3727 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3731 if (var
->unusable
|| !var
->present
)
3734 ar
= var
->type
& 15;
3735 ar
|= (var
->s
& 1) << 4;
3736 ar
|= (var
->dpl
& 3) << 5;
3737 ar
|= (var
->present
& 1) << 7;
3738 ar
|= (var
->avl
& 1) << 12;
3739 ar
|= (var
->l
& 1) << 13;
3740 ar
|= (var
->db
& 1) << 14;
3741 ar
|= (var
->g
& 1) << 15;
3747 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3748 struct kvm_segment
*var
, int seg
)
3750 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3751 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3753 vmx_segment_cache_clear(vmx
);
3755 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3756 vmx
->rmode
.segs
[seg
] = *var
;
3757 if (seg
== VCPU_SREG_TR
)
3758 vmcs_write16(sf
->selector
, var
->selector
);
3760 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3764 vmcs_writel(sf
->base
, var
->base
);
3765 vmcs_write32(sf
->limit
, var
->limit
);
3766 vmcs_write16(sf
->selector
, var
->selector
);
3769 * Fix the "Accessed" bit in AR field of segment registers for older
3771 * IA32 arch specifies that at the time of processor reset the
3772 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3773 * is setting it to 0 in the userland code. This causes invalid guest
3774 * state vmexit when "unrestricted guest" mode is turned on.
3775 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3776 * tree. Newer qemu binaries with that qemu fix would not need this
3779 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3780 var
->type
|= 0x1; /* Accessed */
3782 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3785 vmx
->emulation_required
= emulation_required(vcpu
);
3788 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3790 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3792 *db
= (ar
>> 14) & 1;
3793 *l
= (ar
>> 13) & 1;
3796 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3798 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3799 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3802 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3804 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3805 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3808 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3810 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3811 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3814 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3816 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3817 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3820 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3822 struct kvm_segment var
;
3825 vmx_get_segment(vcpu
, &var
, seg
);
3827 if (seg
== VCPU_SREG_CS
)
3829 ar
= vmx_segment_access_rights(&var
);
3831 if (var
.base
!= (var
.selector
<< 4))
3833 if (var
.limit
!= 0xffff)
3841 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3843 struct kvm_segment cs
;
3844 unsigned int cs_rpl
;
3846 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3847 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3851 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3855 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3856 if (cs
.dpl
> cs_rpl
)
3859 if (cs
.dpl
!= cs_rpl
)
3865 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3869 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3871 struct kvm_segment ss
;
3872 unsigned int ss_rpl
;
3874 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3875 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
3879 if (ss
.type
!= 3 && ss
.type
!= 7)
3883 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3891 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3893 struct kvm_segment var
;
3896 vmx_get_segment(vcpu
, &var
, seg
);
3897 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
3905 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
3906 if (var
.dpl
< rpl
) /* DPL < RPL */
3910 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3916 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3918 struct kvm_segment tr
;
3920 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3924 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3926 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3934 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3936 struct kvm_segment ldtr
;
3938 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3942 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3952 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3954 struct kvm_segment cs
, ss
;
3956 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3957 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3959 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
3960 (ss
.selector
& SEGMENT_RPL_MASK
));
3964 * Check if guest state is valid. Returns true if valid, false if
3966 * We assume that registers are always usable
3968 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3970 if (enable_unrestricted_guest
)
3973 /* real mode guest state checks */
3974 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3975 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3977 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3979 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3981 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3983 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3985 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3988 /* protected mode guest state checks */
3989 if (!cs_ss_rpl_check(vcpu
))
3991 if (!code_segment_valid(vcpu
))
3993 if (!stack_segment_valid(vcpu
))
3995 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3997 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3999 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4001 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4003 if (!tr_valid(vcpu
))
4005 if (!ldtr_valid(vcpu
))
4009 * - Add checks on RIP
4010 * - Add checks on RFLAGS
4016 static int init_rmode_tss(struct kvm
*kvm
)
4022 idx
= srcu_read_lock(&kvm
->srcu
);
4023 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4024 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4027 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4028 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4029 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4032 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4035 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4039 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4040 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4043 srcu_read_unlock(&kvm
->srcu
, idx
);
4047 static int init_rmode_identity_map(struct kvm
*kvm
)
4050 pfn_t identity_map_pfn
;
4056 /* Protect kvm->arch.ept_identity_pagetable_done. */
4057 mutex_lock(&kvm
->slots_lock
);
4059 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4062 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4064 r
= alloc_identity_pagetable(kvm
);
4068 idx
= srcu_read_lock(&kvm
->srcu
);
4069 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4072 /* Set up identity-mapping pagetable for EPT in real mode */
4073 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4074 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4075 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4076 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4077 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4081 kvm
->arch
.ept_identity_pagetable_done
= true;
4084 srcu_read_unlock(&kvm
->srcu
, idx
);
4087 mutex_unlock(&kvm
->slots_lock
);
4091 static void seg_setup(int seg
)
4093 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4096 vmcs_write16(sf
->selector
, 0);
4097 vmcs_writel(sf
->base
, 0);
4098 vmcs_write32(sf
->limit
, 0xffff);
4100 if (seg
== VCPU_SREG_CS
)
4101 ar
|= 0x08; /* code segment */
4103 vmcs_write32(sf
->ar_bytes
, ar
);
4106 static int alloc_apic_access_page(struct kvm
*kvm
)
4109 struct kvm_userspace_memory_region kvm_userspace_mem
;
4112 mutex_lock(&kvm
->slots_lock
);
4113 if (kvm
->arch
.apic_access_page_done
)
4115 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4116 kvm_userspace_mem
.flags
= 0;
4117 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
4118 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4119 r
= __x86_set_memory_region(kvm
, &kvm_userspace_mem
);
4123 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4124 if (is_error_page(page
)) {
4130 * Do not pin the page in memory, so that memory hot-unplug
4131 * is able to migrate it.
4134 kvm
->arch
.apic_access_page_done
= true;
4136 mutex_unlock(&kvm
->slots_lock
);
4140 static int alloc_identity_pagetable(struct kvm
*kvm
)
4142 /* Called with kvm->slots_lock held. */
4144 struct kvm_userspace_memory_region kvm_userspace_mem
;
4147 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4149 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4150 kvm_userspace_mem
.flags
= 0;
4151 kvm_userspace_mem
.guest_phys_addr
=
4152 kvm
->arch
.ept_identity_map_addr
;
4153 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4154 r
= __x86_set_memory_region(kvm
, &kvm_userspace_mem
);
4159 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4166 spin_lock(&vmx_vpid_lock
);
4167 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4168 if (vpid
< VMX_NR_VPIDS
) {
4170 __set_bit(vpid
, vmx_vpid_bitmap
);
4172 spin_unlock(&vmx_vpid_lock
);
4175 static void free_vpid(struct vcpu_vmx
*vmx
)
4179 spin_lock(&vmx_vpid_lock
);
4181 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4182 spin_unlock(&vmx_vpid_lock
);
4185 #define MSR_TYPE_R 1
4186 #define MSR_TYPE_W 2
4187 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4190 int f
= sizeof(unsigned long);
4192 if (!cpu_has_vmx_msr_bitmap())
4196 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4197 * have the write-low and read-high bitmap offsets the wrong way round.
4198 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4200 if (msr
<= 0x1fff) {
4201 if (type
& MSR_TYPE_R
)
4203 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4205 if (type
& MSR_TYPE_W
)
4207 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4209 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4211 if (type
& MSR_TYPE_R
)
4213 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4215 if (type
& MSR_TYPE_W
)
4217 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4222 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4225 int f
= sizeof(unsigned long);
4227 if (!cpu_has_vmx_msr_bitmap())
4231 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4232 * have the write-low and read-high bitmap offsets the wrong way round.
4233 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4235 if (msr
<= 0x1fff) {
4236 if (type
& MSR_TYPE_R
)
4238 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4240 if (type
& MSR_TYPE_W
)
4242 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4244 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4246 if (type
& MSR_TYPE_R
)
4248 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4250 if (type
& MSR_TYPE_W
)
4252 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4258 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4259 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4261 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4262 unsigned long *msr_bitmap_nested
,
4265 int f
= sizeof(unsigned long);
4267 if (!cpu_has_vmx_msr_bitmap()) {
4273 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4274 * have the write-low and read-high bitmap offsets the wrong way round.
4275 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4277 if (msr
<= 0x1fff) {
4278 if (type
& MSR_TYPE_R
&&
4279 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4281 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4283 if (type
& MSR_TYPE_W
&&
4284 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4286 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4288 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4290 if (type
& MSR_TYPE_R
&&
4291 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4293 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4295 if (type
& MSR_TYPE_W
&&
4296 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4298 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4303 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4306 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4307 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4308 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4309 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4312 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4314 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4316 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4320 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4328 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4330 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4332 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4336 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4338 return enable_apicv
&& irqchip_in_kernel(kvm
);
4341 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
4343 return vmx_vm_has_apicv(vcpu
->kvm
);
4346 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4348 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4353 if (vmx
->nested
.pi_desc
&&
4354 vmx
->nested
.pi_pending
) {
4355 vmx
->nested
.pi_pending
= false;
4356 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4359 max_irr
= find_last_bit(
4360 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4365 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4370 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4371 kunmap(vmx
->nested
.virtual_apic_page
);
4373 status
= vmcs_read16(GUEST_INTR_STATUS
);
4374 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4376 status
|= (u8
)max_irr
;
4377 vmcs_write16(GUEST_INTR_STATUS
, status
);
4383 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4386 if (vcpu
->mode
== IN_GUEST_MODE
) {
4387 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4388 POSTED_INTR_VECTOR
);
4395 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4400 if (is_guest_mode(vcpu
) &&
4401 vector
== vmx
->nested
.posted_intr_nv
) {
4402 /* the PIR and ON have been set by L1. */
4403 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4405 * If a posted intr is not recognized by hardware,
4406 * we will accomplish it in the next vmentry.
4408 vmx
->nested
.pi_pending
= true;
4409 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4415 * Send interrupt to vcpu via posted interrupt way.
4416 * 1. If target vcpu is running(non-root mode), send posted interrupt
4417 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4418 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4419 * interrupt from PIR in next vmentry.
4421 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4426 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4430 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4433 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4434 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4435 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4436 kvm_vcpu_kick(vcpu
);
4439 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4443 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4446 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4449 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4455 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4456 * will not change in the lifetime of the guest.
4457 * Note that host-state that does change is set elsewhere. E.g., host-state
4458 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4460 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4467 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4468 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4470 /* Save the most likely value for this task's CR4 in the VMCS. */
4471 cr4
= cr4_read_shadow();
4472 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4473 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4475 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4476 #ifdef CONFIG_X86_64
4478 * Load null selectors, so we can avoid reloading them in
4479 * __vmx_load_host_state(), in case userspace uses the null selectors
4480 * too (the expected case).
4482 vmcs_write16(HOST_DS_SELECTOR
, 0);
4483 vmcs_write16(HOST_ES_SELECTOR
, 0);
4485 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4486 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4488 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4489 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4491 native_store_idt(&dt
);
4492 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4493 vmx
->host_idt_base
= dt
.address
;
4495 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4497 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4498 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4499 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4500 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4502 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4503 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4504 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4508 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4510 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4512 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4513 if (is_guest_mode(&vmx
->vcpu
))
4514 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4515 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4516 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4519 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4521 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4523 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4524 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4525 return pin_based_exec_ctrl
;
4528 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4530 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4532 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4533 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4535 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4536 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4537 #ifdef CONFIG_X86_64
4538 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4539 CPU_BASED_CR8_LOAD_EXITING
;
4543 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4544 CPU_BASED_CR3_LOAD_EXITING
|
4545 CPU_BASED_INVLPG_EXITING
;
4546 return exec_control
;
4549 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4551 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4552 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4553 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4555 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4557 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4558 enable_unrestricted_guest
= 0;
4559 /* Enable INVPCID for non-ept guests may cause performance regression. */
4560 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4562 if (!enable_unrestricted_guest
)
4563 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4565 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4566 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4567 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4568 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4569 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4570 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4572 We can NOT enable shadow_vmcs here because we don't have yet
4575 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4576 /* PML is enabled/disabled in creating/destorying vcpu */
4577 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4579 return exec_control
;
4582 static void ept_set_mmio_spte_mask(void)
4585 * EPT Misconfigurations can be generated if the value of bits 2:0
4586 * of an EPT paging-structure entry is 110b (write/execute).
4587 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4590 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4593 #define VMX_XSS_EXIT_BITMAP 0
4595 * Sets up the vmcs for emulated real mode.
4597 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4599 #ifdef CONFIG_X86_64
4605 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4606 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4608 if (enable_shadow_vmcs
) {
4609 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4610 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4612 if (cpu_has_vmx_msr_bitmap())
4613 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4615 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4618 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4620 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4622 if (cpu_has_secondary_exec_ctrls()) {
4623 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4624 vmx_secondary_exec_control(vmx
));
4627 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4628 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4629 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4630 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4631 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4633 vmcs_write16(GUEST_INTR_STATUS
, 0);
4635 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4636 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4640 vmcs_write32(PLE_GAP
, ple_gap
);
4641 vmx
->ple_window
= ple_window
;
4642 vmx
->ple_window_dirty
= true;
4645 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4646 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4647 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4649 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4650 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4651 vmx_set_constant_host_state(vmx
);
4652 #ifdef CONFIG_X86_64
4653 rdmsrl(MSR_FS_BASE
, a
);
4654 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4655 rdmsrl(MSR_GS_BASE
, a
);
4656 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4658 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4659 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4662 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4663 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4664 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4665 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4666 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4668 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4669 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4671 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4672 u32 index
= vmx_msr_index
[i
];
4673 u32 data_low
, data_high
;
4676 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4678 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4680 vmx
->guest_msrs
[j
].index
= i
;
4681 vmx
->guest_msrs
[j
].data
= 0;
4682 vmx
->guest_msrs
[j
].mask
= -1ull;
4687 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4689 /* 22.2.1, 20.8.1 */
4690 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4692 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4693 set_cr4_guest_host_mask(vmx
);
4695 if (vmx_xsaves_supported())
4696 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4701 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4703 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4704 struct msr_data apic_base_msr
;
4707 vmx
->rmode
.vm86_active
= 0;
4709 vmx
->soft_vnmi_blocked
= 0;
4711 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4712 kvm_set_cr8(vcpu
, 0);
4715 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4716 MSR_IA32_APICBASE_ENABLE
;
4717 if (kvm_vcpu_is_reset_bsp(vcpu
))
4718 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4719 apic_base_msr
.host_initiated
= true;
4720 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4723 vmx_segment_cache_clear(vmx
);
4725 seg_setup(VCPU_SREG_CS
);
4726 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4727 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4729 seg_setup(VCPU_SREG_DS
);
4730 seg_setup(VCPU_SREG_ES
);
4731 seg_setup(VCPU_SREG_FS
);
4732 seg_setup(VCPU_SREG_GS
);
4733 seg_setup(VCPU_SREG_SS
);
4735 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4736 vmcs_writel(GUEST_TR_BASE
, 0);
4737 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4738 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4740 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4741 vmcs_writel(GUEST_LDTR_BASE
, 0);
4742 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4743 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4746 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4747 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4748 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4749 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4752 vmcs_writel(GUEST_RFLAGS
, 0x02);
4753 kvm_rip_write(vcpu
, 0xfff0);
4755 vmcs_writel(GUEST_GDTR_BASE
, 0);
4756 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4758 vmcs_writel(GUEST_IDTR_BASE
, 0);
4759 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4761 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4762 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4763 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4767 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4769 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4770 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4771 if (vm_need_tpr_shadow(vcpu
->kvm
))
4772 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4773 __pa(vcpu
->arch
.apic
->regs
));
4774 vmcs_write32(TPR_THRESHOLD
, 0);
4777 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4779 if (vmx_vm_has_apicv(vcpu
->kvm
))
4780 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4783 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4785 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4786 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4787 vmx
->vcpu
.arch
.cr0
= cr0
;
4788 vmx_set_cr4(vcpu
, 0);
4790 vmx_set_efer(vcpu
, 0);
4791 vmx_fpu_activate(vcpu
);
4792 update_exception_bitmap(vcpu
);
4794 vpid_sync_context(vmx
);
4798 * In nested virtualization, check if L1 asked to exit on external interrupts.
4799 * For most existing hypervisors, this will always return true.
4801 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4803 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4804 PIN_BASED_EXT_INTR_MASK
;
4808 * In nested virtualization, check if L1 has set
4809 * VM_EXIT_ACK_INTR_ON_EXIT
4811 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4813 return get_vmcs12(vcpu
)->vm_exit_controls
&
4814 VM_EXIT_ACK_INTR_ON_EXIT
;
4817 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4819 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4820 PIN_BASED_NMI_EXITING
;
4823 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4825 u32 cpu_based_vm_exec_control
;
4827 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4828 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4829 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4832 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4834 u32 cpu_based_vm_exec_control
;
4836 if (!cpu_has_virtual_nmis() ||
4837 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4838 enable_irq_window(vcpu
);
4842 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4843 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4847 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4851 int irq
= vcpu
->arch
.interrupt
.nr
;
4853 trace_kvm_inj_virq(irq
);
4855 ++vcpu
->stat
.irq_injections
;
4856 if (vmx
->rmode
.vm86_active
) {
4858 if (vcpu
->arch
.interrupt
.soft
)
4859 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4860 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4861 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4864 intr
= irq
| INTR_INFO_VALID_MASK
;
4865 if (vcpu
->arch
.interrupt
.soft
) {
4866 intr
|= INTR_TYPE_SOFT_INTR
;
4867 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4868 vmx
->vcpu
.arch
.event_exit_inst_len
);
4870 intr
|= INTR_TYPE_EXT_INTR
;
4871 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4874 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4876 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4878 if (is_guest_mode(vcpu
))
4881 if (!cpu_has_virtual_nmis()) {
4883 * Tracking the NMI-blocked state in software is built upon
4884 * finding the next open IRQ window. This, in turn, depends on
4885 * well-behaving guests: They have to keep IRQs disabled at
4886 * least as long as the NMI handler runs. Otherwise we may
4887 * cause NMI nesting, maybe breaking the guest. But as this is
4888 * highly unlikely, we can live with the residual risk.
4890 vmx
->soft_vnmi_blocked
= 1;
4891 vmx
->vnmi_blocked_time
= 0;
4894 ++vcpu
->stat
.nmi_injections
;
4895 vmx
->nmi_known_unmasked
= false;
4896 if (vmx
->rmode
.vm86_active
) {
4897 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4898 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4901 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4902 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4905 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4907 if (!cpu_has_virtual_nmis())
4908 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4909 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4911 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4914 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4916 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4918 if (!cpu_has_virtual_nmis()) {
4919 if (vmx
->soft_vnmi_blocked
!= masked
) {
4920 vmx
->soft_vnmi_blocked
= masked
;
4921 vmx
->vnmi_blocked_time
= 0;
4924 vmx
->nmi_known_unmasked
= !masked
;
4926 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4927 GUEST_INTR_STATE_NMI
);
4929 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4930 GUEST_INTR_STATE_NMI
);
4934 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4936 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4939 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4942 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4943 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4944 | GUEST_INTR_STATE_NMI
));
4947 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4949 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4950 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4951 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4952 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4955 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4958 struct kvm_userspace_memory_region tss_mem
= {
4959 .slot
= TSS_PRIVATE_MEMSLOT
,
4960 .guest_phys_addr
= addr
,
4961 .memory_size
= PAGE_SIZE
* 3,
4965 ret
= x86_set_memory_region(kvm
, &tss_mem
);
4968 kvm
->arch
.tss_addr
= addr
;
4969 return init_rmode_tss(kvm
);
4972 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4977 * Update instruction length as we may reinject the exception
4978 * from user space while in guest debugging mode.
4980 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4981 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4982 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4986 if (vcpu
->guest_debug
&
4987 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5004 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5005 int vec
, u32 err_code
)
5008 * Instruction with address size override prefix opcode 0x67
5009 * Cause the #SS fault with 0 error code in VM86 mode.
5011 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5012 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5013 if (vcpu
->arch
.halt_request
) {
5014 vcpu
->arch
.halt_request
= 0;
5015 return kvm_vcpu_halt(vcpu
);
5023 * Forward all other exceptions that are valid in real mode.
5024 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5025 * the required debugging infrastructure rework.
5027 kvm_queue_exception(vcpu
, vec
);
5032 * Trigger machine check on the host. We assume all the MSRs are already set up
5033 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5034 * We pass a fake environment to the machine check handler because we want
5035 * the guest to be always treated like user space, no matter what context
5036 * it used internally.
5038 static void kvm_machine_check(void)
5040 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5041 struct pt_regs regs
= {
5042 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5043 .flags
= X86_EFLAGS_IF
,
5046 do_machine_check(®s
, 0);
5050 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5052 /* already handled by vcpu_run */
5056 static int handle_exception(struct kvm_vcpu
*vcpu
)
5058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5059 struct kvm_run
*kvm_run
= vcpu
->run
;
5060 u32 intr_info
, ex_no
, error_code
;
5061 unsigned long cr2
, rip
, dr6
;
5063 enum emulation_result er
;
5065 vect_info
= vmx
->idt_vectoring_info
;
5066 intr_info
= vmx
->exit_intr_info
;
5068 if (is_machine_check(intr_info
))
5069 return handle_machine_check(vcpu
);
5071 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5072 return 1; /* already handled by vmx_vcpu_run() */
5074 if (is_no_device(intr_info
)) {
5075 vmx_fpu_activate(vcpu
);
5079 if (is_invalid_opcode(intr_info
)) {
5080 if (is_guest_mode(vcpu
)) {
5081 kvm_queue_exception(vcpu
, UD_VECTOR
);
5084 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5085 if (er
!= EMULATE_DONE
)
5086 kvm_queue_exception(vcpu
, UD_VECTOR
);
5091 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5092 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5095 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5096 * MMIO, it is better to report an internal error.
5097 * See the comments in vmx_handle_exit.
5099 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5100 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5101 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5102 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5103 vcpu
->run
->internal
.ndata
= 3;
5104 vcpu
->run
->internal
.data
[0] = vect_info
;
5105 vcpu
->run
->internal
.data
[1] = intr_info
;
5106 vcpu
->run
->internal
.data
[2] = error_code
;
5110 if (is_page_fault(intr_info
)) {
5111 /* EPT won't cause page fault directly */
5113 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5114 trace_kvm_page_fault(cr2
, error_code
);
5116 if (kvm_event_needs_reinjection(vcpu
))
5117 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5118 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5121 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5123 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5124 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5128 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5129 if (!(vcpu
->guest_debug
&
5130 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5131 vcpu
->arch
.dr6
&= ~15;
5132 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5133 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5134 skip_emulated_instruction(vcpu
);
5136 kvm_queue_exception(vcpu
, DB_VECTOR
);
5139 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5140 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5144 * Update instruction length as we may reinject #BP from
5145 * user space while in guest debugging mode. Reading it for
5146 * #DB as well causes no harm, it is not used in that case.
5148 vmx
->vcpu
.arch
.event_exit_inst_len
=
5149 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5150 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5151 rip
= kvm_rip_read(vcpu
);
5152 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5153 kvm_run
->debug
.arch
.exception
= ex_no
;
5156 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5157 kvm_run
->ex
.exception
= ex_no
;
5158 kvm_run
->ex
.error_code
= error_code
;
5164 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5166 ++vcpu
->stat
.irq_exits
;
5170 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5172 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5176 static int handle_io(struct kvm_vcpu
*vcpu
)
5178 unsigned long exit_qualification
;
5179 int size
, in
, string
;
5182 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5183 string
= (exit_qualification
& 16) != 0;
5184 in
= (exit_qualification
& 8) != 0;
5186 ++vcpu
->stat
.io_exits
;
5189 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5191 port
= exit_qualification
>> 16;
5192 size
= (exit_qualification
& 7) + 1;
5193 skip_emulated_instruction(vcpu
);
5195 return kvm_fast_pio_out(vcpu
, size
, port
);
5199 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5202 * Patch in the VMCALL instruction:
5204 hypercall
[0] = 0x0f;
5205 hypercall
[1] = 0x01;
5206 hypercall
[2] = 0xc1;
5209 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5211 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5212 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5214 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5215 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5216 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5217 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5218 return (val
& always_on
) == always_on
;
5221 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5222 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5224 if (is_guest_mode(vcpu
)) {
5225 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5226 unsigned long orig_val
= val
;
5229 * We get here when L2 changed cr0 in a way that did not change
5230 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5231 * but did change L0 shadowed bits. So we first calculate the
5232 * effective cr0 value that L1 would like to write into the
5233 * hardware. It consists of the L2-owned bits from the new
5234 * value combined with the L1-owned bits from L1's guest_cr0.
5236 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5237 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5239 if (!nested_cr0_valid(vcpu
, val
))
5242 if (kvm_set_cr0(vcpu
, val
))
5244 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5247 if (to_vmx(vcpu
)->nested
.vmxon
&&
5248 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5250 return kvm_set_cr0(vcpu
, val
);
5254 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5256 if (is_guest_mode(vcpu
)) {
5257 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5258 unsigned long orig_val
= val
;
5260 /* analogously to handle_set_cr0 */
5261 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5262 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5263 if (kvm_set_cr4(vcpu
, val
))
5265 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5268 return kvm_set_cr4(vcpu
, val
);
5271 /* called to set cr0 as approriate for clts instruction exit. */
5272 static void handle_clts(struct kvm_vcpu
*vcpu
)
5274 if (is_guest_mode(vcpu
)) {
5276 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5277 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5278 * just pretend it's off (also in arch.cr0 for fpu_activate).
5280 vmcs_writel(CR0_READ_SHADOW
,
5281 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5282 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5284 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5287 static int handle_cr(struct kvm_vcpu
*vcpu
)
5289 unsigned long exit_qualification
, val
;
5294 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5295 cr
= exit_qualification
& 15;
5296 reg
= (exit_qualification
>> 8) & 15;
5297 switch ((exit_qualification
>> 4) & 3) {
5298 case 0: /* mov to cr */
5299 val
= kvm_register_readl(vcpu
, reg
);
5300 trace_kvm_cr_write(cr
, val
);
5303 err
= handle_set_cr0(vcpu
, val
);
5304 kvm_complete_insn_gp(vcpu
, err
);
5307 err
= kvm_set_cr3(vcpu
, val
);
5308 kvm_complete_insn_gp(vcpu
, err
);
5311 err
= handle_set_cr4(vcpu
, val
);
5312 kvm_complete_insn_gp(vcpu
, err
);
5315 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5317 err
= kvm_set_cr8(vcpu
, cr8
);
5318 kvm_complete_insn_gp(vcpu
, err
);
5319 if (irqchip_in_kernel(vcpu
->kvm
))
5321 if (cr8_prev
<= cr8
)
5323 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5330 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5331 skip_emulated_instruction(vcpu
);
5332 vmx_fpu_activate(vcpu
);
5334 case 1: /*mov from cr*/
5337 val
= kvm_read_cr3(vcpu
);
5338 kvm_register_write(vcpu
, reg
, val
);
5339 trace_kvm_cr_read(cr
, val
);
5340 skip_emulated_instruction(vcpu
);
5343 val
= kvm_get_cr8(vcpu
);
5344 kvm_register_write(vcpu
, reg
, val
);
5345 trace_kvm_cr_read(cr
, val
);
5346 skip_emulated_instruction(vcpu
);
5351 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5352 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5353 kvm_lmsw(vcpu
, val
);
5355 skip_emulated_instruction(vcpu
);
5360 vcpu
->run
->exit_reason
= 0;
5361 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5362 (int)(exit_qualification
>> 4) & 3, cr
);
5366 static int handle_dr(struct kvm_vcpu
*vcpu
)
5368 unsigned long exit_qualification
;
5371 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5372 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5374 /* First, if DR does not exist, trigger UD */
5375 if (!kvm_require_dr(vcpu
, dr
))
5378 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5379 if (!kvm_require_cpl(vcpu
, 0))
5381 dr7
= vmcs_readl(GUEST_DR7
);
5384 * As the vm-exit takes precedence over the debug trap, we
5385 * need to emulate the latter, either for the host or the
5386 * guest debugging itself.
5388 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5389 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5390 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5391 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5392 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5393 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5396 vcpu
->arch
.dr6
&= ~15;
5397 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5398 kvm_queue_exception(vcpu
, DB_VECTOR
);
5403 if (vcpu
->guest_debug
== 0) {
5404 u32 cpu_based_vm_exec_control
;
5406 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5407 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5411 * No more DR vmexits; force a reload of the debug registers
5412 * and reenter on this instruction. The next vmexit will
5413 * retrieve the full state of the debug registers.
5415 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5419 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5420 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5423 if (kvm_get_dr(vcpu
, dr
, &val
))
5425 kvm_register_write(vcpu
, reg
, val
);
5427 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5430 skip_emulated_instruction(vcpu
);
5434 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5436 return vcpu
->arch
.dr6
;
5439 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5443 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5445 u32 cpu_based_vm_exec_control
;
5447 get_debugreg(vcpu
->arch
.db
[0], 0);
5448 get_debugreg(vcpu
->arch
.db
[1], 1);
5449 get_debugreg(vcpu
->arch
.db
[2], 2);
5450 get_debugreg(vcpu
->arch
.db
[3], 3);
5451 get_debugreg(vcpu
->arch
.dr6
, 6);
5452 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5454 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5456 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5457 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5458 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5461 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5463 vmcs_writel(GUEST_DR7
, val
);
5466 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5468 kvm_emulate_cpuid(vcpu
);
5472 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5474 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5475 struct msr_data msr_info
;
5477 msr_info
.index
= ecx
;
5478 msr_info
.host_initiated
= false;
5479 if (vmx_get_msr(vcpu
, &msr_info
)) {
5480 trace_kvm_msr_read_ex(ecx
);
5481 kvm_inject_gp(vcpu
, 0);
5485 trace_kvm_msr_read(ecx
, msr_info
.data
);
5487 /* FIXME: handling of bits 32:63 of rax, rdx */
5488 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5489 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5490 skip_emulated_instruction(vcpu
);
5494 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5496 struct msr_data msr
;
5497 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5498 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5499 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5503 msr
.host_initiated
= false;
5504 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5505 trace_kvm_msr_write_ex(ecx
, data
);
5506 kvm_inject_gp(vcpu
, 0);
5510 trace_kvm_msr_write(ecx
, data
);
5511 skip_emulated_instruction(vcpu
);
5515 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5517 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5521 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5523 u32 cpu_based_vm_exec_control
;
5525 /* clear pending irq */
5526 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5527 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5530 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5532 ++vcpu
->stat
.irq_window_exits
;
5535 * If the user space waits to inject interrupts, exit as soon as
5538 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5539 vcpu
->run
->request_interrupt_window
&&
5540 !kvm_cpu_has_interrupt(vcpu
)) {
5541 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5547 static int handle_halt(struct kvm_vcpu
*vcpu
)
5549 return kvm_emulate_halt(vcpu
);
5552 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5554 kvm_emulate_hypercall(vcpu
);
5558 static int handle_invd(struct kvm_vcpu
*vcpu
)
5560 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5563 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5565 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5567 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5568 skip_emulated_instruction(vcpu
);
5572 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5576 err
= kvm_rdpmc(vcpu
);
5577 kvm_complete_insn_gp(vcpu
, err
);
5582 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5584 kvm_emulate_wbinvd(vcpu
);
5588 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5590 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5591 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5593 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5594 skip_emulated_instruction(vcpu
);
5598 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5600 skip_emulated_instruction(vcpu
);
5601 WARN(1, "this should never happen\n");
5605 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5607 skip_emulated_instruction(vcpu
);
5608 WARN(1, "this should never happen\n");
5612 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5614 if (likely(fasteoi
)) {
5615 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5616 int access_type
, offset
;
5618 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5619 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5621 * Sane guest uses MOV to write EOI, with written value
5622 * not cared. So make a short-circuit here by avoiding
5623 * heavy instruction emulation.
5625 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5626 (offset
== APIC_EOI
)) {
5627 kvm_lapic_set_eoi(vcpu
);
5628 skip_emulated_instruction(vcpu
);
5632 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5635 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5637 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5638 int vector
= exit_qualification
& 0xff;
5640 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5641 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5645 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5647 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5648 u32 offset
= exit_qualification
& 0xfff;
5650 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5651 kvm_apic_write_nodecode(vcpu
, offset
);
5655 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5657 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5658 unsigned long exit_qualification
;
5659 bool has_error_code
= false;
5662 int reason
, type
, idt_v
, idt_index
;
5664 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5665 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5666 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5668 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5670 reason
= (u32
)exit_qualification
>> 30;
5671 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5673 case INTR_TYPE_NMI_INTR
:
5674 vcpu
->arch
.nmi_injected
= false;
5675 vmx_set_nmi_mask(vcpu
, true);
5677 case INTR_TYPE_EXT_INTR
:
5678 case INTR_TYPE_SOFT_INTR
:
5679 kvm_clear_interrupt_queue(vcpu
);
5681 case INTR_TYPE_HARD_EXCEPTION
:
5682 if (vmx
->idt_vectoring_info
&
5683 VECTORING_INFO_DELIVER_CODE_MASK
) {
5684 has_error_code
= true;
5686 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5689 case INTR_TYPE_SOFT_EXCEPTION
:
5690 kvm_clear_exception_queue(vcpu
);
5696 tss_selector
= exit_qualification
;
5698 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5699 type
!= INTR_TYPE_EXT_INTR
&&
5700 type
!= INTR_TYPE_NMI_INTR
))
5701 skip_emulated_instruction(vcpu
);
5703 if (kvm_task_switch(vcpu
, tss_selector
,
5704 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5705 has_error_code
, error_code
) == EMULATE_FAIL
) {
5706 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5707 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5708 vcpu
->run
->internal
.ndata
= 0;
5713 * TODO: What about debug traps on tss switch?
5714 * Are we supposed to inject them and update dr6?
5720 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5722 unsigned long exit_qualification
;
5727 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5729 gla_validity
= (exit_qualification
>> 7) & 0x3;
5730 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5731 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5732 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5733 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5734 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5735 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5736 (long unsigned int)exit_qualification
);
5737 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5738 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5743 * EPT violation happened while executing iret from NMI,
5744 * "blocked by NMI" bit has to be set before next VM entry.
5745 * There are errata that may cause this bit to not be set:
5748 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5749 cpu_has_virtual_nmis() &&
5750 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5751 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5753 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5754 trace_kvm_page_fault(gpa
, exit_qualification
);
5756 /* It is a write fault? */
5757 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5758 /* It is a fetch fault? */
5759 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5760 /* ept page table is present? */
5761 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5763 vcpu
->arch
.exit_qualification
= exit_qualification
;
5765 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5768 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5773 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5774 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5775 skip_emulated_instruction(vcpu
);
5779 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5780 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5781 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5784 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5785 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5787 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5790 /* It is the real ept misconfig */
5793 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5794 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5799 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5801 u32 cpu_based_vm_exec_control
;
5803 /* clear pending NMI */
5804 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5805 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5806 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5807 ++vcpu
->stat
.nmi_window_exits
;
5808 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5813 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5815 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5816 enum emulation_result err
= EMULATE_DONE
;
5819 bool intr_window_requested
;
5820 unsigned count
= 130;
5822 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5823 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5825 while (vmx
->emulation_required
&& count
-- != 0) {
5826 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5827 return handle_interrupt_window(&vmx
->vcpu
);
5829 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5832 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5834 if (err
== EMULATE_USER_EXIT
) {
5835 ++vcpu
->stat
.mmio_exits
;
5840 if (err
!= EMULATE_DONE
) {
5841 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5842 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5843 vcpu
->run
->internal
.ndata
= 0;
5847 if (vcpu
->arch
.halt_request
) {
5848 vcpu
->arch
.halt_request
= 0;
5849 ret
= kvm_vcpu_halt(vcpu
);
5853 if (signal_pending(current
))
5863 static int __grow_ple_window(int val
)
5865 if (ple_window_grow
< 1)
5868 val
= min(val
, ple_window_actual_max
);
5870 if (ple_window_grow
< ple_window
)
5871 val
*= ple_window_grow
;
5873 val
+= ple_window_grow
;
5878 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5883 if (modifier
< ple_window
)
5888 return max(val
, minimum
);
5891 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5894 int old
= vmx
->ple_window
;
5896 vmx
->ple_window
= __grow_ple_window(old
);
5898 if (vmx
->ple_window
!= old
)
5899 vmx
->ple_window_dirty
= true;
5901 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5904 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5907 int old
= vmx
->ple_window
;
5909 vmx
->ple_window
= __shrink_ple_window(old
,
5910 ple_window_shrink
, ple_window
);
5912 if (vmx
->ple_window
!= old
)
5913 vmx
->ple_window_dirty
= true;
5915 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5919 * ple_window_actual_max is computed to be one grow_ple_window() below
5920 * ple_window_max. (See __grow_ple_window for the reason.)
5921 * This prevents overflows, because ple_window_max is int.
5922 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5924 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5926 static void update_ple_window_actual_max(void)
5928 ple_window_actual_max
=
5929 __shrink_ple_window(max(ple_window_max
, ple_window
),
5930 ple_window_grow
, INT_MIN
);
5933 static __init
int hardware_setup(void)
5935 int r
= -ENOMEM
, i
, msr
;
5937 rdmsrl_safe(MSR_EFER
, &host_efer
);
5939 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
5940 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5942 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5943 if (!vmx_io_bitmap_a
)
5946 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5947 if (!vmx_io_bitmap_b
)
5950 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5951 if (!vmx_msr_bitmap_legacy
)
5954 vmx_msr_bitmap_legacy_x2apic
=
5955 (unsigned long *)__get_free_page(GFP_KERNEL
);
5956 if (!vmx_msr_bitmap_legacy_x2apic
)
5959 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5960 if (!vmx_msr_bitmap_longmode
)
5963 vmx_msr_bitmap_longmode_x2apic
=
5964 (unsigned long *)__get_free_page(GFP_KERNEL
);
5965 if (!vmx_msr_bitmap_longmode_x2apic
)
5969 vmx_msr_bitmap_nested
=
5970 (unsigned long *)__get_free_page(GFP_KERNEL
);
5971 if (!vmx_msr_bitmap_nested
)
5975 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5976 if (!vmx_vmread_bitmap
)
5979 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5980 if (!vmx_vmwrite_bitmap
)
5983 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
5984 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
5987 * Allow direct access to the PC debug port (it is often used for I/O
5988 * delays, but the vmexits simply slow things down).
5990 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
5991 clear_bit(0x80, vmx_io_bitmap_a
);
5993 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
5995 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
5996 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
5998 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6000 if (setup_vmcs_config(&vmcs_config
) < 0) {
6005 if (boot_cpu_has(X86_FEATURE_NX
))
6006 kvm_enable_efer_bits(EFER_NX
);
6008 if (!cpu_has_vmx_vpid())
6010 if (!cpu_has_vmx_shadow_vmcs())
6011 enable_shadow_vmcs
= 0;
6012 if (enable_shadow_vmcs
)
6013 init_vmcs_shadow_fields();
6015 if (!cpu_has_vmx_ept() ||
6016 !cpu_has_vmx_ept_4levels()) {
6018 enable_unrestricted_guest
= 0;
6019 enable_ept_ad_bits
= 0;
6022 if (!cpu_has_vmx_ept_ad_bits())
6023 enable_ept_ad_bits
= 0;
6025 if (!cpu_has_vmx_unrestricted_guest())
6026 enable_unrestricted_guest
= 0;
6028 if (!cpu_has_vmx_flexpriority())
6029 flexpriority_enabled
= 0;
6032 * set_apic_access_page_addr() is used to reload apic access
6033 * page upon invalidation. No need to do anything if not
6034 * using the APIC_ACCESS_ADDR VMCS field.
6036 if (!flexpriority_enabled
)
6037 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6039 if (!cpu_has_vmx_tpr_shadow())
6040 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6042 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6043 kvm_disable_largepages();
6045 if (!cpu_has_vmx_ple())
6048 if (!cpu_has_vmx_apicv())
6052 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6054 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6055 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6056 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6057 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6060 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6061 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6062 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6063 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6064 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6065 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6066 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6068 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6069 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6070 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6071 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6073 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6076 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6077 vmx_disable_intercept_msr_read_x2apic(msr
);
6079 /* According SDM, in x2apic mode, the whole id reg is used.
6080 * But in KVM, it only use the highest eight bits. Need to
6082 vmx_enable_intercept_msr_read_x2apic(0x802);
6084 vmx_enable_intercept_msr_read_x2apic(0x839);
6086 vmx_disable_intercept_msr_write_x2apic(0x808);
6088 vmx_disable_intercept_msr_write_x2apic(0x80b);
6090 vmx_disable_intercept_msr_write_x2apic(0x83f);
6094 kvm_mmu_set_mask_ptes(0ull,
6095 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6096 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6097 0ull, VMX_EPT_EXECUTABLE_MASK
);
6098 ept_set_mmio_spte_mask();
6103 update_ple_window_actual_max();
6106 * Only enable PML when hardware supports PML feature, and both EPT
6107 * and EPT A/D bit features are enabled -- PML depends on them to work.
6109 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6113 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6114 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6115 kvm_x86_ops
->flush_log_dirty
= NULL
;
6116 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6119 return alloc_kvm_area();
6122 free_page((unsigned long)vmx_vmwrite_bitmap
);
6124 free_page((unsigned long)vmx_vmread_bitmap
);
6127 free_page((unsigned long)vmx_msr_bitmap_nested
);
6129 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6131 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6133 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6135 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6137 free_page((unsigned long)vmx_io_bitmap_b
);
6139 free_page((unsigned long)vmx_io_bitmap_a
);
6144 static __exit
void hardware_unsetup(void)
6146 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6147 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6148 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6149 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6150 free_page((unsigned long)vmx_io_bitmap_b
);
6151 free_page((unsigned long)vmx_io_bitmap_a
);
6152 free_page((unsigned long)vmx_vmwrite_bitmap
);
6153 free_page((unsigned long)vmx_vmread_bitmap
);
6155 free_page((unsigned long)vmx_msr_bitmap_nested
);
6161 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6162 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6164 static int handle_pause(struct kvm_vcpu
*vcpu
)
6167 grow_ple_window(vcpu
);
6169 skip_emulated_instruction(vcpu
);
6170 kvm_vcpu_on_spin(vcpu
);
6175 static int handle_nop(struct kvm_vcpu
*vcpu
)
6177 skip_emulated_instruction(vcpu
);
6181 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6183 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6184 return handle_nop(vcpu
);
6187 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6192 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6194 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6195 return handle_nop(vcpu
);
6199 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6200 * We could reuse a single VMCS for all the L2 guests, but we also want the
6201 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6202 * allows keeping them loaded on the processor, and in the future will allow
6203 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6204 * every entry if they never change.
6205 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6206 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6208 * The following functions allocate and free a vmcs02 in this pool.
6211 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6212 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6214 struct vmcs02_list
*item
;
6215 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6216 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6217 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6218 return &item
->vmcs02
;
6221 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6222 /* Recycle the least recently used VMCS. */
6223 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6224 struct vmcs02_list
, list
);
6225 item
->vmptr
= vmx
->nested
.current_vmptr
;
6226 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6227 return &item
->vmcs02
;
6230 /* Create a new VMCS */
6231 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6234 item
->vmcs02
.vmcs
= alloc_vmcs();
6235 if (!item
->vmcs02
.vmcs
) {
6239 loaded_vmcs_init(&item
->vmcs02
);
6240 item
->vmptr
= vmx
->nested
.current_vmptr
;
6241 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6242 vmx
->nested
.vmcs02_num
++;
6243 return &item
->vmcs02
;
6246 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6247 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6249 struct vmcs02_list
*item
;
6250 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6251 if (item
->vmptr
== vmptr
) {
6252 free_loaded_vmcs(&item
->vmcs02
);
6253 list_del(&item
->list
);
6255 vmx
->nested
.vmcs02_num
--;
6261 * Free all VMCSs saved for this vcpu, except the one pointed by
6262 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6263 * must be &vmx->vmcs01.
6265 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6267 struct vmcs02_list
*item
, *n
;
6269 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6270 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6272 * Something will leak if the above WARN triggers. Better than
6275 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6278 free_loaded_vmcs(&item
->vmcs02
);
6279 list_del(&item
->list
);
6281 vmx
->nested
.vmcs02_num
--;
6286 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6287 * set the success or error code of an emulated VMX instruction, as specified
6288 * by Vol 2B, VMX Instruction Reference, "Conventions".
6290 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6292 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6293 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6294 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6297 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6299 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6300 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6301 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6305 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6306 u32 vm_instruction_error
)
6308 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6310 * failValid writes the error number to the current VMCS, which
6311 * can't be done there isn't a current VMCS.
6313 nested_vmx_failInvalid(vcpu
);
6316 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6317 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6318 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6320 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6322 * We don't need to force a shadow sync because
6323 * VM_INSTRUCTION_ERROR is not shadowed
6327 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6329 /* TODO: not to reset guest simply here. */
6330 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6331 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6334 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6336 struct vcpu_vmx
*vmx
=
6337 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6339 vmx
->nested
.preemption_timer_expired
= true;
6340 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6341 kvm_vcpu_kick(&vmx
->vcpu
);
6343 return HRTIMER_NORESTART
;
6347 * Decode the memory-address operand of a vmx instruction, as recorded on an
6348 * exit caused by such an instruction (run by a guest hypervisor).
6349 * On success, returns 0. When the operand is invalid, returns 1 and throws
6352 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6353 unsigned long exit_qualification
,
6354 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6358 struct kvm_segment s
;
6361 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6362 * Execution", on an exit, vmx_instruction_info holds most of the
6363 * addressing components of the operand. Only the displacement part
6364 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6365 * For how an actual address is calculated from all these components,
6366 * refer to Vol. 1, "Operand Addressing".
6368 int scaling
= vmx_instruction_info
& 3;
6369 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6370 bool is_reg
= vmx_instruction_info
& (1u << 10);
6371 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6372 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6373 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6374 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6375 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6378 kvm_queue_exception(vcpu
, UD_VECTOR
);
6382 /* Addr = segment_base + offset */
6383 /* offset = base + [index * scale] + displacement */
6384 off
= exit_qualification
; /* holds the displacement */
6386 off
+= kvm_register_read(vcpu
, base_reg
);
6388 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6389 vmx_get_segment(vcpu
, &s
, seg_reg
);
6390 *ret
= s
.base
+ off
;
6392 if (addr_size
== 1) /* 32 bit */
6395 /* Checks for #GP/#SS exceptions. */
6397 if (is_protmode(vcpu
)) {
6398 /* Protected mode: apply checks for segment validity in the
6400 * - segment type check (#GP(0) may be thrown)
6401 * - usability check (#GP(0)/#SS(0))
6402 * - limit check (#GP(0)/#SS(0))
6405 /* #GP(0) if the destination operand is located in a
6406 * read-only data segment or any code segment.
6408 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6410 /* #GP(0) if the source operand is located in an
6411 * execute-only code segment
6413 exn
= ((s
.type
& 0xa) == 8);
6416 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6419 if (is_long_mode(vcpu
)) {
6420 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6421 * non-canonical form. This is an only check for long mode.
6423 exn
= is_noncanonical_address(*ret
);
6424 } else if (is_protmode(vcpu
)) {
6425 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6427 exn
= (s
.unusable
!= 0);
6428 /* Protected mode: #GP(0)/#SS(0) if the memory
6429 * operand is outside the segment limit.
6431 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6434 kvm_queue_exception_e(vcpu
,
6435 seg_reg
== VCPU_SREG_SS
?
6436 SS_VECTOR
: GP_VECTOR
,
6445 * This function performs the various checks including
6446 * - if it's 4KB aligned
6447 * - No bits beyond the physical address width are set
6448 * - Returns 0 on success or else 1
6449 * (Intel SDM Section 30.3)
6451 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6456 struct x86_exception e
;
6458 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6459 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6461 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6462 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6465 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6466 sizeof(vmptr
), &e
)) {
6467 kvm_inject_page_fault(vcpu
, &e
);
6471 switch (exit_reason
) {
6472 case EXIT_REASON_VMON
:
6475 * The first 4 bytes of VMXON region contain the supported
6476 * VMCS revision identifier
6478 * Note - IA32_VMX_BASIC[48] will never be 1
6479 * for the nested case;
6480 * which replaces physical address width with 32
6483 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6484 nested_vmx_failInvalid(vcpu
);
6485 skip_emulated_instruction(vcpu
);
6489 page
= nested_get_page(vcpu
, vmptr
);
6491 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6492 nested_vmx_failInvalid(vcpu
);
6494 skip_emulated_instruction(vcpu
);
6498 vmx
->nested
.vmxon_ptr
= vmptr
;
6500 case EXIT_REASON_VMCLEAR
:
6501 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6502 nested_vmx_failValid(vcpu
,
6503 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6504 skip_emulated_instruction(vcpu
);
6508 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6509 nested_vmx_failValid(vcpu
,
6510 VMXERR_VMCLEAR_VMXON_POINTER
);
6511 skip_emulated_instruction(vcpu
);
6515 case EXIT_REASON_VMPTRLD
:
6516 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6517 nested_vmx_failValid(vcpu
,
6518 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6519 skip_emulated_instruction(vcpu
);
6523 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6524 nested_vmx_failValid(vcpu
,
6525 VMXERR_VMCLEAR_VMXON_POINTER
);
6526 skip_emulated_instruction(vcpu
);
6531 return 1; /* shouldn't happen */
6540 * Emulate the VMXON instruction.
6541 * Currently, we just remember that VMX is active, and do not save or even
6542 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6543 * do not currently need to store anything in that guest-allocated memory
6544 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6545 * argument is different from the VMXON pointer (which the spec says they do).
6547 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6549 struct kvm_segment cs
;
6550 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6551 struct vmcs
*shadow_vmcs
;
6552 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6553 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6555 /* The Intel VMX Instruction Reference lists a bunch of bits that
6556 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6557 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6558 * Otherwise, we should fail with #UD. We test these now:
6560 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6561 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6562 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6563 kvm_queue_exception(vcpu
, UD_VECTOR
);
6567 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6568 if (is_long_mode(vcpu
) && !cs
.l
) {
6569 kvm_queue_exception(vcpu
, UD_VECTOR
);
6573 if (vmx_get_cpl(vcpu
)) {
6574 kvm_inject_gp(vcpu
, 0);
6578 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6581 if (vmx
->nested
.vmxon
) {
6582 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6583 skip_emulated_instruction(vcpu
);
6587 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6588 != VMXON_NEEDED_FEATURES
) {
6589 kvm_inject_gp(vcpu
, 0);
6593 if (enable_shadow_vmcs
) {
6594 shadow_vmcs
= alloc_vmcs();
6597 /* mark vmcs as shadow */
6598 shadow_vmcs
->revision_id
|= (1u << 31);
6599 /* init shadow vmcs */
6600 vmcs_clear(shadow_vmcs
);
6601 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6604 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6605 vmx
->nested
.vmcs02_num
= 0;
6607 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6609 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6611 vmx
->nested
.vmxon
= true;
6613 skip_emulated_instruction(vcpu
);
6614 nested_vmx_succeed(vcpu
);
6619 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6620 * for running VMX instructions (except VMXON, whose prerequisites are
6621 * slightly different). It also specifies what exception to inject otherwise.
6623 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6625 struct kvm_segment cs
;
6626 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6628 if (!vmx
->nested
.vmxon
) {
6629 kvm_queue_exception(vcpu
, UD_VECTOR
);
6633 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6634 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6635 (is_long_mode(vcpu
) && !cs
.l
)) {
6636 kvm_queue_exception(vcpu
, UD_VECTOR
);
6640 if (vmx_get_cpl(vcpu
)) {
6641 kvm_inject_gp(vcpu
, 0);
6648 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6651 if (vmx
->nested
.current_vmptr
== -1ull)
6654 /* current_vmptr and current_vmcs12 are always set/reset together */
6655 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6658 if (enable_shadow_vmcs
) {
6659 /* copy to memory all shadowed fields in case
6660 they were modified */
6661 copy_shadow_to_vmcs12(vmx
);
6662 vmx
->nested
.sync_shadow_vmcs
= false;
6663 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6664 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6665 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6666 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6668 vmx
->nested
.posted_intr_nv
= -1;
6669 kunmap(vmx
->nested
.current_vmcs12_page
);
6670 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6671 vmx
->nested
.current_vmptr
= -1ull;
6672 vmx
->nested
.current_vmcs12
= NULL
;
6676 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6677 * just stops using VMX.
6679 static void free_nested(struct vcpu_vmx
*vmx
)
6681 if (!vmx
->nested
.vmxon
)
6684 vmx
->nested
.vmxon
= false;
6685 nested_release_vmcs12(vmx
);
6686 if (enable_shadow_vmcs
)
6687 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6688 /* Unpin physical memory we referred to in current vmcs02 */
6689 if (vmx
->nested
.apic_access_page
) {
6690 nested_release_page(vmx
->nested
.apic_access_page
);
6691 vmx
->nested
.apic_access_page
= NULL
;
6693 if (vmx
->nested
.virtual_apic_page
) {
6694 nested_release_page(vmx
->nested
.virtual_apic_page
);
6695 vmx
->nested
.virtual_apic_page
= NULL
;
6697 if (vmx
->nested
.pi_desc_page
) {
6698 kunmap(vmx
->nested
.pi_desc_page
);
6699 nested_release_page(vmx
->nested
.pi_desc_page
);
6700 vmx
->nested
.pi_desc_page
= NULL
;
6701 vmx
->nested
.pi_desc
= NULL
;
6704 nested_free_all_saved_vmcss(vmx
);
6707 /* Emulate the VMXOFF instruction */
6708 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6710 if (!nested_vmx_check_permission(vcpu
))
6712 free_nested(to_vmx(vcpu
));
6713 skip_emulated_instruction(vcpu
);
6714 nested_vmx_succeed(vcpu
);
6718 /* Emulate the VMCLEAR instruction */
6719 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6721 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6723 struct vmcs12
*vmcs12
;
6726 if (!nested_vmx_check_permission(vcpu
))
6729 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6732 if (vmptr
== vmx
->nested
.current_vmptr
)
6733 nested_release_vmcs12(vmx
);
6735 page
= nested_get_page(vcpu
, vmptr
);
6738 * For accurate processor emulation, VMCLEAR beyond available
6739 * physical memory should do nothing at all. However, it is
6740 * possible that a nested vmx bug, not a guest hypervisor bug,
6741 * resulted in this case, so let's shut down before doing any
6744 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6747 vmcs12
= kmap(page
);
6748 vmcs12
->launch_state
= 0;
6750 nested_release_page(page
);
6752 nested_free_vmcs02(vmx
, vmptr
);
6754 skip_emulated_instruction(vcpu
);
6755 nested_vmx_succeed(vcpu
);
6759 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6761 /* Emulate the VMLAUNCH instruction */
6762 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6764 return nested_vmx_run(vcpu
, true);
6767 /* Emulate the VMRESUME instruction */
6768 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6771 return nested_vmx_run(vcpu
, false);
6774 enum vmcs_field_type
{
6775 VMCS_FIELD_TYPE_U16
= 0,
6776 VMCS_FIELD_TYPE_U64
= 1,
6777 VMCS_FIELD_TYPE_U32
= 2,
6778 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6781 static inline int vmcs_field_type(unsigned long field
)
6783 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6784 return VMCS_FIELD_TYPE_U32
;
6785 return (field
>> 13) & 0x3 ;
6788 static inline int vmcs_field_readonly(unsigned long field
)
6790 return (((field
>> 10) & 0x3) == 1);
6794 * Read a vmcs12 field. Since these can have varying lengths and we return
6795 * one type, we chose the biggest type (u64) and zero-extend the return value
6796 * to that size. Note that the caller, handle_vmread, might need to use only
6797 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6798 * 64-bit fields are to be returned).
6800 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6801 unsigned long field
, u64
*ret
)
6803 short offset
= vmcs_field_to_offset(field
);
6809 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6811 switch (vmcs_field_type(field
)) {
6812 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6813 *ret
= *((natural_width
*)p
);
6815 case VMCS_FIELD_TYPE_U16
:
6818 case VMCS_FIELD_TYPE_U32
:
6821 case VMCS_FIELD_TYPE_U64
:
6831 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6832 unsigned long field
, u64 field_value
){
6833 short offset
= vmcs_field_to_offset(field
);
6834 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6838 switch (vmcs_field_type(field
)) {
6839 case VMCS_FIELD_TYPE_U16
:
6840 *(u16
*)p
= field_value
;
6842 case VMCS_FIELD_TYPE_U32
:
6843 *(u32
*)p
= field_value
;
6845 case VMCS_FIELD_TYPE_U64
:
6846 *(u64
*)p
= field_value
;
6848 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6849 *(natural_width
*)p
= field_value
;
6858 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6861 unsigned long field
;
6863 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6864 const unsigned long *fields
= shadow_read_write_fields
;
6865 const int num_fields
= max_shadow_read_write_fields
;
6869 vmcs_load(shadow_vmcs
);
6871 for (i
= 0; i
< num_fields
; i
++) {
6873 switch (vmcs_field_type(field
)) {
6874 case VMCS_FIELD_TYPE_U16
:
6875 field_value
= vmcs_read16(field
);
6877 case VMCS_FIELD_TYPE_U32
:
6878 field_value
= vmcs_read32(field
);
6880 case VMCS_FIELD_TYPE_U64
:
6881 field_value
= vmcs_read64(field
);
6883 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6884 field_value
= vmcs_readl(field
);
6890 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6893 vmcs_clear(shadow_vmcs
);
6894 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6899 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6901 const unsigned long *fields
[] = {
6902 shadow_read_write_fields
,
6903 shadow_read_only_fields
6905 const int max_fields
[] = {
6906 max_shadow_read_write_fields
,
6907 max_shadow_read_only_fields
6910 unsigned long field
;
6911 u64 field_value
= 0;
6912 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6914 vmcs_load(shadow_vmcs
);
6916 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6917 for (i
= 0; i
< max_fields
[q
]; i
++) {
6918 field
= fields
[q
][i
];
6919 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6921 switch (vmcs_field_type(field
)) {
6922 case VMCS_FIELD_TYPE_U16
:
6923 vmcs_write16(field
, (u16
)field_value
);
6925 case VMCS_FIELD_TYPE_U32
:
6926 vmcs_write32(field
, (u32
)field_value
);
6928 case VMCS_FIELD_TYPE_U64
:
6929 vmcs_write64(field
, (u64
)field_value
);
6931 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6932 vmcs_writel(field
, (long)field_value
);
6941 vmcs_clear(shadow_vmcs
);
6942 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6946 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6947 * used before) all generate the same failure when it is missing.
6949 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6951 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6952 if (vmx
->nested
.current_vmptr
== -1ull) {
6953 nested_vmx_failInvalid(vcpu
);
6954 skip_emulated_instruction(vcpu
);
6960 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6962 unsigned long field
;
6964 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6965 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6968 if (!nested_vmx_check_permission(vcpu
) ||
6969 !nested_vmx_check_vmcs12(vcpu
))
6972 /* Decode instruction info and find the field to read */
6973 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6974 /* Read the field, zero-extended to a u64 field_value */
6975 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
6976 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6977 skip_emulated_instruction(vcpu
);
6981 * Now copy part of this value to register or memory, as requested.
6982 * Note that the number of bits actually copied is 32 or 64 depending
6983 * on the guest's mode (32 or 64 bit), not on the given field's length.
6985 if (vmx_instruction_info
& (1u << 10)) {
6986 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6989 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6990 vmx_instruction_info
, true, &gva
))
6992 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6993 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6994 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6997 nested_vmx_succeed(vcpu
);
6998 skip_emulated_instruction(vcpu
);
7003 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7005 unsigned long field
;
7007 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7008 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7009 /* The value to write might be 32 or 64 bits, depending on L1's long
7010 * mode, and eventually we need to write that into a field of several
7011 * possible lengths. The code below first zero-extends the value to 64
7012 * bit (field_value), and then copies only the approriate number of
7013 * bits into the vmcs12 field.
7015 u64 field_value
= 0;
7016 struct x86_exception e
;
7018 if (!nested_vmx_check_permission(vcpu
) ||
7019 !nested_vmx_check_vmcs12(vcpu
))
7022 if (vmx_instruction_info
& (1u << 10))
7023 field_value
= kvm_register_readl(vcpu
,
7024 (((vmx_instruction_info
) >> 3) & 0xf));
7026 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7027 vmx_instruction_info
, false, &gva
))
7029 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7030 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7031 kvm_inject_page_fault(vcpu
, &e
);
7037 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7038 if (vmcs_field_readonly(field
)) {
7039 nested_vmx_failValid(vcpu
,
7040 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7041 skip_emulated_instruction(vcpu
);
7045 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7046 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7047 skip_emulated_instruction(vcpu
);
7051 nested_vmx_succeed(vcpu
);
7052 skip_emulated_instruction(vcpu
);
7056 /* Emulate the VMPTRLD instruction */
7057 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7059 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7063 if (!nested_vmx_check_permission(vcpu
))
7066 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7069 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7070 struct vmcs12
*new_vmcs12
;
7072 page
= nested_get_page(vcpu
, vmptr
);
7074 nested_vmx_failInvalid(vcpu
);
7075 skip_emulated_instruction(vcpu
);
7078 new_vmcs12
= kmap(page
);
7079 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7081 nested_release_page_clean(page
);
7082 nested_vmx_failValid(vcpu
,
7083 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7084 skip_emulated_instruction(vcpu
);
7088 nested_release_vmcs12(vmx
);
7089 vmx
->nested
.current_vmptr
= vmptr
;
7090 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7091 vmx
->nested
.current_vmcs12_page
= page
;
7092 if (enable_shadow_vmcs
) {
7093 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7094 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
7095 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7096 vmcs_write64(VMCS_LINK_POINTER
,
7097 __pa(vmx
->nested
.current_shadow_vmcs
));
7098 vmx
->nested
.sync_shadow_vmcs
= true;
7102 nested_vmx_succeed(vcpu
);
7103 skip_emulated_instruction(vcpu
);
7107 /* Emulate the VMPTRST instruction */
7108 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7110 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7111 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7113 struct x86_exception e
;
7115 if (!nested_vmx_check_permission(vcpu
))
7118 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7119 vmx_instruction_info
, true, &vmcs_gva
))
7121 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7122 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7123 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7125 kvm_inject_page_fault(vcpu
, &e
);
7128 nested_vmx_succeed(vcpu
);
7129 skip_emulated_instruction(vcpu
);
7133 /* Emulate the INVEPT instruction */
7134 static int handle_invept(struct kvm_vcpu
*vcpu
)
7136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7137 u32 vmx_instruction_info
, types
;
7140 struct x86_exception e
;
7145 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7146 SECONDARY_EXEC_ENABLE_EPT
) ||
7147 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7148 kvm_queue_exception(vcpu
, UD_VECTOR
);
7152 if (!nested_vmx_check_permission(vcpu
))
7155 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7156 kvm_queue_exception(vcpu
, UD_VECTOR
);
7160 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7161 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7163 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7165 if (!(types
& (1UL << type
))) {
7166 nested_vmx_failValid(vcpu
,
7167 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7171 /* According to the Intel VMX instruction reference, the memory
7172 * operand is read even if it isn't needed (e.g., for type==global)
7174 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7175 vmx_instruction_info
, false, &gva
))
7177 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7178 sizeof(operand
), &e
)) {
7179 kvm_inject_page_fault(vcpu
, &e
);
7184 case VMX_EPT_EXTENT_GLOBAL
:
7185 kvm_mmu_sync_roots(vcpu
);
7186 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7187 nested_vmx_succeed(vcpu
);
7190 /* Trap single context invalidation invept calls */
7195 skip_emulated_instruction(vcpu
);
7199 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7201 kvm_queue_exception(vcpu
, UD_VECTOR
);
7205 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7207 unsigned long exit_qualification
;
7209 trace_kvm_pml_full(vcpu
->vcpu_id
);
7211 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7214 * PML buffer FULL happened while executing iret from NMI,
7215 * "blocked by NMI" bit has to be set before next VM entry.
7217 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7218 cpu_has_virtual_nmis() &&
7219 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7220 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7221 GUEST_INTR_STATE_NMI
);
7224 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7225 * here.., and there's no userspace involvement needed for PML.
7231 * The exit handlers return 1 if the exit was handled fully and guest execution
7232 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7233 * to be done to userspace and return 0.
7235 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7236 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7237 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7238 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7239 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7240 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7241 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7242 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7243 [EXIT_REASON_CPUID
] = handle_cpuid
,
7244 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7245 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7246 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7247 [EXIT_REASON_HLT
] = handle_halt
,
7248 [EXIT_REASON_INVD
] = handle_invd
,
7249 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7250 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7251 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7252 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7253 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7254 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7255 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7256 [EXIT_REASON_VMREAD
] = handle_vmread
,
7257 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7258 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7259 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7260 [EXIT_REASON_VMON
] = handle_vmon
,
7261 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7262 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7263 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7264 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7265 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7266 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7267 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7268 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7269 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7270 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7271 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7272 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7273 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7274 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7275 [EXIT_REASON_INVEPT
] = handle_invept
,
7276 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7277 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7278 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7279 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7282 static const int kvm_vmx_max_exit_handlers
=
7283 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7285 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7286 struct vmcs12
*vmcs12
)
7288 unsigned long exit_qualification
;
7289 gpa_t bitmap
, last_bitmap
;
7294 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7295 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7297 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7299 port
= exit_qualification
>> 16;
7300 size
= (exit_qualification
& 7) + 1;
7302 last_bitmap
= (gpa_t
)-1;
7307 bitmap
= vmcs12
->io_bitmap_a
;
7308 else if (port
< 0x10000)
7309 bitmap
= vmcs12
->io_bitmap_b
;
7312 bitmap
+= (port
& 0x7fff) / 8;
7314 if (last_bitmap
!= bitmap
)
7315 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7317 if (b
& (1 << (port
& 7)))
7322 last_bitmap
= bitmap
;
7329 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7330 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7331 * disinterest in the current event (read or write a specific MSR) by using an
7332 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7334 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7335 struct vmcs12
*vmcs12
, u32 exit_reason
)
7337 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7340 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7344 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7345 * for the four combinations of read/write and low/high MSR numbers.
7346 * First we need to figure out which of the four to use:
7348 bitmap
= vmcs12
->msr_bitmap
;
7349 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7351 if (msr_index
>= 0xc0000000) {
7352 msr_index
-= 0xc0000000;
7356 /* Then read the msr_index'th bit from this bitmap: */
7357 if (msr_index
< 1024*8) {
7359 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7361 return 1 & (b
>> (msr_index
& 7));
7363 return true; /* let L1 handle the wrong parameter */
7367 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7368 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7369 * intercept (via guest_host_mask etc.) the current event.
7371 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7372 struct vmcs12
*vmcs12
)
7374 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7375 int cr
= exit_qualification
& 15;
7376 int reg
= (exit_qualification
>> 8) & 15;
7377 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7379 switch ((exit_qualification
>> 4) & 3) {
7380 case 0: /* mov to cr */
7383 if (vmcs12
->cr0_guest_host_mask
&
7384 (val
^ vmcs12
->cr0_read_shadow
))
7388 if ((vmcs12
->cr3_target_count
>= 1 &&
7389 vmcs12
->cr3_target_value0
== val
) ||
7390 (vmcs12
->cr3_target_count
>= 2 &&
7391 vmcs12
->cr3_target_value1
== val
) ||
7392 (vmcs12
->cr3_target_count
>= 3 &&
7393 vmcs12
->cr3_target_value2
== val
) ||
7394 (vmcs12
->cr3_target_count
>= 4 &&
7395 vmcs12
->cr3_target_value3
== val
))
7397 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7401 if (vmcs12
->cr4_guest_host_mask
&
7402 (vmcs12
->cr4_read_shadow
^ val
))
7406 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7412 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7413 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7416 case 1: /* mov from cr */
7419 if (vmcs12
->cpu_based_vm_exec_control
&
7420 CPU_BASED_CR3_STORE_EXITING
)
7424 if (vmcs12
->cpu_based_vm_exec_control
&
7425 CPU_BASED_CR8_STORE_EXITING
)
7432 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7433 * cr0. Other attempted changes are ignored, with no exit.
7435 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7436 (val
^ vmcs12
->cr0_read_shadow
))
7438 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7439 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7448 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7449 * should handle it ourselves in L0 (and then continue L2). Only call this
7450 * when in is_guest_mode (L2).
7452 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7454 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7455 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7456 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7457 u32 exit_reason
= vmx
->exit_reason
;
7459 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7460 vmcs_readl(EXIT_QUALIFICATION
),
7461 vmx
->idt_vectoring_info
,
7463 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7466 if (vmx
->nested
.nested_run_pending
)
7469 if (unlikely(vmx
->fail
)) {
7470 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7471 vmcs_read32(VM_INSTRUCTION_ERROR
));
7475 switch (exit_reason
) {
7476 case EXIT_REASON_EXCEPTION_NMI
:
7477 if (!is_exception(intr_info
))
7479 else if (is_page_fault(intr_info
))
7481 else if (is_no_device(intr_info
) &&
7482 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7484 return vmcs12
->exception_bitmap
&
7485 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7486 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7488 case EXIT_REASON_TRIPLE_FAULT
:
7490 case EXIT_REASON_PENDING_INTERRUPT
:
7491 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7492 case EXIT_REASON_NMI_WINDOW
:
7493 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7494 case EXIT_REASON_TASK_SWITCH
:
7496 case EXIT_REASON_CPUID
:
7497 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7500 case EXIT_REASON_HLT
:
7501 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7502 case EXIT_REASON_INVD
:
7504 case EXIT_REASON_INVLPG
:
7505 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7506 case EXIT_REASON_RDPMC
:
7507 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7508 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7509 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7510 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7511 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7512 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7513 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7514 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7515 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7517 * VMX instructions trap unconditionally. This allows L1 to
7518 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7521 case EXIT_REASON_CR_ACCESS
:
7522 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7523 case EXIT_REASON_DR_ACCESS
:
7524 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7525 case EXIT_REASON_IO_INSTRUCTION
:
7526 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7527 case EXIT_REASON_MSR_READ
:
7528 case EXIT_REASON_MSR_WRITE
:
7529 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7530 case EXIT_REASON_INVALID_STATE
:
7532 case EXIT_REASON_MWAIT_INSTRUCTION
:
7533 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7534 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7535 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7536 case EXIT_REASON_MONITOR_INSTRUCTION
:
7537 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7538 case EXIT_REASON_PAUSE_INSTRUCTION
:
7539 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7540 nested_cpu_has2(vmcs12
,
7541 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7542 case EXIT_REASON_MCE_DURING_VMENTRY
:
7544 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7545 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7546 case EXIT_REASON_APIC_ACCESS
:
7547 return nested_cpu_has2(vmcs12
,
7548 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7549 case EXIT_REASON_APIC_WRITE
:
7550 case EXIT_REASON_EOI_INDUCED
:
7551 /* apic_write and eoi_induced should exit unconditionally. */
7553 case EXIT_REASON_EPT_VIOLATION
:
7555 * L0 always deals with the EPT violation. If nested EPT is
7556 * used, and the nested mmu code discovers that the address is
7557 * missing in the guest EPT table (EPT12), the EPT violation
7558 * will be injected with nested_ept_inject_page_fault()
7561 case EXIT_REASON_EPT_MISCONFIG
:
7563 * L2 never uses directly L1's EPT, but rather L0's own EPT
7564 * table (shadow on EPT) or a merged EPT table that L0 built
7565 * (EPT on EPT). So any problems with the structure of the
7566 * table is L0's fault.
7569 case EXIT_REASON_WBINVD
:
7570 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7571 case EXIT_REASON_XSETBV
:
7573 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7575 * This should never happen, since it is not possible to
7576 * set XSS to a non-zero value---neither in L1 nor in L2.
7577 * If if it were, XSS would have to be checked against
7578 * the XSS exit bitmap in vmcs12.
7580 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7586 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7588 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7589 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7592 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7594 struct page
*pml_pg
;
7597 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7601 vmx
->pml_pg
= pml_pg
;
7603 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7604 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7606 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7607 exec_control
|= SECONDARY_EXEC_ENABLE_PML
;
7608 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7613 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7617 ASSERT(vmx
->pml_pg
);
7618 __free_page(vmx
->pml_pg
);
7621 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7622 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
7623 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7626 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7628 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7632 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7634 /* Do nothing if PML buffer is empty */
7635 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7638 /* PML index always points to next available PML buffer entity */
7639 if (pml_idx
>= PML_ENTITY_NUM
)
7644 pml_buf
= page_address(vmx
->pml_pg
);
7645 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7648 gpa
= pml_buf
[pml_idx
];
7649 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7650 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7653 /* reset PML index */
7654 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7658 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7659 * Called before reporting dirty_bitmap to userspace.
7661 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7664 struct kvm_vcpu
*vcpu
;
7666 * We only need to kick vcpu out of guest mode here, as PML buffer
7667 * is flushed at beginning of all VMEXITs, and it's obvious that only
7668 * vcpus running in guest are possible to have unflushed GPAs in PML
7671 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7672 kvm_vcpu_kick(vcpu
);
7675 static void vmx_dump_sel(char *name
, uint32_t sel
)
7677 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7678 name
, vmcs_read32(sel
),
7679 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7680 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7681 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7684 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7686 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7687 name
, vmcs_read32(limit
),
7688 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7691 static void dump_vmcs(void)
7693 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7694 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7695 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7696 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7697 u32 secondary_exec_control
= 0;
7698 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7699 u64 efer
= vmcs_readl(GUEST_IA32_EFER
);
7702 if (cpu_has_secondary_exec_ctrls())
7703 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7705 pr_err("*** Guest State ***\n");
7706 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7707 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7708 vmcs_readl(CR0_GUEST_HOST_MASK
));
7709 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7710 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7711 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7712 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7713 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7715 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7716 vmcs_readl(GUEST_PDPTR0
), vmcs_readl(GUEST_PDPTR1
));
7717 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7718 vmcs_readl(GUEST_PDPTR2
), vmcs_readl(GUEST_PDPTR3
));
7720 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7721 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
7722 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7723 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
7724 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7725 vmcs_readl(GUEST_SYSENTER_ESP
),
7726 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
7727 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
7728 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
7729 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
7730 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
7731 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
7732 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
7733 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
7734 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
7735 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
7736 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
7737 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
7738 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
7739 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7740 efer
, vmcs_readl(GUEST_IA32_PAT
));
7741 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7742 vmcs_readl(GUEST_IA32_DEBUGCTL
),
7743 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
7744 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
7745 pr_err("PerfGlobCtl = 0x%016lx\n",
7746 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL
));
7747 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
7748 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS
));
7749 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7750 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
7751 vmcs_read32(GUEST_ACTIVITY_STATE
));
7752 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
7753 pr_err("InterruptStatus = %04x\n",
7754 vmcs_read16(GUEST_INTR_STATUS
));
7756 pr_err("*** Host State ***\n");
7757 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7758 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
7759 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7760 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
7761 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
7762 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
7763 vmcs_read16(HOST_TR_SELECTOR
));
7764 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7765 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
7766 vmcs_readl(HOST_TR_BASE
));
7767 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7768 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
7769 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7770 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
7771 vmcs_readl(HOST_CR4
));
7772 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7773 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
7774 vmcs_read32(HOST_IA32_SYSENTER_CS
),
7775 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
7776 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
7777 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7778 vmcs_readl(HOST_IA32_EFER
), vmcs_readl(HOST_IA32_PAT
));
7779 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7780 pr_err("PerfGlobCtl = 0x%016lx\n",
7781 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL
));
7783 pr_err("*** Control State ***\n");
7784 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7785 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
7786 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
7787 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7788 vmcs_read32(EXCEPTION_BITMAP
),
7789 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
7790 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
7791 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
7792 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7793 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
7794 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
7795 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
7796 vmcs_read32(VM_EXIT_INTR_INFO
),
7797 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7798 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
7799 pr_err(" reason=%08x qualification=%016lx\n",
7800 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
7801 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
7802 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
7803 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
7804 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET
));
7805 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
7806 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
7807 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
7808 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
7809 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
7810 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER
));
7811 n
= vmcs_read32(CR3_TARGET_COUNT
);
7812 for (i
= 0; i
+ 1 < n
; i
+= 4)
7813 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
7814 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
7815 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
7817 pr_err("CR3 target%u=%016lx\n",
7818 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
7819 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
7820 pr_err("PLE Gap=%08x Window=%08x\n",
7821 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
7822 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
7823 pr_err("Virtual processor ID = 0x%04x\n",
7824 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
7828 * The guest has exited. See if we can fix it or if we need userspace
7831 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7833 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7834 u32 exit_reason
= vmx
->exit_reason
;
7835 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7838 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7839 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7840 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7841 * mode as if vcpus is in root mode, the PML buffer must has been
7845 vmx_flush_pml_buffer(vcpu
);
7847 /* If guest state is invalid, start emulating */
7848 if (vmx
->emulation_required
)
7849 return handle_invalid_guest_state(vcpu
);
7851 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7852 nested_vmx_vmexit(vcpu
, exit_reason
,
7853 vmcs_read32(VM_EXIT_INTR_INFO
),
7854 vmcs_readl(EXIT_QUALIFICATION
));
7858 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7860 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7861 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7866 if (unlikely(vmx
->fail
)) {
7867 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7868 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7869 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7875 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7876 * delivery event since it indicates guest is accessing MMIO.
7877 * The vm-exit can be triggered again after return to guest that
7878 * will cause infinite loop.
7880 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7881 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7882 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7883 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7884 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7885 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7886 vcpu
->run
->internal
.ndata
= 2;
7887 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7888 vcpu
->run
->internal
.data
[1] = exit_reason
;
7892 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7893 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7894 get_vmcs12(vcpu
))))) {
7895 if (vmx_interrupt_allowed(vcpu
)) {
7896 vmx
->soft_vnmi_blocked
= 0;
7897 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7898 vcpu
->arch
.nmi_pending
) {
7900 * This CPU don't support us in finding the end of an
7901 * NMI-blocked window if the guest runs with IRQs
7902 * disabled. So we pull the trigger after 1 s of
7903 * futile waiting, but inform the user about this.
7905 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7906 "state on VCPU %d after 1 s timeout\n",
7907 __func__
, vcpu
->vcpu_id
);
7908 vmx
->soft_vnmi_blocked
= 0;
7912 if (exit_reason
< kvm_vmx_max_exit_handlers
7913 && kvm_vmx_exit_handlers
[exit_reason
])
7914 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7916 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7917 kvm_queue_exception(vcpu
, UD_VECTOR
);
7922 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7924 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7926 if (is_guest_mode(vcpu
) &&
7927 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7930 if (irr
== -1 || tpr
< irr
) {
7931 vmcs_write32(TPR_THRESHOLD
, 0);
7935 vmcs_write32(TPR_THRESHOLD
, irr
);
7938 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7940 u32 sec_exec_control
;
7943 * There is not point to enable virtualize x2apic without enable
7946 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7947 !vmx_vm_has_apicv(vcpu
->kvm
))
7950 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7953 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7956 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7957 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7959 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7960 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7962 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7964 vmx_set_msr_bitmap(vcpu
);
7967 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
7969 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7972 * Currently we do not handle the nested case where L2 has an
7973 * APIC access page of its own; that page is still pinned.
7974 * Hence, we skip the case where the VCPU is in guest mode _and_
7975 * L1 prepared an APIC access page for L2.
7977 * For the case where L1 and L2 share the same APIC access page
7978 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7979 * in the vmcs12), this function will only update either the vmcs01
7980 * or the vmcs02. If the former, the vmcs02 will be updated by
7981 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7982 * the next L2->L1 exit.
7984 if (!is_guest_mode(vcpu
) ||
7985 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
7986 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
7987 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
7990 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7998 status
= vmcs_read16(GUEST_INTR_STATUS
);
8003 vmcs_write16(GUEST_INTR_STATUS
, status
);
8007 static void vmx_set_rvi(int vector
)
8015 status
= vmcs_read16(GUEST_INTR_STATUS
);
8016 old
= (u8
)status
& 0xff;
8017 if ((u8
)vector
!= old
) {
8019 status
|= (u8
)vector
;
8020 vmcs_write16(GUEST_INTR_STATUS
, status
);
8024 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8026 if (!is_guest_mode(vcpu
)) {
8027 vmx_set_rvi(max_irr
);
8035 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8038 if (nested_exit_on_intr(vcpu
))
8042 * Else, fall back to pre-APICv interrupt injection since L2
8043 * is run without virtual interrupt delivery.
8045 if (!kvm_event_needs_reinjection(vcpu
) &&
8046 vmx_interrupt_allowed(vcpu
)) {
8047 kvm_queue_interrupt(vcpu
, max_irr
, false);
8048 vmx_inject_irq(vcpu
);
8052 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
8054 u64
*eoi_exit_bitmap
= vcpu
->arch
.eoi_exit_bitmap
;
8055 if (!vmx_vm_has_apicv(vcpu
->kvm
))
8058 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8059 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8060 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8061 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8064 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8068 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8069 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8072 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8073 exit_intr_info
= vmx
->exit_intr_info
;
8075 /* Handle machine checks before interrupts are enabled */
8076 if (is_machine_check(exit_intr_info
))
8077 kvm_machine_check();
8079 /* We need to handle NMIs before interrupts are enabled */
8080 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8081 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8082 kvm_before_handle_nmi(&vmx
->vcpu
);
8084 kvm_after_handle_nmi(&vmx
->vcpu
);
8088 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8090 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8093 * If external interrupt exists, IF bit is set in rflags/eflags on the
8094 * interrupt stack frame, and interrupt will be enabled on a return
8095 * from interrupt handler.
8097 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8098 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8099 unsigned int vector
;
8100 unsigned long entry
;
8102 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8103 #ifdef CONFIG_X86_64
8107 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8108 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8109 entry
= gate_offset(*desc
);
8111 #ifdef CONFIG_X86_64
8112 "mov %%" _ASM_SP
", %[sp]\n\t"
8113 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8118 "orl $0x200, (%%" _ASM_SP
")\n\t"
8119 __ASM_SIZE(push
) " $%c[cs]\n\t"
8120 "call *%[entry]\n\t"
8122 #ifdef CONFIG_X86_64
8127 [ss
]"i"(__KERNEL_DS
),
8128 [cs
]"i"(__KERNEL_CS
)
8134 static bool vmx_has_high_real_mode_segbase(void)
8136 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8139 static bool vmx_mpx_supported(void)
8141 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8142 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8145 static bool vmx_xsaves_supported(void)
8147 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8148 SECONDARY_EXEC_XSAVES
;
8151 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8156 bool idtv_info_valid
;
8158 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8160 if (cpu_has_virtual_nmis()) {
8161 if (vmx
->nmi_known_unmasked
)
8164 * Can't use vmx->exit_intr_info since we're not sure what
8165 * the exit reason is.
8167 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8168 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8169 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8171 * SDM 3: 27.7.1.2 (September 2008)
8172 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8173 * a guest IRET fault.
8174 * SDM 3: 23.2.2 (September 2008)
8175 * Bit 12 is undefined in any of the following cases:
8176 * If the VM exit sets the valid bit in the IDT-vectoring
8177 * information field.
8178 * If the VM exit is due to a double fault.
8180 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8181 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8182 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8183 GUEST_INTR_STATE_NMI
);
8185 vmx
->nmi_known_unmasked
=
8186 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8187 & GUEST_INTR_STATE_NMI
);
8188 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8189 vmx
->vnmi_blocked_time
+=
8190 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8193 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8194 u32 idt_vectoring_info
,
8195 int instr_len_field
,
8196 int error_code_field
)
8200 bool idtv_info_valid
;
8202 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8204 vcpu
->arch
.nmi_injected
= false;
8205 kvm_clear_exception_queue(vcpu
);
8206 kvm_clear_interrupt_queue(vcpu
);
8208 if (!idtv_info_valid
)
8211 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8213 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8214 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8217 case INTR_TYPE_NMI_INTR
:
8218 vcpu
->arch
.nmi_injected
= true;
8220 * SDM 3: 27.7.1.2 (September 2008)
8221 * Clear bit "block by NMI" before VM entry if a NMI
8224 vmx_set_nmi_mask(vcpu
, false);
8226 case INTR_TYPE_SOFT_EXCEPTION
:
8227 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8229 case INTR_TYPE_HARD_EXCEPTION
:
8230 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8231 u32 err
= vmcs_read32(error_code_field
);
8232 kvm_requeue_exception_e(vcpu
, vector
, err
);
8234 kvm_requeue_exception(vcpu
, vector
);
8236 case INTR_TYPE_SOFT_INTR
:
8237 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8239 case INTR_TYPE_EXT_INTR
:
8240 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8247 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8249 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8250 VM_EXIT_INSTRUCTION_LEN
,
8251 IDT_VECTORING_ERROR_CODE
);
8254 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8256 __vmx_complete_interrupts(vcpu
,
8257 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8258 VM_ENTRY_INSTRUCTION_LEN
,
8259 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8261 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8264 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8267 struct perf_guest_switch_msr
*msrs
;
8269 msrs
= perf_guest_get_msrs(&nr_msrs
);
8274 for (i
= 0; i
< nr_msrs
; i
++)
8275 if (msrs
[i
].host
== msrs
[i
].guest
)
8276 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8278 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8282 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8284 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8285 unsigned long debugctlmsr
, cr4
;
8287 /* Record the guest's net vcpu time for enforced NMI injections. */
8288 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8289 vmx
->entry_time
= ktime_get();
8291 /* Don't enter VMX if guest state is invalid, let the exit handler
8292 start emulation until we arrive back to a valid state */
8293 if (vmx
->emulation_required
)
8296 if (vmx
->ple_window_dirty
) {
8297 vmx
->ple_window_dirty
= false;
8298 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8301 if (vmx
->nested
.sync_shadow_vmcs
) {
8302 copy_vmcs12_to_shadow(vmx
);
8303 vmx
->nested
.sync_shadow_vmcs
= false;
8306 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8307 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8308 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8309 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8311 cr4
= cr4_read_shadow();
8312 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8313 vmcs_writel(HOST_CR4
, cr4
);
8314 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8317 /* When single-stepping over STI and MOV SS, we must clear the
8318 * corresponding interruptibility bits in the guest state. Otherwise
8319 * vmentry fails as it then expects bit 14 (BS) in pending debug
8320 * exceptions being set, but that's not correct for the guest debugging
8322 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8323 vmx_set_interrupt_shadow(vcpu
, 0);
8325 atomic_switch_perf_msrs(vmx
);
8326 debugctlmsr
= get_debugctlmsr();
8328 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8330 /* Store host registers */
8331 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8332 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8333 "push %%" _ASM_CX
" \n\t"
8334 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8336 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8337 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8339 /* Reload cr2 if changed */
8340 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8341 "mov %%cr2, %%" _ASM_DX
" \n\t"
8342 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8344 "mov %%" _ASM_AX
", %%cr2 \n\t"
8346 /* Check if vmlaunch of vmresume is needed */
8347 "cmpl $0, %c[launched](%0) \n\t"
8348 /* Load guest registers. Don't clobber flags. */
8349 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8350 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8351 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8352 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8353 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8354 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8355 #ifdef CONFIG_X86_64
8356 "mov %c[r8](%0), %%r8 \n\t"
8357 "mov %c[r9](%0), %%r9 \n\t"
8358 "mov %c[r10](%0), %%r10 \n\t"
8359 "mov %c[r11](%0), %%r11 \n\t"
8360 "mov %c[r12](%0), %%r12 \n\t"
8361 "mov %c[r13](%0), %%r13 \n\t"
8362 "mov %c[r14](%0), %%r14 \n\t"
8363 "mov %c[r15](%0), %%r15 \n\t"
8365 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8367 /* Enter guest mode */
8369 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8371 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8373 /* Save guest registers, load host registers, keep flags */
8374 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8376 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8377 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8378 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8379 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8380 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8381 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8382 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8383 #ifdef CONFIG_X86_64
8384 "mov %%r8, %c[r8](%0) \n\t"
8385 "mov %%r9, %c[r9](%0) \n\t"
8386 "mov %%r10, %c[r10](%0) \n\t"
8387 "mov %%r11, %c[r11](%0) \n\t"
8388 "mov %%r12, %c[r12](%0) \n\t"
8389 "mov %%r13, %c[r13](%0) \n\t"
8390 "mov %%r14, %c[r14](%0) \n\t"
8391 "mov %%r15, %c[r15](%0) \n\t"
8393 "mov %%cr2, %%" _ASM_AX
" \n\t"
8394 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8396 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8397 "setbe %c[fail](%0) \n\t"
8398 ".pushsection .rodata \n\t"
8399 ".global vmx_return \n\t"
8400 "vmx_return: " _ASM_PTR
" 2b \n\t"
8402 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8403 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8404 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8405 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8406 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8407 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8408 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8409 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8410 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8411 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8412 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8413 #ifdef CONFIG_X86_64
8414 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8415 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8416 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8417 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8418 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8419 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8420 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8421 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8423 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8424 [wordsize
]"i"(sizeof(ulong
))
8426 #ifdef CONFIG_X86_64
8427 , "rax", "rbx", "rdi", "rsi"
8428 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8430 , "eax", "ebx", "edi", "esi"
8434 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8436 update_debugctlmsr(debugctlmsr
);
8438 #ifndef CONFIG_X86_64
8440 * The sysexit path does not restore ds/es, so we must set them to
8441 * a reasonable value ourselves.
8443 * We can't defer this to vmx_load_host_state() since that function
8444 * may be executed in interrupt context, which saves and restore segments
8445 * around it, nullifying its effect.
8447 loadsegment(ds
, __USER_DS
);
8448 loadsegment(es
, __USER_DS
);
8451 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8452 | (1 << VCPU_EXREG_RFLAGS
)
8453 | (1 << VCPU_EXREG_PDPTR
)
8454 | (1 << VCPU_EXREG_SEGMENTS
)
8455 | (1 << VCPU_EXREG_CR3
));
8456 vcpu
->arch
.regs_dirty
= 0;
8458 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8460 vmx
->loaded_vmcs
->launched
= 1;
8462 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8463 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8466 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8467 * we did not inject a still-pending event to L1 now because of
8468 * nested_run_pending, we need to re-enable this bit.
8470 if (vmx
->nested
.nested_run_pending
)
8471 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8473 vmx
->nested
.nested_run_pending
= 0;
8475 vmx_complete_atomic_exit(vmx
);
8476 vmx_recover_nmi_blocking(vmx
);
8477 vmx_complete_interrupts(vmx
);
8480 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8482 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8485 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8489 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8491 vmx_vcpu_load(vcpu
, cpu
);
8496 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8498 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8501 vmx_disable_pml(vmx
);
8503 leave_guest_mode(vcpu
);
8504 vmx_load_vmcs01(vcpu
);
8506 free_loaded_vmcs(vmx
->loaded_vmcs
);
8507 kfree(vmx
->guest_msrs
);
8508 kvm_vcpu_uninit(vcpu
);
8509 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8512 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8515 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8519 return ERR_PTR(-ENOMEM
);
8523 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8527 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8528 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8532 if (!vmx
->guest_msrs
) {
8536 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8537 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8538 if (!vmx
->loaded_vmcs
->vmcs
)
8541 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8542 loaded_vmcs_init(vmx
->loaded_vmcs
);
8547 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8548 vmx
->vcpu
.cpu
= cpu
;
8549 err
= vmx_vcpu_setup(vmx
);
8550 vmx_vcpu_put(&vmx
->vcpu
);
8554 if (vm_need_virtualize_apic_accesses(kvm
)) {
8555 err
= alloc_apic_access_page(kvm
);
8561 if (!kvm
->arch
.ept_identity_map_addr
)
8562 kvm
->arch
.ept_identity_map_addr
=
8563 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8564 err
= init_rmode_identity_map(kvm
);
8570 nested_vmx_setup_ctls_msrs(vmx
);
8572 vmx
->nested
.posted_intr_nv
= -1;
8573 vmx
->nested
.current_vmptr
= -1ull;
8574 vmx
->nested
.current_vmcs12
= NULL
;
8577 * If PML is turned on, failure on enabling PML just results in failure
8578 * of creating the vcpu, therefore we can simplify PML logic (by
8579 * avoiding dealing with cases, such as enabling PML partially on vcpus
8580 * for the guest, etc.
8583 err
= vmx_enable_pml(vmx
);
8591 free_loaded_vmcs(vmx
->loaded_vmcs
);
8593 kfree(vmx
->guest_msrs
);
8595 kvm_vcpu_uninit(&vmx
->vcpu
);
8598 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8599 return ERR_PTR(err
);
8602 static void __init
vmx_check_processor_compat(void *rtn
)
8604 struct vmcs_config vmcs_conf
;
8607 if (setup_vmcs_config(&vmcs_conf
) < 0)
8609 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8610 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8611 smp_processor_id());
8616 static int get_ept_level(void)
8618 return VMX_EPT_DEFAULT_GAW
+ 1;
8621 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8626 /* For VT-d and EPT combination
8627 * 1. MMIO: always map as UC
8629 * a. VT-d without snooping control feature: can't guarantee the
8630 * result, try to trust guest.
8631 * b. VT-d with snooping control feature: snooping control feature of
8632 * VT-d engine can guarantee the cache correctness. Just set it
8633 * to WB to keep consistent with host. So the same as item 3.
8634 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8635 * consistent with host MTRR
8638 cache
= MTRR_TYPE_UNCACHABLE
;
8642 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8643 ipat
= VMX_EPT_IPAT_BIT
;
8644 cache
= MTRR_TYPE_WRBACK
;
8648 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8649 ipat
= VMX_EPT_IPAT_BIT
;
8650 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8651 cache
= MTRR_TYPE_WRBACK
;
8653 cache
= MTRR_TYPE_UNCACHABLE
;
8657 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8660 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8663 static int vmx_get_lpage_level(void)
8665 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8666 return PT_DIRECTORY_LEVEL
;
8668 /* For shadow and EPT supported 1GB page */
8669 return PT_PDPE_LEVEL
;
8672 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8674 struct kvm_cpuid_entry2
*best
;
8675 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8678 vmx
->rdtscp_enabled
= false;
8679 if (vmx_rdtscp_supported()) {
8680 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8681 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
8682 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
8683 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
8684 vmx
->rdtscp_enabled
= true;
8686 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8691 if (nested
&& !vmx
->rdtscp_enabled
)
8692 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8693 ~SECONDARY_EXEC_RDTSCP
;
8696 /* Exposing INVPCID only when PCID is exposed */
8697 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8698 if (vmx_invpcid_supported() &&
8699 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
8700 guest_cpuid_has_pcid(vcpu
)) {
8701 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8702 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
8703 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8706 if (cpu_has_secondary_exec_ctrls()) {
8707 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8708 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8709 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8713 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8717 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8719 if (func
== 1 && nested
)
8720 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8723 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8724 struct x86_exception
*fault
)
8726 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8729 if (fault
->error_code
& PFERR_RSVD_MASK
)
8730 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8732 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8733 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8734 vmcs12
->guest_physical_address
= fault
->address
;
8737 /* Callbacks for nested_ept_init_mmu_context: */
8739 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8741 /* return the page table to be shadowed - in our case, EPT12 */
8742 return get_vmcs12(vcpu
)->ept_pointer
;
8745 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8747 WARN_ON(mmu_is_nested(vcpu
));
8748 kvm_init_shadow_ept_mmu(vcpu
,
8749 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8750 VMX_EPT_EXECUTE_ONLY_BIT
);
8751 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8752 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8753 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8755 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8758 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8760 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8763 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8766 bool inequality
, bit
;
8768 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8770 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
8771 vmcs12
->page_fault_error_code_match
;
8772 return inequality
^ bit
;
8775 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8776 struct x86_exception
*fault
)
8778 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8780 WARN_ON(!is_guest_mode(vcpu
));
8782 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
8783 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8784 vmcs_read32(VM_EXIT_INTR_INFO
),
8785 vmcs_readl(EXIT_QUALIFICATION
));
8787 kvm_inject_page_fault(vcpu
, fault
);
8790 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8791 struct vmcs12
*vmcs12
)
8793 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8794 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8796 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8797 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
8798 vmcs12
->apic_access_addr
>> maxphyaddr
)
8802 * Translate L1 physical address to host physical
8803 * address for vmcs02. Keep the page pinned, so this
8804 * physical address remains valid. We keep a reference
8805 * to it so we can release it later.
8807 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8808 nested_release_page(vmx
->nested
.apic_access_page
);
8809 vmx
->nested
.apic_access_page
=
8810 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8813 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8814 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
8815 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
8818 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8819 nested_release_page(vmx
->nested
.virtual_apic_page
);
8820 vmx
->nested
.virtual_apic_page
=
8821 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8824 * Failing the vm entry is _not_ what the processor does
8825 * but it's basically the only possibility we have.
8826 * We could still enter the guest if CR8 load exits are
8827 * enabled, CR8 store exits are enabled, and virtualize APIC
8828 * access is disabled; in this case the processor would never
8829 * use the TPR shadow and we could simply clear the bit from
8830 * the execution control. But such a configuration is useless,
8831 * so let's keep the code simple.
8833 if (!vmx
->nested
.virtual_apic_page
)
8837 if (nested_cpu_has_posted_intr(vmcs12
)) {
8838 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
8839 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
8842 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
8843 kunmap(vmx
->nested
.pi_desc_page
);
8844 nested_release_page(vmx
->nested
.pi_desc_page
);
8846 vmx
->nested
.pi_desc_page
=
8847 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
8848 if (!vmx
->nested
.pi_desc_page
)
8851 vmx
->nested
.pi_desc
=
8852 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
8853 if (!vmx
->nested
.pi_desc
) {
8854 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
8857 vmx
->nested
.pi_desc
=
8858 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
8859 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
8866 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8868 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8869 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8871 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8874 /* Make sure short timeouts reliably trigger an immediate vmexit.
8875 * hrtimer_start does not guarantee this. */
8876 if (preemption_timeout
<= 1) {
8877 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8881 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8882 preemption_timeout
*= 1000000;
8883 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8884 hrtimer_start(&vmx
->nested
.preemption_timer
,
8885 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8888 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
8889 struct vmcs12
*vmcs12
)
8894 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8897 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
8901 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8903 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
8904 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
8911 * Merge L0's and L1's MSR bitmap, return false to indicate that
8912 * we do not use the hardware.
8914 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
8915 struct vmcs12
*vmcs12
)
8919 unsigned long *msr_bitmap
;
8921 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
8924 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
8929 msr_bitmap
= (unsigned long *)kmap(page
);
8931 nested_release_page_clean(page
);
8936 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
8937 if (nested_cpu_has_apic_reg_virt(vmcs12
))
8938 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8939 nested_vmx_disable_intercept_for_msr(
8941 vmx_msr_bitmap_nested
,
8943 /* TPR is allowed */
8944 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
8945 vmx_msr_bitmap_nested
,
8946 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8947 MSR_TYPE_R
| MSR_TYPE_W
);
8948 if (nested_cpu_has_vid(vmcs12
)) {
8949 /* EOI and self-IPI are allowed */
8950 nested_vmx_disable_intercept_for_msr(
8952 vmx_msr_bitmap_nested
,
8953 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
8955 nested_vmx_disable_intercept_for_msr(
8957 vmx_msr_bitmap_nested
,
8958 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
8963 * Enable reading intercept of all the x2apic
8964 * MSRs. We should not rely on vmcs12 to do any
8965 * optimizations here, it may have been modified
8968 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8969 __vmx_enable_intercept_for_msr(
8970 vmx_msr_bitmap_nested
,
8974 __vmx_enable_intercept_for_msr(
8975 vmx_msr_bitmap_nested
,
8976 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8978 __vmx_enable_intercept_for_msr(
8979 vmx_msr_bitmap_nested
,
8980 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
8982 __vmx_enable_intercept_for_msr(
8983 vmx_msr_bitmap_nested
,
8984 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
8988 nested_release_page_clean(page
);
8993 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
8994 struct vmcs12
*vmcs12
)
8996 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
8997 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
8998 !nested_cpu_has_vid(vmcs12
) &&
8999 !nested_cpu_has_posted_intr(vmcs12
))
9003 * If virtualize x2apic mode is enabled,
9004 * virtualize apic access must be disabled.
9006 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9007 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9011 * If virtual interrupt delivery is enabled,
9012 * we must exit on external interrupts.
9014 if (nested_cpu_has_vid(vmcs12
) &&
9015 !nested_exit_on_intr(vcpu
))
9019 * bits 15:8 should be zero in posted_intr_nv,
9020 * the descriptor address has been already checked
9021 * in nested_get_vmcs12_pages.
9023 if (nested_cpu_has_posted_intr(vmcs12
) &&
9024 (!nested_cpu_has_vid(vmcs12
) ||
9025 !nested_exit_intr_ack_set(vcpu
) ||
9026 vmcs12
->posted_intr_nv
& 0xff00))
9029 /* tpr shadow is needed by all apicv features. */
9030 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9036 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9037 unsigned long count_field
,
9038 unsigned long addr_field
)
9043 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9044 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9050 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9051 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9052 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9053 pr_warn_ratelimited(
9054 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9055 addr_field
, maxphyaddr
, count
, addr
);
9061 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9062 struct vmcs12
*vmcs12
)
9064 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9065 vmcs12
->vm_exit_msr_store_count
== 0 &&
9066 vmcs12
->vm_entry_msr_load_count
== 0)
9067 return 0; /* Fast path */
9068 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9069 VM_EXIT_MSR_LOAD_ADDR
) ||
9070 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9071 VM_EXIT_MSR_STORE_ADDR
) ||
9072 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9073 VM_ENTRY_MSR_LOAD_ADDR
))
9078 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9079 struct vmx_msr_entry
*e
)
9081 /* x2APIC MSR accesses are not allowed */
9082 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9084 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9085 e
->index
== MSR_IA32_UCODE_REV
)
9087 if (e
->reserved
!= 0)
9092 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9093 struct vmx_msr_entry
*e
)
9095 if (e
->index
== MSR_FS_BASE
||
9096 e
->index
== MSR_GS_BASE
||
9097 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9098 nested_vmx_msr_check_common(vcpu
, e
))
9103 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9104 struct vmx_msr_entry
*e
)
9106 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9107 nested_vmx_msr_check_common(vcpu
, e
))
9113 * Load guest's/host's msr at nested entry/exit.
9114 * return 0 for success, entry index for failure.
9116 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9119 struct vmx_msr_entry e
;
9120 struct msr_data msr
;
9122 msr
.host_initiated
= false;
9123 for (i
= 0; i
< count
; i
++) {
9124 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9126 pr_warn_ratelimited(
9127 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9128 __func__
, i
, gpa
+ i
* sizeof(e
));
9131 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9132 pr_warn_ratelimited(
9133 "%s check failed (%u, 0x%x, 0x%x)\n",
9134 __func__
, i
, e
.index
, e
.reserved
);
9137 msr
.index
= e
.index
;
9139 if (kvm_set_msr(vcpu
, &msr
)) {
9140 pr_warn_ratelimited(
9141 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9142 __func__
, i
, e
.index
, e
.value
);
9151 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9154 struct vmx_msr_entry e
;
9156 for (i
= 0; i
< count
; i
++) {
9157 struct msr_data msr_info
;
9158 if (kvm_vcpu_read_guest(vcpu
,
9159 gpa
+ i
* sizeof(e
),
9160 &e
, 2 * sizeof(u32
))) {
9161 pr_warn_ratelimited(
9162 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9163 __func__
, i
, gpa
+ i
* sizeof(e
));
9166 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9167 pr_warn_ratelimited(
9168 "%s check failed (%u, 0x%x, 0x%x)\n",
9169 __func__
, i
, e
.index
, e
.reserved
);
9172 msr_info
.host_initiated
= false;
9173 msr_info
.index
= e
.index
;
9174 if (kvm_get_msr(vcpu
, &msr_info
)) {
9175 pr_warn_ratelimited(
9176 "%s cannot read MSR (%u, 0x%x)\n",
9177 __func__
, i
, e
.index
);
9180 if (kvm_vcpu_write_guest(vcpu
,
9181 gpa
+ i
* sizeof(e
) +
9182 offsetof(struct vmx_msr_entry
, value
),
9183 &msr_info
.data
, sizeof(msr_info
.data
))) {
9184 pr_warn_ratelimited(
9185 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9186 __func__
, i
, e
.index
, msr_info
.data
);
9194 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9195 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9196 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9197 * guest in a way that will both be appropriate to L1's requests, and our
9198 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9199 * function also has additional necessary side-effects, like setting various
9200 * vcpu->arch fields.
9202 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9204 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9207 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9208 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9209 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9210 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9211 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9212 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9213 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9214 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9215 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9216 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9217 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9218 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9219 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9220 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9221 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9222 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9223 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9224 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9225 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9226 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9227 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9228 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9229 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9230 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9231 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9232 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9233 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9234 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9235 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9236 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9237 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9238 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9239 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9240 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9241 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9242 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9244 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9245 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9246 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9248 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9249 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9251 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9252 vmcs12
->vm_entry_intr_info_field
);
9253 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9254 vmcs12
->vm_entry_exception_error_code
);
9255 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9256 vmcs12
->vm_entry_instruction_len
);
9257 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9258 vmcs12
->guest_interruptibility_info
);
9259 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9260 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9261 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9262 vmcs12
->guest_pending_dbg_exceptions
);
9263 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9264 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9266 if (nested_cpu_has_xsaves(vmcs12
))
9267 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9268 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9270 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9271 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9272 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9274 if (nested_cpu_has_posted_intr(vmcs12
)) {
9276 * Note that we use L0's vector here and in
9277 * vmx_deliver_nested_posted_interrupt.
9279 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9280 vmx
->nested
.pi_pending
= false;
9281 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9282 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9283 page_to_phys(vmx
->nested
.pi_desc_page
) +
9284 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9287 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9289 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9291 vmx
->nested
.preemption_timer_expired
= false;
9292 if (nested_cpu_has_preemption_timer(vmcs12
))
9293 vmx_start_preemption_timer(vcpu
);
9296 * Whether page-faults are trapped is determined by a combination of
9297 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9298 * If enable_ept, L0 doesn't care about page faults and we should
9299 * set all of these to L1's desires. However, if !enable_ept, L0 does
9300 * care about (at least some) page faults, and because it is not easy
9301 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9302 * to exit on each and every L2 page fault. This is done by setting
9303 * MASK=MATCH=0 and (see below) EB.PF=1.
9304 * Note that below we don't need special code to set EB.PF beyond the
9305 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9306 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9307 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9309 * A problem with this approach (when !enable_ept) is that L1 may be
9310 * injected with more page faults than it asked for. This could have
9311 * caused problems, but in practice existing hypervisors don't care.
9312 * To fix this, we will need to emulate the PFEC checking (on the L1
9313 * page tables), using walk_addr(), when injecting PFs to L1.
9315 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9316 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9317 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9318 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9320 if (cpu_has_secondary_exec_ctrls()) {
9321 exec_control
= vmx_secondary_exec_control(vmx
);
9322 if (!vmx
->rdtscp_enabled
)
9323 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
9324 /* Take the following fields only from vmcs12 */
9325 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9326 SECONDARY_EXEC_RDTSCP
|
9327 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9328 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
9329 if (nested_cpu_has(vmcs12
,
9330 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9331 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9333 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9335 * If translation failed, no matter: This feature asks
9336 * to exit when accessing the given address, and if it
9337 * can never be accessed, this feature won't do
9340 if (!vmx
->nested
.apic_access_page
)
9342 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9344 vmcs_write64(APIC_ACCESS_ADDR
,
9345 page_to_phys(vmx
->nested
.apic_access_page
));
9346 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9347 (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))) {
9349 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9350 kvm_vcpu_reload_apic_access_page(vcpu
);
9353 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9354 vmcs_write64(EOI_EXIT_BITMAP0
,
9355 vmcs12
->eoi_exit_bitmap0
);
9356 vmcs_write64(EOI_EXIT_BITMAP1
,
9357 vmcs12
->eoi_exit_bitmap1
);
9358 vmcs_write64(EOI_EXIT_BITMAP2
,
9359 vmcs12
->eoi_exit_bitmap2
);
9360 vmcs_write64(EOI_EXIT_BITMAP3
,
9361 vmcs12
->eoi_exit_bitmap3
);
9362 vmcs_write16(GUEST_INTR_STATUS
,
9363 vmcs12
->guest_intr_status
);
9366 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9371 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9372 * Some constant fields are set here by vmx_set_constant_host_state().
9373 * Other fields are different per CPU, and will be set later when
9374 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9376 vmx_set_constant_host_state(vmx
);
9379 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9380 * entry, but only if the current (host) sp changed from the value
9381 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9382 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9383 * here we just force the write to happen on entry.
9387 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9388 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9389 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9390 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9391 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9393 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9394 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9395 page_to_phys(vmx
->nested
.virtual_apic_page
));
9396 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9399 if (cpu_has_vmx_msr_bitmap() &&
9400 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9401 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9402 /* MSR_BITMAP will be set by following vmx_set_efer. */
9404 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9407 * Merging of IO bitmap not currently supported.
9408 * Rather, exit every time.
9410 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9411 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9413 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9415 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9416 * bitwise-or of what L1 wants to trap for L2, and what we want to
9417 * trap. Note that CR0.TS also needs updating - we do this later.
9419 update_exception_bitmap(vcpu
);
9420 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9421 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9423 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9424 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9425 * bits are further modified by vmx_set_efer() below.
9427 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9429 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9430 * emulated by vmx_set_efer(), below.
9432 vm_entry_controls_init(vmx
,
9433 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9434 ~VM_ENTRY_IA32E_MODE
) |
9435 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9437 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9438 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9439 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9440 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9441 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9444 set_cr4_guest_host_mask(vmx
);
9446 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9447 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9449 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9450 vmcs_write64(TSC_OFFSET
,
9451 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9453 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9457 * Trivially support vpid by letting L2s share their parent
9458 * L1's vpid. TODO: move to a more elaborate solution, giving
9459 * each L2 its own vpid and exposing the vpid feature to L1.
9461 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9462 vmx_flush_tlb(vcpu
);
9465 if (nested_cpu_has_ept(vmcs12
)) {
9466 kvm_mmu_unload(vcpu
);
9467 nested_ept_init_mmu_context(vcpu
);
9470 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9471 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9472 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9473 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9475 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9476 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9477 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9480 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9481 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9482 * The CR0_READ_SHADOW is what L2 should have expected to read given
9483 * the specifications by L1; It's not enough to take
9484 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9485 * have more bits than L1 expected.
9487 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9488 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9490 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9491 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9493 /* shadow page tables on either EPT or shadow page tables */
9494 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9495 kvm_mmu_reset_context(vcpu
);
9498 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9501 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9504 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9505 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9506 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9507 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9510 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9511 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9515 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9516 * for running an L2 nested guest.
9518 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9520 struct vmcs12
*vmcs12
;
9521 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9523 struct loaded_vmcs
*vmcs02
;
9527 if (!nested_vmx_check_permission(vcpu
) ||
9528 !nested_vmx_check_vmcs12(vcpu
))
9531 skip_emulated_instruction(vcpu
);
9532 vmcs12
= get_vmcs12(vcpu
);
9534 if (enable_shadow_vmcs
)
9535 copy_shadow_to_vmcs12(vmx
);
9538 * The nested entry process starts with enforcing various prerequisites
9539 * on vmcs12 as required by the Intel SDM, and act appropriately when
9540 * they fail: As the SDM explains, some conditions should cause the
9541 * instruction to fail, while others will cause the instruction to seem
9542 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9543 * To speed up the normal (success) code path, we should avoid checking
9544 * for misconfigurations which will anyway be caught by the processor
9545 * when using the merged vmcs02.
9547 if (vmcs12
->launch_state
== launch
) {
9548 nested_vmx_failValid(vcpu
,
9549 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9550 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9554 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9555 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9556 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9560 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9561 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9565 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9566 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9570 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9571 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9575 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9576 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9580 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9581 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9582 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9583 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9584 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9585 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9586 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9587 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9588 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9589 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9590 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9591 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9592 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9593 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9594 vmx
->nested
.nested_vmx_entry_ctls_high
))
9596 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9600 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9601 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9602 nested_vmx_failValid(vcpu
,
9603 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9607 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9608 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9609 nested_vmx_entry_failure(vcpu
, vmcs12
,
9610 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9613 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9614 nested_vmx_entry_failure(vcpu
, vmcs12
,
9615 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9620 * If the load IA32_EFER VM-entry control is 1, the following checks
9621 * are performed on the field for the IA32_EFER MSR:
9622 * - Bits reserved in the IA32_EFER MSR must be 0.
9623 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9624 * the IA-32e mode guest VM-exit control. It must also be identical
9625 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9628 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9629 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9630 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9631 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9632 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9633 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9634 nested_vmx_entry_failure(vcpu
, vmcs12
,
9635 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9641 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9642 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9643 * the values of the LMA and LME bits in the field must each be that of
9644 * the host address-space size VM-exit control.
9646 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9647 ia32e
= (vmcs12
->vm_exit_controls
&
9648 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9649 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9650 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9651 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9652 nested_vmx_entry_failure(vcpu
, vmcs12
,
9653 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9659 * We're finally done with prerequisite checking, and can start with
9663 vmcs02
= nested_get_current_vmcs02(vmx
);
9667 enter_guest_mode(vcpu
);
9669 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9671 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9672 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9675 vmx
->loaded_vmcs
= vmcs02
;
9677 vmx_vcpu_load(vcpu
, cpu
);
9681 vmx_segment_cache_clear(vmx
);
9683 prepare_vmcs02(vcpu
, vmcs12
);
9685 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9686 vmcs12
->vm_entry_msr_load_addr
,
9687 vmcs12
->vm_entry_msr_load_count
);
9688 if (msr_entry_idx
) {
9689 leave_guest_mode(vcpu
);
9690 vmx_load_vmcs01(vcpu
);
9691 nested_vmx_entry_failure(vcpu
, vmcs12
,
9692 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9696 vmcs12
->launch_state
= 1;
9698 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9699 return kvm_vcpu_halt(vcpu
);
9701 vmx
->nested
.nested_run_pending
= 1;
9704 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9705 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9706 * returned as far as L1 is concerned. It will only return (and set
9707 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9713 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9714 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9715 * This function returns the new value we should put in vmcs12.guest_cr0.
9716 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9717 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9718 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9719 * didn't trap the bit, because if L1 did, so would L0).
9720 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9721 * been modified by L2, and L1 knows it. So just leave the old value of
9722 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9723 * isn't relevant, because if L0 traps this bit it can set it to anything.
9724 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9725 * changed these bits, and therefore they need to be updated, but L0
9726 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9727 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9729 static inline unsigned long
9730 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9733 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9734 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9735 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9736 vcpu
->arch
.cr0_guest_owned_bits
));
9739 static inline unsigned long
9740 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9743 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9744 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9745 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9746 vcpu
->arch
.cr4_guest_owned_bits
));
9749 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9750 struct vmcs12
*vmcs12
)
9755 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9756 nr
= vcpu
->arch
.exception
.nr
;
9757 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9759 if (kvm_exception_is_soft(nr
)) {
9760 vmcs12
->vm_exit_instruction_len
=
9761 vcpu
->arch
.event_exit_inst_len
;
9762 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
9764 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
9766 if (vcpu
->arch
.exception
.has_error_code
) {
9767 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
9768 vmcs12
->idt_vectoring_error_code
=
9769 vcpu
->arch
.exception
.error_code
;
9772 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9773 } else if (vcpu
->arch
.nmi_injected
) {
9774 vmcs12
->idt_vectoring_info_field
=
9775 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
9776 } else if (vcpu
->arch
.interrupt
.pending
) {
9777 nr
= vcpu
->arch
.interrupt
.nr
;
9778 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9780 if (vcpu
->arch
.interrupt
.soft
) {
9781 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
9782 vmcs12
->vm_entry_instruction_len
=
9783 vcpu
->arch
.event_exit_inst_len
;
9785 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
9787 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9791 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
9793 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9795 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
9796 vmx
->nested
.preemption_timer_expired
) {
9797 if (vmx
->nested
.nested_run_pending
)
9799 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
9803 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
9804 if (vmx
->nested
.nested_run_pending
||
9805 vcpu
->arch
.interrupt
.pending
)
9807 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9808 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
9809 INTR_INFO_VALID_MASK
, 0);
9811 * The NMI-triggered VM exit counts as injection:
9812 * clear this one and block further NMIs.
9814 vcpu
->arch
.nmi_pending
= 0;
9815 vmx_set_nmi_mask(vcpu
, true);
9819 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
9820 nested_exit_on_intr(vcpu
)) {
9821 if (vmx
->nested
.nested_run_pending
)
9823 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
9827 return vmx_complete_nested_posted_interrupt(vcpu
);
9830 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
9833 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
9836 if (ktime_to_ns(remaining
) <= 0)
9839 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
9840 do_div(value
, 1000000);
9841 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9845 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9846 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9847 * and this function updates it to reflect the changes to the guest state while
9848 * L2 was running (and perhaps made some exits which were handled directly by L0
9849 * without going back to L1), and to reflect the exit reason.
9850 * Note that we do not have to copy here all VMCS fields, just those that
9851 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9852 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9853 * which already writes to vmcs12 directly.
9855 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9856 u32 exit_reason
, u32 exit_intr_info
,
9857 unsigned long exit_qualification
)
9859 /* update guest state fields: */
9860 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
9861 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
9863 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
9864 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
9865 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
9867 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
9868 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
9869 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
9870 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
9871 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
9872 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
9873 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
9874 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
9875 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
9876 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
9877 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
9878 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
9879 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
9880 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
9881 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
9882 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
9883 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
9884 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
9885 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
9886 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
9887 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
9888 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
9889 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
9890 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
9891 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
9892 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
9893 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
9894 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
9895 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
9896 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
9897 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
9898 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
9899 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
9900 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
9901 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
9902 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
9904 vmcs12
->guest_interruptibility_info
=
9905 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
9906 vmcs12
->guest_pending_dbg_exceptions
=
9907 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
9908 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
9909 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
9911 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
9913 if (nested_cpu_has_preemption_timer(vmcs12
)) {
9914 if (vmcs12
->vm_exit_controls
&
9915 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
9916 vmcs12
->vmx_preemption_timer_value
=
9917 vmx_get_preemption_timer_value(vcpu
);
9918 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
9922 * In some cases (usually, nested EPT), L2 is allowed to change its
9923 * own CR3 without exiting. If it has changed it, we must keep it.
9924 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9925 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9927 * Additionally, restore L2's PDPTR to vmcs12.
9930 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
9931 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
9932 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
9933 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
9934 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
9937 if (nested_cpu_has_vid(vmcs12
))
9938 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
9940 vmcs12
->vm_entry_controls
=
9941 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
9942 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
9944 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
9945 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
9946 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9949 /* TODO: These cannot have changed unless we have MSR bitmaps and
9950 * the relevant bit asks not to trap the change */
9951 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
9952 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
9953 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
9954 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
9955 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
9956 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
9957 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
9958 if (vmx_mpx_supported())
9959 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
9960 if (nested_cpu_has_xsaves(vmcs12
))
9961 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
9963 /* update exit information fields: */
9965 vmcs12
->vm_exit_reason
= exit_reason
;
9966 vmcs12
->exit_qualification
= exit_qualification
;
9968 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
9969 if ((vmcs12
->vm_exit_intr_info
&
9970 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
9971 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
9972 vmcs12
->vm_exit_intr_error_code
=
9973 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
9974 vmcs12
->idt_vectoring_info_field
= 0;
9975 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
9976 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9978 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
9979 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9980 * instead of reading the real value. */
9981 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
9984 * Transfer the event that L0 or L1 may wanted to inject into
9985 * L2 to IDT_VECTORING_INFO_FIELD.
9987 vmcs12_save_pending_event(vcpu
, vmcs12
);
9991 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9992 * preserved above and would only end up incorrectly in L1.
9994 vcpu
->arch
.nmi_injected
= false;
9995 kvm_clear_exception_queue(vcpu
);
9996 kvm_clear_interrupt_queue(vcpu
);
10000 * A part of what we need to when the nested L2 guest exits and we want to
10001 * run its L1 parent, is to reset L1's guest state to the host state specified
10003 * This function is to be called not only on normal nested exit, but also on
10004 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10005 * Failures During or After Loading Guest State").
10006 * This function should be called when the active VMCS is L1's (vmcs01).
10008 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10009 struct vmcs12
*vmcs12
)
10011 struct kvm_segment seg
;
10013 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10014 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10015 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10016 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10018 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10019 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10021 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10022 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10023 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10025 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10026 * actually changed, because it depends on the current state of
10027 * fpu_active (which may have changed).
10028 * Note that vmx_set_cr0 refers to efer set above.
10030 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10032 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10033 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10034 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10036 update_exception_bitmap(vcpu
);
10037 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10038 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10041 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10042 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10044 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10045 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10047 nested_ept_uninit_mmu_context(vcpu
);
10049 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10050 kvm_mmu_reset_context(vcpu
);
10053 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10057 * Trivially support vpid by letting L2s share their parent
10058 * L1's vpid. TODO: move to a more elaborate solution, giving
10059 * each L2 its own vpid and exposing the vpid feature to L1.
10061 vmx_flush_tlb(vcpu
);
10065 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10066 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10067 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10068 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10069 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10071 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10072 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10073 vmcs_write64(GUEST_BNDCFGS
, 0);
10075 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10076 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10077 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10079 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10080 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10081 vmcs12
->host_ia32_perf_global_ctrl
);
10083 /* Set L1 segment info according to Intel SDM
10084 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10085 seg
= (struct kvm_segment
) {
10087 .limit
= 0xFFFFFFFF,
10088 .selector
= vmcs12
->host_cs_selector
,
10094 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10098 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10099 seg
= (struct kvm_segment
) {
10101 .limit
= 0xFFFFFFFF,
10108 seg
.selector
= vmcs12
->host_ds_selector
;
10109 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10110 seg
.selector
= vmcs12
->host_es_selector
;
10111 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10112 seg
.selector
= vmcs12
->host_ss_selector
;
10113 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10114 seg
.selector
= vmcs12
->host_fs_selector
;
10115 seg
.base
= vmcs12
->host_fs_base
;
10116 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10117 seg
.selector
= vmcs12
->host_gs_selector
;
10118 seg
.base
= vmcs12
->host_gs_base
;
10119 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10120 seg
= (struct kvm_segment
) {
10121 .base
= vmcs12
->host_tr_base
,
10123 .selector
= vmcs12
->host_tr_selector
,
10127 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10129 kvm_set_dr(vcpu
, 7, 0x400);
10130 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10132 if (cpu_has_vmx_msr_bitmap())
10133 vmx_set_msr_bitmap(vcpu
);
10135 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10136 vmcs12
->vm_exit_msr_load_count
))
10137 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10141 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10142 * and modify vmcs12 to make it see what it would expect to see there if
10143 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10145 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10146 u32 exit_intr_info
,
10147 unsigned long exit_qualification
)
10149 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10150 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10152 /* trying to cancel vmlaunch/vmresume is a bug */
10153 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10155 leave_guest_mode(vcpu
);
10156 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10157 exit_qualification
);
10159 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10160 vmcs12
->vm_exit_msr_store_count
))
10161 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10163 vmx_load_vmcs01(vcpu
);
10165 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10166 && nested_exit_intr_ack_set(vcpu
)) {
10167 int irq
= kvm_cpu_get_interrupt(vcpu
);
10169 vmcs12
->vm_exit_intr_info
= irq
|
10170 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10173 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10174 vmcs12
->exit_qualification
,
10175 vmcs12
->idt_vectoring_info_field
,
10176 vmcs12
->vm_exit_intr_info
,
10177 vmcs12
->vm_exit_intr_error_code
,
10180 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10181 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10182 vmx_segment_cache_clear(vmx
);
10184 /* if no vmcs02 cache requested, remove the one we used */
10185 if (VMCS02_POOL_SIZE
== 0)
10186 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10188 load_vmcs12_host_state(vcpu
, vmcs12
);
10190 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10191 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10193 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10196 /* Unpin physical memory we referred to in vmcs02 */
10197 if (vmx
->nested
.apic_access_page
) {
10198 nested_release_page(vmx
->nested
.apic_access_page
);
10199 vmx
->nested
.apic_access_page
= NULL
;
10201 if (vmx
->nested
.virtual_apic_page
) {
10202 nested_release_page(vmx
->nested
.virtual_apic_page
);
10203 vmx
->nested
.virtual_apic_page
= NULL
;
10205 if (vmx
->nested
.pi_desc_page
) {
10206 kunmap(vmx
->nested
.pi_desc_page
);
10207 nested_release_page(vmx
->nested
.pi_desc_page
);
10208 vmx
->nested
.pi_desc_page
= NULL
;
10209 vmx
->nested
.pi_desc
= NULL
;
10213 * We are now running in L2, mmu_notifier will force to reload the
10214 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10216 kvm_vcpu_reload_apic_access_page(vcpu
);
10219 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10220 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10221 * success or failure flag accordingly.
10223 if (unlikely(vmx
->fail
)) {
10225 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10227 nested_vmx_succeed(vcpu
);
10228 if (enable_shadow_vmcs
)
10229 vmx
->nested
.sync_shadow_vmcs
= true;
10231 /* in case we halted in L2 */
10232 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10236 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10238 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10240 if (is_guest_mode(vcpu
))
10241 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10242 free_nested(to_vmx(vcpu
));
10246 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10247 * 23.7 "VM-entry failures during or after loading guest state" (this also
10248 * lists the acceptable exit-reason and exit-qualification parameters).
10249 * It should only be called before L2 actually succeeded to run, and when
10250 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10252 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10253 struct vmcs12
*vmcs12
,
10254 u32 reason
, unsigned long qualification
)
10256 load_vmcs12_host_state(vcpu
, vmcs12
);
10257 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10258 vmcs12
->exit_qualification
= qualification
;
10259 nested_vmx_succeed(vcpu
);
10260 if (enable_shadow_vmcs
)
10261 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10264 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10265 struct x86_instruction_info
*info
,
10266 enum x86_intercept_stage stage
)
10268 return X86EMUL_CONTINUE
;
10271 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10274 shrink_ple_window(vcpu
);
10277 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10278 struct kvm_memory_slot
*slot
)
10280 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10281 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10284 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10285 struct kvm_memory_slot
*slot
)
10287 kvm_mmu_slot_set_dirty(kvm
, slot
);
10290 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10292 kvm_flush_pml_buffers(kvm
);
10295 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10296 struct kvm_memory_slot
*memslot
,
10297 gfn_t offset
, unsigned long mask
)
10299 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10302 static struct kvm_x86_ops vmx_x86_ops
= {
10303 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10304 .disabled_by_bios
= vmx_disabled_by_bios
,
10305 .hardware_setup
= hardware_setup
,
10306 .hardware_unsetup
= hardware_unsetup
,
10307 .check_processor_compatibility
= vmx_check_processor_compat
,
10308 .hardware_enable
= hardware_enable
,
10309 .hardware_disable
= hardware_disable
,
10310 .cpu_has_accelerated_tpr
= report_flexpriority
,
10311 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10313 .vcpu_create
= vmx_create_vcpu
,
10314 .vcpu_free
= vmx_free_vcpu
,
10315 .vcpu_reset
= vmx_vcpu_reset
,
10317 .prepare_guest_switch
= vmx_save_host_state
,
10318 .vcpu_load
= vmx_vcpu_load
,
10319 .vcpu_put
= vmx_vcpu_put
,
10321 .update_db_bp_intercept
= update_exception_bitmap
,
10322 .get_msr
= vmx_get_msr
,
10323 .set_msr
= vmx_set_msr
,
10324 .get_segment_base
= vmx_get_segment_base
,
10325 .get_segment
= vmx_get_segment
,
10326 .set_segment
= vmx_set_segment
,
10327 .get_cpl
= vmx_get_cpl
,
10328 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10329 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10330 .decache_cr3
= vmx_decache_cr3
,
10331 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10332 .set_cr0
= vmx_set_cr0
,
10333 .set_cr3
= vmx_set_cr3
,
10334 .set_cr4
= vmx_set_cr4
,
10335 .set_efer
= vmx_set_efer
,
10336 .get_idt
= vmx_get_idt
,
10337 .set_idt
= vmx_set_idt
,
10338 .get_gdt
= vmx_get_gdt
,
10339 .set_gdt
= vmx_set_gdt
,
10340 .get_dr6
= vmx_get_dr6
,
10341 .set_dr6
= vmx_set_dr6
,
10342 .set_dr7
= vmx_set_dr7
,
10343 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10344 .cache_reg
= vmx_cache_reg
,
10345 .get_rflags
= vmx_get_rflags
,
10346 .set_rflags
= vmx_set_rflags
,
10347 .fpu_activate
= vmx_fpu_activate
,
10348 .fpu_deactivate
= vmx_fpu_deactivate
,
10350 .tlb_flush
= vmx_flush_tlb
,
10352 .run
= vmx_vcpu_run
,
10353 .handle_exit
= vmx_handle_exit
,
10354 .skip_emulated_instruction
= skip_emulated_instruction
,
10355 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10356 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10357 .patch_hypercall
= vmx_patch_hypercall
,
10358 .set_irq
= vmx_inject_irq
,
10359 .set_nmi
= vmx_inject_nmi
,
10360 .queue_exception
= vmx_queue_exception
,
10361 .cancel_injection
= vmx_cancel_injection
,
10362 .interrupt_allowed
= vmx_interrupt_allowed
,
10363 .nmi_allowed
= vmx_nmi_allowed
,
10364 .get_nmi_mask
= vmx_get_nmi_mask
,
10365 .set_nmi_mask
= vmx_set_nmi_mask
,
10366 .enable_nmi_window
= enable_nmi_window
,
10367 .enable_irq_window
= enable_irq_window
,
10368 .update_cr8_intercept
= update_cr8_intercept
,
10369 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10370 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10371 .cpu_uses_apicv
= vmx_cpu_uses_apicv
,
10372 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10373 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10374 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10375 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10376 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10378 .set_tss_addr
= vmx_set_tss_addr
,
10379 .get_tdp_level
= get_ept_level
,
10380 .get_mt_mask
= vmx_get_mt_mask
,
10382 .get_exit_info
= vmx_get_exit_info
,
10384 .get_lpage_level
= vmx_get_lpage_level
,
10386 .cpuid_update
= vmx_cpuid_update
,
10388 .rdtscp_supported
= vmx_rdtscp_supported
,
10389 .invpcid_supported
= vmx_invpcid_supported
,
10391 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10393 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10395 .set_tsc_khz
= vmx_set_tsc_khz
,
10396 .read_tsc_offset
= vmx_read_tsc_offset
,
10397 .write_tsc_offset
= vmx_write_tsc_offset
,
10398 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10399 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10400 .read_l1_tsc
= vmx_read_l1_tsc
,
10402 .set_tdp_cr3
= vmx_set_cr3
,
10404 .check_intercept
= vmx_check_intercept
,
10405 .handle_external_intr
= vmx_handle_external_intr
,
10406 .mpx_supported
= vmx_mpx_supported
,
10407 .xsaves_supported
= vmx_xsaves_supported
,
10409 .check_nested_events
= vmx_check_nested_events
,
10411 .sched_in
= vmx_sched_in
,
10413 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10414 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10415 .flush_log_dirty
= vmx_flush_log_dirty
,
10416 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10418 .pmu_ops
= &intel_pmu_ops
,
10421 static int __init
vmx_init(void)
10423 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10424 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10428 #ifdef CONFIG_KEXEC_CORE
10429 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10430 crash_vmclear_local_loaded_vmcss
);
10436 static void __exit
vmx_exit(void)
10438 #ifdef CONFIG_KEXEC_CORE
10439 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10446 module_init(vmx_init
)
10447 module_exit(vmx_exit
)