]> git.proxmox.com Git - pve-kernel-2.6.32.git/blob - atl1c-Add-support-for-Atheros-AR8152-and-AR8152.patch
projects / pve-kernel-2.6.32.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
update igb to 3.4.8, include ixgbe_fix_mac_flush.patch
[pve-kernel-2.6.32.git] / atl1c-Add-support-for-Atheros-AR8152-and-AR8152.patch
1 From 496c185c9495629ef1c65387cb2594578393cfe0 Mon Sep 17 00:00:00 2001
2 From: "Luis R. Rodriguez" <lrodriguez@atheros.com>
3 Date: Tue, 16 Feb 2010 15:16:45 -0800
4 Subject: [PATCH] atl1c: Add support for Atheros AR8152 and AR8152
5
6 AR8151 is a Gigabit Ethernet device. AR8152 devices are
7 Fast Ethernet devices, there are two revisions, a 1.0
8 and a 2.0 revision.
9
10 This has been tested against these devices:
11
12 Driver Model-name vendor:device Type
13 atl1c AR8131 1969:1063 Gigabit Ethernet
14 atl1c AR8132 1969:1062 Fast Ethernet
15 atl1c AR8151(v1.0) 1969:1073 Gigabit Ethernet
16 atl1c AR8152(v1.1) 1969:2060 Fast Ethernet
17
18 This device has no hardware available yet so it goes untested,
19 but it should work:
20
21 atl1c AR8152(v2.0) 1969:2062 Fast Ethernet
22
23 Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
24 Signed-off-by: David S. Miller <davem@davemloft.net>
25 ---
26 drivers/net/atl1c/atl1c.h | 11 +++-
27 drivers/net/atl1c/atl1c_ethtool.c | 2 +-
28 drivers/net/atl1c/atl1c_hw.c | 83 +++++++++++++++++++++++----
29 drivers/net/atl1c/atl1c_hw.h | 5 ++
30 drivers/net/atl1c/atl1c_main.c | 115 +++++++++++++++++++++++++++++++++---
31 5 files changed, 191 insertions(+), 25 deletions(-)
32
33 diff --git a/drivers/net/atl1c/atl1c.h b/drivers/net/atl1c/atl1c.h
34 index efe5435..84ae905 100644
35 --- a/drivers/net/atl1c/atl1c.h
36 +++ b/drivers/net/atl1c/atl1c.h
37 @@ -313,6 +313,9 @@ enum atl1c_rss_type {
38 enum atl1c_nic_type {
39 athr_l1c = 0,
40 athr_l2c = 1,
41 + athr_l2c_b,
42 + athr_l2c_b2,
43 + athr_l1d,
44 };
45
46 enum atl1c_trans_queue {
47 @@ -426,8 +429,12 @@ struct atl1c_hw {
48 #define ATL1C_ASPM_L1_SUPPORT 0x0100
49 #define ATL1C_ASPM_CTRL_MON 0x0200
50 #define ATL1C_HIB_DISABLE 0x0400
51 -#define ATL1C_LINK_CAP_1000M 0x0800
52 -#define ATL1C_FPGA_VERSION 0x8000
53 +#define ATL1C_APS_MODE_ENABLE 0x0800
54 +#define ATL1C_LINK_EXT_SYNC 0x1000
55 +#define ATL1C_CLK_GATING_EN 0x2000
56 +#define ATL1C_FPGA_VERSION 0x8000
57 + u16 link_cap_flags;
58 +#define ATL1C_LINK_CAP_1000M 0x0001
59 u16 cmb_tpd;
60 u16 cmb_rrd;
61 u16 cmb_rx_timer; /* 2us resolution */
62 diff --git a/drivers/net/atl1c/atl1c_ethtool.c b/drivers/net/atl1c/atl1c_ethtool.c
63 index 9b1e0ea..61a0f2f 100644
64 --- a/drivers/net/atl1c/atl1c_ethtool.c
65 +++ b/drivers/net/atl1c/atl1c_ethtool.c
66 @@ -37,7 +37,7 @@ static int atl1c_get_settings(struct net_device *netdev,
67 SUPPORTED_100baseT_Full |
68 SUPPORTED_Autoneg |
69 SUPPORTED_TP);
70 - if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M)
71 + if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M)
72 ecmd->supported |= SUPPORTED_1000baseT_Full;
73
74 ecmd->advertising = ADVERTISED_TP;
75 diff --git a/drivers/net/atl1c/atl1c_hw.c b/drivers/net/atl1c/atl1c_hw.c
76 index 3e69b94..f1389d6 100644
77 --- a/drivers/net/atl1c/atl1c_hw.c
78 +++ b/drivers/net/atl1c/atl1c_hw.c
79 @@ -70,17 +70,39 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
80 u32 otp_ctrl_data;
81 u32 twsi_ctrl_data;
82 u8 eth_addr[ETH_ALEN];
83 + u16 phy_data;
84 + bool raise_vol = false;
85
86 /* init */
87 addr[0] = addr[1] = 0;
88 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
89 if (atl1c_check_eeprom_exist(hw)) {
90 - /* Enable OTP CLK */
91 - if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
92 - otp_ctrl_data |= OTP_CTRL_CLK_EN;
93 - AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
94 - AT_WRITE_FLUSH(hw);
95 - msleep(1);
96 + if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b) {
97 + /* Enable OTP CLK */
98 + if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
99 + otp_ctrl_data |= OTP_CTRL_CLK_EN;
100 + AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
101 + AT_WRITE_FLUSH(hw);
102 + msleep(1);
103 + }
104 + }
105 +
106 + if (hw->nic_type == athr_l2c_b ||
107 + hw->nic_type == athr_l2c_b2 ||
108 + hw->nic_type == athr_l1d) {
109 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
110 + if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
111 + goto out;
112 + phy_data &= 0xFF7F;
113 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
114 +
115 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
116 + if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
117 + goto out;
118 + phy_data |= 0x8;
119 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
120 + udelay(20);
121 + raise_vol = true;
122 }
123
124 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
125 @@ -96,11 +118,31 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
126 return -1;
127 }
128 /* Disable OTP_CLK */
129 - if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
130 - otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
131 - AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
132 - AT_WRITE_FLUSH(hw);
133 - msleep(1);
134 + if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) {
135 + if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
136 + otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
137 + AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
138 + AT_WRITE_FLUSH(hw);
139 + msleep(1);
140 + }
141 + }
142 + if (raise_vol) {
143 + if (hw->nic_type == athr_l2c_b ||
144 + hw->nic_type == athr_l2c_b2 ||
145 + hw->nic_type == athr_l1d) {
146 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
147 + if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
148 + goto out;
149 + phy_data |= 0x80;
150 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
151 +
152 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
153 + if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
154 + goto out;
155 + phy_data &= 0xFFF7;
156 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
157 + udelay(20);
158 + }
159 }
160
161 /* maybe MAC-address is from BIOS */
162 @@ -114,6 +156,7 @@ static int atl1c_get_permanent_address(struct atl1c_hw *hw)
163 return 0;
164 }
165
166 +out:
167 return -1;
168 }
169
170 @@ -307,7 +350,7 @@ static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
171 mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
172 ADVERTISE_100HALF | ADVERTISE_100FULL;
173
174 - if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) {
175 + if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) {
176 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
177 mii_giga_ctrl_data |= ADVERTISE_1000HALF;
178 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
179 @@ -389,6 +432,7 @@ int atl1c_phy_reset(struct atl1c_hw *hw)
180 {
181 struct atl1c_adapter *adapter = hw->adapter;
182 struct pci_dev *pdev = adapter->pdev;
183 + u16 phy_data;
184 u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
185 u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
186 int err;
187 @@ -404,6 +448,21 @@ int atl1c_phy_reset(struct atl1c_hw *hw)
188 AT_WRITE_FLUSH(hw);
189 msleep(10);
190
191 + if (hw->nic_type == athr_l2c_b) {
192 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
193 + atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
194 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
195 + }
196 +
197 + if (hw->nic_type == athr_l2c_b ||
198 + hw->nic_type == athr_l2c_b2 ||
199 + hw->nic_type == athr_l1d) {
200 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
201 + atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
202 + atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
203 + msleep(20);
204 + }
205 +
206 /*Enable PHY LinkChange Interrupt */
207 err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
208 if (err) {
209 diff --git a/drivers/net/atl1c/atl1c_hw.h b/drivers/net/atl1c/atl1c_hw.h
210 index c2c738d..1eeb3ed 100644
211 --- a/drivers/net/atl1c/atl1c_hw.h
212 +++ b/drivers/net/atl1c/atl1c_hw.h
213 @@ -57,6 +57,7 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
214 #define REG_LINK_CTRL 0x68
215 #define LINK_CTRL_L0S_EN 0x01
216 #define LINK_CTRL_L1_EN 0x02
217 +#define LINK_CTRL_EXT_SYNC 0x80
218
219 #define REG_VPD_CAP 0x6C
220 #define VPD_CAP_ID_MASK 0xff
221 @@ -156,6 +157,8 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
222 #define PM_CTRL_PM_REQ_TIMER_SHIFT 20
223 #define PM_CTRL_LCKDET_TIMER_MASK 0x3F
224 #define PM_CTRL_LCKDET_TIMER_SHIFT 24
225 +#define PM_CTRL_EN_BUFS_RX_L0S 0x10000000
226 +#define PM_CTRL_SA_DLY_EN 0x20000000
227 #define PM_CTRL_MAC_ASPM_CHK 0x40000000
228 #define PM_CTRL_HOTRST 0x80000000
229
230 @@ -314,6 +317,8 @@ int atl1c_restart_autoneg(struct atl1c_hw *hw);
231 #define MAC_CTRL_BC_EN 0x4000000
232 #define MAC_CTRL_DBG 0x8000000
233 #define MAC_CTRL_SINGLE_PAUSE_EN 0x10000000
234 +#define MAC_CTRL_HASH_ALG_CRC32 0x20000000
235 +#define MAC_CTRL_SPEED_MODE_SW 0x40000000
236
237 /* MAC IPG/IFG Control Register */
238 #define REG_MAC_IPG_IFG 0x1484
239 diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c
240 index d98095d..3d4c0a5 100644
241 --- a/drivers/net/atl1c/atl1c_main.c
242 +++ b/drivers/net/atl1c/atl1c_main.c
243 @@ -21,11 +21,18 @@
244
245 #include "atl1c.h"
246
247 -#define ATL1C_DRV_VERSION "1.0.0.1-NAPI"
248 +#define ATL1C_DRV_VERSION "1.0.0.2-NAPI"
249 char atl1c_driver_name[] = "atl1c";
250 char atl1c_driver_version[] = ATL1C_DRV_VERSION;
251 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
252 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
253 +#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
254 +#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
255 +#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
256 +
257 +#define L2CB_V10 0xc0
258 +#define L2CB_V11 0xc1
259 +
260 /*
261 * atl1c_pci_tbl - PCI Device ID Table
262 *
263 @@ -38,6 +45,9 @@ char atl1c_driver_version[] = ATL1C_DRV_VERSION;
264 static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
265 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
266 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
267 + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
268 + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
269 + {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
270 /* required last entry */
271 { 0 }
272 };
273 @@ -593,11 +603,18 @@ static void atl1c_set_mac_type(struct atl1c_hw *hw)
274 case PCI_DEVICE_ID_ATTANSIC_L2C:
275 hw->nic_type = athr_l2c;
276 break;
277 -
278 case PCI_DEVICE_ID_ATTANSIC_L1C:
279 hw->nic_type = athr_l1c;
280 break;
281 -
282 + case PCI_DEVICE_ID_ATHEROS_L2C_B:
283 + hw->nic_type = athr_l2c_b;
284 + break;
285 + case PCI_DEVICE_ID_ATHEROS_L2C_B2:
286 + hw->nic_type = athr_l2c_b2;
287 + break;
288 + case PCI_DEVICE_ID_ATHEROS_L1D:
289 + hw->nic_type = athr_l1d;
290 + break;
291 default:
292 break;
293 }
294 @@ -620,10 +637,13 @@ static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
295 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
296 if (link_ctrl_data & LINK_CTRL_L1_EN)
297 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
298 + if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
299 + hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
300
301 - if (hw->nic_type == athr_l1c) {
302 + if (hw->nic_type == athr_l1c ||
303 + hw->nic_type == athr_l1d) {
304 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
305 - hw->ctrl_flags |= ATL1C_LINK_CAP_1000M;
306 + hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
307 }
308 return 0;
309 }
310 @@ -1234,21 +1254,92 @@ static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
311 static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
312 {
313 u32 pm_ctrl_data;
314 + u32 link_ctrl_data;
315
316 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
317 -
318 + AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
319 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
320 +
321 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
322 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
323 + pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
324 + PM_CTRL_LCKDET_TIMER_SHIFT);
325
326 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
327 + pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
328 + pm_ctrl_data |= PM_CTRL_RBER_EN;
329 + pm_ctrl_data |= PM_CTRL_SDES_EN;
330 +
331 + if (hw->nic_type == athr_l2c_b ||
332 + hw->nic_type == athr_l1d ||
333 + hw->nic_type == athr_l2c_b2) {
334 + link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
335 + if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
336 + if (hw->nic_type == athr_l2c_b &&
337 + hw->revision_id == L2CB_V10)
338 + link_ctrl_data |= LINK_CTRL_EXT_SYNC;
339 + }
340 +
341 + AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
342 +
343 + pm_ctrl_data |= PM_CTRL_PCIE_RECV;
344 + pm_ctrl_data |= AT_ASPM_L1_TIMER << PM_CTRL_PM_REQ_TIMER_SHIFT;
345 + pm_ctrl_data &= ~PM_CTRL_EN_BUFS_RX_L0S;
346 + pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
347 + pm_ctrl_data &= ~PM_CTRL_HOTRST;
348 + pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
349 + pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
350 + }
351
352 if (linkup) {
353 - pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
354 - pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
355 + pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
356 + pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
357 + if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
358 + pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
359 + if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
360 + pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
361 +
362 + if (hw->nic_type == athr_l2c_b ||
363 + hw->nic_type == athr_l1d ||
364 + hw->nic_type == athr_l2c_b2) {
365 + if (hw->nic_type == athr_l2c_b)
366 + if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
367 + pm_ctrl_data &= PM_CTRL_ASPM_L0S_EN;
368 + pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
369 + pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
370 + pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
371 + pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
372 + if (hw->adapter->link_speed == SPEED_100 ||
373 + hw->adapter->link_speed == SPEED_1000) {
374 + pm_ctrl_data &=
375 + ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
376 + PM_CTRL_L1_ENTRY_TIMER_SHIFT);
377 + if (hw->nic_type == athr_l1d)
378 + pm_ctrl_data |= 0xF <<
379 + PM_CTRL_L1_ENTRY_TIMER_SHIFT;
380 + else
381 + pm_ctrl_data |= 7 <<
382 + PM_CTRL_L1_ENTRY_TIMER_SHIFT;
383 + }
384 + } else {
385 + pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
386 + pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
387 + pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
388 + pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
389 + pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
390 + pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
391 + }
392 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
393 + if (hw->adapter->link_speed == SPEED_10)
394 + if (hw->nic_type == athr_l1d)
395 + atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0xB69D);
396 + else
397 + atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
398 + else if (hw->adapter->link_speed == SPEED_100)
399 + atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB2DD);
400 + else
401 + atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x96DD);
402
403 - pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
404 - pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
405 } else {
406 pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
407 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
408 @@ -1302,6 +1393,10 @@ static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
409 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
410
411 mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
412 + if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2) {
413 + mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
414 + mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
415 + }
416 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
417 }
418
419 --
420 1.7.6.5
421
Linux Kernel 2.6.32