ceph/src/boost/boost/atomic/detail/fence_arch_ops_gcc_arm.hpp

   1 /*
   2  * Distributed under the Boost Software License, Version 1.0.
   3  * (See accompanying file LICENSE_1_0.txt or copy at
   4  * http://www.boost.org/LICENSE_1_0.txt)
   5  *
   6  * Copyright (c) 2020 Andrey Semashev
   7  */
   8 /*!
   9  * \file   atomic/detail/fence_arch_ops_gcc_arm.hpp
  10  *
  11  * This header contains implementation of the \c fence_arch_operations struct.
  12  */
  13
  14 #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
  15 #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
  16
  17 #include <boost/cstdint.hpp>
  18 #include <boost/memory_order.hpp>
  19 #include <boost/atomic/detail/config.hpp>
  20 #include <boost/atomic/detail/capabilities.hpp>
  21 #include <boost/atomic/detail/gcc_arm_asm_common.hpp>
  22 #include <boost/atomic/detail/header.hpp>
  23
  24 #ifdef BOOST_HAS_PRAGMA_ONCE
  25 #pragma once
  26 #endif
  27
  28 namespace boost {
  29 namespace atomics {
  30 namespace detail {
  31
  32 //! Fence operations for legacy ARM
  33 struct fence_arch_operations_gcc_arm
  34 {
  35     static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
  36     {
  37         if (order != memory_order_relaxed)
  38             hardware_full_fence();
  39     }
  40
  41     static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
  42     {
  43         if (order != memory_order_relaxed)
  44             __asm__ __volatile__ ("" ::: "memory");
  45     }
  46
  47     static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
  48     {
  49         // A memory barrier is effected using a "co-processor 15" instruction,
  50         // though a separate assembler mnemonic is available for it in v7.
  51
  52 #if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
  53         // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
  54         // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
  55         // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
  56         __asm__ __volatile__
  57         (
  58 #if defined(__thumb2__)
  59             ".short 0xF3BF, 0x8F5B\n\t" // dmb ish
  60 #else
  61             ".word 0xF57FF05B\n\t" // dmb ish
  62 #endif
  63             :
  64             :
  65             : "memory"
  66         );
  67 #else
  68         uint32_t tmp;
  69         __asm__ __volatile__
  70         (
  71             BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
  72             "mcr p15, 0, r0, c7, c10, 5\n\t"
  73             BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
  74             : "=&l" (tmp)
  75             :
  76             : "memory"
  77         );
  78 #endif
  79     }
  80 };
  81
  82 typedef fence_arch_operations_gcc_arm fence_arch_operations;
  83
  84 } // namespace detail
  85 } // namespace atomics
  86 } // namespace boost
  87
  88 #include <boost/atomic/detail/footer.hpp>
  89
  90 #endif // BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_