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update ceph source to reef 18.1.2
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1 /**********************************************************************
2 Copyright(c) 2021 Arm Corporation All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions
6 are met:
7 * Redistributions of source code must retain the above copyright
8 notice, this list of conditions and the following disclaimer.
9 * Redistributions in binary form must reproduce the above copyright
10 notice, this list of conditions and the following disclaimer in
11 the documentation and/or other materials provided with the
12 distribution.
13 * Neither the name of Arm Corporation nor the names of its
14 contributors may be used to endorse or promote products derived
15 from this software without specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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27 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 **********************************************************************/
29 /*
30 void aes_gcm_precomp(struct gcm_key_data *key_data);
31 */
32 declare_var_generic_reg key_data ,0
33 declare_var_generic_reg temp0 ,1
34 declare_var_generic_reg hashkey_base,0
35 declare_var_generic_reg hashkey_addr,1
36
37 declare_var_vector_reg Low ,0
38 declare_var_vector_reg Middle0 ,1
39 declare_var_vector_reg Middle1 ,2
40 declare_var_vector_reg High ,3
41 declare_var_vector_reg HashKeyIter ,4
42 declare_var_vector_reg HashKey ,5
43 declare_var_vector_reg HashKeyExt ,6
44 declare_var_vector_reg Poly ,7
45 declare_var_vector_reg Zero ,31
46
47 START_FUNC(precomp,KEY_LEN,_)
48 load_aes_keys key_data
49 mov temp0,0x87
50 eor vZero.16b,vZero.16b,vZero.16b
51 eor vHashKey.16b,vHashKey.16b,vHashKey.16b
52 dup vPoly.2d,temp0
53 aes_encrypt_block HashKey
54 add hashkey_addr,hashkey_base,(HASHKEY_TOTAL_NUM-1)*32
55 rbit vHashKey.16b,vHashKey.16b
56 ext vHashKeyExt.16b,vHashKey.16b,vHashKey.16b,8
57 mov vHashKeyIter.16b,vHashKey.16b
58 stp qHashKey,qHashKeyExt,[hashkey_addr],-32
59
60 1:
61 pmull vMiddle0.1q,vHashKeyIter.1d,vHashKeyExt.1d
62 pmull2 vMiddle1.1q,vHashKeyIter.2d,vHashKeyExt.2d
63 pmull vLow.1q ,vHashKeyIter.1d,vHashKey.1d
64 eor vMiddle0.16b,vMiddle0.16b,vMiddle1.16b
65 pmull2 vHigh.1q ,vHashKeyIter.2d,vHashKey.2d
66 ext vMiddle1.16b,vMiddle0.16b,vZero.16b,8 //high
67 ext vMiddle0.16b,vZero.16b,vMiddle0.16b,8 //low
68 eor vHigh.16b ,vHigh.16b,vMiddle1.16b
69 eor vLow.16b ,vLow.16b ,vMiddle0.16b
70 pmull2 vMiddle0.1q ,vHigh.2d ,vPoly.2d
71 ext vMiddle1.16b,vMiddle0.16b,vZero.16b,8 //high
72 ext vMiddle0.16b,vZero.16b,vMiddle0.16b,8 //low
73 eor vHigh.16b ,vHigh.16b,vMiddle1.16b
74 eor vLow.16b ,vLow.16b ,vMiddle0.16b
75 pmull vMiddle0.1q ,vHigh.1d ,vPoly.1d
76 eor vHashKeyIter.16b,vLow.16b,vMiddle0.16b
77 ext vLow.16b,vHashKeyIter.16b,vHashKeyIter.16b,8
78 stp qHashKeyIter,qLow,[hashkey_addr],-32
79 cmp hashkey_addr,hashkey_base
80 bcs 1b
81
82 ret
83 END_FUNC(precomp,KEY_LEN,_)