ceph/src/crypto/isa-l/isa-l_crypto/md5_mb/aarch64/md5_mb_asimd_x1.S

   1 /**********************************************************************
   2   Copyright(c) 2020 Arm Corporation All rights reserved.
   3
   4   Redistribution and use in source and binary forms, with or without
   5   modification, are permitted provided that the following conditions
   6   are met:
   7     * Redistributions of source code must retain the above copyright
   8       notice, this list of conditions and the following disclaimer.
   9     * Redistributions in binary form must reproduce the above copyright
  10       notice, this list of conditions and the following disclaimer in
  11       the documentation and/or other materials provided with the
  12       distribution.
  13     * Neither the name of Arm Corporation nor the names of its
  14       contributors may be used to endorse or promote products derived
  15       from this software without specific prior written permission.
  16
  17   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 **********************************************************************/
  29         .arch armv8-a
  30
  31 /*
  32 Macros
  33 */
  34
  35 .macro  declare_var_vector_reg name:req,reg:req
  36         q_\name .req    q\reg
  37         v_\name .req    v\reg
  38         s_\name .req    s\reg
  39 .endm
  40
  41
  42 .macro  round_0_15      d_a:req,d_b:req,d_c:req,d_d:req,kh:req,kl:req,w:req,r:req
  43         eor     tmp0,\d_c,\d_d
  44         mov     k,\kl
  45         and     tmp0,tmp0,\d_b
  46         movk    k,\kh,lsl 16
  47         eor     tmp0,tmp0,\d_d
  48         add     tmp1,k,\w
  49         add     tmp0,tmp1,tmp0
  50         add     tmp0,\d_a,tmp0
  51         ror     tmp0,tmp0,32 - \r
  52         add     \d_a,\d_b,tmp0
  53 .endm
  54
  55 .macro  round_16_31     d_a:req,d_b:req,d_c:req,d_d:req,kh:req,kl:req,w:req,r:req
  56         eor     tmp0,\d_b,\d_c
  57         mov     k,\kl
  58         and     tmp0,tmp0,\d_d
  59         movk    k,\kh,lsl 16
  60         eor     tmp0,tmp0,\d_c
  61         add     tmp1,k,\w
  62         add     tmp0,tmp1,tmp0
  63         add     tmp0,\d_a,tmp0
  64         ror     tmp0,tmp0,32 - \r
  65         add     \d_a,\d_b,tmp0
  66 .endm
  67
  68 .macro  round_32_47     d_a:req,d_b:req,d_c:req,d_d:req,kh:req,kl:req,w:req,r:req
  69         eor     tmp0,\d_b,\d_c
  70         mov     k,\kl
  71         eor     tmp0,tmp0,\d_d
  72         movk    k,\kh,lsl 16
  73         add     tmp1,k,\w
  74         add     tmp0,tmp1,tmp0
  75         add     tmp0,\d_a,tmp0
  76         ror     tmp0,tmp0,32 - \r
  77         add     \d_a,\d_b,tmp0
  78 .endm
  79
  80 .macro  round_48_63     d_a:req,d_b:req,d_c:req,d_d:req,kh:req,kl:req,w:req,r:req
  81         orn     tmp0,\d_b,\d_d
  82         mov     k,\kl
  83         eor     tmp0,tmp0,\d_c
  84         movk    k,\kh,lsl 16
  85         add     tmp1,k,\w
  86         add     tmp0,tmp1,tmp0
  87         add     tmp0,\d_a,tmp0
  88         ror     tmp0,tmp0,32 - \r
  89         add     \d_a,\d_b,tmp0
  90 .endm
  91 /*
  92         variables
  93 */
  94         job0            .req    x0
  95         digest_addr     .req    x0
  96         len             .req    w1
  97         end             .req    x1
  98
  99         buf_adr         .req    x2
 100         d_a             .req    w3
 101         d_b             .req    w4
 102         d_c             .req    w5
 103         d_d             .req    w6
 104         k               .req    w7
 105         m0              .req    w8
 106         m1              .req    w9
 107         m2              .req    w10
 108         m3              .req    w11
 109         m4              .req    w12
 110         m5              .req    w13
 111         m6              .req    w14
 112         m7              .req    w15
 113         m8              .req    w19
 114         m9              .req    w20
 115         m10             .req    w21
 116         m11             .req    w22
 117         m12             .req    w23
 118         m13             .req    w24
 119         m14             .req    w25
 120         m15             .req    w26
 121
 122         tmp0            .req    w27
 123         tmp1            .req    w28
 124
 125         d_a1            .req    w8
 126         d_b1            .req    w9
 127         d_c1            .req    w15
 128         d_d1            .req    w19
 129
 130 /*
 131         void md5_mb_asimd_x1(MD5_JOB * job0,int len)
 132 */
 133         .global md5_mb_asimd_x1
 134         .type md5_mb_asimd_x1, %function
 135 md5_mb_asimd_x1:
 136         cmp     len,0
 137         stp     x29, x30, [sp,-96]!
 138         ldr     buf_adr,[job0],64
 139         stp     x19, x20, [sp, 16]
 140         add     end,buf_adr,end,lsl 6
 141         stp     x21, x22, [sp, 32]
 142         ldp     d_a,d_b,[digest_addr]
 143         stp     x23, x24, [sp, 48]
 144         ldp     d_c,d_d,[digest_addr,8]
 145         stp     x25, x26, [sp, 64]
 146         stp     x27, x28, [sp, 80]
 147         ble     .exit
 148
 149 .loop_start:
 150         ldp             m0,m1,[buf_adr],8
 151         ldp             m2,m3,[buf_adr],8
 152         round_0_15      d_a,d_b,d_c,d_d,0xd76a,0xa478,m0,7
 153
 154         ldp             m4,m5,[buf_adr],8
 155         round_0_15      d_d,d_a,d_b,d_c,0xe8c7,0xb756,m1,12
 156         ldp             m6,m7,[buf_adr],8
 157         round_0_15      d_c,d_d,d_a,d_b,0x2420,0x70db,m2,17
 158         ldp             m8,m9,[buf_adr],8
 159         round_0_15      d_b,d_c,d_d,d_a,0xc1bd,0xceee,m3,22
 160         ldp             m10,m11,[buf_adr],8
 161         round_0_15      d_a,d_b,d_c,d_d,0xf57c,0xfaf,m4,7
 162         ldp             m12,m13,[buf_adr],8
 163         round_0_15      d_d,d_a,d_b,d_c,0x4787,0xc62a,m5,12
 164         ldp             m14,m15,[buf_adr],8
 165         round_0_15      d_c,d_d,d_a,d_b,0xa830,0x4613,m6,17
 166         round_0_15      d_b,d_c,d_d,d_a,0xfd46,0x9501,m7,22
 167         round_0_15      d_a,d_b,d_c,d_d,0x6980,0x98d8,m8,7
 168         round_0_15      d_d,d_a,d_b,d_c,0x8b44,0xf7af,m9,12
 169         round_0_15      d_c,d_d,d_a,d_b,0xffff,0x5bb1,m10,17
 170         round_0_15      d_b,d_c,d_d,d_a,0x895c,0xd7be,m11,22
 171         round_0_15      d_a,d_b,d_c,d_d,0x6b90,0x1122,m12,7
 172         round_0_15      d_d,d_a,d_b,d_c,0xfd98,0x7193,m13,12
 173         round_0_15      d_c,d_d,d_a,d_b,0xa679,0x438e,m14,17
 174         round_0_15      d_b,d_c,d_d,d_a,0x49b4,0x821,m15,22
 175
 176         round_16_31     d_a,d_b,d_c,d_d,0xf61e,0x2562,m1,5
 177         round_16_31     d_d,d_a,d_b,d_c,0xc040,0xb340,m6,9
 178         round_16_31     d_c,d_d,d_a,d_b,0x265e,0x5a51,m11,14
 179         round_16_31     d_b,d_c,d_d,d_a,0xe9b6,0xc7aa,m0,20
 180         round_16_31     d_a,d_b,d_c,d_d,0xd62f,0x105d,m5,5
 181         round_16_31     d_d,d_a,d_b,d_c,0x244,0x1453,m10,9
 182         round_16_31     d_c,d_d,d_a,d_b,0xd8a1,0xe681,m15,14
 183         round_16_31     d_b,d_c,d_d,d_a,0xe7d3,0xfbc8,m4,20
 184         round_16_31     d_a,d_b,d_c,d_d,0x21e1,0xcde6,m9,5
 185         round_16_31     d_d,d_a,d_b,d_c,0xc337,0x7d6,m14,9
 186         round_16_31     d_c,d_d,d_a,d_b,0xf4d5,0xd87,m3,14
 187         round_16_31     d_b,d_c,d_d,d_a,0x455a,0x14ed,m8,20
 188         round_16_31     d_a,d_b,d_c,d_d,0xa9e3,0xe905,m13,5
 189         round_16_31     d_d,d_a,d_b,d_c,0xfcef,0xa3f8,m2,9
 190         round_16_31     d_c,d_d,d_a,d_b,0x676f,0x2d9,m7,14
 191         round_16_31     d_b,d_c,d_d,d_a,0x8d2a,0x4c8a,m12,20
 192
 193         round_32_47     d_a,d_b,d_c,d_d,0xfffa,0x3942,m5,4
 194         round_32_47     d_d,d_a,d_b,d_c,0x8771,0xf681,m8,11
 195         round_32_47     d_c,d_d,d_a,d_b,0x6d9d,0x6122,m11,16
 196         round_32_47     d_b,d_c,d_d,d_a,0xfde5,0x380c,m14,23
 197         round_32_47     d_a,d_b,d_c,d_d,0xa4be,0xea44,m1,4
 198         round_32_47     d_d,d_a,d_b,d_c,0x4bde,0xcfa9,m4,11
 199         round_32_47     d_c,d_d,d_a,d_b,0xf6bb,0x4b60,m7,16
 200         round_32_47     d_b,d_c,d_d,d_a,0xbebf,0xbc70,m10,23
 201         round_32_47     d_a,d_b,d_c,d_d,0x289b,0x7ec6,m13,4
 202         round_32_47     d_d,d_a,d_b,d_c,0xeaa1,0x27fa,m0,11
 203         round_32_47     d_c,d_d,d_a,d_b,0xd4ef,0x3085,m3,16
 204         round_32_47     d_b,d_c,d_d,d_a,0x488,0x1d05,m6,23
 205         round_32_47     d_a,d_b,d_c,d_d,0xd9d4,0xd039,m9,4
 206         round_32_47     d_d,d_a,d_b,d_c,0xe6db,0x99e5,m12,11
 207         round_32_47     d_c,d_d,d_a,d_b,0x1fa2,0x7cf8,m15,16
 208         round_32_47     d_b,d_c,d_d,d_a,0xc4ac,0x5665,m2,23
 209
 210         round_48_63     d_a,d_b,d_c,d_d,0xf429,0x2244,m0,6
 211         round_48_63     d_d,d_a,d_b,d_c,0x432a,0xff97,m7,10
 212         round_48_63     d_c,d_d,d_a,d_b,0xab94,0x23a7,m14,15
 213         round_48_63     d_b,d_c,d_d,d_a,0xfc93,0xa039,m5,21
 214         round_48_63     d_a,d_b,d_c,d_d,0x655b,0x59c3,m12,6
 215         round_48_63     d_d,d_a,d_b,d_c,0x8f0c,0xcc92,m3,10
 216         round_48_63     d_c,d_d,d_a,d_b,0xffef,0xf47d,m10,15
 217         round_48_63     d_b,d_c,d_d,d_a,0x8584,0x5dd1,m1,21
 218         round_48_63     d_a,d_b,d_c,d_d,0x6fa8,0x7e4f,m8,6
 219         round_48_63     d_d,d_a,d_b,d_c,0xfe2c,0xe6e0,m15,10
 220         round_48_63     d_c,d_d,d_a,d_b,0xa301,0x4314,m6,15
 221         round_48_63     d_b,d_c,d_d,d_a,0x4e08,0x11a1,m13,21
 222         round_48_63     d_a,d_b,d_c,d_d,0xf753,0x7e82,m4,6
 223         ldp             d_a1,d_b1,[digest_addr]
 224         round_48_63     d_d,d_a,d_b,d_c,0xbd3a,0xf235,m11,10
 225         ldp             d_c1,d_d1,[digest_addr,8]
 226         round_48_63     d_c,d_d,d_a,d_b,0x2ad7,0xd2bb,m2,15
 227         round_48_63     d_b,d_c,d_d,d_a,0xeb86,0xd391,m9,21
 228
 229         cmp     buf_adr,end
 230         add     d_a,d_a1 ,d_a
 231         str     d_a,[digest_addr]
 232         add     d_b,d_b1 ,d_b
 233         str     d_b,[digest_addr,4]
 234         add     d_c,d_c1 ,d_c
 235         str     d_c,[digest_addr,8]
 236         add     d_d,d_d1 ,d_d
 237         str     d_d,[digest_addr,12]
 238         bne     .loop_start
 239
 240 .exit:
 241         ldp     x19, x20, [sp, 16]
 242         ldp     x21, x22, [sp, 32]
 243         ldp     x23, x24, [sp, 48]
 244         ldp     x25, x26, [sp, 64]
 245         ldp     x27, x28, [sp, 80]
 246         ldp     x29, x30, [sp], 96
 247         ret
 248         .size md5_mb_asimd_x1, .-md5_mb_asimd_x1