ceph/src/crypto/isa-l/isa-l_crypto/md5_mb/md5_mb_mgr_flush_sse.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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  28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29
  30 %include "md5_job.asm"
  31 %include "md5_mb_mgr_datastruct.asm"
  32
  33 %include "reg_sizes.asm"
  34
  35 extern md5_mb_x4x2_sse
  36 default rel
  37
  38 %if 1
  39 %ifidn __OUTPUT_FORMAT__, elf64
  40 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  41 ; UN*X register definitions
  42 %define arg1    rdi ; rcx
  43 %define arg2    rsi ; rdx
  44
  45 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  46
  47 %else
  48
  49 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  50 ; WINDOWS register definitions
  51 %define arg1    rcx
  52 %define arg2    rdx
  53
  54 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  55 %endif
  56
  57 ; Common register definitions
  58
  59 %define state   arg1
  60 %define len2    arg2
  61
  62 ; idx must be a register not clobberred by md5_mb_x4x2_sse
  63 %define idx             r8
  64
  65 %define unused_lanes    r9
  66
  67 %define lane_data       r10
  68
  69 %define job_rax         rax
  70 %define tmp             rax
  71
  72 %endif ;; if 1
  73
  74 ; STACK_SPACE needs to be an odd multiple of 8
  75 _XMM_SAVE_SIZE  equ 10*16
  76 _GPR_SAVE_SIZE  equ 8*8
  77 _ALIGN_SIZE     equ 8
  78
  79 _XMM_SAVE       equ 0
  80 _GPR_SAVE       equ _XMM_SAVE + _XMM_SAVE_SIZE
  81 STACK_SPACE     equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
  82
  83 %define APPEND(a,b) a %+ b
  84
  85 ; JOB* md5_mb_mgr_flush_sse(MB_MGR_HMAC_OOO *state)
  86 ; arg 1 : rcx : state
  87 global md5_mb_mgr_flush_sse:function
  88 md5_mb_mgr_flush_sse:
  89         sub     rsp, STACK_SPACE
  90         mov     [rsp + _GPR_SAVE + 8*0], rbx
  91         mov     [rsp + _GPR_SAVE + 8*3], rbp
  92         mov     [rsp + _GPR_SAVE + 8*4], r12
  93         mov     [rsp + _GPR_SAVE + 8*5], r13
  94         mov     [rsp + _GPR_SAVE + 8*6], r14
  95         mov     [rsp + _GPR_SAVE + 8*7], r15
  96 %ifidn __OUTPUT_FORMAT__, win64
  97         mov     [rsp + _GPR_SAVE + 8*1], rsi
  98         mov     [rsp + _GPR_SAVE + 8*2], rdi
  99         movdqa  [rsp + _XMM_SAVE + 16*0], xmm6
 100         movdqa  [rsp + _XMM_SAVE + 16*1], xmm7
 101         movdqa  [rsp + _XMM_SAVE + 16*2], xmm8
 102         movdqa  [rsp + _XMM_SAVE + 16*3], xmm9
 103         movdqa  [rsp + _XMM_SAVE + 16*4], xmm10
 104         movdqa  [rsp + _XMM_SAVE + 16*5], xmm11
 105         movdqa  [rsp + _XMM_SAVE + 16*6], xmm12
 106         movdqa  [rsp + _XMM_SAVE + 16*7], xmm13
 107         movdqa  [rsp + _XMM_SAVE + 16*8], xmm14
 108         movdqa  [rsp + _XMM_SAVE + 16*9], xmm15
 109 %endif
 110
 111         ; if bit (32+3) is set, then all lanes are empty
 112         mov     unused_lanes, [state + _unused_lanes]
 113         bt      unused_lanes, 32+3
 114         jc      return_null
 115
 116         ; find a lane with a non-null job
 117         xor     idx, idx
 118         cmp     qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
 119         cmovne  idx, [one]
 120         cmp     qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0
 121         cmovne  idx, [two]
 122         cmp     qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0
 123         cmovne  idx, [three]
 124         cmp     qword [state + _ldata + 4 * _LANE_DATA_size + _job_in_lane], 0
 125         cmovne  idx, [four]
 126         cmp     qword [state + _ldata + 5 * _LANE_DATA_size + _job_in_lane], 0
 127         cmovne  idx, [five]
 128         cmp     qword [state + _ldata + 6 * _LANE_DATA_size + _job_in_lane], 0
 129         cmovne  idx, [six]
 130         cmp     qword [state + _ldata + 7 * _LANE_DATA_size + _job_in_lane], 0
 131         cmovne  idx, [seven]
 132
 133         ; copy idx to empty lanes
 134 copy_lane_data:
 135         mov     tmp, [state + _args + _data_ptr + 8*idx]
 136
 137 %assign I 0
 138 %rep 8
 139         cmp     qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
 140         jne     APPEND(skip_,I)
 141         mov     [state + _args + _data_ptr + 8*I], tmp
 142         mov     dword [state + _lens + 4*I], 0xFFFFFFFF
 143 APPEND(skip_,I):
 144 %assign I (I+1)
 145 %endrep
 146
 147         ; Find min length
 148         movdqa  xmm0, [state + _lens + 0*16]
 149         movdqa  xmm1, [state + _lens + 1*16]
 150
 151         movdqa  xmm2, xmm0
 152         pminud  xmm2, xmm1        ; xmm2 has {D,C,B,A}
 153         palignr xmm3, xmm2, 8     ; xmm3 has {x,x,D,C}
 154         pminud  xmm2, xmm3        ; xmm2 has {x,x,E,F}
 155         palignr xmm3, xmm2, 4     ; xmm3 has {x,x,x,E}
 156         pminud  xmm2, xmm3        ; xmm2 has min value in low dword
 157
 158         movd    DWORD(idx), xmm2
 159         mov     len2, idx
 160         and     idx, 0xF
 161         shr     len2, 4
 162         jz      len_is_0
 163
 164         pand   xmm2, [rel clear_low_nibble]
 165         pshufd xmm2, xmm2, 0
 166
 167         psubd  xmm0, xmm2
 168         psubd  xmm1, xmm2
 169
 170         movdqa [state + _lens + 0*16], xmm0
 171         movdqa [state + _lens + 1*16], xmm1
 172
 173
 174         ; "state" and "args" are the same address, arg1
 175         ; len is arg2
 176         call    md5_mb_x4x2_sse
 177         ; state and idx are intact
 178
 179 len_is_0:
 180         ; process completed job "idx"
 181         imul    lane_data, idx, _LANE_DATA_size
 182         lea     lane_data, [state + _ldata + lane_data]
 183
 184         mov     job_rax, [lane_data + _job_in_lane]
 185         mov     qword [lane_data + _job_in_lane], 0
 186         mov     dword [job_rax + _status], STS_COMPLETED
 187         mov     unused_lanes, [state + _unused_lanes]
 188         shl     unused_lanes, 4
 189         or      unused_lanes, idx
 190         mov     [state + _unused_lanes], unused_lanes
 191
 192         mov     dword [state + _lens + 4*idx], 0xFFFFFFFF
 193
 194         movd    xmm0, [state + _args_digest + 4*idx + 0*32]
 195         pinsrd  xmm0, [state + _args_digest + 4*idx + 1*32], 1
 196         pinsrd  xmm0, [state + _args_digest + 4*idx + 2*32], 2
 197         pinsrd  xmm0, [state + _args_digest + 4*idx + 3*32], 3
 198
 199         movdqa  [job_rax + _result_digest + 0*16], xmm0
 200
 201 return:
 202
 203 %ifidn __OUTPUT_FORMAT__, win64
 204         movdqa  xmm6, [rsp + _XMM_SAVE + 16*0]
 205         movdqa  xmm7, [rsp + _XMM_SAVE + 16*1]
 206         movdqa  xmm8, [rsp + _XMM_SAVE + 16*2]
 207         movdqa  xmm9, [rsp + _XMM_SAVE + 16*3]
 208         movdqa  xmm10, [rsp + _XMM_SAVE + 16*4]
 209         movdqa  xmm11, [rsp + _XMM_SAVE + 16*5]
 210         movdqa  xmm12, [rsp + _XMM_SAVE + 16*6]
 211         movdqa  xmm13, [rsp + _XMM_SAVE + 16*7]
 212         movdqa  xmm14, [rsp + _XMM_SAVE + 16*8]
 213         movdqa  xmm15, [rsp + _XMM_SAVE + 16*9]
 214         mov     rsi, [rsp + _GPR_SAVE + 8*1]
 215         mov     rdi, [rsp + _GPR_SAVE + 8*2]
 216 %endif
 217         mov     rbx, [rsp + _GPR_SAVE + 8*0]
 218         mov     rbp, [rsp + _GPR_SAVE + 8*3]
 219         mov     r12, [rsp + _GPR_SAVE + 8*4]
 220         mov     r13, [rsp + _GPR_SAVE + 8*5]
 221         mov     r14, [rsp + _GPR_SAVE + 8*6]
 222         mov     r15, [rsp + _GPR_SAVE + 8*7]
 223         add     rsp, STACK_SPACE
 224
 225         ret
 226
 227 return_null:
 228         xor     job_rax, job_rax
 229         jmp     return
 230
 231
 232 section .data align=16
 233
 234 align 16
 235 clear_low_nibble:
 236         dq 0x00000000FFFFFFF0, 0x0000000000000000
 237 one:    dq  1
 238 two:    dq  2
 239 three:  dq  3
 240 four:   dq  4
 241 five:   dq  5
 242 six:    dq  6
 243 seven:  dq  7
 244