]> git.proxmox.com Git - ceph.git/blob - ceph/src/crypto/isa-l/isa-l_crypto/md5_mb/md5_multibinary.asm
add subtree-ish sources for 12.0.3
[ceph.git] / ceph / src / crypto / isa-l / isa-l_crypto / md5_mb / md5_multibinary.asm
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3 ;
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
6 ; are met:
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
12 ; distribution.
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
16 ;
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30 %ifidn __OUTPUT_FORMAT__, elf64
31 %define WRT_OPT wrt ..plt
32 %else
33 %define WRT_OPT
34 %endif
35
36 %include "reg_sizes.asm"
37 %include "multibinary.asm"
38 default rel
39 [bits 64]
40
41 ; declare the L3 ctx level symbols (these will then call the appropriate
42 ; L2 symbols)
43 extern md5_ctx_mgr_init_sse
44 extern md5_ctx_mgr_submit_sse
45 extern md5_ctx_mgr_flush_sse
46
47 extern md5_ctx_mgr_init_avx
48 extern md5_ctx_mgr_submit_avx
49 extern md5_ctx_mgr_flush_avx
50
51 extern md5_ctx_mgr_init_avx2
52 extern md5_ctx_mgr_submit_avx2
53 extern md5_ctx_mgr_flush_avx2
54
55 %ifdef HAVE_AS_KNOWS_AVX512
56 extern md5_ctx_mgr_init_avx512
57 extern md5_ctx_mgr_submit_avx512
58 extern md5_ctx_mgr_flush_avx512
59 %endif
60
61 ;;; *_mbinit are initial values for *_dispatched; is updated on first call.
62 ;;; Therefore, *_dispatch_init is only executed on first call.
63
64 ; Initialise symbols
65 mbin_interface md5_ctx_mgr_init
66 mbin_interface md5_ctx_mgr_submit
67 mbin_interface md5_ctx_mgr_flush
68
69 %ifdef HAVE_AS_KNOWS_AVX512
70 ; Reuse mbin_dispatch_init6 through replacing base by sse version
71 mbin_dispatch_init6 md5_ctx_mgr_init, md5_ctx_mgr_init_sse, md5_ctx_mgr_init_sse, md5_ctx_mgr_init_avx, md5_ctx_mgr_init_avx2, md5_ctx_mgr_init_avx512
72 mbin_dispatch_init6 md5_ctx_mgr_submit, md5_ctx_mgr_submit_sse, md5_ctx_mgr_submit_sse, md5_ctx_mgr_submit_avx, md5_ctx_mgr_submit_avx2, md5_ctx_mgr_submit_avx512
73 mbin_dispatch_init6 md5_ctx_mgr_flush, md5_ctx_mgr_flush_sse, md5_ctx_mgr_flush_sse, md5_ctx_mgr_flush_avx, md5_ctx_mgr_flush_avx2, md5_ctx_mgr_flush_avx512
74 %else
75 mbin_dispatch_init md5_ctx_mgr_init, md5_ctx_mgr_init_sse, md5_ctx_mgr_init_avx, md5_ctx_mgr_init_avx2
76 mbin_dispatch_init md5_ctx_mgr_submit, md5_ctx_mgr_submit_sse, md5_ctx_mgr_submit_avx, md5_ctx_mgr_submit_avx2
77 mbin_dispatch_init md5_ctx_mgr_flush, md5_ctx_mgr_flush_sse, md5_ctx_mgr_flush_avx, md5_ctx_mgr_flush_avx2
78 %endif
79
80 ;; func core, ver, snum
81 slversion md5_ctx_mgr_init, 00, 03, 0189
82 slversion md5_ctx_mgr_submit, 00, 03, 018a
83 slversion md5_ctx_mgr_flush, 00, 03, 018b