1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30 %include "sha1_job.asm"
31 %include "sha1_mb_mgr_datastruct.asm"
33 %include "reg_sizes.asm"
38 %ifidn __OUTPUT_FORMAT__, elf64
39 ; LINUX register definitions
40 %define arg1 rdi ; rcx
41 %define arg2 rsi ; rdx
43 ; idx needs to be in a register not clobberred by sha1_mult
46 ; WINDOWS register definitions
50 ; idx needs to be in a register not clobberred by sha1_mult
59 %define unused_lanes rbx
65 %define size_offset rax
67 %define start_offset rax
71 %define extra_blocks arg2
81 ; STACK_SPACE needs to be an odd multiple of 8
82 _XMM_SAVE_SIZE equ 10*16
83 _GPR_SAVE_SIZE equ 8*2
87 _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
88 STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
90 %define APPEND(a,b) a %+ b
92 ; SHA1_JOB* sha1_mb_mgr_flush_avx(SHA1_MB_JOB_MGR *state)
94 global sha1_mb_mgr_flush_avx:function
95 sha1_mb_mgr_flush_avx:
98 mov [rsp + _GPR_SAVE + 8*0], rbx
99 %ifidn __OUTPUT_FORMAT__, win64
100 mov [rsp + _GPR_SAVE + 8*1], rsi
101 vmovdqa [rsp + _XMM_SAVE + 16*0], xmm6
102 vmovdqa [rsp + _XMM_SAVE + 16*1], xmm7
103 vmovdqa [rsp + _XMM_SAVE + 16*2], xmm8
104 vmovdqa [rsp + _XMM_SAVE + 16*3], xmm9
105 vmovdqa [rsp + _XMM_SAVE + 16*4], xmm10
106 vmovdqa [rsp + _XMM_SAVE + 16*5], xmm11
107 vmovdqa [rsp + _XMM_SAVE + 16*6], xmm12
108 vmovdqa [rsp + _XMM_SAVE + 16*7], xmm13
109 vmovdqa [rsp + _XMM_SAVE + 16*8], xmm14
110 vmovdqa [rsp + _XMM_SAVE + 16*9], xmm15
113 mov unused_lanes, [state + _unused_lanes]
114 bt unused_lanes, 16+3
117 ; find a lane with a non-null job
119 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
121 cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0
123 cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0
126 ; copy idx to empty lanes
128 mov tmp, [state + _args + _data_ptr + 8*idx]
132 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
134 mov [state + _args + _data_ptr + 8*I], tmp
135 mov dword [state + _lens + 4*I], 0xFFFFFFFF
141 mov DWORD(lens0), [state + _lens + 0*4]
143 mov DWORD(lens1), [state + _lens + 1*4]
146 mov DWORD(lens2), [state + _lens + 2*4]
149 mov DWORD(lens3), [state + _lens + 3*4]
162 mov [state + _lens + 0*4], DWORD(lens0)
163 mov [state + _lens + 1*4], DWORD(lens1)
164 mov [state + _lens + 2*4], DWORD(lens2)
165 mov [state + _lens + 3*4], DWORD(lens3)
167 ; "state" and "args" are the same address, arg1
170 ; state and idx are intact
173 ; process completed job "idx"
174 imul lane_data, idx, _LANE_DATA_size
175 lea lane_data, [state + _ldata + lane_data]
177 mov job_rax, [lane_data + _job_in_lane]
178 mov qword [lane_data + _job_in_lane], 0
179 mov dword [job_rax + _status], STS_COMPLETED
180 mov unused_lanes, [state + _unused_lanes]
183 mov [state + _unused_lanes], unused_lanes
185 vmovd xmm0, [state + _args_digest + 4*idx + 0*16]
186 vpinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1
187 vpinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2
188 vpinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3
189 mov DWORD(tmp2), [state + _args_digest + 4*idx + 4*16]
191 vmovdqa [job_rax + _result_digest + 0*16], xmm0
192 mov [job_rax + _result_digest + 1*16], DWORD(tmp2)
196 %ifidn __OUTPUT_FORMAT__, win64
197 vmovdqa xmm6, [rsp + _XMM_SAVE + 16*0]
198 vmovdqa xmm7, [rsp + _XMM_SAVE + 16*1]
199 vmovdqa xmm8, [rsp + _XMM_SAVE + 16*2]
200 vmovdqa xmm9, [rsp + _XMM_SAVE + 16*3]
201 vmovdqa xmm10, [rsp + _XMM_SAVE + 16*4]
202 vmovdqa xmm11, [rsp + _XMM_SAVE + 16*5]
203 vmovdqa xmm12, [rsp + _XMM_SAVE + 16*6]
204 vmovdqa xmm13, [rsp + _XMM_SAVE + 16*7]
205 vmovdqa xmm14, [rsp + _XMM_SAVE + 16*8]
206 vmovdqa xmm15, [rsp + _XMM_SAVE + 16*9]
207 mov rsi, [rsp + _GPR_SAVE + 8*1]
209 mov rbx, [rsp + _GPR_SAVE + 8*0]
218 section .data align=16