1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30 %include "sha1_job.asm"
31 %include "sha1_mb_mgr_datastruct.asm"
33 %include "reg_sizes.asm"
38 %ifidn __OUTPUT_FORMAT__, elf64
39 ; LINUX register definitions
40 %define arg1 rdi ; rcx
41 %define arg2 rsi ; rdx
43 ; idx needs to be other than ARG1, ARG2, rax, r8-r11
46 ; WINDOWS register definitions
50 ; idx needs to be other than ARG1, ARG2, rax, r8-r11
59 %define unused_lanes rbx
65 %define size_offset rax
67 %define start_offset rax
71 %define extra_blocks arg2
82 ; STACK_SPACE needs to be an odd multiple of 8
83 _XMM_SAVE_SIZE equ 10*16
84 _GPR_SAVE_SIZE equ 8*2
88 _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
89 STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
91 %define APPEND(a,b) a %+ b
93 ; SHA1_JOB* sha1_mb_mgr_flush_sse(SHA1_MB_JOB_MGR *state)
95 global sha1_mb_mgr_flush_sse:function
96 sha1_mb_mgr_flush_sse:
99 mov [rsp + _GPR_SAVE + 8*0], rbx
100 %ifidn __OUTPUT_FORMAT__, win64
101 mov [rsp + _GPR_SAVE + 8*1], rsi
102 movdqa [rsp + _XMM_SAVE + 16*0], xmm6
103 movdqa [rsp + _XMM_SAVE + 16*1], xmm7
104 movdqa [rsp + _XMM_SAVE + 16*2], xmm8
105 movdqa [rsp + _XMM_SAVE + 16*3], xmm9
106 movdqa [rsp + _XMM_SAVE + 16*4], xmm10
107 movdqa [rsp + _XMM_SAVE + 16*5], xmm11
108 movdqa [rsp + _XMM_SAVE + 16*6], xmm12
109 movdqa [rsp + _XMM_SAVE + 16*7], xmm13
110 movdqa [rsp + _XMM_SAVE + 16*8], xmm14
111 movdqa [rsp + _XMM_SAVE + 16*9], xmm15
114 mov unused_lanes, [state + _unused_lanes]
115 bt unused_lanes, 16+3
118 ; find a lane with a non-null job
120 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
122 cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0
124 cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0
127 ; copy idx to empty lanes
129 mov tmp, [state + _args + _data_ptr + 8*idx]
133 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
135 mov [state + _args + _data_ptr + 8*I], tmp
136 mov dword [state + _lens + 4*I], 0xFFFFFFFF
142 mov DWORD(lens0), [state + _lens + 0*4]
144 mov DWORD(lens1), [state + _lens + 1*4]
147 mov DWORD(lens2), [state + _lens + 2*4]
150 mov DWORD(lens3), [state + _lens + 3*4]
163 mov [state + _lens + 0*4], DWORD(lens0)
164 mov [state + _lens + 1*4], DWORD(lens1)
165 mov [state + _lens + 2*4], DWORD(lens2)
166 mov [state + _lens + 3*4], DWORD(lens3)
168 ; "state" and "args" are the same address, arg1
171 ; state and idx are intact
174 ; process completed job "idx"
175 imul lane_data, idx, _LANE_DATA_size
176 lea lane_data, [state + _ldata + lane_data]
178 mov job_rax, [lane_data + _job_in_lane]
179 mov qword [lane_data + _job_in_lane], 0
180 mov dword [job_rax + _status], STS_COMPLETED
181 mov unused_lanes, [state + _unused_lanes]
184 mov [state + _unused_lanes], unused_lanes
186 movd xmm0, [state + _args_digest + 4*idx + 0*16]
187 pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1
188 pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2
189 pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3
190 mov DWORD(tmp2), [state + _args_digest + 4*idx + 4*16]
192 movdqa [job_rax + _result_digest + 0*16], xmm0
193 mov [job_rax + _result_digest + 1*16], DWORD(tmp2)
197 %ifidn __OUTPUT_FORMAT__, win64
198 movdqa xmm6, [rsp + _XMM_SAVE + 16*0]
199 movdqa xmm7, [rsp + _XMM_SAVE + 16*1]
200 movdqa xmm8, [rsp + _XMM_SAVE + 16*2]
201 movdqa xmm9, [rsp + _XMM_SAVE + 16*3]
202 movdqa xmm10, [rsp + _XMM_SAVE + 16*4]
203 movdqa xmm11, [rsp + _XMM_SAVE + 16*5]
204 movdqa xmm12, [rsp + _XMM_SAVE + 16*6]
205 movdqa xmm13, [rsp + _XMM_SAVE + 16*7]
206 movdqa xmm14, [rsp + _XMM_SAVE + 16*8]
207 movdqa xmm15, [rsp + _XMM_SAVE + 16*9]
208 mov rsi, [rsp + _GPR_SAVE + 8*1]
210 mov rbx, [rsp + _GPR_SAVE + 8*0]
219 section .data align=16