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add subtree-ish sources for 12.0.3
[ceph.git] / ceph / src / crypto / isa-l / isa-l_crypto / sha1_mb / sha1_mb_mgr_submit_avx.asm
1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
3 ;
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
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7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
12 ; distribution.
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
16 ;
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29
30 %include "sha1_job.asm"
31 %include "sha1_mb_mgr_datastruct.asm"
32
33 %include "reg_sizes.asm"
34
35 extern sha1_mb_x4_avx
36
37 %ifidn __OUTPUT_FORMAT__, win64
38 ; WINDOWS register definitions
39 %define arg1 rcx
40 %define arg2 rdx
41
42 ; idx needs to be in a register not clobberred by sha1_mult
43 %define last_len rsi
44 %define idx rsi
45
46 %define size_offset rdi
47 %define tmp2 rdi
48
49 %else
50 ; LINUX register definitions
51 %define arg1 rdi
52 %define arg2 rsi
53
54 ; idx needs to be in a register not clobberred by sha1_mult
55 %define last_len rdx
56 %define idx rdx
57
58 %define size_offset rcx
59 %define tmp2 rcx
60
61 %endif
62
63 ; Common definitions
64 %define state arg1
65 %define job arg2
66 %define len2 arg2
67 %define p2 arg2
68
69 %define p r11
70 %define start_offset r11
71
72 %define unused_lanes rbx
73
74 %define job_rax rax
75 %define len rax
76
77 %define lane rbp
78 %define tmp3 rbp
79 %define lens3 rbp
80
81 %define extra_blocks r8
82 %define lens0 r8
83
84 %define tmp r9
85 %define lens1 r9
86
87 %define lane_data r10
88 %define lens2 r10
89
90 ; STACK_SPACE needs to be an odd multiple of 8
91 %define STACK_SPACE 8*4 + 16*10 + 8
92
93 ; SHA1_JOB* sha1_mb_mgr_submit_avx(SHA1_MB_JOB_MGR *state, SHA1_JOB *job)
94 ; arg 1 : rcx : state
95 ; arg 2 : rdx : job
96 global sha1_mb_mgr_submit_avx:function
97 sha1_mb_mgr_submit_avx:
98
99 sub rsp, STACK_SPACE
100 mov [rsp + 8*0], rbx
101 mov [rsp + 8*3], rbp
102 %ifidn __OUTPUT_FORMAT__, win64
103 mov [rsp + 8*1], rsi
104 mov [rsp + 8*2], rdi
105 vmovdqa [rsp + 8*4 + 16*0], xmm6
106 vmovdqa [rsp + 8*4 + 16*1], xmm7
107 vmovdqa [rsp + 8*4 + 16*2], xmm8
108 vmovdqa [rsp + 8*4 + 16*3], xmm9
109 vmovdqa [rsp + 8*4 + 16*4], xmm10
110 vmovdqa [rsp + 8*4 + 16*5], xmm11
111 vmovdqa [rsp + 8*4 + 16*6], xmm12
112 vmovdqa [rsp + 8*4 + 16*7], xmm13
113 vmovdqa [rsp + 8*4 + 16*8], xmm14
114 vmovdqa [rsp + 8*4 + 16*9], xmm15
115 %endif
116
117 mov unused_lanes, [state + _unused_lanes]
118 movzx lane, BYTE(unused_lanes)
119 and lane, 0xF
120 shr unused_lanes, 4
121 imul lane_data, lane, _LANE_DATA_size
122 mov dword [job + _status], STS_BEING_PROCESSED
123 lea lane_data, [state + _ldata + lane_data]
124 mov [state + _unused_lanes], unused_lanes
125 mov DWORD(len), [job + _len]
126
127 shl len, 4
128 or len, lane
129
130 mov [lane_data + _job_in_lane], job
131 mov [state + _lens + 4*lane], DWORD(len)
132
133 ; Load digest words from result_digest
134 vmovdqu xmm0, [job + _result_digest + 0*16]
135 mov DWORD(tmp), [job + _result_digest + 1*16]
136 vmovd [state + _args_digest + 4*lane + 0*16], xmm0
137 vpextrd [state + _args_digest + 4*lane + 1*16], xmm0, 1
138 vpextrd [state + _args_digest + 4*lane + 2*16], xmm0, 2
139 vpextrd [state + _args_digest + 4*lane + 3*16], xmm0, 3
140 mov [state + _args_digest + 4*lane + 4*16], DWORD(tmp)
141
142 mov p, [job + _buffer]
143 mov [state + _args_data_ptr + 8*lane], p
144
145 cmp unused_lanes, 0xF
146 jne return_null
147
148 start_loop:
149 ; Find min length
150 mov DWORD(lens0), [state + _lens + 0*4]
151 mov idx, lens0
152 mov DWORD(lens1), [state + _lens + 1*4]
153 cmp lens1, idx
154 cmovb idx, lens1
155 mov DWORD(lens2), [state + _lens + 2*4]
156 cmp lens2, idx
157 cmovb idx, lens2
158 mov DWORD(lens3), [state + _lens + 3*4]
159 cmp lens3, idx
160 cmovb idx, lens3
161 mov len2, idx
162 and idx, 0xF
163 and len2, ~0xF
164 jz len_is_0
165
166 sub lens0, len2
167 sub lens1, len2
168 sub lens2, len2
169 sub lens3, len2
170 shr len2, 4
171 mov [state + _lens + 0*4], DWORD(lens0)
172 mov [state + _lens + 1*4], DWORD(lens1)
173 mov [state + _lens + 2*4], DWORD(lens2)
174 mov [state + _lens + 3*4], DWORD(lens3)
175
176 ; "state" and "args" are the same address, arg1
177 ; len is arg2
178 call sha1_mb_x4_avx
179 ; state and idx are intact
180
181 len_is_0:
182 ; process completed job "idx"
183 imul lane_data, idx, _LANE_DATA_size
184 lea lane_data, [state + _ldata + lane_data]
185
186 mov job_rax, [lane_data + _job_in_lane]
187 mov unused_lanes, [state + _unused_lanes]
188 mov qword [lane_data + _job_in_lane], 0
189 mov dword [job_rax + _status], STS_COMPLETED
190 shl unused_lanes, 4
191 or unused_lanes, idx
192 mov [state + _unused_lanes], unused_lanes
193
194 vmovd xmm0, [state + _args_digest + 4*idx + 0*16]
195 vpinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1
196 vpinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2
197 vpinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3
198 mov DWORD(tmp), [state + _args_digest + 4*idx + 4*16]
199
200 vmovdqa [job_rax + _result_digest + 0*16], xmm0
201 mov [job_rax + _result_digest + 1*16], DWORD(tmp)
202
203 return:
204
205 %ifidn __OUTPUT_FORMAT__, win64
206 vmovdqa xmm6, [rsp + 8*4 + 16*0]
207 vmovdqa xmm7, [rsp + 8*4 + 16*1]
208 vmovdqa xmm8, [rsp + 8*4 + 16*2]
209 vmovdqa xmm9, [rsp + 8*4 + 16*3]
210 vmovdqa xmm10, [rsp + 8*4 + 16*4]
211 vmovdqa xmm11, [rsp + 8*4 + 16*5]
212 vmovdqa xmm12, [rsp + 8*4 + 16*6]
213 vmovdqa xmm13, [rsp + 8*4 + 16*7]
214 vmovdqa xmm14, [rsp + 8*4 + 16*8]
215 vmovdqa xmm15, [rsp + 8*4 + 16*9]
216 mov rsi, [rsp + 8*1]
217 mov rdi, [rsp + 8*2]
218 %endif
219 mov rbx, [rsp + 8*0]
220 mov rbp, [rsp + 8*3]
221 add rsp, STACK_SPACE
222
223 ret
224
225 return_null:
226 xor job_rax, job_rax
227 jmp return
228
229
230 section .data align=16
231
232 align 16
233 H0: dd 0x67452301
234 H1: dd 0xefcdab89
235 H2: dd 0x98badcfe
236 H3: dd 0x10325476
237 H4: dd 0xc3d2e1f0
238