ceph/src/crypto/isa-l/isa-l_crypto/sha1_mb/sha1_multibinary.asm

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   2 ;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
   3 ;
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  29
  30 %ifidn __OUTPUT_FORMAT__, elf64
  31 %define WRT_OPT         wrt ..plt
  32 %else
  33 %define WRT_OPT
  34 %endif
  35
  36 %include "reg_sizes.asm"
  37 %include "multibinary.asm"
  38 default rel
  39 [bits 64]
  40
  41 ; declare the L3 ctx level symbols (these will then call the appropriate
  42 ; L2 symbols)
  43 extern sha1_ctx_mgr_init_sse
  44 extern sha1_ctx_mgr_submit_sse
  45 extern sha1_ctx_mgr_flush_sse
  46
  47 extern sha1_ctx_mgr_init_avx
  48 extern sha1_ctx_mgr_submit_avx
  49 extern sha1_ctx_mgr_flush_avx
  50
  51 extern sha1_ctx_mgr_init_avx2
  52 extern sha1_ctx_mgr_submit_avx2
  53 extern sha1_ctx_mgr_flush_avx2
  54
  55 extern sha1_ctx_mgr_init_base
  56 extern sha1_ctx_mgr_submit_base
  57 extern sha1_ctx_mgr_flush_base
  58
  59 %ifdef HAVE_AS_KNOWS_AVX512
  60  extern sha1_ctx_mgr_init_avx512
  61  extern sha1_ctx_mgr_submit_avx512
  62  extern sha1_ctx_mgr_flush_avx512
  63 %endif
  64
  65 %ifdef HAVE_AS_KNOWS_SHANI
  66  extern sha1_ctx_mgr_init_sse_ni
  67  extern sha1_ctx_mgr_submit_sse_ni
  68  extern sha1_ctx_mgr_flush_sse_ni
  69 %endif
  70
  71 %ifdef HAVE_AS_KNOWS_AVX512
  72  %ifdef HAVE_AS_KNOWS_SHANI
  73   extern sha1_ctx_mgr_init_avx512_ni
  74   extern sha1_ctx_mgr_submit_avx512_ni
  75   extern sha1_ctx_mgr_flush_avx512_ni
  76  %endif
  77 %endif
  78
  79 ;;; *_mbinit are initial values for *_dispatched; is updated on first call.
  80 ;;; Therefore, *_dispatch_init is only executed on first call.
  81
  82 ; Initialise symbols
  83 mbin_interface sha1_ctx_mgr_init
  84 mbin_interface sha1_ctx_mgr_submit
  85 mbin_interface sha1_ctx_mgr_flush
  86
  87 %ifdef HAVE_AS_KNOWS_AVX512
  88  ; Reuse mbin_dispatch_init6's extension through replacing base by sse version
  89  %ifdef HAVE_AS_KNOWS_SHANI
  90   mbin_dispatch_base_to_avx512_shani sha1_ctx_mgr_init, sha1_ctx_mgr_init_base, \
  91         sha1_ctx_mgr_init_sse, sha1_ctx_mgr_init_avx, sha1_ctx_mgr_init_avx2, \
  92         sha1_ctx_mgr_init_avx512, sha1_ctx_mgr_init_sse_ni, sha1_ctx_mgr_init_avx512_ni
  93   mbin_dispatch_base_to_avx512_shani sha1_ctx_mgr_submit, sha1_ctx_mgr_submit_base, \
  94         sha1_ctx_mgr_submit_sse, sha1_ctx_mgr_submit_avx, sha1_ctx_mgr_submit_avx2, \
  95         sha1_ctx_mgr_submit_avx512, sha1_ctx_mgr_submit_sse_ni, sha1_ctx_mgr_submit_avx512_ni
  96   mbin_dispatch_base_to_avx512_shani sha1_ctx_mgr_flush, sha1_ctx_mgr_flush_base, \
  97         sha1_ctx_mgr_flush_sse, sha1_ctx_mgr_flush_avx, sha1_ctx_mgr_flush_avx2, \
  98         sha1_ctx_mgr_flush_avx512, sha1_ctx_mgr_flush_sse_ni, sha1_ctx_mgr_flush_avx512_ni
  99  %else
 100   mbin_dispatch_init6 sha1_ctx_mgr_init, sha1_ctx_mgr_init_base, \
 101         sha1_ctx_mgr_init_sse, sha1_ctx_mgr_init_avx, sha1_ctx_mgr_init_avx2, \
 102         sha1_ctx_mgr_init_avx512
 103   mbin_dispatch_init6 sha1_ctx_mgr_submit, sha1_ctx_mgr_submit_base, \
 104         sha1_ctx_mgr_submit_sse, sha1_ctx_mgr_submit_avx, sha1_ctx_mgr_submit_avx2, \
 105         sha1_ctx_mgr_submit_avx512
 106   mbin_dispatch_init6 sha1_ctx_mgr_flush, sha1_ctx_mgr_flush_base, \
 107         sha1_ctx_mgr_flush_sse, sha1_ctx_mgr_flush_avx, sha1_ctx_mgr_flush_avx2, \
 108         sha1_ctx_mgr_flush_avx512
 109  %endif
 110 %else
 111  %ifdef HAVE_AS_KNOWS_SHANI
 112   mbin_dispatch_sse_to_avx2_shani sha1_ctx_mgr_init, sha1_ctx_mgr_init_sse, \
 113         sha1_ctx_mgr_init_avx, sha1_ctx_mgr_init_avx2, sha1_ctx_mgr_init_sse_ni
 114   mbin_dispatch_sse_to_avx2_shani sha1_ctx_mgr_submit, sha1_ctx_mgr_submit_sse, \
 115         sha1_ctx_mgr_submit_avx, sha1_ctx_mgr_submit_avx2, sha1_ctx_mgr_submit_sse_ni
 116   mbin_dispatch_sse_to_avx2_shani sha1_ctx_mgr_flush, sha1_ctx_mgr_flush_sse, \
 117         sha1_ctx_mgr_flush_avx, sha1_ctx_mgr_flush_avx2, sha1_ctx_mgr_flush_sse_ni
 118  %else
 119   mbin_dispatch_init sha1_ctx_mgr_init, sha1_ctx_mgr_init_sse, \
 120         sha1_ctx_mgr_init_avx, sha1_ctx_mgr_init_avx2
 121   mbin_dispatch_init sha1_ctx_mgr_submit, sha1_ctx_mgr_submit_sse, \
 122         sha1_ctx_mgr_submit_avx, sha1_ctx_mgr_submit_avx2
 123   mbin_dispatch_init sha1_ctx_mgr_flush, sha1_ctx_mgr_flush_sse, \
 124         sha1_ctx_mgr_flush_avx, sha1_ctx_mgr_flush_avx2
 125  %endif
 126 %endif
 127
 128 ;;;       func                  core, ver, snum
 129 slversion sha1_ctx_mgr_init,    00,   04,  0148
 130 slversion sha1_ctx_mgr_submit,  00,   04,  0149
 131 slversion sha1_ctx_mgr_flush,   00,   04,  0150