ceph/src/crypto/isa-l/isa-l_crypto/sha256_mb/sha256_mb_mgr_flush_avx512.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   2 ;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
   3 ;
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  28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29
  30 %include "sha256_job.asm"
  31 %include "sha256_mb_mgr_datastruct.asm"
  32 %include "reg_sizes.asm"
  33
  34 %ifdef HAVE_AS_KNOWS_AVX512
  35
  36 extern sha256_mb_x16_avx512
  37 default rel
  38
  39 %ifidn __OUTPUT_FORMAT__, elf64
  40 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  41 ; LINUX register definitions
  42 %define arg1    rdi ; rcx
  43 %define arg2    rsi ; rdx
  44
  45 %define tmp4    rdx
  46 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  47
  48 %else
  49
  50 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  51 ; WINDOWS register definitions
  52 %define arg1    rcx
  53 %define arg2    rdx
  54
  55 %define tmp4    rsi
  56 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  57 %endif
  58
  59 ; Common register definitions
  60
  61 %define state   arg1
  62 %define job     arg2
  63 %define len2    arg2
  64
  65 ; idx must be a register not clobberred by sha1_mult
  66 %define idx             r8
  67
  68 %define num_lanes_inuse r9
  69 %define unused_lanes    rbx
  70 %define lane_data       rbx
  71 %define tmp2            rbx
  72
  73 %define job_rax         rax
  74 %define tmp1            rax
  75 %define size_offset     rax
  76 %define tmp             rax
  77 %define start_offset    rax
  78
  79 %define tmp3            arg1
  80
  81 %define extra_blocks    arg2
  82 %define p               arg2
  83
  84
  85 ; STACK_SPACE needs to be an odd multiple of 8
  86 _XMM_SAVE_SIZE  equ 10*16
  87 _GPR_SAVE_SIZE  equ 8*8
  88 _ALIGN_SIZE     equ 8
  89
  90 _XMM_SAVE       equ 0
  91 _GPR_SAVE       equ _XMM_SAVE + _XMM_SAVE_SIZE
  92 STACK_SPACE     equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
  93
  94 %define APPEND(a,b) a %+ b
  95
  96 ; SHA256_JOB* sha256_mb_mgr_flush_avx512(SHA256_MB_JOB_MGR *state)
  97 ; arg 1 : rcx : state
  98 global sha256_mb_mgr_flush_avx512:function
  99 sha256_mb_mgr_flush_avx512:
 100         sub     rsp, STACK_SPACE
 101         mov     [rsp + _GPR_SAVE + 8*0], rbx
 102         mov     [rsp + _GPR_SAVE + 8*3], rbp
 103         mov     [rsp + _GPR_SAVE + 8*4], r12
 104         mov     [rsp + _GPR_SAVE + 8*5], r13
 105         mov     [rsp + _GPR_SAVE + 8*6], r14
 106         mov     [rsp + _GPR_SAVE + 8*7], r15
 107 %ifidn __OUTPUT_FORMAT__, win64
 108         mov     [rsp + _GPR_SAVE + 8*1], rsi
 109         mov     [rsp + _GPR_SAVE + 8*2], rdi
 110         vmovdqa  [rsp + _XMM_SAVE + 16*0], xmm6
 111         vmovdqa  [rsp + _XMM_SAVE + 16*1], xmm7
 112         vmovdqa  [rsp + _XMM_SAVE + 16*2], xmm8
 113         vmovdqa  [rsp + _XMM_SAVE + 16*3], xmm9
 114         vmovdqa  [rsp + _XMM_SAVE + 16*4], xmm10
 115         vmovdqa  [rsp + _XMM_SAVE + 16*5], xmm11
 116         vmovdqa  [rsp + _XMM_SAVE + 16*6], xmm12
 117         vmovdqa  [rsp + _XMM_SAVE + 16*7], xmm13
 118         vmovdqa  [rsp + _XMM_SAVE + 16*8], xmm14
 119         vmovdqa  [rsp + _XMM_SAVE + 16*9], xmm15
 120 %endif
 121
 122         mov     DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
 123         cmp     num_lanes_inuse, 0
 124         jz      return_null
 125
 126         ; find a lane with a non-null job
 127         xor     idx, idx
 128 %assign I 1
 129 %rep 15
 130         cmp     qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
 131         cmovne  idx, [APPEND(lane_,I)]
 132 %assign I (I+1)
 133 %endrep
 134
 135
 136         ; copy idx to empty lanes
 137 copy_lane_data:
 138         mov     tmp, [state + _args + _data_ptr + 8*idx]
 139
 140 %assign I 0
 141 %rep 16
 142         cmp     qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
 143         jne     APPEND(skip_,I)
 144         mov     [state + _args + _data_ptr + 8*I], tmp
 145         mov     dword [state + _lens + 4*I], 0xFFFFFFFF
 146 APPEND(skip_,I):
 147 %assign I (I+1)
 148 %endrep
 149
 150         ; Find min length
 151         vmovdqu ymm0, [state + _lens + 0*32]
 152         vmovdqu ymm1, [state + _lens + 1*32]
 153
 154         vpminud ymm2, ymm0, ymm1        ; ymm2 has {H1,G1,F1,E1,D1,C1,B1,A1}
 155         vpalignr ymm3, ymm3, ymm2, 8    ; ymm3 has {x,x,H1,G1,x,x,D1,C1}
 156         vpminud ymm2, ymm2, ymm3        ; ymm2 has {x,x,H2,G2,x,x,D2,C2}
 157         vpalignr ymm3, ymm3, ymm2, 4    ; ymm3 has {x,x, x,H2,x,x, x,D2}
 158         vpminud ymm2, ymm2, ymm3        ; ymm2 has {x,x, x,G3,x,x, x,C3}
 159         vperm2i128 ymm3, ymm2, ymm2, 1  ; ymm3 has {x,x, x, x,x,x, x,C3}
 160         vpminud ymm2, ymm2, ymm3        ; ymm2 has min value in low dword
 161
 162         vmovd   DWORD(idx), xmm2
 163         mov     len2, idx
 164         and     idx, 0xF
 165         shr     len2, 4
 166         jz      len_is_0
 167
 168         vpand   ymm2, ymm2, [rel clear_low_nibble]
 169         vpshufd ymm2, ymm2, 0
 170
 171         vpsubd  ymm0, ymm0, ymm2
 172         vpsubd  ymm1, ymm1, ymm2
 173
 174         vmovdqu [state + _lens + 0*32], ymm0
 175         vmovdqu [state + _lens + 1*32], ymm1
 176
 177         ; "state" and "args" are the same address, arg1
 178         ; len is arg2
 179         call    sha256_mb_x16_avx512
 180         ; state and idx are intact
 181
 182 len_is_0:
 183         ; process completed job "idx"
 184         imul    lane_data, idx, _LANE_DATA_size
 185         lea     lane_data, [state + _ldata + lane_data]
 186
 187         mov     job_rax, [lane_data + _job_in_lane]
 188         mov     qword [lane_data + _job_in_lane], 0
 189         mov     dword [job_rax + _status], STS_COMPLETED
 190         mov     unused_lanes, [state + _unused_lanes]
 191         shl     unused_lanes, 4
 192         or      unused_lanes, idx
 193         mov     [state + _unused_lanes], unused_lanes
 194
 195         mov     DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
 196         sub     num_lanes_inuse, 1
 197         mov     [state + _num_lanes_inuse], DWORD(num_lanes_inuse)
 198
 199         vmovd   xmm0, [state + _args_digest + 4*idx + 0*4*16]
 200         vpinsrd xmm0, [state + _args_digest + 4*idx + 1*4*16], 1
 201         vpinsrd xmm0, [state + _args_digest + 4*idx + 2*4*16], 2
 202         vpinsrd xmm0, [state + _args_digest + 4*idx + 3*4*16], 3
 203         vmovd   xmm1, [state + _args_digest + 4*idx + 4*4*16]
 204         vpinsrd xmm1, [state + _args_digest + 4*idx + 5*4*16], 1
 205         vpinsrd xmm1, [state + _args_digest + 4*idx + 6*4*16], 2
 206         vpinsrd xmm1, [state + _args_digest + 4*idx + 7*4*16], 3
 207
 208         vmovdqa [job_rax + _result_digest + 0*16], xmm0
 209         vmovdqa [job_rax + _result_digest + 1*16], xmm1
 210
 211 return:
 212 %ifidn __OUTPUT_FORMAT__, win64
 213         vmovdqa  xmm6, [rsp + _XMM_SAVE + 16*0]
 214         vmovdqa  xmm7, [rsp + _XMM_SAVE + 16*1]
 215         vmovdqa  xmm8, [rsp + _XMM_SAVE + 16*2]
 216         vmovdqa  xmm9, [rsp + _XMM_SAVE + 16*3]
 217         vmovdqa  xmm10, [rsp + _XMM_SAVE + 16*4]
 218         vmovdqa  xmm11, [rsp + _XMM_SAVE + 16*5]
 219         vmovdqa  xmm12, [rsp + _XMM_SAVE + 16*6]
 220         vmovdqa  xmm13, [rsp + _XMM_SAVE + 16*7]
 221         vmovdqa  xmm14, [rsp + _XMM_SAVE + 16*8]
 222         vmovdqa  xmm15, [rsp + _XMM_SAVE + 16*9]
 223         mov     rsi, [rsp + _GPR_SAVE + 8*1]
 224         mov     rdi, [rsp + _GPR_SAVE + 8*2]
 225 %endif
 226         mov     rbx, [rsp + _GPR_SAVE + 8*0]
 227         mov     rbp, [rsp + _GPR_SAVE + 8*3]
 228         mov     r12, [rsp + _GPR_SAVE + 8*4]
 229         mov     r13, [rsp + _GPR_SAVE + 8*5]
 230         mov     r14, [rsp + _GPR_SAVE + 8*6]
 231         mov     r15, [rsp + _GPR_SAVE + 8*7]
 232         add     rsp, STACK_SPACE
 233
 234         ret
 235
 236 return_null:
 237         xor     job_rax, job_rax
 238         jmp     return
 239
 240 section .data align=16
 241
 242 align 16
 243 clear_low_nibble:
 244         dq 0x00000000FFFFFFF0, 0x0000000000000000
 245         dq 0x00000000FFFFFFF0, 0x0000000000000000
 246 lane_1:     dq  1
 247 lane_2:     dq  2
 248 lane_3:     dq  3
 249 lane_4:     dq  4
 250 lane_5:     dq  5
 251 lane_6:     dq  6
 252 lane_7:     dq  7
 253 lane_8:     dq  8
 254 lane_9:     dq  9
 255 lane_10:    dq  10
 256 lane_11:    dq  11
 257 lane_12:    dq  12
 258 lane_13:    dq  13
 259 lane_14:    dq  14
 260 lane_15:    dq  15
 261
 262 %else
 263 %ifidn __OUTPUT_FORMAT__, win64
 264 global no_sha256_mb_mgr_flush_avx512
 265 no_sha256_mb_mgr_flush_avx512:
 266 %endif
 267 %endif ; HAVE_AS_KNOWS_AVX512