1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 ; Copyright(c) 2011-2017 Intel Corporation All rights reserved.
4 ; Redistribution and use in source and binary forms, with or without
5 ; modification, are permitted provided that the following conditions
7 ; * Redistributions of source code must retain the above copyright
8 ; notice, this list of conditions and the following disclaimer.
9 ; * Redistributions in binary form must reproduce the above copyright
10 ; notice, this list of conditions and the following disclaimer in
11 ; the documentation and/or other materials provided with the
13 ; * Neither the name of Intel Corporation nor the names of its
14 ; contributors may be used to endorse or promote products derived
15 ; from this software without specific prior written permission.
17 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 ; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 ; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 ; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 ; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 ; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 ; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 ; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
30 %include "sha256_job.asm"
31 %include "sha256_mb_mgr_datastruct.asm"
33 %include "reg_sizes.asm"
35 %ifdef HAVE_AS_KNOWS_SHANI
36 extern sha256_mb_x4_sse
43 %ifidn __OUTPUT_FORMAT__, elf64
44 ; LINUX register definitions
45 %define arg1 rdi ; rcx
46 %define arg2 rsi ; rdx
48 ; idx needs to be other than arg1, arg2, rbx, r12
51 ; WINDOWS register definitions
55 ; idx needs to be other than arg1, arg2, rbx, r12
64 %define unused_lanes rbx
70 %define size_offset rax
72 %define start_offset rax
76 %define extra_blocks arg2
87 ; STACK_SPACE needs to be an odd multiple of 8
88 _XMM_SAVE_SIZE equ 10*16
89 _GPR_SAVE_SIZE equ 8*3
93 _GPR_SAVE equ _XMM_SAVE + _XMM_SAVE_SIZE
94 STACK_SPACE equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE
96 %define APPEND(a,b) a %+ b
98 ; SHA256_JOB* sha256_mb_mgr_flush_sse_ni(SHA256_MB_JOB_MGR *state)
100 mk_global sha256_mb_mgr_flush_sse_ni, function
101 sha256_mb_mgr_flush_sse_ni:
105 mov [rsp + _GPR_SAVE + 8*0], rbx
106 mov [rsp + _GPR_SAVE + 8*1], r12
107 %ifidn __OUTPUT_FORMAT__, win64
108 mov [rsp + _GPR_SAVE + 8*2], rsi
109 movdqa [rsp + _XMM_SAVE + 16*0], xmm6
110 movdqa [rsp + _XMM_SAVE + 16*1], xmm7
111 movdqa [rsp + _XMM_SAVE + 16*2], xmm8
112 movdqa [rsp + _XMM_SAVE + 16*3], xmm9
113 movdqa [rsp + _XMM_SAVE + 16*4], xmm10
114 movdqa [rsp + _XMM_SAVE + 16*5], xmm11
115 movdqa [rsp + _XMM_SAVE + 16*6], xmm12
116 movdqa [rsp + _XMM_SAVE + 16*7], xmm13
117 movdqa [rsp + _XMM_SAVE + 16*8], xmm14
118 movdqa [rsp + _XMM_SAVE + 16*9], xmm15
121 ; use num_lanes_inuse to judge all lanes are empty
122 cmp dword [state + _num_lanes_inuse], 0
125 ; find a lane with a non-null job
127 cmp qword [state + _ldata + 1 * _LANE_DATA_size + _job_in_lane], 0
129 cmp qword [state + _ldata + 2 * _LANE_DATA_size + _job_in_lane], 0
131 cmp qword [state + _ldata + 3 * _LANE_DATA_size + _job_in_lane], 0
134 ; copy idx to empty lanes
136 mov tmp, [state + _args + _data_ptr + 8*idx]
140 cmp qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
142 mov [state + _args + _data_ptr + 8*I], tmp
143 mov dword [state + _lens + 4*I], 0xFFFFFFFF
149 mov DWORD(lens0), [state + _lens + 0*4]
151 mov DWORD(lens1), [state + _lens + 1*4]
154 mov DWORD(lens2), [state + _lens + 2*4]
157 mov DWORD(lens3), [state + _lens + 3*4]
165 ; compare with shani-sb threshold, if num_lanes_inuse <= threshold, using shani func
166 cmp dword [state + _num_lanes_inuse], SHA256_NI_SB_THRESHOLD_SSE
171 mov [state + _lens + idx*4], DWORD(idx)
173 or r10, 0x1000 ; sse has 4 lanes *4, r10b is idx, r10b2 is 16
174 ; "state" and "args" are the same address, arg1
175 ; len is arg2, idx and nlane in r10
177 ; state and idx are intact
187 mov [state + _lens + 0*4], DWORD(lens0)
188 mov [state + _lens + 1*4], DWORD(lens1)
189 mov [state + _lens + 2*4], DWORD(lens2)
190 mov [state + _lens + 3*4], DWORD(lens3)
192 ; "state" and "args" are the same address, arg1
194 call sha256_mb_x4_sse
195 ; state and idx are intact
198 ; process completed job "idx"
199 imul lane_data, idx, _LANE_DATA_size
200 lea lane_data, [state + _ldata + lane_data]
202 mov job_rax, [lane_data + _job_in_lane]
203 mov qword [lane_data + _job_in_lane], 0
204 mov dword [job_rax + _status], STS_COMPLETED
205 mov unused_lanes, [state + _unused_lanes]
208 mov [state + _unused_lanes], unused_lanes
210 sub dword [state + _num_lanes_inuse], 1
212 movd xmm0, [state + _args_digest + 4*idx + 0*16]
213 pinsrd xmm0, [state + _args_digest + 4*idx + 1*16], 1
214 pinsrd xmm0, [state + _args_digest + 4*idx + 2*16], 2
215 pinsrd xmm0, [state + _args_digest + 4*idx + 3*16], 3
216 movd xmm1, [state + _args_digest + 4*idx + 4*16]
217 pinsrd xmm1, [state + _args_digest + 4*idx + 5*16], 1
218 pinsrd xmm1, [state + _args_digest + 4*idx + 6*16], 2
219 pinsrd xmm1, [state + _args_digest + 4*idx + 7*16], 3
221 movdqa [job_rax + _result_digest + 0*16], xmm0
222 movdqa [job_rax + _result_digest + 1*16], xmm1
226 %ifidn __OUTPUT_FORMAT__, win64
227 movdqa xmm6, [rsp + _XMM_SAVE + 16*0]
228 movdqa xmm7, [rsp + _XMM_SAVE + 16*1]
229 movdqa xmm8, [rsp + _XMM_SAVE + 16*2]
230 movdqa xmm9, [rsp + _XMM_SAVE + 16*3]
231 movdqa xmm10, [rsp + _XMM_SAVE + 16*4]
232 movdqa xmm11, [rsp + _XMM_SAVE + 16*5]
233 movdqa xmm12, [rsp + _XMM_SAVE + 16*6]
234 movdqa xmm13, [rsp + _XMM_SAVE + 16*7]
235 movdqa xmm14, [rsp + _XMM_SAVE + 16*8]
236 movdqa xmm15, [rsp + _XMM_SAVE + 16*9]
237 mov rsi, [rsp + _GPR_SAVE + 8*2]
239 mov rbx, [rsp + _GPR_SAVE + 8*0]
240 mov r12, [rsp + _GPR_SAVE + 8*1]
249 section .data align=16
257 %ifidn __OUTPUT_FORMAT__, win64
258 global no_sha256_mb_mgr_flush_sse_ni
259 no_sha256_mb_mgr_flush_sse_ni:
261 %endif ; HAVE_AS_KNOWS_SHANI